Re: [PATCH] remoteproc: qcom: Introduce Hexagon V5 based WCSS driver

[Sricharan R]

Hi Bjorn,

On 6/7/2018 9:54 AM, Bjorn Andersson wrote:
> On Wed 06 Jun 21:11 PDT 2018, Vinod wrote:
> 
>> On 06-06-18, 09:17, Bjorn Andersson wrote:
>>> On Tue 05 Jun 05:56 PDT 2018, Sricharan R wrote:
>>>
>>>> Hi Vinod,
>>>>
>>>> On 6/5/2018 11:49 AM, Vinod wrote:
>>>>> On 05-06-18, 11:12, Sricharan R wrote:
>>>>>
>>>>>> +config QCOM_Q6V5_WCSS
>>>>>> +tristate "Qualcomm Hexagon based WCSS Peripheral Image Loader"
>>>>>> +depends on OF && ARCH_QCOM
>>>>>> +depends on QCOM_SMEM
>>>>>> +depends on RPMSG_QCOM_SMD || (COMPILE_TEST && RPMSG_QCOM_SMD=n)
>>>>>> +depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
>>>>>
>>>>> Is there a reason why it depends on RPMSG_QCOM_GLINK_SMEM=n? What would
>>>>> happen if distro wants both this and RPMSG_QCOM_GLINK_SMEM
>>>>>
>>>
>>> It says that QCOM_Q6V5_WCSS either must have a compatible state (i.e.
>>> builtin vs builtin, module vs builtin, but not builtin vs module) or
>>> that it's disabled, in which case we will hit the stub functions in
>>> qcom_glink.h.
>>>
>>> I.e. this prevents QCOM_Q6V5_WCSS to be compiled builtin when
>>> RPMSG_QCOM_GLINK_SMEM is module, as this would give us both stubs and
>>> the module.
>>
>> IIUC, you want to have QCOM_Q6V5_WCSS and RPMSG_QCOM_GLINK_SMEM as
>> modules or builtin
>>
> 
> RPMSG_QCOM_SMD, RPMSG_QCOM_GLINK_SMEM and QCOM_Q6V5_WCSS are all
> tristate.
> 
>> So, wouldn't Kconfig syntax something like where we say:
>> M if RPMSG_QCOM_GLINK_SMEM=m
>> bool if RPMSG_QCOM_GLINK_SMEM=y
>>
> 
> If we ignore SMD for a while we have the following combinations:
> 
> glink/wcss
> y y - valid
> y m - valid
> y n - valid
> m y - link failure (invalid)
> m m - valid
> m n - valid
> n y - valid (platform uses wcss, but not glink)
> n m - valid (-"-)
> n n - valid
> 
> So to distill this we have the two valid cases:
> module/no if RPMSG_QCOM_GLINK_SMEM=m
> yes/module/no if RPMSG_QCOM_GLINK_SMEM=y
> 
> and the way you express that in Kconfig is the somewhat awkward
> 
>   depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
> 

 ok, Having "depends on RPMSG_QCOM_GLINK_SMEM" takes care of the
 first 6 cases in the above list.

 But just was thinking that by allowing the last three combinations,
 there is a chance that some config that really needs GLINK_SMEM and WCSS,
 but selects only Q6V5_WCSS and misses to select GLINK_SMEM,
 would still built and make it non-functional, right ?

Regards,
 Sricharan

>> Which makes it clear that both these have to be same type?
>>
> 
> They don't have to be of the same type, only of a compatible type.
> 

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Re: [PATCH] remoteproc: qcom: Introduce Hexagon V5 based WCSS driver

[Sricharan R]

Hi Vinod,

On 6/6/2018 12:19 PM, Vinod wrote:
> Hi Sricharan,
> 
> On 06-06-18, 12:09, Sricharan R wrote:
> 
>>>>>> +config QCOM_Q6V5_WCSS
>>>>>> +tristate "Qualcomm Hexagon based WCSS Peripheral Image Loader"
>>>>>> +depends on OF && ARCH_QCOM
>>>>>> +depends on QCOM_SMEM
>>>>>> +depends on RPMSG_QCOM_SMD || (COMPILE_TEST && RPMSG_QCOM_SMD=n)
>>>>>> +depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
>>>>>
>>>>> Is there a reason why it depends on RPMSG_QCOM_GLINK_SMEM=n? What would
>>>>> happen if distro wants both this and RPMSG_QCOM_GLINK_SMEM
>>>>>
>>>>   RPMSG_QCOM_GLINK_SMEM=n should be for the COMPILE_TEST. Probably that
>>>
>>> why would that be a limitation? I am more worried about
>>> RPMSG_QCOM_GLINK_SMEM=n being the condition here. In new drivers we
>>> should not typically have dependency on some symbol being not there
>>
>> Without that, if RPMSG_QCOM_GLINK_SMEM=m is compiled as a module, then
>> it would break the build.
> 
> Okay I do not know the details, but that doesn't sound correct to me.
> Breaking build sounds a bit extreme to me. Can you give details on this
> part..
> 

 Having, just, depends on RPMSG_QCOM_GLINK_SMEM || COMPILE_TEST,
 is going to break when RPMSG_QCOM_GLINK_SMEM=m and COMPILE_TEST=y.
 Hence the COMPILE_TEST && RPMSG_QCOM_GLINK_SMEM=n.

 Having said that, COMPILE_TEST is getting tested for RPMSG_QCOM_SMD=n in
 the previous line. So that's the reason for not having it in below line for
 RPMSG_QCOM_GLINK_SMEM.

>>>>   means that it should be corrected here and for ADSP, Q6V5_PIL as well.
>>>>   Bjorn, is that correct ?, should it be, below ?
>>>>  
>>>>   depends on (RPMSG_QCOM_SMD || (COMPILE_TEST && RPMSG_QCOM_SMD=n)) || 
>>>> (RPMSG_QCOM_GLINK_SMEM || (COMPILE_TEST && RPMSG_QCOM_GLINK_SMEM=n))
>>>
>>> that doesnt really sound good :(
>>
>>  Hmm, but i was thinking it should functionally depend on either SMD or 
>> GLINK and not both.
> 
> If you are depedent upon a symbol provided by a module you should say
> depends on. If a machine is not supposed to have both SMD or GLINK then
> the driver will not get probed.
> 

This is where, i was thinking, it should be functional if either of SMD or GLINK
is there, but should not require both.

Regards,
 Sricharan

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Re: [PATCH] remoteproc: qcom: Introduce Hexagon V5 based WCSS driver

[Sricharan R]

Hi Vinod,

On 6/5/2018 10:10 PM, Vinod Koul wrote:
> On 05-06-18, 18:26, Sricharan R wrote:
>> Hi Vinod,
>>
>> On 6/5/2018 11:49 AM, Vinod wrote:
>>> On 05-06-18, 11:12, Sricharan R wrote:
>>>
>>>> +config QCOM_Q6V5_WCSS
>>>> +  tristate "Qualcomm Hexagon based WCSS Peripheral Image Loader"
>>>> +  depends on OF && ARCH_QCOM
>>>> +  depends on QCOM_SMEM
>>>> +  depends on RPMSG_QCOM_SMD || (COMPILE_TEST && RPMSG_QCOM_SMD=n)
>>>> +  depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
>>>
>>> Is there a reason why it depends on RPMSG_QCOM_GLINK_SMEM=n? What would
>>> happen if distro wants both this and RPMSG_QCOM_GLINK_SMEM
>>>
>>   RPMSG_QCOM_GLINK_SMEM=n should be for the COMPILE_TEST. Probably that
> 
> why would that be a limitation? I am more worried about
> RPMSG_QCOM_GLINK_SMEM=n being the condition here. In new drivers we
> should not typically have dependency on some symbol being not there
> 

Without that, if RPMSG_QCOM_GLINK_SMEM=m is compiled as a module, then
it would break the build.

>>   means that it should be corrected here and for ADSP, Q6V5_PIL as well.
>>   Bjorn, is that correct ?, should it be, below ?
>>  
>>   depends on (RPMSG_QCOM_SMD || (COMPILE_TEST && RPMSG_QCOM_SMD=n)) || 
>> (RPMSG_QCOM_GLINK_SMEM || (COMPILE_TEST && RPMSG_QCOM_GLINK_SMEM=n))
> 
> that doesnt really sound good :(
> 

 Hmm, but i was thinking it should functionally depend on either SMD or GLINK 
and not both.

Regards,
 Sricharan

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Re: [PATCH] remoteproc: qcom: Introduce Hexagon V5 based WCSS driver

[Sricharan R]

Hi Vinod,

On 6/5/2018 11:49 AM, Vinod wrote:
> On 05-06-18, 11:12, Sricharan R wrote:
> 
>> +config QCOM_Q6V5_WCSS
>> +tristate "Qualcomm Hexagon based WCSS Peripheral Image Loader"
>> +depends on OF && ARCH_QCOM
>> +depends on QCOM_SMEM
>> +depends on RPMSG_QCOM_SMD || (COMPILE_TEST && RPMSG_QCOM_SMD=n)
>> +depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
> 
> Is there a reason why it depends on RPMSG_QCOM_GLINK_SMEM=n? What would
> happen if distro wants both this and RPMSG_QCOM_GLINK_SMEM
> 
  RPMSG_QCOM_GLINK_SMEM=n should be for the COMPILE_TEST. Probably that
  means that it should be corrected here and for ADSP, Q6V5_PIL as well.
  Bjorn, is that correct ?, should it be, below ?
 
  depends on (RPMSG_QCOM_SMD || (COMPILE_TEST && RPMSG_QCOM_SMD=n)) || 
(RPMSG_QCOM_GLINK_SMEM || (COMPILE_TEST && RPMSG_QCOM_GLINK_SMEM=n))

>> +/* QDSP6SS Register Offsets */
>> +#define QDSP6SS_RESET_REG   0x014
>> +#define QDSP6SS_GFMUX_CTL_REG   0x020
>> +#define QDSP6SS_PWR_CTL_REG 0x030
>> +#define QDSP6SS_MEM_PWR_CTL 0x0B0
>> +
>> +/* AXI Halt Register Offsets */
>> +#define AXI_HALTREQ_REG 0x0
>> +#define AXI_HALTACK_REG 0x4
>> +#define AXI_IDLE_REG0x8
>> +
>> +#define HALT_ACK_TIMEOUT_MS 100
>> +
>> +/* QDSP6SS_RESET */
>> +#define Q6SS_STOP_CORE  BIT(0)
>> +#define Q6SS_CORE_ARES  BIT(1)
>> +#define Q6SS_BUS_ARES_ENABLEBIT(2)
> 
> Wouldn't it be nice if the defines are all consistent, some of them are
> QDSP6SS_xxx, some Q6SS_ some are not
> 
> Please do pick one and make it consistent :)
> 

 ok.

>> +/* QDSP6v56 parameters */
>> +#define QDSP6v56_LDO_BYPBIT(25)
>> +#define QDSP6v56_BHS_ON BIT(24)
>> +#define QDSP6v56_CLAMP_WL   BIT(21)
>> +#define QDSP6v56_CLAMP_QMC_MEM  BIT(22)
>> +#define HALT_CHECK_MAX_LOOPS200
>> +#define QDSP6SS_XO_CBCR 0x0038
> 
> GENMASK() perhaps?
> 

 ok.

>> +static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
>> +{
>> +int ret;
>> +u32 val;
>> +int i;
> 
> int ret, i;
> 
>> +static int q6v5_wcss_start(struct rproc *rproc)
>> +{
>> +struct q6v5_wcss *wcss = rproc->priv;
>> +int ret;
>> +
>> +qcom_q6v5_prepare(&wcss->q6v5);
>> +
>> +/* Release Q6 and WCSS reset */
>> +ret = reset_control_deassert(wcss->wcss_reset);
>> +if (ret) {
>> +dev_err(wcss->dev, "wcss_reset failed\n");
>> +return ret;
>> +}
>> +
>> +ret = reset_control_deassert(wcss->wcss_q6_reset);
>> +if (ret) {
>> +dev_err(wcss->dev, "wcss_q6_reset failed\n");
>> +goto wcss_reset;
>> +}
>> +
>> +/* Lithium configuration - clock gating and bus arbitration */
>> +ret = regmap_update_bits(wcss->halt_map,
>> + wcss->halt_nc + TCSR_GLOBAL_CFG0,
>> + 0x1F, 0x14);
> 
> magic numbers??
> 

 ok, will find out what it is for this one and below.
 But atleast from register map could not find out and
 these are sort of hardcoded sequences coming from the hw
 folks. So will have to reach out to them to find the specifics.

>> +static int q6v5_wcss_powerdown(struct q6v5_wcss *wcss)
>> +{
>> +int ret;
>> +u32 val;
>> +
>> +/* 1 - Assert WCSS/Q6 HALTREQ */
>> +q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_wcss);
>> +
>> +/* 2 - Enable WCSSAON_CONFIG */
>> +val = readl(wcss->rmb_base + SSCAON_CONFIG);
>> +val |= SSCAON_ENABLE;
>> +writel(val, wcss->rmb_base + SSCAON_CONFIG);
>> +
>> +/* 3 - Set SSCAON_CONFIG */
>> +val |= BIT(15);
>> +val &= ~BIT(16);
>> +val &= ~BIT(17);
>> +val &= ~BIT(18);
> 
> wouldn't it be nice to define these bits?
> 
>> +static int q6v5_q6_powerdown(struct q6v5_wcss *wcss)
>> +{
>> +int ret;
>> +u32 val;
>> +int i;
> 
> int ret, i;
> 

Regards,
 Sricharan

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[PATCH] remoteproc: qcom: Introduce Hexagon V5 based WCSS driver

[Sricharan R]

IPQ8074 has an integrated Hexagon dsp core q6v5 and a wireless lan
(Lithium) IP. An mdt type single image format is used for the
firmware. So the mdt_load function can be directly used to load
the firmware. Also add the relevant resets required for this core.

Acked-by: Rob Herring  (for bindings)
Signed-off-by: Sricharan R 
[bjorn: Rewrote as a separate driver, intead of extending q6v5_pil.c]
Signed-off-by: Bjorn Andersson 
---
 Fixed review comments from Vinod.
 Retained the reg read/update/write sequence instead of modify for
 readability
 In q6v5_wcss_powerdown SSCAON_CONFIG bits 16,17,18 documentation
 have to be updated.

 .../devicetree/bindings/remoteproc/qcom,q6v5.txt   |   7 +-
 drivers/remoteproc/Kconfig |  16 +
 drivers/remoteproc/Makefile|   1 +
 drivers/remoteproc/qcom_q6v5_wcss.c| 588 +
 4 files changed, 611 insertions(+), 1 deletion(-)
 create mode 100644 drivers/remoteproc/qcom_q6v5_wcss.c

diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt 
b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
index 00d3d58..d52d05e 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
@@ -11,6 +11,7 @@ on the Qualcomm Hexagon core.
"qcom,msm8916-mss-pil",
"qcom,msm8974-mss-pil"
"qcom,msm8996-mss-pil"
+   "qcom,ipq8074-wcss-pil"
 
 - reg:
Usage: required
@@ -49,11 +50,15 @@ on the Qualcomm Hexagon core.
Usage: required
Value type: 
Definition: reference to the reset-controller for the modem sub-system
+   reference to the list of 3 reset-controllers for the
+   wcss sub-system
 
 - reset-names:
Usage: required
Value type: 
-   Definition: must be "mss_restart"
+   Definition: must be "mss_restart" for the modem sub-system
+   Definition: must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
+   for the wcss syb-system
 
 - cx-supply:
 - mss-supply:
diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
index be76619..7b1a9ef 100644
--- a/drivers/remoteproc/Kconfig
+++ b/drivers/remoteproc/Kconfig
@@ -123,6 +123,22 @@ config QCOM_Q6V5_PIL
  Say y here to support the Qualcomm Peripherial Image Loader for the
  Hexagon V5 based remote processors.
 
+config QCOM_Q6V5_WCSS
+   tristate "Qualcomm Hexagon based WCSS Peripheral Image Loader"
+   depends on OF && ARCH_QCOM
+   depends on QCOM_SMEM
+   depends on RPMSG_QCOM_SMD || (COMPILE_TEST && RPMSG_QCOM_SMD=n)
+   depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
+   depends on QCOM_SYSMON || QCOM_SYSMON=n
+   select MFD_SYSCON
+   select QCOM_MDT_LOADER
+   select QCOM_Q6V5_COMMON
+   select QCOM_RPROC_COMMON
+   select QCOM_SCM
+   help
+ Say y here to support the Qualcomm Peripheral Image Loader for the
+ Hexagon V5 based WCSS remote processors.
+
 config QCOM_SYSMON
tristate "Qualcomm sysmon driver"
depends on RPMSG
diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
index 5dd0249..03332fa 100644
--- a/drivers/remoteproc/Makefile
+++ b/drivers/remoteproc/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_QCOM_ADSP_PIL)   += qcom_adsp_pil.o
 obj-$(CONFIG_QCOM_RPROC_COMMON)+= qcom_common.o
 obj-$(CONFIG_QCOM_Q6V5_COMMON) += qcom_q6v5.o
 obj-$(CONFIG_QCOM_Q6V5_PIL)+= qcom_q6v5_pil.o
+obj-$(CONFIG_QCOM_Q6V5_WCSS)   += qcom_q6v5_wcss.o
 obj-$(CONFIG_QCOM_SYSMON)  += qcom_sysmon.o
 obj-$(CONFIG_QCOM_WCNSS_PIL)   += qcom_wcnss_pil.o
 qcom_wcnss_pil-y   += qcom_wcnss.o
diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c 
b/drivers/remoteproc/qcom_q6v5_wcss.c
new file mode 100644
index 000..9c5b3b4
--- /dev/null
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -0,0 +1,588 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Linaro Ltd.
+ * Copyright (C) 2014 Sony Mobile Communications AB
+ * Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "qcom_common.h"
+#include "qcom_q6v5.h"
+
+#define WCSS_CRASH_REASON  421
+
+/* QDSP6SS Register Offsets */
+#define QDSP6SS_RESET_REG  0x014
+#define QDSP6SS_GFMUX_CTL_REG  0x020
+#define QDSP6SS_PWR_CTL_REG0x030
+#define QDSP6SS_MEM_PWR_CTL0x0B0
+
+/* AXI Halt Register Offsets */
+#define AXI_HALTREQ_REG0x0
+#define AXI_HALTACK_REG0x4
+#define A

Re: [RFC PATCH 2/5] remoteproc: q6v5: Extract common resource handling

[Sricharan R]

Hi Sibi,

On 6/1/2018 8:48 PM, Sibi S wrote:
> Hi Sricharan,
> 
> On 06/01/2018 11:46 AM, Sricharan R wrote:
>> Hi Bjorn,
>>    Thanks for this much needed consolidation.
>>
>> On 5/23/2018 10:50 AM, Bjorn Andersson wrote:
>>> Shared between all Hexagon V5 based remoteprocs is the handling of the 5
>>> interrupts and the SMP2P stop request, so break this out into a separate
>>> function in order to allow these drivers to be cleaned up.
>>>
>>> Signed-off-by: Bjorn Andersson 
>>> ---
>>>   drivers/remoteproc/Kconfig |   5 +
>>>   drivers/remoteproc/Makefile    |   1 +
>>>   drivers/remoteproc/qcom_q6v5.c | 243 +
>>>   drivers/remoteproc/qcom_q6v5.h |  46 +++
>>>   4 files changed, 295 insertions(+)
>>>   create mode 100644 drivers/remoteproc/qcom_q6v5.c
>>>   create mode 100644 drivers/remoteproc/qcom_q6v5.h
>>>
>>> diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
>>> index cd1c168fd188..63b79ea91a21 100644
>>> --- a/drivers/remoteproc/Kconfig
>>> +++ b/drivers/remoteproc/Kconfig
>>> @@ -102,6 +102,11 @@ config QCOM_ADSP_PIL
>>>   config QCOM_RPROC_COMMON
>>>   tristate
>>>   +config QCOM_Q6V5_COMMON
>>> +    tristate
>>> +    depends on ARCH_QCOM
>>> +    depends on QCOM_SMEM
>>> +
>>>   config QCOM_Q6V5_PIL
>>>   tristate "Qualcomm Hexagon V5 Peripherial Image Loader"
>>>   depends on OF && ARCH_QCOM
>>> diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
>>> index 02627ede8d4a..5dd0249cf76a 100644
>>> --- a/drivers/remoteproc/Makefile
>>> +++ b/drivers/remoteproc/Makefile
>>> @@ -16,6 +16,7 @@ obj-$(CONFIG_DA8XX_REMOTEPROC)    += 
>>> da8xx_remoteproc.o
>>>   obj-$(CONFIG_KEYSTONE_REMOTEPROC)    += keystone_remoteproc.o
>>>   obj-$(CONFIG_QCOM_ADSP_PIL)    += qcom_adsp_pil.o
>>>   obj-$(CONFIG_QCOM_RPROC_COMMON)    += qcom_common.o
>>> +obj-$(CONFIG_QCOM_Q6V5_COMMON)    += qcom_q6v5.o
>>>   obj-$(CONFIG_QCOM_Q6V5_PIL)    += qcom_q6v5_pil.o
>>>   obj-$(CONFIG_QCOM_SYSMON)    += qcom_sysmon.o
>>>   obj-$(CONFIG_QCOM_WCNSS_PIL)    += qcom_wcnss_pil.o
>>> diff --git a/drivers/remoteproc/qcom_q6v5.c b/drivers/remoteproc/qcom_q6v5.c
>>> new file mode 100644
>>> index ..9076537a1671
>>> --- /dev/null
>>> +++ b/drivers/remoteproc/qcom_q6v5.c
>>> @@ -0,0 +1,243 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * Qualcomm Peripheral Image Loader for Q6V5 WCSS
>>> + *
>>
>>    Probably just Q6V5, QCSS not needed.
>>
>>> + * Copyright (C) 2016-2018 Linaro Ltd.
>>> + * Copyright (C) 2014 Sony Mobile Communications AB
>>> + * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
>>> + */
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include "qcom_q6v5.h"
>>> +
>>> +/**
>>> + * qcom_q6v5_prepare() - reinitialize the qcom_q6v5 context before start
>>> + * @q6v5:    reference to qcom_q6v5 context to be reinitialized
>>> + *
>>> + * Return: 0 on success, negative errno on failure
>>> + */
>>> +int qcom_q6v5_prepare(struct qcom_q6v5 *q6v5)
>>> +{
>>> +    reinit_completion(&q6v5->start_done);
>>> +    reinit_completion(&q6v5->stop_done);
>>> +
>>> +    q6v5->running = true;
>>> +    q6v5->handover_issued = false;
>>> +
>>> +    enable_irq(q6v5->handover_irq);
>>> +
>>> +    return 0;
>>> +}
>>> +
>>> +/**
>>> + * qcom_q6v5_unprepare() - unprepare the qcom_q6v5 context after stop
>>> + * @q6v5:    reference to qcom_q6v5 context to be unprepared
>>> + *
>>> + * Return: 0 on success, 1 if handover hasn't yet been called
>>> + */
>>> +int qcom_q6v5_unprepare(struct qcom_q6v5 *q6v5)
>>> +{
>>> +    disable_irq(q6v5->handover_irq);
>>> +
>>> +    return !q6v5->handover_issued;
>>> +}
>>> +
>>> +static irqreturn_t q6v5_wdog_interrupt(int irq, void *data)
>>> +{
>>> +    struct qcom_q6v5 *q6v5 = data;
>>> +    size_t len;
>>> +    char *msg;
>>> +
>>> +    /* Sometimes the stop triggers a watchdog rathe

Re: [PATCH v9 01/15] ARM: Add Krait L2 register accessor functions

[Sricharan R]

Hi Stephen,

On 5/31/2018 1:11 PM, Stephen Boyd wrote:
> Quoting Sricharan R (2018-05-30 21:57:20)
>> Hi Stephen,
>>
>> On 5/30/2018 9:25 PM, Stephen Boyd wrote:
>>> Quoting Sricharan R (2018-05-24 22:40:11)
>>>> Hi Bjorn,
>>>>
>>>> On 5/24/2018 11:09 PM, Bjorn Andersson wrote:
>>>>> On Tue 06 Mar 06:38 PST 2018, Sricharan R wrote:
>>>>>
>>>>>> From: Stephen Boyd 
>>>>>>
>>>>>> Krait CPUs have a handful of L2 cache controller registers that
>>>>>> live behind a cp15 based indirection register. First you program
>>>>>> the indirection register (l2cpselr) to point the L2 'window'
>>>>>> register (l2cpdr) at what you want to read/write.  Then you
>>>>>> read/write the 'window' register to do what you want. The
>>>>>> l2cpselr register is not banked per-cpu so we must lock around
>>>>>> accesses to it to prevent other CPUs from re-pointing l2cpdr
>>>>>> underneath us.
>>>>>>
>>>>>> Cc: Mark Rutland 
>>>>>> Cc: Russell King 
>>>>>> Signed-off-by: Stephen Boyd 
>>>>>
>>>>> This should have your signed-off-by here as well.
>>>>>
>>>>
>>>>  ok.
>>>>
>>>>> Apart from that:
>>>>>
>>>>> Acked-by: Bjorn Andersson 
>>>>>
>>>>
>>>
>>> Will these patches come around again? I'll do a quick sweep on them
>>> today but I expect them to be resent.
>>
>> Sure, i will have to resend them again, fixing couple of Bjorn's
>> minor comments. Will address your comments that you would give
>> as well along with that.
>>
> 
> Ok. One general comment is that it would be nice if the bindings for all
> the nodes that are introduced included 'clocks' properties and also
> maybe 'clock-names' properties for the clocks that are consumed by each
> node. Right now, we hide those details from DT and rely on the string
> names to hook the clk tree up for us. That sort of prevents us from
> moving away from string easily, so I would just throw the clocks into
> the binding right now and always have them there just in case we want to
> use the binding to figure out the hierarchy in the future.
> 

 ok, understand that mostly. So will try to revamp those patches with
 the 'clocks' property in the binding added, reading them in the driver
 from DT.

> I've been thinking we need to do something similar for the gcc and other
> nodes for any clks they use, but I haven't gotten around to it.
> 
> Otherwise the patches look mostly ok to me. Not sure I'll have any other
> comments.
> 

 Thanks, will respin.

Regards,
 Sricharan

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Re: [RFC PATCH 4/5] remoteproc: qcom: q6v5-pil: Use common q6v5 helpers

[Sricharan R]

Hi Bjorn,

On 5/23/2018 10:50 AM, Bjorn Andersson wrote:
> Migrate the MSS remoteproc driver to use the newly extracted helper
> functions.
> 
> Signed-off-by: Bjorn Andersson 
> ---
>  drivers/remoteproc/Kconfig |   4 +
>  drivers/remoteproc/qcom_q6v5_pil.c | 157 +++--
>  2 files changed, 19 insertions(+), 142 deletions(-)
> 
> diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
> index d51d155cf8bd..2316908e9788 100644
> --- a/drivers/remoteproc/Kconfig
> +++ b/drivers/remoteproc/Kconfig
> @@ -116,6 +116,10 @@ config QCOM_Q6V5_PIL
>   depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
>   depends on QCOM_SYSMON || QCOM_SYSMON=n
>   select MFD_SYSCON
> + select QCOM_Q6V5_COMMON

 The below three are duplicate.

> + select QCOM_RPROC_COMMON
> + select QCOM_SCM
> + select QCOM_Q6V5_COMMON
>   select QCOM_RPROC_COMMON
>   select QCOM_SCM

<..>

> @@ -946,16 +934,10 @@ static int q6v5_stop(struct rproc *rproc)
>  
>   qproc->running = false;
>  
> - qcom_smem_state_update_bits(qproc->state,
> - BIT(qproc->stop_bit), BIT(qproc->stop_bit));
> -
> - ret = wait_for_completion_timeout(&qproc->stop_done,
> -   msecs_to_jiffies(5000));
> - if (ret == 0)
> + ret = qcom_q6v5_request_stop(&qproc->q6v5);
> + if (ret == -ETIMEDOUT)
>   dev_err(qproc->dev, "timed out on wait\n");
>  
> - qcom_smem_state_update_bits(qproc->state, BIT(qproc->stop_bit), 0);
> -
>   q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
>   q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
>   q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
> @@ -976,9 +958,8 @@ static int q6v5_stop(struct rproc *rproc)
>  
>   q6v5_reset_assert(qproc);
>  
> - disable_irq(qproc->handover_irq);
> -
> - if (!qproc->proxy_unvoted) {
> + ret = qcom_q6v5_unprepare(&qproc->q6v5);
> + if (ret) {
>   q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
>qproc->proxy_clk_count);
>   q6v5_regulator_disable(qproc, qproc->proxy_regs,

 Nit, can qcom_msa_handover api be used instead here ?

 Rest all looks good,
reviewed-by: Sricharan R 

Regards,
 Sricharan

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Re: [RFC PATCH 3/5] remoteproc: qcom: adsp: Use common q6v5 helpers

[Sricharan R]

c, RPROC_WATCHDOG);
> -
> - return IRQ_HANDLED;
> -}
> -
> -static irqreturn_t adsp_fatal_interrupt(int irq, void *dev)
> -{
> - struct qcom_adsp *adsp = dev;
> - size_t len;
> - char *msg;
> -
> - msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, adsp->crash_reason_smem, &len);
> - if (!IS_ERR(msg) && len > 0 && msg[0])
> - dev_err(adsp->dev, "fatal error received: %s\n", msg);
> -
> - rproc_report_crash(adsp->rproc, RPROC_FATAL_ERROR);
> -
> - return IRQ_HANDLED;
> -}
> -
> -static irqreturn_t adsp_ready_interrupt(int irq, void *dev)
> -{
> - return IRQ_HANDLED;
> -}
> -
> -static irqreturn_t adsp_handover_interrupt(int irq, void *dev)
> -{
> - struct qcom_adsp *adsp = dev;
> -
> - complete(&adsp->start_done);
> -
> - return IRQ_HANDLED;
> -}
> -
> -static irqreturn_t adsp_stop_ack_interrupt(int irq, void *dev)
> -{
> - struct qcom_adsp *adsp = dev;
> -
> - complete(&adsp->stop_done);
> -
> - return IRQ_HANDLED;
> -}
> -
>  static int adsp_init_clock(struct qcom_adsp *adsp)
>  {
>   int ret;
> @@ -272,29 +225,6 @@ static int adsp_init_regulator(struct qcom_adsp *adsp)
>   return PTR_ERR_OR_ZERO(adsp->px_supply);
>  }
>  
> -static int adsp_request_irq(struct qcom_adsp *adsp,
> -  struct platform_device *pdev,
> -  const char *name,
> -  irq_handler_t thread_fn)
> -{
> - int ret;
> -
> - ret = platform_get_irq_byname(pdev, name);
> - if (ret < 0) {
> - dev_err(&pdev->dev, "no %s IRQ defined\n", name);
> - return ret;
> - }
> -
> - ret = devm_request_threaded_irq(&pdev->dev, ret,
> - NULL, thread_fn,
> - IRQF_ONESHOT,
> - "adsp", adsp);
> - if (ret)
> - dev_err(&pdev->dev, "request %s IRQ failed\n", name);
> -
> - return ret;
> -}
> -
>  static int adsp_alloc_memory_region(struct qcom_adsp *adsp)
>  {
>   struct device_node *node;
> @@ -348,13 +278,9 @@ static int adsp_probe(struct platform_device *pdev)
>   adsp->dev = &pdev->dev;
>   adsp->rproc = rproc;
>   adsp->pas_id = desc->pas_id;
> - adsp->crash_reason_smem = desc->crash_reason_smem;
>   adsp->has_aggre2_clk = desc->has_aggre2_clk;
>   platform_set_drvdata(pdev, adsp);
>  
> - init_completion(&adsp->start_done);
> - init_completion(&adsp->stop_done);
> -
>   ret = adsp_alloc_memory_region(adsp);
>   if (ret)
>   goto free_rproc;
> @@ -367,37 +293,10 @@ static int adsp_probe(struct platform_device *pdev)
>   if (ret)
>   goto free_rproc;
>  
> - ret = adsp_request_irq(adsp, pdev, "wdog", adsp_wdog_interrupt);
> - if (ret < 0)
> - goto free_rproc;
> - adsp->wdog_irq = ret;
> -
> - ret = adsp_request_irq(adsp, pdev, "fatal", adsp_fatal_interrupt);
> - if (ret < 0)
> - goto free_rproc;
> - adsp->fatal_irq = ret;
> -
> - ret = adsp_request_irq(adsp, pdev, "ready", adsp_ready_interrupt);
> - if (ret < 0)
> - goto free_rproc;
> - adsp->ready_irq = ret;
> -
> -     ret = adsp_request_irq(adsp, pdev, "handover", adsp_handover_interrupt);
> - if (ret < 0)
> - goto free_rproc;
> - adsp->handover_irq = ret;
> -
> - ret = adsp_request_irq(adsp, pdev, "stop-ack", adsp_stop_ack_interrupt);
> - if (ret < 0)
> - goto free_rproc;
> - adsp->stop_ack_irq = ret;
> -
> - adsp->state = qcom_smem_state_get(&pdev->dev, "stop",
> -   &adsp->stop_bit);
> - if (IS_ERR(adsp->state)) {
> - ret = PTR_ERR(adsp->state);
> + ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem,
> +  qcom_pas_handover);
> + if (ret)
>   goto free_rproc;
> - }
>  
>   qcom_add_glink_subdev(rproc, &adsp->glink_subdev);
>   qcom_add_smd_subdev(rproc, &adsp->smd_subdev);
> @@ -422,7 +321,6 @@ static int adsp_remove(struct platform_device *pdev)
>  {
>   struct qcom_adsp *adsp = platform_get_drvdata(pdev);
>  
> - qcom_smem_state_put(adsp->state);

 Is this change required ?

  Otherwise,
   reviewed-by: Sricharan R 

Regards,
 Sricharan

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Re: [RFC PATCH 2/5] remoteproc: q6v5: Extract common resource handling

[Sricharan R]

}
> +
> + q6v5->ready_irq = platform_get_irq_byname(pdev, "ready");
> + ret = devm_request_threaded_irq(&pdev->dev, q6v5->ready_irq,
> + NULL, q6v5_ready_interrupt,
> + IRQF_TRIGGER_RISING | IRQF_ONESHOT,
> + "q6v5 ready", q6v5);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to acquire ready IRQ\n");
> + return ret;
> + }
> +
> + q6v5->handover_irq = platform_get_irq_byname(pdev, "handover");
> + ret = devm_request_threaded_irq(&pdev->dev, q6v5->handover_irq,
> + NULL, q6v5_handover_interrupt,
> + IRQF_TRIGGER_RISING | IRQF_ONESHOT,
> + "q6v5 handover", q6v5);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to acquire handover IRQ\n");
> + return ret;
> + }
> + disable_irq(q6v5->handover_irq);
> +
> + q6v5->stop_irq = platform_get_irq_byname(pdev, "stop-ack");
> + ret = devm_request_threaded_irq(&pdev->dev, q6v5->stop_irq,
> + NULL, q6v5_stop_interrupt,
> + IRQF_TRIGGER_RISING | IRQF_ONESHOT,
> + "q6v5 stop", q6v5);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to acquire stop-ack IRQ\n");
> + return ret;
> + }
> +
> + q6v5->state = qcom_smem_state_get(&pdev->dev, "stop", &q6v5->stop_bit);
> + if (IS_ERR(q6v5->state)) {
> + dev_err(&pdev->dev, "failed to acquire stop state\n");
> + return PTR_ERR(q6v5->state);
> + }
> +
> + return 0;
> +}
> diff --git a/drivers/remoteproc/qcom_q6v5.h b/drivers/remoteproc/qcom_q6v5.h
> new file mode 100644
> index ..7ac92c1e0f49
> --- /dev/null
> +++ b/drivers/remoteproc/qcom_q6v5.h
> @@ -0,0 +1,46 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +
> +#ifndef __QCOM_Q6V5_H__
> +#define __QCOM_Q6V5_H__
> +
> +#include 
> +#include 
> +
> +struct rproc;
> +struct qcom_smem_state;
> +
> +struct qcom_q6v5 {
> + struct device *dev;
> + struct rproc *rproc;
> +
> + struct qcom_smem_state *state;
> + unsigned stop_bit;
> +
> + int wdog_irq;
> + int fatal_irq;
> + int ready_irq;
> + int handover_irq;
> + int stop_irq;
> +
> + bool handover_issued;
> +
> + struct completion start_done;
> + struct completion stop_done;
> +
> + int crash_reason;
> +
> + bool running;
> +
> + void (*handover)(struct qcom_q6v5 *q6v5);
> +};
> +
> +int qcom_q6v5_init(struct qcom_q6v5 *q6v5, struct platform_device *pdev,
> +struct rproc *rproc, int crash_reason,
> +void (*handover)(struct qcom_q6v5 *q6v5));
> +
> +int qcom_q6v5_prepare(struct qcom_q6v5 *q6v5);
> +int qcom_q6v5_unprepare(struct qcom_q6v5 *q6v5);
> +int qcom_q6v5_request_stop(struct qcom_q6v5 *q6v5);
> +int qcom_q6v5_wait_for_start(struct qcom_q6v5 *q6v5, int timeout);
> +
> +#endif
> 

Regards,
 Sricharan

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Re: [PATCH v9 01/15] ARM: Add Krait L2 register accessor functions

[Sricharan R]

Hi Stephen,

On 5/30/2018 9:25 PM, Stephen Boyd wrote:
> Quoting Sricharan R (2018-05-24 22:40:11)
>> Hi Bjorn,
>>
>> On 5/24/2018 11:09 PM, Bjorn Andersson wrote:
>>> On Tue 06 Mar 06:38 PST 2018, Sricharan R wrote:
>>>
>>>> From: Stephen Boyd 
>>>>
>>>> Krait CPUs have a handful of L2 cache controller registers that
>>>> live behind a cp15 based indirection register. First you program
>>>> the indirection register (l2cpselr) to point the L2 'window'
>>>> register (l2cpdr) at what you want to read/write.  Then you
>>>> read/write the 'window' register to do what you want. The
>>>> l2cpselr register is not banked per-cpu so we must lock around
>>>> accesses to it to prevent other CPUs from re-pointing l2cpdr
>>>> underneath us.
>>>>
>>>> Cc: Mark Rutland 
>>>> Cc: Russell King 
>>>> Signed-off-by: Stephen Boyd 
>>>
>>> This should have your signed-off-by here as well.
>>>
>>
>>  ok.
>>
>>> Apart from that:
>>>
>>> Acked-by: Bjorn Andersson 
>>>
>>
> 
> Will these patches come around again? I'll do a quick sweep on them
> today but I expect them to be resent.

Sure, i will have to resend them again, fixing couple of Bjorn's
minor comments. Will address your comments that you would give
as well along with that.

Regards,
 Sricharan

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Re: [RFC PATCH 5/5] remoteproc: qcom: Introduce Hexagon V5 based WCSS driver

[Sricharan R]

Hi Bjorn,

On 5/29/2018 9:37 AM, Bjorn Andersson wrote:
> On Wed 23 May 07:48 PDT 2018, Sricharan R wrote:
>> On 5/23/2018 1:07 PM, Vinod wrote:
>>> On 22-05-18, 23:58, Bjorn Andersson wrote:
>>>> On Tue 22 May 23:05 PDT 2018, Vinod wrote:
>>>>> On 22-05-18, 22:20, Bjorn Andersson wrote:
> [..]
>>>>> Looking at the patch, few other comments would be applicable too, so 
>>>>> would be
>>>>> great if you/Sricharan can update this
>>>>>
>>>>
>>>> I agree, the primary purpose of this patch was rather to get feedback on
>>>> the structure of the drivers, I do expect this to take another round
>>>> through the editor to get some polishing touches. Sorry if this wasn't
>>>> clear from the description.
>>>
>>> Since Sricharan replied to comments, I though they would be fixed. Yeah 
>>> this is
>>> fine from RFC..
>>>
>>
>>  Thanks for this.
>>
>>  Tested this on ipq8074 and wcss rproc is up with this.
>>
>>  Tested-by: Sricharan R 
>>
> 
> Thanks Sricharan!
> 
>>  So regarding the cleanup, as i see, this consolidates the code much better.
>>
>>  so about the point of avoiding duplication for soc specific functions like
>>  qcv5_wcss_reset common between qcv5_wcss and qcv5_pil drivers as done in my
>>  series, with a second thought that feels it might be difficult to maintain
>>  in the longer run. Since the sequences are specific to each soc and for now
>>  although some part of it is common, for a minor update in one soc, common
>>  code needs to reworked every time and tested on all boards that share them.
>>
>>  So feels like having the duplication for hw init sequences is the cleaner 
>> way.
>>
> 
> Sounds good, then let's go with this approach!
> 
>>  Apart from that for other comments on the q6v5 wcss driver, i can address 
>> them
>>  on this final patch that you have posted and same can be included in your
>>  next version. Please let me know how you want to go about it.
>>
> 
> If you can help me review the first 4 patches and fix up and resend the
> 5th that would be greatly appreciated.

 Sure, will do.

Regards,
 Sricharan

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[PATCH v8 11/12] ARM: dts: ipq8074: Add pcie nodes

[Sricharan R]

The driver/phy support for ipq8074 is available now.
So enabling the nodes in DT.

Reviewed-by: Abhishek Sahu 
Acked-by: Bjorn Andersson 
Signed-off-by: Sricharan R 
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 157 +-
 1 file changed, 156 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi 
b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index bd58ab4..1822698 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -24,7 +24,7 @@
ranges = <0 0 0 0x>;
compatible = "simple-bus";
 
-   pinctrl@100 {
+   tlmm: pinctrl@100 {
compatible = "qcom,ipq8074-pinctrl";
reg = <0x100 0x30>;
interrupts = ;
@@ -278,6 +278,161 @@
pinctrl-names = "default";
status = "disabled";
};
+
+   pcie_phy0: phy@86000 {
+   compatible = "qcom,ipq8074-qmp-pcie-phy";
+   reg = <0x86000 0x1000>;
+   #phy-cells = <0>;
+   clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
+   clock-names = "pipe_clk";
+   clock-output-names = "pcie20_phy0_pipe_clk";
+
+   resets = <&gcc GCC_PCIE0_PHY_BCR>,
+   <&gcc GCC_PCIE0PHY_PHY_BCR>;
+   reset-names = "phy",
+ "common";
+   status = "disabled";
+   };
+
+   pcie0: pci@2000 {
+   compatible = "qcom,pcie-ipq8074";
+   reg =  <0x2000 0xf1d
+   0x2f20 0xa8
+   0x8 0x2000
+   0x2010 0x1000>;
+   reg-names = "dbi", "elbi", "parf", "config";
+   device_type = "pci";
+   linux,pci-domain = <0>;
+   bus-range = <0x00 0xff>;
+   num-lanes = <1>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+
+   phys = <&pcie_phy0>;
+   phy-names = "pciephy";
+
+   ranges = <0x8100 0 0x2020 0x2020
+ 0 0x10   /* downstream I/O */
+ 0x8200 0 0x2030 0x2030
+ 0 0xd0>; /* non-prefetchable memory */
+
+   interrupts = ;
+   interrupt-names = "msi";
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0x7>;
+   interrupt-map = <0 0 0 1 &intc 0 75
+IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+   <0 0 0 2 &intc 0 78
+IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+   <0 0 0 3 &intc 0 79
+IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+   <0 0 0 4 &intc 0 83
+IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+   clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
+<&gcc GCC_PCIE0_AXI_M_CLK>,
+<&gcc GCC_PCIE0_AXI_S_CLK>,
+<&gcc GCC_PCIE0_AHB_CLK>,
+<&gcc GCC_PCIE0_AUX_CLK>;
+
+   clock-names = "iface",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "aux";
+   resets = <&gcc GCC_PCIE0_PIPE_ARES>,
+<&gcc GCC_PCIE0_SLEEP_ARES>,
+<&gcc GCC_PCIE0_CORE_STICKY_ARES>,
+<&gcc GCC_PCIE0_AXI_MASTER_ARES>,
+<&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
+<&gcc GCC_PCIE0_AHB_ARES>,
+<&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
+   reset-names = "pipe",
+   

[PATCH v8 08/12] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file

[Sricharan R]

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 64 +
 2 files changed, 65 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index c6cabec..596cce3 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -762,6 +762,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c3.dtb \
+   qcom-ipq4019-ap.dk07.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
new file mode 100644
index 000..8c7ef65
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk07.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C1";
+   compatible = "qcom,ipq4019-ap-dk07.1-c1";
+
+   soc {
+   pci@4000 {
+   status = "ok";
+   perst-gpio = <&tlmm 38 0x1>;
+   };
+
+   spi@78b6000 {
+   status = "ok";
+   };
+
+   pinctrl@100 {
+   serial_1_pins: serial1-pinmux {
+   pins = "gpio8", "gpio9",
+   "gpio10", "gpio11";
+   function = "blsp_uart1";
+   bias-disable;
+   };
+
+   spi_0_pins: spi-0-pinmux {
+   pinmux {
+   function = "blsp_spi0";
+   pins = "gpio13", "gpio14", "gpio15";
+   bias-disable;
+   };
+   pinmux_cs {
+   function = "gpio";
+   pins = "gpio12";
+   bias-disable;
+   output-high;
+   };
+   };
+   };
+
+   serial@78b {
+   pinctrl-0 = <&serial_1_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   spi@78b5000 {
+   pinctrl-0 = <&spi_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   cs-gpios = <&tlmm 12 0>;
+
+   m25p80@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   reg = <0>;
+   compatible = "n25q128a11";
+   spi-max-frequency = <2400>;
+   };
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v8 12/12] ARM: dts: ipq8074: Enable few peripherals for hk01 board

[Sricharan R]

Reviewed-by: Abhishek Sahu 
Acked-by: Bjorn Andersson 
Signed-off-by: Sricharan R 
---
 arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 54 +++
 1 file changed, 54 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts 
b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
index 72c5b4a3..c13ddee 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -21,6 +21,7 @@
 
aliases {
serial0 = &blsp1_uart5;
+   serial1 = &blsp1_uart3;
};
 
chosen {
@@ -36,5 +37,58 @@
serial@78b3000 {
status = "ok";
};
+
+   spi@78b5000 {
+   status = "ok";
+
+   m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <5000>;
+   };
+   };
+
+   serial@78b1000 {
+status = "ok";
+   };
+
+   i2c@78b6000 {
+status = "ok";
+   };
+
+   dma@7984000 {
+status = "ok";
+   };
+
+   nand@79b {
+   status = "ok";
+
+   nand@0 {
+   reg = <0>;
+   nand-ecc-strength = <4>;
+   nand-ecc-step-size = <512>;
+   nand-bus-width = <8>;
+   };
+   };
+
+   phy@86000 {
+   status = "ok";
+   };
+
+   phy@8e000 {
+   status = "ok";
+   };
+
+   pci@2000 {
+   status = "ok";
+   perst-gpio = <&tlmm 58 0x1>;
+   };
+
+   pci@1000 {
+   status = "ok";
+   perst-gpio = <&tlmm 61 0x1>;
+   };
};
 };
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v8 09/12] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file

[Sricharan R]

Reviewed-by: Abhishek Sahu 
Acked-by: Bjorn Andersson 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 25 +
 2 files changed, 26 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 596cce3..02b7f1d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -763,6 +763,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq4019-ap.dk07.1-c1.dtb \
+   qcom-ipq4019-ap.dk07.1-c2.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
new file mode 100644
index 000..af7a902
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk07.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C2";
+   compatible = "qcom,ipq4019-ap-dk07.1-c2";
+
+   soc {
+   pinctrl@100 {
+   serial_1_pins: serial1-pinmux {
+   pins = "gpio8", "gpio9";
+   function = "blsp_uart1";
+   bias-disable;
+   };
+   };
+
+   serial@78b {
+   pinctrl-0 = <&serial_1_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v8 10/12] ARM: dts: ipq8074: Add peripheral nodes

[Sricharan R]

Add serial, i2c, bam, spi, qpic peripheral nodes.

While here, fix the PMU node's irq trigger to avoid
the boot warnings from GIC.

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm64/boot/dts/qcom/ipq8074-hk01.dts |  12 ---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 156 +-
 2 files changed, 155 insertions(+), 13 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts 
b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
index 6a838b5..72c5b4a3 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -33,19 +33,7 @@
};
 
soc {
-   pinctrl@100 {
-   serial_4_pins: serial4_pinmux {
-   mux {
-   pins = "gpio23", "gpio24";
-   function = "blsp4_uart1";
-   bias-disable;
-   };
-   };
-   };
-
serial@78b3000 {
-   pinctrl-0 = <&serial_4_pins>;
-   pinctrl-names = "default";
status = "ok";
};
};
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi 
b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 2bc5dec..bd58ab4 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -32,6 +32,45 @@
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
+
+   serial_4_pins: serial4-pinmux {
+   pins = "gpio23", "gpio24";
+   function = "blsp4_uart1";
+   drive-strength = <8>;
+   bias-disable;
+   };
+
+   i2c_0_pins: i2c-0-pinmux {
+   pins = "gpio42", "gpio43";
+   function = "blsp1_i2c";
+   drive-strength = <8>;
+   bias-disable;
+   };
+
+   spi_0_pins: spi-0-pins {
+   pins = "gpio38", "gpio39", "gpio40", "gpio41";
+   function = "blsp0_spi";
+   drive-strength = <8>;
+   bias-disable;
+   };
+
+   hsuart_pins: hsuart-pins {
+   pins = "gpio46", "gpio47", "gpio48", "gpio49";
+   function = "blsp2_uart";
+   drive-strength = <8>;
+   bias-disable;
+   };
+
+   qpic_pins: qpic-pins {
+   pins = "gpio1", "gpio3", "gpio4",
+  "gpio5", "gpio6", "gpio7",
+  "gpio8", "gpio10", "gpio11",
+  "gpio12", "gpio13", "gpio14",
+  "gpio15", "gpio16", "gpio17";
+   function = "qpic";
+   drive-strength = <8>;
+   bias-disable;
+   };
};
 
intc: interrupt-controller@b00 {
@@ -122,6 +161,121 @@
clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
 <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+   pinctrl-0 = <&serial_4_pins>;
+   pinctrl-names = "default";
+   status = "disabled";
+   };
+
+   blsp_dma: dma@7884000 {
+   compatible = "qcom,bam-v1.7.0";
+   reg = <0x7884000 0x2b000>;
+   interrupts = ;
+   clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+   clock-names = "bam_clk";
+   #dma-cells = <1>;
+   qcom,ee = <0>;
+   };
+
+   blsp1_uart1: serial@78af000 {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x78af000 0x

[PATCH v8 05/12] ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file

[Sricharan R]

Reviewed-by: Abhishek Sahu 
Tested-by: Varadarajan Narayanan 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 19 +++
 2 files changed, 20 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7e24249..4e15d0d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -760,6 +760,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-ifc6540.dtb \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
+   qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
new file mode 100644
index 000..7a96f30
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C1";
+   compatible = "qcom,ipq4019-dk04.1-c1";
+
+   soc {
+   dma@7984000 {
+   status = "ok";
+   };
+
+   qpic-nand@79b {
+   status = "ok";
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v8 06/12] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file

[Sricharan R]

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/Makefile  | 1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 9 +
 2 files changed, 10 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4e15d0d..c6cabec 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -761,6 +761,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
+   qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
new file mode 100644
index 000..2d1c4c6
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C3";
+   compatible = "qcom,ipq4019-ap-dk04.1-c3";
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v8 07/12] ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data

[Sricharan R]

Add the common data for all dk07 based boards.

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 75 +++
 1 file changed, 75 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
new file mode 100644
index 000..9f1a5a66
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019.dtsi"
+#include 
+#include 
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1";
+
+   memory {
+   device_type = "memory";
+   reg = <0x8000 0x2000>; /* 512MB */
+   };
+
+   aliases {
+   serial0 = &blsp1_uart1;
+   serial1 = &blsp1_uart2;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   soc {
+   pinctrl@100 {
+   serial_0_pins: serial0-pinmux {
+   pins = "gpio16", "gpio17";
+   function = "blsp_uart0";
+   bias-disable;
+   };
+
+   i2c_0_pins: i2c-0-pinmux {
+   pins = "gpio20", "gpio21";
+   function = "blsp_i2c0";
+   bias-disable;
+   };
+
+   nand_pins: nand-pins {
+   pins = "gpio53", "gpio55", "gpio56",
+  "gpio57", "gpio58", "gpio59",
+  "gpio60", "gpio62", "gpio63",
+  "gpio64", "gpio65", "gpio66",
+  "gpio67", "gpio68", "gpio69";
+   function = "qpic";
+};
+   };
+
+   serial@78af000 {
+   pinctrl-0 = <&serial_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   dma@7884000 {
+   status = "ok";
+   };
+
+   i2c@78b7000 { /* BLSP1 QUP2 */
+   pinctrl-0 = <&i2c_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   dma@7984000 {
+   status = "ok";
+   };
+
+   qpic-nand@79b {
+   pinctrl-0 = <&nand_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v8 04/12] ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi

[Sricharan R]

Add the common parts for the dk04 boards.

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 111 ++
 arch/arm/boot/dts/qcom-ipq4019.dtsi   |   2 +-
 2 files changed, 112 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
new file mode 100644
index 000..7c1eb19
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019.dtsi"
+#include 
+#include 
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
+
+   aliases {
+   serial0 = &blsp1_uart1;
+   serial1 = &blsp1_uart2;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   memory {
+   device_type = "memory";
+   reg = <0x8000 0x1000>; /* 256MB */
+   };
+
+   soc {
+   pinctrl@100 {
+   serial_0_pins: serial0-pinmux {
+   pins = "gpio16", "gpio17";
+   function = "blsp_uart0";
+   bias-disable;
+   };
+
+   serial_1_pins: serial1-pinmux {
+   pins = "gpio8", "gpio9",
+   "gpio10", "gpio11";
+   function = "blsp_uart1";
+   bias-disable;
+   };
+
+   spi_0_pins: spi-0-pinmux {
+   pinmux {
+   function = "blsp_spi0";
+   pins = "gpio13", "gpio14", "gpio15";
+   bias-disable;
+   };
+   pinmux_cs {
+   function = "gpio";
+   pins = "gpio12";
+   bias-disable;
+   output-high;
+   };
+   };
+
+   i2c_0_pins: i2c-0-pinmux {
+   pins = "gpio20", "gpio21";
+   function = "blsp_i2c0";
+   bias-disable;
+   };
+
+   nand_pins: nand-pins {
+   pins = "gpio53", "gpio55", "gpio56",
+   "gpio57", "gpio58", "gpio59",
+   "gpio60", "gpio62", "gpio63",
+   "gpio64", "gpio65", "gpio66",
+   "gpio67", "gpio68", "gpio69";
+   function = "qpic";
+   };
+   };
+
+   serial@78af000 {
+   pinctrl-0 = <&serial_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   serial@78b {
+   pinctrl-0 = <&serial_1_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   dma@7884000 {
+   status = "ok";
+   };
+
+   spi@78b5000 { /* BLSP1 QUP1 */
+   pinctrl-0 = <&spi_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   cs-gpios = <&tlmm 12 0>;
+
+   m25p80@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   reg = <0>;
+   compatible = "n25q128a11";
+   spi-max-frequency = <2400>;
+   };
+   };
+
+   pci@4000 {
+   status = "ok";
+   perst-gpio = <&tlmm 38 0x1>;
+   };
+
+   qpic-nand@79b {
+   pinctrl-0 

[PATCH v8 03/12] ARM: dts: ipq4019: Change the max opp frequency

[Sricharan R]

The max opp frequency is 716MHZ. So update that.

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 737097e..ad61a55 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -63,7 +63,7 @@
48000   110
20  110
50  110
-   666000  110
+   716000  110
>;
clock-latency = <256000>;
};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v8 01/12] ARM: dts: ipq4019: Add a default chosen node

[Sricharan R]

Add a 'chosen' node to select the serial console.
This is needed when bootloaders do not pass the
'console=' bootargs.

Acked-by: Bjorn Andersson 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 8 
 arch/arm/boot/dts/qcom-ipq4019.dtsi   | 2 +-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index e413b21e..ef8d8c8 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -20,6 +20,14 @@
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
compatible = "qcom,ipq4019";
 
+   aliases {
+   serial0 = &blsp1_uart1;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
soc {
rng@22000 {
status = "ok";
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index b25daf3..2efc8a2 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -272,7 +272,7 @@
 regulator;
 };
 
-   serial@78af000 {
+   blsp1_uart1: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
interrupts = <0 107 0>;
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v8 02/12] ARM: dts: ipq4019: Add a few peripheral nodes

[Sricharan R]

Now with the driver updates for some peripherals being there,
add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
peripheral support.

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi |   2 +-
 arch/arm/boot/dts/qcom-ipq4019.dtsi   | 156 --
 2 files changed, 146 insertions(+), 12 deletions(-)

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index ef8d8c8..418f9a0 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -69,7 +69,7 @@
status = "ok";
};
 
-   spi_0: spi@78b5000 {
+   spi@78b5000 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "ok";
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 2efc8a2..737097e 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -40,8 +40,10 @@
};
 
aliases {
-   spi0 = &spi_0;
-   i2c0 = &i2c_0;
+   spi0 = &blsp1_spi1;
+   spi1 = &blsp1_spi2;
+   i2c0 = &blsp1_i2c3;
+   i2c1 = &blsp1_i2c4;
};
 
cpus {
@@ -120,6 +122,12 @@
};
};
 
+   firmware {
+   scm {
+   compatible = "qcom,scm-ipq4019";
+   };
+   };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <1 2 0xf08>,
@@ -165,13 +173,13 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
-   interrupts = <0 208 0>;
+   interrupts = ;
};
 
blsp_dma: dma@7884000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07884000 0x23000>;
-   interrupts = ;
+   interrupts = ;
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
@@ -179,7 +187,7 @@
status = "disabled";
};
 
-   spi_0: spi@78b5000 {
+   blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x78b5000 0x600>;
interrupts = ;
@@ -188,10 +196,26 @@
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
+   dmas = <&blsp_dma 5>, <&blsp_dma 4>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
+
+   blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
+   compatible = "qcom,spi-qup-v2.2.1";
+   reg = <0x78b6000 0x600>;
+   interrupts = ;
+   clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
+   <&gcc GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   dmas = <&blsp_dma 7>, <&blsp_dma 6>;
+   dma-names = "rx", "tx";
status = "disabled";
};
 
-   i2c_0: i2c@78b7000 {
+   blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b7000 0x600>;
interrupts = ;
@@ -200,14 +224,29 @@
clock-names = "iface", "core";
#address-cells = <1>;
#size-cells = <0>;
+   dmas = <&blsp_dma 9>, <&blsp_dma 8>;
+   dma-names = "rx", "tx";
status = "disabled";
};
 
+   blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
+   compatible = "qcom,i2c-qup-v2.2.1";
+   reg = <0x78b8000 0x600>;
+   interrupts = ;
+   clocks = <&

[PATCH v8 00/12] ARM: dts: ipq: updates to enable a few peripherals

[Sricharan R]

All the patches have been tested on ipq4019 dk01, 04, 07 and ipq8074 hk01
boards for spi, bam, qup, qpic, spi-nor, serial, pci.

[V8]
* Rebased on top of Andy's for-next
[V7]
* Fixed Kbuild git bisectability issue

[V6]
* Fixed Bjorn's comments, added his acks that he gave, added Varada's acks
* Rebased on top of Andy's for-next branch.

[v5]
* Fixed a minor comment that i missed earlier.
* https://www.spinics.net/lists/arm-kernel/msg643071.html

[v4]
* Fixed more comments.
* Dropped reserved-memory nodes from board files as
  that might break existing users whose u-boot do not
  specify the fdt_high accordingly.
* Added chosen serial node for all boards to have
  the default serial console specified from DT.

[v3]
* Fixed minor comments from v2,
  https://www.spinics.net/lists/arm-kernel/msg641480.html

* Added Abhishek's review tags

[v2]
* Addressed all comments from Abhishek
* Removed dk01-c2 and dk04-c5 spinand based boards
  as support for spinand is not complete
* Based all patches on top of Andy's for-next branch

[V1]
* https://www.spinics.net/lists/arm-kernel/msg631318.html

Sricharan R (12):
  ARM: dts: ipq4019: Add a default chosen node
  ARM: dts: ipq4019: Add a few peripheral nodes
  ARM: dts: ipq4019: Change the max opp frequency
  ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi
  ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file
  ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file
  ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data
  ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file
  ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file
  ARM: dts: ipq8074: Add peripheral nodes
  ARM: dts: ipq8074: Add pcie nodes
  ARM: dts: ipq8074: Enable few peripherals for hk01 board

 arch/arm/boot/dts/Makefile  |   4 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi   |  10 +-
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts |  19 ++
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts |   9 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi   | 111 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts |  64 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts |  25 ++
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi   |  75 ++
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 162 ++--
 arch/arm64/boot/dts/qcom/ipq8074-hk01.dts   |  62 -
 arch/arm64/boot/dts/qcom/ipq8074.dtsi   | 313 +++-
 11 files changed, 827 insertions(+), 27 deletions(-)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi

-- 
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Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v9 01/15] ARM: Add Krait L2 register accessor functions

[Sricharan R]

Hi Bjorn,

On 5/24/2018 11:09 PM, Bjorn Andersson wrote:
> On Tue 06 Mar 06:38 PST 2018, Sricharan R wrote:
> 
>> From: Stephen Boyd 
>>
>> Krait CPUs have a handful of L2 cache controller registers that
>> live behind a cp15 based indirection register. First you program
>> the indirection register (l2cpselr) to point the L2 'window'
>> register (l2cpdr) at what you want to read/write.  Then you
>> read/write the 'window' register to do what you want. The
>> l2cpselr register is not banked per-cpu so we must lock around
>> accesses to it to prevent other CPUs from re-pointing l2cpdr
>> underneath us.
>>
>> Cc: Mark Rutland 
>> Cc: Russell King 
>> Signed-off-by: Stephen Boyd 
> 
> This should have your signed-off-by here as well.
> 

 ok.

> Apart from that:
> 
> Acked-by: Bjorn Andersson 
> 

 Thanks.

Regards,
 Sricharan


> Regards,
> Bjorn
> 
>> ---
>>  arch/arm/common/Kconfig   |  3 ++
>>  arch/arm/common/Makefile  |  1 +
>>  arch/arm/common/krait-l2-accessors.c  | 48 
>> +++
>>  arch/arm/include/asm/krait-l2-accessors.h | 10 +++
>>  4 files changed, 62 insertions(+)
>>  create mode 100644 arch/arm/common/krait-l2-accessors.c
>>  create mode 100644 arch/arm/include/asm/krait-l2-accessors.h
>>
>> diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
>> index e5ad070..c8e1986 100644
>> --- a/arch/arm/common/Kconfig
>> +++ b/arch/arm/common/Kconfig
>> @@ -7,6 +7,9 @@ config DMABOUNCE
>>  bool
>>  select ZONE_DMA
>>  
>> +config KRAIT_L2_ACCESSORS
>> +bool
>> +
>>  config SHARP_LOCOMO
>>  bool
>>  
>> diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
>> index 70b4a14..eec6cd1 100644
>> --- a/arch/arm/common/Makefile
>> +++ b/arch/arm/common/Makefile
>> @@ -7,6 +7,7 @@ obj-y+= firmware.o
>>  
>>  obj-$(CONFIG_SA)+= sa.o
>>  obj-$(CONFIG_DMABOUNCE) += dmabounce.o
>> +obj-$(CONFIG_KRAIT_L2_ACCESSORS) += krait-l2-accessors.o
>>  obj-$(CONFIG_SHARP_LOCOMO)  += locomo.o
>>  obj-$(CONFIG_SHARP_PARAM)   += sharpsl_param.o
>>  obj-$(CONFIG_SHARP_SCOOP)   += scoop.o
>> diff --git a/arch/arm/common/krait-l2-accessors.c 
>> b/arch/arm/common/krait-l2-accessors.c
>> new file mode 100644
>> index 000..9a97dda
>> --- /dev/null
>> +++ b/arch/arm/common/krait-l2-accessors.c
>> @@ -0,0 +1,48 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +// Copyright (c) 2018, The Linux Foundation. All rights reserved.
>> +
>> +#include 
>> +#include 
>> +
>> +#include 
>> +#include 
>> +
>> +static DEFINE_RAW_SPINLOCK(krait_l2_lock);
>> +
>> +void krait_set_l2_indirect_reg(u32 addr, u32 val)
>> +{
>> +unsigned long flags;
>> +
>> +raw_spin_lock_irqsave(&krait_l2_lock, flags);
>> +/*
>> + * Select the L2 window by poking l2cpselr, then write to the window
>> + * via l2cpdr.
>> + */
>> +asm volatile ("mcr p15, 3, %0, c15, c0, 6 @ l2cpselr" : : "r" (addr));
>> +isb();
>> +asm volatile ("mcr p15, 3, %0, c15, c0, 7 @ l2cpdr" : : "r" (val));
>> +isb();
>> +
>> +raw_spin_unlock_irqrestore(&krait_l2_lock, flags);
>> +}
>> +EXPORT_SYMBOL(krait_set_l2_indirect_reg);
>> +
>> +u32 krait_get_l2_indirect_reg(u32 addr)
>> +{
>> +u32 val;
>> +unsigned long flags;
>> +
>> +raw_spin_lock_irqsave(&krait_l2_lock, flags);
>> +/*
>> + * Select the L2 window by poking l2cpselr, then read from the window
>> + * via l2cpdr.
>> + */
>> +asm volatile ("mcr p15, 3, %0, c15, c0, 6 @ l2cpselr" : : "r" (addr));
>> +isb();
>> +asm volatile ("mrc p15, 3, %0, c15, c0, 7 @ l2cpdr" : "=r" (val));
>> +
>> +raw_spin_unlock_irqrestore(&krait_l2_lock, flags);
>> +
>> +return val;
>> +}
>> +EXPORT_SYMBOL(krait_get_l2_indirect_reg);
>> diff --git a/arch/arm/include/asm/krait-l2-accessors.h 
>> b/arch/arm/include/asm/krait-l2-accessors.h
>> new file mode 100644
>> index 000..dd7c474
>> --- /dev/null
>> +++ b/arch/arm/include/asm/krait-l2-accessors.h
>> @@ -0,0 +1,10 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +// Copyright (c) 2018, The Linux Foundation. All rights reserved.
>> +
>> +#ifndef __ASMARM_KRAIT_L2_ACCESSORS_H
>> +#define __ASMARM_KRAIT_L2_ACCESSORS_H
>> +
>> +extern void krait_set_l2_indirect_reg(u32 addr, u32 val);
>> +extern u32 krait_get_l2_indirect_reg(u32 addr);
>> +
>> +#endif
>> -- 
>> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
>> Code Aurora Forum, hosted by The Linux Foundation
>>

-- 
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Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v9 02/15] clk: mux: Split out register accessors for reuse

[Sricharan R]

Hi Bjorn,

On 5/24/2018 10:20 PM, Bjorn Andersson wrote:
> On Tue 06 Mar 06:38 PST 2018, Sricharan R wrote:
> 
>> From: Stephen Boyd 
>>
>> We want to reuse the logic in clk-mux.c for other clock drivers
>> that don't use readl as register accessors. Fortunately, there
>> really isn't much to the mux code besides the table indirection
>> and quirk flags if you assume any bit shifting and masking has
>> been done already. Pull that logic out into reusable functions
>> that operate on an optional table and some flags so that other
>> drivers can use the same logic.
>>
>> [Sricharan: Rebased for mainline]
>> Signed-off-by: Sricharan R 
>> Signed-off-by: Stephen Boyd 
> 
> This should read as a log, where the first entry is Stephen stating that
> he acquired or wrote the code and can release it according to the
> license requirements. Then you state that you acquired it, changed it
> and are releasing it according to the license requirements.
> 

 ok, will fix this to make it more clear.

> 
> PS. Please expand your last name.
> 

 ok. Just that, all my previous patches has so far gone like this :-)

Regards,
 Sricharan

> Regards,
> Bjorn
> 
>> ---
>>  drivers/clk/clk-mux.c | 74 
>> +++
>>  drivers/clk/nxp/clk-lpc32xx.c | 21 +++-
>>  include/linux/clk-provider.h  |  6 
>>  3 files changed, 57 insertions(+), 44 deletions(-)
>>
>> diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
>> index 39cabe1..28223fa 100644
>> --- a/drivers/clk/clk-mux.c
>> +++ b/drivers/clk/clk-mux.c
>> @@ -26,35 +26,25 @@
>>   * parent - parent is adjustable through clk_set_parent
>>   */
>>  
>> -static u8 clk_mux_get_parent(struct clk_hw *hw)
>> +unsigned int clk_mux_get_parent(struct clk_hw *hw, unsigned int val,
>> +unsigned int *table,
>> +unsigned long flags)
>>  {
>> -struct clk_mux *mux = to_clk_mux(hw);
>>  int num_parents = clk_hw_get_num_parents(hw);
>> -u32 val;
>> -
>> -/*
>> - * FIXME need a mux-specific flag to determine if val is bitwise or 
>> numeric
>> - * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
>> - * to 0x7 (index starts at one)
>> - * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
>> - * val = 0x4 really means "bit 2, index starts at bit 0"
>> - */
>> -val = clk_readl(mux->reg) >> mux->shift;
>> -val &= mux->mask;
>>  
>> -if (mux->table) {
>> +if (table) {
>>  int i;
>>  
>>  for (i = 0; i < num_parents; i++)
>> -if (mux->table[i] == val)
>> +if (table[i] == val)
>>  return i;
>>  return -EINVAL;
>>  }
>>  
>> -if (val && (mux->flags & CLK_MUX_INDEX_BIT))
>> +if (val && (flags & CLK_MUX_INDEX_BIT))
>>  val = ffs(val) - 1;
>>  
>> -if (val && (mux->flags & CLK_MUX_INDEX_ONE))
>> +if (val && (flags & CLK_MUX_INDEX_ONE))
>>  val--;
>>  
>>  if (val >= num_parents)
>> @@ -62,23 +52,53 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)
>>  
>>  return val;
>>  }
>> +EXPORT_SYMBOL_GPL(clk_mux_get_parent);
>>  
>> -static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
>> +static u8 _clk_mux_get_parent(struct clk_hw *hw)
>>  {
>>  struct clk_mux *mux = to_clk_mux(hw);
>>  u32 val;
>> -unsigned long flags = 0;
>>  
>> -if (mux->table) {
>> -index = mux->table[index];
>> +/*
>> + * FIXME need a mux-specific flag to determine if val is bitwise or
>> + * numeric e.g. sys_clkin_ck's clksel field is 3 bits wide,
>> + * but ranges from 0x1 to 0x7 (index starts at one)
>> + * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
>> + * val = 0x4 really means "bit 2, index starts at bit 0"
>> + */
>> +val = clk_readl(mux->reg) >> mux->shift;
>> +val &= mux->mask;
>> +
>> +return clk_mux_get_parent(hw, val, mux->table, mux->flags);
>> +}
>> +
>> +unsigned int clk_mux_reindex(u8 index, unsigned int *table,
>> + unsigned long flags)
>> +{
>> +unsi

Re: [RFC PATCH 5/5] remoteproc: qcom: Introduce Hexagon V5 based WCSS driver

[Sricharan R]

Hi Bjorn,

On 5/23/2018 1:07 PM, Vinod wrote:
> On 22-05-18, 23:58, Bjorn Andersson wrote:
>> On Tue 22 May 23:05 PDT 2018, Vinod wrote:
>>
>>> On 22-05-18, 22:20, Bjorn Andersson wrote:
>>>
>>>> +static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
>>>> +{
>>>> +  int ret;
>>>> +  u32 val;
>>>> +  int i;
>>>> +
>>>> +  /* Assert resets, stop core */
>>>> +  val = readl(wcss->reg_base + QDSP6SS_RESET_REG);
>>>> +  val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
>>>> +  writel(val, wcss->reg_base + QDSP6SS_RESET_REG);
>>>> +
>>>> +  /* BHS require xo cbcr to be enabled */
>>>> +  val = readl(wcss->reg_base + QDSP6SS_XO_CBCR);
>>>> +  val |= 0x1;
>>>> +  writel(val, wcss->reg_base + QDSP6SS_XO_CBCR);
>>>
>>> As commented on previous patch, it would help IMO to add a modify() wrapper
>>> here which would perform read, modify and write.
>>>
>>
>> Iirc the code ended up like this because a lot of these operations ended
>> up being line wrapped and harder to read using some modify(reg, mask,
>> val) helper. That said, the function isn't very pretty in it's current
>> state either...
> 
> Agreed :) and i thought modify make help it make better
> 
>> One of the parts of the RFC is that this sequence is a verbatim copy
>> from the qcom_q6v5_pil.c driver for 8996, so if we find this duplication
>> suitable I would prefer that we keep them the same.
>>
>>
>> The alternative to duplicating this function is as Sricharan proposed to
>> have the qcom_q6v5_pil.c be both a driver for both the single-stage
>> remoteproc and the two-stage (load boot loader, then modem firmware).
>>
>>> Looking at the patch, few other comments would be applicable too, so would 
>>> be
>>> great if you/Sricharan can update this
>>>
>>
>> I agree, the primary purpose of this patch was rather to get feedback on
>> the structure of the drivers, I do expect this to take another round
>> through the editor to get some polishing touches. Sorry if this wasn't
>> clear from the description.
> 
> Since Sricharan replied to comments, I though they would be fixed. Yeah this 
> is
> fine from RFC..
> 

 Thanks for this.

 Tested this on ipq8074 and wcss rproc is up with this.

 Tested-by: Sricharan R 

 So regarding the cleanup, as i see, this consolidates the code much better.

 so about the point of avoiding duplication for soc specific functions like
 qcv5_wcss_reset common between qcv5_wcss and qcv5_pil drivers as done in my
 series, with a second thought that feels it might be difficult to maintain
 in the longer run. Since the sequences are specific to each soc and for now
 although some part of it is common, for a minor update in one soc, common
 code needs to reworked every time and tested on all boards that share them.

 So feels like having the duplication for hw init sequences is the cleaner way.

 Apart from that for other comments on the q6v5 wcss driver, i can address them
 on this final patch that you have posted and same can be included in your
 next version. Please let me know how you want to go about it.

Regards,
 Sricharan

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Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH V6 5/5] remoteproc: qcom: Add q6v5-wcss rproc ops

[Sricharan R]

Hi,

On 5/18/2018 5:59 PM, Vinod wrote:
> On 14-05-18, 16:16, Sricharan R wrote:
> 
>> +static int q6v5_wcss_start(struct rproc *rproc)
>> +{
>> +struct q6v5 *qproc = rproc->priv;
>> +int ret = 0;
> 
> Superfluous initialization
> 

 ok.

>> +
>> +ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
>> +  qproc->active_clk_count);
>> +if (ret) {
>> +dev_err(qproc->dev, "failed to enable clocks\n");
>> +return ret;
>> +}
>> +
>> +/* Release Q6 and WCSS reset */
>> +ret = reset_control_deassert(qproc->wcss_reset);
>> +if (ret)
>> +dev_err(qproc->dev, "wcss_reset failed\n");
>> +
>> +ret = reset_control_deassert(qproc->wcss_q6_reset);
>> +if (ret)
>> +dev_err(qproc->dev, "wcss_q6_reset failed\n");
> 
> shouldn't we abort on these two errors?
> 

 ha right. will fix it.

>> +
>> +/* Lithium configuration - clock gating and bus arbitration */
>> +ret = regmap_update_bits(qproc->halt_map,
>> + qproc->halt_nc + TCSR_GLOBAL_CFG0,
>> + 0x1F, 0x14);
>> +if (ret)
>> +return ret;
>> +
>> +ret = regmap_update_bits(qproc->halt_map,
>> + qproc->halt_nc + TCSR_GLOBAL_CFG1,
>> + 1, 0);
>> +if (ret)
>> +return ret;
>> +
>> +/* Write bootaddr to EVB so that Q6WCSS will jump there after reset */
>> +writel(rproc->bootaddr >> 4, qproc->reg_base + QDSP6SS_RST_EVB);
>> +
>> +ret = q6v5_reset(qproc);
>> +if (ret)
>> +return ret;
> 
> all these returns, aren't we leaving device in some dangling state?
> 

 hmm ok. clocks and resets have to be reverted. will add error handling here.

>> +static int q6v5_wcss_powerdown(struct q6v5 *qproc)
>> +{
>> +unsigned int val = 0;
> 
> superfluous initialization
> 
 ok.

>> +int ret;
>> +
>> +/* 1 - Assert WCSS/Q6 HALTREQ */
>> +q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
>> +
>> +/* 2 - Enable WCSSAON_CONFIG */
>> +val = readl(qproc->rmb_base + SSCAON_CONFIG);
>> +val |= SSCAON_ENABLE;
>> +writel(val, qproc->rmb_base + SSCAON_CONFIG);
>> +
>> +/* 3 - Set SSCAON_CONFIG */
>> +val |= BIT(15);
>> +val &= ~BIT(16);
>> +val &= ~BIT(17);
>> +val &= ~BIT(18);
> 
> shouldn't bit 15 thru 18 be defined on what they mean?
> 

 hmm, ok. would define them.

>> +static int q6v5_q6_powerdown(struct q6v5 *qproc)
>> +{
>> +int i = 0, ret;
>> +unsigned int val = 0;
>> +
>> +/* 1 - Halt Q6 bus interface */
>> +q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
>> +
>> +/* 2 - Disable Q6 Core clock */
>> +val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
>> +val &= ~Q6SS_CLK_ENABLE;
>> +writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
>> +
>> +/* 3 - Clamp I/O */
>> +val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
>> +val |= Q6SS_CLAMP_IO;
>> +writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
>> +
>> +/* 4 - Clamp WL */
>> +val |= QDSS_BHS_ON;
>> +writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
>> +
>> +/* 5 - Clear Erase standby */
>> +val &= ~Q6SS_L2DATA_STBY_N;
>> +writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
>> +
>> +/* 6 - Clear Sleep RTN */
>> +val &= ~Q6SS_SLP_RET_N;
>> +writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
>> +
>> +/* 7 - turn off QDSP6 memory foot/head switch one bank at a time */
>> +for (i = 0; i < 20; i++) {
>> +val = readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL);
>> +val &= ~BIT(i);
>> +writel(val, qproc->reg_base + QDSP6SS_MEM_PWR_CTL);
>> +mdelay(1);
>> +}
>> +/* 8 - Assert QMC memory RTN */
>> +val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
>> +val |= QDSP6v56_CLAMP_QMC_MEM;
>> +writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
>> +
>> +/* 9 - Turn off BHS */
>> +val &= ~QDSP6v56_BHS_ON;
>> +writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
>> +udelay(

Re: [PATCH V6 3/5] remoteproc: qcom: Split the head and tail of the q5v5-pil rproc reset function

[Sricharan R]

Hi Vinod,

Thanks for the review.

On 5/18/2018 5:52 PM, Vinod wrote:
> On 14-05-18, 16:16, Sricharan R wrote:
> 
>> +static int q6v5_reset(struct q6v5 *qproc)
>> +{
>> +u32 ret;
>> +int val, i;
>> +
>> +/* Assert resets, stop core */
>> +val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
>> +val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
>> +writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
>> +
>> +/* BHS require xo cbcr to be enabled */
>> +val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
>> +val |= 0x1;
>> +writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
> 
> consider adding a updatel macro which does read, update and write for you...
> 

 ok.

>> +
>> +/* Read CLKOFF bit to go low indicating CLK is enabled */
>> +ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
>> + val, !(val & BIT(31)), 1,
>> + HALT_CHECK_MAX_LOOPS);
>> +if (ret) {
>> +dev_err(qproc->dev,
>> +"xo cbcr enabling timed out (rc:%d)\n", ret);
>> +return ret;
>> +}
>> +/* Enable power block headswitch and wait for it to stabilize */
>> +val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
>> +val |= QDSP6v56_BHS_ON;
>> +writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
>> +val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
> 
> why is this read required
> 

 It was a ditto of what was given in the programming sequence from HW folks.
 yeah, logically the readl does not look needed. Will remove and update.

>> +udelay(1);
>> +
>> +/* Put LDO in bypass mode */
>> +val |= QDSP6v56_LDO_BYP;
>> +writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
>> +
>> +/* Deassert QDSP6 compiler memory clamp */
>> +val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
>> +val &= ~QDSP6v56_CLAMP_QMC_MEM;
>> +writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
>> +
>> +/* Deassert memory peripheral sleep and L2 memory standby */
>> +val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
>> +writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
>> +
>> +/* Turn on L1, L2, ETB and JU memories 1 at a time */
>> +val = readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL);
>> +for (i = 19; i >= 0; i--) {
> 
> where is the magic number 19 coming from?
> 

 Its the total number of Q6's memory head/foot switch banks. Infact
 the magic was there even before my patch. But will add a Macro to fix it.

Regards,
 Sricharan

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"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH V7 00/12] ARM: dts: ipq: updates to enable a few peripherals

[Sricharan R]

All the patches have been tested on ipq4019 dk01, 04, 07 and ipq8074 hk01
boards for spi, bam, qup, qpic, spi-nor, serial, pci.

[V7]
* Fixed Kbuild git bisectability issue

[V6]
* Fixed Bjorn's comments, added his acks that he gave, added Varada's acks
* Rebased on top of Andy's for-next branch.

[v5]
* Fixed a minor comment that i missed earlier.
* https://www.spinics.net/lists/arm-kernel/msg643071.html

[v4]
* Fixed more comments.
* Dropped reserved-memory nodes from board files as
  that might break existing users whose u-boot do not
  specify the fdt_high accordingly.
* Added chosen serial node for all boards to have
  the default serial console specified from DT.

[v3]
* Fixed minor comments from v2,
  https://www.spinics.net/lists/arm-kernel/msg641480.html

* Added Abhishek's review tags

[v2]
* Addressed all comments from Abhishek
* Removed dk01-c2 and dk04-c5 spinand based boards
  as support for spinand is not complete
* Based all patches on top of Andy's for-next branch

[V1]
* https://www.spinics.net/lists/arm-kernel/msg631318.html

Sricharan R (12):
  ARM: dts: ipq4019: Add a default chosen node
  ARM: dts: ipq4019: Add a few peripheral nodes
  ARM: dts: ipq4019: Change the max opp frequency
  ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi
  ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file
  ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file
  ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data
  ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file
  ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file
  ARM: dts: ipq8074: Add peripheral nodes
  ARM: dts: ipq8074: Add pcie nodes
  ARM: dts: ipq8074: Enable few peripherals for hk01 board

 arch/arm/boot/dts/Makefile  |   4 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi   |  10 +-
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts |  19 ++
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts |   9 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi   | 111 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts |  64 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts |  25 ++
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi   |  75 ++
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 162 ++--
 arch/arm64/boot/dts/qcom/ipq8074-hk01.dts   |  62 -
 arch/arm64/boot/dts/qcom/ipq8074.dtsi   | 313 +++-
 11 files changed, 827 insertions(+), 27 deletions(-)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH V7 01/12] ARM: dts: ipq4019: Add a default chosen node

[Sricharan R]

Add a 'chosen' node to select the serial console.
This is needed when bootloaders do not pass the
'console=' bootargs.

Acked-by: Bjorn Andersson 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 8 
 arch/arm/boot/dts/qcom-ipq4019.dtsi   | 2 +-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index e413b21e..ef8d8c8 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -20,6 +20,14 @@
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
compatible = "qcom,ipq4019";
 
+   aliases {
+   serial0 = &blsp1_uart1;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
soc {
rng@22000 {
status = "ok";
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 10d112a..ea9202a 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -256,7 +256,7 @@
 regulator;
 };
 
-   serial@78af000 {
+   blsp1_uart1: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
interrupts = <0 107 0>;
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH V7 03/12] ARM: dts: ipq4019: Change the max opp frequency

[Sricharan R]

The max opp frequency is 716MHZ. So update that.

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 1541e18..2c4ad7d 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -47,7 +47,7 @@
48000   110
20  110
50  110
-   666000  110
+   716000  110
>;
clock-latency = <256000>;
};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH V7 02/12] ARM: dts: ipq4019: Add a few peripheral nodes

[Sricharan R]

Now with the driver updates for some peripherals being there,
add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
peripheral support.

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi |   2 +-
 arch/arm/boot/dts/qcom-ipq4019.dtsi   | 156 --
 2 files changed, 146 insertions(+), 12 deletions(-)

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index ef8d8c8..418f9a0 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -69,7 +69,7 @@
status = "ok";
};
 
-   spi_0: spi@78b5000 {
+   spi@78b5000 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "ok";
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index ea9202a..1541e18 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -24,8 +24,10 @@
interrupt-parent = <&intc>;
 
aliases {
-   spi0 = &spi_0;
-   i2c0 = &i2c_0;
+   spi0 = &blsp1_spi1;
+   spi1 = &blsp1_spi2;
+   i2c0 = &blsp1_i2c3;
+   i2c1 = &blsp1_i2c4;
};
 
cpus {
@@ -104,6 +106,12 @@
};
};
 
+   firmware {
+   scm {
+   compatible = "qcom,scm-ipq4019";
+   };
+   };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <1 2 0xf08>,
@@ -149,13 +157,13 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
-   interrupts = <0 208 0>;
+   interrupts = ;
};
 
blsp_dma: dma@7884000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07884000 0x23000>;
-   interrupts = ;
+   interrupts = ;
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
@@ -163,7 +171,7 @@
status = "disabled";
};
 
-   spi_0: spi@78b5000 {
+   blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x78b5000 0x600>;
interrupts = ;
@@ -172,10 +180,26 @@
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
+   dmas = <&blsp_dma 5>, <&blsp_dma 4>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
+
+   blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
+   compatible = "qcom,spi-qup-v2.2.1";
+   reg = <0x78b6000 0x600>;
+   interrupts = ;
+   clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
+   <&gcc GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   dmas = <&blsp_dma 7>, <&blsp_dma 6>;
+   dma-names = "rx", "tx";
status = "disabled";
};
 
-   i2c_0: i2c@78b7000 {
+   blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b7000 0x600>;
interrupts = ;
@@ -184,14 +208,29 @@
clock-names = "iface", "core";
#address-cells = <1>;
#size-cells = <0>;
+   dmas = <&blsp_dma 9>, <&blsp_dma 8>;
+   dma-names = "rx", "tx";
status = "disabled";
};
 
+   blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
+   compatible = "qcom,i2c-qup-v2.2.1";
+   reg = <0x78b8000 0x600>;
+   in

[PATCH V7 04/12] ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi

[Sricharan R]

Add the common parts for the dk04 boards.

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 111 ++
 arch/arm/boot/dts/qcom-ipq4019.dtsi   |   2 +-
 2 files changed, 112 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
new file mode 100644
index 000..7c1eb19
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019.dtsi"
+#include 
+#include 
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
+
+   aliases {
+   serial0 = &blsp1_uart1;
+   serial1 = &blsp1_uart2;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   memory {
+   device_type = "memory";
+   reg = <0x8000 0x1000>; /* 256MB */
+   };
+
+   soc {
+   pinctrl@100 {
+   serial_0_pins: serial0-pinmux {
+   pins = "gpio16", "gpio17";
+   function = "blsp_uart0";
+   bias-disable;
+   };
+
+   serial_1_pins: serial1-pinmux {
+   pins = "gpio8", "gpio9",
+   "gpio10", "gpio11";
+   function = "blsp_uart1";
+   bias-disable;
+   };
+
+   spi_0_pins: spi-0-pinmux {
+   pinmux {
+   function = "blsp_spi0";
+   pins = "gpio13", "gpio14", "gpio15";
+   bias-disable;
+   };
+   pinmux_cs {
+   function = "gpio";
+   pins = "gpio12";
+   bias-disable;
+   output-high;
+   };
+   };
+
+   i2c_0_pins: i2c-0-pinmux {
+   pins = "gpio20", "gpio21";
+   function = "blsp_i2c0";
+   bias-disable;
+   };
+
+   nand_pins: nand-pins {
+   pins = "gpio53", "gpio55", "gpio56",
+   "gpio57", "gpio58", "gpio59",
+   "gpio60", "gpio62", "gpio63",
+   "gpio64", "gpio65", "gpio66",
+   "gpio67", "gpio68", "gpio69";
+   function = "qpic";
+   };
+   };
+
+   serial@78af000 {
+   pinctrl-0 = <&serial_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   serial@78b {
+   pinctrl-0 = <&serial_1_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   dma@7884000 {
+   status = "ok";
+   };
+
+   spi@78b5000 { /* BLSP1 QUP1 */
+   pinctrl-0 = <&spi_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   cs-gpios = <&tlmm 12 0>;
+
+   m25p80@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   reg = <0>;
+   compatible = "n25q128a11";
+   spi-max-frequency = <2400>;
+   };
+   };
+
+   pci@4000 {
+   status = "ok";
+   perst-gpio = <&tlmm 38 0x1>;
+   };
+
+   qpic-nand@79b {
+   pinctrl-0 

[PATCH V7 06/12] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file

[Sricharan R]

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/Makefile  | 1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 9 +
 2 files changed, 10 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4e15d0d..c6cabec 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -761,6 +761,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
+   qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
new file mode 100644
index 000..2d1c4c6
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C3";
+   compatible = "qcom,ipq4019-ap-dk04.1-c3";
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH V7 08/12] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file

[Sricharan R]

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 64 +
 2 files changed, 65 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index c6cabec..596cce3 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -762,6 +762,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c3.dtb \
+   qcom-ipq4019-ap.dk07.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
new file mode 100644
index 000..8c7ef65
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk07.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C1";
+   compatible = "qcom,ipq4019-ap-dk07.1-c1";
+
+   soc {
+   pci@4000 {
+   status = "ok";
+   perst-gpio = <&tlmm 38 0x1>;
+   };
+
+   spi@78b6000 {
+   status = "ok";
+   };
+
+   pinctrl@100 {
+   serial_1_pins: serial1-pinmux {
+   pins = "gpio8", "gpio9",
+   "gpio10", "gpio11";
+   function = "blsp_uart1";
+   bias-disable;
+   };
+
+   spi_0_pins: spi-0-pinmux {
+   pinmux {
+   function = "blsp_spi0";
+   pins = "gpio13", "gpio14", "gpio15";
+   bias-disable;
+   };
+   pinmux_cs {
+   function = "gpio";
+   pins = "gpio12";
+   bias-disable;
+   output-high;
+   };
+   };
+   };
+
+   serial@78b {
+   pinctrl-0 = <&serial_1_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   spi@78b5000 {
+   pinctrl-0 = <&spi_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   cs-gpios = <&tlmm 12 0>;
+
+   m25p80@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   reg = <0>;
+   compatible = "n25q128a11";
+   spi-max-frequency = <2400>;
+   };
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH V7 07/12] ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data

[Sricharan R]

Add the common data for all dk07 based boards.

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 75 +++
 1 file changed, 75 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
new file mode 100644
index 000..9f1a5a66
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019.dtsi"
+#include 
+#include 
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1";
+
+   memory {
+   device_type = "memory";
+   reg = <0x8000 0x2000>; /* 512MB */
+   };
+
+   aliases {
+   serial0 = &blsp1_uart1;
+   serial1 = &blsp1_uart2;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   soc {
+   pinctrl@100 {
+   serial_0_pins: serial0-pinmux {
+   pins = "gpio16", "gpio17";
+   function = "blsp_uart0";
+   bias-disable;
+   };
+
+   i2c_0_pins: i2c-0-pinmux {
+   pins = "gpio20", "gpio21";
+   function = "blsp_i2c0";
+   bias-disable;
+   };
+
+   nand_pins: nand-pins {
+   pins = "gpio53", "gpio55", "gpio56",
+  "gpio57", "gpio58", "gpio59",
+  "gpio60", "gpio62", "gpio63",
+  "gpio64", "gpio65", "gpio66",
+  "gpio67", "gpio68", "gpio69";
+   function = "qpic";
+};
+   };
+
+   serial@78af000 {
+   pinctrl-0 = <&serial_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   dma@7884000 {
+   status = "ok";
+   };
+
+   i2c@78b7000 { /* BLSP1 QUP2 */
+   pinctrl-0 = <&i2c_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   dma@7984000 {
+   status = "ok";
+   };
+
+   qpic-nand@79b {
+   pinctrl-0 = <&nand_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH V7 09/12] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file

[Sricharan R]

Reviewed-by: Abhishek Sahu 
Acked-by: Bjorn Andersson 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 25 +
 2 files changed, 26 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 596cce3..02b7f1d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -763,6 +763,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq4019-ap.dk07.1-c1.dtb \
+   qcom-ipq4019-ap.dk07.1-c2.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
new file mode 100644
index 000..af7a902
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk07.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C2";
+   compatible = "qcom,ipq4019-ap-dk07.1-c2";
+
+   soc {
+   pinctrl@100 {
+   serial_1_pins: serial1-pinmux {
+   pins = "gpio8", "gpio9";
+   function = "blsp_uart1";
+   bias-disable;
+   };
+   };
+
+   serial@78b {
+   pinctrl-0 = <&serial_1_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH V7 11/12] ARM: dts: ipq8074: Add pcie nodes

[Sricharan R]

The driver/phy support for ipq8074 is available now.
So enabling the nodes in DT.

Reviewed-by: Abhishek Sahu 
Acked-by: Bjorn Andersson 
Signed-off-by: Sricharan R 
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 157 +-
 1 file changed, 156 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi 
b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index bd58ab4..1822698 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -24,7 +24,7 @@
ranges = <0 0 0 0x>;
compatible = "simple-bus";
 
-   pinctrl@100 {
+   tlmm: pinctrl@100 {
compatible = "qcom,ipq8074-pinctrl";
reg = <0x100 0x30>;
interrupts = ;
@@ -278,6 +278,161 @@
pinctrl-names = "default";
status = "disabled";
};
+
+   pcie_phy0: phy@86000 {
+   compatible = "qcom,ipq8074-qmp-pcie-phy";
+   reg = <0x86000 0x1000>;
+   #phy-cells = <0>;
+   clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
+   clock-names = "pipe_clk";
+   clock-output-names = "pcie20_phy0_pipe_clk";
+
+   resets = <&gcc GCC_PCIE0_PHY_BCR>,
+   <&gcc GCC_PCIE0PHY_PHY_BCR>;
+   reset-names = "phy",
+ "common";
+   status = "disabled";
+   };
+
+   pcie0: pci@2000 {
+   compatible = "qcom,pcie-ipq8074";
+   reg =  <0x2000 0xf1d
+   0x2f20 0xa8
+   0x8 0x2000
+   0x2010 0x1000>;
+   reg-names = "dbi", "elbi", "parf", "config";
+   device_type = "pci";
+   linux,pci-domain = <0>;
+   bus-range = <0x00 0xff>;
+   num-lanes = <1>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+
+   phys = <&pcie_phy0>;
+   phy-names = "pciephy";
+
+   ranges = <0x8100 0 0x2020 0x2020
+ 0 0x10   /* downstream I/O */
+ 0x8200 0 0x2030 0x2030
+ 0 0xd0>; /* non-prefetchable memory */
+
+   interrupts = ;
+   interrupt-names = "msi";
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0x7>;
+   interrupt-map = <0 0 0 1 &intc 0 75
+IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+   <0 0 0 2 &intc 0 78
+IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+   <0 0 0 3 &intc 0 79
+IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+   <0 0 0 4 &intc 0 83
+IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+   clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
+<&gcc GCC_PCIE0_AXI_M_CLK>,
+<&gcc GCC_PCIE0_AXI_S_CLK>,
+<&gcc GCC_PCIE0_AHB_CLK>,
+<&gcc GCC_PCIE0_AUX_CLK>;
+
+   clock-names = "iface",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "aux";
+   resets = <&gcc GCC_PCIE0_PIPE_ARES>,
+<&gcc GCC_PCIE0_SLEEP_ARES>,
+<&gcc GCC_PCIE0_CORE_STICKY_ARES>,
+<&gcc GCC_PCIE0_AXI_MASTER_ARES>,
+<&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
+<&gcc GCC_PCIE0_AHB_ARES>,
+<&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
+   reset-names = "pipe",
+   

[PATCH V7 12/12] ARM: dts: ipq8074: Enable few peripherals for hk01 board

[Sricharan R]

Reviewed-by: Abhishek Sahu 
Acked-by: Bjorn Andersson 
Signed-off-by: Sricharan R 
---
 arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 54 +++
 1 file changed, 54 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts 
b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
index 72c5b4a3..c13ddee 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -21,6 +21,7 @@
 
aliases {
serial0 = &blsp1_uart5;
+   serial1 = &blsp1_uart3;
};
 
chosen {
@@ -36,5 +37,58 @@
serial@78b3000 {
status = "ok";
};
+
+   spi@78b5000 {
+   status = "ok";
+
+   m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <5000>;
+   };
+   };
+
+   serial@78b1000 {
+status = "ok";
+   };
+
+   i2c@78b6000 {
+status = "ok";
+   };
+
+   dma@7984000 {
+status = "ok";
+   };
+
+   nand@79b {
+   status = "ok";
+
+   nand@0 {
+   reg = <0>;
+   nand-ecc-strength = <4>;
+   nand-ecc-step-size = <512>;
+   nand-bus-width = <8>;
+   };
+   };
+
+   phy@86000 {
+   status = "ok";
+   };
+
+   phy@8e000 {
+   status = "ok";
+   };
+
+   pci@2000 {
+   status = "ok";
+   perst-gpio = <&tlmm 58 0x1>;
+   };
+
+   pci@1000 {
+   status = "ok";
+   perst-gpio = <&tlmm 61 0x1>;
+   };
};
 };
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH V7 10/12] ARM: dts: ipq8074: Add peripheral nodes

[Sricharan R]

Add serial, i2c, bam, spi, qpic peripheral nodes.

While here, fix the PMU node's irq trigger to avoid
the boot warnings from GIC.

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm64/boot/dts/qcom/ipq8074-hk01.dts |  12 ---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 156 +-
 2 files changed, 155 insertions(+), 13 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts 
b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
index 6a838b5..72c5b4a3 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -33,19 +33,7 @@
};
 
soc {
-   pinctrl@100 {
-   serial_4_pins: serial4_pinmux {
-   mux {
-   pins = "gpio23", "gpio24";
-   function = "blsp4_uart1";
-   bias-disable;
-   };
-   };
-   };
-
serial@78b3000 {
-   pinctrl-0 = <&serial_4_pins>;
-   pinctrl-names = "default";
status = "ok";
};
};
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi 
b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 2bc5dec..bd58ab4 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -32,6 +32,45 @@
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
+
+   serial_4_pins: serial4-pinmux {
+   pins = "gpio23", "gpio24";
+   function = "blsp4_uart1";
+   drive-strength = <8>;
+   bias-disable;
+   };
+
+   i2c_0_pins: i2c-0-pinmux {
+   pins = "gpio42", "gpio43";
+   function = "blsp1_i2c";
+   drive-strength = <8>;
+   bias-disable;
+   };
+
+   spi_0_pins: spi-0-pins {
+   pins = "gpio38", "gpio39", "gpio40", "gpio41";
+   function = "blsp0_spi";
+   drive-strength = <8>;
+   bias-disable;
+   };
+
+   hsuart_pins: hsuart-pins {
+   pins = "gpio46", "gpio47", "gpio48", "gpio49";
+   function = "blsp2_uart";
+   drive-strength = <8>;
+   bias-disable;
+   };
+
+   qpic_pins: qpic-pins {
+   pins = "gpio1", "gpio3", "gpio4",
+  "gpio5", "gpio6", "gpio7",
+  "gpio8", "gpio10", "gpio11",
+  "gpio12", "gpio13", "gpio14",
+  "gpio15", "gpio16", "gpio17";
+   function = "qpic";
+   drive-strength = <8>;
+   bias-disable;
+   };
};
 
intc: interrupt-controller@b00 {
@@ -122,6 +161,121 @@
clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
 <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+   pinctrl-0 = <&serial_4_pins>;
+   pinctrl-names = "default";
+   status = "disabled";
+   };
+
+   blsp_dma: dma@7884000 {
+   compatible = "qcom,bam-v1.7.0";
+   reg = <0x7884000 0x2b000>;
+   interrupts = ;
+   clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+   clock-names = "bam_clk";
+   #dma-cells = <1>;
+   qcom,ee = <0>;
+   };
+
+   blsp1_uart1: serial@78af000 {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x78af000 0x

[PATCH V7 05/12] ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file

[Sricharan R]

Reviewed-by: Abhishek Sahu 
Tested-by: Varadarajan Narayanan 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 19 +++
 2 files changed, 20 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7e24249..4e15d0d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -760,6 +760,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-ifc6540.dtb \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
+   qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
new file mode 100644
index 000..7a96f30
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C1";
+   compatible = "qcom,ipq4019-dk04.1-c1";
+
+   soc {
+   dma@7984000 {
+   status = "ok";
+   };
+
+   qpic-nand@79b {
+   status = "ok";
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH V6 03/12] ARM: dts: ipq4019: Change the max opp frequency

[Sricharan R]

The max opp frequency is 716MHZ. So update that.

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 1541e18..2c4ad7d 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -47,7 +47,7 @@
48000   110
20  110
50  110
-   666000  110
+   716000  110
>;
clock-latency = <256000>;
};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH V6 05/12] ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file

[Sricharan R]

Reviewed-by: Abhishek Sahu 
Tested-by: Varadarajan Narayanan 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 19 +++
 2 files changed, 20 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7e24249..4e15d0d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -760,6 +760,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-ifc6540.dtb \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
+   qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
new file mode 100644
index 000..7a96f30
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C1";
+   compatible = "qcom,ipq4019-dk04.1-c1";
+
+   soc {
+   dma@7984000 {
+   status = "ok";
+   };
+
+   qpic-nand@79b {
+   status = "ok";
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH V6 08/12] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file

[Sricharan R]

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 64 +
 2 files changed, 65 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index c6cabec..596cce3 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -762,6 +762,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c3.dtb \
+   qcom-ipq4019-ap.dk07.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
new file mode 100644
index 000..8c7ef65
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk07.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C1";
+   compatible = "qcom,ipq4019-ap-dk07.1-c1";
+
+   soc {
+   pci@4000 {
+   status = "ok";
+   perst-gpio = <&tlmm 38 0x1>;
+   };
+
+   spi@78b6000 {
+   status = "ok";
+   };
+
+   pinctrl@100 {
+   serial_1_pins: serial1-pinmux {
+   pins = "gpio8", "gpio9",
+   "gpio10", "gpio11";
+   function = "blsp_uart1";
+   bias-disable;
+   };
+
+   spi_0_pins: spi-0-pinmux {
+   pinmux {
+   function = "blsp_spi0";
+   pins = "gpio13", "gpio14", "gpio15";
+   bias-disable;
+   };
+   pinmux_cs {
+   function = "gpio";
+   pins = "gpio12";
+   bias-disable;
+   output-high;
+   };
+   };
+   };
+
+   serial@78b {
+   pinctrl-0 = <&serial_1_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   spi@78b5000 {
+   pinctrl-0 = <&spi_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   cs-gpios = <&tlmm 12 0>;
+
+   m25p80@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   reg = <0>;
+   compatible = "n25q128a11";
+   spi-max-frequency = <2400>;
+   };
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH V6 07/12] ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data

[Sricharan R]

Add the common data for all dk07 based boards.

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 75 +++
 1 file changed, 75 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
new file mode 100644
index 000..9f1a5a66
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019.dtsi"
+#include 
+#include 
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1";
+
+   memory {
+   device_type = "memory";
+   reg = <0x8000 0x2000>; /* 512MB */
+   };
+
+   aliases {
+   serial0 = &blsp1_uart1;
+   serial1 = &blsp1_uart2;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   soc {
+   pinctrl@100 {
+   serial_0_pins: serial0-pinmux {
+   pins = "gpio16", "gpio17";
+   function = "blsp_uart0";
+   bias-disable;
+   };
+
+   i2c_0_pins: i2c-0-pinmux {
+   pins = "gpio20", "gpio21";
+   function = "blsp_i2c0";
+   bias-disable;
+   };
+
+   nand_pins: nand-pins {
+   pins = "gpio53", "gpio55", "gpio56",
+  "gpio57", "gpio58", "gpio59",
+  "gpio60", "gpio62", "gpio63",
+  "gpio64", "gpio65", "gpio66",
+  "gpio67", "gpio68", "gpio69";
+   function = "qpic";
+};
+   };
+
+   serial@78af000 {
+   pinctrl-0 = <&serial_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   dma@7884000 {
+   status = "ok";
+   };
+
+   i2c@78b7000 { /* BLSP1 QUP2 */
+   pinctrl-0 = <&i2c_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   dma@7984000 {
+   status = "ok";
+   };
+
+   qpic-nand@79b {
+   pinctrl-0 = <&nand_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH V6 09/12] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file

[Sricharan R]

Reviewed-by: Abhishek Sahu 
Acked-by: Bjorn Andersson 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 25 +
 2 files changed, 26 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 596cce3..02b7f1d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -763,6 +763,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq4019-ap.dk07.1-c1.dtb \
+   qcom-ipq4019-ap.dk07.1-c2.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
new file mode 100644
index 000..af7a902
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk07.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C2";
+   compatible = "qcom,ipq4019-ap-dk07.1-c2";
+
+   soc {
+   pinctrl@100 {
+   serial_1_pins: serial1-pinmux {
+   pins = "gpio8", "gpio9";
+   function = "blsp_uart1";
+   bias-disable;
+   };
+   };
+
+   serial@78b {
+   pinctrl-0 = <&serial_1_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH V6 11/12] ARM: dts: ipq8074: Add pcie nodes

[Sricharan R]

The driver/phy support for ipq8074 is available now.
So enabling the nodes in DT.

Reviewed-by: Abhishek Sahu 
Acked-by: Bjorn Andersson 
Signed-off-by: Sricharan R 
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 157 +-
 1 file changed, 156 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi 
b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index bd58ab4..1822698 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -24,7 +24,7 @@
ranges = <0 0 0 0x>;
compatible = "simple-bus";
 
-   pinctrl@100 {
+   tlmm: pinctrl@100 {
compatible = "qcom,ipq8074-pinctrl";
reg = <0x100 0x30>;
interrupts = ;
@@ -278,6 +278,161 @@
pinctrl-names = "default";
status = "disabled";
};
+
+   pcie_phy0: phy@86000 {
+   compatible = "qcom,ipq8074-qmp-pcie-phy";
+   reg = <0x86000 0x1000>;
+   #phy-cells = <0>;
+   clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
+   clock-names = "pipe_clk";
+   clock-output-names = "pcie20_phy0_pipe_clk";
+
+   resets = <&gcc GCC_PCIE0_PHY_BCR>,
+   <&gcc GCC_PCIE0PHY_PHY_BCR>;
+   reset-names = "phy",
+ "common";
+   status = "disabled";
+   };
+
+   pcie0: pci@2000 {
+   compatible = "qcom,pcie-ipq8074";
+   reg =  <0x2000 0xf1d
+   0x2f20 0xa8
+   0x8 0x2000
+   0x2010 0x1000>;
+   reg-names = "dbi", "elbi", "parf", "config";
+   device_type = "pci";
+   linux,pci-domain = <0>;
+   bus-range = <0x00 0xff>;
+   num-lanes = <1>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+
+   phys = <&pcie_phy0>;
+   phy-names = "pciephy";
+
+   ranges = <0x8100 0 0x2020 0x2020
+ 0 0x10   /* downstream I/O */
+ 0x8200 0 0x2030 0x2030
+ 0 0xd0>; /* non-prefetchable memory */
+
+   interrupts = ;
+   interrupt-names = "msi";
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0x7>;
+   interrupt-map = <0 0 0 1 &intc 0 75
+IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+   <0 0 0 2 &intc 0 78
+IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+   <0 0 0 3 &intc 0 79
+IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+   <0 0 0 4 &intc 0 83
+IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+   clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
+<&gcc GCC_PCIE0_AXI_M_CLK>,
+<&gcc GCC_PCIE0_AXI_S_CLK>,
+<&gcc GCC_PCIE0_AHB_CLK>,
+<&gcc GCC_PCIE0_AUX_CLK>;
+
+   clock-names = "iface",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "aux";
+   resets = <&gcc GCC_PCIE0_PIPE_ARES>,
+<&gcc GCC_PCIE0_SLEEP_ARES>,
+<&gcc GCC_PCIE0_CORE_STICKY_ARES>,
+<&gcc GCC_PCIE0_AXI_MASTER_ARES>,
+<&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
+<&gcc GCC_PCIE0_AHB_ARES>,
+<&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
+   reset-names = "pipe",
+   

[PATCH V6 12/12] ARM: dts: ipq8074: Enable few peripherals for hk01 board

[Sricharan R]

Reviewed-by: Abhishek Sahu 
Acked-by: Bjorn Andersson 
Signed-off-by: Sricharan R 
---
 arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 62 ++-
 1 file changed, 52 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts 
b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
index 6a838b5..c13ddee 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -21,6 +21,7 @@
 
aliases {
serial0 = &blsp1_uart5;
+   serial1 = &blsp1_uart3;
};
 
chosen {
@@ -33,20 +34,61 @@
};
 
soc {
-   pinctrl@100 {
-   serial_4_pins: serial4_pinmux {
-   mux {
-   pins = "gpio23", "gpio24";
-   function = "blsp4_uart1";
-   bias-disable;
-   };
+   serial@78b3000 {
+   status = "ok";
+   };
+
+   spi@78b5000 {
+   status = "ok";
+
+   m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <5000>;
};
};
 
-   serial@78b3000 {
-   pinctrl-0 = <&serial_4_pins>;
-   pinctrl-names = "default";
+   serial@78b1000 {
+status = "ok";
+   };
+
+   i2c@78b6000 {
+status = "ok";
+   };
+
+   dma@7984000 {
+status = "ok";
+   };
+
+   nand@79b {
+   status = "ok";
+
+   nand@0 {
+   reg = <0>;
+   nand-ecc-strength = <4>;
+   nand-ecc-step-size = <512>;
+   nand-bus-width = <8>;
+   };
+   };
+
+   phy@86000 {
+   status = "ok";
+   };
+
+   phy@8e000 {
+   status = "ok";
+   };
+
+   pci@2000 {
+   status = "ok";
+   perst-gpio = <&tlmm 58 0x1>;
+   };
+
+   pci@1000 {
status = "ok";
+   perst-gpio = <&tlmm 61 0x1>;
};
};
 };
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH V6 10/12] ARM: dts: ipq8074: Add peripheral nodes

[Sricharan R]

Add serial, i2c, bam, spi, qpic peripheral nodes.

While here, fix the PMU node's irq trigger to avoid
the boot warnings from GIC.

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 156 +-
 1 file changed, 155 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi 
b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 2bc5dec..bd58ab4 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -32,6 +32,45 @@
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
+
+   serial_4_pins: serial4-pinmux {
+   pins = "gpio23", "gpio24";
+   function = "blsp4_uart1";
+   drive-strength = <8>;
+   bias-disable;
+   };
+
+   i2c_0_pins: i2c-0-pinmux {
+   pins = "gpio42", "gpio43";
+   function = "blsp1_i2c";
+   drive-strength = <8>;
+   bias-disable;
+   };
+
+   spi_0_pins: spi-0-pins {
+   pins = "gpio38", "gpio39", "gpio40", "gpio41";
+   function = "blsp0_spi";
+   drive-strength = <8>;
+   bias-disable;
+   };
+
+   hsuart_pins: hsuart-pins {
+   pins = "gpio46", "gpio47", "gpio48", "gpio49";
+   function = "blsp2_uart";
+   drive-strength = <8>;
+   bias-disable;
+   };
+
+   qpic_pins: qpic-pins {
+   pins = "gpio1", "gpio3", "gpio4",
+  "gpio5", "gpio6", "gpio7",
+  "gpio8", "gpio10", "gpio11",
+  "gpio12", "gpio13", "gpio14",
+  "gpio15", "gpio16", "gpio17";
+   function = "qpic";
+   drive-strength = <8>;
+   bias-disable;
+   };
};
 
intc: interrupt-controller@b00 {
@@ -122,6 +161,121 @@
clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
 <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+   pinctrl-0 = <&serial_4_pins>;
+   pinctrl-names = "default";
+   status = "disabled";
+   };
+
+   blsp_dma: dma@7884000 {
+   compatible = "qcom,bam-v1.7.0";
+   reg = <0x7884000 0x2b000>;
+   interrupts = ;
+   clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+   clock-names = "bam_clk";
+   #dma-cells = <1>;
+   qcom,ee = <0>;
+   };
+
+   blsp1_uart1: serial@78af000 {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x78af000 0x200>;
+   interrupts = ;
+   clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
+<&gcc GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   status = "disabled";
+   };
+
+   blsp1_uart3: serial@78b1000 {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x78b1000 0x200>;
+   interrupts = ;
+   clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
+   <&gcc GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   dmas = <&blsp_dma 4>,
+   <&blsp_dma 5>;
+   dma-names = "tx", "rx";
+  

[PATCH V6 06/12] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file

[Sricharan R]

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/Makefile  | 1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 9 +
 2 files changed, 10 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4e15d0d..c6cabec 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -761,6 +761,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
+   qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
new file mode 100644
index 000..2d1c4c6
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C3";
+   compatible = "qcom,ipq4019-ap-dk04.1-c3";
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH V6 04/12] ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi

[Sricharan R]

Add the common parts for the dk04 boards.

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 111 ++
 arch/arm/boot/dts/qcom-ipq4019.dtsi   |   2 +-
 2 files changed, 112 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
new file mode 100644
index 000..7c1eb19
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019.dtsi"
+#include 
+#include 
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
+
+   aliases {
+   serial0 = &blsp1_uart1;
+   serial1 = &blsp1_uart2;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   memory {
+   device_type = "memory";
+   reg = <0x8000 0x1000>; /* 256MB */
+   };
+
+   soc {
+   pinctrl@100 {
+   serial_0_pins: serial0-pinmux {
+   pins = "gpio16", "gpio17";
+   function = "blsp_uart0";
+   bias-disable;
+   };
+
+   serial_1_pins: serial1-pinmux {
+   pins = "gpio8", "gpio9",
+   "gpio10", "gpio11";
+   function = "blsp_uart1";
+   bias-disable;
+   };
+
+   spi_0_pins: spi-0-pinmux {
+   pinmux {
+   function = "blsp_spi0";
+   pins = "gpio13", "gpio14", "gpio15";
+   bias-disable;
+   };
+   pinmux_cs {
+   function = "gpio";
+   pins = "gpio12";
+   bias-disable;
+   output-high;
+   };
+   };
+
+   i2c_0_pins: i2c-0-pinmux {
+   pins = "gpio20", "gpio21";
+   function = "blsp_i2c0";
+   bias-disable;
+   };
+
+   nand_pins: nand-pins {
+   pins = "gpio53", "gpio55", "gpio56",
+   "gpio57", "gpio58", "gpio59",
+   "gpio60", "gpio62", "gpio63",
+   "gpio64", "gpio65", "gpio66",
+   "gpio67", "gpio68", "gpio69";
+   function = "qpic";
+   };
+   };
+
+   serial@78af000 {
+   pinctrl-0 = <&serial_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   serial@78b {
+   pinctrl-0 = <&serial_1_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   dma@7884000 {
+   status = "ok";
+   };
+
+   spi@78b5000 { /* BLSP1 QUP1 */
+   pinctrl-0 = <&spi_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   cs-gpios = <&tlmm 12 0>;
+
+   m25p80@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   reg = <0>;
+   compatible = "n25q128a11";
+   spi-max-frequency = <2400>;
+   };
+   };
+
+   pci@4000 {
+   status = "ok";
+   perst-gpio = <&tlmm 38 0x1>;
+   };
+
+   qpic-nand@79b {
+   pinctrl-0 

[PATCH V6 02/12] ARM: dts: ipq4019: Add a few peripheral nodes

[Sricharan R]

Now with the driver updates for some peripherals being there,
add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
peripheral support.

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi |   2 +-
 arch/arm/boot/dts/qcom-ipq4019.dtsi   | 156 --
 2 files changed, 146 insertions(+), 12 deletions(-)

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index ef8d8c8..418f9a0 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -69,7 +69,7 @@
status = "ok";
};
 
-   spi_0: spi@78b5000 {
+   spi@78b5000 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "ok";
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index ea9202a..1541e18 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -24,8 +24,10 @@
interrupt-parent = <&intc>;
 
aliases {
-   spi0 = &spi_0;
-   i2c0 = &i2c_0;
+   spi0 = &blsp1_spi1;
+   spi1 = &blsp1_spi2;
+   i2c0 = &blsp1_i2c3;
+   i2c1 = &blsp1_i2c4;
};
 
cpus {
@@ -104,6 +106,12 @@
};
};
 
+   firmware {
+   scm {
+   compatible = "qcom,scm-ipq4019";
+   };
+   };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <1 2 0xf08>,
@@ -149,13 +157,13 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
-   interrupts = <0 208 0>;
+   interrupts = ;
};
 
blsp_dma: dma@7884000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07884000 0x23000>;
-   interrupts = ;
+   interrupts = ;
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
@@ -163,7 +171,7 @@
status = "disabled";
};
 
-   spi_0: spi@78b5000 {
+   blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x78b5000 0x600>;
interrupts = ;
@@ -172,10 +180,26 @@
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
+   dmas = <&blsp_dma 5>, <&blsp_dma 4>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
+
+   blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
+   compatible = "qcom,spi-qup-v2.2.1";
+   reg = <0x78b6000 0x600>;
+   interrupts = ;
+   clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
+   <&gcc GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   dmas = <&blsp_dma 7>, <&blsp_dma 6>;
+   dma-names = "rx", "tx";
status = "disabled";
};
 
-   i2c_0: i2c@78b7000 {
+   blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b7000 0x600>;
interrupts = ;
@@ -184,14 +208,29 @@
clock-names = "iface", "core";
#address-cells = <1>;
#size-cells = <0>;
+   dmas = <&blsp_dma 9>, <&blsp_dma 8>;
+   dma-names = "rx", "tx";
status = "disabled";
};
 
+   blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
+   compatible = "qcom,i2c-qup-v2.2.1";
+   reg = <0x78b8000 0x600>;
+   in

[PATCH V6 00/12] ARM: dts: ipq: updates to enable a few peripherals

[Sricharan R]

All the patches have been tested on ipq4019 dk01, 04, 07 and ipq8074 hk01
boards for spi, bam, qup, qpic, spi-nor, serial, pci.

[V6]
* Fixed Bjorn's comments, added his acks that he gave, added Varada's acks
* Rebased on top of Andy's for-next branch.

[v5]
* Fixed a minor comment that i missed earlier.
* https://www.spinics.net/lists/arm-kernel/msg643071.html

[v4]
* Fixed more comments.
* Dropped reserved-memory nodes from board files as
  that might break existing users whose u-boot do not
  specify the fdt_high accordingly.
* Added chosen serial node for all boards to have
  the default serial console specified from DT.

[v3]
* Fixed minor comments from v2,
  https://www.spinics.net/lists/arm-kernel/msg641480.html

* Added Abhishek's review tags

[v2]
* Addressed all comments from Abhishek
* Removed dk01-c2 and dk04-c5 spinand based boards
  as support for spinand is not complete
* Based all patches on top of Andy's for-next branch

[V1]
* https://www.spinics.net/lists/arm-kernel/msg631318.html

Sricharan R (12):
  ARM: dts: ipq4019: Add a default chosen node
  ARM: dts: ipq4019: Add a few peripheral nodes
  ARM: dts: ipq4019: Change the max opp frequency
  ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi
  ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file
  ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file
  ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data
  ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file
  ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file
  ARM: dts: ipq8074: Add peripheral nodes
  ARM: dts: ipq8074: Add pcie nodes
  ARM: dts: ipq8074: Enable few peripherals for hk01 board

 arch/arm/boot/dts/Makefile  |   4 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi   |  10 +-
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts |  19 ++
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts |   9 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi   | 111 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts |  64 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts |  25 ++
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi   |  75 ++
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 162 ++--
 arch/arm64/boot/dts/qcom/ipq8074-hk01.dts   |  62 -
 arch/arm64/boot/dts/qcom/ipq8074.dtsi   | 313 +++-
 11 files changed, 827 insertions(+), 27 deletions(-)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH V6 01/12] ARM: dts: ipq4019: Add a default chosen node

[Sricharan R]

Add a 'chosen' node to select the serial console.
This is needed when bootloaders do not pass the
'console=' bootargs.

Acked-by: Bjorn Andersson 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 8 
 arch/arm/boot/dts/qcom-ipq4019.dtsi   | 2 +-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index e413b21e..ef8d8c8 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -20,6 +20,14 @@
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
compatible = "qcom,ipq4019";
 
+   aliases {
+   serial0 = &blsp1_uart1;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
soc {
rng@22000 {
status = "ok";
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 10d112a..ea9202a 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -256,7 +256,7 @@
 regulator;
 };
 
-   serial@78af000 {
+   blsp1_uart1: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
interrupts = <0 107 0>;
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH V6 4/5] remoteproc: qcom: Add support for q6v5-wcss pil

[Sricharan R]

IPQ8074 has an integrated Hexagon dsp core q6v5 and a wireless lan
(Lithium) IP. An mdt type single image format is used for the
firmware. So the mdt_load function can be directly used to load
the firmware. Also add the relevant resets required for this core.

Acked-by: Rob Herring 
Signed-off-by: Sricharan R 
---
 .../devicetree/bindings/remoteproc/qcom,q6v5.txt   |  7 +++-
 drivers/remoteproc/Kconfig |  1 +
 drivers/remoteproc/qcom_q6v5_pil.c | 37 +-
 3 files changed, 43 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt 
b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
index d901824..3a4a1a92 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
@@ -12,6 +12,7 @@ on the Qualcomm Hexagon core.
"qcom,msm8974-mss-pil"
"qcom,msm8996-mss-pil"
"qcom,sdm845-mss-pil"
+   "qcom,ipq8074-wcss-pil"
 
 - reg:
Usage: required
@@ -50,11 +51,15 @@ on the Qualcomm Hexagon core.
Usage: required
Value type: 
Definition: reference to the reset-controller for the modem sub-system
+   reference to the list of 3 reset-controllers for the
+   wcss sub-system
 
 - reset-names:
Usage: required
Value type: 
-   Definition: must be "mss_restart"
+   Definition: must be "mss_restart" for the modem sub-system
+   Definition: must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
+   for the wcss syb-system
 
 - cx-supply:
 - mss-supply:
diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
index 0272740..4841420 100644
--- a/drivers/remoteproc/Kconfig
+++ b/drivers/remoteproc/Kconfig
@@ -113,6 +113,7 @@ config QCOM_Q6V5_PIL
select MFD_SYSCON
select QCOM_RPROC_COMMON
select QCOM_SCM
+   select QCOM_MDT_LOADER
help
  Say y here to support the Qualcomm Peripherial Image Loader for the
  Hexagon V5 based remote processors.
diff --git a/drivers/remoteproc/qcom_q6v5_pil.c 
b/drivers/remoteproc/qcom_q6v5_pil.c
index 2403bb2..fbe179d 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -138,6 +138,9 @@ struct q6v5 {
u32 halt_nc;
 
struct reset_control *mss_restart;
+   struct reset_control *wcss_aon_reset;
+   struct reset_control *wcss_reset;
+   struct reset_control *wcss_q6_reset;
 
struct qcom_smem_state *state;
unsigned stop_bit;
@@ -204,6 +207,7 @@ enum {
MSS_MSM8974,
MSS_MSM8996,
MSS_SDM845,
+   WCSS_IPQ8074,
 };
 
 static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
@@ -1173,6 +1177,26 @@ static int q6v5_init_clocks(struct device *dev, struct 
clk **clks,
return i;
 }
 
+static int q6v5_wcss_init_reset(struct q6v5 *qproc)
+{
+   qproc->wcss_aon_reset = devm_reset_control_get(qproc->dev,
+  "wcss_aon_reset");
+   if (IS_ERR(qproc->wcss_aon_reset))
+   return PTR_ERR(qproc->wcss_aon_reset);
+
+   qproc->wcss_reset = devm_reset_control_get(qproc->dev,
+  "wcss_reset");
+   if (IS_ERR(qproc->wcss_reset))
+   return PTR_ERR(qproc->wcss_reset);
+
+   qproc->wcss_q6_reset = devm_reset_control_get(qproc->dev,
+ "wcss_q6_reset");
+   if (IS_ERR(qproc->wcss_q6_reset))
+   return PTR_ERR(qproc->wcss_q6_reset);
+
+   return 0;
+}
+
 static int q6v5_init_reset(struct q6v5 *qproc)
 {
qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev,
@@ -1237,6 +1261,9 @@ static int q6v5_alloc_memory_region(struct q6v5 *qproc)
return -EBUSY;
}
 
+   if (qproc->version == WCSS_IPQ8074)
+   return 0;
+
child = of_get_child_by_name(qproc->dev->of_node, "mpss");
node = of_parse_phandle(child, "memory-region", 0);
ret = of_address_to_resource(node, 0, &r);
@@ -1279,6 +1306,7 @@ static int q6v5_probe(struct platform_device *pdev)
qproc = (struct q6v5 *)rproc->priv;
qproc->dev = &pdev->dev;
qproc->rproc = rproc;
+   qproc->version = desc->version;
platform_set_drvdata(pdev, qproc);
 
if (desc->has_alt_reset) {
@@ -1344,7 +1372,6 @@ static int q6v5_probe(struct platform_device *pdev)
if (ret)
goto free_rproc;
 
-   qproc->version = desc->version;
qproc->need_mem_protection = de

[PATCH V6 5/5] remoteproc: qcom: Add q6v5-wcss rproc ops

[Sricharan R]

q6v5-wcss core's start function is mostly common
with the q6v5 of msm8996. So reuse that and add
the stop function.

Signed-off-by: Sricharan R 
---
 drivers/remoteproc/qcom_q6v5_pil.c | 227 +
 1 file changed, 227 insertions(+)

diff --git a/drivers/remoteproc/qcom_q6v5_pil.c 
b/drivers/remoteproc/qcom_q6v5_pil.c
index fbe179d..979f6c9 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -113,6 +113,17 @@
 #define SLEEP_CHECK_MAX_LOOPS   200
 #define BOOT_FSM_TIMEOUT1
 
+/* QDSP6v5-WCSS config/status registers */
+#define TCSR_GLOBAL_CFG0   0x0
+#define TCSR_GLOBAL_CFG1   0x4
+#define SSCAON_CONFIG  0x8
+#define SSCAON_STATUS  0xc
+#define QDSP6SS_BHS_STATUS 0x78
+#define QDSP6SS_RST_EVB0x10
+
+#define BHS_EN_REST_ACKBIT(0)
+#define SSCAON_ENABLE  BIT(13)
+
 struct reg_info {
struct regulator *reg;
int uV;
@@ -823,6 +834,61 @@ static int q6v5_mpss_load(struct q6v5 *qproc)
return ret < 0 ? ret : 0;
 }
 
+static int q6v5_wcss_start(struct rproc *rproc)
+{
+   struct q6v5 *qproc = rproc->priv;
+   int ret = 0;
+
+   ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
+ qproc->active_clk_count);
+   if (ret) {
+   dev_err(qproc->dev, "failed to enable clocks\n");
+   return ret;
+   }
+
+   /* Release Q6 and WCSS reset */
+   ret = reset_control_deassert(qproc->wcss_reset);
+   if (ret)
+   dev_err(qproc->dev, "wcss_reset failed\n");
+
+   ret = reset_control_deassert(qproc->wcss_q6_reset);
+   if (ret)
+   dev_err(qproc->dev, "wcss_q6_reset failed\n");
+
+   /* Lithium configuration - clock gating and bus arbitration */
+   ret = regmap_update_bits(qproc->halt_map,
+qproc->halt_nc + TCSR_GLOBAL_CFG0,
+0x1F, 0x14);
+   if (ret)
+   return ret;
+
+   ret = regmap_update_bits(qproc->halt_map,
+qproc->halt_nc + TCSR_GLOBAL_CFG1,
+1, 0);
+   if (ret)
+   return ret;
+
+   /* Write bootaddr to EVB so that Q6WCSS will jump there after reset */
+   writel(rproc->bootaddr >> 4, qproc->reg_base + QDSP6SS_RST_EVB);
+
+   ret = q6v5_reset(qproc);
+   if (ret)
+   return ret;
+
+   q6v5_reset_rest(qproc);
+
+   ret = wait_for_completion_timeout(&qproc->start_done,
+ msecs_to_jiffies(5000));
+   if (ret == 0) {
+   dev_err(qproc->dev, "start timed out\n");
+   return -ETIMEDOUT;
+   }
+
+   qproc->running = true;
+
+   return 0;
+}
+
 static int q6v5_start(struct rproc *rproc)
 {
struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
@@ -972,6 +1038,149 @@ static int q6v5_start(struct rproc *rproc)
return ret;
 }
 
+static int q6v5_wcss_powerdown(struct q6v5 *qproc)
+{
+   unsigned int val = 0;
+   int ret;
+
+   /* 1 - Assert WCSS/Q6 HALTREQ */
+   q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
+
+   /* 2 - Enable WCSSAON_CONFIG */
+   val = readl(qproc->rmb_base + SSCAON_CONFIG);
+   val |= SSCAON_ENABLE;
+   writel(val, qproc->rmb_base + SSCAON_CONFIG);
+
+   /* 3 - Set SSCAON_CONFIG */
+   val |= BIT(15);
+   val &= ~BIT(16);
+   val &= ~BIT(17);
+   val &= ~BIT(18);
+   writel(val, qproc->rmb_base + SSCAON_CONFIG);
+
+   /* 4 - SSCAON_CONFIG 1 */
+   val |= BIT(1);
+   writel(val, qproc->rmb_base + SSCAON_CONFIG);
+
+   /* 5 - wait for SSCAON_STATUS */
+   ret = readl_poll_timeout(qproc->rmb_base + SSCAON_STATUS,
+val, (val & 0x) == 0x400, 1000,
+HALT_CHECK_MAX_LOOPS);
+   if (ret) {
+   dev_err(qproc->dev,
+   "can't get SSCAON_STATUS rc:%d)\n", ret);
+   }
+
+   /* 6 - De-assert WCSS_AON reset */
+   reset_control_assert(qproc->wcss_aon_reset);
+
+   /* 7 - Disable WCSSAON_CONFIG 13 */
+   val = readl(qproc->rmb_base + SSCAON_CONFIG);
+   val &= ~SSCAON_ENABLE;
+   writel(val, qproc->rmb_base + SSCAON_CONFIG);
+
+   /* 8 - De-assert WCSS/Q6 HALTREQ */
+   reset_control_assert(qproc->wcss_reset);
+
+   return ret;
+}
+
+static int q6v5_q6_powerdown(struct q6v5 *qproc)
+{
+   int i = 0, ret;
+   unsigned int val = 0;
+
+   /* 1 - Halt Q6 bus interface */
+   q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
+
+   /* 2 - Disable Q6 Core clock */
+   val = 

[PATCH V6 1/5] remoteproc: qcom: mdt_loader: Make the firmware authentication optional

[Sricharan R]

qcom_mdt_load function loads the mdt type firmware and
initialises the secure memory as well. Make the initialisation only
when requested by the caller, so that the function can be used
by self-authenticating remoteproc as well.

Acked-by: Bjorn Andersson 
Signed-off-by: Sricharan R 
---
 drivers/soc/qcom/mdt_loader.c   | 87 ++---
 include/linux/soc/qcom/mdt_loader.h |  4 ++
 2 files changed, 66 insertions(+), 25 deletions(-)

diff --git a/drivers/soc/qcom/mdt_loader.c b/drivers/soc/qcom/mdt_loader.c
index 17b314d..3747487 100644
--- a/drivers/soc/qcom/mdt_loader.c
+++ b/drivers/soc/qcom/mdt_loader.c
@@ -74,23 +74,10 @@ ssize_t qcom_mdt_get_size(const struct firmware *fw)
 }
 EXPORT_SYMBOL_GPL(qcom_mdt_get_size);
 
-/**
- * qcom_mdt_load() - load the firmware which header is loaded as fw
- * @dev:   device handle to associate resources with
- * @fw:firmware object for the mdt file
- * @firmware:  name of the firmware, for construction of segment file names
- * @pas_id:PAS identifier
- * @mem_region:allocated memory region to load firmware into
- * @mem_phys:  physical address of allocated memory region
- * @mem_size:  size of the allocated memory region
- * @reloc_base:adjusted physical address after relocation
- *
- * Returns 0 on success, negative errno otherwise.
- */
-int qcom_mdt_load(struct device *dev, const struct firmware *fw,
- const char *firmware, int pas_id, void *mem_region,
- phys_addr_t mem_phys, size_t mem_size,
- phys_addr_t *reloc_base)
+static int __qcom_mdt_load(struct device *dev, const struct firmware *fw,
+  const char *firmware, int pas_id, void *mem_region,
+  phys_addr_t mem_phys, size_t mem_size,
+  phys_addr_t *reloc_base, bool pas_init)
 {
const struct elf32_phdr *phdrs;
const struct elf32_phdr *phdr;
@@ -121,10 +108,12 @@ int qcom_mdt_load(struct device *dev, const struct 
firmware *fw,
if (!fw_name)
return -ENOMEM;
 
-   ret = qcom_scm_pas_init_image(pas_id, fw->data, fw->size);
-   if (ret) {
-   dev_err(dev, "invalid firmware metadata\n");
-   goto out;
+   if (pas_init) {
+   ret = qcom_scm_pas_init_image(pas_id, fw->data, fw->size);
+   if (ret) {
+   dev_err(dev, "invalid firmware metadata\n");
+   goto out;
+   }
}
 
for (i = 0; i < ehdr->e_phnum; i++) {
@@ -144,10 +133,13 @@ int qcom_mdt_load(struct device *dev, const struct 
firmware *fw,
}
 
if (relocate) {
-   ret = qcom_scm_pas_mem_setup(pas_id, mem_phys, max_addr - 
min_addr);
-   if (ret) {
-   dev_err(dev, "unable to setup relocation\n");
-   goto out;
+   if (pas_init) {
+   ret = qcom_scm_pas_mem_setup(pas_id, mem_phys,
+max_addr - min_addr);
+   if (ret) {
+   dev_err(dev, "unable to setup relocation\n");
+   goto out;
+   }
}
 
/*
@@ -202,7 +194,52 @@ int qcom_mdt_load(struct device *dev, const struct 
firmware *fw,
 
return ret;
 }
+
+/**
+ * qcom_mdt_load() - load the firmware which header is loaded as fw
+ * @dev:   device handle to associate resources with
+ * @fw:firmware object for the mdt file
+ * @firmware:  name of the firmware, for construction of segment file names
+ * @pas_id:PAS identifier
+ * @mem_region:allocated memory region to load firmware into
+ * @mem_phys:  physical address of allocated memory region
+ * @mem_size:  size of the allocated memory region
+ * @reloc_base:adjusted physical address after relocation
+ *
+ * Returns 0 on success, negative errno otherwise.
+ */
+int qcom_mdt_load(struct device *dev, const struct firmware *fw,
+ const char *firmware, int pas_id, void *mem_region,
+ phys_addr_t mem_phys, size_t mem_size,
+ phys_addr_t *reloc_base)
+{
+   return __qcom_mdt_load(dev, fw, firmware, pas_id, mem_region, mem_phys,
+  mem_size, reloc_base, true);
+}
 EXPORT_SYMBOL_GPL(qcom_mdt_load);
 
+/**
+ * qcom_mdt_load_no_init() - load the firmware which header is loaded as fw
+ * @dev:   device handle to associate resources with
+ * @fw:firmware object for the mdt file
+ * @firmware:  name of the firmware, for construction of segment file names
+ * @pas_id:PAS identifier
+ * @mem_region:allocated memory region to load firmware into
+ * @mem_phys:  physical address of allocated memory region
+ * @mem_size:  size of th

[PATCH V6 2/5] remoteproc: qcom: Push reset ops, rproc ops in to of_match data

[Sricharan R]

Instead of directly assigning reset and rproc ops, put them
in to of_match data and get from that. Currently same ops
are used for all compatibles, but that will change when we add
q6v5-wcss support.

Signed-off-by: Sricharan R 
---
 drivers/remoteproc/qcom_q6v5_pil.c | 38 --
 1 file changed, 24 insertions(+), 14 deletions(-)

diff --git a/drivers/remoteproc/qcom_q6v5_pil.c 
b/drivers/remoteproc/qcom_q6v5_pil.c
index a3d65a7..cc26cab 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -125,18 +125,6 @@ struct qcom_mss_reg_res {
int uA;
 };
 
-struct rproc_hexagon_res {
-   const char *hexagon_mba_image;
-   struct qcom_mss_reg_res *proxy_supply;
-   struct qcom_mss_reg_res *active_supply;
-   char **proxy_clk_names;
-   char **reset_clk_names;
-   char **active_clk_names;
-   int version;
-   bool need_mem_protection;
-   bool has_alt_reset;
-};
-
 struct q6v5 {
struct device *dev;
struct rproc *rproc;
@@ -197,6 +185,20 @@ struct q6v5 {
int version;
 };
 
+struct rproc_hexagon_res {
+   const char *hexagon_mba_image;
+   struct qcom_mss_reg_res *proxy_supply;
+   struct qcom_mss_reg_res *active_supply;
+   char **proxy_clk_names;
+   char **reset_clk_names;
+   char **active_clk_names;
+   int version;
+   bool need_mem_protection;
+   bool has_alt_reset;
+   int (*init_reset)(struct q6v5 *qproc);
+   const struct rproc_ops *ops;
+};
+
 enum {
MSS_MSM8916,
MSS_MSM8974,
@@ -1250,7 +1252,7 @@ static int q6v5_probe(struct platform_device *pdev)
if (!desc)
return -EINVAL;
 
-   rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops,
+   rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops,
desc->hexagon_mba_image, sizeof(*qproc));
if (!rproc) {
dev_err(&pdev->dev, "failed to allocate rproc\n");
@@ -1321,7 +1323,7 @@ static int q6v5_probe(struct platform_device *pdev)
}
qproc->active_reg_count = ret;
 
-   ret = q6v5_init_reset(qproc);
+   ret = desc->init_reset(qproc);
if (ret)
goto free_rproc;
 
@@ -1417,6 +1419,8 @@ static int q6v5_remove(struct platform_device *pdev)
.need_mem_protection = true,
.has_alt_reset = true,
.version = MSS_SDM845,
+   .init_reset = q6v5_init_reset,
+   .ops = &q6v5_ops,
 };
 
 static const struct rproc_hexagon_res msm8996_mss = {
@@ -1436,6 +1440,8 @@ static int q6v5_remove(struct platform_device *pdev)
.need_mem_protection = true,
.has_alt_reset = false,
.version = MSS_MSM8996,
+   .init_reset = q6v5_init_reset,
+   .ops = &q6v5_ops,
 };
 
 static const struct rproc_hexagon_res msm8916_mss = {
@@ -1468,6 +1474,8 @@ static int q6v5_remove(struct platform_device *pdev)
.need_mem_protection = false,
.has_alt_reset = false,
.version = MSS_MSM8916,
+   .init_reset = q6v5_init_reset,
+   .ops = &q6v5_ops,
 };
 
 static const struct rproc_hexagon_res msm8974_mss = {
@@ -1508,6 +1516,8 @@ static int q6v5_remove(struct platform_device *pdev)
.need_mem_protection = false,
.has_alt_reset = false,
.version = MSS_MSM8974,
+   .init_reset = q6v5_init_reset,
+   .ops = &q6v5_ops,
 };
 
 static const struct of_device_id q6v5_of_match[] = {
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH V6 3/5] remoteproc: qcom: Split the head and tail of the q5v5-pil rproc reset function

[Sricharan R]

Most of the q6v5-wcss reset function is same as MSM8996 reset sequence
that will be added later. So split and move out the common pieces
so that the same code can be reused.

Signed-off-by: Sricharan R 
---
 drivers/remoteproc/qcom_q6v5_pil.c | 169 -
 1 file changed, 93 insertions(+), 76 deletions(-)

diff --git a/drivers/remoteproc/qcom_q6v5_pil.c 
b/drivers/remoteproc/qcom_q6v5_pil.c
index cc26cab..2403bb2 100644
--- a/drivers/remoteproc/qcom_q6v5_pil.c
+++ b/drivers/remoteproc/qcom_q6v5_pil.c
@@ -430,11 +430,101 @@ static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 
status, int ms)
return val;
 }
 
+static int q6v5_reset(struct q6v5 *qproc)
+{
+   u32 ret;
+   int val, i;
+
+   /* Assert resets, stop core */
+   val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
+   val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
+   writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
+
+   /* BHS require xo cbcr to be enabled */
+   val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
+   val |= 0x1;
+   writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
+
+   /* Read CLKOFF bit to go low indicating CLK is enabled */
+   ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
+val, !(val & BIT(31)), 1,
+HALT_CHECK_MAX_LOOPS);
+   if (ret) {
+   dev_err(qproc->dev,
+   "xo cbcr enabling timed out (rc:%d)\n", ret);
+   return ret;
+   }
+   /* Enable power block headswitch and wait for it to stabilize */
+   val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+   val |= QDSP6v56_BHS_ON;
+   writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+   val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+   udelay(1);
+
+   /* Put LDO in bypass mode */
+   val |= QDSP6v56_LDO_BYP;
+   writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+
+   /* Deassert QDSP6 compiler memory clamp */
+   val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+   val &= ~QDSP6v56_CLAMP_QMC_MEM;
+   writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+
+   /* Deassert memory peripheral sleep and L2 memory standby */
+   val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
+   writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+
+   /* Turn on L1, L2, ETB and JU memories 1 at a time */
+   val = readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL);
+   for (i = 19; i >= 0; i--) {
+   val |= BIT(i);
+   writel(val, qproc->reg_base + QDSP6SS_MEM_PWR_CTL);
+   /*
+* Read back value to ensure the write is done then
+* wait for 1us for both memory peripheral and data
+* array to turn on.
+*/
+   val |= readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL);
+   udelay(1);
+   }
+   /* Remove word line clamp */
+   val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+   val &= ~QDSP6v56_CLAMP_WL;
+   writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+
+   return 0;
+}
+
+static void q6v5_reset_rest(struct q6v5 *qproc)
+{
+   u32 val;
+
+   val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+
+   /* Remove IO clamp */
+   val &= ~Q6SS_CLAMP_IO;
+   writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
+
+   /* Bring core out of reset */
+   val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
+   val &= ~Q6SS_CORE_ARES;
+   writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
+
+   /* Turn on core clock */
+   val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
+   val |= Q6SS_CLK_ENABLE;
+   writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
+
+   /* Start core execution */
+   val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
+   val &= ~Q6SS_STOP_CORE;
+   writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
+}
+
 static int q6v5proc_reset(struct q6v5 *qproc)
 {
u32 val;
int ret;
-   int i;
 
if (qproc->version == MSS_SDM845) {
 
@@ -470,64 +560,7 @@ static int q6v5proc_reset(struct q6v5 *qproc)
/* Override the ACC value if required */
writel(QDSP6SS_ACC_OVERRIDE_VAL,
   qproc->reg_base + QDSP6SS_STRAP_ACC);
-
-   /* Assert resets, stop core */
-   val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
-   val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
-   writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
-
-   /* BHS require xo cbcr to be enabled */
-   val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
-   val |= 0x1;
-   writel(val, qproc->reg_base + QDSP6SS

[PATCH V6 0/5] Add support for Hexagon q6v5-wcss integrated core

[Sricharan R]

IPQ8074 has an integrated Hexagon dsp core Q6v5 and a wireless lan
(Lithium) IP. This series adds the remoteproc driver to reset, load
and boot Q6 firmware.

The first patch is to make the mdt_loader authenticate
the firmware only if required, so that the code can be reused for
self-authenticating firmware like the Q6v5 core in IPQ8074. The second
patch exports the elf header's get_boot_addr helper to reuse it.
The next couple of patches arranges the code in the original q6v5-mpss
rproc to add q6v5-wcss later. The last couple of patches add the relevant
bits for the q6v5-wcss core.

This is done on top of Avaneesh's msm8996 rproc support [1]

[1] https://lkml.org/lkml/2017/10/24/771

V6:
   Rebased on top of,
   https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1674300.html

   Dropped remoteproc: Export rproc_elf_get_boot_addr, as it is already merged
   by a different patch from Bjorn.

   Minor change to the q6 power down sequence.

v5:
No change. Just updated tags in PATCH #5

V4:
Fixed Bjorn's comment in PATCH#1 and added his acked-by
Rebased on top of Avinash's latest rproc for msm8996 q6 support.

V3:
Rebased on top of latest remoteproc next

V2:
Last time introduced this a new rproc driver, but there is lot
of code that can be shared if it is added to the q6v5-mpss pil
    driver.

Sricharan R (5):
  remoteproc: qcom: mdt_loader: Make the firmware authentication
optional
  remoteproc: qcom: Push reset ops, rproc ops in to of_match data
  remoteproc: qcom: Split the head and tail of the q5v5-pil rproc reset
function
  remoteproc: qcom: Add support for q6v5-wcss pil
  remoteproc: qcom: Add q6v5-wcss rproc ops

 .../devicetree/bindings/remoteproc/qcom,q6v5.txt   |   7 +-
 drivers/remoteproc/Kconfig |   1 +
 drivers/remoteproc/qcom_q6v5_pil.c | 468 +
 drivers/soc/qcom/mdt_loader.c  |  87 ++--
 include/linux/soc/qcom/mdt_loader.h|   4 +
 5 files changed, 450 insertions(+), 117 deletions(-)

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

Re: [v5,05/13] ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi

[Sricharan R]

Hi Sven,

On 4/18/2018 1:08 PM, Sven Eckelmann wrote:
> Hi,
> 
> On Mittwoch, 18. April 2018 12:45:20 CEST Sricharan R wrote:
>>  Right, will add the above change to soc.dtsi in V6. Does that sound ok for 
>> you ?
> 
> I have submitted a patch for this now [1] because I need this for OpenWrt 
> (sooner rather than later). And I am not sure whether it is good to have this 
> in your feature series because it is a bugfix which might even qualify for 
> sta...@vger.kernel.org.
> 
> I hope this patch [1] is ok for you.
> 

 Sure. Acked that. Thanks.

Regards,
 Sricharan

-- 
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

Re: [v5,05/13] ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi

[Sricharan R]

Hi Sven,

On 4/18/2018 12:37 PM, Sven Eckelmann wrote:
> On Mittwoch, 18. April 2018 08:59:46 CEST Sven Eckelmann wrote:
> [...]
>> I would not know how to disable QSEE on these boards and thus would assume 
>> that it should be part of this dtsi.
> 
> 
> Just did some reviews of the reserved-memory regions in other QCA devices and 
> it looks like this tz and smem are often directly added to the SoC dtsi. So I 
> will prepare a similar change for qcom-ipq4019.dtsi and this would then solve 
> it for AP-DK01/04/07 and no changes in the board-family specific dtsi would 
> be 
> necessary.
> 
> But maybe someone has an objection because tz and smem can actually be 
> disabled in a sane way on these SoCs and thus it would be better to have 
> these 
> regions in the board specific dts(i) files. We will see...

 Right, will add the above change to soc.dtsi in V6. Does that sound ok for you 
?

Regards,
 Sricharan

-- 
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

Re: [v5,08/13] ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data

[Sricharan R]

Hi Sven,

On 4/18/2018 12:29 PM, Sven Eckelmann wrote:
> On Freitag, 23. März 2018 15:48:51 CEST Sricharan R wrote:
>> Add the common data for all dk07 based boards.
>>
>> Reviewed-by: Abhishek Sahu 
>> Signed-off-by: Sricharan R 
>> ---
>>  arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 69 
>> +++
>>  1 file changed, 69 insertions(+)
>>  create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
> 
> The no-map reserved-memory for tz and smem are missing. Linux doesn't have 
> control over these regions and they are placed in the middle of the ram 
> before 
> Linux even starts. And u-boot is also not adding these ranges automatically.
> 
>   reserved-memory {
>   #address-cells = <0x1>;
>   #size-cells = <0x1>;
>   ranges;
> 
>   smem@87e0 {
>   reg = <0x87e0 0x08>;
>   no-map;
>   };
> 
>   tz@87e8 {
>   reg = <0x87e8 0x18>;
>   no-map;
>   };
>   };
> 
> This can either (depending on HW/SW configuration) lead to a failed boot [1] 
> or to runtime crashes like:
> 
> root@OpenWrt:/# /tmp/memory-allocator-test
> main 0
> [  571.758058] Unhandled fault: imprecise external abort (0xc06) at 
> 0x01715ff8
> [  571.758099] pgd = cebec000
> [  571.763826] [01715ff8] *pgd=8e7fa835, *pte=87e7f75f, *ppte=87e7fc7f
> Bus error
> 
> I would not know how to disable QSEE on these boards and thus would assume 
> that it should be part of this dtsi.

 As we discussed offline, i agree that the smem and tz reserved memory nodes 
need to
 be added. It still boots today without that, but would abort when that memory
 region is allocated and written. I will add the reserved-memory node for that
 in V6 along with other comments.

Regards,
 Sricharan

-- 
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data

[sricharan]

On 2018-04-06 20:43, Richard Cochran wrote:
On Fri, Apr 06, 2018 at 06:35:49PM +0530, sricha...@codeaurora.org 
wrote:

 I tried booting mainline built with qcom_defconfig on ap148 and
 did boot. Not sure if your bootloader's bootarg is this,
  'console=ttyMSM0,115200n8' ?


Yes, I think so.  I'll double check it.

Do you have any out-of-tree patches or special jumper settings?


 No out of tree patches or special jumper settings. I am booting the
 mainline kernel, ap148.dtb + ramfs.

Regards,
 Sricharan

Re: [PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data

[sricharan]

On 2018-04-06 10:25, Richard Cochran wrote:
On Mon, Apr 02, 2018 at 03:28:47PM +0530, sricha...@codeaurora.org 
wrote:

  Yes, i will post another series for ipq806[2/4] updates and the
corresponding
  boards after this.


I tried mainline on the ap148 using qcom_defconfig and the
qcom-ipq8064-ap148.dtb, and it doesn't boot FYI.



 I tried booting mainline built with qcom_defconfig on ap148 and
 did boot. Not sure if your bootloader's bootarg is this,
  'console=ttyMSM0,115200n8' ?


 root@(none):/# cat /proc/version
 Linux version 4.16.0 (srichara@srichara-linux) (gcc version 6.3.1 
20170109 (Linaro GCC 6.3-2017.02)) #1691 SMP PREEMPT Fri Apr 6 15:30:45 
IST 2018

 root@(none):/#

Regards,
 Sricharan

Re: [PATCH v4 13/14] dt-bindings: cpufreq: Document operating-points-v2-kryo-cpu

[Sricharan R]

Hi Viresh,

On 4/3/2018 9:53 AM, Viresh Kumar wrote:
> On 03-04-18, 08:11, Sricharan R wrote:
>>  Right, i was adding a similar one for krait cores [1]. There is code common 
>> in the
>>  init sequence across both (little). Do you suggest to make them common ?
> 
> It may make sense as we are talking about one SoC family here :)
> 
  ok. So either of us can merge, depending upon which one goes first.

Regards,
 Sricharan
-- 
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Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v4 13/14] dt-bindings: cpufreq: Document operating-points-v2-kryo-cpu

[Sricharan R]

Hi Viresh,

On 4/2/2018 8:37 PM, Sricharan R wrote:
> Hi Viresh,
> 
> On 4/2/2018 3:00 PM, Viresh Kumar wrote:
>> +Sricharan,
>>
>> On 30-03-18, 00:26, Ilia Lin wrote:
>>> In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996
>>> that have KRYO processors, the CPU ferequencies subset and voltage value
>>> of each OPP varies based on the silicon variant in use.
>>> Qualcomm Technologies, Inc. Process Voltage Scaling Tables
>>> defines the voltage and frequency value based on the msm-id in SMEM
>>> and speedbin blown in the efuse combination.
>>> The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
>>> to provide the OPP framework with required information.
>>> This is used to determine the voltage and frequency value for each OPP of
>>> operating-points-v2 table when it is parsed by the OPP framework.
>>>
>>> This change adds documentation.
>>>
>>> Change-Id: I1953f652a48249fb516d175f0e965a9510cd4209
>>> Signed-off-by: Ilia Lin 
>>> ---
>>>  .../devicetree/bindings/cpufreq/kryo-cpufreq.txt   | 693 
>>> +
>>>  1 file changed, 693 insertions(+)
>>>  create mode 100644 
>>> Documentation/devicetree/bindings/cpufreq/kryo-cpufreq.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/cpufreq/kryo-cpufreq.txt 
>>> b/Documentation/devicetree/bindings/cpufreq/kryo-cpufreq.txt
>>
>> This should really go in opp directory.
>>
>>> new file mode 100644
>>> index 000..20cef9d
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/cpufreq/kryo-cpufreq.txt
>>> @@ -0,0 +1,693 @@
>>> +Qualcomm Technologies, Inc. KRYO CPUFreq and OPP bindings
>>> +===
>>> +
>>> +In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996
>>> +that have KRYO processors, the CPU ferequencies subset and voltage value
>>> +of each OPP varies based on the silicon variant in use.
>>> +Qualcomm Technologies, Inc. Process Voltage Scaling Tables
>>> +defines the voltage and frequency value based on the msm-id in SMEM
>>> +and speedbin blown in the efuse combination.
>>> +The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
>>> +to provide the OPP framework with required information (existing HW 
>>> bitmap).
>>> +This is used to determine the voltage and frequency value for each OPP of
>>> +operating-points-v2 table when it is parsed by the OPP framework.
>>> +
>>> +Required properties:
>>> +
>>> +In 'cpus' nodes:
>>> +- operating-points-v2: Phandle to the operating-points-v2 table to use.
>>> +
>>> +In 'operating-points-v2' table:
>>> +- compatible: Should be
>>> +   - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996.
>>> +- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
>>> +   efuse registers that has information about the
>>> +   speedbin that is used to select the right frequency/voltage
>>> +   value pair.
>>> +   Please refer the for nvmem-cells
>>> +   bindings Documentation/devicetree/bindings/nvmem/nvmem.txt
>>> +   and also examples below.
>>
>> Sricharan is also working on adding these, just make sure you guys do the 
>> same
>> thing..
>>
 Right, i was adding a similar one for krait cores [1]. There is code common in 
the
 init sequence across both (little). Do you suggest to make them common ?

Regards,
 Sricharan

 [1] https://patchwork.kernel.org/patch/10261873/

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Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v4 13/14] dt-bindings: cpufreq: Document operating-points-v2-kryo-cpu

[Sricharan R]

Hi Viresh,

On 4/2/2018 3:00 PM, Viresh Kumar wrote:
> +Sricharan,
> 
> On 30-03-18, 00:26, Ilia Lin wrote:
>> In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996
>> that have KRYO processors, the CPU ferequencies subset and voltage value
>> of each OPP varies based on the silicon variant in use.
>> Qualcomm Technologies, Inc. Process Voltage Scaling Tables
>> defines the voltage and frequency value based on the msm-id in SMEM
>> and speedbin blown in the efuse combination.
>> The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
>> to provide the OPP framework with required information.
>> This is used to determine the voltage and frequency value for each OPP of
>> operating-points-v2 table when it is parsed by the OPP framework.
>>
>> This change adds documentation.
>>
>> Change-Id: I1953f652a48249fb516d175f0e965a9510cd4209
>> Signed-off-by: Ilia Lin 
>> ---
>>  .../devicetree/bindings/cpufreq/kryo-cpufreq.txt   | 693 
>> +
>>  1 file changed, 693 insertions(+)
>>  create mode 100644 
>> Documentation/devicetree/bindings/cpufreq/kryo-cpufreq.txt
>>
>> diff --git a/Documentation/devicetree/bindings/cpufreq/kryo-cpufreq.txt 
>> b/Documentation/devicetree/bindings/cpufreq/kryo-cpufreq.txt
> 
> This should really go in opp directory.
> 
>> new file mode 100644
>> index 000..20cef9d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/cpufreq/kryo-cpufreq.txt
>> @@ -0,0 +1,693 @@
>> +Qualcomm Technologies, Inc. KRYO CPUFreq and OPP bindings
>> +===
>> +
>> +In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996
>> +that have KRYO processors, the CPU ferequencies subset and voltage value
>> +of each OPP varies based on the silicon variant in use.
>> +Qualcomm Technologies, Inc. Process Voltage Scaling Tables
>> +defines the voltage and frequency value based on the msm-id in SMEM
>> +and speedbin blown in the efuse combination.
>> +The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
>> +to provide the OPP framework with required information (existing HW bitmap).
>> +This is used to determine the voltage and frequency value for each OPP of
>> +operating-points-v2 table when it is parsed by the OPP framework.
>> +
>> +Required properties:
>> +
>> +In 'cpus' nodes:
>> +- operating-points-v2: Phandle to the operating-points-v2 table to use.
>> +
>> +In 'operating-points-v2' table:
>> +- compatible: Should be
>> +- 'operating-points-v2-kryo-cpu' for apq8096 and msm8996.
>> +- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
>> +efuse registers that has information about the
>> +speedbin that is used to select the right frequency/voltage
>> +value pair.
>> +Please refer the for nvmem-cells
>> +bindings Documentation/devicetree/bindings/nvmem/nvmem.txt
>> +and also examples below.
> 
> Sricharan is also working on adding these, just make sure you guys do the same
> thing..
> 

 Right, i was adding a similar one for krait cores [1]. There is code common in 
the
 init sequence across both (little). Do you intent to make them common ?

Regards,
 Sricharan

 [1] https://patchwork.kernel.org/patch/10261873/


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Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v4 12/14] cpufreq: Add Kryo CPU scaling driver

[Sricharan R]

Hi Ilia,

> diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
> index 7f56fe5..71350e2 100644
> --- a/drivers/cpufreq/Kconfig.arm
> +++ b/drivers/cpufreq/Kconfig.arm
> @@ -134,6 +134,17 @@ config ARM_OMAP2PLUS_CPUFREQ
>   depends on ARCH_OMAP2PLUS
>   default ARCH_OMAP2PLUS
>  
> +config ARM_QCOM_CPUFREQ_KRYO
> + tristate "Qualcomm Technologies, Inc. Kryo based"

 Does this need to be 'tristate' ?. 'cpu-freq-dt' driver is already
 built as module.

<..>

> +
> +#include 
> +#include 
> +#include 
> +#include 

 Is io.h required ?

Regards,
  Sricharan

> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define MSM_ID_SMEM  137
> +#define SILVER_LEAD  0
> +#define GOLD_LEAD2
> +
> +enum _msm_id {
> + MSM8996V3 = 0xF6ul,
> + APQ8096V3 = 0x123ul,
> + MSM8996SG = 0x131ul,
> + APQ8096SG = 0x138ul,
> +};
> +
> +enum _msm8996_version {
> + MSM8996_V3,
> + MSM8996_SG,
> + NUM_OF_MSM8996_VERSIONS,
> +};
> +
> +static enum _msm8996_version __init qcom_cpufreq_kryo_get_msm_id(void)
> +{
> + size_t len;
> + u32 *msm_id;
> + enum _msm8996_version version;
> +
> + msm_id = qcom_smem_get(QCOM_SMEM_HOST_ANY, MSM_ID_SMEM, &len);
> + /* The first 4 bytes are format, next to them is the actual msm-id */
> + msm_id++;
> +
> + switch ((enum _msm_id)*msm_id) {
> + case MSM8996V3:
> + case APQ8096V3:
> + version = MSM8996_V3;
> + break;
> + case MSM8996SG:
> + case APQ8096SG:
> + version = MSM8996_SG;
> + break;
> + default:
> + version = NUM_OF_MSM8996_VERSIONS;
> + }
> +
> + return version;
> +}
> +
> +static int __init qcom_cpufreq_kryo_driver_init(void)
> +{
> + struct platform_device *pdev;
> + struct device *cpu_dev;
> + struct device_node *np;
> + struct nvmem_cell *speedbin_nvmem;
> + enum _msm8996_version msm8996_version;
> + u8 *speedbin;
> + size_t len;
> + int ret;
> + u32 versions;
> +
> + cpu_dev = get_cpu_device(SILVER_LEAD);
> + if (IS_ERR_OR_NULL(cpu_dev))
> + return PTR_ERR(cpu_dev);
> +
> + msm8996_version = qcom_cpufreq_kryo_get_msm_id();
> + if (NUM_OF_MSM8996_VERSIONS == msm8996_version) {
> + dev_err(cpu_dev, "Not Snapdragon 820/821!");
> + return -ENODEV;
> +}
> +
> + np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
> + if (IS_ERR_OR_NULL(np))
> + return PTR_ERR(np);
> +
> + if (!of_device_is_compatible(np, "operating-points-v2-kryo-cpu")) {
> + ret = -ENOENT;
> + goto free_np;
> + }
> +
> + speedbin_nvmem = of_nvmem_cell_get(np, NULL);
> + if (IS_ERR(speedbin_nvmem)) {
> + ret = PTR_ERR(speedbin_nvmem);
> + dev_err(cpu_dev, "Could not get nvmem cell: %d\n", ret);
> + goto free_np;
> + }
> +
> + speedbin = nvmem_cell_read(speedbin_nvmem, &len);
> +
> + switch (msm8996_version) {
> + case MSM8996_V3:
> + versions = 1 << (unsigned int)(*speedbin);
> + break;
> + case MSM8996_SG:
> + versions = 1 << ((unsigned int)(*speedbin) + 4);
> + break;
> + default:
> + BUG();
> + break;
> + }
> +
> + ret = PTR_ERR_OR_ZERO(dev_pm_opp_set_supported_hw(cpu_dev,&versions,1));
> + if (0 > ret)
> + goto free_np;
> +
> + cpu_dev = get_cpu_device(GOLD_LEAD);
> + ret = PTR_ERR_OR_ZERO(dev_pm_opp_set_supported_hw(cpu_dev,&versions,1));
> +
> + of_node_put(np);
> +
> + pdev = platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
> + if (IS_ERR(pdev)) {
> + return PTR_ERR(pdev);
> + }
> +
> + return 0;
> +
> +free_np:
> + of_node_put(np);
> +
> + return ret;
> +}
> +late_initcall(qcom_cpufreq_kryo_driver_init);
> +
> +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Kryo CPUfreq driver");
> +MODULE_LICENSE("GPL v2");
> 

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Re: [PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data

[sricharan]

On 2018-03-29 22:07, Richard Cochran wrote:

On Thu, Mar 29, 2018 at 09:37:15AM -0500, Andy Gross wrote:


Feel free to send your own contributions where you are adding the 
things that

are important to you.


You can count on it.  I am really happy that ipq4019 at least boots 
mainline.


BTW is there any hope of getting a working mainline DTS for the
ipq8062, ideally for the ap145_100 board?


  Yes, i will post another series for ipq806[2/4] updates and the 
corresponding

  boards after this.

Regards,
 Sricharan

Re: [PATCH v5 13/13] ARM: dts: ipq8074: Enable few peripherals for hk01 board

[Sricharan R]

Hi Bjorn,


On 3/27/2018 11:19 PM, Bjorn Andersson wrote:
> On Fri 23 Mar 03:18 PDT 2018, Sricharan R wrote:
> 
>> Reviewed-by: Abhishek Sahu 
>> Signed-off-by: Sricharan R 
>> ---
>>  arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 103 
>> ++
>>  1 file changed, 103 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts 
>> b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
>> index 6a838b5..dbca7ec 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
>> +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
>> @@ -21,6 +21,7 @@
>>  
>>  aliases {
>>  serial0 = &blsp1_uart5;
>> +serial1 = &serial_blsp2;
>>  };
>>  
>>  chosen {
>> @@ -41,6 +42,47 @@
>>  bias-disable;
>>  };
>>  };
>> +
>> + i2c_0_pins: i2c_0_pinmux {
>> +  mux {
>> +   pins = "gpio42", "gpio43";
>> +   function = "blsp1_i2c";
>> +   drive-strength = <8>;
>> +   bias-disable;
>> +  };
>> + };
>> +
>> + spi_0_pins: spi_0_pins {
>> +  mux {
>> +   pins = "gpio38", "gpio39", "gpio40", 
>> "gpio41";
>> +   function = "blsp0_spi";
>> +   drive-strength = <8>;
>> +   bias-disable;
>> +  };
>> + };
>> +
>> + hsuart_pins: hsuart_pins {
>> +  mux {
>> +   pins = "gpio46", "gpio47", "gpio48", 
>> "gpio49";
>> +   function = "blsp2_uart";
>> +   drive-strength = <8>;
>> +   bias-disable;
>> +  };
>> + };
>> +
>> + qpic_pins: qpic_pins {
>> +mux {
>> +   pins = "gpio1", "gpio3", "gpio4",
>> +  "gpio5", "gpio6", "gpio7",
>> +  "gpio8", "gpio10", "gpio11",
>> +  "gpio12", "gpio13", "gpio14",
>> +  "gpio15", "gpio16", "gpio17";
>> +   function = "qpic";
> 
> I would prefer that you move the pinmux part to the same dtsi that
> defines the nand and add the board specific pinconf (electrical
> properties) here. That way we limit the repetition between the board
> files.
> 

 sure. will do.

>> +   drive-strength = <8>;
>> +   bias-disable;
>> +  };
>> +};
>> +
>>  };
>>  
> 
> Other than that,
> 
> Acked-by: Bjorn Andersson 
> 

 Thanks. Again, thanks for your time and all the reviews.

Regards,
 Sricharan

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Re: [PATCH v5 12/13] ARM: dts: ipq8074: Add pcie nodes

[Sricharan R]

On 3/27/2018 11:16 PM, Bjorn Andersson wrote:
> On Fri 23 Mar 03:18 PDT 2018, Sricharan R wrote:
> 
>> The driver/phy support for ipq8074 is available now.
>> So enabling the nodes in DT.
>>
> 
> Acked-by: Bjorn Andersson 
> 

 Thanks.

Regards,
 Sricharan



> Regards,
> Bjorn
> 
>> Reviewed-by: Abhishek Sahu 
>> Signed-off-by: Sricharan R 
>> ---
>>  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 157 
>> +-
>>  1 file changed, 156 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi 
>> b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> index a8dbbf0..caf3485 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> @@ -24,7 +24,7 @@
>>  ranges = <0 0 0 0x>;
>>  compatible = "simple-bus";
>>  
>> -pinctrl@100 {
>> +tlmm: pinctrl@100 {
>>  compatible = "qcom,ipq8074-pinctrl";
>>  reg = <0x100 0x30>;
>>  interrupts = ;
>> @@ -229,6 +229,161 @@
>>  dma-names = "tx", "rx", "cmd";
>>  status = "disabled";
>>  };
>> +
>> +pcie_phy0: phy@86000 {
>> +compatible = "qcom,ipq8074-qmp-pcie-phy";
>> +reg = <0x86000 0x1000>;
>> +#phy-cells = <0>;
>> +clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
>> +clock-names = "pipe_clk";
>> +clock-output-names = "pcie20_phy0_pipe_clk";
>> +
>> +resets = <&gcc GCC_PCIE0_PHY_BCR>,
>> +<&gcc GCC_PCIE0PHY_PHY_BCR>;
>> +reset-names = "phy",
>> +  "common";
>> +status = "disabled";
>> +};
>> +
>> +pcie0: pci@2000 {
>> +compatible = "qcom,pcie-ipq8074";
>> +reg =  <0x2000 0xf1d
>> +0x2f20 0xa8
>> +0x8 0x2000
>> +0x2010 0x1000>;
>> +reg-names = "dbi", "elbi", "parf", "config";
>> +device_type = "pci";
>> +linux,pci-domain = <0>;
>> +bus-range = <0x00 0xff>;
>> +num-lanes = <1>;
>> +#address-cells = <3>;
>> +#size-cells = <2>;
>> +
>> +phys = <&pcie_phy0>;
>> +phy-names = "pciephy";
>> +
>> +ranges = <0x8100 0 0x2020 0x2020
>> +  0 0x10   /* downstream I/O */
>> +  0x8200 0 0x2030 0x2030
>> +  0 0xd0>; /* non-prefetchable memory */
>> +
>> +interrupts = ;
>> +interrupt-names = "msi";
>> +#interrupt-cells = <1>;
>> +interrupt-map-mask = <0 0 0 0x7>;
>> +interrupt-map = <0 0 0 1 &intc 0 75
>> + IRQ_TYPE_LEVEL_HIGH>, /* int_a */
>> +<0 0 0 2 &intc 0 78
>> + IRQ_TYPE_LEVEL_HIGH>, /* int_b */
>> +<0 0 0 3 &intc 0 79
>> + IRQ_TYPE_LEVEL_HIGH>, /* int_c */
>> +<0 0 0 4 &intc 0 83
>> + IRQ_TYPE_LEVEL_HIGH>; /* int_d */
>> +
>> +clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
>> + <&gcc GCC_PCIE0_AXI_M_CLK>,
>> + <&gcc GCC_PCIE0_AXI_S_CLK>,
>> + <&gcc GCC_PCIE0_AHB_CLK>,
>> + <&gcc GCC_PCIE0_AUX_CLK>;
>> +
>> +clock-names = "iface",
>> +  &quo

Re: [PATCH v5 11/13] ARM: dts: ipq8074: Add peripheral nodes

[Sricharan R]

On 3/27/2018 11:15 PM, Bjorn Andersson wrote:
> On Fri 23 Mar 03:18 PDT 2018, Sricharan R wrote:
>> +serial_blsp0: serial@78af000 {
> 
> Please try to have a single scheme for how you name your labels; this is
> serial0 or blsp1_uart1.
> 
> [..]
>> +i2c_0: i2c@78b6000 {
> 
> As in the previous patches, this is the 2nd i2c master in the SoC,
> please label it accordingly.

 ok, sure. will correct the label names uniformly.

Regards,
 Sricharan

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Re: [PATCH v5 10/13] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file

[Sricharan R]

Hi Bjorn,

On 3/27/2018 10:59 PM, Bjorn Andersson wrote:
> On Fri 23 Mar 03:18 PDT 2018, Sricharan R wrote:
> 
>> Reviewed-by: Abhishek Sahu 
>> Signed-off-by: Sricharan R 
>> ---
>>  arch/arm/boot/dts/Makefile  |  1 +
>>  arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 26 
>> +
>>  2 files changed, 27 insertions(+)
>>  create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index ae7f214..3b65e30 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -750,6 +750,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
>>  qcom-ipq4019-ap.dk04.1-c1.dtb \
>>  qcom-ipq4019-ap.dk04.1-c3.dtb \
>>  qcom-ipq4019-ap.dk07.1-c1.dtb \
>> +qcom-ipq4019-ap.dk07.1-c2.dtb \
>>  qcom-ipq8064-ap148.dtb \
>>  qcom-msm8660-surf.dtb \
>>  qcom-msm8960-cdp.dtb \
>> diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts 
>> b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
>> new file mode 100644
>> index 000..c1e909c
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
>> @@ -0,0 +1,26 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +// Copyright (c) 2018, The Linux Foundation. All rights reserved.
>> +
>> +#include "qcom-ipq4019-ap.dk07.1.dtsi"
>> +
>> +/ {
>> +model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C2";
> 
> compatible
> 

 ok.

> Apart from that you have my
> 
> Acked-by: Bjorn Andersson 
> 

 Thanks.

Regards,
 Sricharan

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Re: [PATCH v5 09/13] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file

[Sricharan R]

On 3/27/2018 10:52 PM, Bjorn Andersson wrote:
> On Fri 23 Mar 03:18 PDT 2018, Sricharan R wrote:
>> +#include "qcom-ipq4019-ap.dk07.1.dtsi"
>> +
>> +/ {
>> +model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C1";
> 
> Add compatible for the board.
> 

 ok.

Regards,
 Sricharan

-- 
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Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v5 08/13] ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data

[Sricharan R]

On 3/27/2018 10:50 PM, Bjorn Andersson wrote:
> On Fri 23 Mar 03:18 PDT 2018, Sricharan R wrote:
>> +#include "qcom-ipq4019.dtsi"
>> +#include 
>> +#include 
>> +
>> +/ {
>> +model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1";
>> +compatible = "qcom,ipq4019";
> 
> The board should set these, so you shouldn't need to specify them here.
> And you should be able to find a more specific compatible for the board.
> 

 ok. agree. As mentioned earlier, will correct the compatible in all boards.

>> +
> [..]
>> +qpic-nand@79b {
>> +status = "ok";
> 
> No pinmux for the qpic on these boards?
> 
 clearly missed it and was lucky that bootloader was doing it in this case.
 Will add it.

Regards,
 Sricharan

-- 
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Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v5 07/13] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file

[Sricharan R]

On 3/27/2018 10:44 PM, Bjorn Andersson wrote:
> On Fri 23 Mar 03:18 PDT 2018, Sricharan R wrote:
>> +#include "qcom-ipq4019-ap.dk04.1.dtsi"
>> +
>> +/ {
>> +model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C3";
> 
> Add a compatible to the board file.
> 

 ok.

> Also, things like alias would make sense to put in the board unless
> there's some restriction making every board having the same layout.
> 
>> +};

 hmm. i also thought of having them in board specific files initially.
 In this case, at-least the aliases for serial nodes seems to match across
 dk-01/04/07 base variants. But might be if we add something else in future
 it might not be common. Yeah, would move it to board specific files.

Regards,
 Sricharan

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Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v5 06/13] ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file

[Sricharan R]

Hi Bjorn,

On 3/27/2018 10:42 PM, Bjorn Andersson wrote:
> On Fri 23 Mar 03:18 PDT 2018, Sricharan R wrote:
>> +#include "qcom-ipq4019-ap.dk04.1.dtsi"
>> +
>> +/ {
>> +model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C1";
>> +
> 
> If this is the board and qcom-ipq4019-ap.dk04.1.dtsi is the platform
> file then the compatible should be here and not there. Also qcom,ipq4019
> is not an awesome compatible for a board file.
> 

 ok, agree. Will correct the compatible and move it here.

>> +soc {
>> +dma@7984000 {
>> +status = "ok";
>> +};
>> +
>> +qpic-nand@79b {
>> +pinctrl-0 = <&nand_pins>;
>> +pinctrl-names = "default";
>> +status = "ok";
>> +};
> 
> nand_pins defines the muxing and is defined in the other dtsi. So please
> move these pinctrl-* properties to the dtsi.
> 
> As long as the node is disabled the pinctrl state won't be applied
> anyways.
> 
> 
> If there are electrical properties that needs to be specified you can
> override the pinctrl state in the board specific file.
> 

 ok, understood. Will follow these conventions in rest of the places as well.

Regards,
 Sricharan

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Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v5 05/13] ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi

[Sricharan R]

On 3/27/2018 10:34 PM, Bjorn Andersson wrote:
> On Fri 23 Mar 03:18 PDT 2018, Sricharan R wrote:
>> +soc {
>> +pinctrl@100 {
>> +serial_0_pins: serial0_pinmux {
> 
> Please, no underscores in the node name.

 ok.

> 
>> +mux {
> 
> Fyi, you can put the pinctrl properties directly into the state node,
> omitting the "mux" level.
> 

 ok, will change.

>> +pins = "gpio16", "gpio17";
>> +function = "blsp_uart0";
>> +bias-disable;
>> +    };
>> +};
>> +
> 
> Apart from this the patch looks good.
 Thanks.

Regards,
 Sricharan

-- 
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Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v5 03/13] ARM: dts: ipq4019: Add a few peripheral nodes

[Sricharan R]

Hi Bjorn,
  Thanks a lot for all the reviews.

On 3/27/2018 10:20 PM, Bjorn Andersson wrote:
> On Fri 23 Mar 03:18 PDT 2018, Sricharan R wrote:
>> @@ -172,6 +180,22 @@
>>  clock-names = "core", "iface";
>>  #address-cells = <1>;
>>  #size-cells = <0>;
>> +dmas = <&blsp_dma 5>, <&blsp_dma 4>;
>> +dma-names = "rx", "tx";
>> +status = "disabled";
>> +};
>> +
>> +spi_1: spi@78b6000 { /* BLSP1 QUP2 */
>> +compatible = "qcom,spi-qup-v2.2.1";
>> +reg = <0x78b6000 0x600>;
>> +interrupts = ;
>> +clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
>> +<&gcc GCC_BLSP1_AHB_CLK>;
>> +clock-names = "core", "iface";
>> +#address-cells = <1>;
>> +#size-cells = <0>;
>> +dmas = <&blsp_dma 7>, <&blsp_dma 6>;
>> +dma-names = "rx", "tx";
>>  status = "disabled";
>>  };
>>  
>> @@ -184,9 +208,24 @@
>>  clock-names = "iface", "core";
>>  #address-cells = <1>;
>>  #size-cells = <0>;
>> +dmas = <&blsp_dma 9>, <&blsp_dma 8>;
>> +dma-names = "rx", "tx";
>>  status = "disabled";
>>  };
>>  
>> +i2c_1: i2c@78b8000 { /* BLSP1 QUP4 */
> 
> The label, comment and the core clock disagrees on which qup this is.
> 
> Label your nodes based on the SoC naming, not your board - as this will
> prevent a future board from using e.g. blsp1 qup2 as i2c (as you already
> used the label for that).

Sure. will fix. Infact this is QUP3.

> 
>> +compatible = "qcom,i2c-qup-v2.2.1";
>> +reg = <0x78b8000 0x600>;
>> +interrupts = ;
>> +clocks = <&gcc GCC_BLSP1_AHB_CLK>,
>> + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
> 
> QUP4?

 QUP3

> 
>> +clock-names = "iface", "core";
>> +#address-cells = <1>;
>> +#size-cells = <0>;
>> +dmas = <&blsp_dma 11>, <&blsp_dma 10>;
>> +dma-names = "rx", "tx";
>> +status = "disabled";
>> +};
> 
> Apart from this the patch looks good.

 Thanks.

Regards,
  Sricharan

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Re: [v9,04/15] clk: qcom: Add HFPLL driver

[sricharan]

On 2018-03-26 01:03, Craig Tatlor wrote:

This doesn't seem to work correctly with the higher clocks on 8974pro,
specifically 215040 hz or above, maybe its something to do with
being bigger than an unsigned long.

When i try to set any higher frequency it jumps down to 300mhz.



 Thanks for testing this series. Not sure i got dropped from the list.
 So i will check on this and come back.

Regards,
 Sricharan

Re: [PATCH v5 00/13] ARM: dts: ipq: updates to enable a few peripherals

[sricharan]

On 2018-03-24 07:47, Richard Cochran wrote:

On Fri, Mar 23, 2018 at 03:48:43PM +0530, Sricharan R wrote:

[v5]
* Fixed a minor comment that i missed earlier.


I tried booting this series with qcom_defconfig on my custom,
dk07-like board.  It works!


 Thanks.
 Can i take that as a Tested-by: Richard Cochran 


 on DK07 ?

Regards,
 Sricharan

[PATCH v5 00/13] ARM: dts: ipq: updates to enable a few peripherals

[Sricharan R]

[v5]
* Fixed a minor comment that i missed earlier.

[v4]
* Fixed more comments.
* Dropped reserved-memory nodes from board files as
  that might break existing users whose u-boot do not
  specify the fdt_high accordingly.
* Added chosen serial node for all boards to have
  the default serial console specified from DT.

[v3]
* Fixed minor comments from v2,
  https://www.spinics.net/lists/arm-kernel/msg641480.html

* Added Abhishek's review tags

[v2]
* Addressed all comments from Abhishek
* Removed dk01-c2 and dk04-c5 spinand based boards
  as support for spinand is not complete
* Based all patches on top of Andy's for-next branch

[V1]
* https://www.spinics.net/lists/arm-kernel/msg631318.html

Sricharan R (13):
  firmware: qcom: scm: Add ipq4019 soc compatible
  ARM: dts: ipq4019: Add a default chosen node
  ARM: dts: ipq4019: Add a few peripheral nodes
  ARM: dts: ipq4019: Change the max opp frequency
  ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi
  ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file
  ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file
  ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data
  ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file
  ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file
  ARM: dts: ipq8074: Add peripheral nodes
  ARM: dts: ipq8074: Add pcie nodes
  ARM: dts: ipq8074: Enable few peripherals for hk01 board

 .../devicetree/bindings/firmware/qcom,scm.txt  |   3 +-
 arch/arm/boot/dts/Makefile |   4 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi  |   8 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts|  20 ++
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts|   8 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi  | 115 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts|  65 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts|  26 ++
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi  |  68 ++
 arch/arm/boot/dts/qcom-ipq4019.dtsi| 140 ++-
 arch/arm64/boot/dts/qcom/ipq8074-hk01.dts  | 103 
 arch/arm64/boot/dts/qcom/ipq8074.dtsi  | 262 -
 drivers/firmware/qcom_scm.c|   3 +
 13 files changed, 820 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi

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[PATCH v5 01/13] firmware: qcom: scm: Add ipq4019 soc compatible

[Sricharan R]

Add the compatible for ipq4019.
This does not need clocks to do scm calls.

Reviewed-by: Rob Herring 
Signed-off-by: Sricharan R 
---
 Documentation/devicetree/bindings/firmware/qcom,scm.txt | 3 ++-
 drivers/firmware/qcom_scm.c | 3 +++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt 
b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
index 7b40054..fcf6979 100644
--- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
@@ -11,9 +11,10 @@ Required properties:
  * "qcom,scm-msm8660" for MSM8660 platforms
  * "qcom,scm-msm8690" for MSM8690 platforms
  * "qcom,scm-msm8996" for MSM8996 platforms
+ * "qcom,scm-ipq4019" for IPQ4019 platforms
  * "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc)
 - clocks: One to three clocks may be required based on compatible.
- * No clock required for "qcom,scm-msm8996"
+ * No clock required for "qcom,scm-msm8996", "qcom,scm-ipq4019"
  * Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and 
"qcom,scm-msm8960"
  * Core, iface, and bus clocks required for "qcom,scm"
 - clock-names: Must contain "core" for the core clock, "iface" for the 
interface
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 5a7d6930..e778af7 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -603,6 +603,9 @@ static void qcom_scm_shutdown(struct platform_device *pdev)
{ .compatible = "qcom,scm-msm8996",
  .data = NULL, /* no clocks */
},
+   { .compatible = "qcom,scm-ipq4019",
+ .data = NULL, /* no clocks */
+   },
{ .compatible = "qcom,scm",
  .data = (void *)(SCM_HAS_CORE_CLK
   | SCM_HAS_IFACE_CLK
-- 
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[PATCH v5 02/13] ARM: dts: ipq4019: Add a default chosen node

[Sricharan R]

Add a 'chosen' node to select the serial console.
This is needed when bootloaders do not pass the
'console=' bootargs.

Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 8 
 arch/arm/boot/dts/qcom-ipq4019.dtsi   | 2 +-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index e413b21e..ef8d8c8 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -20,6 +20,14 @@
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
compatible = "qcom,ipq4019";
 
+   aliases {
+   serial0 = &blsp1_uart1;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
soc {
rng@22000 {
status = "ok";
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 10d112a..ea9202a 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -256,7 +256,7 @@
 regulator;
 };
 
-   serial@78af000 {
+   blsp1_uart1: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
interrupts = <0 107 0>;
-- 
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Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data

[sricharan]

On 2018-03-23 03:02, Richard Cochran wrote:
On Thu, Mar 22, 2018 at 06:35:48PM +0530, sricha...@codeaurora.org 
wrote:

  Meanwhile i just posted a v4 (CCed you), is it possible that
  i can have test feedback ? . That will be great.


I don't have any DK in hand, but I do have a custom design most
similar to the DK7.  I'll gladly try to boot it with your series.

Just to be clear:  You are running pure mainline with absolutely no
out-of-tree patches or other modifications, right?


 Yes, mainline (4.16-rc6), plus my patches, pushed it here as well [1]
 Btw, posted v5 to fix a minor thing that i missed earlier.

 [1] https://github.com/sricharanaz/kernel/tree/ipq_test

Regards,
 Sricharan

[PATCH v5 03/13] ARM: dts: ipq4019: Add a few peripheral nodes

[Sricharan R]

Now with the driver updates for some peripherals being there,
add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
peripheral support.

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 134 
 1 file changed, 134 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index ea9202a..f985518 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -25,7 +25,9 @@
 
aliases {
spi0 = &spi_0;
+   spi1 = &spi_1;
i2c0 = &i2c_0;
+   i2c1 = &i2c_1;
};
 
cpus {
@@ -104,6 +106,12 @@
};
};
 
+   firmware {
+   scm {
+   compatible = "qcom,scm-ipq4019";
+   };
+   };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <1 2 0xf08>,
@@ -172,6 +180,22 @@
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
+   dmas = <&blsp_dma 5>, <&blsp_dma 4>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
+
+   spi_1: spi@78b6000 { /* BLSP1 QUP2 */
+   compatible = "qcom,spi-qup-v2.2.1";
+   reg = <0x78b6000 0x600>;
+   interrupts = ;
+   clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
+   <&gcc GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   dmas = <&blsp_dma 7>, <&blsp_dma 6>;
+   dma-names = "rx", "tx";
status = "disabled";
};
 
@@ -184,9 +208,24 @@
clock-names = "iface", "core";
#address-cells = <1>;
#size-cells = <0>;
+   dmas = <&blsp_dma 9>, <&blsp_dma 8>;
+   dma-names = "rx", "tx";
status = "disabled";
};
 
+   i2c_1: i2c@78b8000 { /* BLSP1 QUP4 */
+   compatible = "qcom,i2c-qup-v2.2.1";
+   reg = <0x78b8000 0x600>;
+   interrupts = ;
+   clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+   clock-names = "iface", "core";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   dmas = <&blsp_dma 11>, <&blsp_dma 10>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
 
cryptobam: dma@8e04000 {
compatible = "qcom,bam-v1.7.0";
@@ -293,6 +332,101 @@
reg = <0x4ab000 0x4>;
};
 
+   pcie0: pci@4000 {
+   compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
+   reg =  <0x4000 0xf1d
+   0x4f20 0xa8
+   0x8 0x2000
+   0x4010 0x1000>;
+   reg-names = "dbi", "elbi", "parf", "config";
+   device_type = "pci";
+   linux,pci-domain = <0>;
+   bus-range = <0x00 0xff>;
+   num-lanes = <1>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+
+   ranges = <0x8100 0 0x4020 0x4020 0 
0x0010
+ 0x8200 0 0x4800 0x4800 0 
0x1000>;
+
+   interrupts = ;
+   interrupt-names = "msi";
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0x7>;
+   interrupt-map = <0 0 0 1 &intc 0 142 
IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+   <0 0 0 2 &intc 0 143 
IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+  

[PATCH v5 04/13] ARM: dts: ipq4019: Change the max opp frequency

[Sricharan R]

The max opp frequency is 716MHZ. So update that.

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index f985518..1c3b0ff 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -47,7 +47,7 @@
48000   110
20  110
50  110
-   666000  110
+   716000  110
>;
clock-latency = <256000>;
};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v5 05/13] ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi

[Sricharan R]

Add the common parts for the dk04 boards.

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 115 ++
 arch/arm/boot/dts/qcom-ipq4019.dtsi   |   2 +-
 2 files changed, 116 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
new file mode 100644
index 000..7c5d717
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019.dtsi"
+#include 
+#include 
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
+   compatible = "qcom,ipq4019";
+
+   aliases {
+   serial0 = &blsp1_uart1;
+   serial1 = &blsp1_uart2;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   memory {
+   device_type = "memory";
+   reg = <0x8000 0x1000>; /* 256MB */
+   };
+
+   soc {
+   pinctrl@100 {
+   serial_0_pins: serial0_pinmux {
+   mux {
+   pins = "gpio16", "gpio17";
+   function = "blsp_uart0";
+   bias-disable;
+   };
+   };
+
+   serial_1_pins: serial1_pinmux {
+   mux {
+   pins = "gpio8", "gpio9",
+   "gpio10", "gpio11";
+   function = "blsp_uart1";
+   bias-disable;
+   };
+   };
+
+   spi_0_pins: spi_0_pinmux {
+   pinmux {
+   function = "blsp_spi0";
+   pins = "gpio13", "gpio14", "gpio15";
+   bias-disable;
+   };
+   pinmux_cs {
+   function = "gpio";
+   pins = "gpio12";
+   bias-disable;
+   output-high;
+   };
+   };
+
+   i2c_0_pins: i2c_0_pinmux {
+   mux {
+   pins = "gpio20", "gpio21";
+   function = "blsp_i2c0";
+   bias-disable;
+   };
+   };
+
+   nand_pins: nand_pins {
+   mux {
+   pins = "gpio53", "gpio55", "gpio56",
+   "gpio57", "gpio58", "gpio59",
+   "gpio60", "gpio62", "gpio63",
+   "gpio64", "gpio65", "gpio66",
+   "gpio67", "gpio68", "gpio69";
+   function = "qpic";
+   };
+   };
+   };
+
+   serial@78af000 {
+   pinctrl-0 = <&serial_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   serial@78b {
+   pinctrl-0 = <&serial_1_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   dma@7884000 {
+   status = "ok";
+   };
+
+   spi@78b5000 { /* BLSP1 QUP1 */
+   pinctrl-0 = <&spi_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   cs-gpios = <&tlmm 12 0>;
+
+   m25p80@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+

[PATCH v5 08/13] ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data

[Sricharan R]

Add the common data for all dk07 based boards.

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 69 +++
 1 file changed, 69 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi

diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
new file mode 100644
index 000..4cc519f
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019.dtsi"
+#include 
+#include 
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1";
+   compatible = "qcom,ipq4019";
+
+   memory {
+   device_type = "memory";
+   reg = <0x8000 0x2000>; /* 512MB */
+   };
+
+   aliases {
+   serial0 = &blsp1_uart1;
+   serial1 = &blsp1_uart2;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   soc {
+   pinctrl@100 {
+   serial_0_pins: serial0_pinmux {
+   mux {
+   pins = "gpio16", "gpio17";
+   function = "blsp_uart0";
+   bias-disable;
+   };
+   };
+
+   i2c_0_pins: i2c_0_pinmux {
+   mux {
+   pins = "gpio20", "gpio21";
+   function = "blsp_i2c0";
+   bias-disable;
+   };
+   };
+   };
+
+   serial@78af000 {
+   pinctrl-0 = <&serial_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   dma@7884000 {
+   status = "ok";
+   };
+
+   i2c@78b7000 { /* BLSP1 QUP2 */
+   pinctrl-0 = <&i2c_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   dma@7984000 {
+   status = "ok";
+   };
+
+   qpic-nand@79b {
+   status = "ok";
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v5 11/13] ARM: dts: ipq8074: Add peripheral nodes

[Sricharan R]

Add serial, i2c, bam, spi, qpic peripheral nodes.

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 105 ++
 1 file changed, 105 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi 
b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 2bc5dec..a8dbbf0 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -124,6 +124,111 @@
clock-names = "core", "iface";
status = "disabled";
};
+
+   blsp_dma: dma@7884000 {
+   compatible = "qcom,bam-v1.7.0";
+   reg = <0x7884000 0x2b000>;
+   interrupts = ;
+   clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+   clock-names = "bam_clk";
+   #dma-cells = <1>;
+   qcom,ee = <0>;
+   };
+
+   serial_blsp0: serial@78af000 {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x78af000 0x200>;
+   interrupts = ;
+   clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
+<&gcc GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   status = "disabled";
+   };
+
+   serial_blsp2: serial@78b1000 {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x78b1000 0x200>;
+   interrupts = ;
+   clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
+   <&gcc GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   dmas = <&blsp_dma 4>,
+   <&blsp_dma 5>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+   };
+
+   spi_0: spi@78b5000 {
+   compatible = "qcom,spi-qup-v2.2.1";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x78b5000 0x600>;
+   interrupts = ;
+   spi-max-frequency = <5000>;
+   clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+   <&gcc GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   dmas = <&blsp_dma 12>, <&blsp_dma 13>;
+   dma-names = "tx", "rx";
+   status = "disabled";
+   };
+
+   i2c_0: i2c@78b6000 {
+   compatible = "qcom,i2c-qup-v2.2.1";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x78b6000 0x600>;
+   interrupts = ;
+   clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+   <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+   clock-names = "iface", "core";
+   clock-frequency = <40>;
+   dmas = <&blsp_dma 15>, <&blsp_dma 14>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
+
+   i2c_1: i2c@78b7000 {
+   compatible = "qcom,i2c-qup-v2.2.1";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0x78b7000 0x600>;
+   interrupts = ;
+   clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+   <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
+   clock-names = "iface", "core";
+   clock-frequency = <10>;
+   dmas = <&blsp_dma 17>, <&blsp_dma 16>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
+
+   qpic_bam: dma@7984000 {
+   compatible = "qcom,bam-v1.7.0";
+   reg = <0x7984000 0x1a000>;
+   interrupts = ;
+   clocks = <&gcc 

[PATCH v5 13/13] ARM: dts: ipq8074: Enable few peripherals for hk01 board

[Sricharan R]

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 103 ++
 1 file changed, 103 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts 
b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
index 6a838b5..dbca7ec 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -21,6 +21,7 @@
 
aliases {
serial0 = &blsp1_uart5;
+   serial1 = &serial_blsp2;
};
 
chosen {
@@ -41,6 +42,47 @@
bias-disable;
};
};
+
+i2c_0_pins: i2c_0_pinmux {
+ mux {
+  pins = "gpio42", "gpio43";
+  function = "blsp1_i2c";
+  drive-strength = <8>;
+  bias-disable;
+ };
+};
+
+spi_0_pins: spi_0_pins {
+ mux {
+  pins = "gpio38", "gpio39", "gpio40", 
"gpio41";
+  function = "blsp0_spi";
+  drive-strength = <8>;
+  bias-disable;
+ };
+};
+
+hsuart_pins: hsuart_pins {
+ mux {
+  pins = "gpio46", "gpio47", "gpio48", 
"gpio49";
+  function = "blsp2_uart";
+  drive-strength = <8>;
+  bias-disable;
+ };
+};
+
+qpic_pins: qpic_pins {
+   mux {
+  pins = "gpio1", "gpio3", "gpio4",
+ "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio10", "gpio11",
+ "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17";
+  function = "qpic";
+  drive-strength = <8>;
+  bias-disable;
+ };
+   };
+
};
 
serial@78b3000 {
@@ -48,5 +90,66 @@
pinctrl-names = "default";
status = "ok";
};
+
+   spi@78b5000 {
+pinctrl-0 = <&spi_0_pins>;
+pinctrl-names = "default";
+status = "ok";
+
+m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q128a11", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <5000>;
+};
+   };
+
+   serial@78b1000 {
+pinctrl-0 = <&hsuart_pins>;
+pinctrl-names = "default";
+status = "ok";
+   };
+
+   i2c@78b6000 {
+pinctrl-0 = <&i2c_0_pins>;
+pinctrl-names = "default";
+status = "ok";
+   };
+
+   dma@7984000 {
+status = "ok";
+   };
+
+   nand@79b {
+   pinctrl-0 = <&qpic_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+
+   nand@0 {
+   reg = <0>;
+   nand-ecc-strength = <4>;
+   nand-ecc-step-size = <512>;
+   nand-bus-width = <8>;
+   };
+   };
+
+   phy@86000 {
+  

[PATCH v5 12/13] ARM: dts: ipq8074: Add pcie nodes

[Sricharan R]

The driver/phy support for ipq8074 is available now.
So enabling the nodes in DT.

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 157 +-
 1 file changed, 156 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi 
b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index a8dbbf0..caf3485 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -24,7 +24,7 @@
ranges = <0 0 0 0x>;
compatible = "simple-bus";
 
-   pinctrl@100 {
+   tlmm: pinctrl@100 {
compatible = "qcom,ipq8074-pinctrl";
reg = <0x100 0x30>;
interrupts = ;
@@ -229,6 +229,161 @@
dma-names = "tx", "rx", "cmd";
status = "disabled";
};
+
+   pcie_phy0: phy@86000 {
+   compatible = "qcom,ipq8074-qmp-pcie-phy";
+   reg = <0x86000 0x1000>;
+   #phy-cells = <0>;
+   clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
+   clock-names = "pipe_clk";
+   clock-output-names = "pcie20_phy0_pipe_clk";
+
+   resets = <&gcc GCC_PCIE0_PHY_BCR>,
+   <&gcc GCC_PCIE0PHY_PHY_BCR>;
+   reset-names = "phy",
+ "common";
+   status = "disabled";
+   };
+
+   pcie0: pci@2000 {
+   compatible = "qcom,pcie-ipq8074";
+   reg =  <0x2000 0xf1d
+   0x2f20 0xa8
+   0x8 0x2000
+   0x2010 0x1000>;
+   reg-names = "dbi", "elbi", "parf", "config";
+   device_type = "pci";
+   linux,pci-domain = <0>;
+   bus-range = <0x00 0xff>;
+   num-lanes = <1>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+
+   phys = <&pcie_phy0>;
+   phy-names = "pciephy";
+
+   ranges = <0x8100 0 0x2020 0x2020
+ 0 0x10   /* downstream I/O */
+ 0x8200 0 0x2030 0x2030
+ 0 0xd0>; /* non-prefetchable memory */
+
+   interrupts = ;
+   interrupt-names = "msi";
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0x7>;
+   interrupt-map = <0 0 0 1 &intc 0 75
+IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+   <0 0 0 2 &intc 0 78
+IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+   <0 0 0 3 &intc 0 79
+IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+   <0 0 0 4 &intc 0 83
+IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+   clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
+<&gcc GCC_PCIE0_AXI_M_CLK>,
+<&gcc GCC_PCIE0_AXI_S_CLK>,
+<&gcc GCC_PCIE0_AHB_CLK>,
+<&gcc GCC_PCIE0_AUX_CLK>;
+
+   clock-names = "iface",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "aux";
+   resets = <&gcc GCC_PCIE0_PIPE_ARES>,
+<&gcc GCC_PCIE0_SLEEP_ARES>,
+<&gcc GCC_PCIE0_CORE_STICKY_ARES>,
+<&gcc GCC_PCIE0_AXI_MASTER_ARES>,
+<&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
+<&gcc GCC_PCIE0_AHB_ARES>,
+<&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
+   reset-names = "pipe",
+ "sleep

[PATCH v5 09/13] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file

[Sricharan R]

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 65 +
 2 files changed, 66 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index cf083c9..ae7f214 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -749,6 +749,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c3.dtb \
+   qcom-ipq4019-ap.dk07.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
new file mode 100644
index 000..dab052c
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk07.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C1";
+
+   soc {
+   pci@4000 {
+   status = "ok";
+   perst-gpio = <&tlmm 38 0x1>;
+   };
+
+   spi@78b6000 { /* BLSP1 QUP2 */
+   status = "ok";
+   };
+
+   pinctrl@100 {
+   serial_1_pins: serial1_pinmux {
+   mux {
+   pins = "gpio8", "gpio9",
+   "gpio10", "gpio11";
+   function = "blsp_uart1";
+   bias-disable;
+   };
+   };
+
+   spi_0_pins: spi_0_pinmux {
+   pinmux {
+   function = "blsp_spi0";
+   pins = "gpio13", "gpio14", "gpio15";
+   bias-disable;
+   };
+   pinmux_cs {
+   function = "gpio";
+   pins = "gpio12";
+   bias-disable;
+   output-high;
+   };
+   };
+   };
+
+   serial@78b {
+   pinctrl-0 = <&serial_1_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+
+   spi@78b5000 { /* BLSP1 QUP1 */
+   pinctrl-0 = <&spi_0_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   cs-gpios = <&tlmm 12 0>;
+
+   m25p80@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   reg = <0>;
+   compatible = "n25q128a11";
+   spi-max-frequency = <2400>;
+   };
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v5 10/13] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file

[Sricharan R]

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 26 +
 2 files changed, 27 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index ae7f214..3b65e30 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -750,6 +750,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq4019-ap.dk07.1-c1.dtb \
+   qcom-ipq4019-ap.dk07.1-c2.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
new file mode 100644
index 000..c1e909c
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk07.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C2";
+
+   soc {
+   pinctrl@100 {
+   serial_1_pins: serial1_pinmux {
+   mux {
+   pins = "gpio8", "gpio9";
+   function = "blsp_uart1";
+   bias-disable;
+   };
+   };
+   };
+
+   serial@78b {
+   pinctrl-0 = <&serial_1_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v5 07/13] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file

[Sricharan R]

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/Makefile  | 1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 8 
 2 files changed, 9 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b6c62c6..cf083c9 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -748,6 +748,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
+   qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
new file mode 100644
index 000..0843523
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C3";
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

[PATCH v5 06/13] ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file

[Sricharan R]

Reviewed-by: Abhishek Sahu 
Signed-off-by: Sricharan R 
---
 arch/arm/boot/dts/Makefile  |  1 +
 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 20 
 2 files changed, 21 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index ade7a38..b6c62c6 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -747,6 +747,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-ifc6540.dtb \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
+   qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts 
b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
new file mode 100644
index 000..526b7f8
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C1";
+
+   soc {
+   dma@7984000 {
+   status = "ok";
+   };
+
+   qpic-nand@79b {
+   pinctrl-0 = <&nand_pins>;
+   pinctrl-names = "default";
+   status = "ok";
+   };
+   };
+};
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of 
Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH v3 04/13] ARM: dts: ipq4019: Update ipq4019-dk01.1 board data

[sricharan]

On 2018-03-21 20:37, Richard Cochran wrote:
On Wed, Mar 21, 2018 at 02:40:43PM +0530, sricha...@codeaurora.org 
wrote:

 Yes, i saw that it was booting out of mainline.
 Both DK01 and DK04 boards boots out of mainline.


Well, that is good news.

Which kernel config did you use?


  qcom_defconfig.
  Meanwhile i just posted a v4 (CCed you), is it possible that
  i can have test feedback ? . That will be great.

Regards,
 Sricharan