Re: [PATCH] clk: socfpga: allow for multiple parents on Arria10 periph clocks

[Dinh Nguyen]

On 02/22/2016 03:50 PM, Stephen Boyd wrote:
> 
> Oops, spoke too soon:
> 
> drivers/clk/socfpga/clk-periph-a10.c:113:27: warning: incorrect type in 
> assignment (different base types)
> drivers/clk/socfpga/clk-periph-a10.c:113:27:expected char const *const 
> *[assigned] parent_names
> drivers/clk/socfpga/clk-periph-a10.c:113:27:got char const *( * 
> )[5]
>   CC  drivers/clk/socfpga/clk-periph-a10.o
> drivers/clk/socfpga/clk-periph-a10.c: In function ‘__socfpga_periph_init’:
> drivers/clk/socfpga/clk-periph-a10.c:113:20: warning: assignment from 
> incompatible pointer type [enabled by default]
> 

Sorry about that. V2 is inbound.

Thanks,
Dinh

Re: [PATCH] clk: socfpga: allow for multiple parents on Arria10 periph clocks

[Dinh Nguyen]

On 02/22/2016 03:50 PM, Stephen Boyd wrote:
> 
> Oops, spoke too soon:
> 
> drivers/clk/socfpga/clk-periph-a10.c:113:27: warning: incorrect type in 
> assignment (different base types)
> drivers/clk/socfpga/clk-periph-a10.c:113:27:expected char const *const 
> *[assigned] parent_names
> drivers/clk/socfpga/clk-periph-a10.c:113:27:got char const *( * 
> )[5]
>   CC  drivers/clk/socfpga/clk-periph-a10.o
> drivers/clk/socfpga/clk-periph-a10.c: In function ‘__socfpga_periph_init’:
> drivers/clk/socfpga/clk-periph-a10.c:113:20: warning: assignment from 
> incompatible pointer type [enabled by default]
> 

Sorry about that. V2 is inbound.

Thanks,
Dinh

Re: [PATCH] clk: socfpga: allow for multiple parents on Arria10 periph clocks

[kbuild test robot]

Hi Dinh,

[auto build test WARNING on clk/clk-next]
[also build test WARNING on v4.5-rc5 next-20160222]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improving the system]

url:
https://github.com/0day-ci/linux/commits/dinguyen-opensource-altera-com/clk-socfpga-allow-for-multiple-parents-on-Arria10-periph-clocks/20160223-043710
base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: arm-multi_v7_defconfig (attached as .config)
reproduce:
wget 
https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross
 -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm 

All warnings (new ones prefixed by >>):

   drivers/clk/socfpga/clk-periph-a10.c: In function '__socfpga_periph_init':
>> drivers/clk/socfpga/clk-periph-a10.c:113:20: warning: assignment from 
>> incompatible pointer type
 init.parent_names = _name;
   ^

vim +113 drivers/clk/socfpga/clk-periph-a10.c

5343325f Dinh Nguyen 2015-05-19   97periph_clk->div_reg = NULL;
5343325f Dinh Nguyen 2015-05-19   98}
5343325f Dinh Nguyen 2015-05-19   99  
5343325f Dinh Nguyen 2015-05-19  100rc = of_property_read_u32(node, 
"fixed-divider", _div);
5343325f Dinh Nguyen 2015-05-19  101if (rc)
5343325f Dinh Nguyen 2015-05-19  102periph_clk->fixed_div = 0;
5343325f Dinh Nguyen 2015-05-19  103else
5343325f Dinh Nguyen 2015-05-19  104periph_clk->fixed_div = 
fixed_div;
5343325f Dinh Nguyen 2015-05-19  105  
5343325f Dinh Nguyen 2015-05-19  106of_property_read_string(node, 
"clock-output-names", _name);
5343325f Dinh Nguyen 2015-05-19  107  
5343325f Dinh Nguyen 2015-05-19  108init.name = clk_name;
5343325f Dinh Nguyen 2015-05-19  109init.ops = ops;
5343325f Dinh Nguyen 2015-05-19  110init.flags = 0;
5343325f Dinh Nguyen 2015-05-19  111  
aaf2a8b5 Dinh Nguyen 2016-02-22  112init.num_parents = 
of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
5343325f Dinh Nguyen 2015-05-19 @113init.parent_names = _name;
5343325f Dinh Nguyen 2015-05-19  114  
5343325f Dinh Nguyen 2015-05-19  115periph_clk->hw.hw.init = 
5343325f Dinh Nguyen 2015-05-19  116  
5343325f Dinh Nguyen 2015-05-19  117clk = clk_register(NULL, 
_clk->hw.hw);
5343325f Dinh Nguyen 2015-05-19  118if (WARN_ON(IS_ERR(clk))) {
5343325f Dinh Nguyen 2015-05-19  119kfree(periph_clk);
5343325f Dinh Nguyen 2015-05-19  120return;
5343325f Dinh Nguyen 2015-05-19  121}

:: The code at line 113 was first introduced by commit
:: 5343325ff3dd299f459fa9dacbd95dca5c9bf215 clk: socfpga: add a clock 
driver for the Arria 10 platform

:: TO: Dinh Nguyen 
:: CC: Stephen Boyd 

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: Binary data

Re: [PATCH] clk: socfpga: allow for multiple parents on Arria10 periph clocks

[kbuild test robot]

Hi Dinh,

[auto build test WARNING on clk/clk-next]
[also build test WARNING on v4.5-rc5 next-20160222]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improving the system]

url:
https://github.com/0day-ci/linux/commits/dinguyen-opensource-altera-com/clk-socfpga-allow-for-multiple-parents-on-Arria10-periph-clocks/20160223-043710
base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: arm-multi_v7_defconfig (attached as .config)
reproduce:
wget 
https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross
 -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm 

All warnings (new ones prefixed by >>):

   drivers/clk/socfpga/clk-periph-a10.c: In function '__socfpga_periph_init':
>> drivers/clk/socfpga/clk-periph-a10.c:113:20: warning: assignment from 
>> incompatible pointer type
 init.parent_names = _name;
   ^

vim +113 drivers/clk/socfpga/clk-periph-a10.c

5343325f Dinh Nguyen 2015-05-19   97periph_clk->div_reg = NULL;
5343325f Dinh Nguyen 2015-05-19   98}
5343325f Dinh Nguyen 2015-05-19   99  
5343325f Dinh Nguyen 2015-05-19  100rc = of_property_read_u32(node, 
"fixed-divider", _div);
5343325f Dinh Nguyen 2015-05-19  101if (rc)
5343325f Dinh Nguyen 2015-05-19  102periph_clk->fixed_div = 0;
5343325f Dinh Nguyen 2015-05-19  103else
5343325f Dinh Nguyen 2015-05-19  104periph_clk->fixed_div = 
fixed_div;
5343325f Dinh Nguyen 2015-05-19  105  
5343325f Dinh Nguyen 2015-05-19  106of_property_read_string(node, 
"clock-output-names", _name);
5343325f Dinh Nguyen 2015-05-19  107  
5343325f Dinh Nguyen 2015-05-19  108init.name = clk_name;
5343325f Dinh Nguyen 2015-05-19  109init.ops = ops;
5343325f Dinh Nguyen 2015-05-19  110init.flags = 0;
5343325f Dinh Nguyen 2015-05-19  111  
aaf2a8b5 Dinh Nguyen 2016-02-22  112init.num_parents = 
of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
5343325f Dinh Nguyen 2015-05-19 @113init.parent_names = _name;
5343325f Dinh Nguyen 2015-05-19  114  
5343325f Dinh Nguyen 2015-05-19  115periph_clk->hw.hw.init = 
5343325f Dinh Nguyen 2015-05-19  116  
5343325f Dinh Nguyen 2015-05-19  117clk = clk_register(NULL, 
_clk->hw.hw);
5343325f Dinh Nguyen 2015-05-19  118if (WARN_ON(IS_ERR(clk))) {
5343325f Dinh Nguyen 2015-05-19  119kfree(periph_clk);
5343325f Dinh Nguyen 2015-05-19  120return;
5343325f Dinh Nguyen 2015-05-19  121}

:: The code at line 113 was first introduced by commit
:: 5343325ff3dd299f459fa9dacbd95dca5c9bf215 clk: socfpga: add a clock 
driver for the Arria 10 platform

:: TO: Dinh Nguyen 
:: CC: Stephen Boyd 

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: Binary data

Re: [PATCH] clk: socfpga: allow for multiple parents on Arria10 periph clocks

[Stephen Boyd]

On 02/22, Stephen Boyd wrote:
> On 02/22, dingu...@opensource.altera.com wrote:
> > From: Dinh Nguyen 
> > 
> > There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can
> > have multiple parents. Fix up the __socfpga_periph_init() to call
> > of_clk_parent_fill() that will return the appropriate number of parents.
> > 
> > Also, update __socfpga_gate_init() to call of_clk_parent_fill() helper
> > function.
> > 
> > Signed-off-by: Dinh Nguyen 
> > ---
> 
> Applied to clk-next
> 

Oops, spoke too soon:

drivers/clk/socfpga/clk-periph-a10.c:113:27: warning: incorrect type in 
assignment (different base types)
drivers/clk/socfpga/clk-periph-a10.c:113:27:expected char const *const 
*[assigned] parent_names
drivers/clk/socfpga/clk-periph-a10.c:113:27:got char const *( * 
)[5]
  CC  drivers/clk/socfpga/clk-periph-a10.o
drivers/clk/socfpga/clk-periph-a10.c: In function ‘__socfpga_periph_init’:
drivers/clk/socfpga/clk-periph-a10.c:113:20: warning: assignment from 
incompatible pointer type [enabled by default]


-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH] clk: socfpga: allow for multiple parents on Arria10 periph clocks

[Stephen Boyd]

On 02/22, Stephen Boyd wrote:
> On 02/22, dingu...@opensource.altera.com wrote:
> > From: Dinh Nguyen 
> > 
> > There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can
> > have multiple parents. Fix up the __socfpga_periph_init() to call
> > of_clk_parent_fill() that will return the appropriate number of parents.
> > 
> > Also, update __socfpga_gate_init() to call of_clk_parent_fill() helper
> > function.
> > 
> > Signed-off-by: Dinh Nguyen 
> > ---
> 
> Applied to clk-next
> 

Oops, spoke too soon:

drivers/clk/socfpga/clk-periph-a10.c:113:27: warning: incorrect type in 
assignment (different base types)
drivers/clk/socfpga/clk-periph-a10.c:113:27:expected char const *const 
*[assigned] parent_names
drivers/clk/socfpga/clk-periph-a10.c:113:27:got char const *( * 
)[5]
  CC  drivers/clk/socfpga/clk-periph-a10.o
drivers/clk/socfpga/clk-periph-a10.c: In function ‘__socfpga_periph_init’:
drivers/clk/socfpga/clk-periph-a10.c:113:20: warning: assignment from 
incompatible pointer type [enabled by default]


-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH] clk: socfpga: allow for multiple parents on Arria10 periph clocks

[Stephen Boyd]

On 02/22, dingu...@opensource.altera.com wrote:
> From: Dinh Nguyen 
> 
> There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can
> have multiple parents. Fix up the __socfpga_periph_init() to call
> of_clk_parent_fill() that will return the appropriate number of parents.
> 
> Also, update __socfpga_gate_init() to call of_clk_parent_fill() helper
> function.
> 
> Signed-off-by: Dinh Nguyen 
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH] clk: socfpga: allow for multiple parents on Arria10 periph clocks

[Stephen Boyd]

On 02/22, dingu...@opensource.altera.com wrote:
> From: Dinh Nguyen 
> 
> There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can
> have multiple parents. Fix up the __socfpga_periph_init() to call
> of_clk_parent_fill() that will return the appropriate number of parents.
> 
> Also, update __socfpga_gate_init() to call of_clk_parent_fill() helper
> function.
> 
> Signed-off-by: Dinh Nguyen 
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH] clk: socfpga: allow for multiple parents on Arria10 periph clocks

[dinguyen]

From: Dinh Nguyen 

There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can
have multiple parents. Fix up the __socfpga_periph_init() to call
of_clk_parent_fill() that will return the appropriate number of parents.

Also, update __socfpga_gate_init() to call of_clk_parent_fill() helper
function.

Signed-off-by: Dinh Nguyen 
---
 drivers/clk/socfpga/clk-gate-a10.c   | 5 +
 drivers/clk/socfpga/clk-periph-a10.c | 5 ++---
 2 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/socfpga/clk-gate-a10.c 
b/drivers/clk/socfpga/clk-gate-a10.c
index 1cebf25..0b6ee7b 100644
--- a/drivers/clk/socfpga/clk-gate-a10.c
+++ b/drivers/clk/socfpga/clk-gate-a10.c
@@ -167,12 +167,9 @@ static void __init __socfpga_gate_init(struct device_node 
*node,
init.name = clk_name;
init.ops = ops;
init.flags = 0;
-   while (i < SOCFPGA_MAX_PARENTS && (parent_name[i] =
-   of_clk_get_parent_name(node, i)) != NULL)
-   i++;
 
+   init.num_parents = of_clk_parent_fill(node, parent_name, 
SOCFPGA_MAX_PARENTS);
init.parent_names = parent_name;
-   init.num_parents = i;
socfpga_clk->hw.hw.init = 
 
clk = clk_register(NULL, _clk->hw.hw);
diff --git a/drivers/clk/socfpga/clk-periph-a10.c 
b/drivers/clk/socfpga/clk-periph-a10.c
index 1f397cb..2b7e215 100644
--- a/drivers/clk/socfpga/clk-periph-a10.c
+++ b/drivers/clk/socfpga/clk-periph-a10.c
@@ -74,7 +74,7 @@ static __init void __socfpga_periph_init(struct device_node 
*node,
struct clk *clk;
struct socfpga_periph_clk *periph_clk;
const char *clk_name = node->name;
-   const char *parent_name;
+   const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init;
int rc;
u32 fixed_div;
@@ -109,8 +109,7 @@ static __init void __socfpga_periph_init(struct device_node 
*node,
init.ops = ops;
init.flags = 0;
 
-   parent_name = of_clk_get_parent_name(node, 0);
-   init.num_parents = 1;
+   init.num_parents = of_clk_parent_fill(node, parent_name, 
SOCFPGA_MAX_PARENTS);
init.parent_names = _name;
 
periph_clk->hw.hw.init = 
-- 
2.6.2

[PATCH] clk: socfpga: allow for multiple parents on Arria10 periph clocks

[dinguyen]

From: Dinh Nguyen 

There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can
have multiple parents. Fix up the __socfpga_periph_init() to call
of_clk_parent_fill() that will return the appropriate number of parents.

Also, update __socfpga_gate_init() to call of_clk_parent_fill() helper
function.

Signed-off-by: Dinh Nguyen 
---
 drivers/clk/socfpga/clk-gate-a10.c   | 5 +
 drivers/clk/socfpga/clk-periph-a10.c | 5 ++---
 2 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/socfpga/clk-gate-a10.c 
b/drivers/clk/socfpga/clk-gate-a10.c
index 1cebf25..0b6ee7b 100644
--- a/drivers/clk/socfpga/clk-gate-a10.c
+++ b/drivers/clk/socfpga/clk-gate-a10.c
@@ -167,12 +167,9 @@ static void __init __socfpga_gate_init(struct device_node 
*node,
init.name = clk_name;
init.ops = ops;
init.flags = 0;
-   while (i < SOCFPGA_MAX_PARENTS && (parent_name[i] =
-   of_clk_get_parent_name(node, i)) != NULL)
-   i++;
 
+   init.num_parents = of_clk_parent_fill(node, parent_name, 
SOCFPGA_MAX_PARENTS);
init.parent_names = parent_name;
-   init.num_parents = i;
socfpga_clk->hw.hw.init = 
 
clk = clk_register(NULL, _clk->hw.hw);
diff --git a/drivers/clk/socfpga/clk-periph-a10.c 
b/drivers/clk/socfpga/clk-periph-a10.c
index 1f397cb..2b7e215 100644
--- a/drivers/clk/socfpga/clk-periph-a10.c
+++ b/drivers/clk/socfpga/clk-periph-a10.c
@@ -74,7 +74,7 @@ static __init void __socfpga_periph_init(struct device_node 
*node,
struct clk *clk;
struct socfpga_periph_clk *periph_clk;
const char *clk_name = node->name;
-   const char *parent_name;
+   const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init;
int rc;
u32 fixed_div;
@@ -109,8 +109,7 @@ static __init void __socfpga_periph_init(struct device_node 
*node,
init.ops = ops;
init.flags = 0;
 
-   parent_name = of_clk_get_parent_name(node, 0);
-   init.num_parents = 1;
+   init.num_parents = of_clk_parent_fill(node, parent_name, 
SOCFPGA_MAX_PARENTS);
init.parent_names = _name;
 
periph_clk->hw.hw.init = 
-- 
2.6.2