Re: [PATCH 1/2] x86/mce/amd: Extend "Disable error thresholding bank 4" to more models

2019-01-14 Thread Borislav Petkov 
On Thu, Jan 10, 2019 at 08:02:47AM +, S wrote:
> I wanted to send the patch with you in recipient field rather than cc, 
> unfortunately --cc remained in the git-send command

Next time look at the manpage:

git send-email --to  --cc  --suppress-cc=all

and the last switch stops git from adding more CCs.

Make sure you add "--dry-run" to check whether it adds the proper
CCs/Tos first and then send it for real.

-- 
Regards/Gruss,
Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

Re: [PATCH 1/2] x86/mce/amd: Extend "Disable error thresholding bank 4" to more models

2019-01-10 Thread S 
Hi Borislav,

On 1/10/2019 3:24 AM, Borislav Petkov wrote:
> On Mon, Jan 07, 2019 at 10:37:17AM +, S, Shirish wrote:
>> The below patch added this quirk only for the first generation of family
>> 15 processors, over time its noticed that its required for later
>> generations too.
>>
>> "575203b4747c x86, MCE, AMD: Disable error thresholding bank 4 on some
>> models"
>>
>> This patch extends the quirk to make it applicable till 7th Generation,
> Avoid having "This patch" or "This commit" in the commit message. It is
> tautologically useless.

Agree, have made the changes and re-spun re-spun v2 here: 
https://lkml.org/lkml/2019/1/10/69

I wanted to send the patch with you in recipient field rather than cc, 
unfortunately --cc remained in the git-send command

that i used, let me know i need to re-send it or you can see the patch.

Thanks.

Regards,

Shirish S

> Also, do
>
> $ git grep 'This patch' Documentation/process
>
> for more details.
>
-- 
Regards,
Shirish S

Re: [PATCH 1/2] x86/mce/amd: Extend "Disable error thresholding bank 4" to more models

2019-01-09 Thread Borislav Petkov 
On Mon, Jan 07, 2019 at 10:37:17AM +, S, Shirish wrote:
> The below patch added this quirk only for the first generation of family
> 15 processors, over time its noticed that its required for later
> generations too.
> 
> "575203b4747c x86, MCE, AMD: Disable error thresholding bank 4 on some
> models"
> 
> This patch extends the quirk to make it applicable till 7th Generation,

Avoid having "This patch" or "This commit" in the commit message. It is
tautologically useless.

Also, do

$ git grep 'This patch' Documentation/process

for more details.

-- 
Regards/Gruss,
Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

[PATCH 1/2] x86/mce/amd: Extend "Disable error thresholding bank 4" to more models

2019-01-07 Thread S, Shirish 
The below patch added this quirk only for the first generation of family
15 processors, over time its noticed that its required for later
generations too.

"575203b4747c x86, MCE, AMD: Disable error thresholding bank 4 on some
models"

This patch extends the quirk to make it applicable till 7th Generation,
so as to address the below warning at boot:

"[Firmware Bug]: cpu 0, invalid threshold interrupt offset ..."

Signed-off-by: Shirish S 
---
 arch/x86/kernel/cpu/mce/core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 672c722..051b536 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1616,7 +1616,7 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 
*c)
 * they're not supported there.
 */
if (c->x86 == 0x15 &&
-   (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) {
+   (c->x86_model >= 0x10 && c->x86_model <= 0x7f)) {
int i;
u64 hwcr;
bool need_toggle;
-- 
2.7.4

[PATCH 1/2] x86/mce/amd: Extend "Disable error thresholding bank 4" to more models

2019-01-04 Thread S, Shirish 
The below patch added this quirk only for the first generation of family
15 processors, over time its noticed that its required for later
generations too.

"575203b4747c x86, MCE, AMD: Disable error thresholding bank 4 on some
models"

This patch extends the quirk to make it applicable till 7th Generation,
so as to address the below warning at boot:

"[Firmware Bug]: cpu 0, invalid threshold interrupt offset ..."

Signed-off-by: Shirish S 
---
 arch/x86/kernel/cpu/mce/core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 672c722..051b536 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1616,7 +1616,7 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 
*c)
 * they're not supported there.
 */
if (c->x86 == 0x15 &&
-   (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) {
+   (c->x86_model >= 0x10 && c->x86_model <= 0x7f)) {
int i;
u64 hwcr;
bool need_toggle;
-- 
2.7.4