subject:"\[PATCH 1\/3\] arm64\: dts\: hi3660\: add pcie node"

Re: [PATCH 1/3] arm64: dts: hi3660: add pcie node

2017-05-15 Thread Guodong Xu

This PCIe node has dependencies on _ctrl and  However,
both of them are not appearing in mainline kernel tree yet. Sorry
about that. But I do have a plan to send all dts related changes to
maillist within this week, no later than this Wed (17/May). Would it
be possible you maintainers review this patch in parallel?

+Device tree maintainers.

-Guodong

>
> On Mon, May 15, 2017 at 5:18 PM, kbuild test robot  wrote:
>>
>> Hi Song,
>>
>> [auto build test ERROR on pci/next]
>> [also build test ERROR on v4.12-rc1 next-20170515]
>> [if your patch is applied to the wrong git tree, please drop us a note to 
>> help improve the system]
>>
>> url:
>> https://github.com/0day-ci/linux/commits/Song-Xiaowei/arm64-dts-hi3660-add-pcie-node/20170515-144035
>> base:   https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
>> config: arm64-defconfig (attached as .config)
>> compiler: aarch64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
>> reproduce:
>> wget 
>> https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O 
>> ~/bin/make.cross
>> chmod +x ~/bin/make.cross
>> # save the attached .config to linux build tree
>> make.cross ARCH=arm64
>>
>> All errors (new ones prefixed by >>):
>>
>> >> Error: arch/arm64/boot/dts/hisilicon/hi3660.dtsi:180.24-25 syntax error
>>FATAL ERROR: Unable to parse input tree
>>
>> ---
>> 0-DAY kernel test infrastructureOpen Source Technology Center
>> https://lists.01.org/pipermail/kbuild-all   Intel Corporation
>
>

Re: [PATCH 1/3] arm64: dts: hi3660: add pcie node

2017-05-15 Thread Guodong Xu

This PCIe node has dependencies on _ctrl and  However,
both of them are not appearing in mainline kernel tree yet. Sorry
about that. But I do have a plan to send all dts related changes to
maillist within this week, no later than this Wed (17/May). Would it
be possible you maintainers review this patch in parallel?

+Device tree maintainers.

-Guodong

>
> On Mon, May 15, 2017 at 5:18 PM, kbuild test robot  wrote:
>>
>> Hi Song,
>>
>> [auto build test ERROR on pci/next]
>> [also build test ERROR on v4.12-rc1 next-20170515]
>> [if your patch is applied to the wrong git tree, please drop us a note to 
>> help improve the system]
>>
>> url:
>> https://github.com/0day-ci/linux/commits/Song-Xiaowei/arm64-dts-hi3660-add-pcie-node/20170515-144035
>> base:   https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
>> config: arm64-defconfig (attached as .config)
>> compiler: aarch64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
>> reproduce:
>> wget 
>> https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O 
>> ~/bin/make.cross
>> chmod +x ~/bin/make.cross
>> # save the attached .config to linux build tree
>> make.cross ARCH=arm64
>>
>> All errors (new ones prefixed by >>):
>>
>> >> Error: arch/arm64/boot/dts/hisilicon/hi3660.dtsi:180.24-25 syntax error
>>FATAL ERROR: Unable to parse input tree
>>
>> ---
>> 0-DAY kernel test infrastructureOpen Source Technology Center
>> https://lists.01.org/pipermail/kbuild-all   Intel Corporation
>
>

Re: [PATCH 1/3] arm64: dts: hi3660: add pcie node

2017-05-15 Thread kbuild test robot

Hi Song,

[auto build test ERROR on pci/next]
[also build test ERROR on v4.12-rc1 next-20170515]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Song-Xiaowei/arm64-dts-hi3660-add-pcie-node/20170515-144035
base:   https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: arm64-defconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget 
https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm64 

All errors (new ones prefixed by >>):

>> Error: arch/arm64/boot/dts/hisilicon/hi3660.dtsi:180.24-25 syntax error
   FATAL ERROR: Unable to parse input tree

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: application/gzip

Re: [PATCH 1/3] arm64: dts: hi3660: add pcie node

2017-05-15 Thread kbuild test robot

Hi Song,

[auto build test ERROR on pci/next]
[also build test ERROR on v4.12-rc1 next-20170515]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Song-Xiaowei/arm64-dts-hi3660-add-pcie-node/20170515-144035
base:   https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: arm64-defconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget 
https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm64 

All errors (new ones prefixed by >>):

>> Error: arch/arm64/boot/dts/hisilicon/hi3660.dtsi:180.24-25 syntax error
   FATAL ERROR: Unable to parse input tree

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: application/gzip

Re: [PATCH 1/3] arm64: dts: hi3660: add pcie node

2017-05-15 Thread Niklas Cassel

Hello Song


You forgot to add the device tree maintainers
and the device tree mailing list to this patch.

If you use ./scripts/get_maintainer.pl 
it will show you this information.


Regards,
Niklas


On 05/15/2017 08:27 AM, Song Xiaowei wrote:
> Add PCIe node for hi3660, and add binding documentation.
> 
> Cc: Guodong Xu 
> Signed-off-by: Song Xiaowei 
> ---
>  .../devicetree/bindings/pci/hisilicon-pcie.txt | 52 
> ++
>  arch/arm64/boot/dts/hisilicon/hi3660.dtsi  | 31 +
>  2 files changed, 83 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt 
> b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
> index a339dbb15493..71491178c86c 100644
> --- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
> @@ -85,3 +85,55 @@ Example:
>0x0 0 0 4 _pcie0 650 4>;
>   status = "ok";
>   };
> +
> +
> +
> +HiSilicon Kirin SoC PCIe host DT description
> +
> +Kirin PCIe host controller is also based on Designware PCI core.
> +It shares common functions with PCIe Designware core driver and inherits
> +common properties defined in
> +Documentation/devicetree/bindings/pci/designware-pci.txt.
> +
> +Additional properties are described here:
> +
> +Required properties
> +- compatible: Should contain "hisilicon,kirin-pcie".
> +- reg: Should contain rc_dbi, apb, phy, config registers location and length.
> +- reg-names: Must include the following entries:
> +  "dbi": controller configuration registers;
> +  "apb": apb Ctrl register;
> +  "phy": apb PHY register;
> +  "config": PCIe configuration space registers.
> +- reset-gpio: perst assert/deassert gpio
> +
> +Optional properties:
> +- status: Either "ok" or "disabled".
> +
> +Kirin960 Example:
> +kirin_pcie@f400 {
> +compatible = "hisilicon,kirin-pcie";
> +reg =  <0x0 0xf400 0x0 0x1000>, <0x0 0xff3fe000 
> 0x0 0x1000>,
> + <0x0 0xf3f2 0x0 0x4>, <0x0 
> 0xF500 0 0x2000>;
> +reg-names = "dbi","apb","phy", "config";
> +bus-range = <0x0  0x1>;
> +#address-cells = <3>;
> +#size-cells = <2>;
> +device_type = "pci";
> +ranges = <0x0200 0x0 0x 0x0 0xf600 
> 0x0 0x200>;
> +num-lanes = <1>;
> +#interrupt-cells = <1>;
> +interrupt-map-mask = <0xf800 0 0 7>;
> + interrupt-map = <0x0 0 0 2  0 0 0  283 4>,
> +<0x0 0 0 3  0 0 0  284 4>,
> +<0x0 0 0 4  0 0 0  285 4>;
> +clocks = <_ctrl HI3660_PCIEPHY_REF>,
> +<_ctrl HI3660_CLK_GATE_PCIEAUX>,
> +<_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
> +<_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
> +<_ctrl HI3660_ACLK_GATE_PCIE>;
> +clock-names = "pcie_phy_ref", "pcie_aux",
> +"pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
> +reset-gpio = < 1 0 >;
> +status = "ok";
> +};
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi 
> b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> index 3983086bd67b..2406a54947df 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> @@ -156,5 +156,36 @@
>   clock-names = "uartclk", "apb_pclk";
>   status = "disabled";
>   };
> +
> + kirin_pcie@f400 {
> + compatible = "hisilicon,kirin-pcie";
> + reg =  <0x0 0xf400 0x0 0x1000>,
> + <0x0 0xff3fe000 0x0 0x1000>,
> + <0x0 0xf3f2 0x0 0x4>,
> + <0x0 0xF500 0x0 0x2000>;
> + reg-names = "dbi", "apb", "phy", "config";
> + bus-range = <0x0  0x1>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + ranges = <0x0200 0x0 0x 0x0
> + 0xf600 0x0 0x200>;
> + num-lanes = <1>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0xf800 0 0 7>;
> + interrupt-map = <0x0 0 0 1  0 0 0 282 4>,
> + <0x0 0 0 2  0 0 0  283 4>,
> + <0x0 0 0 3  0 0 0  284 4>,
> +

Re: [PATCH 1/3] arm64: dts: hi3660: add pcie node

2017-05-15 Thread Niklas Cassel

Hello Song


You forgot to add the device tree maintainers
and the device tree mailing list to this patch.

If you use ./scripts/get_maintainer.pl 
it will show you this information.


Regards,
Niklas


On 05/15/2017 08:27 AM, Song Xiaowei wrote:
> Add PCIe node for hi3660, and add binding documentation.
> 
> Cc: Guodong Xu 
> Signed-off-by: Song Xiaowei 
> ---
>  .../devicetree/bindings/pci/hisilicon-pcie.txt | 52 
> ++
>  arch/arm64/boot/dts/hisilicon/hi3660.dtsi  | 31 +
>  2 files changed, 83 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt 
> b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
> index a339dbb15493..71491178c86c 100644
> --- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
> @@ -85,3 +85,55 @@ Example:
>0x0 0 0 4 _pcie0 650 4>;
>   status = "ok";
>   };
> +
> +
> +
> +HiSilicon Kirin SoC PCIe host DT description
> +
> +Kirin PCIe host controller is also based on Designware PCI core.
> +It shares common functions with PCIe Designware core driver and inherits
> +common properties defined in
> +Documentation/devicetree/bindings/pci/designware-pci.txt.
> +
> +Additional properties are described here:
> +
> +Required properties
> +- compatible: Should contain "hisilicon,kirin-pcie".
> +- reg: Should contain rc_dbi, apb, phy, config registers location and length.
> +- reg-names: Must include the following entries:
> +  "dbi": controller configuration registers;
> +  "apb": apb Ctrl register;
> +  "phy": apb PHY register;
> +  "config": PCIe configuration space registers.
> +- reset-gpio: perst assert/deassert gpio
> +
> +Optional properties:
> +- status: Either "ok" or "disabled".
> +
> +Kirin960 Example:
> +kirin_pcie@f400 {
> +compatible = "hisilicon,kirin-pcie";
> +reg =  <0x0 0xf400 0x0 0x1000>, <0x0 0xff3fe000 
> 0x0 0x1000>,
> + <0x0 0xf3f2 0x0 0x4>, <0x0 
> 0xF500 0 0x2000>;
> +reg-names = "dbi","apb","phy", "config";
> +bus-range = <0x0  0x1>;
> +#address-cells = <3>;
> +#size-cells = <2>;
> +device_type = "pci";
> +ranges = <0x0200 0x0 0x 0x0 0xf600 
> 0x0 0x200>;
> +num-lanes = <1>;
> +#interrupt-cells = <1>;
> +interrupt-map-mask = <0xf800 0 0 7>;
> + interrupt-map = <0x0 0 0 2  0 0 0  283 4>,
> +<0x0 0 0 3  0 0 0  284 4>,
> +<0x0 0 0 4  0 0 0  285 4>;
> +clocks = <_ctrl HI3660_PCIEPHY_REF>,
> +<_ctrl HI3660_CLK_GATE_PCIEAUX>,
> +<_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
> +<_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
> +<_ctrl HI3660_ACLK_GATE_PCIE>;
> +clock-names = "pcie_phy_ref", "pcie_aux",
> +"pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
> +reset-gpio = < 1 0 >;
> +status = "ok";
> +};
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi 
> b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> index 3983086bd67b..2406a54947df 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> @@ -156,5 +156,36 @@
>   clock-names = "uartclk", "apb_pclk";
>   status = "disabled";
>   };
> +
> + kirin_pcie@f400 {
> + compatible = "hisilicon,kirin-pcie";
> + reg =  <0x0 0xf400 0x0 0x1000>,
> + <0x0 0xff3fe000 0x0 0x1000>,
> + <0x0 0xf3f2 0x0 0x4>,
> + <0x0 0xF500 0x0 0x2000>;
> + reg-names = "dbi", "apb", "phy", "config";
> + bus-range = <0x0  0x1>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + ranges = <0x0200 0x0 0x 0x0
> + 0xf600 0x0 0x200>;
> + num-lanes = <1>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0xf800 0 0 7>;
> + interrupt-map = <0x0 0 0 1  0 0 0 282 4>,
> + <0x0 0 0 2  0 0 0  283 4>,
> + <0x0 0 0 3  0 0 0  284 4>,
> + <0x0 0 0 4  0 0 0  285 4>;
> +

[PATCH 1/3] arm64: dts: hi3660: add pcie node

2017-05-15 Thread Song Xiaowei

Add PCIe node for hi3660, and add binding documentation.

Cc: Guodong Xu 
Signed-off-by: Song Xiaowei 
---
 .../devicetree/bindings/pci/hisilicon-pcie.txt | 52 ++
 arch/arm64/boot/dts/hisilicon/hi3660.dtsi  | 31 +
 2 files changed, 83 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt 
b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
index a339dbb15493..71491178c86c 100644
--- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
@@ -85,3 +85,55 @@ Example:
 0x0 0 0 4 _pcie0 650 4>;
status = "ok";
};
+
+
+
+HiSilicon Kirin SoC PCIe host DT description
+
+Kirin PCIe host controller is also based on Designware PCI core.
+It shares common functions with PCIe Designware core driver and inherits
+common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties
+- compatible: Should contain "hisilicon,kirin-pcie".
+- reg: Should contain rc_dbi, apb, phy, config registers location and length.
+- reg-names: Must include the following entries:
+  "dbi": controller configuration registers;
+  "apb": apb Ctrl register;
+  "phy": apb PHY register;
+  "config": PCIe configuration space registers.
+- reset-gpio: perst assert/deassert gpio
+
+Optional properties:
+- status: Either "ok" or "disabled".
+
+Kirin960 Example:
+kirin_pcie@f400 {
+compatible = "hisilicon,kirin-pcie";
+reg =  <0x0 0xf400 0x0 0x1000>, <0x0 0xff3fe000 
0x0 0x1000>,
+ <0x0 0xf3f2 0x0 0x4>, <0x0 0xF500 
0 0x2000>;
+reg-names = "dbi","apb","phy", "config";
+bus-range = <0x0  0x1>;
+#address-cells = <3>;
+#size-cells = <2>;
+device_type = "pci";
+ranges = <0x0200 0x0 0x 0x0 0xf600 0x0 
0x200>;
+num-lanes = <1>;
+#interrupt-cells = <1>;
+interrupt-map-mask = <0xf800 0 0 7>;
+   interrupt-map = <0x0 0 0 2  0 0 0  283 4>,
+<0x0 0 0 3  0 0 0  284 4>,
+<0x0 0 0 4  0 0 0  285 4>;
+clocks = <_ctrl HI3660_PCIEPHY_REF>,
+<_ctrl HI3660_CLK_GATE_PCIEAUX>,
+<_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
+<_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+<_ctrl HI3660_ACLK_GATE_PCIE>;
+clock-names = "pcie_phy_ref", "pcie_aux",
+"pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
+reset-gpio = < 1 0 >;
+status = "ok";
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi 
b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 3983086bd67b..2406a54947df 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -156,5 +156,36 @@
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
+
+   kirin_pcie@f400 {
+   compatible = "hisilicon,kirin-pcie";
+   reg =  <0x0 0xf400 0x0 0x1000>,
+   <0x0 0xff3fe000 0x0 0x1000>,
+   <0x0 0xf3f2 0x0 0x4>,
+   <0x0 0xF500 0x0 0x2000>;
+   reg-names = "dbi", "apb", "phy", "config";
+   bus-range = <0x0  0x1>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
+   ranges = <0x0200 0x0 0x 0x0
+   0xf600 0x0 0x200>;
+   num-lanes = <1>;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0xf800 0 0 7>;
+   interrupt-map = <0x0 0 0 1  0 0 0 282 4>,
+   <0x0 0 0 2  0 0 0  283 4>,
+   <0x0 0 0 3  0 0 0  284 4>,
+   <0x0 0 0 4  0 0 0  285 4>;
+   clocks = <_ctrl HI3660_PCIEPHY_REF>,
+   <_ctrl HI3660_CLK_GATE_PCIEAUX>,
+   <_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
+   <_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+   <_ctrl HI3660_ACLK_GATE_PCIE>;
+   clock-names = "pcie_phy_ref",

[PATCH 1/3] arm64: dts: hi3660: add pcie node

2017-05-15 Thread Song Xiaowei

Add PCIe node for hi3660, and add binding documentation.

Cc: Guodong Xu 
Signed-off-by: Song Xiaowei 
---
 .../devicetree/bindings/pci/hisilicon-pcie.txt | 52 ++
 arch/arm64/boot/dts/hisilicon/hi3660.dtsi  | 31 +
 2 files changed, 83 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt 
b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
index a339dbb15493..71491178c86c 100644
--- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
@@ -85,3 +85,55 @@ Example:
 0x0 0 0 4 _pcie0 650 4>;
status = "ok";
};
+
+
+
+HiSilicon Kirin SoC PCIe host DT description
+
+Kirin PCIe host controller is also based on Designware PCI core.
+It shares common functions with PCIe Designware core driver and inherits
+common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties
+- compatible: Should contain "hisilicon,kirin-pcie".
+- reg: Should contain rc_dbi, apb, phy, config registers location and length.
+- reg-names: Must include the following entries:
+  "dbi": controller configuration registers;
+  "apb": apb Ctrl register;
+  "phy": apb PHY register;
+  "config": PCIe configuration space registers.
+- reset-gpio: perst assert/deassert gpio
+
+Optional properties:
+- status: Either "ok" or "disabled".
+
+Kirin960 Example:
+kirin_pcie@f400 {
+compatible = "hisilicon,kirin-pcie";
+reg =  <0x0 0xf400 0x0 0x1000>, <0x0 0xff3fe000 
0x0 0x1000>,
+ <0x0 0xf3f2 0x0 0x4>, <0x0 0xF500 
0 0x2000>;
+reg-names = "dbi","apb","phy", "config";
+bus-range = <0x0  0x1>;
+#address-cells = <3>;
+#size-cells = <2>;
+device_type = "pci";
+ranges = <0x0200 0x0 0x 0x0 0xf600 0x0 
0x200>;
+num-lanes = <1>;
+#interrupt-cells = <1>;
+interrupt-map-mask = <0xf800 0 0 7>;
+   interrupt-map = <0x0 0 0 2  0 0 0  283 4>,
+<0x0 0 0 3  0 0 0  284 4>,
+<0x0 0 0 4  0 0 0  285 4>;
+clocks = <_ctrl HI3660_PCIEPHY_REF>,
+<_ctrl HI3660_CLK_GATE_PCIEAUX>,
+<_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
+<_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+<_ctrl HI3660_ACLK_GATE_PCIE>;
+clock-names = "pcie_phy_ref", "pcie_aux",
+"pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
+reset-gpio = < 1 0 >;
+status = "ok";
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi 
b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 3983086bd67b..2406a54947df 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -156,5 +156,36 @@
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
+
+   kirin_pcie@f400 {
+   compatible = "hisilicon,kirin-pcie";
+   reg =  <0x0 0xf400 0x0 0x1000>,
+   <0x0 0xff3fe000 0x0 0x1000>,
+   <0x0 0xf3f2 0x0 0x4>,
+   <0x0 0xF500 0x0 0x2000>;
+   reg-names = "dbi", "apb", "phy", "config";
+   bus-range = <0x0  0x1>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   device_type = "pci";
+   ranges = <0x0200 0x0 0x 0x0
+   0xf600 0x0 0x200>;
+   num-lanes = <1>;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0xf800 0 0 7>;
+   interrupt-map = <0x0 0 0 1  0 0 0 282 4>,
+   <0x0 0 0 2  0 0 0  283 4>,
+   <0x0 0 0 3  0 0 0  284 4>,
+   <0x0 0 0 4  0 0 0  285 4>;
+   clocks = <_ctrl HI3660_PCIEPHY_REF>,
+   <_ctrl HI3660_CLK_GATE_PCIEAUX>,
+   <_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
+   <_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+   <_ctrl HI3660_ACLK_GATE_PCIE>;
+   clock-names = "pcie_phy_ref", "pcie_aux",
+

Re: [PATCH 1/3] arm64: dts: hi3660: add pcie node

Re: [PATCH 1/3] arm64: dts: hi3660: add pcie node

Re: [PATCH 1/3] arm64: dts: hi3660: add pcie node

Re: [PATCH 1/3] arm64: dts: hi3660: add pcie node

Re: [PATCH 1/3] arm64: dts: hi3660: add pcie node

Re: [PATCH 1/3] arm64: dts: hi3660: add pcie node

[PATCH 1/3] arm64: dts: hi3660: add pcie node

[PATCH 1/3] arm64: dts: hi3660: add pcie node

8 matches

Site Navigation

Mail list logo

Footer information