Re: [PATCH v1 1/3] x86/cpu/AMD: Make LFENCE a serializing instruction

[Tom Lendacky]

On 1/5/2018 10:35 AM, Brian Gerst wrote:
> On Fri, Jan 5, 2018 at 11:07 AM, Tom Lendacky  wrote:
>> To aid in speculation control, make LFENCE a serializing instruction.
>> This is done by setting bit 1 of MSR 0xc0011029 (DE_CFG).  Some families
>> that support LFENCE do not have this MSR.  For these families, the LFENCE
>> instruction is already serializing.
> 
> Does this require a microcode update?

No, it doesn't.

Thanks,
Tom

> 
> --
> Brian Gerst
> 

Re: [PATCH v1 1/3] x86/cpu/AMD: Make LFENCE a serializing instruction

[Tom Lendacky]

On 1/5/2018 10:35 AM, Brian Gerst wrote:
> On Fri, Jan 5, 2018 at 11:07 AM, Tom Lendacky  wrote:
>> To aid in speculation control, make LFENCE a serializing instruction.
>> This is done by setting bit 1 of MSR 0xc0011029 (DE_CFG).  Some families
>> that support LFENCE do not have this MSR.  For these families, the LFENCE
>> instruction is already serializing.
> 
> Does this require a microcode update?

No, it doesn't.

Thanks,
Tom

> 
> --
> Brian Gerst
> 

Re: [PATCH v1 1/3] x86/cpu/AMD: Make LFENCE a serializing instruction

[Brian Gerst]

On Fri, Jan 5, 2018 at 11:07 AM, Tom Lendacky  wrote:
> To aid in speculation control, make LFENCE a serializing instruction.
> This is done by setting bit 1 of MSR 0xc0011029 (DE_CFG).  Some families
> that support LFENCE do not have this MSR.  For these families, the LFENCE
> instruction is already serializing.

Does this require a microcode update?

--
Brian Gerst

Re: [PATCH v1 1/3] x86/cpu/AMD: Make LFENCE a serializing instruction

[Brian Gerst]

On Fri, Jan 5, 2018 at 11:07 AM, Tom Lendacky  wrote:
> To aid in speculation control, make LFENCE a serializing instruction.
> This is done by setting bit 1 of MSR 0xc0011029 (DE_CFG).  Some families
> that support LFENCE do not have this MSR.  For these families, the LFENCE
> instruction is already serializing.

Does this require a microcode update?

--
Brian Gerst

[PATCH v1 1/3] x86/cpu/AMD: Make LFENCE a serializing instruction

[Tom Lendacky]

To aid in speculation control, make LFENCE a serializing instruction.
This is done by setting bit 1 of MSR 0xc0011029 (DE_CFG).  Some families
that support LFENCE do not have this MSR.  For these families, the LFENCE
instruction is already serializing.

Signed-off-by: Tom Lendacky 
---
 arch/x86/include/asm/msr-index.h |2 ++
 arch/x86/kernel/cpu/amd.c|9 +
 2 files changed, 11 insertions(+)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index ab02261..1e7d710 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -352,6 +352,8 @@
 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffULL
 #define FAM10H_MMIO_CONF_BASE_SHIFT20
 #define MSR_FAM10H_NODE_ID 0xc001100c
+#define MSR_F10H_DECFG 0xc0011029
+#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT1
 
 /* K8 MSRs */
 #define MSR_K8_TOP_MEM10xc001001a
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index bcb75dc..fbd439e 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -829,6 +829,15 @@ static void init_amd(struct cpuinfo_x86 *c)
set_cpu_cap(c, X86_FEATURE_K8);
 
if (cpu_has(c, X86_FEATURE_XMM2)) {
+   /*
+* Use LFENCE for execution serialization. On families which
+* don't have that MSR, LFENCE is already serializing.
+* msr_set_bit() uses the safe accessors, too, even if the MSR
+* is not present.
+*/
+   msr_set_bit(MSR_F10H_DECFG,
+   MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
+
/* MFENCE stops RDTSC speculation */
set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
}

[PATCH v1 1/3] x86/cpu/AMD: Make LFENCE a serializing instruction

[Tom Lendacky]

To aid in speculation control, make LFENCE a serializing instruction.
This is done by setting bit 1 of MSR 0xc0011029 (DE_CFG).  Some families
that support LFENCE do not have this MSR.  For these families, the LFENCE
instruction is already serializing.

Signed-off-by: Tom Lendacky 
---
 arch/x86/include/asm/msr-index.h |2 ++
 arch/x86/kernel/cpu/amd.c|9 +
 2 files changed, 11 insertions(+)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index ab02261..1e7d710 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -352,6 +352,8 @@
 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffULL
 #define FAM10H_MMIO_CONF_BASE_SHIFT20
 #define MSR_FAM10H_NODE_ID 0xc001100c
+#define MSR_F10H_DECFG 0xc0011029
+#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT1
 
 /* K8 MSRs */
 #define MSR_K8_TOP_MEM10xc001001a
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index bcb75dc..fbd439e 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -829,6 +829,15 @@ static void init_amd(struct cpuinfo_x86 *c)
set_cpu_cap(c, X86_FEATURE_K8);
 
if (cpu_has(c, X86_FEATURE_XMM2)) {
+   /*
+* Use LFENCE for execution serialization. On families which
+* don't have that MSR, LFENCE is already serializing.
+* msr_set_bit() uses the safe accessors, too, even if the MSR
+* is not present.
+*/
+   msr_set_bit(MSR_F10H_DECFG,
+   MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
+
/* MFENCE stops RDTSC speculation */
set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
}