Re: [PATCH v4 1/2] of: add J-Core interrupt controller bindings

[Rich Felker]

On Wed, Jul 27, 2016 at 11:05:05AM +0100, Mark Rutland wrote:
> On Wed, Jul 27, 2016 at 05:35:09AM +, Rich Felker wrote:
> > Signed-off-by: Rich Felker 
> > ---
> >  .../bindings/interrupt-controller/jcore,aic.txt| 26 
> > ++
> >  1 file changed, 26 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> > 
> > diff --git 
> > a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt 
> > b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> > new file mode 100644
> > index 000..b7a56ad
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> > @@ -0,0 +1,26 @@
> > +J-Core Advanced Interrupt Controller
> > +
> > +Required properties:
> > +
> > +- compatible: Should be "jcore,aic1" for the (obsolete) first-generation 
> > aic
> > +  with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
> > +  the "aic2" core with 64 interrupts.
> > +
> > +- reg: Memory region(s) for configuration. For SMP, there should be one
> > +  region per cpu, indexed by the sequential, zero-based hardware cpu
> > +  number (which is also the logical cpu number).
> 
> Nit: remove the bit about the logical number. That's a linux detail that
> doesn't belong in the binding.

OK.

> > +- interrupt-controller: Identifies the node as an interrupt controller
> > +
> > +- #interrupt-cells: Specifies the number of cells needed to encode an
> > +  interrupt source. The value shall be 1.
> 
>  where the value encoded in that cell is?
> 
> I guess it's the zero-based index of the interrupt?
> 
> No flags? Can the AIC only do one trigger type?

This was asked before. The AIC does all the interrupt control (aside
from the cpu's main imask status) and does not expose trigger types or
require any kind of ack/eoi from the software. If you'd like to know
more about the motivations behind how it works I could ask on the
j-core list but for the purpose of the bindings and driver I'm just
documenting/supporting what the existing hw design does.

Rich

Re: [PATCH v4 1/2] of: add J-Core interrupt controller bindings

[Rich Felker]

On Wed, Jul 27, 2016 at 11:05:05AM +0100, Mark Rutland wrote:
> On Wed, Jul 27, 2016 at 05:35:09AM +, Rich Felker wrote:
> > Signed-off-by: Rich Felker 
> > ---
> >  .../bindings/interrupt-controller/jcore,aic.txt| 26 
> > ++
> >  1 file changed, 26 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> > 
> > diff --git 
> > a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt 
> > b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> > new file mode 100644
> > index 000..b7a56ad
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> > @@ -0,0 +1,26 @@
> > +J-Core Advanced Interrupt Controller
> > +
> > +Required properties:
> > +
> > +- compatible: Should be "jcore,aic1" for the (obsolete) first-generation 
> > aic
> > +  with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
> > +  the "aic2" core with 64 interrupts.
> > +
> > +- reg: Memory region(s) for configuration. For SMP, there should be one
> > +  region per cpu, indexed by the sequential, zero-based hardware cpu
> > +  number (which is also the logical cpu number).
> 
> Nit: remove the bit about the logical number. That's a linux detail that
> doesn't belong in the binding.

OK.

> > +- interrupt-controller: Identifies the node as an interrupt controller
> > +
> > +- #interrupt-cells: Specifies the number of cells needed to encode an
> > +  interrupt source. The value shall be 1.
> 
>  where the value encoded in that cell is?
> 
> I guess it's the zero-based index of the interrupt?
> 
> No flags? Can the AIC only do one trigger type?

This was asked before. The AIC does all the interrupt control (aside
from the cpu's main imask status) and does not expose trigger types or
require any kind of ack/eoi from the software. If you'd like to know
more about the motivations behind how it works I could ask on the
j-core list but for the purpose of the bindings and driver I'm just
documenting/supporting what the existing hw design does.

Rich

Re: [PATCH v4 1/2] of: add J-Core interrupt controller bindings

[Mark Rutland]

On Wed, Jul 27, 2016 at 05:35:09AM +, Rich Felker wrote:
> Signed-off-by: Rich Felker 
> ---
>  .../bindings/interrupt-controller/jcore,aic.txt| 26 
> ++
>  1 file changed, 26 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> 
> diff --git 
> a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt 
> b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> new file mode 100644
> index 000..b7a56ad
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> @@ -0,0 +1,26 @@
> +J-Core Advanced Interrupt Controller
> +
> +Required properties:
> +
> +- compatible: Should be "jcore,aic1" for the (obsolete) first-generation aic
> +  with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
> +  the "aic2" core with 64 interrupts.
> +
> +- reg: Memory region(s) for configuration. For SMP, there should be one
> +  region per cpu, indexed by the sequential, zero-based hardware cpu
> +  number (which is also the logical cpu number).

Nit: remove the bit about the logical number. That's a linux detail that
doesn't belong in the binding.

> +- interrupt-controller: Identifies the node as an interrupt controller
> +
> +- #interrupt-cells: Specifies the number of cells needed to encode an
> +  interrupt source. The value shall be 1.

... where the value encoded in that cell is?

I guess it's the zero-based index of the interrupt?

No flags? Can the AIC only do one trigger type?

Thanks,
Mark.

Re: [PATCH v4 1/2] of: add J-Core interrupt controller bindings

[Mark Rutland]

On Wed, Jul 27, 2016 at 05:35:09AM +, Rich Felker wrote:
> Signed-off-by: Rich Felker 
> ---
>  .../bindings/interrupt-controller/jcore,aic.txt| 26 
> ++
>  1 file changed, 26 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> 
> diff --git 
> a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt 
> b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> new file mode 100644
> index 000..b7a56ad
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> @@ -0,0 +1,26 @@
> +J-Core Advanced Interrupt Controller
> +
> +Required properties:
> +
> +- compatible: Should be "jcore,aic1" for the (obsolete) first-generation aic
> +  with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
> +  the "aic2" core with 64 interrupts.
> +
> +- reg: Memory region(s) for configuration. For SMP, there should be one
> +  region per cpu, indexed by the sequential, zero-based hardware cpu
> +  number (which is also the logical cpu number).

Nit: remove the bit about the logical number. That's a linux detail that
doesn't belong in the binding.

> +- interrupt-controller: Identifies the node as an interrupt controller
> +
> +- #interrupt-cells: Specifies the number of cells needed to encode an
> +  interrupt source. The value shall be 1.

... where the value encoded in that cell is?

I guess it's the zero-based index of the interrupt?

No flags? Can the AIC only do one trigger type?

Thanks,
Mark.

[PATCH v4 1/2] of: add J-Core interrupt controller bindings

[Rich Felker]

Signed-off-by: Rich Felker 
---
 .../bindings/interrupt-controller/jcore,aic.txt| 26 ++
 1 file changed, 26 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt 
b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
new file mode 100644
index 000..b7a56ad
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
@@ -0,0 +1,26 @@
+J-Core Advanced Interrupt Controller
+
+Required properties:
+
+- compatible: Should be "jcore,aic1" for the (obsolete) first-generation aic
+  with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
+  the "aic2" core with 64 interrupts.
+
+- reg: Memory region(s) for configuration. For SMP, there should be one
+  region per cpu, indexed by the sequential, zero-based hardware cpu
+  number (which is also the logical cpu number).
+
+- interrupt-controller: Identifies the node as an interrupt controller
+
+- #interrupt-cells: Specifies the number of cells needed to encode an
+  interrupt source. The value shall be 1.
+
+
+Example:
+
+aic: interrupt-controller@200 {
+   compatible = "jcore,aic2";
+   reg = < 0x200 0x30 0x500 0x30 >;
+   interrupt-controller;
+   #interrupt-cells = <1>;
+};
-- 
2.8.1

[PATCH v4 1/2] of: add J-Core interrupt controller bindings

[Rich Felker]

Signed-off-by: Rich Felker 
---
 .../bindings/interrupt-controller/jcore,aic.txt| 26 ++
 1 file changed, 26 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt 
b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
new file mode 100644
index 000..b7a56ad
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
@@ -0,0 +1,26 @@
+J-Core Advanced Interrupt Controller
+
+Required properties:
+
+- compatible: Should be "jcore,aic1" for the (obsolete) first-generation aic
+  with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
+  the "aic2" core with 64 interrupts.
+
+- reg: Memory region(s) for configuration. For SMP, there should be one
+  region per cpu, indexed by the sequential, zero-based hardware cpu
+  number (which is also the logical cpu number).
+
+- interrupt-controller: Identifies the node as an interrupt controller
+
+- #interrupt-cells: Specifies the number of cells needed to encode an
+  interrupt source. The value shall be 1.
+
+
+Example:
+
+aic: interrupt-controller@200 {
+   compatible = "jcore,aic2";
+   reg = < 0x200 0x30 0x500 0x30 >;
+   interrupt-controller;
+   #interrupt-cells = <1>;
+};
-- 
2.8.1