Re: [PATCH v2 1/2] mtd: hisilicon: add a new NAND controller driver for hisilicon hip04 Soc

2014-10-24 Thread Zhou Wang

On 2014年10月24日 19:46, Haojian Zhuang wrote:

On Thu, Oct 23, 2014 at 10:04 PM, Zhou Wang  wrote:

Signed-off-by: Zhou Wang 
---
  drivers/mtd/nand/Kconfig|5 +
  drivers/mtd/nand/Makefile   |1 +
  drivers/mtd/nand/hisi504_nand.c |  836 +++
  3 files changed, 842 insertions(+)
  create mode 100644 drivers/mtd/nand/hisi504_nand.c



I think that you need to run scripts/checkpatch.pl. There're some
warnings reported on this patch.


Hi Haojian,

I will run the checkpatch.pl again and fix the warnings.
But for lines like this:
+   if (host->command == NAND_CMD_ERASE1)
+   host->addr_value[0] |= ((page_addr >>16) & 0xff) << 16;
+   else
+   host->addr_value[1] |= ((page_addr >> 16) & 0xff);
Only over 80 for some characters in one line, it will report a warning.
Can I just leave the warning there for the tidy of the code?


+
+   case NAND_CMD_SEQIN:
+   host->offset = column;
+


It's better not using waterfall style. Maybe you can write it clearly.
 case NAND_CMD_SEQIN:
 host->offset = column;
 set_addr(mtd, column, page_addr);
 break;

Thanks, I will modify the code like this above.



+   chip->ecc.mode = of_get_nand_ecc_mode(np);
+   /* read ecc-bits from dts */
+   of_property_read_u32(np, "hisi,nand-ecc-bits", &host->ecc_bits);


Do you need to check the ecc_bits at here? Maybe user inputed the
wrong ecc_bits in DTS.

Yes, it is better to check the ecc_bits here, thanks for your reminding.

Best regards,
Zhou Wang


Best Regards
Haojian



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Re: [PATCH v2 1/2] mtd: hisilicon: add a new NAND controller driver for hisilicon hip04 Soc

2014-10-24 Thread Haojian Zhuang
On Thu, Oct 23, 2014 at 10:04 PM, Zhou Wang  wrote:
> Signed-off-by: Zhou Wang 
> ---
>  drivers/mtd/nand/Kconfig|5 +
>  drivers/mtd/nand/Makefile   |1 +
>  drivers/mtd/nand/hisi504_nand.c |  836 
> +++
>  3 files changed, 842 insertions(+)
>  create mode 100644 drivers/mtd/nand/hisi504_nand.c
>

I think that you need to run scripts/checkpatch.pl. There're some
warnings reported on this patch.

> +
> +   case NAND_CMD_SEQIN:
> +   host->offset = column;
> +

It's better not using waterfall style. Maybe you can write it clearly.
case NAND_CMD_SEQIN:
host->offset = column;
set_addr(mtd, column, page_addr);
break;

> +   chip->ecc.mode = of_get_nand_ecc_mode(np);
> +   /* read ecc-bits from dts */
> +   of_property_read_u32(np, "hisi,nand-ecc-bits", &host->ecc_bits);

Do you need to check the ecc_bits at here? Maybe user inputed the
wrong ecc_bits in DTS.

Best Regards
Haojian
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