Re: [PATCH 2/4] ARM: mvebu/orion: remove NO_IRQ check from device init
mapbase,
> unsigned long freq_m)
> {
> orion_i2c_pdata.freq_m = freq_m;
> - fill_resources(_i2c, orion_i2c_resources, mapbase,
> + fill_resources_irq(_i2c, orion_i2c_resources, mapbase,
> SZ_32 - 1, irq);
> platform_device_register(_i2c);
> }
> @@ -545,7 +551,7 @@ void __init orion_i2c_1_init(unsigned long mapbase,
>unsigned long freq_m)
> {
> orion_i2c_1_pdata.freq_m = freq_m;
> - fill_resources(_i2c_1, orion_i2c_1_resources, mapbase,
> + fill_resources_irq(_i2c_1, orion_i2c_1_resources, mapbase,
> SZ_32 - 1, irq);
> platform_device_register(_i2c_1);
> }
> @@ -573,14 +579,14 @@ static struct platform_device orion_spi_1 = {
> void __init orion_spi_init(unsigned long mapbase)
> {
> fill_resources(_spi, _spi_resources,
> -mapbase, SZ_512 - 1, NO_IRQ);
> +mapbase, SZ_512 - 1);
> platform_device_register(_spi);
> }
>
> void __init orion_spi_1_init(unsigned long mapbase)
> {
> fill_resources(_spi_1, _spi_1_resources,
> -mapbase, SZ_512 - 1, NO_IRQ);
> +mapbase, SZ_512 - 1);
> platform_device_register(_spi_1);
> }
>
> @@ -738,7 +744,7 @@ void __init orion_ehci_init(unsigned long mapbase,
> enum orion_ehci_phy_ver phy_version)
> {
> orion_ehci_data.phy_version = phy_version;
> - fill_resources(_ehci, orion_ehci_resources, mapbase, SZ_4K - 1,
> + fill_resources_irq(_ehci, orion_ehci_resources, mapbase, SZ_4K -
> 1,
> irq);
>
> platform_device_register(_ehci);
> @@ -762,7 +768,7 @@ static struct platform_device orion_ehci_1 = {
> void __init orion_ehci_1_init(unsigned long mapbase,
> unsigned long irq)
> {
> - fill_resources(_ehci_1, orion_ehci_1_resources,
> + fill_resources_irq(_ehci_1, orion_ehci_1_resources,
> mapbase, SZ_4K - 1, irq);
>
> platform_device_register(_ehci_1);
> @@ -786,7 +792,7 @@ static struct platform_device orion_ehci_2 = {
> void __init orion_ehci_2_init(unsigned long mapbase,
> unsigned long irq)
> {
> - fill_resources(_ehci_2, orion_ehci_2_resources,
> + fill_resources_irq(_ehci_2, orion_ehci_2_resources,
> mapbase, SZ_4K - 1, irq);
>
> platform_device_register(_ehci_2);
> @@ -816,7 +822,7 @@ void __init orion_sata_init(struct mv_sata_platform_data
> *sata_data,
> unsigned long irq)
> {
> orion_sata.dev.platform_data = sata_data;
> - fill_resources(_sata, orion_sata_resources,
> + fill_resources_irq(_sata, orion_sata_resources,
> mapbase, 0x5000 - 1, irq);
>
> platform_device_register(_sata);
> @@ -846,7 +852,7 @@ void __init orion_crypto_init(unsigned long mapbase,
> unsigned long sram_size,
> unsigned long irq)
> {
> - fill_resources(_crypto, orion_crypto_resources,
> + fill_resources_irq(_crypto, orion_crypto_resources,
> mapbase, 0x, irq);
> orion_crypto.num_resources = 3;
> orion_crypto_resources[2].start = srambase;
> --
> 2.9.0
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH 4/4] ARM: orion5x: remove extraneous NO_IRQ
Hi Arnd,
On mar., sept. 06 2016, Arnd Bergmann <a...@arndb.de> wrote:
> rd88f6183ap-ge passes NO_IRQ as the interrupt line for its m25p80
> NOR flash. However, this device never uses an interrupt and the
> driver doesn't care, so we can simply remove the deprecated constant
> here.
>
> Signed-off-by: Arnd Bergmann <a...@arndb.de>
Applied on mvebu/soc with Reviewed-by tag from Andrew Lunn
Thanks,
Gregory
> ---
> arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
> b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
> index 4bf80dd5478c..8ffaead76771 100644
> --- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
> +++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
> @@ -71,7 +71,6 @@ static struct spi_board_info __initdata
> rd88f6183ap_ge_spi_slave_info[] = {
> {
> .modalias = "m25p80",
> .platform_data = _ge_spi_slave_data,
> - .irq= NO_IRQ,
> .max_speed_hz = 2000,
> .bus_num= 0,
> .chip_select= 0,
> --
> 2.9.0
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH 3/4] ARM: orion5x: avoid NO_IRQ in orion_ge00_switch_init
},
> -};
> -
> -static struct platform_device orion_switch_device = {
> - .name = "dsa",
> - .id = 0,
> - .num_resources = 0,
> - .resource = orion_switch_resources,
> -};
> -
> -void __init orion_ge00_switch_init(struct dsa_platform_data *d, int irq)
> +void __init orion_ge00_switch_init(struct dsa_platform_data *d)
> {
> int i;
>
> - if (irq != NO_IRQ) {
> - orion_switch_resources[0].start = irq;
> - orion_switch_resources[0].end = irq;
> - orion_switch_device.num_resources = 1;
> - }
> -
> d->netdev = _ge00.dev;
> for (i = 0; i < d->nr_chips; i++)
> d->chip[i].host_dev = _ge_mvmdio.dev;
> - orion_switch_device.dev.platform_data = d;
>
> - platform_device_register(_switch_device);
> + platform_device_register_data(NULL, "dsa", 0, d, sizeof(d));
> }
>
>
> /*
> diff --git a/arch/arm/plat-orion/include/plat/common.h
> b/arch/arm/plat-orion/include/plat/common.h
> index 8519727faa5e..9347f3c58a6d 100644
> --- a/arch/arm/plat-orion/include/plat/common.h
> +++ b/arch/arm/plat-orion/include/plat/common.h
> @@ -57,8 +57,7 @@ void __init orion_ge11_init(struct
> mv643xx_eth_platform_data *eth_data,
> unsigned long mapbase,
> unsigned long irq);
>
> -void __init orion_ge00_switch_init(struct dsa_platform_data *d,
> -int irq);
> +void __init orion_ge00_switch_init(struct dsa_platform_data *d);
>
> void __init orion_i2c_init(unsigned long mapbase,
> unsigned long irq,
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH 09/15] net: mvneta: use IS_ENABLED() instead of checking for built-in or module
Hi Javier,
On lun., sept. 12 2016, Javier Martinez Canillas <jav...@osg.samsung.com>
wrote:
> The IS_ENABLED() macro checks if a Kconfig symbol has been enabled either
> built-in or as a module, use that macro instead of open coding the same.
>
> Using the macro makes the code more readable by helping abstract away some
> of the Kconfig built-in and module enable details.
>
> Signed-off-by: Javier Martinez Canillas <jav...@osg.samsung.com>
Acked-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Thanks,
Gregory
> ---
>
> drivers/net/ethernet/marvell/mvneta_bm.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/marvell/mvneta_bm.h
> b/drivers/net/ethernet/marvell/mvneta_bm.h
> index e74fd44a92f7..a32de432800c 100644
> --- a/drivers/net/ethernet/marvell/mvneta_bm.h
> +++ b/drivers/net/ethernet/marvell/mvneta_bm.h
> @@ -133,7 +133,7 @@ struct mvneta_bm_pool {
> void *mvneta_frag_alloc(unsigned int frag_size);
> void mvneta_frag_free(unsigned int frag_size, void *data);
>
> -#if defined(CONFIG_MVNETA_BM) || defined(CONFIG_MVNETA_BM_MODULE)
> +#if IS_ENABLED(CONFIG_MVNETA_BM)
> void mvneta_bm_pool_destroy(struct mvneta_bm *priv,
> struct mvneta_bm_pool *bm_pool, u8 port_map);
> void mvneta_bm_bufs_free(struct mvneta_bm *priv, struct mvneta_bm_pool
> *bm_pool,
> --
> 2.7.4
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
[PATCH] clk: mvebu: armada-37xx-periph: Fix the clock provider registration
While trying using a peripheral clock on a driver, I saw that the clock
pointer returned by the provider was NULL.
The problem was a missing indirection. It was the pointer stored in the
hws array which needed to be updated not the value it contains.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/clk/mvebu/armada-37xx-periph.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/mvebu/armada-37xx-periph.c
b/drivers/clk/mvebu/armada-37xx-periph.c
index 45905fc0d75b..d5dfbad4ceab 100644
--- a/drivers/clk/mvebu/armada-37xx-periph.c
+++ b/drivers/clk/mvebu/armada-37xx-periph.c
@@ -305,7 +305,7 @@ static const struct of_device_id
armada_3700_periph_clock_of_match[] = {
};
static int armada_3700_add_composite_clk(const struct clk_periph_data *data,
void __iomem *reg, spinlock_t *lock,
-struct device *dev, struct clk_hw *hw)
+struct device *dev, struct clk_hw **hw)
{
const struct clk_ops *mux_ops = NULL, *gate_ops = NULL,
*rate_ops = NULL;
@@ -353,13 +353,13 @@ static int armada_3700_add_composite_clk(const struct
clk_periph_data *data,
}
}
- hw = clk_hw_register_composite(dev, data->name, data->parent_names,
+ *hw = clk_hw_register_composite(dev, data->name, data->parent_names,
data->num_parents, mux_hw,
mux_ops, rate_hw, rate_ops,
gate_hw, gate_ops, CLK_IGNORE_UNUSED);
- if (IS_ERR(hw))
- return PTR_ERR(hw);
+ if (IS_ERR(*hw))
+ return PTR_ERR(*hw);
return 0;
}
@@ -400,7 +400,7 @@ static int armada_3700_periph_clock_probe(struct
platform_device *pdev)
spin_lock_init(_data->lock);
for (i = 0; i < num_periph; i++) {
- struct clk_hw *hw = driver_data->hw_data->hws[i];
+ struct clk_hw **hw = _data->hw_data->hws[i];
if (armada_3700_add_composite_clk([i], reg,
_data->lock, dev, hw))
--
2.9.3
[PATCH] clk: mvebu: armada-37xx-periph: Fix the clock gate flag
For the gate part of the peripheral clock setting the bit disables the
clock and clearing it enables the clock. This is not the default behavior
of clk_gate component, so we need to use the CLK_GATE_SET_TO_DISABLE flag.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/clk/mvebu/armada-37xx-periph.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/mvebu/armada-37xx-periph.c
b/drivers/clk/mvebu/armada-37xx-periph.c
index d5dfbad4ceab..cecb0fdfaef6 100644
--- a/drivers/clk/mvebu/armada-37xx-periph.c
+++ b/drivers/clk/mvebu/armada-37xx-periph.c
@@ -329,6 +329,7 @@ static int armada_3700_add_composite_clk(const struct
clk_periph_data *data,
gate->lock = lock;
gate_ops = gate_hw->init->ops;
gate->reg = reg + (u64)gate->reg;
+ gate->flags = CLK_GATE_SET_TO_DISABLE;
}
if (data->rate_hw) {
--
2.9.3
[PATCH 3/10] mmc: sdhci: Export sdhci_execute_tuning() in sdhci.c
From: Ziji Hu <huz...@marvell.com>
Export sdhci_execute_tuning() from sdhci.c.
Thus vendor sdhci driver can execute its own tuning process.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Reviewed-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/mmc/host/sdhci.c | 3 ++-
drivers/mmc/host/sdhci.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 2250ea22231f..330119cd5a93 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1946,7 +1946,7 @@ static int sdhci_prepare_hs400_tuning(struct mmc_host
*mmc, struct mmc_ios *ios)
return 0;
}
-static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
+int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
{
struct sdhci_host *host = mmc_priv(mmc);
u16 ctrl;
@@ -2135,6 +2135,7 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32
opcode)
spin_unlock_irqrestore(>lock, flags);
return err;
}
+EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
static int sdhci_select_drive_strength(struct mmc_card *card,
unsigned int max_dtr, int host_drv,
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index c38ab65b9a97..035274ddea54 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -689,6 +689,7 @@ void sdhci_set_uhs_signaling(struct sdhci_host *host,
unsigned timing);
void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
struct mmc_ios *ios);
+int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
#ifdef CONFIG_PM
extern int sdhci_suspend_host(struct sdhci_host *host);
--
git-series 0.8.10
[PATCH 4/10] MAINTAINERS: add entry for Marvell Xenon MMC Host Controller drivers
From: Ziji Hu <huz...@marvell.com> Add maintainer entry for Marvell Xenon eMMC/SD/SDIO Host Controller drivers. Signed-off-by: Hu Ziji <huz...@marvell.com> Reviewed-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> --- MAINTAINERS | 5 + 1 file changed, 5 insertions(+), 0 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 207eaefd3b97..89adcd57aa25 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7578,6 +7578,11 @@ M: Nicolas Pitre <n...@fluxnic.net> S: Odd Fixes F: drivers/mmc/host/mvsdio.* +MARVELL XENON MMC/SD/SDIO HOST CONTROLLER DRIVER +M: Ziji Hu <huz...@marvell.com> +L: linux-...@vger.kernel.org +S: Supported + MATROX FRAMEBUFFER DRIVER L: linux-fb...@vger.kernel.org S: Orphan -- git-series 0.8.10
[PATCH 10/10] arm64: configs: enable SDHCI driver for Xenon
This patch enables the driver for the SDHCI controller found on the Marvell Armada 3700 and 7K/8K ARM64 SoCs. Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+), 0 deletions(-) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index dab2cb0c1f1c..2d1f5ee62b18 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -353,6 +353,7 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_EXYNOS=y CONFIG_MMC_DW_K3=y CONFIG_MMC_SUNXI=y +CONFIG_MMC_SDHCI_XENON=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y -- git-series 0.8.10
[PATCH 8/10] arm64: dts: marvell: add eMMC support for Armada 37xx
Add the eMMC support for Armada 37xx SoC and enable it in the Armada 3720
DB board.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 7 +++
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 11 +++
2 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index 1372e9a6aaa4..5b9cff4d5d7a 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -72,6 +72,13 @@
status = "okay";
};
+ {
+ non-removable;
+ bus-width = <8>;
+ xenon,pad-type = "fixed-1-8v";
+ status = "okay";
+};
+
/* CON31 */
{
status = "okay";
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index c4762538ec01..0c4cafe92e66 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -161,6 +161,17 @@
};
};
+ sdhci0: sdhci@d8000 {
+ compatible = "marvell,armada-3700-sdhci",
+ "marvell,sdhci-xenon";
+ reg = <0xd8000 0x300
+ 0x17808 0x4>;
+ interrupts = ;
+ clocks = <_perih_clk 0>;
+ clock-names = "core";
+ status = "disabled";
+ };
+
sata: sata@e {
compatible = "marvell,armada-3700-ahci";
reg = <0xe 0x2000>;
--
git-series 0.8.10
[PATCH 2/10] mmc: sdhci: Export sdhci_start_signal_voltage_switch() in sdhci.c
From: Ziji Hu <huz...@marvell.com>
Export sdhci_start_signal_voltage_switch() from sdhci.c.
Thus vendor sdhci driver can implement its own signal voltage
switch routine.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Reviewed-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/mmc/host/sdhci.c | 5 +++--
drivers/mmc/host/sdhci.h | 2 ++
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index d4bb818c52d5..2250ea22231f 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1828,8 +1828,8 @@ static void sdhci_enable_sdio_irq(struct mmc_host *mmc,
int enable)
spin_unlock_irqrestore(>lock, flags);
}
-static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
-struct mmc_ios *ios)
+int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
+ struct mmc_ios *ios)
{
struct sdhci_host *host = mmc_priv(mmc);
u16 ctrl;
@@ -1921,6 +1921,7 @@ static int sdhci_start_signal_voltage_switch(struct
mmc_host *mmc,
return 0;
}
}
+EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
static int sdhci_card_busy(struct mmc_host *mmc)
{
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 21dc80b8ae3d..c38ab65b9a97 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -687,6 +687,8 @@ void sdhci_set_bus_width(struct sdhci_host *host, int
width);
void sdhci_reset(struct sdhci_host *host, u8 mask);
void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
+int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
+ struct mmc_ios *ios);
#ifdef CONFIG_PM
extern int sdhci_suspend_host(struct sdhci_host *host);
--
git-series 0.8.10
[PATCH 7/10] mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC
From: Ziji Hu <huz...@marvell.com>
Marvell Xenon eMMC/SD/SDIO Host Controller contains PHY.
Three types of PHYs are supported.
Add support to multiple types of PHYs init and configuration.
Add register definitions of PHYs.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Reviewed-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
MAINTAINERS|1 +-
drivers/mmc/host/Makefile |2 +-
drivers/mmc/host/sdhci-xenon-phy.c | 1141 +-
drivers/mmc/host/sdhci-xenon-phy.h | 157 -
drivers/mmc/host/sdhci-xenon.c |4 +-
drivers/mmc/host/sdhci-xenon.h | 17 +-
6 files changed, 1321 insertions(+), 1 deletion(-)
create mode 100644 drivers/mmc/host/sdhci-xenon-phy.c
create mode 100644 drivers/mmc/host/sdhci-xenon-phy.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 859420e5dfd3..b5673c2ee5f2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7583,6 +7583,7 @@ M:Ziji Hu <huz...@marvell.com>
L: linux-...@vger.kernel.org
S: Supported
F: drivers/mmc/host/sdhci-xenon.*
+F: drivers/mmc/host/sdhci-xenon-phy.*
F: Documentation/devicetree/bindings/mmc/marvell,sdhci-xenon.txt
MATROX FRAMEBUFFER DRIVER
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 75eaf743486c..4f2854556ff7 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -82,4 +82,4 @@ ifeq ($(CONFIG_CB710_DEBUG),y)
endif
obj-$(CONFIG_MMC_SDHCI_XENON) += sdhci-xenon-driver.o
-sdhci-xenon-driver-y += sdhci-xenon.o
+sdhci-xenon-driver-y += sdhci-xenon.o sdhci-xenon-phy.o
diff --git a/drivers/mmc/host/sdhci-xenon-phy.c
b/drivers/mmc/host/sdhci-xenon-phy.c
new file mode 100644
index ..4eb8fea1bec9
--- /dev/null
+++ b/drivers/mmc/host/sdhci-xenon-phy.c
@@ -0,0 +1,1141 @@
+/*
+ * PHY support for Xenon SDHC
+ *
+ * Copyright (C) 2016 Marvell, All Rights Reserved.
+ *
+ * Author: Hu Ziji <huz...@marvell.com>
+ * Date: 2016-8-24
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "sdhci.h"
+#include "sdhci-pltfm.h"
+#include "sdhci-xenon.h"
+
+static const char * const phy_types[] = {
+ "sdh phy",
+ "emmc 5.0 phy",
+ "emmc 5.1 phy"
+};
+
+enum phy_type_enum {
+ SDH_PHY,
+ EMMC_5_0_PHY,
+ EMMC_5_1_PHY,
+ NR_PHY_TYPES
+};
+
+struct soc_pad_ctrl_table {
+ const char *soc;
+ void (*set_soc_pad)(struct sdhci_host *host,
+ unsigned char signal_voltage);
+};
+
+struct soc_pad_ctrl {
+ /* Register address of SOC PHY PAD ctrl */
+ void __iomem*reg;
+ /* SOC PHY PAD ctrl type */
+ enum soc_pad_ctrl_type pad_type;
+ /* SOC specific operation to set SOC PHY PAD */
+ void (*set_soc_pad)(struct sdhci_host *host,
+ unsigned char signal_voltage);
+};
+
+static struct xenon_emmc_phy_regs xenon_emmc_5_0_phy_regs = {
+ .timing_adj = EMMC_5_0_PHY_TIMING_ADJUST,
+ .func_ctrl = EMMC_5_0_PHY_FUNC_CONTROL,
+ .pad_ctrl = EMMC_5_0_PHY_PAD_CONTROL,
+ .pad_ctrl2 = EMMC_5_0_PHY_PAD_CONTROL2,
+ .dll_ctrl = EMMC_5_0_PHY_DLL_CONTROL,
+ .logic_timing_adj = EMMC_5_0_PHY_LOGIC_TIMING_ADJUST,
+ .delay_mask = EMMC_5_0_PHY_FIXED_DELAY_MASK,
+ .dll_update = DLL_UPDATE_STROBE_5_0,
+};
+
+static struct xenon_emmc_phy_regs xenon_emmc_5_1_phy_regs = {
+ .timing_adj = EMMC_PHY_TIMING_ADJUST,
+ .func_ctrl = EMMC_PHY_FUNC_CONTROL,
+ .pad_ctrl = EMMC_PHY_PAD_CONTROL,
+ .pad_ctrl2 = EMMC_PHY_PAD_CONTROL2,
+ .dll_ctrl = EMMC_PHY_DLL_CONTROL,
+ .logic_timing_adj = EMMC_PHY_LOGIC_TIMING_ADJUST,
+ .delay_mask = EMMC_PHY_FIXED_DELAY_MASK,
+ .dll_update = DLL_UPDATE,
+};
+
+static int xenon_delay_adj_test(struct mmc_card *card);
+
+/*
+ * eMMC PHY configuration and operations
+ */
+struct emmc_phy_params {
+ boolslow_mode;
+
+ u8 znr;
+ u8 zpr;
+
+ /* Nr of consecutive Sampling Points of a Valid Sampling Window */
+ u8 nr_tun_times;
+ /* Divider for calculating Tuning Step */
+ u8 tun_step_divider;
+
+ struct soc_pad_ctrl pad_ctrl;
+};
+
+static void xenon_emmc_phy_strobe_delay_adj(struct sdhci_host *host,
+ struct mmc_card *card);
+static int xenon_emmc_phy_fix_sampl_delay_adj(struct sdhci_host *host,
+ struct mmc_card *card);
+static void xenon_emmc_phy
[PATCH 0/10] mmc: Add support to Marvell Xenon SD Host Controller
Hello, This series adds support for the SDHCI Xenon controller which can be currently found on the Armada 37xx and the Armada 7K/8K but will be also used in more Marvell SoC (and not only the mvebu ones actually). A few months ago a series has been sent to support this controller: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-June/434925.html However, since this first version, the engineer team in charge of this controller wished to have a better involvement in the mainline support of the driver. This new series is the result the Marvell development with the aim of supporting more feature that only the ones needed for the Armada 3720 SoC. About the hardware and the driver itself, according to Ziji Hu: "Marvell Xenon SDHC is widely used in Marvell products. It supports SD/SDIO/eMMC. It conforms to SD Physical Layer Specification Version 3.01 and is designed according to the guidelines provided in the SD Host Controller Standard Specification Version 3.00. Xenon SDHC IP contains PHY. There are tree types of Xenon PHY in use. Each Xenon SDHC only contain one type of PHY." Thanks, Gregory Gregory CLEMENT (3): arm64: dts: marvell: add eMMC support for Armada 37xx arm64: dts: marvell: add sdhci support for Armada 7K/8K arm64: configs: enable SDHCI driver for Xenon Ziji Hu (7): mmc: sdhci: Export sdhci_set_ios() from sdhci.c mmc: sdhci: Export sdhci_start_signal_voltage_switch() in sdhci.c mmc: sdhci: Export sdhci_execute_tuning() in sdhci.c MAINTAINERS: add entry for Marvell Xenon MMC Host Controller drivers dt: bindings: Add bindings for Marvell Xenon SD Host Controller mmc: sdhci-xenon: Add Marvell Xenon SDHC core functionality mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC Documentation/devicetree/bindings/mmc/marvell,sdhci-xenon.txt | 164 +- MAINTAINERS |8 +- arch/arm64/boot/dts/marvell/armada-3720-db.dts|7 +- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 11 +- arch/arm64/boot/dts/marvell/armada-7040-db.dts|7 +- arch/arm64/boot/dts/marvell/armada-ap806.dtsi |9 +- arch/arm64/configs/defconfig |1 +- drivers/mmc/host/Kconfig |9 +- drivers/mmc/host/Makefile |3 +- drivers/mmc/host/sdhci-xenon-phy.c| 1141 +++- drivers/mmc/host/sdhci-xenon-phy.h| 157 +- drivers/mmc/host/sdhci-xenon.c| 603 - drivers/mmc/host/sdhci-xenon.h| 151 +- drivers/mmc/host/sdhci.c | 11 +- drivers/mmc/host/sdhci.h |4 +- 15 files changed, 2282 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/mmc/marvell,sdhci-xenon.txt create mode 100644 drivers/mmc/host/sdhci-xenon-phy.c create mode 100644 drivers/mmc/host/sdhci-xenon-phy.h create mode 100644 drivers/mmc/host/sdhci-xenon.c create mode 100644 drivers/mmc/host/sdhci-xenon.h base-commit: 32b7d4a95f79deb8b73e8b303a54dfdef4a3d845 -- git-series 0.8.10
[PATCH 9/10] arm64: dts: marvell: add sdhci support for Armada 7K/8K
Also enable it on the Armada 7040 DB board
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 7 +++
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 9 +
2 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index 070b589680c5..f7f978a12a49 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -146,3 +146,10 @@
_usb3_1 {
status = "okay";
};
+
+ {
+ status = "okay";
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index 7b6136182ad0..ef2ce6be7205 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -229,6 +229,15 @@
};
+ sdhci0: sdhci@6e {
+ compatible = "marvell,sdhci-xenon";
+ reg = <0x6e 0x300>;
+ interrupts = ;
+ clock-names = "core";
+ clocks = <_syscon0 1 4>;
+ status = "disabled";
+ };
+
ap_syscon: system-controller@6f4000 {
compatible = "marvell,ap806-system-controller",
"syscon";
--
git-series 0.8.10
[PATCH 5/10] dt: bindings: Add bindings for Marvell Xenon SD Host Controller
From: Ziji Hu <huz...@marvell.com> Marvell Xenon SDHC can support eMMC/SD/SDIO. Add Xenon-specific properties. Also add properties for Xenon PHY setting. Signed-off-by: Hu Ziji <huz...@marvell.com> Reviewed-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> --- Documentation/devicetree/bindings/mmc/marvell,sdhci-xenon.txt | 164 +++- MAINTAINERS | 1 +- 2 files changed, 165 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/mmc/marvell,sdhci-xenon.txt diff --git a/Documentation/devicetree/bindings/mmc/marvell,sdhci-xenon.txt b/Documentation/devicetree/bindings/mmc/marvell,sdhci-xenon.txt new file mode 100644 index ..8b25ad28ebbd --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/marvell,sdhci-xenon.txt @@ -0,0 +1,164 @@ +Marvell's Xenon SDHCI Controller device tree bindings +This file documents differences between the core mmc properties +described by mmc.txt and the properties used by the Xenon implementation. + +A single Xenon IP can support multiple slots. +Each slot acts as an independent SDHC. It owns independent resources, such +as register sets clock and PHY. +Each slot should have an independent device tree node. + +Required Properties: +- compatible: should be "marvell,sdhci-xenon" or "marvell,armada-3700-sdhci". + +- Input Clock Name + Some SOCs require additional clock for AXI bus. + The input clock for Xenon IP core should be named as "core". + The optional AXI clock should be named as "axi". + - clocks = <_clk>, <_clock>; + - clock-names = "core", "axi"; + +- Register Set Size + Different Xenon SDHC release has different register set size. + The specific size should also refer to the SOC implementation. + +Optional Properties: +- Slot Index + A single Xenon IP can support multiple slots. + During initialization, each slot should set corresponding setting bit in + some Xenon-specific registers. The corresponding bit is determined by + this property. + - xenon,slotno = ; + If this property is not provided, Xenon IP should contain only one slot + and the slot index will be 0x0 by default. + +- PHY Type + Xenon support mutilple types of PHYs. + To select eMMC 5.1 PHY, set: + - xenon,phy-type = "emmc 5.1 phy" + eMMC 5.1 PHY is the default choice if this property is not provided. + To select eMMC 5.0 PHY, set: + - xenon,phy-type = "emmc 5.0 phy" + To select SDH PHY, set: + - xenon,phy-type = "sdh phy" + Please note that eMMC PHY is a general PHY for eMMC/SD/SDIO, other than for + eMMC only. + +- Customized eMMC PHY Parameters + Some boards require different values of some specific eMMC PHY parameters. + Some SOCs also require specific workaround to set eMMC PHY. + These properties enable diverse boards to customize the eMMC PHY. + The supported eMMC PHY parameters are listed in below. All those properties + are only available for eMMC PHY 5.1 and eMMC PHY 5.0. + ZNR + valid range = [0:0x1F]. + ZNR is set as 0xF by default if this property is not provided. + - xenon,phy-znr = ; + + ZPR + valid range = [0:0x1F]. + ZPR is set as 0xF by default if this property is not provided. + - xenon,phy-zpr = ; + + Number of successful tuning times + Set the number of required consecutive successful sampling points used to + identify a valid sampling window, in tuning process. + Valid range = [1:7]. Set as 0x4 by default if this property is not provided. + - xenon,phy-nr-tun-times = ; + + Divider for TUN_STEP + Set the divider for calculating TUN_STEP. + Set as 64 by default if this property is not provided. + - xenon,phy-tun-step-divider = ; + + Force PHY into slow mode. + Only available when bus frequency lower than 50MHz in SDR mde. + Disabled by default. Please do not enable it unless it is necessary. + - xenon,phy-slow-mode; + +- Mask Conflict Error Report + Disable Conflict Error alert on some SOC. Disabled by default. + xenon,mask-conflict-err; + +- Re-tuning Counter + Xenon SDHC SOC usually doesn't provide re-tuning counter in + Capabilities Register 3 Bit[11:8]. + This property provides the re-tuning counter. + xenon,tuning-count = ; + If this property is not set, default re-tuning counter will + be set as 0x9 in driver. + +- SOC PHY PAD Voltage Control register + Some SOCs have SOC PHY PAD Voltage Control register outside Xenon IP. + This register sets SOC PHY PAD Voltage to keep aligh with Vccq. + Two properties provide information of this control register. + These two properties are only valid when "marvell,armada-3700-sdhci" + is selected. Both of them must be provided when "marvell,armada-3700-sdhci" + is selected. + - xenon,pad-type +Two types: "sd" and "fixed-1-8v". +If
[PATCH 1/10] mmc: sdhci: Export sdhci_set_ios() from sdhci.c
From: Ziji Hu <huz...@marvell.com>
Export sdhci_set_ios() in sdhci.c.
Thus vendor sdhci driver can implement its own set_ios() routine.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Reviewed-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/mmc/host/sdhci.c | 3 ++-
drivers/mmc/host/sdhci.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 48055666c655..d4bb818c52d5 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1562,7 +1562,7 @@ void sdhci_set_uhs_signaling(struct sdhci_host *host,
unsigned timing)
}
EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
-static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
struct sdhci_host *host = mmc_priv(mmc);
unsigned long flags;
@@ -1719,6 +1719,7 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct
mmc_ios *ios)
mmiowb();
spin_unlock_irqrestore(>lock, flags);
}
+EXPORT_SYMBOL_GPL(sdhci_set_ios);
static int sdhci_get_cd(struct mmc_host *mmc)
{
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index c722cd23205c..21dc80b8ae3d 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -686,6 +686,7 @@ void sdhci_set_power(struct sdhci_host *host, unsigned char
mode,
void sdhci_set_bus_width(struct sdhci_host *host, int width);
void sdhci_reset(struct sdhci_host *host, u8 mask);
void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
+void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
#ifdef CONFIG_PM
extern int sdhci_suspend_host(struct sdhci_host *host);
--
git-series 0.8.10
[PATCH 6/10] mmc: sdhci-xenon: Add Marvell Xenon SDHC core functionality
From: Ziji Hu <huz...@marvell.com>
Add Xenon eMMC/SD/SDIO host controller core functionality.
Add Xenon specific intialization process.
Add Xenon specific mmc_host_ops APIs.
Add Xenon specific register definitions.
Add CONFIG_MMC_SDHCI_XENON support in drivers/mmc/host/Kconfig.
Marvell Xenon SDHC conforms to SD Physical Layer Specification
Version 3.01 and is designed according to the guidelines provided
in the SD Host Controller Standard Specification Version 3.00.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Reviewed-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
MAINTAINERS| 1 +-
drivers/mmc/host/Kconfig | 9 +-
drivers/mmc/host/Makefile | 3 +-
drivers/mmc/host/sdhci-xenon.c | 599 ++-
drivers/mmc/host/sdhci-xenon.h | 134 -
5 files changed, 746 insertions(+), 0 deletions(-)
create mode 100644 drivers/mmc/host/sdhci-xenon.c
create mode 100644 drivers/mmc/host/sdhci-xenon.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 4aa0eac9bfc7..859420e5dfd3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7582,6 +7582,7 @@ MARVELL XENON MMC/SD/SDIO HOST CONTROLLER DRIVER
M: Ziji Hu <huz...@marvell.com>
L: linux-...@vger.kernel.org
S: Supported
+F: drivers/mmc/host/sdhci-xenon.*
F: Documentation/devicetree/bindings/mmc/marvell,sdhci-xenon.txt
MATROX FRAMEBUFFER DRIVER
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 5274f503a39a..85a53623526a 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -798,3 +798,12 @@ config MMC_SDHCI_BRCMSTB
Broadcom STB SoCs.
If unsure, say Y.
+
+config MMC_SDHCI_XENON
+ tristate "Marvell Xenon eMMC/SD/SDIO SDHCI driver"
+ depends on MMC_SDHCI && MMC_SDHCI_PLTFM
+ help
+ This selects Marvell Xenon eMMC/SD/SDIO SDHCI.
+ If you have a machine with integrated Marvell Xenon SDHC IP,
+ say Y or M here.
+ If unsure, say N.
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index e2bdaaf43184..75eaf743486c 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -80,3 +80,6 @@ obj-$(CONFIG_MMC_SDHCI_BRCMSTB) +=
sdhci-brcmstb.o
ifeq ($(CONFIG_CB710_DEBUG),y)
CFLAGS-cb710-mmc+= -DDEBUG
endif
+
+obj-$(CONFIG_MMC_SDHCI_XENON) += sdhci-xenon-driver.o
+sdhci-xenon-driver-y += sdhci-xenon.o
diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c
new file mode 100644
index ..03ba183494d3
--- /dev/null
+++ b/drivers/mmc/host/sdhci-xenon.c
@@ -0,0 +1,599 @@
+/*
+ * Driver for Marvell SOC Platform Group Xenon SDHC as a platform device
+ *
+ * Copyright (C) 2016 Marvell, All Rights Reserved.
+ *
+ * Author: Hu Ziji <huz...@marvell.com>
+ * Date: 2016-8-24
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * Inspired by Jisheng Zhang <jszh...@marvell.com>
+ * Special thanks to Video BG4 project team.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "sdhci-pltfm.h"
+#include "sdhci.h"
+#include "sdhci-xenon.h"
+
+/* Set SDCLK-off-while-idle */
+static void xenon_set_sdclk_off_idle(struct sdhci_host *host,
+unsigned char slot_idx, bool enable)
+{
+ u32 reg;
+ u32 mask;
+
+ reg = sdhci_readl(host, SDHC_SYS_OP_CTRL);
+ /* Get the bit shift basing on the slot index */
+ mask = (0x1 << (SDCLK_IDLEOFF_ENABLE_SHIFT + slot_idx));
+ if (enable)
+ reg |= mask;
+ else
+ reg &= ~mask;
+
+ sdhci_writel(host, reg, SDHC_SYS_OP_CTRL);
+}
+
+/* Enable/Disable the Auto Clock Gating function */
+static void xenon_set_acg(struct sdhci_host *host, bool enable)
+{
+ u32 reg;
+
+ reg = sdhci_readl(host, SDHC_SYS_OP_CTRL);
+ if (enable)
+ reg &= ~AUTO_CLKGATE_DISABLE_MASK;
+ else
+ reg |= AUTO_CLKGATE_DISABLE_MASK;
+ sdhci_writel(host, reg, SDHC_SYS_OP_CTRL);
+}
+
+/* Enable this slot */
+static void xenon_enable_slot(struct sdhci_host *host,
+ unsigned char slot_idx)
+{
+ u32 reg;
+
+ reg = sdhci_readl(host, SDHC_SYS_OP_CTRL);
+ reg |= (BIT(slot_idx) << SLOT_ENABLE_SHIFT);
+ sdhci_writel(host, reg, SDHC_SYS_OP_CTRL);
+
+ /*
+* Manually set the flag which all the slots require,
+* including SD, eMMC, SDIO
+*/
+ host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
+}
+
+/* Disable this slot */
+static void xenon_disable_sl
Re: [PATCH] clk: mvebu: armada-37xx-periph: Fix the clock provider registration
Hi Stephen and Mike
On jeu., sept. 29 2016, Gregory CLEMENT <gregory.clem...@free-electrons.com>
wrote:
> While trying using a peripheral clock on a driver, I saw that the clock
> pointer returned by the provider was NULL.
>
> The problem was a missing indirection. It was the pointer stored in the
> hws array which needed to be updated not the value it contains.
>
> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
I saw that you already did the pull request for the clk subsystem.
Do you consider to do a another pull request for the fixes?
It would be nice to have this driver working since the rc1 :)
For this driver an other fix is needed:
http://lists.infradead.org/pipermail/linux-arm-kernel/2016-September/459640.html
Thanks!
Gregory
> ---
> drivers/clk/mvebu/armada-37xx-periph.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/clk/mvebu/armada-37xx-periph.c
> b/drivers/clk/mvebu/armada-37xx-periph.c
> index 45905fc0d75b..d5dfbad4ceab 100644
> --- a/drivers/clk/mvebu/armada-37xx-periph.c
> +++ b/drivers/clk/mvebu/armada-37xx-periph.c
> @@ -305,7 +305,7 @@ static const struct of_device_id
> armada_3700_periph_clock_of_match[] = {
> };
> static int armada_3700_add_composite_clk(const struct clk_periph_data *data,
>void __iomem *reg, spinlock_t *lock,
> - struct device *dev, struct clk_hw *hw)
> + struct device *dev, struct clk_hw **hw)
> {
> const struct clk_ops *mux_ops = NULL, *gate_ops = NULL,
> *rate_ops = NULL;
> @@ -353,13 +353,13 @@ static int armada_3700_add_composite_clk(const struct
> clk_periph_data *data,
> }
> }
>
> - hw = clk_hw_register_composite(dev, data->name, data->parent_names,
> + *hw = clk_hw_register_composite(dev, data->name, data->parent_names,
> data->num_parents, mux_hw,
> mux_ops, rate_hw, rate_ops,
> gate_hw, gate_ops, CLK_IGNORE_UNUSED);
>
> - if (IS_ERR(hw))
> - return PTR_ERR(hw);
> + if (IS_ERR(*hw))
> + return PTR_ERR(*hw);
>
> return 0;
> }
> @@ -400,7 +400,7 @@ static int armada_3700_periph_clock_probe(struct
> platform_device *pdev)
> spin_lock_init(_data->lock);
>
> for (i = 0; i < num_periph; i++) {
> - struct clk_hw *hw = driver_data->hw_data->hws[i];
> + struct clk_hw **hw = _data->hw_data->hws[i];
>
> if (armada_3700_add_composite_clk([i], reg,
> _data->lock, dev, hw))
> --
> 2.9.3
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH] clk: mvebu: Add clk support for the orion5x SoC mv88f5181
Hi Stephen, On mar., sept. 20 2016, Stephen Boyd <sb...@codeaurora.org> wrote: > On 09/20, Gregory CLEMENT wrote: >> From: Jamie Lentin <j...@lentin.co.uk> >> >> Referring to the u-boot sources for the Netgear WNR854T, add support >> for the mv88f5181. >> >> [gregory.clem...@free-electrons.com: fix commit title] >> Signed-off-by: Jamie Lentin <j...@lentin.co.uk> >> Reviewed-by: Andrew Lunn <and...@lunn.ch> >> Acked-by: Rob Herring <r...@kernel.org> >> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> >> --- >> >> Hi Stephen and Mike, >> >> do you agree to give your acked-by on this patch. It is part of a >> convertion of old orion5x Socv to the device tree. If you acked-by >> this one, then I will be able to take it in my tree and avoiding >> breaking the git bisect. > > Is the problem that we're changing some dts files somewhere and > those platforms would stop booting if this change wasn't present? > Given that we're adding a new compatible it seems like we're > adding new SoC support, so having the clk patch and the dts patch > come together in -next via a merge instead of basing the dts > patch on top of the clk patch would be how things are normally > done. The problem appear if the dts for the board using the clock driver is merged in Linus tree before the support in the driver. At this point the board won't be able to boot. It introduces a hole in the git bisect between the merge of the clock subsystem and the arm-soc subsystem. > > If we're really changing some dts to be backwards incompatible, > then I understand the bisect problem and you can have my ack. > > Acked-by: Stephen Boyd <sb...@codeaurora.org. Thanks, Gregory > > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > a Linux Foundation Collaborative Project -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
[PATCH] clk: mvebu: Add clk support for the orion5x SoC mv88f5181
From: Jamie Lentin <j...@lentin.co.uk>
Referring to the u-boot sources for the Netgear WNR854T, add support
for the mv88f5181.
[gregory.clem...@free-electrons.com: fix commit title]
Signed-off-by: Jamie Lentin <j...@lentin.co.uk>
Reviewed-by: Andrew Lunn <and...@lunn.ch>
Acked-by: Rob Herring <r...@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
Hi Stephen and Mike,
do you agree to give your acked-by on this patch. It is part of a
convertion of old orion5x Socv to the device tree. If you acked-by
this one, then I will be able to take it in my tree and avoiding
breaking the git bisect.
This patch is really about adding a new variant, teh logic remains the
same and also it won't produce any conflict.
Sorry to not have asked this before.
Thanks,
Gregory
.../devicetree/bindings/clock/mvebu-core-clock.txt | 1 +
drivers/clk/mvebu/orion.c | 70 ++
2 files changed, 71 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
index 670c2af3e931..eb985a633d59 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
@@ -52,6 +52,7 @@ Required properties:
"marvell,dove-core-clock" - for Dove SoC core clocks
"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
+ "marvell,mv88f5181-core-clock" - for Orion MV88F5181 SoC
"marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC
"marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC
"marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC
diff --git a/drivers/clk/mvebu/orion.c b/drivers/clk/mvebu/orion.c
index fd129566c1ce..a6e5bee23385 100644
--- a/drivers/clk/mvebu/orion.c
+++ b/drivers/clk/mvebu/orion.c
@@ -21,6 +21,76 @@ static const struct coreclk_ratio orion_coreclk_ratios[]
__initconst = {
};
/*
+ * Orion 5181
+ */
+
+#define SAR_MV88F5181_TCLK_FREQ 8
+#define SAR_MV88F5181_TCLK_FREQ_MASK 0x3
+
+static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar)
+{
+ u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) &
+ SAR_MV88F5181_TCLK_FREQ_MASK;
+ if (opt == 0)
+ return 1;
+ else if (opt == 1)
+ return 15000;
+ else if (opt == 2)
+ return 16667;
+ else
+ return 0;
+}
+
+#define SAR_MV88F5181_CPU_FREQ 4
+#define SAR_MV88F5181_CPU_FREQ_MASK 0xf
+
+static u32 __init mv88f5181_get_cpu_freq(void __iomem *sar)
+{
+ u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
+ SAR_MV88F5181_CPU_FREQ_MASK;
+ if (opt == 0)
+ return 3;
+ else if (opt == 1 || opt == 2)
+ return 4;
+ else if (opt == 3)
+ return 5;
+ else
+ return 0;
+}
+
+static void __init mv88f5181_get_clk_ratio(void __iomem *sar, int id,
+ int *mult, int *div)
+{
+ u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
+ SAR_MV88F5181_CPU_FREQ_MASK;
+ if (opt == 0 || opt == 1) {
+ *mult = 1;
+ *div = 2;
+ } else if (opt == 2 || opt == 3) {
+ *mult = 1;
+ *div = 3;
+ } else {
+ *mult = 0;
+ *div = 1;
+ }
+}
+
+static const struct coreclk_soc_desc mv88f5181_coreclks = {
+ .get_tclk_freq = mv88f5181_get_tclk_freq,
+ .get_cpu_freq = mv88f5181_get_cpu_freq,
+ .get_clk_ratio = mv88f5181_get_clk_ratio,
+ .ratios = orion_coreclk_ratios,
+ .num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
+};
+
+static void __init mv88f5181_clk_init(struct device_node *np)
+{
+ return mvebu_coreclk_setup(np, _coreclks);
+}
+
+CLK_OF_DECLARE(mv88f5181_clk, "marvell,mv88f5181-core-clock",
mv88f5181_clk_init);
+
+/*
* Orion 5182
*/
--
2.9.3
Re: [PATCH 2/2] arm64: dts: marvell: fix clocksource for CP110 slave SPI0
Hi Olof and Arnd,
On mar., sept. 06 2016, Marcin Wojtas <m...@semihalf.com> wrote:
> I2C and SPI interfaces share common clock trees within the CP110 HW block.
> It occurred that SPI0 interface has wrong clock assignment in the device
> tree, which is fixed in this commit to a proper value.
>
> Fixes: c749b8d9de32 ("arm64: dts: marvell: add description for the ...")
> Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Acked-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Could you take this patch for 4.9? I didn't realized at first view it
was for 4.9, I though I could put it the PR for fixes for 4.8.
I can do a new PR for dt64 with this single patch if you prefer.
The last option will be to have it as a fix for v4.9-rc2.
Thanks,
Gregory
> ---
> arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
> b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
> index 37bff70..150675c 100644
> --- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
> @@ -133,7 +133,7 @@
> #address-cells = <0x1>;
> #size-cells = <0x0>;
> cell-index = <1>;
> - clocks = <_syscon0 0 3>;
> + clocks = <_syscon0 1 21>;
> status = "disabled";
> };
>
> --
> 1.8.3.1
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH 1/2] arm64: dts: marvell: fix clocksource for CP110 master SPI0
Hi Marcin,
On mar., sept. 06 2016, Marcin Wojtas <m...@semihalf.com> wrote:
> I2C and SPI interfaces share common clock trees within the CP110 HW block.
> It occurred that SPI0 interface has wrong clock assignment in the device
> tree, which is fixed in this commit to a proper value.
>
> Fixes: 728dacc7f4dd ("arm64: dts: marvell: initial DT description of ...")
> Signed-off-by: Marcin Wojtas <m...@semihalf.com>
> CC: <sta...@vger.kernel.org> v4.7+
Applied on mvebu/fixes
Thanks,
Gregory
> ---
> arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
> b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
> index db1be4c..903b0f6 100644
> --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
> @@ -133,7 +133,7 @@
> #address-cells = <0x1>;
> #size-cells = <0x0>;
> cell-index = <1>;
> - clocks = <_syscon0 0 3>;
> + clocks = <_syscon0 1 21>;
> status = "disabled";
> };
>
> --
> 1.8.3.1
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH 4/4] arm64: dts: marvell: describe the PIC and PMU on Armada 7K/8K
Hi Thomas,
On ven., août 05 2016, Thomas Petazzoni <thomas.petazz...@free-electrons.com>
wrote:
> This commit adds the necessary Device Tree description for the PIC
> interrupt controller and the PMU available in the Marvell Armada 7K and
> Armada 8K SoCs.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
Applied on mvebu/dt64
Thanks,
Gregory
> ---
> arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
> b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
> index eab1a42..e70b996 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
> @@ -128,6 +128,12 @@
> (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
> };
>
> + pmu {
> + compatible = "arm,cortex-a72-pmu";
> + interrupt-parent = <>;
> + interrupts = <17>;
> + };
> +
> odmi: odmi@30 {
> compatible = "marvell,odmi-controller";
> interrupt-controller;
> @@ -140,6 +146,14 @@
> marvell,spi-base = <128>, <136>, <144>, <152>;
> };
>
> + pic: interrupt-controller@3f0100 {
> + compatible = "marvell,armada-8k-pic";
> + reg = <0x3f0100 0x10>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + interrupts = ;
> + };
> +
> xor@40 {
> compatible = "marvell,armada-7k-xor",
> "marvell,xor-v2";
> reg = <0x40 0x1000>,
> --
> 2.7.4
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [Regression?] Commit cb4f71c429 deliberately changes order of network interfaces
wer be? "We did it last time, but not this >> time." or "Ok, but gosh-darnit, this is the last time." >> > > If you use the ordering by address as main argument for the revert there > will be nothing to argue about. > >> To be blunt, I think our best path forward is to just hold our noses >> and let it stand as is. Some will fix their userspace to adapt, >> others will carry a patch. It's more important at this point to be >> consistent moving forward. It's better to hear "Yeah, it fucking >> changed once." rather than "I don't know what to expect, it changes >> every few releases." >> >> thx, >> >> Jason. >> >> >> [1] CDO: OCD with the letters neatly arranged in alphabetical order. > > Thanks for sharing your thoughts > > Regards > Ralph -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Re: [PATCH] ARM: dts: armada-38x: Add NAND pinctrl information
Hi Chris,
On mer., août 24 2016, Chris Packham <chris.pack...@alliedtelesis.co.nz> wrote:
> Add pin control information for the NAND flash interface. This interface
> is multiplexed with the device bus interface to the function is "dev"
> not "nand" as one might expect.
>
> Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
Applied on mvebu/dt
Thanks,
Gregory
> ---
> arch/arm/boot/dts/armada-38x.dtsi | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm/boot/dts/armada-38x.dtsi
> b/arch/arm/boot/dts/armada-38x.dtsi
> index 3312be6c82cc..30381d421d43 100644
> --- a/arch/arm/boot/dts/armada-38x.dtsi
> +++ b/arch/arm/boot/dts/armada-38x.dtsi
> @@ -287,6 +287,15 @@
> marvell,function = "spi1";
> };
>
> + nand_pins: nand-pins {
> + marvell,pins = "mpp22", "mpp34",
> "mpp23",
> +"mpp33", "mpp38",
> "mpp28",
> +"mpp40", "mpp42",
> "mpp35",
> +"mpp36", "mpp25",
> "mpp30",
> +"mpp32";
> + marvell,function = "dev";
> + };
> +
> uart0_pins: uart-pins-0 {
> marvell,pins = "mpp0", "mpp1";
> marvell,function = "ua0";
> --
> 2.9.2.518.ged577c6.dirty
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH] ARM: dts: mvebu: fix reference to a390 spi controller
Hi Arnd,
On ven., août 26 2016, Arnd Bergmann <a...@arndb.de> wrote:
> The SPI controller in the arch/arm/boot/dts/armada-39x.dtsi file has moved
> to a different location in the hierarchy, which breaks the overrides
> in the board specific file:
>
> Warning (reg_format): "reg" property in
> /soc/internal-regs/spi@10680/spi-flash@1 has invalid length (4 bytes)
> (#address-cells == 2, #size-cells == 1)
> Warning (avoid_default_addr_size): Relying on default #address-cells value
> for /soc/internal-regs/spi@10680/spi-flash@1
>
> This changes the board to reference the spi controller by its label
> (which has not changed) rather than the full path.
>
> Signed-off-by: Arnd Bergmann <a...@arndb.de>
> Fixes: 0160a4b68987 ("ARM: dts: mvebu: A37x/XP/38x/39x: Move SPI controller
> nodes into 'soc' node")
Applied on mvebu/dt
Thanks,
Gregory
> ---
> arch/arm/boot/dts/armada-390-db.dts | 60
> ++---
> 1 file changed, 30 insertions(+), 30 deletions(-)
>
> diff --git a/arch/arm/boot/dts/armada-390-db.dts
> b/arch/arm/boot/dts/armada-390-db.dts
> index 9d0d9b2e9bfc..34e279d973c8 100644
> --- a/arch/arm/boot/dts/armada-390-db.dts
> +++ b/arch/arm/boot/dts/armada-390-db.dts
> @@ -66,36 +66,6 @@
> MBUS_ID(0x01, 0x1d) 0 0xfff0 0x10>;
>
> internal-regs {
> - spi@10680 {
> - status = "okay";
> - pinctrl-0 = <_pins>;
> - pinctrl-names = "default";
> -
> - spi-flash@1 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - compatible = "n25q128a13",
> - "jedec,spi-nor";
> - reg = <0>; /* Chip select 0 */
> - spi-max-frequency = <10800>;
> -
> - partitions {
> - compatible = "fixed-partitions";
> - #address-cells = <1>;
> - #size-cells = <1>;
> -
> - partition@0 {
> - label = "U-Boot";
> - reg = <0 0x40>;
> - };
> - partition@40 {
> - label = "Filesystem";
> - reg = <0x40
> 0xc0>;
> - };
> - };
> - };
> - };
> -
> i2c@11000 {
> status = "okay";
> clock-frequency = <10>;
> @@ -173,3 +143,33 @@
> };
> };
> };
> +
> + {
> + status = "okay";
> + pinctrl-0 = <_pins>;
> + pinctrl-names = "default";
> +
> + spi-flash@1 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "n25q128a13",
> + "jedec,spi-nor";
> + reg = <0>; /* Chip select 0 */
> + spi-max-frequency = <10800>;
> +
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + partition@0 {
> + label = "U-Boot";
> + reg = <0 0x40>;
> + };
> + partition@40 {
> + label = "Filesystem";
> + reg = <0x40 0xc0>;
> + };
> + };
> + };
> +};
> --
> 2.9.0
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH] arm64: dts: marvell: add unique identifiers for Armada A8k SPI controllers
Hi Marcin,
On mar., nov. 08 2016, Thomas Petazzoni <thomas.petazz...@free-electrons.com>
wrote:
> Hello,
>
> On Tue, 8 Nov 2016 17:31:32 +0100, Marcin Wojtas wrote:
>> Enabling SPI controllers, which are attached to different busses
>> inside an SoC, may result in overlapping enumeration and cause
>> sysfs registration failure. Example log after enabling two
>> controllers on Armada 8040 SoC with same identifiers:
>>
>> [3.740415] sysfs: cannot create duplicate filename
>> '/class/spi_master/spi0'
>> [3.747510] [ cut here ]
>> [3.752145] WARNING: at fs/sysfs/dir.c:31
>> [...]
>> [4.002299] orion_spi: probe of f4700600.spi failed with error -17
>>
>> spi-orion driver offers dedicated DT property ('cell-index'), that
>> allow setting unique identifiers. Recently added support for CP110-slave
>> HW block introduced two new SPI controllers' nodes with same ID as
>> ones from CP110-master.
>>
>> This commit fixes the issue by assigning different 'cell-index' values
>> for CP110-slave SPI controllers.
>>
>> Fixes: 4eef78a0091b ("arm64: dts: marvell: add description for the slave
>> CP110 in Armada 8K")
>> Signed-off-by: Marcin Wojtas <m...@semihalf.com>
>
> It's sad that we need to hardcode those indexes in the Device Tree
> (which by no means are a description of the HW by the way), but that's
> what the SPI framework expects I believe. Therefore:
>
> Acked-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
Applied on mvebu/fixes with acked-by from Thomas.
In the same time I also applied "arm64: dts: marvell: fix clocksource
for CP110 slave SPI0" which didn't find his way to mainline yet.
Thanks,
Gregory
>
> Thomas
> --
> Thomas Petazzoni, CTO, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH 5/10] dt: bindings: Add bindings for Marvell Xenon SD Host Controller
Hi Rob,
On mar., oct. 11 2016, Ziji Hu <huz...@marvell.com> wrote:
[...]
>>> + Different Xenon SDHC release has different register set size.
>>> + The specific size should also refer to the SOC implementation.
>>> +
>>> +Optional Properties:
>>> +- Slot Index
>>> + A single Xenon IP can support multiple slots.
>>> + During initialization, each slot should set corresponding setting bit in
>>> + some Xenon-specific registers. The corresponding bit is determined by
>>> + this property.
>>> + - xenon,slotno = ;
>>
>> Slots should probably be represented as child nodes with the reg
>> property being the slot number.
>
> Since each SDHC slot is independent, I find it is more
> convenient to implement each one as independent SD host/MMC host
> instant.
> Otherwise, a main function should loop and initialize each
> slot, like sdhci-pci. I prefer to avoiding such a unnecessary main
> function.
>
> It is very hard to determine the slot number by reg property.
> Xenon slots are likely to be different types. 1st slot might
> be eMMC and 2nd one might be SD. They might have different register
> size.
> The register size might also varies in different Xenon versions.
>
Something that took me a while to figure out is that even it is the same
hardware block which handle multiple SoCs.
Each slots is managed by its own set of register. From the point of view
of the OS, it is as if we have an independent controller for each
slot.
But for an obscure reason, some command need to know which slot is
used. That's why we ended with this property.
With some example what you had in mind was something like that:
sdhci@aa {
compatible = "marvell,armada-3700-sdhci";
reg = <0xaa 0x1000>;
[...]
slot0 {
/* slot0 is an eMMC */
reg = <0>;
bus-width = <8>;
xenon,pad-type = "fixed-1-8v";
}
slot1 {
/* slot1 is an SD Card */
reg = <1>;
bus-width = <4>;
xenon,pad-type = "fixed-1-8v";
}
};
But it won't work as each slot uses its own address registers, that why we
ended with this:
sdhci@aa {
/* slot0 is an eMMC */
compatible = "marvell,armada-3700-sdhci";
reg = <0xaa 0x1000>;
[...]
xenon,slotno = <0>;
bus-width = <8>;
xenon,pad-type = "fixed-1-8v";
};
sdhci@bb {
/* slot1 is an SD Card */
compatible = "marvell,armada-3700-sdhci";
reg = <0xbb 0x1000>;
[...]
xenon,slotno = <1>;
bus-width = <4>;
xenon,pad-type = "fixed-1-8v";
};
I hope it is more clear now.
Gregory
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: Build failure with v4.9-rc1 and GCC trunk -- compiler weirdness
Hi Arnd,
On mer., oct. 19 2016, Arnd Bergmann <a...@arndb.de> wrote:
> On Wednesday, October 19, 2016 4:01:58 PM CEST Ard Biesheuvel wrote:
>> On 19 October 2016 at 15:59, Ard Biesheuvel <ard.biesheu...@linaro.org>
>> wrote:
>> > On 19 October 2016 at 14:35, Will Deacon <will.dea...@arm.com> wrote:
>> >> On Mon, Oct 17, 2016 at 08:43:19PM +0100, Ard Biesheuvel wrote:
>> >>> On 17 October 2016 at 19:38, Will Deacon <will.dea...@arm.com> wrote:
>> >
>> > Yes, and that would be perfectly legal from a correctness point of
>> > view, and would likely help performance as well. By using
>> > __builtin_constant_p(), you are choosing to perform a build time
>> > evaluation of an expression that would ordinarily be evaluated only at
>> > runtime. This implies that you have to address undefined behavior at
>> > build time rather than at runtime as well.
>> >
>> >>> If order_base_2() is not defined for input 0, it should BUG() in that
>> >>> case, and the associated __builtin_unreachable() should prevent the
>> >>> special version from being emitted. If order_base_2() is defined for
>> >>> input
>> >>> 0, it should not invoke ilog2() with that argument, and the problem
>> >>> should
>> >>> go away as well.
>> >>
>> >> I don't necessarily think it should BUG() if it's not defined for input
>> >> 0; things like __ffs don't do that and we'd be introducing conditional
>> >> checks for cases that should not happen. The comment above order_base_2
>> >> does suggest that ob2(0) should return 0, but it can actually end up
>> >> invoking ilog2(-1), which is obviously wrong.
>> >>
>> >> I could update the comment, but that doesn't fix the build issue.
>> >>
>> >
>> > Fixing roundup_pow_of_two() [which is arguably incorrect]
>>
>> I just spotted the comment that says it is undefined. But that means
>> it could legally return 1 for input 0, i suppose
>
> I think having the link error in roundup_pow_of_two() is safer than
> returning 1.
>
> Why not turn it into a runtime warning in this driver?
>
> diff --git a/drivers/clk/mvebu/armada-37xx-periph.c
> b/drivers/clk/mvebu/armada-37xx-periph.c
> index cecb0fdfaef6..711d1d9842cc 100644
> --- a/drivers/clk/mvebu/armada-37xx-periph.c
> +++ b/drivers/clk/mvebu/armada-37xx-periph.c
> @@ -349,8 +349,10 @@ static int armada_3700_add_composite_clk(const struct
> clk_periph_data *data,
> rate->reg = reg + (u64)rate->reg;
> for (clkt = rate->table; clkt->div; clkt++)
> table_size++;
> - rate->width = order_base_2(table_size);
> - rate->lock = lock;
> + if (!WARN_ON(table_size == 0)) {
> + rate->width = order_base_2(table_size);
> + rate->lock = lock;
> + }
With the way the data are constructed in the driver I don't see how the
table_size can be 0.
However I understand it is more something for the compiler.
In this case it is better to nullify the rate_hw as having width=0 will
lead to trouble in the clk_divider operations
If it is the needed solution for this build error I can submit this kind
of patch:
diff --git a/drivers/clk/mvebu/armada-37xx-periph.c
b/drivers/clk/mvebu/armada-37xx-periph.c
index 45905fc0d75b..dbc49359406d 100644
--- a/drivers/clk/mvebu/armada-37xx-periph.c
+++ b/drivers/clk/mvebu/armada-37xx-periph.c
@@ -345,11 +345,16 @@ static int armada_3700_add_composite_clk(const struct
clk_periph_data *data,
const struct clk_div_table *clkt;
int table_size = 0;
- rate->reg = reg + (u64)rate->reg;
for (clkt = rate->table; clkt->div; clkt++)
table_size++;
- rate->width = order_base_2(table_size);
- rate->lock = lock;
+ if (!WARN_ON(table_size == 0)) {
+ rate->reg = reg + (u64)rate->reg;
+ rate->width = order_base_2(table_size);
+ rate->lock = lock;
+ } else {
+ rate_hw = NULL;
+ rate_ops = NULL;
+ }
}
}
Gregory
> }
> }
>
>
>
> Arnd
>
> ___
> linux-arm-kernel mailing list
> linux-arm-ker...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
[PATCH net-next 4/5] net: mvneta: Add network support for Armada 3700 SoC
From: Marcin Wojtas <m...@semihalf.com>
Armada 3700 is a new ARMv8 SoC from Marvell using same network controller
as older Armada 370/38x/XP. There are however some differences that
needed taking into account when adding support for it:
* open default MBUS window to 4GB of DRAM - Armada 3700 SoC's Mbus
configuration for network controller has to be done on two levels:
global and per-port. The first one is inherited from the
bootloader. The latter can be opened in a default way, leaving
arbitration to the bus controller. Hence filled mbus_dram_target_info
structure is not needed
* make per-CPU operation optional - Recent patches adding RSS and XPS
support for Armada 38x/XP enabled per-CPU operation of the controller
by default. Contrary to older SoC's Armada 3700 SoC's network
controller is not capable of per-CPU processing due to interrupt lines'
connectivity. This patch restores non-per-CPU operation, which is now
optional and depends on neta_armada3700 flag value in mvneta_port
structure. In order not to complicate the code, separate interrupt
subroutine is implemented.
For now, on the Armada 3700, RSS is disabled as the current
implementation depend on the per cpu interrupts.
[gregory.clem...@free-electrons.com: extract from a larger patch, replace
some ifdef and port to net-next for v4.10]
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt | 7 +-
drivers/net/ethernet/marvell/Kconfig | 7 +-
drivers/net/ethernet/marvell/mvneta.c | 287
+++-
3 files changed, 214 insertions(+), 87 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
index 73be8970815e..7aa840c8768d 100644
--- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
+++ b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
@@ -1,7 +1,10 @@
-* Marvell Armada 370 / Armada XP Ethernet Controller (NETA)
+* Marvell Armada 370 / Armada XP / Armada 3700 Ethernet Controller (NETA)
Required properties:
-- compatible: "marvell,armada-370-neta" or "marvell,armada-xp-neta".
+- compatible: could be one of the followings
+ "marvell,armada-370-neta"
+ "marvell,armada-xp-neta"
+ "marvell,armada-3700-neta"
- reg: address and length of the register set for the device.
- interrupts: interrupt for the device
- phy: See ethernet.txt file in the same directory.
diff --git a/drivers/net/ethernet/marvell/Kconfig
b/drivers/net/ethernet/marvell/Kconfig
index 2ccea9dd9248..3b8f11fe5e13 100644
--- a/drivers/net/ethernet/marvell/Kconfig
+++ b/drivers/net/ethernet/marvell/Kconfig
@@ -56,14 +56,15 @@ config MVNETA_BM_ENABLE
buffer management.
config MVNETA
- tristate "Marvell Armada 370/38x/XP network interface support"
- depends on PLAT_ORION || COMPILE_TEST
+ tristate "Marvell Armada 370/38x/XP/37xx network interface support"
+ depends on ARCH_MVEBU || COMPILE_TEST
depends on HAS_DMA
select MVMDIO
select FIXED_PHY
---help---
This driver supports the network interface units in the
- Marvell ARMADA XP, ARMADA 370 and ARMADA 38x SoC family.
+ Marvell ARMADA XP, ARMADA 370, ARMADA 38x and
+ ARMADA 37xx SoC family.
Note that this driver is distinct from the mv643xx_eth
driver, which should be used for the older Marvell SoCs
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index ad3872e07a93..77cef5a9de7b 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -397,6 +397,9 @@ struct mvneta_port {
spinlock_t lock;
bool is_stopped;
+ u32 cause_rx_tx;
+ struct napi_struct napi;
+
/* Core clock */
struct clk *clk;
/* AXI clock */
@@ -422,6 +425,9 @@ struct mvneta_port {
u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
+
+ /* Flags for special SoC configurations */
+ bool neta_armada3700;
u16 rx_offset_correction;
};
@@ -965,14 +971,9 @@ static int mvneta_mbus_io_win_set(struct mvneta_port *pp,
u32 base, u32 wsize,
return 0;
}
-/* Assign and initialize pools for port. In case of fail
- * buffer manager will remain disabled for current port.
- */
-static int mvneta_bm_port_init(struct platform_device *pdev,
- struct mvneta_port *pp)
+static int mvneta_bm_port_mbus_init(struct mvneta_port *pp)
{
- struct device_node *dn = pdev->dev.of_node;
- u32
[PATCH net-next 2/5] net: mvneta: Convert to be 64 bits compatible
From: Marcin Wojtas <m...@semihalf.com>
Prepare the mvneta driver in order to be usable on the 64 bits platform
such as the Armada 3700.
[gregory.clem...@free-electrons.com]: this patch was extract from a larger
one to ease review and maintenance.
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index b6849f88cab7..ad3872e07a93 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -296,6 +296,12 @@
/* descriptor aligned size */
#define MVNETA_DESC_ALIGNED_SIZE 32
+/* Number of bytes to be taken into account by HW when putting incoming data
+ * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet
+ * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers.
+ */
+#define MVNETA_RX_PKT_OFFSET_CORRECTION64
+
#define MVNETA_RX_PKT_SIZE(mtu) \
ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
ETH_HLEN + ETH_FCS_LEN,\
@@ -416,6 +422,7 @@ struct mvneta_port {
u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
+ u16 rx_offset_correction;
};
/* The mvneta_tx_desc and mvneta_rx_desc structures describe the
@@ -1807,6 +1814,7 @@ static int mvneta_rx_refill(struct mvneta_port *pp,
return -ENOMEM;
}
+ phys_addr += pp->rx_offset_correction;
mvneta_rx_desc_fill(rx_desc, phys_addr, data, rxq);
return 0;
}
@@ -2838,7 +2846,7 @@ static int mvneta_rxq_init(struct mvneta_port *pp,
mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
/* Set Offset */
- mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD);
+ mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD - pp->rx_offset_correction);
/* Set coalescing pkts and time */
mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
@@ -4091,6 +4099,13 @@ static int mvneta_probe(struct platform_device *pdev)
pp->rxq_def = rxq_def;
+ /* Set RX packet offset correction for platforms, whose
+* NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit
+* platforms and 0B for 32-bit ones.
+*/
+ pp->rx_offset_correction =
+ max(0, NET_SKB_PAD - MVNETA_RX_PKT_OFFSET_CORRECTION);
+
pp->indir[0] = rxq_def;
pp->clk = devm_clk_get(>dev, "core");
--
git-series 0.8.10
[PATCH net-next 3/5] net: mvneta: Only disable mvneta_bm for 64-bits
Actually only the mvneta_bm support is not 64-bits compatible. The mvneta code itself can run on 64-bits architecture. Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> --- drivers/net/ethernet/marvell/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/Kconfig b/drivers/net/ethernet/marvell/Kconfig index 66fd9dbb2ca7..2ccea9dd9248 100644 --- a/drivers/net/ethernet/marvell/Kconfig +++ b/drivers/net/ethernet/marvell/Kconfig @@ -44,6 +44,7 @@ config MVMDIO config MVNETA_BM_ENABLE tristate "Marvell Armada 38x/XP network interface BM support" depends on MVNETA + depends on !64BIT ---help--- This driver supports auxiliary block of the network interface units in the Marvell ARMADA XP and ARMADA 38x SoC @@ -58,7 +59,6 @@ config MVNETA tristate "Marvell Armada 370/38x/XP network interface support" depends on PLAT_ORION || COMPILE_TEST depends on HAS_DMA - depends on !64BIT select MVMDIO select FIXED_PHY ---help--- @@ -71,6 +71,7 @@ config MVNETA config MVNETA_BM tristate + depends on !64BIT default y if MVNETA=y && MVNETA_BM_ENABLE!=n default MVNETA_BM_ENABLE select HWBM -- git-series 0.8.10
[PATCH net-next 1/5] net: mvneta: Use cacheable memory to store the rx buffer virtual address
Until now the virtual address of the received buffer were stored in the
cookie field of the rx descriptor. However, this field is 32-bits only
which prevents to use the driver on a 64-bits architecture.
With this patch the virtual address is stored in an array not shared with
the hardware (no more need to use the DMA API). Thanks to this, it is
possible to use cache contrary to the access of the rx descriptor member.
The change is done in the swbm path only because the hwbm uses the cookie
field, this also means that currently the hwbm is not usable in 64-bits.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 96
1 file changed, 84 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 87274d4ab102..b6849f88cab7 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -561,6 +561,9 @@ struct mvneta_rx_queue {
u32 pkts_coal;
u32 time_coal;
+ /* Virtual address of the RX buffer */
+ void **buf_virt_addr;
+
/* Virtual address of the RX DMA descriptors array */
struct mvneta_rx_desc *descs;
@@ -1573,10 +1576,14 @@ static void mvneta_tx_done_pkts_coal_set(struct
mvneta_port *pp,
/* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
- u32 phys_addr, u32 cookie)
+ u32 phys_addr, void *virt_addr,
+ struct mvneta_rx_queue *rxq)
{
- rx_desc->buf_cookie = cookie;
+ int i;
+
rx_desc->buf_phys_addr = phys_addr;
+ i = rx_desc - rxq->descs;
+ rxq->buf_virt_addr[i] = virt_addr;
}
/* Decrement sent descriptors counter */
@@ -1781,7 +1788,8 @@ EXPORT_SYMBOL_GPL(mvneta_frag_free);
/* Refill processing for SW buffer management */
static int mvneta_rx_refill(struct mvneta_port *pp,
- struct mvneta_rx_desc *rx_desc)
+ struct mvneta_rx_desc *rx_desc,
+ struct mvneta_rx_queue *rxq)
{
dma_addr_t phys_addr;
@@ -1799,7 +1807,7 @@ static int mvneta_rx_refill(struct mvneta_port *pp,
return -ENOMEM;
}
- mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data);
+ mvneta_rx_desc_fill(rx_desc, phys_addr, data, rxq);
return 0;
}
@@ -1861,7 +1869,12 @@ static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
for (i = 0; i < rxq->size; i++) {
struct mvneta_rx_desc *rx_desc = rxq->descs + i;
- void *data = (void *)rx_desc->buf_cookie;
+ void *data;
+
+ if (!pp->bm_priv)
+ data = rxq->buf_virt_addr[i];
+ else
+ data = (void *)(uintptr_t)rx_desc->buf_cookie;
dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
MVNETA_RX_BUF_SIZE(pp->pkt_size),
DMA_FROM_DEVICE);
@@ -1894,12 +1907,13 @@ static int mvneta_rx_swbm(struct mvneta_port *pp, int
rx_todo,
unsigned char *data;
dma_addr_t phys_addr;
u32 rx_status, frag_size;
- int rx_bytes, err;
+ int rx_bytes, err, index;
rx_done++;
rx_status = rx_desc->status;
rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
- data = (unsigned char *)rx_desc->buf_cookie;
+ index = rx_desc - rxq->descs;
+ data = (unsigned char *)rxq->buf_virt_addr[index];
phys_addr = rx_desc->buf_phys_addr;
if (!mvneta_rxq_desc_is_first_last(rx_status) ||
@@ -1938,7 +1952,7 @@ static int mvneta_rx_swbm(struct mvneta_port *pp, int
rx_todo,
}
/* Refill processing */
- err = mvneta_rx_refill(pp, rx_desc);
+ err = mvneta_rx_refill(pp, rx_desc, rxq);
if (err) {
netdev_err(dev, "Linux processing - Can't refill\n");
rxq->missed++;
@@ -2020,7 +2034,7 @@ static int mvneta_rx_hwbm(struct mvneta_port *pp, int
rx_todo,
rx_done++;
rx_status = rx_desc->status;
rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
- data = (unsigned char *)rx_desc->buf_cookie;
+ data = (u8 *)(uintptr_t)rx_desc->buf_cookie;
phys_addr = rx_desc->buf_phys_addr;
pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
bm_pool = >bm_priv->bm_pools[pool_id];
@@ -2708,6 +2722,57 @@ static int mvneta_poll(struct napi_struct *napi,
[PATCH net-next 0/5] Support Armada 37xx SoC (ARMv8 64-bits) in mvneta driver
Hi, The Armada 37xx is a new ARMv8 SoC from Marvell using same network controller as the older Armada 370/38x/XP SoCs. This series adapts the driver in order to be able to use it on this new SoC. The main changes are: - 64-bits support: the first patches allow using the driver on a 64-bit architecture. - MBUS support: the mbus configuration is different on Armada 37xx from the older SoCs. - per cpu interrupt: Armada 37xx do not support per cpu interrupt for the NETA IP, the non-per-CPU behavior was added back. The first item is solved by patches 1 to 3. The 2 last items are solved by patch 4. In patch 5 the dt support is added. Beside Armada 37xx, the series have been tested on Armada XP and Armada 38x (with Hardware Buffer Management and with Software Buffer Managment). Thanks, Gregory Gregory CLEMENT (3): net: mvneta: Use cacheable memory to store the rx buffer virtual address net: mvneta: Only disable mvneta_bm for 64-bits ARM64: dts: marvell: Add network support for Armada 3700 Marcin Wojtas (2): net: mvneta: Convert to be 64 bits compatible net: mvneta: Add network support for Armada 3700 SoC Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt | 7 +- arch/arm64/boot/dts/marvell/armada-3720-db.dts| 23 - arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 23 - drivers/net/ethernet/marvell/Kconfig | 10 +- drivers/net/ethernet/marvell/mvneta.c | 400 ++-- 5 files changed, 362 insertions(+), 101 deletions(-) base-commit: 436accebb53021ef7c63535f60bda410aa87c136 -- git-series 0.8.10
[PATCH net-next 5/5] ARM64: dts: marvell: Add network support for Armada 3700
Add neta nodes for network support both in device tree for the SoC and
the board.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 23 +++-
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 23 +++-
2 files changed, 46 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index 1372e9a6aaa4..c8b82e4145de 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -81,3 +81,26 @@
{
status = "okay";
};
+
+ {
+ status = "okay";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+ {
+ phy-mode = "rgmii-id";
+ phy = <>;
+ status = "okay";
+};
+
+ {
+ phy-mode = "rgmii-id";
+ phy = <>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index e9bd58793464..3b8eb45bdc76 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -140,6 +140,29 @@
};
};
+ eth0: ethernet@3 {
+ compatible = "marvell,armada-3700-neta";
+ reg = <0x3 0x4000>;
+ interrupts = ;
+ clocks = <_periph_clk 8>;
+ status = "disabled";
+ };
+
+ mdio: mdio@32004 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,orion-mdio";
+ reg = <0x32004 0x4>;
+ };
+
+ eth1: ethernet@4 {
+ compatible = "marvell,armada-3700-neta";
+ reg = <0x4 0x4000>;
+ interrupts = ;
+ clocks = <_periph_clk 7>;
+ status = "disabled";
+ };
+
usb3: usb@58000 {
compatible = "marvell,armada3700-xhci",
"generic-xhci";
--
git-series 0.8.10
Re: [PATCH 0/10] mmc: Add support to Marvell Xenon SD Host Controller
Hi Ulf, On lun., oct. 31 2016, Gregory CLEMENT <gregory.clem...@free-electrons.com> wrote: > Hello, > > This the second version of the series adding support for the SDHCI > Xenon controller. It can be currently found on the Armada 37xx and the > Armada 7K/8K but will be also used in more Marvell SoC (and not only > the mvebu ones actually). > > Some of the remarks had been taking into account since the first > version, according to Ziji Hu, here are the following chcanges: > "Changes in V2: > rebase on v4.9-rc2. > Re-write Xenon bindings. Ajust Xenon DT property naming. > Add a new DT property to indicate eMMC card type, instead of using > variable card_candidate. > Clear quirks SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 in Xenon platform data > Add support to HS400 retuning." > > I think the main open point which remains is about issuing commands > from the ->set_ios() callback (in patch 7). > Ulf, could you comment about it? This part is the last thing missing, we are about to solve the last issues about the binding, but we still didn't have your opinion about issuing commands from the ->set_ios() callback and Adrian required it to take this series. To have more context you can have a look on: http://marc.info/?l=linux-mmc=147618996414673=2 it is the original email where Adrian wanted your agreement. Thanks, Gregory -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Re: [PATCH net-next 1/4] net: mvneta: Convert to be 64 bits compatible
Hi Jisheng, Arnd,
Thanks for your feedback.
On mer., nov. 23 2016, Arnd Bergmann <a...@arndb.de> wrote:
> On Wednesday, November 23, 2016 5:53:41 PM CET Jisheng Zhang wrote:
>> On Tue, 22 Nov 2016 22:04:12 +0100 Arnd Bergmann wrote:
>>
>> > On Tuesday, November 22, 2016 5:48:41 PM CET Gregory CLEMENT wrote:
>> > > +#ifdef CONFIG_64BIT
>> > > + void *data_tmp;
>> > > +
>> > > + /* In Neta HW only 32 bits data is supported, so in order to
>> > > +* obtain whole 64 bits address from RX descriptor, we store
>> > > +* the upper 32 bits when allocating buffer, and put it back
>> > > +* when using buffer cookie for accessing packet in memory.
>> > > +* Frags should be allocated from single 'memory' region,
>> > > +* hence common upper address half should be sufficient.
>> > > +*/
>> > > + data_tmp = mvneta_frag_alloc(pp->frag_size);
>> > > + if (data_tmp) {
>> > > + pp->data_high = (u64)upper_32_bits((u64)data_tmp) << 32;
>> > > + mvneta_frag_free(pp->frag_size, data_tmp);
>> > > + }
>> > >
>> >
>> > How does this work when the region spans a n*4GB address boundary?
>>
>> indeed. We also make use of this driver on 64bit platforms. We use
>> different solution to make the driver 64bit safe.
>>
>> solA: make use of the reserved field in the mvneta_rx_desc, such
>> as reserved2 etc. Yes, the field is marked as "for future use, PnC", but
>> now it's not used at all. This is one possible solution however.
>
> Right, this sounds like the most straightforward choice.
The PnC (which stands for Parsing and Classification) is not used yet
indeed but this field will be needed when we will enable it. It is
something we want to do but it is not planned in a near future. However
from the datasheets I have it seems only present on the Armada XP. It is
not mentioned on datasheets for the Armada 38x or the Armada 3700.
That would mean it was safe to use on of this field in 64-bits mode on
the Armada 3700.
So I am going to take this approach.
Thanks,
Gregory
>
>> solB: allocate a shadow buf cookie during init, e.g
>>
>> rxq->descs_bufcookie = kmalloc(rxq->size * sizeof(void*), GFP_KERNEL);
>>
>> then modify mvneta_rx_desc_fill a bit to save the 64bit pointer in
>> the shadow buf cookie, e.g
>> static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
>> u32 phys_addr, u32 cookie,
>> struct mvneta_rx_queue *rxq)
>>
>> {
>> int i;
>>
>> rx_desc->buf_cookie = cookie;
>> rx_desc->buf_phys_addr = phys_addr;
>> i = rx_desc - rxq->descs;
>> rxq->descs_bufcookie[i] = cookie;
>> }
>>
>> then fetch the desc from the shadow buf cookie in all code path, such
>> as mvneta_rx() etc.
>>
>> Both solutions should not have the problems pointed out by Arnd.
>
> Wait, since you compute an index 'i' here, can't you just store 'i'
> directly in the descriptor instead of the pointer?
>
> Arnd
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH net-next] marvell: mark mvneta and mvpp2 32-bit only
Hi Arnd,
On mar., nov. 22 2016, Arnd Bergmann <a...@arndb.de> wrote:
> Both of these drivers won't work on 64-bit architectures unless they
> are redesigned, since they store a virtual address pointer in a 32-bit
> field of the descriptors:
>
> drivers/net/ethernet/marvell/mvneta_bm.c: In function 'mvneta_bm_construct':
> drivers/net/ethernet/marvell/mvneta_bm.c:103:16: error: cast from pointer to
> integer of different size [-Werror=pointer-to-int-cast]
> drivers/net/ethernet/marvell/mvpp2.c: In function 'mvpp2_prs_vlan_init':
> drivers/net/ethernet/marvell/mvpp2.c:2563:32: error: large integer implicitly
> truncated to unsigned type [-Werror=overflow]
>
> This limits the COMPILE_TEST option for the two drivers again to
> only build them on 32-bit. This seems nicer than shutting up the
> warnings, in case we ever actually want to use them on 64-bit,
> as the warnings indicate which parts of the driver are currently
Actually we are using these drivers on 64-bits so obviously there are
not 32 bits only!
For mvneta currently we do not use BM on the 64-bits version. I agree
that there is a problem with mvneta_bm.c when building in 64-bits but it
should not prevent us to use the mvneta driver.
Gregory
> broken there.
>
> Fixes: a0627f776a45 ("net: marvell: Allow drivers to be built with
> COMPILE_TEST")
> Signed-off-by: Arnd Bergmann <a...@arndb.de>
> ---
> drivers/net/ethernet/marvell/Kconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/net/ethernet/marvell/Kconfig
> b/drivers/net/ethernet/marvell/Kconfig
> index d74d4e6f0b34..66fd9dbb2ca7 100644
> --- a/drivers/net/ethernet/marvell/Kconfig
> +++ b/drivers/net/ethernet/marvell/Kconfig
> @@ -58,6 +58,7 @@ config MVNETA
> tristate "Marvell Armada 370/38x/XP network interface support"
> depends on PLAT_ORION || COMPILE_TEST
> depends on HAS_DMA
> + depends on !64BIT
> select MVMDIO
> select FIXED_PHY
> ---help---
> @@ -81,6 +82,7 @@ config MVPP2
> tristate "Marvell Armada 375 network interface support"
> depends on MACH_ARMADA_375 || COMPILE_TEST
> depends on HAS_DMA
> + depends on !64BIT
> select MVMDIO
> ---help---
> This driver supports the network interface units in the
> --
> 2.9.0
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
[PATCH] net: mvneta: Only disable mvneta_bm for 64-bits
Actually only the mvneta_bm support is not 64-bits compatible. The mvneta code itself can run on 64-bits architecture. Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> --- drivers/net/ethernet/marvell/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/Kconfig b/drivers/net/ethernet/marvell/Kconfig index 66fd9dbb2ca7..2ccea9dd9248 100644 --- a/drivers/net/ethernet/marvell/Kconfig +++ b/drivers/net/ethernet/marvell/Kconfig @@ -44,6 +44,7 @@ config MVMDIO config MVNETA_BM_ENABLE tristate "Marvell Armada 38x/XP network interface BM support" depends on MVNETA + depends on !64BIT ---help--- This driver supports auxiliary block of the network interface units in the Marvell ARMADA XP and ARMADA 38x SoC @@ -58,7 +59,6 @@ config MVNETA tristate "Marvell Armada 370/38x/XP network interface support" depends on PLAT_ORION || COMPILE_TEST depends on HAS_DMA - depends on !64BIT select MVMDIO select FIXED_PHY ---help--- @@ -71,6 +71,7 @@ config MVNETA config MVNETA_BM tristate + depends on !64BIT default y if MVNETA=y && MVNETA_BM_ENABLE!=n default MVNETA_BM_ENABLE select HWBM -- 2.10.2
Re: [PATCH] net: mvneta: Only disable mvneta_bm for 64-bits
Hi, On mar., nov. 22 2016, Gregory CLEMENT <gregory.clem...@free-electrons.com> wrote: > Actually only the mvneta_bm support is not 64-bits compatible. > The mvneta code itself can run on 64-bits architecture. I have just realized that my topic prefix was wrong (net-next was missing), I am send a new email with the correct prefix. Sorry for the noise. Gregory > > Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> > --- > drivers/net/ethernet/marvell/Kconfig | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/net/ethernet/marvell/Kconfig > b/drivers/net/ethernet/marvell/Kconfig > index 66fd9dbb2ca7..2ccea9dd9248 100644 > --- a/drivers/net/ethernet/marvell/Kconfig > +++ b/drivers/net/ethernet/marvell/Kconfig > @@ -44,6 +44,7 @@ config MVMDIO > config MVNETA_BM_ENABLE > tristate "Marvell Armada 38x/XP network interface BM support" > depends on MVNETA > + depends on !64BIT > ---help--- > This driver supports auxiliary block of the network > interface units in the Marvell ARMADA XP and ARMADA 38x SoC > @@ -58,7 +59,6 @@ config MVNETA > tristate "Marvell Armada 370/38x/XP network interface support" > depends on PLAT_ORION || COMPILE_TEST > depends on HAS_DMA > - depends on !64BIT > select MVMDIO > select FIXED_PHY > ---help--- > @@ -71,6 +71,7 @@ config MVNETA > > config MVNETA_BM > tristate > + depends on !64BIT > default y if MVNETA=y && MVNETA_BM_ENABLE!=n > default MVNETA_BM_ENABLE > select HWBM > -- > 2.10.2 > -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
[PATCH net-next] net: mvneta: Only disable mvneta_bm for 64-bits
Actually only the mvneta_bm support is not 64-bits compatible. The mvneta code itself can run on 64-bits architecture. Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> --- drivers/net/ethernet/marvell/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/Kconfig b/drivers/net/ethernet/marvell/Kconfig index 66fd9dbb2ca7..2ccea9dd9248 100644 --- a/drivers/net/ethernet/marvell/Kconfig +++ b/drivers/net/ethernet/marvell/Kconfig @@ -44,6 +44,7 @@ config MVMDIO config MVNETA_BM_ENABLE tristate "Marvell Armada 38x/XP network interface BM support" depends on MVNETA + depends on !64BIT ---help--- This driver supports auxiliary block of the network interface units in the Marvell ARMADA XP and ARMADA 38x SoC @@ -58,7 +59,6 @@ config MVNETA tristate "Marvell Armada 370/38x/XP network interface support" depends on PLAT_ORION || COMPILE_TEST depends on HAS_DMA - depends on !64BIT select MVMDIO select FIXED_PHY ---help--- @@ -71,6 +71,7 @@ config MVNETA config MVNETA_BM tristate + depends on !64BIT default y if MVNETA=y && MVNETA_BM_ENABLE!=n default MVNETA_BM_ENABLE select HWBM -- 2.10.2
Re: [PATCH net-next] net: mvneta: Only disable mvneta_bm for 64-bits
Hi David, On mar., nov. 22 2016, David Miller <da...@davemloft.net> wrote: > From: Gregory CLEMENT <gregory.clem...@free-electrons.com> > Date: Tue, 22 Nov 2016 17:00:37 +0100 > >> Actually only the mvneta_bm support is not 64-bits compatible. >> The mvneta code itself can run on 64-bits architecture. >> >> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> > > No it cannot, it emits warnings because it casts pointers to and > from 32-bit integers. > > I'm not applying this. > > drivers/net/ethernet/marvell/mvneta.c: In function ‘mvneta_rx_refill’: > drivers/net/ethernet/marvell/mvneta.c:1802:42: warning: cast from pointer to > integer of different size [-Wpointer-to-int-cast] > mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data); > ^ > drivers/net/ethernet/marvell/mvneta.c: In function ‘mvneta_rxq_drop_pkts’: > drivers/net/ethernet/marvell/mvneta.c:1864:16: warning: cast to pointer from > integer of different size [-Wint-to-pointer-cast] >void *data = (void *)rx_desc->buf_cookie; > ^ > drivers/net/ethernet/marvell/mvneta.c: In function ‘mvneta_rx_swbm’: > drivers/net/ethernet/marvell/mvneta.c:1902:10: warning: cast to pointer from > integer of different size [-Wint-to-pointer-cast] >data = (unsigned char *)rx_desc->buf_cookie; > ^ > drivers/net/ethernet/marvell/mvneta.c: In function ‘mvneta_rx_hwbm’: > drivers/net/ethernet/marvell/mvneta.c:2023:10: warning: cast to pointer from > integer of different size [-Wint-to-pointer-cast] >data = (unsigned char *)rx_desc->buf_cookie; > ^ Indeed! There was a missing patch for it that I had in my tree and I didn't submit yet. I am bout to doing it now. Thanks, Gregory -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Re: [PATCH 5/10] dt: bindings: Add bindings for Marvell Xenon SD Host Controller
Hi Rob, On jeu., nov. 10 2016, Ziji Hu <huz...@marvell.com> wrote: [...] >>> + >>> +- reg: >>> + * For "marvell,xenon-sdhci", one register area for Xenon IP. >>> + >>> + * For "marvell,armada-3700-sdhci", two register areas. >>> +The first one for Xenon IP register. The second one for the Armada >>> 3700 SOC >>> +PHY PAD Voltage Control register. >>> +Please follow the examples with compatible "marvell,armada-3700-sdhci" >>> +in below. >>> +Please also check property marvell,pad-type in below. >>> + >>> +Optional Properties: >>> +- marvell,xenon-slotno: >> >> Multiple slots should be represented as child nodes IMO. I think some >> other bindings already do this. >> > > All the slots are entirely independent. > I prefer to consider it as multiple independent SDHCs placed in > a single IP, instead of that a IP contains multiple child slots. It was indeed what I tried to show in my answer for the 1st version: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-October/461860.html Maybe you missed it. You also mentioned other bindings using child nodes, but for this one we have one controller with only one set of register with multiple slots (Atmel is an example). Here each slot have it own set of register. Actually giving the fact that each slot is controlled by a different set of register I wonder why the hardware can't also deduce the slot number from the address register. For me it looks like an hardware bug but we have to deal with it. Do you still think we needchild node here? > > It is unlike the implementation which put multiple slots behind PCIe EP > interface. sdhci-pci.c will handle each slot init one by one. > If Xenon SDHC slots are represented as child nodes, there should also > be a main entry in Xenon driver to init each child node one by one. > In my very own opinion, it is inconvenient and unnecessary. Gregory -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
[PATCH net-next 0/4] Extend mvneta to support Armada 3700 (ARM 64)
Hi, This series enable the use of mvneta driver on the Armada 3700 SoCs. Armada 3700 is a new ARMv8 SoC from Marvell using same network controller as older Armada 370/38x/XP. Besides the changes needed to be used on 64-bits architecture done in the 1st patch, there are also few difference related to the Armada 3700 SoC. The main one being the used of shared interrupt instead of the private ones. It has been addressed in the 3rd patch. Not all the feature supported on the older Soc have been ported yet for this new SoC. Gregory CLEMENT (2): net: mvneta: Only disable mvneta_bm for 64-bits ARM64: dts: marvell: Add network support for Armada 3700 Marcin Wojtas (2): net: mvneta: Convert to be 64 bits compatible net: mvneta: Add network support for Armada 3700 SoC .../bindings/net/marvell-armada-370-neta.txt | 7 +- arch/arm64/boot/dts/marvell/armada-3720-db.dts | 23 ++ arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 23 ++ drivers/net/ethernet/marvell/Kconfig | 10 +- drivers/net/ethernet/marvell/mvneta.c | 364 - 5 files changed, 333 insertions(+), 94 deletions(-) -- 2.10.2
[PATCH net-next 3/4] net: mvneta: Add network support for Armada 3700 SoC
From: Marcin Wojtas <m...@semihalf.com>
Armada 3700 is a new ARMv8 SoC from Marvell using same network controller
as older Armada 370/38x/XP. There are however some differences that
needed taking into account when adding support for it:
* open default MBUS window to 4GB of DRAM - Armada 3700 SoC's Mbus
configuration for network controller has to be done on two levels:
global and per-port. The first one is inherited from the
bootloader. The latter can be opened in a default way, leaving
arbitration to the bus controller. Hence filled mbus_dram_target_info
structure is not needed
* make per-CPU operation optional - Recent patches adding RSS and XPS
support for Armada 38x/XP enabled per-CPU operation of the controller
by default. Contrary to older SoC's Armada 3700 SoC's network
controller is not capable of per-CPU processing due to interrupt lines'
connectivity. This patch restores non-per-CPU operation, which is now
optional and depends on neta_armada3700 flag value in mvneta_port
structure. In order not to complicate the code, separate interrupt
subroutine is implemented.
For now, on the Armada 3700, RSS is disabled as the current
implementation depend on precpu interrupt.
[gregory.clem...@free-electrons.com: extract from a larger patch, replace
some ifdef and port to net-next for v4.10]
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
.../bindings/net/marvell-armada-370-neta.txt | 7 +-
drivers/net/ethernet/marvell/Kconfig | 7 +-
drivers/net/ethernet/marvell/mvneta.c | 287 +++--
3 files changed, 214 insertions(+), 87 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
index 73be8970815e..7aa840c8768d 100644
--- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
+++ b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
@@ -1,7 +1,10 @@
-* Marvell Armada 370 / Armada XP Ethernet Controller (NETA)
+* Marvell Armada 370 / Armada XP / Armada 3700 Ethernet Controller (NETA)
Required properties:
-- compatible: "marvell,armada-370-neta" or "marvell,armada-xp-neta".
+- compatible: could be one of the followings
+ "marvell,armada-370-neta"
+ "marvell,armada-xp-neta"
+ "marvell,armada-3700-neta"
- reg: address and length of the register set for the device.
- interrupts: interrupt for the device
- phy: See ethernet.txt file in the same directory.
diff --git a/drivers/net/ethernet/marvell/Kconfig
b/drivers/net/ethernet/marvell/Kconfig
index 2ccea9dd9248..3b8f11fe5e13 100644
--- a/drivers/net/ethernet/marvell/Kconfig
+++ b/drivers/net/ethernet/marvell/Kconfig
@@ -56,14 +56,15 @@ config MVNETA_BM_ENABLE
buffer management.
config MVNETA
- tristate "Marvell Armada 370/38x/XP network interface support"
- depends on PLAT_ORION || COMPILE_TEST
+ tristate "Marvell Armada 370/38x/XP/37xx network interface support"
+ depends on ARCH_MVEBU || COMPILE_TEST
depends on HAS_DMA
select MVMDIO
select FIXED_PHY
---help---
This driver supports the network interface units in the
- Marvell ARMADA XP, ARMADA 370 and ARMADA 38x SoC family.
+ Marvell ARMADA XP, ARMADA 370, ARMADA 38x and
+ ARMADA 37xx SoC family.
Note that this driver is distinct from the mv643xx_eth
driver, which should be used for the older Marvell SoCs
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 67f6465d96ba..7438ffd5639a 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -397,6 +397,9 @@ struct mvneta_port {
spinlock_t lock;
bool is_stopped;
+ u32 cause_rx_tx;
+ struct napi_struct napi;
+
/* Core clock */
struct clk *clk;
/* AXI clock */
@@ -422,6 +425,9 @@ struct mvneta_port {
u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
+
+ /* Flags for special SoC configurations */
+ bool neta_armada3700;
#ifdef CONFIG_64BIT
u64 data_high;
#endif
@@ -964,14 +970,9 @@ static int mvneta_mbus_io_win_set(struct mvneta_port *pp,
u32 base, u32 wsize,
return 0;
}
-/* Assign and initialize pools for port. In case of fail
- * buffer manager will remain disabled for current port.
- */
-static int mvneta_bm_port_init(struct platform_device *pdev,
- struct mvneta_port *pp)
+static int mvneta_bm_port_mbus_init(struct mvneta_port *pp)
{
- struct device_node *dn = pdev->dev.of_node;
- u32 long_pool_id, short_pool_id, wsize;
+ u32 wsize;
u8 target, attr;
i
[PATCH net-next 2/4] net: mvneta: Only disable mvneta_bm for 64-bits
Actually only the mvneta_bm support is not 64-bits compatible. The mvneta code itself can run on 64-bits architecture. Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> --- drivers/net/ethernet/marvell/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/Kconfig b/drivers/net/ethernet/marvell/Kconfig index 66fd9dbb2ca7..2ccea9dd9248 100644 --- a/drivers/net/ethernet/marvell/Kconfig +++ b/drivers/net/ethernet/marvell/Kconfig @@ -44,6 +44,7 @@ config MVMDIO config MVNETA_BM_ENABLE tristate "Marvell Armada 38x/XP network interface BM support" depends on MVNETA + depends on !64BIT ---help--- This driver supports auxiliary block of the network interface units in the Marvell ARMADA XP and ARMADA 38x SoC @@ -58,7 +59,6 @@ config MVNETA tristate "Marvell Armada 370/38x/XP network interface support" depends on PLAT_ORION || COMPILE_TEST depends on HAS_DMA - depends on !64BIT select MVMDIO select FIXED_PHY ---help--- @@ -71,6 +71,7 @@ config MVNETA config MVNETA_BM tristate + depends on !64BIT default y if MVNETA=y && MVNETA_BM_ENABLE!=n default MVNETA_BM_ENABLE select HWBM -- 2.10.2
[PATCH net-next 4/4] ARM64: dts: marvell: Add network support for Armada 3700
Add neta nodes for network support both in device tree for the SoC and
the board.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 23 +++
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 23 +++
2 files changed, 46 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index 1372e9a6aaa4..c8b82e4145de 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -81,3 +81,26 @@
{
status = "okay";
};
+
+ {
+ status = "okay";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+ {
+ phy-mode = "rgmii-id";
+ phy = <>;
+ status = "okay";
+};
+
+ {
+ phy-mode = "rgmii-id";
+ phy = <>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index c4762538ec01..a7278ce9e523 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -140,6 +140,29 @@
};
};
+ eth0: ethernet@3 {
+ compatible = "marvell,armada-3700-neta";
+ reg = <0x3 0x4000>;
+ interrupts = ;
+ clocks = <_periph_clk 8>;
+ status = "disabled";
+ };
+
+ mdio: mdio@32004 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,orion-mdio";
+ reg = <0x32004 0x4>;
+ };
+
+ eth1: ethernet@4 {
+ compatible = "marvell,armada-3700-neta";
+ reg = <0x4 0x4000>;
+ interrupts = ;
+ clocks = <_periph_clk 7>;
+ status = "disabled";
+ };
+
usb3: usb@58000 {
compatible = "marvell,armada3700-xhci",
"generic-xhci";
--
2.10.2
[PATCH net-next 1/4] net: mvneta: Convert to be 64 bits compatible
From: Marcin Wojtas <m...@semihalf.com>
Prepare the mvneta driver in order to be usable on the 64 bits platform
such as the Armada 3700.
[gregory.clem...@free-electrons.com]: this patch was extract from a larger
one to ease review and maintenance.
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 77 ---
1 file changed, 71 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 87274d4ab102..67f6465d96ba 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -296,6 +296,12 @@
/* descriptor aligned size */
#define MVNETA_DESC_ALIGNED_SIZE 32
+/* Number of bytes to be taken into account by HW when putting incoming data
+ * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet
+ * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers.
+ */
+#define MVNETA_RX_PKT_OFFSET_CORRECTION64
+
#define MVNETA_RX_PKT_SIZE(mtu) \
ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
ETH_HLEN + ETH_FCS_LEN,\
@@ -416,8 +422,11 @@ struct mvneta_port {
u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
+#ifdef CONFIG_64BIT
+ u64 data_high;
+#endif
+ u16 rx_offset_correction;
};
-
/* The mvneta_tx_desc and mvneta_rx_desc structures describe the
* layout of the transmit and reception DMA descriptors, and their
* layout is therefore defined by the hardware design
@@ -1791,6 +1800,10 @@ static int mvneta_rx_refill(struct mvneta_port *pp,
if (!data)
return -ENOMEM;
+#ifdef CONFIG_64BIT
+ if (unlikely(pp->data_high != (u64)upper_32_bits((u64)data) << 32))
+ return -ENOMEM;
+#endif
phys_addr = dma_map_single(pp->dev->dev.parent, data,
MVNETA_RX_BUF_SIZE(pp->pkt_size),
DMA_FROM_DEVICE);
@@ -1799,7 +1812,8 @@ static int mvneta_rx_refill(struct mvneta_port *pp,
return -ENOMEM;
}
- mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data);
+ phys_addr += pp->rx_offset_correction;
+ mvneta_rx_desc_fill(rx_desc, phys_addr, (uintptr_t)data);
return 0;
}
@@ -1861,8 +1875,16 @@ static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
for (i = 0; i < rxq->size; i++) {
struct mvneta_rx_desc *rx_desc = rxq->descs + i;
- void *data = (void *)rx_desc->buf_cookie;
-
+ void *data = (u8 *)(uintptr_t)rx_desc->buf_cookie;
+#ifdef CONFIG_64BIT
+ /* In Neta HW only 32 bits data is supported, so in
+* order to obtain whole 64 bits address from RX
+* descriptor, we store the upper 32 bits when
+* allocating buffer, and put it back when using
+* buffer cookie for accessing packet in memory.
+*/
+ data = (u8 *)(pp->data_high | (u64)data);
+#endif
dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
MVNETA_RX_BUF_SIZE(pp->pkt_size),
DMA_FROM_DEVICE);
mvneta_frag_free(pp->frag_size, data);
@@ -1899,7 +1921,17 @@ static int mvneta_rx_swbm(struct mvneta_port *pp, int
rx_todo,
rx_done++;
rx_status = rx_desc->status;
rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
+#ifdef CONFIG_64BIT
+ /* In Neta HW only 32 bits data is supported, so in
+* order to obtain whole 64 bits address from RX
+* descriptor, we store the upper 32 bits when
+* allocating buffer, and put it back when using
+* buffer cookie for accessing packet in memory.
+*/
+ data = (u8 *)(pp->data_high | (u64)rx_desc->buf_cookie);
+#else
data = (unsigned char *)rx_desc->buf_cookie;
+#endif
phys_addr = rx_desc->buf_phys_addr;
if (!mvneta_rxq_desc_is_first_last(rx_status) ||
@@ -2020,7 +2052,17 @@ static int mvneta_rx_hwbm(struct mvneta_port *pp, int
rx_todo,
rx_done++;
rx_status = rx_desc->status;
rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
- data = (unsigned char *)rx_desc->buf_cookie;
+#ifdef CONFIG_64BIT
+ /* In Neta HW only 32 bits data is supported, so in
+* order to obtain whole 64 bits address from RX
+* descriptor, we store the upper 32 bits when
+* allocating buffer, and put it back when using
+*
Re: [PATCH 5/10] dt: bindings: Add bindings for Marvell Xenon SD Host Controller
Hi Arnd, On jeu., nov. 24 2016, Arnd Bergmann <a...@arndb.de> wrote: > On Thursday, November 24, 2016 10:05:45 AM CET Ulf Hansson wrote: >> > You also mentioned other bindings using child nodes, but for this one >> > we have one controller with only one set of register with multiple slots >> > (Atmel is an example). Here each slot have it own set of register. >> > >> > Actually giving the fact that each slot is controlled by a different set >> > of register I wonder why the hardware can't also deduce the slot number >> > from the address register. For me it looks like an hardware bug but we >> > have to deal with it. >> > >> > Do you still think we needchild node here? >> >> Using child-nodes for slots like what's done in the atmel case, is >> currently broken. I would recommend to avoid using child-nodes for >> slots, if possible. >> >> To give you some more background, currently the mmc core treats child >> nodes as embedded non-removable cards or SDIO funcs. However, we can >> change to make child-nodes also allowed to describe slots, but it >> requires a specific compatible for "slots" and of course then we also >> need to update the DT parsing of the child-nodes in the mmc core. >> >> Documentation/devicetree/bindings/mmc/mmc.txt >> Documentation/devicetree/bindings/mmc/mmc-card.txt > > I don't see anything wrong with having child nodes for the slots > even with the current binding, under one condition: > > The mmc.txt binding above must refer only to the child node, while > the parent node conceptually becomes a plain bus or MFD that > happens to encapsulate multiple MMC host controllers, and possibly > provides some shared registers to them. I don't have an option for mmc in general, but using child node do not fit at all the xenon controller. For this controller each slot has its own set of register, so there is no common ressource to share so no advantage to use it. Using child node in our case will just make the code more complex for no benefit. Gregory > > Arnd -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Re: [PATCH net-next 1/5] net: mvneta: Use cacheable memory to store the rx buffer virtual address
Hi Jisheng,
On lun., nov. 28 2016, Jisheng Zhang <jszh...@marvell.com> wrote:
> Hi Gregory,
>
> On Fri, 25 Nov 2016 16:30:14 +0100 Gregory CLEMENT wrote:
>
>> Until now the virtual address of the received buffer were stored in the
>> cookie field of the rx descriptor. However, this field is 32-bits only
>> which prevents to use the driver on a 64-bits architecture.
>>
>> With this patch the virtual address is stored in an array not shared with
>> the hardware (no more need to use the DMA API). Thanks to this, it is
>> possible to use cache contrary to the access of the rx descriptor member.
>>
>> The change is done in the swbm path only because the hwbm uses the cookie
>> field, this also means that currently the hwbm is not usable in 64-bits.
>>
>> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
>> ---
>> drivers/net/ethernet/marvell/mvneta.c | 96
>> 1 file changed, 84 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/marvell/mvneta.c
>> b/drivers/net/ethernet/marvell/mvneta.c
>> index 87274d4ab102..b6849f88cab7 100644
>> --- a/drivers/net/ethernet/marvell/mvneta.c
>> +++ b/drivers/net/ethernet/marvell/mvneta.c
>> @@ -561,6 +561,9 @@ struct mvneta_rx_queue {
>> u32 pkts_coal;
>> u32 time_coal;
>>
>> +/* Virtual address of the RX buffer */
>> +void **buf_virt_addr;
>
> can we store buf_phys_addr in cacheable memory as well?
Even if we store in in cacheable memory we will still need to store it
in the buffer descriptor as it is used by the hardware.
>
>> +
>> /* Virtual address of the RX DMA descriptors array */
>> struct mvneta_rx_desc *descs;
>>
>> @@ -1573,10 +1576,14 @@ static void mvneta_tx_done_pkts_coal_set(struct
>> mvneta_port *pp,
>>
>> /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
>> static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
>> -u32 phys_addr, u32 cookie)
>> +u32 phys_addr, void *virt_addr,
>> +struct mvneta_rx_queue *rxq)
>> {
>> -rx_desc->buf_cookie = cookie;
>> +int i;
>> +
>> rx_desc->buf_phys_addr = phys_addr;
>> +i = rx_desc - rxq->descs;
>> +rxq->buf_virt_addr[i] = virt_addr;
>> }
>>
>> /* Decrement sent descriptors counter */
>> @@ -1781,7 +1788,8 @@ EXPORT_SYMBOL_GPL(mvneta_frag_free);
>>
>> /* Refill processing for SW buffer management */
>> static int mvneta_rx_refill(struct mvneta_port *pp,
>> -struct mvneta_rx_desc *rx_desc)
>> +struct mvneta_rx_desc *rx_desc,
>> +struct mvneta_rx_queue *rxq)
>>
>> {
>> dma_addr_t phys_addr;
>> @@ -1799,7 +1807,7 @@ static int mvneta_rx_refill(struct mvneta_port *pp,
>> return -ENOMEM;
>> }
>>
>> -mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data);
>> +mvneta_rx_desc_fill(rx_desc, phys_addr, data, rxq);
>> return 0;
>> }
>>
>> @@ -1861,7 +1869,12 @@ static void mvneta_rxq_drop_pkts(struct mvneta_port
>> *pp,
>>
>> for (i = 0; i < rxq->size; i++) {
>> struct mvneta_rx_desc *rx_desc = rxq->descs + i;
>> -void *data = (void *)rx_desc->buf_cookie;
>> +void *data;
>> +
>> +if (!pp->bm_priv)
>> +data = rxq->buf_virt_addr[i];
>> +else
>> +data = (void *)(uintptr_t)rx_desc->buf_cookie;
>>
>> dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
>> MVNETA_RX_BUF_SIZE(pp->pkt_size),
>> DMA_FROM_DEVICE);
>> @@ -1894,12 +1907,13 @@ static int mvneta_rx_swbm(struct mvneta_port *pp,
>> int rx_todo,
>> unsigned char *data;
>> dma_addr_t phys_addr;
>> u32 rx_status, frag_size;
>> -int rx_bytes, err;
>> +int rx_bytes, err, index;
>>
>> rx_done++;
>> rx_status = rx_desc->status;
>> rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
>> -data = (unsigned char *)rx_desc->buf_cookie;
>> +index = rx_desc - rxq->descs;
>> +data = (unsigned char *)rxq->buf_virt_addr[index];
>>
Re: [PATCH net-next 1/4] net: mvneta: Convert to be 64 bits compatible
Hi Arnd,
On jeu., nov. 24 2016, Arnd Bergmann <a...@arndb.de> wrote:
> On Thursday, November 24, 2016 4:37:36 PM CET Jisheng Zhang wrote:
>> solB (a SW shadow cookie) perhaps gives a better performance: in hot path,
>> such as mvneta_rx(), the driver accesses buf_cookie and buf_phys_addr of
>> rx_desc which is allocated by dma_alloc_coherent, it's noncacheable if the
>> device isn't cache-coherent. I didn't measure the performance difference,
>> because in fact we take solA as well internally. From your experience,
>> can the performance gain deserve the complex code?
>
> Yes, a read from uncached memory is fairly slow, so if you have a chance
> to avoid that it will probably help. When adding complexity to the code,
> it probably makes sense to take a runtime profile anyway quantify how
> much it gains.
>
> On machines that have cache-coherent DMA, accessing the descriptor
> should be fine, as you already have to load the entire cache line
> to read the status field.
>
> Looking at this snippet:
>
> rx_status = rx_desc->status;
> rx_bytes = rx_desc->data_size - (ETH_FCS_LEN +
> MVNETA_MH_SIZE);
> data = (unsigned char *)rx_desc->buf_cookie;
> phys_addr = rx_desc->buf_phys_addr;
> pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
> bm_pool = >bm_priv->bm_pools[pool_id];
>
> if (!mvneta_rxq_desc_is_first_last(rx_status) ||
> (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
> err_drop_frame_ret_pool:
> /* Return the buffer to the pool */
> mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
> rx_desc->buf_phys_addr);
> err_drop_frame:
>
>
> I think there is more room for optimizing if you start: you read
> the status field twice (the second one in MVNETA_RX_GET_BM_POOL_ID)
> and you can cache the buf_phys_addr along with the virtual address
> once you add that.
I agree we can optimize this code but it is not related to the 64 bits
conversion. Indeed this part is running when we use the HW buffer
management, however currently this part is not ready at all for 64
bits. The virtual address is directly handled by the hardware but it has
only 32 bits to store it in the cookie. So if we want to use the HWBM in
64 bits we need to redesign the code, (maybe by storing the virtual
address in a array and pass the index in the cookie).
Gregory
>
> Generally speaking, I'd recommend using READ_ONCE()/WRITE_ONCE()
> to access the descriptor fields, to ensure the compiler doesn't
> add extra references as well as to annotate the expensive
> operations.
>
> Arnd
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH] bus: mvebu-mbus: fix iounmap() in error path
Hi Luis,
On mer., nov. 16 2016, Luis Henriques <hen...@camandro.org> wrote:
> This patch fixes the following Coccinelle error:
>
> ./drivers/bus/mvebu-mbus.c:1115:2-8: \
> ERROR: missing iounmap; ioremap on line 1108 \
> and execution via conditional on line 1113
>
> Although all mvebu_mbus_common_init() callers seem to actually use
> _state in the 1st argument, this is still a bug that could be
> triggered by future changes.
>
> Signed-off-by: Luis Henriques <hen...@camandro.org>
Acked-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
and applied on mvebu/dt
Thanks,
Gregory
> ---
> drivers/bus/mvebu-mbus.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
> index c7f396903184..449466eff56f 100644
> --- a/drivers/bus/mvebu-mbus.c
> +++ b/drivers/bus/mvebu-mbus.c
> @@ -,7 +,7 @@ static int __init mvebu_mbus_common_init(struct
> mvebu_mbus_state *mbus,
>
> mbus->sdramwins_base = ioremap(sdramwins_phys_base, sdramwins_size);
> if (!mbus->sdramwins_base) {
> - iounmap(mbus_state.mbuswins_base);
> + iounmap(mbus->mbuswins_base);
> return -ENOMEM;
> }
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
[PATCH 3/10] mmc: sdhci: Export sdhci_execute_tuning() in sdhci.c
From: Ziji Hu <huz...@marvell.com>
Export sdhci_execute_tuning() from sdhci.c.
Thus vendor sdhci driver can execute its own tuning process.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/mmc/host/sdhci.c | 3 ++-
drivers/mmc/host/sdhci.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 8e6e4e37e3b4..e971abb1368f 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1950,7 +1950,7 @@ static int sdhci_prepare_hs400_tuning(struct mmc_host
*mmc, struct mmc_ios *ios)
return 0;
}
-static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
+int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
{
struct sdhci_host *host = mmc_priv(mmc);
u16 ctrl;
@@ -2139,6 +2139,7 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32
opcode)
spin_unlock_irqrestore(>lock, flags);
return err;
}
+EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
static int sdhci_select_drive_strength(struct mmc_card *card,
unsigned int max_dtr, int host_drv,
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index cd18b6f19c3b..95beadc66849 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -691,6 +691,7 @@ void sdhci_set_uhs_signaling(struct sdhci_host *host,
unsigned timing);
void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
struct mmc_ios *ios);
+int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
#ifdef CONFIG_PM
extern int sdhci_suspend_host(struct sdhci_host *host);
--
git-series 0.8.10
[PATCH 5/10] dt: bindings: Add bindings for Marvell Xenon SD Host Controller
From: Ziji Hu <huz...@marvell.com> Marvell Xenon SDHC can support eMMC/SD/SDIO. Add Xenon-specific properties. Also add properties for Xenon PHY setting. Signed-off-by: Hu Ziji <huz...@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> --- Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt | 161 +++- MAINTAINERS | 1 +- 2 files changed, 162 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt diff --git a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt new file mode 100644 index ..0d2d139494d3 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt @@ -0,0 +1,161 @@ +Marvell's Xenon SDHCI Controller device tree bindings +This file documents differences between the core mmc properties +described by mmc.txt and the properties used by the Xenon implementation. + +A single Xenon IP can support multiple slots. +Each slot acts as an independent SDHC. It owns independent resources, such +as register sets clock and PHY. +Each slot should have an independent device tree node. + +Required Properties: +- compatible: should be one of the following + - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SOC. + Must provide a second register area and marvell,pad-type. + - "marvell,xenon-sdhci": For controllers on all the SOCs, other than + Armada-3700. + +- clocks: + Array of clocks required for SDHCI. + Requires at least one for Xenon IP core. + Some SOCs require additional clock for AXI bus. + +- clock-names: + Array of names corresponding to clocks property. + The input clock for Xenon IP core should be named as "core". + The optional AXI clock should be named as "axi". + +- reg: + * For "marvell,xenon-sdhci", one register area for Xenon IP. + + * For "marvell,armada-3700-sdhci", two register areas. +The first one for Xenon IP register. The second one for the Armada 3700 SOC +PHY PAD Voltage Control register. +Please follow the examples with compatible "marvell,armada-3700-sdhci" +in below. +Please also check property marvell,pad-type in below. + +Optional Properties: +- marvell,xenon-slotno: + Indicate the corresponding bit index of current Xenon SDHC slot in + SDHC System Operation Control Register Bit[7:0]. + Set/clear the corresponding bit to enable/disable current Xenon SDHC + slot. + If this property is not provided, Xenon IP should contain only one + slot. + +- marvell,xenon-phy-type: + Xenon support mutilple types of PHYs. + To select eMMC 5.1 PHY, set: + marvell,xenon-phy-type = "emmc 5.1 phy" + eMMC 5.1 PHY is the default choice if this property is not provided. + To select eMMC 5.0 PHY, set: + marvell,xenon-phy-type = "emmc 5.0 phy" + To select SDH PHY, set: + marvell,xenon-phy-type = "sdh phy" + Please note that eMMC PHY is a general PHY for eMMC/SD/SDIO, other than for + eMMC only. + +- marvell,xenon-phy-znr: + Set PHY ZNR value. + Only available for eMMC PHY 5.1 and eMMC PHY 5.0. + valid range = [0:0x1F]. + ZNR is set as 0xF by default if this property is not provided. + +- marvell,xenon-phy-zpr: + Set PHY ZPR value. + Only available for eMMC PHY 5.1 and eMMC PHY 5.0. + valid range = [0:0x1F]. + ZPR is set as 0xF by default if this property is not provided. + +- marvell,xenon-phy-nr-success-tun: + Set the number of required consecutive successful sampling points used to + identify a valid sampling window, in tuning process. + Valid range = [1:7]. Set as 0x4 by default if this property is not provided. + +- marvell,xenon-phy-tun-step-divider: + Set the divider for calculating TUN_STEP. + Set as 64 by default if this property is not provided. + +- marvell,xenon-phy-slow-mode: + Force PHY into slow mode. + Only available when bus frequency lower than 50MHz in SDR mde. + Disabled by default. Please do not enable it unless it is necessary. + +- marvell,xenon-mask-conflict-err: + Mask Conflict Error alert on some SOC. Disabled by default. + +- marvell,xenon-tun-count: + Xenon SDHC SOC usually doesn't provide re-tuning counter in + Capabilities Register 3 Bit[11:8]. + This property provides the re-tuning counter. + If this property is not set, default re-tuning counter will + be set as 0x9 in driver. + +- marvell,pad-type: + Type of Armada 3700 SOC PHY PAD Voltiage Controller register. + Only valid when "marvell,armada-3700-sdhci" is selected. + Two types: "sd" and "fixed-1-8v". + If "sd" is slected, SOC PHY PAD is set as 3.3V at the beginning and is + switched to 1.8V when SD in UHS-I. + If "fixed-1-8v" is slected, SOC PHY PAD is fixed 1.8V, such as for eMMC. + Please follow the ex
[PATCH 7/10] mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC
From: Ziji Hu <huz...@marvell.com>
Marvell Xenon eMMC/SD/SDIO Host Controller contains PHY.
Three types of PHYs are supported.
Add support to multiple types of PHYs init and configuration.
Add register definitions of PHYs.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
MAINTAINERS|2 +-
drivers/mmc/host/Makefile |2 +-
drivers/mmc/host/sdhci-xenon-phy.c | 1181 +-
drivers/mmc/host/sdhci-xenon-phy.h | 157 -
drivers/mmc/host/sdhci-xenon.c |4 +-
drivers/mmc/host/sdhci-xenon.h | 17 +-
6 files changed, 1361 insertions(+), 2 deletions(-)
create mode 100644 drivers/mmc/host/sdhci-xenon-phy.c
create mode 100644 drivers/mmc/host/sdhci-xenon-phy.h
diff --git a/MAINTAINERS b/MAINTAINERS
index d92f4175574b..bb33286aeb48 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7608,7 +7608,7 @@ MARVELL XENON MMC/SD/SDIO HOST CONTROLLER DRIVER
M: Ziji Hu <huz...@marvell.com>
L: linux-...@vger.kernel.org
S: Supported
-F: drivers/mmc/host/sdhci-xenon.*
+F: drivers/mmc/host/sdhci-xenon*
F: Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
MATROX FRAMEBUFFER DRIVER
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 75eaf743486c..4f2854556ff7 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -82,4 +82,4 @@ ifeq ($(CONFIG_CB710_DEBUG),y)
endif
obj-$(CONFIG_MMC_SDHCI_XENON) += sdhci-xenon-driver.o
-sdhci-xenon-driver-y += sdhci-xenon.o
+sdhci-xenon-driver-y += sdhci-xenon.o sdhci-xenon-phy.o
diff --git a/drivers/mmc/host/sdhci-xenon-phy.c
b/drivers/mmc/host/sdhci-xenon-phy.c
new file mode 100644
index ..af32f8842e0b
--- /dev/null
+++ b/drivers/mmc/host/sdhci-xenon-phy.c
@@ -0,0 +1,1181 @@
+/*
+ * PHY support for Xenon SDHC
+ *
+ * Copyright (C) 2016 Marvell, All Rights Reserved.
+ *
+ * Author: Hu Ziji <huz...@marvell.com>
+ * Date: 2016-8-24
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "sdhci.h"
+#include "sdhci-pltfm.h"
+#include "sdhci-xenon.h"
+
+static const char * const phy_types[] = {
+ "sdh phy",
+ "emmc 5.0 phy",
+ "emmc 5.1 phy"
+};
+
+enum phy_type_enum {
+ SDH_PHY,
+ EMMC_5_0_PHY,
+ EMMC_5_1_PHY,
+ NR_PHY_TYPES
+};
+
+struct soc_pad_ctrl_table {
+ const char *soc;
+ void (*set_soc_pad)(struct sdhci_host *host,
+ unsigned char signal_voltage);
+};
+
+struct soc_pad_ctrl {
+ /* Register address of SOC PHY PAD ctrl */
+ void __iomem*reg;
+ /* SOC PHY PAD ctrl type */
+ enum soc_pad_ctrl_type pad_type;
+ /* SOC specific operation to set SOC PHY PAD */
+ void (*set_soc_pad)(struct sdhci_host *host,
+ unsigned char signal_voltage);
+};
+
+static struct xenon_emmc_phy_regs xenon_emmc_5_0_phy_regs = {
+ .timing_adj = EMMC_5_0_PHY_TIMING_ADJUST,
+ .func_ctrl = EMMC_5_0_PHY_FUNC_CONTROL,
+ .pad_ctrl = EMMC_5_0_PHY_PAD_CONTROL,
+ .pad_ctrl2 = EMMC_5_0_PHY_PAD_CONTROL2,
+ .dll_ctrl = EMMC_5_0_PHY_DLL_CONTROL,
+ .logic_timing_adj = EMMC_5_0_PHY_LOGIC_TIMING_ADJUST,
+ .delay_mask = EMMC_5_0_PHY_FIXED_DELAY_MASK,
+ .dll_update = DLL_UPDATE_STROBE_5_0,
+};
+
+static struct xenon_emmc_phy_regs xenon_emmc_5_1_phy_regs = {
+ .timing_adj = EMMC_PHY_TIMING_ADJUST,
+ .func_ctrl = EMMC_PHY_FUNC_CONTROL,
+ .pad_ctrl = EMMC_PHY_PAD_CONTROL,
+ .pad_ctrl2 = EMMC_PHY_PAD_CONTROL2,
+ .dll_ctrl = EMMC_PHY_DLL_CONTROL,
+ .logic_timing_adj = EMMC_PHY_LOGIC_TIMING_ADJUST,
+ .delay_mask = EMMC_PHY_FIXED_DELAY_MASK,
+ .dll_update = DLL_UPDATE,
+};
+
+static int xenon_delay_adj_test(struct mmc_card *card);
+
+/*
+ * eMMC PHY configuration and operations
+ */
+struct emmc_phy_params {
+ boolslow_mode;
+
+ u8 znr;
+ u8 zpr;
+
+ /* Nr of consecutive Sampling Points of a Valid Sampling Window */
+ u8 nr_tun_times;
+ /* Divider for calculating Tuning Step */
+ u8 tun_step_divider;
+
+ struct soc_pad_ctrl pad_ctrl;
+};
+
+static void xenon_emmc_phy_strobe_delay_adj(struct sdhci_host *host,
+ struct mmc_card *card);
+static int xenon_emmc_phy_fix_sampl_delay_adj(struct sdhci_host *host,
+ struct mmc_card *card);
+static void xenon_emmc_phy_set(struct sdhci_host *host,
+
[PATCH 8/10] arm64: dts: marvell: add eMMC support for Armada 37xx
Add the eMMC support for Armada 37xx SoC and enable it in the Armada 3720
DB board.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 8
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 11 +++
2 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index 1372e9a6aaa4..9107dd3e2a44 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -72,6 +72,14 @@
status = "okay";
};
+ {
+ non-removable;
+ bus-width = <8>;
+ marvell,xenon-emmc;
+ marvell,pad-type = "fixed-1-8v";
+ status = "okay";
+};
+
/* CON31 */
{
status = "okay";
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index c4762538ec01..0c4cafe92e66 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -161,6 +161,17 @@
};
};
+ sdhci0: sdhci@d8000 {
+ compatible = "marvell,armada-3700-sdhci",
+ "marvell,sdhci-xenon";
+ reg = <0xd8000 0x300
+ 0x17808 0x4>;
+ interrupts = ;
+ clocks = <_perih_clk 0>;
+ clock-names = "core";
+ status = "disabled";
+ };
+
sata: sata@e {
compatible = "marvell,armada-3700-ahci";
reg = <0xe 0x2000>;
--
git-series 0.8.10
[PATCH 0/10] mmc: Add support to Marvell Xenon SD Host Controller
Hello, This the second version of the series adding support for the SDHCI Xenon controller. It can be currently found on the Armada 37xx and the Armada 7K/8K but will be also used in more Marvell SoC (and not only the mvebu ones actually). Some of the remarks had been taking into account since the first version, according to Ziji Hu, here are the following chcanges: "Changes in V2: rebase on v4.9-rc2. Re-write Xenon bindings. Ajust Xenon DT property naming. Add a new DT property to indicate eMMC card type, instead of using variable card_candidate. Clear quirks SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 in Xenon platform data Add support to HS400 retuning." I think the main open point which remains is about issuing commands from the ->set_ios() callback (in patch 7). Ulf, could you comment about it? Thanks, Gregory Gregory CLEMENT (3): arm64: dts: marvell: add eMMC support for Armada 37xx arm64: dts: marvell: add sdhci support for Armada 7K/8K arm64: configs: enable SDHCI driver for Xenon Ziji Hu (7): mmc: sdhci: Export sdhci_set_ios() from sdhci.c mmc: sdhci: Export sdhci_start_signal_voltage_switch() in sdhci.c mmc: sdhci: Export sdhci_execute_tuning() in sdhci.c MAINTAINERS: add entry for Marvell Xenon MMC Host Controller drivers dt: bindings: Add bindings for Marvell Xenon SD Host Controller mmc: sdhci-xenon: Add Marvell Xenon SDHC core functionality mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt | 161 +- MAINTAINERS |7 +- arch/arm64/boot/dts/marvell/armada-3720-db.dts|8 +- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 11 +- arch/arm64/boot/dts/marvell/armada-7040-db.dts|8 +- arch/arm64/boot/dts/marvell/armada-ap806.dtsi |9 +- arch/arm64/configs/defconfig |1 +- drivers/mmc/host/Kconfig |9 +- drivers/mmc/host/Makefile |3 +- drivers/mmc/host/sdhci-xenon-phy.c| 1181 +++- drivers/mmc/host/sdhci-xenon-phy.h| 157 +- drivers/mmc/host/sdhci-xenon.c| 598 - drivers/mmc/host/sdhci-xenon.h| 159 +- drivers/mmc/host/sdhci.c | 11 +- drivers/mmc/host/sdhci.h |4 +- 15 files changed, 2323 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt create mode 100644 drivers/mmc/host/sdhci-xenon-phy.c create mode 100644 drivers/mmc/host/sdhci-xenon-phy.h create mode 100644 drivers/mmc/host/sdhci-xenon.c create mode 100644 drivers/mmc/host/sdhci-xenon.h base-commit: 9fe68cad6e74967b88d0c6aeca7d9cd6b6e91942 -- git-series 0.8.10
[PATCH 2/10] mmc: sdhci: Export sdhci_start_signal_voltage_switch() in sdhci.c
From: Ziji Hu <huz...@marvell.com>
Export sdhci_start_signal_voltage_switch() from sdhci.c.
Thus vendor sdhci driver can implement its own signal voltage
switch routine.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/mmc/host/sdhci.c | 5 +++--
drivers/mmc/host/sdhci.h | 2 ++
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index ea06faf8a437..8e6e4e37e3b4 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1832,8 +1832,8 @@ static void sdhci_enable_sdio_irq(struct mmc_host *mmc,
int enable)
spin_unlock_irqrestore(>lock, flags);
}
-static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
-struct mmc_ios *ios)
+int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
+ struct mmc_ios *ios)
{
struct sdhci_host *host = mmc_priv(mmc);
u16 ctrl;
@@ -1925,6 +1925,7 @@ static int sdhci_start_signal_voltage_switch(struct
mmc_host *mmc,
return 0;
}
}
+EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
static int sdhci_card_busy(struct mmc_host *mmc)
{
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 37771de4cafa..cd18b6f19c3b 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -689,6 +689,8 @@ void sdhci_set_bus_width(struct sdhci_host *host, int
width);
void sdhci_reset(struct sdhci_host *host, u8 mask);
void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
+int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
+ struct mmc_ios *ios);
#ifdef CONFIG_PM
extern int sdhci_suspend_host(struct sdhci_host *host);
--
git-series 0.8.10
[PATCH 10/10] arm64: configs: enable SDHCI driver for Xenon
This patch enables the driver for the SDHCI controller found on the Marvell Armada 3700 and 7K/8K ARM64 SoCs. Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+), 0 deletions(-) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index dab2cb0c1f1c..2d1f5ee62b18 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -353,6 +353,7 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_EXYNOS=y CONFIG_MMC_DW_K3=y CONFIG_MMC_SUNXI=y +CONFIG_MMC_SDHCI_XENON=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y -- git-series 0.8.10
[PATCH 6/10] mmc: sdhci-xenon: Add Marvell Xenon SDHC core functionality
From: Ziji Hu <huz...@marvell.com>
Add Xenon eMMC/SD/SDIO host controller core functionality.
Add Xenon specific intialization process.
Add Xenon specific mmc_host_ops APIs.
Add Xenon specific register definitions.
Add CONFIG_MMC_SDHCI_XENON support in drivers/mmc/host/Kconfig.
Marvell Xenon SDHC conforms to SD Physical Layer Specification
Version 3.01 and is designed according to the guidelines provided
in the SD Host Controller Standard Specification Version 3.00.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
MAINTAINERS| 1 +-
drivers/mmc/host/Kconfig | 9 +-
drivers/mmc/host/Makefile | 3 +-
drivers/mmc/host/sdhci-xenon.c | 594 ++-
drivers/mmc/host/sdhci-xenon.h | 142 -
5 files changed, 749 insertions(+), 0 deletions(-)
create mode 100644 drivers/mmc/host/sdhci-xenon.c
create mode 100644 drivers/mmc/host/sdhci-xenon.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 850a0afb0c8d..d92f4175574b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7608,6 +7608,7 @@ MARVELL XENON MMC/SD/SDIO HOST CONTROLLER DRIVER
M: Ziji Hu <huz...@marvell.com>
L: linux-...@vger.kernel.org
S: Supported
+F: drivers/mmc/host/sdhci-xenon.*
F: Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
MATROX FRAMEBUFFER DRIVER
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 5274f503a39a..85a53623526a 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -798,3 +798,12 @@ config MMC_SDHCI_BRCMSTB
Broadcom STB SoCs.
If unsure, say Y.
+
+config MMC_SDHCI_XENON
+ tristate "Marvell Xenon eMMC/SD/SDIO SDHCI driver"
+ depends on MMC_SDHCI && MMC_SDHCI_PLTFM
+ help
+ This selects Marvell Xenon eMMC/SD/SDIO SDHCI.
+ If you have a machine with integrated Marvell Xenon SDHC IP,
+ say Y or M here.
+ If unsure, say N.
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index e2bdaaf43184..75eaf743486c 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -80,3 +80,6 @@ obj-$(CONFIG_MMC_SDHCI_BRCMSTB) +=
sdhci-brcmstb.o
ifeq ($(CONFIG_CB710_DEBUG),y)
CFLAGS-cb710-mmc+= -DDEBUG
endif
+
+obj-$(CONFIG_MMC_SDHCI_XENON) += sdhci-xenon-driver.o
+sdhci-xenon-driver-y += sdhci-xenon.o
diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c
new file mode 100644
index ..3ea059f2aaab
--- /dev/null
+++ b/drivers/mmc/host/sdhci-xenon.c
@@ -0,0 +1,594 @@
+/*
+ * Driver for Marvell SOC Platform Group Xenon SDHC as a platform device
+ *
+ * Copyright (C) 2016 Marvell, All Rights Reserved.
+ *
+ * Author: Hu Ziji <huz...@marvell.com>
+ * Date: 2016-8-24
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * Inspired by Jisheng Zhang <jszh...@marvell.com>
+ * Special thanks to Video BG4 project team.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "sdhci-pltfm.h"
+#include "sdhci.h"
+#include "sdhci-xenon.h"
+
+/* Set SDCLK-off-while-idle */
+static void xenon_set_sdclk_off_idle(struct sdhci_host *host,
+unsigned char slot_idx, bool enable)
+{
+ u32 reg;
+ u32 mask;
+
+ reg = sdhci_readl(host, SDHC_SYS_OP_CTRL);
+ /* Get the bit shift basing on the slot index */
+ mask = (0x1 << (SDCLK_IDLEOFF_ENABLE_SHIFT + slot_idx));
+ if (enable)
+ reg |= mask;
+ else
+ reg &= ~mask;
+
+ sdhci_writel(host, reg, SDHC_SYS_OP_CTRL);
+}
+
+/* Enable/Disable the Auto Clock Gating function */
+static void xenon_set_acg(struct sdhci_host *host, bool enable)
+{
+ u32 reg;
+
+ reg = sdhci_readl(host, SDHC_SYS_OP_CTRL);
+ if (enable)
+ reg &= ~AUTO_CLKGATE_DISABLE_MASK;
+ else
+ reg |= AUTO_CLKGATE_DISABLE_MASK;
+ sdhci_writel(host, reg, SDHC_SYS_OP_CTRL);
+}
+
+/* Enable this slot */
+static void xenon_enable_slot(struct sdhci_host *host,
+ unsigned char slot_idx)
+{
+ u32 reg;
+
+ reg = sdhci_readl(host, SDHC_SYS_OP_CTRL);
+ reg |= (BIT(slot_idx) << SLOT_ENABLE_SHIFT);
+ sdhci_writel(host, reg, SDHC_SYS_OP_CTRL);
+
+ /*
+* Manually set the flag which all the slots require,
+* including SD, eMMC, SDIO
+*/
+ host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
+}
+
+/* Disable this slot */
+static void xenon_disable_slot(struct sdhci_host *host,
+ unsigned char sl
[PATCH 1/10] mmc: sdhci: Export sdhci_set_ios() from sdhci.c
From: Ziji Hu <huz...@marvell.com>
Export sdhci_set_ios() in sdhci.c.
Thus vendor sdhci driver can implement its own set_ios() routine.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/mmc/host/sdhci.c | 3 ++-
drivers/mmc/host/sdhci.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 71654b90227f..ea06faf8a437 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1563,7 +1563,7 @@ void sdhci_set_uhs_signaling(struct sdhci_host *host,
unsigned timing)
}
EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
-static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
struct sdhci_host *host = mmc_priv(mmc);
unsigned long flags;
@@ -1723,6 +1723,7 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct
mmc_ios *ios)
mmiowb();
spin_unlock_irqrestore(>lock, flags);
}
+EXPORT_SYMBOL_GPL(sdhci_set_ios);
static int sdhci_get_cd(struct mmc_host *mmc)
{
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 766df17fb7eb..37771de4cafa 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -688,6 +688,7 @@ void sdhci_set_power_noreg(struct sdhci_host *host,
unsigned char mode,
void sdhci_set_bus_width(struct sdhci_host *host, int width);
void sdhci_reset(struct sdhci_host *host, u8 mask);
void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
+void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
#ifdef CONFIG_PM
extern int sdhci_suspend_host(struct sdhci_host *host);
--
git-series 0.8.10
[PATCH 9/10] arm64: dts: marvell: add sdhci support for Armada 7K/8K
Also enable it on the Armada 7040 DB board
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 8
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 9 +
2 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index 070b589680c5..f8bdabdbd864 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -146,3 +146,11 @@
_usb3_1 {
status = "okay";
};
+
+ {
+ status = "okay";
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+ marvell,xenon-emmc;
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index 7b6136182ad0..174c41b24d4c 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -229,6 +229,15 @@
};
+ sdhci0: sdhci@6e {
+ compatible = "marvell,xenon-sdhci";
+ reg = <0x6e 0x300>;
+ interrupts = ;
+ clock-names = "core";
+ clocks = <_syscon0 1 4>;
+ status = "disabled";
+ };
+
ap_syscon: system-controller@6f4000 {
compatible = "marvell,ap806-system-controller",
"syscon";
--
git-series 0.8.10
[PATCH 4/10] MAINTAINERS: add entry for Marvell Xenon MMC Host Controller drivers
From: Ziji Hu <huz...@marvell.com> Add maintainer entry for Marvell Xenon eMMC/SD/SDIO Host Controller drivers. Signed-off-by: Hu Ziji <huz...@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> --- MAINTAINERS | 5 + 1 file changed, 5 insertions(+), 0 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index c44795306342..1a5c4c30ea24 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7604,6 +7604,11 @@ M: Nicolas Pitre <n...@fluxnic.net> S: Odd Fixes F: drivers/mmc/host/mvsdio.* +MARVELL XENON MMC/SD/SDIO HOST CONTROLLER DRIVER +M: Ziji Hu <huz...@marvell.com> +L: linux-...@vger.kernel.org +S: Supported + MATROX FRAMEBUFFER DRIVER L: linux-fb...@vger.kernel.org S: Orphan -- git-series 0.8.10
Re: [PATCH] ARM: mvebu: Update comment for main PLL frequency
Hi Chris,
On mer., oct. 26 2016, Chris Packham <chris.pack...@alliedtelesis.co.nz> wrote:
> The actual frequency was updated in commit ae142bd99765 ("ARM: mvebu:
> Fix the main PLL frequency on Armada 375, 38x and 39x SoCs") but the
> comment was not updated. Update it now.
>
> Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
Applied on mvebu/dt
Thanks,
Gregory
> ---
> arch/arm/boot/dts/armada-375.dtsi | 2 +-
> arch/arm/boot/dts/armada-38x.dtsi | 2 +-
> arch/arm/boot/dts/armada-39x.dtsi | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/boot/dts/armada-375.dtsi
> b/arch/arm/boot/dts/armada-375.dtsi
> index cc952cf8ec30..45fa92f9cf5c 100644
> --- a/arch/arm/boot/dts/armada-375.dtsi
> +++ b/arch/arm/boot/dts/armada-375.dtsi
> @@ -65,7 +65,7 @@
> };
>
> clocks {
> - /* 2 GHz fixed main PLL */
> + /* 1 GHz fixed main PLL */
> mainpll: mainpll {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> diff --git a/arch/arm/boot/dts/armada-38x.dtsi
> b/arch/arm/boot/dts/armada-38x.dtsi
> index 2d7668848c5a..7450e9fea45d 100644
> --- a/arch/arm/boot/dts/armada-38x.dtsi
> +++ b/arch/arm/boot/dts/armada-38x.dtsi
> @@ -661,7 +661,7 @@
> };
>
> clocks {
> - /* 2 GHz fixed main PLL */
> + /* 1 GHz fixed main PLL */
> mainpll: mainpll {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> diff --git a/arch/arm/boot/dts/armada-39x.dtsi
> b/arch/arm/boot/dts/armada-39x.dtsi
> index 34cba87f9200..de171baffcf6 100644
> --- a/arch/arm/boot/dts/armada-39x.dtsi
> +++ b/arch/arm/boot/dts/armada-39x.dtsi
> @@ -573,7 +573,7 @@
> };
>
> clocks {
> - /* 2 GHz fixed main PLL */
> + /* 1 GHz fixed main PLL */
> mainpll: mainpll {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> --
> 2.10.1
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH 0/10] mmc: Add support to Marvell Xenon SD Host Controller
Hi, On lun., oct. 31 2016, Gregory CLEMENT <gregory.clem...@free-electrons.com> wrote: > Hello, > > This the second version of the series adding support for the SDHCI > Xenon controller. It can be currently found on the Armada 37xx and the > Armada 7K/8K but will be also used in more Marvell SoC (and not only > the mvebu ones actually). > > Some of the remarks had been taking into account since the first > version, according to Ziji Hu, here are the following chcanges: > "Changes in V2: > rebase on v4.9-rc2. > Re-write Xenon bindings. Ajust Xenon DT property naming. > Add a new DT property to indicate eMMC card type, instead of using > variable card_candidate. > Clear quirks SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 in Xenon platform data > Add support to HS400 retuning." > > I think the main open point which remains is about issuing commands > from the ->set_ios() callback (in patch 7). > Ulf, could you comment about it? A few comments: - I forgot to add the v2 prefix on the series I hope it won't be too annoying, if needed I can re-post the series with the correct title. - I also forgot to add my Reviewed-by flag on the 7 first patches, I will add them back on the v3. - For the ones who want to get the series using git here is the place you can get it here: repository: g...@github.com:MISL-EBU-System-SW/mainline-public.git branch: sdhci-xenon-v2 Thanks, Gregory > > Thanks, > > Gregory > > Gregory CLEMENT (3): > arm64: dts: marvell: add eMMC support for Armada 37xx > arm64: dts: marvell: add sdhci support for Armada 7K/8K > arm64: configs: enable SDHCI driver for Xenon > > Ziji Hu (7): > mmc: sdhci: Export sdhci_set_ios() from sdhci.c > mmc: sdhci: Export sdhci_start_signal_voltage_switch() in sdhci.c > mmc: sdhci: Export sdhci_execute_tuning() in sdhci.c > MAINTAINERS: add entry for Marvell Xenon MMC Host Controller drivers > dt: bindings: Add bindings for Marvell Xenon SD Host Controller > mmc: sdhci-xenon: Add Marvell Xenon SDHC core functionality > mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC > > Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt | 161 +- > MAINTAINERS |7 +- > arch/arm64/boot/dts/marvell/armada-3720-db.dts|8 +- > arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 11 +- > arch/arm64/boot/dts/marvell/armada-7040-db.dts|8 +- > arch/arm64/boot/dts/marvell/armada-ap806.dtsi |9 +- > arch/arm64/configs/defconfig |1 +- > drivers/mmc/host/Kconfig |9 +- > drivers/mmc/host/Makefile |3 +- > drivers/mmc/host/sdhci-xenon-phy.c| 1181 +++- > drivers/mmc/host/sdhci-xenon-phy.h| 157 +- > drivers/mmc/host/sdhci-xenon.c| 598 - > drivers/mmc/host/sdhci-xenon.h| 159 +- > drivers/mmc/host/sdhci.c | 11 +- > drivers/mmc/host/sdhci.h |4 +- > 15 files changed, 2323 insertions(+), 4 deletions(-) > create mode 100644 > Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt > create mode 100644 drivers/mmc/host/sdhci-xenon-phy.c > create mode 100644 drivers/mmc/host/sdhci-xenon-phy.h > create mode 100644 drivers/mmc/host/sdhci-xenon.c > create mode 100644 drivers/mmc/host/sdhci-xenon.h > > base-commit: 9fe68cad6e74967b88d0c6aeca7d9cd6b6e91942 > -- > git-series 0.8.10 -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Re: [PATCH] ARM/orion/gpio: Replace three seq_printf() calls by seq_puts() in orion_gpio_dbg_show()
Hi Markus,
On dim., oct. 16 2016, SF Markus Elfring <elfr...@users.sourceforge.net> wrote:
> From: Markus Elfring <elfr...@users.sourceforge.net>
> Date: Sun, 16 Oct 2016 12:30:48 +0200
>
> Strings which did not contain data format specifications should be put
> into a sequence. Thus use the corresponding function "seq_puts".
>
> This issue was detected by using the Coccinelle software.
>
Applied on mvebu/drivers
Thanks,
Gregory
> Signed-off-by: Markus Elfring <elfr...@users.sourceforge.net>
> ---
> arch/arm/plat-orion/gpio.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
> index f740693..26a531e 100644
> --- a/arch/arm/plat-orion/gpio.c
> +++ b/arch/arm/plat-orion/gpio.c
> @@ -478,13 +478,13 @@ static void orion_gpio_dbg_show(struct seq_file *s,
> struct gpio_chip *chip)
> (data_in ^ in_pol) & msk ? "hi" : "lo",
> in_pol & msk ? "lo" : "hi");
> if (!((edg_msk | lvl_msk) & msk)) {
> - seq_printf(s, " disabled\n");
> + seq_puts(s, " disabled\n");
> continue;
> }
> if (edg_msk & msk)
> - seq_printf(s, " edge ");
> + seq_puts(s, " edge ");
> if (lvl_msk & msk)
> - seq_printf(s, " level");
> + seq_puts(s, " level");
> seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
> }
> }
> --
> 2.10.1
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
[PATCH v3 net-next 0/6] Support Armada 37xx SoC (ARMv8 64-bits) in mvneta driver
Hi, The Armada 37xx is a new ARMv8 SoC from Marvell using same network controller as the older Armada 370/38x/XP SoCs. This series adapts the driver in order to be able to use it on this new SoC. The main changes are: - 64-bits support: the first patches allow using the driver on a 64-bit architecture. - MBUS support: the mbus configuration is different on Armada 37xx from the older SoCs. - per cpu interrupt: Armada 37xx do not support per cpu interrupt for the NETA IP, the non-per-CPU behavior was added back. The first item is solved by patches 1 to 3. The 2 last items are solved by patch 4. In patch 5 the dt support is added. Beside Armada 37xx, the series have been tested on Armada XP and Armada 38x (with Hardware Buffer Management and with Software Buffer Managment). Thanks, Gregory Gregory CLEMENT (4): net: mvneta: Optimize rx path for small frame net: mvneta: Use cacheable memory to store the rx buffer virtual address net: mvneta: Only disable mvneta_bm for 64-bits ARM64: dts: marvell: Add network support for Armada 3700 Marcin Wojtas (2): net: mvneta: Convert to be 64 bits compatible net: mvneta: Add network support for Armada 3700 SoC Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt | 7 +- arch/arm64/boot/dts/marvell/armada-3720-db.dts| 23 - arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 23 - drivers/net/ethernet/marvell/Kconfig | 10 +- drivers/net/ethernet/marvell/mvneta.c | 400 ++-- 5 files changed, 361 insertions(+), 102 deletions(-) base-commit: 436accebb53021ef7c63535f60bda410aa87c136 -- git-series 0.8.10
Re: [PATCH v3 net-next 2/6] net: mvneta: Use cacheable memory to store the rx buffer virtual address
Hi Marcin,
On mar., nov. 29 2016, Marcin Wojtas <m...@semihalf.com> wrote:
> Gregory,
>
> 2016-11-29 11:19 GMT+01:00 Gregory CLEMENT
> <gregory.clem...@free-electrons.com>:
>> Hi Marcin,
>>
>> On mar., nov. 29 2016, Marcin Wojtas <m...@semihalf.com> wrote:
>>
>>> Hi Gregory,
>>>
>>> Another remark below, sorry for noise.
>>>
>>> 2016-11-29 10:37 GMT+01:00 Gregory CLEMENT
>>> <gregory.clem...@free-electrons.com>:
>>>> Until now the virtual address of the received buffer were stored in the
>>>> cookie field of the rx descriptor. However, this field is 32-bits only
>>>> which prevents to use the driver on a 64-bits architecture.
>>>>
>>>> With this patch the virtual address is stored in an array not shared with
>>>> the hardware (no more need to use the DMA API). Thanks to this, it is
>>>> possible to use cache contrary to the access of the rx descriptor member.
>>>>
>>>> The change is done in the swbm path only because the hwbm uses the cookie
>>>> field, this also means that currently the hwbm is not usable in 64-bits.
>>>>
>>>> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
>>>> ---
>>>> drivers/net/ethernet/marvell/mvneta.c | 93
>>>> 1 file changed, 81 insertions(+), 12 deletions(-)
>>>>
>>>> diff --git a/drivers/net/ethernet/marvell/mvneta.c
>>>> b/drivers/net/ethernet/marvell/mvneta.c
>>>> index 1b84f746d748..32b142d0e44e 100644
>>>> --- a/drivers/net/ethernet/marvell/mvneta.c
>>>> +++ b/drivers/net/ethernet/marvell/mvneta.c
>>>> @@ -561,6 +561,9 @@ struct mvneta_rx_queue {
>>>> u32 pkts_coal;
>>>> u32 time_coal;
>>>>
>>>> + /* Virtual address of the RX buffer */
>>>> + void **buf_virt_addr;
>>>> +
>>>> /* Virtual address of the RX DMA descriptors array */
>>>> struct mvneta_rx_desc *descs;
>>>>
>>>> @@ -1573,10 +1576,14 @@ static void mvneta_tx_done_pkts_coal_set(struct
>>>> mvneta_port *pp,
>>>>
>>>> /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
>>>> static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
>>>> - u32 phys_addr, u32 cookie)
>>>> + u32 phys_addr, void *virt_addr,
>>>> + struct mvneta_rx_queue *rxq)
>>>> {
>>>> - rx_desc->buf_cookie = cookie;
>>>> + int i;
>>>> +
>>>> rx_desc->buf_phys_addr = phys_addr;
>>>> + i = rx_desc - rxq->descs;
>>>> + rxq->buf_virt_addr[i] = virt_addr;
>>>> }
>>>>
>>>> /* Decrement sent descriptors counter */
>>>> @@ -1781,7 +1788,8 @@ EXPORT_SYMBOL_GPL(mvneta_frag_free);
>>>>
>>>> /* Refill processing for SW buffer management */
>>>> static int mvneta_rx_refill(struct mvneta_port *pp,
>>>> - struct mvneta_rx_desc *rx_desc)
>>>> + struct mvneta_rx_desc *rx_desc,
>>>> + struct mvneta_rx_queue *rxq)
>>>>
>>>> {
>>>> dma_addr_t phys_addr;
>>>> @@ -1799,7 +1807,7 @@ static int mvneta_rx_refill(struct mvneta_port *pp,
>>>> return -ENOMEM;
>>>> }
>>>>
>>>> - mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data);
>>>> + mvneta_rx_desc_fill(rx_desc, phys_addr, data, rxq);
>>>> return 0;
>>>> }
>>>>
>>>> @@ -1861,7 +1869,12 @@ static void mvneta_rxq_drop_pkts(struct mvneta_port
>>>> *pp,
>>>>
>>>> for (i = 0; i < rxq->size; i++) {
>>>> struct mvneta_rx_desc *rx_desc = rxq->descs + i;
>>>> - void *data = (void *)rx_desc->buf_cookie;
>>>> + void *data;
>>>> +
>>>> + if (!pp->bm_priv)
>>>> + data = rxq->buf_virt_addr[i];
>>>> + else
>>>> + data = (void *)(uintptr_t)rx_desc->buf_cookie;
>>>
>>> Dropping packets for HWBM (in fact returning dropped buffers to the
>>> pool) is done a couple of lines above. This point will never be
>>
>> indeed I changed the code at every place the buf_cookie was used and
>> missed the fact that for HWBM this code was never reached.
>>
>>> reached with HWBM enabled (and it's also incorrect).
>>
>> What is incorrect?
>>
>
> Possible dma_unmapping + mvneta_frag_free for buffers in HWBM, when
> dropping packets.
Yes sure, but as you mentioned this code is never reached when HWBM is
enabled. I thought there was other part of the code to fix.
Thanks,
Gregory
>
> Thanks,
> Marcin
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
[PATCH v3 net-next 2/6] net: mvneta: Use cacheable memory to store the rx buffer virtual address
Until now the virtual address of the received buffer were stored in the
cookie field of the rx descriptor. However, this field is 32-bits only
which prevents to use the driver on a 64-bits architecture.
With this patch the virtual address is stored in an array not shared with
the hardware (no more need to use the DMA API). Thanks to this, it is
possible to use cache contrary to the access of the rx descriptor member.
The change is done in the swbm path only because the hwbm uses the cookie
field, this also means that currently the hwbm is not usable in 64-bits.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 93
1 file changed, 81 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 1b84f746d748..32b142d0e44e 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -561,6 +561,9 @@ struct mvneta_rx_queue {
u32 pkts_coal;
u32 time_coal;
+ /* Virtual address of the RX buffer */
+ void **buf_virt_addr;
+
/* Virtual address of the RX DMA descriptors array */
struct mvneta_rx_desc *descs;
@@ -1573,10 +1576,14 @@ static void mvneta_tx_done_pkts_coal_set(struct
mvneta_port *pp,
/* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
- u32 phys_addr, u32 cookie)
+ u32 phys_addr, void *virt_addr,
+ struct mvneta_rx_queue *rxq)
{
- rx_desc->buf_cookie = cookie;
+ int i;
+
rx_desc->buf_phys_addr = phys_addr;
+ i = rx_desc - rxq->descs;
+ rxq->buf_virt_addr[i] = virt_addr;
}
/* Decrement sent descriptors counter */
@@ -1781,7 +1788,8 @@ EXPORT_SYMBOL_GPL(mvneta_frag_free);
/* Refill processing for SW buffer management */
static int mvneta_rx_refill(struct mvneta_port *pp,
- struct mvneta_rx_desc *rx_desc)
+ struct mvneta_rx_desc *rx_desc,
+ struct mvneta_rx_queue *rxq)
{
dma_addr_t phys_addr;
@@ -1799,7 +1807,7 @@ static int mvneta_rx_refill(struct mvneta_port *pp,
return -ENOMEM;
}
- mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data);
+ mvneta_rx_desc_fill(rx_desc, phys_addr, data, rxq);
return 0;
}
@@ -1861,7 +1869,12 @@ static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
for (i = 0; i < rxq->size; i++) {
struct mvneta_rx_desc *rx_desc = rxq->descs + i;
- void *data = (void *)rx_desc->buf_cookie;
+ void *data;
+
+ if (!pp->bm_priv)
+ data = rxq->buf_virt_addr[i];
+ else
+ data = (void *)(uintptr_t)rx_desc->buf_cookie;
dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
MVNETA_RX_BUF_SIZE(pp->pkt_size),
DMA_FROM_DEVICE);
@@ -1894,12 +1907,13 @@ static int mvneta_rx_swbm(struct mvneta_port *pp, int
rx_todo,
unsigned char *data;
dma_addr_t phys_addr;
u32 rx_status, frag_size;
- int rx_bytes, err;
+ int rx_bytes, err, index;
rx_done++;
rx_status = rx_desc->status;
rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
- data = (unsigned char *)rx_desc->buf_cookie;
+ index = rx_desc - rxq->descs;
+ data = (unsigned char *)rxq->buf_virt_addr[index];
phys_addr = rx_desc->buf_phys_addr;
if (!mvneta_rxq_desc_is_first_last(rx_status) ||
@@ -1938,7 +1952,7 @@ static int mvneta_rx_swbm(struct mvneta_port *pp, int
rx_todo,
}
/* Refill processing */
- err = mvneta_rx_refill(pp, rx_desc);
+ err = mvneta_rx_refill(pp, rx_desc, rxq);
if (err) {
netdev_err(dev, "Linux processing - Can't refill\n");
rxq->missed++;
@@ -2020,7 +2034,7 @@ static int mvneta_rx_hwbm(struct mvneta_port *pp, int
rx_todo,
rx_done++;
rx_status = rx_desc->status;
rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
- data = (unsigned char *)rx_desc->buf_cookie;
+ data = (u8 *)(uintptr_t)rx_desc->buf_cookie;
phys_addr = rx_desc->buf_phys_addr;
pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
bm_pool = >bm_priv->bm_pools[pool_id];
@@ -2708,6 +2722,56 @@ static int mvneta_poll(struct napi_struct *napi,
Re: [PATCH v3 net-next 2/6] net: mvneta: Use cacheable memory to store the rx buffer virtual address
Hi Marcin,
On mar., nov. 29 2016, Marcin Wojtas <m...@semihalf.com> wrote:
> Hi Gregory,
>
> Another remark below, sorry for noise.
>
> 2016-11-29 10:37 GMT+01:00 Gregory CLEMENT
> <gregory.clem...@free-electrons.com>:
>> Until now the virtual address of the received buffer were stored in the
>> cookie field of the rx descriptor. However, this field is 32-bits only
>> which prevents to use the driver on a 64-bits architecture.
>>
>> With this patch the virtual address is stored in an array not shared with
>> the hardware (no more need to use the DMA API). Thanks to this, it is
>> possible to use cache contrary to the access of the rx descriptor member.
>>
>> The change is done in the swbm path only because the hwbm uses the cookie
>> field, this also means that currently the hwbm is not usable in 64-bits.
>>
>> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
>> ---
>> drivers/net/ethernet/marvell/mvneta.c | 93
>> 1 file changed, 81 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/marvell/mvneta.c
>> b/drivers/net/ethernet/marvell/mvneta.c
>> index 1b84f746d748..32b142d0e44e 100644
>> --- a/drivers/net/ethernet/marvell/mvneta.c
>> +++ b/drivers/net/ethernet/marvell/mvneta.c
>> @@ -561,6 +561,9 @@ struct mvneta_rx_queue {
>> u32 pkts_coal;
>> u32 time_coal;
>>
>> + /* Virtual address of the RX buffer */
>> + void **buf_virt_addr;
>> +
>> /* Virtual address of the RX DMA descriptors array */
>> struct mvneta_rx_desc *descs;
>>
>> @@ -1573,10 +1576,14 @@ static void mvneta_tx_done_pkts_coal_set(struct
>> mvneta_port *pp,
>>
>> /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
>> static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
>> - u32 phys_addr, u32 cookie)
>> + u32 phys_addr, void *virt_addr,
>> + struct mvneta_rx_queue *rxq)
>> {
>> - rx_desc->buf_cookie = cookie;
>> + int i;
>> +
>> rx_desc->buf_phys_addr = phys_addr;
>> + i = rx_desc - rxq->descs;
>> + rxq->buf_virt_addr[i] = virt_addr;
>> }
>>
>> /* Decrement sent descriptors counter */
>> @@ -1781,7 +1788,8 @@ EXPORT_SYMBOL_GPL(mvneta_frag_free);
>>
>> /* Refill processing for SW buffer management */
>> static int mvneta_rx_refill(struct mvneta_port *pp,
>> - struct mvneta_rx_desc *rx_desc)
>> + struct mvneta_rx_desc *rx_desc,
>> + struct mvneta_rx_queue *rxq)
>>
>> {
>> dma_addr_t phys_addr;
>> @@ -1799,7 +1807,7 @@ static int mvneta_rx_refill(struct mvneta_port *pp,
>> return -ENOMEM;
>> }
>>
>> - mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data);
>> + mvneta_rx_desc_fill(rx_desc, phys_addr, data, rxq);
>> return 0;
>> }
>>
>> @@ -1861,7 +1869,12 @@ static void mvneta_rxq_drop_pkts(struct mvneta_port
>> *pp,
>>
>> for (i = 0; i < rxq->size; i++) {
>> struct mvneta_rx_desc *rx_desc = rxq->descs + i;
>> - void *data = (void *)rx_desc->buf_cookie;
>> + void *data;
>> +
>> + if (!pp->bm_priv)
>> + data = rxq->buf_virt_addr[i];
>> + else
>> + data = (void *)(uintptr_t)rx_desc->buf_cookie;
>
> Dropping packets for HWBM (in fact returning dropped buffers to the
> pool) is done a couple of lines above. This point will never be
indeed I changed the code at every place the buf_cookie was used and
missed the fact that for HWBM this code was never reached.
> reached with HWBM enabled (and it's also incorrect).
What is incorrect?
Gregory
>
> Best regards,
> Marcin
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
[PATCH v3 net-next 6/6] ARM64: dts: marvell: Add network support for Armada 3700
Add neta nodes for network support both in device tree for the SoC and
the board.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 23 +++-
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 23 +++-
2 files changed, 46 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index 1372e9a6aaa4..c8b82e4145de 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -81,3 +81,26 @@
{
status = "okay";
};
+
+ {
+ status = "okay";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+ {
+ phy-mode = "rgmii-id";
+ phy = <>;
+ status = "okay";
+};
+
+ {
+ phy-mode = "rgmii-id";
+ phy = <>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index e9bd58793464..3b8eb45bdc76 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -140,6 +140,29 @@
};
};
+ eth0: ethernet@3 {
+ compatible = "marvell,armada-3700-neta";
+ reg = <0x3 0x4000>;
+ interrupts = ;
+ clocks = <_periph_clk 8>;
+ status = "disabled";
+ };
+
+ mdio: mdio@32004 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,orion-mdio";
+ reg = <0x32004 0x4>;
+ };
+
+ eth1: ethernet@4 {
+ compatible = "marvell,armada-3700-neta";
+ reg = <0x4 0x4000>;
+ interrupts = ;
+ clocks = <_periph_clk 7>;
+ status = "disabled";
+ };
+
usb3: usb@58000 {
compatible = "marvell,armada3700-xhci",
"generic-xhci";
--
git-series 0.8.10
[PATCH v3 net-next 5/6] net: mvneta: Add network support for Armada 3700 SoC
From: Marcin Wojtas <m...@semihalf.com>
Armada 3700 is a new ARMv8 SoC from Marvell using same network controller
as older Armada 370/38x/XP. There are however some differences that
needed taking into account when adding support for it:
* open default MBUS window to 4GB of DRAM - Armada 3700 SoC's Mbus
configuration for network controller has to be done on two levels:
global and per-port. The first one is inherited from the
bootloader. The latter can be opened in a default way, leaving
arbitration to the bus controller. Hence filled mbus_dram_target_info
structure is not needed
* make per-CPU operation optional - Recent patches adding RSS and XPS
support for Armada 38x/XP enabled per-CPU operation of the controller
by default. Contrary to older SoC's Armada 3700 SoC's network
controller is not capable of per-CPU processing due to interrupt lines'
connectivity. This patch restores non-per-CPU operation, which is now
optional and depends on neta_armada3700 flag value in mvneta_port
structure. In order not to complicate the code, separate interrupt
subroutine is implemented.
For now, on the Armada 3700, RSS is disabled as the current
implementation depend on the per cpu interrupts.
[gregory.clem...@free-electrons.com: extract from a larger patch, replace
some ifdef and port to net-next for v4.10]
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt | 7 +-
drivers/net/ethernet/marvell/Kconfig | 7 +-
drivers/net/ethernet/marvell/mvneta.c | 287
+++-
3 files changed, 214 insertions(+), 87 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
index 73be8970815e..7aa840c8768d 100644
--- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
+++ b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
@@ -1,7 +1,10 @@
-* Marvell Armada 370 / Armada XP Ethernet Controller (NETA)
+* Marvell Armada 370 / Armada XP / Armada 3700 Ethernet Controller (NETA)
Required properties:
-- compatible: "marvell,armada-370-neta" or "marvell,armada-xp-neta".
+- compatible: could be one of the followings
+ "marvell,armada-370-neta"
+ "marvell,armada-xp-neta"
+ "marvell,armada-3700-neta"
- reg: address and length of the register set for the device.
- interrupts: interrupt for the device
- phy: See ethernet.txt file in the same directory.
diff --git a/drivers/net/ethernet/marvell/Kconfig
b/drivers/net/ethernet/marvell/Kconfig
index 2ccea9dd9248..3b8f11fe5e13 100644
--- a/drivers/net/ethernet/marvell/Kconfig
+++ b/drivers/net/ethernet/marvell/Kconfig
@@ -56,14 +56,15 @@ config MVNETA_BM_ENABLE
buffer management.
config MVNETA
- tristate "Marvell Armada 370/38x/XP network interface support"
- depends on PLAT_ORION || COMPILE_TEST
+ tristate "Marvell Armada 370/38x/XP/37xx network interface support"
+ depends on ARCH_MVEBU || COMPILE_TEST
depends on HAS_DMA
select MVMDIO
select FIXED_PHY
---help---
This driver supports the network interface units in the
- Marvell ARMADA XP, ARMADA 370 and ARMADA 38x SoC family.
+ Marvell ARMADA XP, ARMADA 370, ARMADA 38x and
+ ARMADA 37xx SoC family.
Note that this driver is distinct from the mv643xx_eth
driver, which should be used for the older Marvell SoCs
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index a8bd0d83028f..99cee88d5052 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -397,6 +397,9 @@ struct mvneta_port {
spinlock_t lock;
bool is_stopped;
+ u32 cause_rx_tx;
+ struct napi_struct napi;
+
/* Core clock */
struct clk *clk;
/* AXI clock */
@@ -422,6 +425,9 @@ struct mvneta_port {
u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
+
+ /* Flags for special SoC configurations */
+ bool neta_armada3700;
u16 rx_offset_correction;
};
@@ -965,14 +971,9 @@ static int mvneta_mbus_io_win_set(struct mvneta_port *pp,
u32 base, u32 wsize,
return 0;
}
-/* Assign and initialize pools for port. In case of fail
- * buffer manager will remain disabled for current port.
- */
-static int mvneta_bm_port_init(struct platform_device *pdev,
- struct mvneta_port *pp)
+static int mvneta_bm_port_mbus_init(struct mvneta_port *pp)
{
- struct device_node *dn = pdev->dev.of_node;
- u32
[PATCH v3 net-next 3/6] net: mvneta: Convert to be 64 bits compatible
From: Marcin Wojtas <m...@semihalf.com>
Prepare the mvneta driver in order to be usable on the 64 bits platform
such as the Armada 3700.
[gregory.clem...@free-electrons.com]: this patch was extract from a larger
one to ease review and maintenance.
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 32b142d0e44e..a8bd0d83028f 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -296,6 +296,12 @@
/* descriptor aligned size */
#define MVNETA_DESC_ALIGNED_SIZE 32
+/* Number of bytes to be taken into account by HW when putting incoming data
+ * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet
+ * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers.
+ */
+#define MVNETA_RX_PKT_OFFSET_CORRECTION64
+
#define MVNETA_RX_PKT_SIZE(mtu) \
ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
ETH_HLEN + ETH_FCS_LEN,\
@@ -416,6 +422,7 @@ struct mvneta_port {
u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
+ u16 rx_offset_correction;
};
/* The mvneta_tx_desc and mvneta_rx_desc structures describe the
@@ -1807,6 +1814,7 @@ static int mvneta_rx_refill(struct mvneta_port *pp,
return -ENOMEM;
}
+ phys_addr += pp->rx_offset_correction;
mvneta_rx_desc_fill(rx_desc, phys_addr, data, rxq);
return 0;
}
@@ -2742,6 +2750,7 @@ static int mvneta_rx_hwbm_refill(struct mvneta_port *pp,
return -ENOMEM;
}
+ phys_addr += pp->rx_offset_correction;
rx_desc->buf_phys_addr = phys_addr;
rx_desc->buf_cookie = (uintptr_t)data;
@@ -2837,7 +2846,7 @@ static int mvneta_rxq_init(struct mvneta_port *pp,
mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
/* Set Offset */
- mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD);
+ mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD - pp->rx_offset_correction);
/* Set coalescing pkts and time */
mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
@@ -4088,6 +4097,13 @@ static int mvneta_probe(struct platform_device *pdev)
pp->rxq_def = rxq_def;
+ /* Set RX packet offset correction for platforms, whose
+* NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit
+* platforms and 0B for 32-bit ones.
+*/
+ pp->rx_offset_correction =
+ max(0, NET_SKB_PAD - MVNETA_RX_PKT_OFFSET_CORRECTION);
+
pp->indir[0] = rxq_def;
pp->clk = devm_clk_get(>dev, "core");
--
git-series 0.8.10
[PATCH v3 net-next 1/6] net: mvneta: Optimize rx path for small frame
For small frame reuse the phys_addr variable instead of accessing the uncacheable value in the rx descriptor. Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> --- drivers/net/ethernet/marvell/mvneta.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c index 87274d4ab102..1b84f746d748 100644 --- a/drivers/net/ethernet/marvell/mvneta.c +++ b/drivers/net/ethernet/marvell/mvneta.c @@ -1918,7 +1918,7 @@ static int mvneta_rx_swbm(struct mvneta_port *pp, int rx_todo, goto err_drop_frame; dma_sync_single_range_for_cpu(dev->dev.parent, - rx_desc->buf_phys_addr, + phys_addr, MVNETA_MH_SIZE + NET_SKB_PAD, rx_bytes, DMA_FROM_DEVICE); -- git-series 0.8.10
[PATCH v3 net-next 4/6] net: mvneta: Only disable mvneta_bm for 64-bits
Actually only the mvneta_bm support is not 64-bits compatible. The mvneta code itself can run on 64-bits architecture. Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> --- drivers/net/ethernet/marvell/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/Kconfig b/drivers/net/ethernet/marvell/Kconfig index 66fd9dbb2ca7..2ccea9dd9248 100644 --- a/drivers/net/ethernet/marvell/Kconfig +++ b/drivers/net/ethernet/marvell/Kconfig @@ -44,6 +44,7 @@ config MVMDIO config MVNETA_BM_ENABLE tristate "Marvell Armada 38x/XP network interface BM support" depends on MVNETA + depends on !64BIT ---help--- This driver supports auxiliary block of the network interface units in the Marvell ARMADA XP and ARMADA 38x SoC @@ -58,7 +59,6 @@ config MVNETA tristate "Marvell Armada 370/38x/XP network interface support" depends on PLAT_ORION || COMPILE_TEST depends on HAS_DMA - depends on !64BIT select MVMDIO select FIXED_PHY ---help--- @@ -71,6 +71,7 @@ config MVNETA config MVNETA_BM tristate + depends on !64BIT default y if MVNETA=y && MVNETA_BM_ENABLE!=n default MVNETA_BM_ENABLE select HWBM -- git-series 0.8.10
Re: [PATCH v3 net-next 0/6] Support Armada 37xx SoC (ARMv8 64-bits) in mvneta driver
Hi, On mar., nov. 29 2016, Gregory CLEMENT <gregory.clem...@free-electrons.com> wrote: > Hi, > > The Armada 37xx is a new ARMv8 SoC from Marvell using same network > controller as the older Armada 370/38x/XP SoCs. This series adapts the > driver in order to be able to use it on this new SoC. The main changes > are: > > - 64-bits support: the first patches allow using the driver on a 64-bit > architecture. > > - MBUS support: the mbus configuration is different on Armada 37xx > from the older SoCs. > > - per cpu interrupt: Armada 37xx do not support per cpu interrupt for > the NETA IP, the non-per-CPU behavior was added back. > > The first item is solved by patches 1 to 3. > The 2 last items are solved by patch 4. > In patch 5 the dt support is added. > > Beside Armada 37xx, the series have been tested on Armada XP and > Armada 38x (with Hardware Buffer Management and with Software Buffer > Managment). > > Thanks, > I forgot to commit my cover with git series, so it was the old one. It should have been the following one: Hi, The Armada 37xx is a new ARMv8 SoC from Marvell using same network controller as the older Armada 370/38x/XP SoCs. This series adapts the driver in order to be able to use it on this new SoC. The main changes are: - 64-bits support: the first patches allow using the driver on a 64-bit architecture. - MBUS support: the mbus configuration is different on Armada 37xx from the older SoCs. - per cpu interrupt: Armada 37xx do not support per cpu interrupt for the NETA IP, the non-per-CPU behavior was added back. The first patch is an optimization in the rx path in swbm mode. The first item is solved by patches 2 to 3. The 2 last items are solved by patch 5. In patch 6 the dt support is added. Beside Armada 37xx, this new series have been again tested on Armada XP and Armada 38x (with Hardware Buffer Management and with Software Buffer Management). This is the 3th version of the series: - 1st version: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/469588.html - 2nd version: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/470476.html Changelog: v2 -> v3: - Adding patch 1 "Optimize rx path for small frame" - Fix the kbuild error by moving the "phys_addr += pp->rx_offset_correction;" line from patch 2 to patch 3 where rx_offset_correction is introduced. - Move the memory allocation of the buf_virt_addr of the rxq to be called by the probe function in order to avoid a memory leak. > Gregory > > Gregory CLEMENT (4): > net: mvneta: Optimize rx path for small frame > net: mvneta: Use cacheable memory to store the rx buffer virtual address > net: mvneta: Only disable mvneta_bm for 64-bits > ARM64: dts: marvell: Add network support for Armada 3700 > > Marcin Wojtas (2): > net: mvneta: Convert to be 64 bits compatible > net: mvneta: Add network support for Armada 3700 SoC > > Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt | 7 +- > arch/arm64/boot/dts/marvell/armada-3720-db.dts| 23 - > arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 23 - > drivers/net/ethernet/marvell/Kconfig | 10 +- > drivers/net/ethernet/marvell/mvneta.c | 400 > ++---------- > 5 files changed, 361 insertions(+), 102 deletions(-) > > base-commit: 436accebb53021ef7c63535f60bda410aa87c136 > -- > git-series 0.8.10 -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Re: [PATCH v3 net-next 2/6] net: mvneta: Use cacheable memory to store the rx buffer virtual address
Hi Marcin,
On mar., nov. 29 2016, Marcin Wojtas <m...@semihalf.com> wrote:
> Hi Gregory,
>
> Apparently HWBM had a mistake in implementation, please see below.
>
> 2016-11-29 10:37 GMT+01:00 Gregory CLEMENT
> <gregory.clem...@free-electrons.com>:
>> Until now the virtual address of the received buffer were stored in the
>> cookie field of the rx descriptor. However, this field is 32-bits only
>> which prevents to use the driver on a 64-bits architecture.
>>
>> With this patch the virtual address is stored in an array not shared with
>> the hardware (no more need to use the DMA API). Thanks to this, it is
>> possible to use cache contrary to the access of the rx descriptor member.
>>
>> The change is done in the swbm path only because the hwbm uses the cookie
>> field, this also means that currently the hwbm is not usable in 64-bits.
>>
>> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
>> ---
>> drivers/net/ethernet/marvell/mvneta.c | 93
>> 1 file changed, 81 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/marvell/mvneta.c
>> b/drivers/net/ethernet/marvell/mvneta.c
>> index 1b84f746d748..32b142d0e44e 100644
>> --- a/drivers/net/ethernet/marvell/mvneta.c
>> +++ b/drivers/net/ethernet/marvell/mvneta.c
>> @@ -561,6 +561,9 @@ struct mvneta_rx_queue {
>> u32 pkts_coal;
>> u32 time_coal;
>>
>> + /* Virtual address of the RX buffer */
>> + void **buf_virt_addr;
>> +
>> /* Virtual address of the RX DMA descriptors array */
>> struct mvneta_rx_desc *descs;
>>
>> @@ -1573,10 +1576,14 @@ static void mvneta_tx_done_pkts_coal_set(struct
>> mvneta_port *pp,
>>
>> /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
>> static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
>> - u32 phys_addr, u32 cookie)
>> + u32 phys_addr, void *virt_addr,
>> + struct mvneta_rx_queue *rxq)
>> {
>> - rx_desc->buf_cookie = cookie;
>> + int i;
>> +
>> rx_desc->buf_phys_addr = phys_addr;
>> + i = rx_desc - rxq->descs;
>> + rxq->buf_virt_addr[i] = virt_addr;
>> }
>>
>> /* Decrement sent descriptors counter */
>> @@ -1781,7 +1788,8 @@ EXPORT_SYMBOL_GPL(mvneta_frag_free);
>>
>> /* Refill processing for SW buffer management */
>> static int mvneta_rx_refill(struct mvneta_port *pp,
>> - struct mvneta_rx_desc *rx_desc)
>> + struct mvneta_rx_desc *rx_desc,
>> + struct mvneta_rx_queue *rxq)
>>
>> {
>> dma_addr_t phys_addr;
>> @@ -1799,7 +1807,7 @@ static int mvneta_rx_refill(struct mvneta_port *pp,
>> return -ENOMEM;
>> }
>>
>> - mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data);
>> + mvneta_rx_desc_fill(rx_desc, phys_addr, data, rxq);
>> return 0;
>> }
>>
>> @@ -1861,7 +1869,12 @@ static void mvneta_rxq_drop_pkts(struct mvneta_port
>> *pp,
>>
>> for (i = 0; i < rxq->size; i++) {
>> struct mvneta_rx_desc *rx_desc = rxq->descs + i;
>> - void *data = (void *)rx_desc->buf_cookie;
>> + void *data;
>> +
>> + if (!pp->bm_priv)
>> + data = rxq->buf_virt_addr[i];
>> + else
>> + data = (void *)(uintptr_t)rx_desc->buf_cookie;
>>
>> dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
>> MVNETA_RX_BUF_SIZE(pp->pkt_size),
>> DMA_FROM_DEVICE);
>> @@ -1894,12 +1907,13 @@ static int mvneta_rx_swbm(struct mvneta_port *pp,
>> int rx_todo,
>> unsigned char *data;
>> dma_addr_t phys_addr;
>> u32 rx_status, frag_size;
>> - int rx_bytes, err;
>> + int rx_bytes, err, index;
>>
>> rx_done++;
>> rx_status = rx_desc->status;
>> rx_bytes = rx_desc->data_size - (ETH_FCS_LEN +
>> MVNETA_MH_SIZE);
>> - data = (unsigned char *)rx_desc->buf_cookie;
>> + index = rx_desc - rxq->descs;
>> + data = (unsigned char *)rxq->buf_v
Re: [PATCH 0/4] ARM64: dts: marvell: fix license text
Hi Alexandre, On mer., déc. 14 2016, Alexandre Belloni <alexandre.bell...@free-electrons.com> wrote: > The dual GPLv2/X11 license the text that is used > is missing a few characters. As for the other series could you squash all this series in a single patch and fix the commit log (s/test/text/) ? Thanks, Gregory > > > Alexandre Belloni (4): > ARM64: dts: marvell/armada-371x: Correct license text > ARM64: dts: marvell/armada-3720-db: Correct license text > ARM64: dts: marvell/armada-372x: Correct license text > ARM64: dts: marvell/armada-37xx: Correct license text > > arch/arm64/boot/dts/marvell/armada-371x.dtsi | 10 +- > arch/arm64/boot/dts/marvell/armada-3720-db.dts | 10 +- > arch/arm64/boot/dts/marvell/armada-372x.dtsi | 10 +- > arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 10 +- > 4 files changed, 20 insertions(+), 20 deletions(-) > > -- > 2.10.2 > -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
Re: [PATCH] soc: dove: constify reset_control_ops structures
Hi Russell King,
On ven., janv. 13 2017, Russell King - ARM Linux <li...@armlinux.org.uk> wrote:
> On Fri, Jan 13, 2017 at 05:36:42PM +0100, Gregory CLEMENT wrote:
>> Hi Sebastian,
>>
>> On lun., janv. 09 2017, Bhumika Goyal <bhumi...@gmail.com> wrote:
>>
>> > Declare reset_control_ops as const as they are only stored in the ops
>> > field of a reset_controller_dev structure. This field is of type const
>> > struct reset_control_ops *, so reset_control_ops structures having this
>> > property can be declared as const.
>> > Done using Coccinelle:
>> >
>> > @r1 disable optional_qualifier@
>> > identifier i;
>> > position p;
>> > @@
>> > static struct reset_control_ops i@p={...};
>> >
>> > @ok1@
>> > identifier r1.i;
>> > position p;
>> > struct reset_controller_dev x;
>> > @@
>> > x.ops=@p;
>> >
>> > @bad@
>> > position p!={r1.p,ok1.p};
>> > identifier r1.i;
>> > @@
>> > i@p
>> >
>> > @depends on !bad disable optional_qualifier@
>> > identifier r1.i;
>> > @@
>> > +const
>> > struct reset_control_ops i;
>> >
>> > File size before: drivers/soc/dove/pmu.o
>> >text data bss dec hex filename
>> >2447112 162575 a0f drivers/soc/dove/pmu.o
>> >
>> > File size after: drivers/soc/dove/pmu.o
>> >text data bss dec hex filename
>> >2479 80 162575 a0f drivers/soc/dove/pmu.o
>> >
>>
>> If you agree with this patch I will apply it on mvebu/soc.
>
> You really ought to be asking me...
Sorry when I saw SoC and Dove I though to Sebastian. And I ma sure he
would have redirect me to you :)
>
> Acked-by: Russell King <rmk+ker...@armlinux.org.uk>
Applied on mvebu/soc
Thanks,
Gregory
>
> --
> RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
> FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
> according to speedtest.net.
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH] soc: dove: constify reset_control_ops structures
Hi Sebastian,
On lun., janv. 09 2017, Bhumika Goyal <bhumi...@gmail.com> wrote:
> Declare reset_control_ops as const as they are only stored in the ops
> field of a reset_controller_dev structure. This field is of type const
> struct reset_control_ops *, so reset_control_ops structures having this
> property can be declared as const.
> Done using Coccinelle:
>
> @r1 disable optional_qualifier@
> identifier i;
> position p;
> @@
> static struct reset_control_ops i@p={...};
>
> @ok1@
> identifier r1.i;
> position p;
> struct reset_controller_dev x;
> @@
> x.ops=@p;
>
> @bad@
> position p!={r1.p,ok1.p};
> identifier r1.i;
> @@
> i@p
>
> @depends on !bad disable optional_qualifier@
> identifier r1.i;
> @@
> +const
> struct reset_control_ops i;
>
> File size before: drivers/soc/dove/pmu.o
>text data bss dec hex filename
>2447 112 162575 a0f drivers/soc/dove/pmu.o
>
> File size after: drivers/soc/dove/pmu.o
>text data bss dec hex filename
>247980 162575 a0f drivers/soc/dove/pmu.o
>
If you agree with this patch I will apply it on mvebu/soc.
Thanks,
Gregory
> Signed-off-by: Bhumika Goyal <bhumi...@gmail.com>
> ---
> drivers/soc/dove/pmu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/soc/dove/pmu.c b/drivers/soc/dove/pmu.c
> index 039374e..95d77ec 100644
> --- a/drivers/soc/dove/pmu.c
> +++ b/drivers/soc/dove/pmu.c
> @@ -87,7 +87,7 @@ static int pmu_reset_deassert(struct reset_controller_dev
> *rc, unsigned long id)
> return 0;
> }
>
> -static struct reset_control_ops pmu_reset_ops = {
> +static const struct reset_control_ops pmu_reset_ops = {
> .reset = pmu_reset_reset,
> .assert = pmu_reset_assert,
> .deassert = pmu_reset_deassert,
> --
> 1.9.1
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Re: [PATCH] ARM: mv78xx0: fix possible PCI buffer overflow
Hi Arnd,
On mer., janv. 11 2017, Arnd Bergmann <a...@arndb.de> wrote:
> gcc-7.0 reports a potential array overflow:
>
> arch/arm/mach-mv78xx0/pcie.c: In function 'mv78xx0_pcie_preinit':
> arch/arm/mach-mv78xx0/pcie.c:81:4: error: output may be truncated before the
> last format character [-Werror=format-truncation=]
>
> I haven't checked if this can actually happen, but making the
> array one 32-bit word longer addresses the warning and makes
> it completely safe.
>
> Signed-off-by: Arnd Bergmann <a...@arndb.de>
Applied on mvebu/soc
Thanks,
Gregory
> ---
> arch/arm/mach-mv78xx0/pcie.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
> index 13a7d72ee0c4..81ff4327a962 100644
> --- a/arch/arm/mach-mv78xx0/pcie.c
> +++ b/arch/arm/mach-mv78xx0/pcie.c
> @@ -29,7 +29,7 @@ struct pcie_port {
> u8 root_bus_nr;
> void __iomem*base;
> spinlock_t conf_lock;
> - charmem_space_name[16];
> + charmem_space_name[20];
> struct resource res;
> };
>
> --
> 2.9.0
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
[PATCH v5 06/12] mmc: sdhci-xenon: Add Marvell Xenon SDHC core functionality
From: Hu Ziji <huz...@marvell.com>
Add Xenon eMMC/SD/SDIO host controller core functionality.
Add Xenon specific intialization process.
Add Xenon specific mmc_host_ops APIs.
Add Xenon specific register definitions.
Add CONFIG_MMC_SDHCI_XENON support in drivers/mmc/host/Kconfig.
Marvell Xenon SDHC conforms to SD Physical Layer Specification
Version 3.01 and is designed according to the guidelines provided
in the SD Host Controller Standard Specification Version 3.00.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Tested-by: Russell King <rmk+ker...@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/mmc/host/Kconfig | 9 +-
drivers/mmc/host/Makefile | 3 +-
drivers/mmc/host/sdhci-xenon.c | 631 ++-
drivers/mmc/host/sdhci-xenon.h | 70 -
4 files changed, 713 insertions(+)
create mode 100644 drivers/mmc/host/sdhci-xenon.c
create mode 100644 drivers/mmc/host/sdhci-xenon.h
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 2eb97014dc3f..8d2d08de14a0 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -819,3 +819,12 @@ config MMC_SDHCI_BRCMSTB
Broadcom STB SoCs.
If unsure, say Y.
+
+config MMC_SDHCI_XENON
+ tristate "Marvell Xenon eMMC/SD/SDIO SDHCI driver"
+ depends on MMC_SDHCI && MMC_SDHCI_PLTFM
+ help
+ This selects Marvell Xenon eMMC/SD/SDIO SDHCI.
+ If you have a machine with integrated Marvell Xenon SDHC IP,
+ say Y or M here.
+ If unsure, say N.
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index ccc9c4cba154..b0a2ab4b256e 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -82,3 +82,6 @@ obj-$(CONFIG_MMC_SDHCI_BRCMSTB) +=
sdhci-brcmstb.o
ifeq ($(CONFIG_CB710_DEBUG),y)
CFLAGS-cb710-mmc+= -DDEBUG
endif
+
+obj-$(CONFIG_MMC_SDHCI_XENON) += sdhci-xenon-driver.o
+sdhci-xenon-driver-y += sdhci-xenon.o
diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c
new file mode 100644
index ..0e0c60892f72
--- /dev/null
+++ b/drivers/mmc/host/sdhci-xenon.c
@@ -0,0 +1,631 @@
+/*
+ * Driver for Marvell Xenon SDHC as a platform device
+ *
+ * Copyright (C) 2016 Marvell, All Rights Reserved.
+ *
+ * Author: Hu Ziji <huz...@marvell.com>
+ * Date: 2016-8-24
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * Inspired by Jisheng Zhang <jszh...@marvell.com>
+ * Special thanks to Video BG4 project team.
+ */
+
+#include
+#include
+#include
+
+#include "sdhci-pltfm.h"
+#include "sdhci-xenon.h"
+
+static int enable_xenon_internal_clk(struct sdhci_host *host)
+{
+ u32 reg;
+ u8 timeout;
+
+ reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
+ reg |= SDHCI_CLOCK_INT_EN;
+ sdhci_writel(host, reg, SDHCI_CLOCK_CONTROL);
+ /* Wait max 20 ms */
+ timeout = 20;
+ while (!((reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
+ & SDHCI_CLOCK_INT_STABLE)) {
+ if (timeout == 0) {
+ pr_err("%s: Internal clock never stabilised.\n",
+ mmc_hostname(host->mmc));
+ return -ETIMEDOUT;
+ }
+ timeout--;
+ mdelay(1);
+ }
+
+ return 0;
+}
+
+/* Set SDCLK-off-while-idle */
+static void xenon_set_sdclk_off_idle(struct sdhci_host *host,
+unsigned char sdhc_id, bool enable)
+{
+ u32 reg;
+ u32 mask;
+
+ reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
+ /* Get the bit shift basing on the SDHC index */
+ mask = (0x1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sdhc_id));
+ if (enable)
+ reg |= mask;
+ else
+ reg &= ~mask;
+
+ sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
+}
+
+/* Enable/Disable the Auto Clock Gating function */
+static void xenon_set_acg(struct sdhci_host *host, bool enable)
+{
+ u32 reg;
+
+ reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
+ if (enable)
+ reg &= ~XENON_AUTO_CLKGATE_DISABLE_MASK;
+ else
+ reg |= XENON_AUTO_CLKGATE_DISABLE_MASK;
+ sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
+}
+
+/* Enable this SDHC */
+static void xenon_enable_sdhc(struct sdhci_host *host,
+ unsigned char sdhc_id)
+{
+ u32 reg;
+
+ reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
+ reg |= (BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT);
+ sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
+
+ /*
+* Manually set the flag which all the card types require,
+
[PATCH v5 09/12] MAINTAINERS: add entry for Marvell Xenon MMC Host Controller drivers
From: Hu Ziji <huz...@marvell.com> Add maintainer entry for Marvell Xenon eMMC/SD/SDIO Host Controller drivers. Signed-off-by: Hu Ziji <huz...@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> --- MAINTAINERS | 7 +++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index cfff2c9e3d94..f4fea77165d5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7757,6 +7757,13 @@ M: Nicolas Pitre <n...@fluxnic.net> S: Odd Fixes F: drivers/mmc/host/mvsdio.* +MARVELL XENON MMC/SD/SDIO HOST CONTROLLER DRIVER +M: Ziji Hu <huz...@marvell.com> +L: linux-...@vger.kernel.org +S: Supported +F: drivers/mmc/host/sdhci-xenon* +F: Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt + MATROX FRAMEBUFFER DRIVER L: linux-fb...@vger.kernel.org S: Orphan -- git-series 0.9.1
[PATCH v5 04/12] mmc: sdhci: Export sdhci_enable_sdio_irq() from sdhci.c
From: Hu Ziji <huz...@marvell.com>
Export sdhci_enable_sdio_irq() from sdhci.c.
Thus vendor SDHC driver can implement its specific SDIO irq
control.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/mmc/host/sdhci.c | 3 ++-
drivers/mmc/host/sdhci.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index d2338dc362f4..9a4fda81ff81 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1824,7 +1824,7 @@ static void sdhci_enable_sdio_irq_nolock(struct
sdhci_host *host, int enable)
}
}
-static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
+void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
{
struct sdhci_host *host = mmc_priv(mmc);
unsigned long flags;
@@ -1838,6 +1838,7 @@ static void sdhci_enable_sdio_irq(struct mmc_host *mmc,
int enable)
sdhci_enable_sdio_irq_nolock(host, enable);
spin_unlock_irqrestore(>lock, flags);
}
+EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
struct mmc_ios *ios)
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index e4a07543a12b..609783364941 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -694,6 +694,7 @@ int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
struct mmc_ios *ios);
+void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable);
#ifdef CONFIG_PM
extern int sdhci_suspend_host(struct sdhci_host *host);
--
git-series 0.9.1
[PATCH v5 03/12] mmc: sdhci: Export sdhci_start_signal_voltage_switch() in sdhci.c
From: Hu Ziji <huz...@marvell.com>
Export sdhci_start_signal_voltage_switch() from sdhci.c.
Thus vendor sdhci driver can implement its own signal voltage
switch routine.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/mmc/host/sdhci.c | 5 +++--
drivers/mmc/host/sdhci.h | 2 ++
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 0e9ed0fadff9..d2338dc362f4 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1839,8 +1839,8 @@ static void sdhci_enable_sdio_irq(struct mmc_host *mmc,
int enable)
spin_unlock_irqrestore(>lock, flags);
}
-static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
-struct mmc_ios *ios)
+int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
+ struct mmc_ios *ios)
{
struct sdhci_host *host = mmc_priv(mmc);
u16 ctrl;
@@ -1932,6 +1932,7 @@ static int sdhci_start_signal_voltage_switch(struct
mmc_host *mmc,
return 0;
}
}
+EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
static int sdhci_card_busy(struct mmc_host *mmc)
{
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 3563c0c384ca..e4a07543a12b 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -692,6 +692,8 @@ void sdhci_reset(struct sdhci_host *host, u8 mask);
void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
+int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
+ struct mmc_ios *ios);
#ifdef CONFIG_PM
extern int sdhci_suspend_host(struct sdhci_host *host);
--
git-series 0.9.1
[PATCH v5 02/12] mmc: sdhci: Export sdhci_set_ios() from sdhci.c
From: Hu Ziji <huz...@marvell.com>
Export sdhci_set_ios() in sdhci.c.
Thus vendor sdhci driver can implement its own set_ios() routine.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/mmc/host/sdhci.c | 3 ++-
drivers/mmc/host/sdhci.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 23909804ffb8..0e9ed0fadff9 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1570,7 +1570,7 @@ void sdhci_set_uhs_signaling(struct sdhci_host *host,
unsigned timing)
}
EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
-static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
struct sdhci_host *host = mmc_priv(mmc);
unsigned long flags;
@@ -1730,6 +1730,7 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct
mmc_ios *ios)
mmiowb();
spin_unlock_irqrestore(>lock, flags);
}
+EXPORT_SYMBOL_GPL(sdhci_set_ios);
static int sdhci_get_cd(struct mmc_host *mmc)
{
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 0b66f210ae82..3563c0c384ca 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -691,6 +691,7 @@ void sdhci_set_bus_width(struct sdhci_host *host, int
width);
void sdhci_reset(struct sdhci_host *host, u8 mask);
void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
+void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
#ifdef CONFIG_PM
extern int sdhci_suspend_host(struct sdhci_host *host);
--
git-series 0.9.1
[PATCH v5 00/12] mmc: Add support to Marvell Xenon SD Host Controller
Hello, This the fifth version of the series adding support for the SDHCI Xenon controller. It can be currently found on the Armada 37xx and the Armada 7K/8K but will be also used in more Marvell SoC (and not only the mvebu ones actually). v4->v5: - Remove the patch to export sdhci_execute_tuning(). It is already exported in v4.10. - Introduce a patch adding a missing clock for the sdhci controller present on the CP master for A7K/A8K. There is no build dependency but obviously this patch is need to use the sdhci controller present on the CP part. - Adjust Xenon return setup, to avoid being overwritten by sdhci_add_host(). - Change Xenon register definition prefix to "XENON_". - Fix typos in Xenon driver and dt-binding docs. - Change compatible string "marvell,armada-7000-sdhci" to "marvell,armada-8k-sdhci". Actually the Armada 7K SoCs are a subset of the Armada 8K SoCs. Moreover, the use of the '000' is not consistent with all the other compatible string already used for the Armada 7K/8K family. - Added the Tested-by from Russell King on an Armada 8K based board. v3 -> v4: For this version a few change have been done: - fixes 2 bug reported by kbuild-bot - remove extra of_node_put() - convert 0 in false for function returning boolean - add a device tree node for the sdhci controller present on the CP master for A7K/A8K. It also led to rename the sdhci0 node on AP to ap_sdhci0 to make a distinction with the one present on CP master. v2 -> v3 I think that now most (if not all) the remarks had been taking into account since the second version. According to Ziji Hu, here are the following changes: " Changes in V3: Adjust and improve Xenon DT bindings. Move some caps setting from driver into DT. Use mmc-card sub-node to represent eMMC type. Remove PHY Sampling Fixed Delay Line scan in lower speed mode. Improve Xenon probe and ->init_card() functions. Export sdhci_enable_sdio_irq() and implement own SDIO IRQ control. Split PHY patch into two smaller patches. Temporarily remove AXI clock before its implementation is improved." Besides this changes I also - Removed the sdhci-xenon-phy.h and moved its content in the shc-xenon-phy.c file. - Fixed the tuning-count usage - Managed the error case for clk_prepare_enable For the record the change from v1 was: " Changes in V2: rebase on v4.9-rc2. Re-write Xenon bindings. Ajust Xenon DT property naming. Add a new DT property to indicate eMMC card type, instead of using variable card_candidate. Clear quirks SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 in Xenon platform data Add support to HS400 retuning." Thanks, Gregory Gregory CLEMENT (3): arm64: dts: marvell: add eMMC support for Armada 37xx arm64: dts: marvell: add sdhci support for Armada 7K/8K arm64: configs: enable SDHCI driver for Xenon Hu Ziji (8): mmc: sdhci: Export sdhci_set_ios() from sdhci.c mmc: sdhci: Export sdhci_start_signal_voltage_switch() in sdhci.c mmc: sdhci: Export sdhci_enable_sdio_irq() from sdhci.c dt: bindings: Add bindings for Marvell Xenon SD Host Controller mmc: sdhci-xenon: Add Marvell Xenon SDHC core functionality mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC. mmc: sdhci-xenon: Add SoC PHY PAD voltage control MAINTAINERS: add entry for Marvell Xenon MMC Host Controller drivers Konstantin Porotchkin (1): clk: apn806: Add eMMC clock to system controller driver Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt | 197 ++- MAINTAINERS | 7 +- arch/arm64/boot/dts/marvell/armada-3720-db.dts| 16 +- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 11 +- arch/arm64/boot/dts/marvell/armada-7040-db.dts| 14 +- arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 13 +- arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 11 +- arch/arm64/configs/defconfig | 1 +- drivers/clk/mvebu/ap806-system-controller.c | 15 +- drivers/mmc/host/Kconfig | 9 +- drivers/mmc/host/Makefile | 3 +- drivers/mmc/host/sdhci-xenon-phy.c| 904 +++- drivers/mmc/host/sdhci-xenon.c| 634 +- drivers/mmc/host/sdhci-xenon.h| 109 +- drivers/mmc/host/sdhci.c | 11 +- drivers/mmc/host/sdhci.h | 4 +- 16 files changed, 1953 insertions(+), 6 deletions(-) create mode 100644 Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt create mode 100644 drivers/mmc/host/sdhci-xenon-phy.c create mode 100644 drivers/mmc/host/sdhci-xenon.c create mode 100644 drivers/mmc/host/sdhci-xenon.h base-commit: 0c744ea4f77d72b3dcebb7a8f2684633ec79be88 -- git-series 0.9.1
[PATCH v5 07/12] mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC.
From: Hu Ziji <huz...@marvell.com> Marvell Xenon eMMC/SD/SDIO Host Controller contains PHY. Multiple types of PHYs are supported. Add support to multiple types of PHYs init and configuration. Add register definitions of PHYs. Xenon PHY cannot fit in kernel common PHY framework. Xenon SDHC PHY register is a part of Xenon SDHC register set. Besides, MMC initialization has to call several PHY functions to complete timing setting. Those PHY setting functions have to access SDHC registers and know current MMC setting, such as bus width, clock frequency and speed mode. As a result, implement Xenon PHY in MMC host directory. Signed-off-by: Hu Ziji <huz...@marvell.com> Tested-by: Russell King <rmk+ker...@armlinux.org.uk> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> --- drivers/mmc/host/Makefile | 2 +- drivers/mmc/host/sdhci-xenon-phy.c | 790 ++- drivers/mmc/host/sdhci-xenon.c | 3 +- drivers/mmc/host/sdhci-xenon.h | 37 +- 4 files changed, 830 insertions(+), 2 deletions(-) create mode 100644 drivers/mmc/host/sdhci-xenon-phy.c diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index b0a2ab4b256e..893b48db5513 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -84,4 +84,4 @@ ifeq ($(CONFIG_CB710_DEBUG),y) endif obj-$(CONFIG_MMC_SDHCI_XENON) += sdhci-xenon-driver.o -sdhci-xenon-driver-y += sdhci-xenon.o +sdhci-xenon-driver-y += sdhci-xenon.o sdhci-xenon-phy.o diff --git a/drivers/mmc/host/sdhci-xenon-phy.c b/drivers/mmc/host/sdhci-xenon-phy.c new file mode 100644 index ..f410712d24ea --- /dev/null +++ b/drivers/mmc/host/sdhci-xenon-phy.c @@ -0,0 +1,790 @@ +/* + * PHY support for Xenon SDHC + * + * Copyright (C) 2016 Marvell, All Rights Reserved. + * + * Author: Hu Ziji <huz...@marvell.com> + * Date: 2016-8-24 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + */ + +#include +#include +#include + +#include "sdhci-pltfm.h" +#include "sdhci-xenon.h" + +/* Register base for eMMC PHY 5.0 Version */ +#define XENON_EMMC_5_0_PHY_REG_BASE0x0160 +/* Register base for eMMC PHY 5.1 Version */ +#define XENON_EMMC_PHY_REG_BASE0x0170 + +#define XENON_EMMC_PHY_TIMING_ADJUST XENON_EMMC_PHY_REG_BASE +#define XENON_EMMC_5_0_PHY_TIMING_ADJUST XENON_EMMC_5_0_PHY_REG_BASE +#define XENON_TIMING_ADJUST_SLOW_MODE BIT(29) +#define XENON_TIMING_ADJUST_SDIO_MODE BIT(28) +#define XENON_OUTPUT_QSN_PHASE_SELECT BIT(17) +#define XENON_SAMPL_INV_QSP_PHASE_SELECT BIT(18) +#define XENON_SAMPL_INV_QSP_PHASE_SELECT_SHIFT 18 +#define XENON_PHY_INITIALIZAIONBIT(31) +#define XENON_WAIT_CYCLE_BEFORE_USING_MASK 0xF +#define XENON_WAIT_CYCLE_BEFORE_USING_SHIFT12 +#define XENON_FC_SYNC_EN_DURATION_MASK 0xF +#define XENON_FC_SYNC_EN_DURATION_SHIFT8 +#define XENON_FC_SYNC_RST_EN_DURATION_MASK 0xF +#define XENON_FC_SYNC_RST_EN_DURATION_SHIFT4 +#define XENON_FC_SYNC_RST_DURATION_MASK0xF +#define XENON_FC_SYNC_RST_DURATION_SHIFT 0 + +#define XENON_EMMC_PHY_FUNC_CONTROL(XENON_EMMC_PHY_REG_BASE + 0x4) +#define XENON_EMMC_5_0_PHY_FUNC_CONTROL\ + (XENON_EMMC_5_0_PHY_REG_BASE + 0x4) +#define XENON_ASYNC_DDRMODE_MASK BIT(23) +#define XENON_ASYNC_DDRMODE_SHIFT 23 +#define XENON_CMD_DDR_MODE BIT(16) +#define XENON_DQ_DDR_MODE_SHIFT8 +#define XENON_DQ_DDR_MODE_MASK 0xFF +#define XENON_DQ_ASYNC_MODEBIT(4) + +#define XENON_EMMC_PHY_PAD_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x8) +#define XENON_EMMC_5_0_PHY_PAD_CONTROL \ + (XENON_EMMC_5_0_PHY_REG_BASE + 0x8) +#define XENON_REC_EN_SHIFT 24 +#define XENON_REC_EN_MASK 0xF +#define XENON_FC_DQ_RECEN BIT(24) +#define XENON_FC_CMD_RECEN BIT(25) +#define XENON_FC_QSP_RECEN BIT(26) +#define XENON_FC_QSN_RECEN BIT(27) +#define XENON_OEN_QSN BIT(28) +#define XENON_AUTO_RECEN_CTRL BIT(30) +#define XENON_FC_ALL_CMOS_RECEIVER 0xF000 + +#define XENON_EMMC5_FC_QSP_PD BIT(18) +#define XENON_EMMC5_FC_QSP_PU BIT(22) +#define XENON_EMMC5_FC_CMD_PD BIT(17) +#define XENON_EMMC5_FC_CMD_PU BIT(21) +#define XENON_EMMC5_FC_DQ_PD BIT(16) +#define XENON_EMMC5_FC_DQ_PU BIT(20) + +#define XENON_EMMC_PHY_PAD_CONTROL1(XENON_EMMC_PHY_REG_BASE + 0xC) +#define XENON_EMMC5_
[PATCH v5 08/12] mmc: sdhci-xenon: Add SoC PHY PAD voltage control
From: Hu Ziji <huz...@marvell.com>
Some SoCs have PHY PAD outside Xenon IP.
PHY PAD voltage should match signalling voltage in use.
Add generic SoC PHY PAD voltage control interface.
Implement Aramda-3700 SoC PHY PAD voltage control.
Signed-off-by: Hu Ziji <huz...@marvell.com>
Tested-by: Russell King <rmk+ker...@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/mmc/host/sdhci-xenon-phy.c | 116 +-
drivers/mmc/host/sdhci-xenon.c | 2 +-
drivers/mmc/host/sdhci-xenon.h | 2 +-
3 files changed, 119 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-xenon-phy.c
b/drivers/mmc/host/sdhci-xenon-phy.c
index f410712d24ea..1221754b7a3d 100644
--- a/drivers/mmc/host/sdhci-xenon-phy.c
+++ b/drivers/mmc/host/sdhci-xenon-phy.c
@@ -143,6 +143,27 @@ enum phy_type_enum {
NR_PHY_TYPES
};
+enum soc_pad_ctrl_type {
+ SOC_PAD_SD,
+ SOC_PAD_FIXED_1_8V,
+};
+
+struct soc_pad_ctrl_table {
+ const char *soc;
+ void (*set_soc_pad)(struct sdhci_host *host,
+ unsigned char signal_voltage);
+};
+
+struct soc_pad_ctrl {
+ /* Register address of SOC PHY PAD ctrl */
+ void __iomem*reg;
+ /* SOC PHY PAD ctrl type */
+ enum soc_pad_ctrl_type pad_type;
+ /* SOC specific operation to set SOC PHY PAD */
+ void (*set_soc_pad)(struct sdhci_host *host,
+ unsigned char signal_voltage);
+};
+
static struct xenon_emmc_phy_regs xenon_emmc_5_0_phy_regs = {
.timing_adj = XENON_EMMC_5_0_PHY_TIMING_ADJUST,
.func_ctrl = XENON_EMMC_5_0_PHY_FUNC_CONTROL,
@@ -176,6 +197,8 @@ struct emmc_phy_params {
u8 nr_tun_times;
/* Divider for calculating Tuning Step */
u8 tun_step_divider;
+
+ struct soc_pad_ctrl pad_ctrl;
};
static int alloc_emmc_phy(struct sdhci_xenon_priv *priv)
@@ -252,6 +275,45 @@ static int emmc_phy_init(struct sdhci_host *host)
return 0;
}
+#define ARMADA_3700_SOC_PAD_1_8V 0x1
+#define ARMADA_3700_SOC_PAD_3_3V 0x0
+
+static void armada_3700_soc_pad_voltage_set(struct sdhci_host *host,
+ unsigned char signal_voltage)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ struct emmc_phy_params *params = priv->phy_params;
+
+ if (params->pad_ctrl.pad_type == SOC_PAD_FIXED_1_8V) {
+ writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg);
+ } else if (params->pad_ctrl.pad_type == SOC_PAD_SD) {
+ if (signal_voltage == MMC_SIGNAL_VOLTAGE_180)
+ writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg);
+ else if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
+ writel(ARMADA_3700_SOC_PAD_3_3V, params->pad_ctrl.reg);
+ }
+}
+
+/*
+ * Set SOC PHY voltage PAD control register,
+ * according to the operation voltage on PAD.
+ * The detailed operation depends on SOC implementaion.
+ */
+static void emmc_phy_set_soc_pad(struct sdhci_host *host,
+unsigned char signal_voltage)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ struct emmc_phy_params *params = priv->phy_params;
+
+ if (!params->pad_ctrl.reg)
+ return;
+
+ if (params->pad_ctrl.set_soc_pad)
+ params->pad_ctrl.set_soc_pad(host, signal_voltage);
+}
+
/*
* Enable eMMC PHY HW DLL
* DLL should be enabled and stable before HS200/SDR104 tuning,
@@ -621,6 +683,51 @@ static void emmc_phy_set(struct sdhci_host *host,
dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting completes\n");
}
+static int get_dt_pad_ctrl_data(struct sdhci_host *host,
+ struct device_node *np,
+ struct emmc_phy_params *params)
+{
+ int ret = 0;
+ const char *name;
+ struct resource iomem;
+
+ if (of_device_is_compatible(np, "marvell,armada-3700-sdhci"))
+ params->pad_ctrl.set_soc_pad = armada_3700_soc_pad_voltage_set;
+ else
+ return 0;
+
+ if (of_address_to_resource(np, 1, )) {
+ dev_err(mmc_dev(host->mmc), "Unable to find SOC PAD ctrl
register address for %s\n",
+ np->name);
+ return -EINVAL;
+ }
+
+ params->pad_ctrl.reg = devm_ioremap_resource(mmc_dev(host->mmc),
+);
+ if (IS_ERR(params->pad_ctrl.reg)) {
+ dev_err(mmc_dev(host->mmc), "Unable to get SOC PHY PAD ctrl
regiser for %s\n",
+ np->name);
+
[PATCH v5 10/12] arm64: dts: marvell: add eMMC support for Armada 37xx
Add the eMMC support for Armada 37xx SoC and enable it in the Armada 3720
DB board.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 16
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 11 +++
2 files changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index 89de0a751093..118796b325e5 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -72,6 +72,22 @@
status = "okay";
};
+ {
+ non-removable;
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ mmc-hs400-1_8v;
+ marvell,pad-type = "fixed-1-8v";
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mmccard: mmccard@0 {
+ compatible = "mmc-card";
+ reg = <0>;
+ };
+};
+
/* CON31 */
{
status = "okay";
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index bab5c6ff5745..966b6f030bfa 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -184,6 +184,17 @@
};
};
+ sdhci0: sdhci@d8000 {
+ compatible = "marvell,armada-3700-sdhci",
+ "marvell,sdhci-xenon";
+ reg = <0xd8000 0x300
+ 0x17808 0x4>;
+ interrupts = ;
+ clocks = <_periph_clk 0>;
+ clock-names = "core";
+ status = "disabled";
+ };
+
sata: sata@e {
compatible = "marvell,armada-3700-ahci";
reg = <0xe 0x2000>;
--
git-series 0.9.1
[PATCH v5 01/12] clk: apn806: Add eMMC clock to system controller driver
From: Konstantin Porotchkin <kos...@marvell.com>
Add fixed clock of 400MHz to system controller driver. This clock is
used as SD/eMMC clock source.
Signed-off-by: Konstantin Porotchkin <kos...@marvell.com>
Reviewed-by: Omri Itach <om...@marvell.com>
Reviewed-by: Hanna Hawa <han...@marvell.com>
[fixed up conflicts, added error handling --rmk]
Signed-off-by: Russell King <rmk+ker...@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 3 ++-
drivers/clk/mvebu/ap806-system-controller.c | 15 ++-
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index a749ba2edec4..5019c8f4acd0 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -235,7 +235,8 @@
#clock-cells = <1>;
clock-output-names = "ap-cpu-cluster-0",
"ap-cpu-cluster-1",
-"ap-fixed", "ap-mss";
+"ap-fixed", "ap-mss",
+"ap-emmc";
reg = <0x6f4000 0x1000>;
};
};
diff --git a/drivers/clk/mvebu/ap806-system-controller.c
b/drivers/clk/mvebu/ap806-system-controller.c
index 8181b919f062..0a785076b0c6 100644
--- a/drivers/clk/mvebu/ap806-system-controller.c
+++ b/drivers/clk/mvebu/ap806-system-controller.c
@@ -23,7 +23,7 @@
#define AP806_SAR_REG 0x400
#define AP806_SAR_CLKFREQ_MODE_MASK0x1f
-#define AP806_CLK_NUM 4
+#define AP806_CLK_NUM 5
static struct clk *ap806_clks[AP806_CLK_NUM];
@@ -117,6 +117,17 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
goto fail3;
}
+ /* eMMC Clock is fixed clock divided by 3 */
+ of_property_read_string_index(np, "clock-output-names",
+ 4, );
+ ap806_clks[4] = clk_register_fixed_factor(NULL, name, fixedclk_name,
+ 0, 1, 3);
+ if (IS_ERR(ap806_clks[4])) {
+ ret = PTR_ERR(ap806_clks[4]);
+ goto fail4;
+ }
+
+ of_clk_add_provider(np, of_clk_src_onecell_get, _clk_data);
ret = of_clk_add_provider(np, of_clk_src_onecell_get, _clk_data);
if (ret)
goto fail_clk_add;
@@ -124,6 +135,8 @@ static int ap806_syscon_clk_probe(struct platform_device
*pdev)
return 0;
fail_clk_add:
+ clk_unregister_fixed_factor(ap806_clks[4]);
+fail4:
clk_unregister_fixed_factor(ap806_clks[3]);
fail3:
clk_unregister_fixed_rate(ap806_clks[2]);
--
git-series 0.9.1
[PATCH v5 12/12] arm64: configs: enable SDHCI driver for Xenon
This patch enables the driver for the SDHCI controller found on the Marvell Armada 3700 and 7K/8K ARM64 SoCs. Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 869dded0f09f..341fc631f598 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -390,6 +390,7 @@ CONFIG_MMC_DW_EXYNOS=y CONFIG_MMC_DW_K3=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SUNXI=y +CONFIG_MMC_SDHCI_XENON=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y -- git-series 0.9.1
[PATCH v5 11/12] arm64: dts: marvell: add sdhci support for Armada 7K/8K
Also enable it on the Armada 7040 DB board
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 14 +-
arch/arm64/boot/dts/marvell/armada-ap806.dtsi| 10 +-
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 11 ++-
3 files changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index 070b589680c5..6adbfcd26369 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -146,3 +146,17 @@
_usb3_1 {
status = "okay";
};
+
+_sdhci0 {
+ status = "okay";
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+};
+
+_sdhci0 {
+ status = "okay";
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index 5019c8f4acd0..0b49cbda8539 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -229,6 +229,16 @@
};
+ ap_sdhci0: sdhci@6e {
+ compatible = "marvell,armada-8k-sdhci";
+ reg = <0x6e 0x300>;
+ interrupts = ;
+ clock-names = "core";
+ clocks = <_syscon 4>;
+ dma-coherent;
+ status = "disabled";
+ };
+
ap_syscon: system-controller@6f4000 {
compatible = "marvell,ap806-system-controller",
"syscon";
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index 05222f749a45..421e91049cf7 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@ -172,6 +172,17 @@
clocks = <_syscon0 1 25>;
status = "okay";
};
+
+ cpm_sdhci0: sdhci@78 {
+ compatible = "marvell,armada-8k-sdhci";
+ reg = <0x78 0x300>;
+ interrupts = ;
+ clock-names = "core";
+ clocks = <_syscon0 1 4>;
+ dma-coherent;
+ status = "disabled";
+ };
+
};
cpm_pcie0: pcie@f260 {
--
git-series 0.9.1
[PATCH v5 05/12] dt: bindings: Add bindings for Marvell Xenon SD Host Controller
From: Hu Ziji <huz...@marvell.com> Marvell Xenon SDHC can support eMMC/SD/SDIO. Add Xenon-specific properties. Also add properties for Xenon PHY setting. Signed-off-by: Hu Ziji <huz...@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> --- Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt | 197 +++- 1 file changed, 197 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt diff --git a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt new file mode 100644 index ..a3876d2cc616 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt @@ -0,0 +1,197 @@ +Marvell Xenon SDHCI Controller device tree bindings +This file documents differences between the core mmc properties +described by mmc.txt and the properties used by the Xenon implementation. + +Multiple SDHCs might be put into a single Xenon IP, to save size and cost. +Each SDHC is independent and owns independent resources, such as register sets, +clock and PHY. +Each SDHC should have an independent device tree node. + +Required Properties: +- compatible: should be one of the following + - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC. + Must provide a second register area and marvell,pad-type. + - "marvell,armada-8k-sdhci": For controllers on Armada 7K/8K SoC + +- clocks: + Array of clocks required for SDHC. + Require at least input clock for Xenon IP core. + +- clock-names: + Array of names corresponding to clocks property. + The input clock for Xenon IP core should be named as "core". + +- reg: + * For "marvell,armada-3700-sdhci", two register areas. +The first one for Xenon IP register. The second one for the Armada 3700 SoC +PHY PAD Voltage Control register. +Please follow the examples with compatible "marvell,armada-3700-sdhci" +in below. +Please also check property marvell,pad-type in below. + + * For other compatible strings, one register area for Xenon IP. + +Optional Properties: +- mmccard: + mmccard child node must be provided when current SDHC is for eMMC. + Xenon SDHC often can support both SD and eMMC. This child node indicates that + current SDHC is for eMMC card. Thus Xenon eMMC specific configuration and + operations can be enabled prior to eMMC init sequence. + Please refer to Documentation/devicetree/bindings/mmc/mmc-card.txt. + This child node should not be set if current Xenon SDHC is for SD/SDIO. + +- bus-width: + When 8-bit data bus width is in use for eMMC, this property should be + explicitly provided and set as 8. + It is optional when data bus width is 4-bit or 1-bit. + +- mmc-ddr-1_8v: + Select this property when eMMC HS DDR is supported on SDHC side. + +- mmc-hs400-1_8v: + Select this property when eMMC HS400 is supported on SDHC side. + +- no-1-8-v: + Select this property when 1.8V signaling voltage supply is unavailable. + When this property is enabled, both mmc-ddr-1_8v and mmc-hs400-1_8v should be + cleared. + +- marvell,xenon-sdhc-id: + Indicate the corresponding bit index of current SDHC in + SDHC System Operation Control Register Bit[7:0]. + Set/clear the corresponding bit to enable/disable current SDHC. + If Xenon IP contains only one SDHC, this property is optional. + +- marvell,xenon-phy-type: + Xenon support mutilple types of PHYs. + To select eMMC 5.1 PHY, set: + marvell,xenon-phy-type = "emmc 5.1 phy" + eMMC 5.1 PHY is the default choice if this property is not provided. + To select eMMC 5.0 PHY, set: + marvell,xenon-phy-type = "emmc 5.0 phy" + + All those types of PHYs can support eMMC, SD and SDIO. + Please note that this property only presents the type of PHY. + It doesn't stand for the entire SDHC type or property. + For example, "emmc 5.1 phy" doesn't mean that this Xenon SDHC only supports + eMMC 5.1. + +- marvell,xenon-phy-znr: + Set PHY ZNR value. + Only available for eMMC PHY 5.1 and eMMC PHY 5.0. + Valid range = [0:0x1F]. + ZNR is set as 0xF by default if this property is not provided. + +- marvell,xenon-phy-zpr: + Set PHY ZPR value. + Only available for eMMC PHY 5.1 and eMMC PHY 5.0. + Valid range = [0:0x1F]. + ZPR is set as 0xF by default if this property is not provided. + +- marvell,xenon-phy-nr-success-tun: + Set the number of required consecutive successful sampling points used to + identify a valid sampling window, in tuning process. + Valid range = [1:7]. + Set as 0x4 by default if this property is not provided. + +- marvell,xenon-phy-tun-step-divider: + Set the divider for calculating TUN_STEP. + Set as 64 by default if this property is not provided. + +- marvell,xenon-phy-slow-mode: + If this property is selected, transfers will bypass PHY. + Only available when bus frequency lower than 55MHz in SDR md
Re: [PATCH v5 net-next 0/7] Support Armada 37xx SoC (ARMv8 64-bits) in mvneta driver
Hi Marcin, On jeu., déc. 01 2016, Marcin Wojtas <m...@semihalf.com> wrote: > Hi Gregory, > > Checked on a388-gp with and without HWBM, also both ports work on > a3700 (second one after changing to sgmii). > > Tested-by: Marcin Wojtas <m...@semihalf.com> Thanks, I am going to send a new version with tour tested-by and the dts fix for the second port. Gregory > > Best regards, > Marcin > > 2016-11-30 22:42 GMT+01:00 Gregory CLEMENT > <gregory.clem...@free-electrons.com>: >> Hi, >> >> The Armada 37xx is a new ARMv8 SoC from Marvell using same network >> controller as the older Armada 370/38x/XP SoCs. This series adapts the >> driver in order to be able to use it on this new SoC. The main changes >> are: >> >> - 64-bits support: the first patches allow using the driver on a 64-bit >> architecture. >> >> - MBUS support: the mbus configuration is different on Armada 37xx >> from the older SoCs. >> >> - per cpu interrupt: Armada 37xx do not support per cpu interrupt for >> the NETA IP, the non-per-CPU behavior was added back. >> >> The first patch is an optimization in the rx path in swbm mode. >> The second patch remove unnecessary allocation for HWBM. >> The first item is solved by patches 4 and 5. >> The 2 last items are solved by patch 6. >> In patch 7 the dt support is added. >> >> Beside Armada 37xx, this series have been again tested on Armada XP >> and Armada 38x (with Hardware Buffer Management and with Software >> Buffer Management). >> >> This is the 5th version of the series: >> - 1st version: >> http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/469588.html >> >> - 2nd version: >> http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/470476.html >> >> - 3rd version: >> http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/470901.html >> >> - 4th version: >> http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/471039.html >> >> Changelog: >> v4 -> v5: >> - remove unnecessary cast in patch 3 >> >> v3 -> v4: >> - Adding new patch: "net: mvneta: do not allocate buffer in rxq init >>with HWBM" >> >> - Simplify the HWBM case in patch 3 as suggested by Marcin >> >> v2 -> v3: >> - Adding patch 1 "Optimize rx path for small frame" >> >> - Fix the kbuild error by moving the "phys_addr += >> pp->rx_offset_correction;" >> line from patch 2 to patch 3 where rx_offset_correction is introduced. >> >> - Move the memory allocation of the buf_virt_addr of the rxq to be >>called by the probe function in order to avoid a memory leak. >> >> Thanks, >> >> Gregory >> >> Gregory CLEMENT (5): >> net: mvneta: Optimize rx path for small frame >> net: mvneta: Do not allocate buffer in rxq init with HWBM >> net: mvneta: Use cacheable memory to store the rx buffer virtual address >> net: mvneta: Only disable mvneta_bm for 64-bits >> ARM64: dts: marvell: Add network support for Armada 3700 >> >> Marcin Wojtas (2): >> net: mvneta: Convert to be 64 bits compatible >> net: mvneta: Add network support for Armada 3700 SoC >> >> Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt | 7 +- >> arch/arm64/boot/dts/marvell/armada-3720-db.dts| 23 >> +- >> arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 23 >> +- >> drivers/net/ethernet/marvell/Kconfig | 10 +- >> drivers/net/ethernet/marvell/mvneta.c | 344 >> +++- >> 5 files changed, 305 insertions(+), 102 deletions(-) >> >> base-commit: 436accebb53021ef7c63535f60bda410aa87c136 >> -- >> git-series 0.8.10 -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
[PATCH v6 net-next 0/7] Support Armada 37xx SoC (ARMv8 64-bits) in mvneta driver
Hi, The Armada 37xx is a new ARMv8 SoC from Marvell using same network controller as the older Armada 370/38x/XP SoCs. This series adapts the driver in order to be able to use it on this new SoC. The main changes are: - 64-bits support: the first patches allow using the driver on a 64-bit architecture. - MBUS support: the mbus configuration is different on Armada 37xx from the older SoCs. - per cpu interrupt: Armada 37xx do not support per cpu interrupt for the NETA IP, the non-per-CPU behavior was added back. The first patch is an optimization in the rx path in swbm mode. The second patch remove unnecessary allocation for HWBM. The first item is solved by patches 4 and 5. The 2 last items are solved by patch 6. In patch 7 the dt support is added. Beside Armada 37xx, this series have been again tested on Armada XP and Armada 38x (with Hardware Buffer Management and with Software Buffer Management). This is the 6th version of the series: - 1st version: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/469588.html - 2nd version: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/470476.html - 3rd version: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/470901.html - 4th version: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/471039.html - 5th version: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-November/471478.html Changelog: v5 -> v6: - Added Tested-by from Marcin Wojtas on the series - Added Reviewed-by from Jisheng Zhang on patch 3 - Fix eth1 phy mode for Armada 3720 DB board on patch 7 v4 -> v5: - remove unnecessary cast in patch 3 v3 -> v4: - Adding new patch: "net: mvneta: do not allocate buffer in rxq init with HWBM" - Simplify the HWBM case in patch 3 as suggested by Marcin v2 -> v3: - Adding patch 1 "Optimize rx path for small frame" - Fix the kbuild error by moving the "phys_addr += pp->rx_offset_correction;" line from patch 2 to patch 3 where rx_offset_correction is introduced. - Move the memory allocation of the buf_virt_addr of the rxq to be called by the probe function in order to avoid a memory leak. Thanks, Gregory Gregory CLEMENT (5): net: mvneta: Optimize rx path for small frame net: mvneta: Do not allocate buffer in rxq init with HWBM net: mvneta: Use cacheable memory to store the rx buffer virtual address net: mvneta: Only disable mvneta_bm for 64-bits ARM64: dts: marvell: Add network support for Armada 3700 Marcin Wojtas (2): net: mvneta: Convert to be 64 bits compatible net: mvneta: Add network support for Armada 3700 SoC Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt | 7 +- arch/arm64/boot/dts/marvell/armada-3720-db.dts| 23 +- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 23 +- drivers/net/ethernet/marvell/Kconfig | 10 +- drivers/net/ethernet/marvell/mvneta.c | 344 +++- 5 files changed, 305 insertions(+), 102 deletions(-) base-commit: 436accebb53021ef7c63535f60bda410aa87c136 -- git-series 0.8.10
[PATCH v6 net-next 2/7] net: mvneta: Do not allocate buffer in rxq init with HWBM
For HWBM all buffers are allocated in mvneta_bm_construct() and in runtime
they are put into descriptors by hardware. There is no need to fill them
at this point.
Suggested-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Tested-by: Marcin Wojtas <m...@semihalf.com>
---
drivers/net/ethernet/marvell/mvneta.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 1b84f746d748..f5319c50f8d9 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -2784,14 +2784,14 @@ static int mvneta_rxq_init(struct mvneta_port *pp,
mvneta_rxq_buf_size_set(pp, rxq,
MVNETA_RX_BUF_SIZE(pp->pkt_size));
mvneta_rxq_bm_disable(pp, rxq);
+ mvneta_rxq_fill(pp, rxq, rxq->size);
} else {
mvneta_rxq_bm_enable(pp, rxq);
mvneta_rxq_long_pool_set(pp, rxq);
mvneta_rxq_short_pool_set(pp, rxq);
+ mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size);
}
- mvneta_rxq_fill(pp, rxq, rxq->size);
-
return 0;
}
--
git-series 0.8.10
[PATCH v6 net-next 7/7] ARM64: dts: marvell: Add network support for Armada 3700
Add neta nodes for network support both in device tree for the SoC and
the board.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 23 +++-
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 23 +++-
2 files changed, 46 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index 1372e9a6aaa4..a59d36cd6caf 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -81,3 +81,26 @@
{
status = "okay";
};
+
+ {
+ status = "okay";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+ {
+ phy-mode = "rgmii-id";
+ phy = <>;
+ status = "okay";
+};
+
+ {
+ phy-mode = "sgmii";
+ phy = <>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index e9bd58793464..3b8eb45bdc76 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -140,6 +140,29 @@
};
};
+ eth0: ethernet@3 {
+ compatible = "marvell,armada-3700-neta";
+ reg = <0x3 0x4000>;
+ interrupts = ;
+ clocks = <_periph_clk 8>;
+ status = "disabled";
+ };
+
+ mdio: mdio@32004 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,orion-mdio";
+ reg = <0x32004 0x4>;
+ };
+
+ eth1: ethernet@4 {
+ compatible = "marvell,armada-3700-neta";
+ reg = <0x4 0x4000>;
+ interrupts = ;
+ clocks = <_periph_clk 7>;
+ status = "disabled";
+ };
+
usb3: usb@58000 {
compatible = "marvell,armada3700-xhci",
"generic-xhci";
--
git-series 0.8.10
[PATCH v6 net-next 1/7] net: mvneta: Optimize rx path for small frame
For small frame reuse the phys_addr variable instead of accessing the uncacheable value in the rx descriptor. Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> Tested-by: Marcin Wojtas <m...@semihalf.com> --- drivers/net/ethernet/marvell/mvneta.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c index 87274d4ab102..1b84f746d748 100644 --- a/drivers/net/ethernet/marvell/mvneta.c +++ b/drivers/net/ethernet/marvell/mvneta.c @@ -1918,7 +1918,7 @@ static int mvneta_rx_swbm(struct mvneta_port *pp, int rx_todo, goto err_drop_frame; dma_sync_single_range_for_cpu(dev->dev.parent, - rx_desc->buf_phys_addr, + phys_addr, MVNETA_MH_SIZE + NET_SKB_PAD, rx_bytes, DMA_FROM_DEVICE); -- git-series 0.8.10
[PATCH v6 net-next 4/7] net: mvneta: Convert to be 64 bits compatible
From: Marcin Wojtas <m...@semihalf.com>
Prepare the mvneta driver in order to be usable on the 64 bits platform
such as the Armada 3700.
[gregory.clem...@free-electrons.com]: this patch was extract from a larger
one to ease review and maintenance.
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Tested-by: Marcin Wojtas <m...@semihalf.com>
---
drivers/net/ethernet/marvell/mvneta.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 92b9af14c352..8ef03fb69bcd 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -296,6 +296,12 @@
/* descriptor aligned size */
#define MVNETA_DESC_ALIGNED_SIZE 32
+/* Number of bytes to be taken into account by HW when putting incoming data
+ * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet
+ * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers.
+ */
+#define MVNETA_RX_PKT_OFFSET_CORRECTION64
+
#define MVNETA_RX_PKT_SIZE(mtu) \
ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
ETH_HLEN + ETH_FCS_LEN,\
@@ -416,6 +422,7 @@ struct mvneta_port {
u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
+ u16 rx_offset_correction;
};
/* The mvneta_tx_desc and mvneta_rx_desc structures describe the
@@ -1807,6 +1814,7 @@ static int mvneta_rx_refill(struct mvneta_port *pp,
return -ENOMEM;
}
+ phys_addr += pp->rx_offset_correction;
mvneta_rx_desc_fill(rx_desc, phys_addr, data, rxq);
return 0;
}
@@ -2782,7 +2790,7 @@ static int mvneta_rxq_init(struct mvneta_port *pp,
mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
/* Set Offset */
- mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD);
+ mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD - pp->rx_offset_correction);
/* Set coalescing pkts and time */
mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
@@ -4033,6 +4041,13 @@ static int mvneta_probe(struct platform_device *pdev)
pp->rxq_def = rxq_def;
+ /* Set RX packet offset correction for platforms, whose
+* NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit
+* platforms and 0B for 32-bit ones.
+*/
+ pp->rx_offset_correction =
+ max(0, NET_SKB_PAD - MVNETA_RX_PKT_OFFSET_CORRECTION);
+
pp->indir[0] = rxq_def;
pp->clk = devm_clk_get(>dev, "core");
--
git-series 0.8.10
