Re: [RESEND PATCH v5 0/6] IR support for A83T
On 13.02.2018 13:29, Philipp Rossak wrote: This patch series adds support for the sunxi A83T ir module and enhances the sunxi-ir driver. Right now the base clock frequency for the ir driver is a hard coded define and is set to 8 MHz. This works for the most common ir receivers. On the Sinovoip Bananapi M3 the ir receiver needs, a 3 MHz base clock frequency to work without problems with this driver. This patch series adds support for an optinal property that makes it able to override the default base clock frequency and enables the ir interface on the a83t and the Bananapi M3. changes since v4: * rename cir pin from cir_pins to r_cir_pin * drop unit-adress from r_cir_pin * add a83t compatible to the cir node * move muxing options to dtsi * rename cir label and reorder it in the bananpim3.dts file changes since v3: * collecting all acks & reviewd by * fixed typos changes since v2: * reorder cir pin (alphabetical) * fix typo in documentation changes since v1: * fix typos, reword Documentation * initialize 'b_clk_freq' to 'SUNXI_IR_BASE_CLK' & remove if statement * change dev_info() to dev_dbg() * change naming to cir* in dts/dtsi * Added acked Ackedi-by to related patch * use whole memory block instead of registers needed + fix for h3/h5 changes since rfc: * The property is now optinal. If the property is not available in the dtb the driver uses the default base clock frequency. * the driver prints out the the selected base clock frequency. * changed devicetree property from base-clk-frequency to clock-frequency Regards, Philipp Philipp Rossak (6): media: rc: update sunxi-ir driver to get base clock frequency from devicetree media: dt: bindings: Update binding documentation for sunxi IR controller arm: dts: sun8i: a83t: Add the cir pin for the A83T arm: dts: sun8i: a83t: Add support for the cir interface arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller arm: dts: sun8i: h3-h5: ir register size should be the whole memory block Documentation/devicetree/bindings/media/sunxi-ir.txt | 3 +++ arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 5 + arch/arm/boot/dts/sun8i-a83t.dtsi| 18 ++ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +- drivers/media/rc/sunxi-cir.c | 19 +++ 5 files changed, 38 insertions(+), 9 deletions(-) I talked yesterday with Maxime about this patch series. And he told me if the first to patches got merged, he will apply the dts patches to the sunxi tree. Sean, can you merge the first two patches through the rc-core? Thanks, Philipp
[RESEND PATCH v5 1/6] media: rc: update sunxi-ir driver to get base clock frequency from devicetree
This patch updates the sunxi-ir driver to set the base clock frequency from
devicetree.
This is necessary since there are different ir receivers on the
market, that operate with different frequencies. So this value could be
set if the attached ir receiver needs a different base clock frequency,
than the default 8 MHz.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Reviewed-by: Andi Shyti <andi.sh...@samsung.com>
Acked-by: Sean Young <s...@mess.org>
---
drivers/media/rc/sunxi-cir.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index 97f367b446c4..f500cea228a9 100644
--- a/drivers/media/rc/sunxi-cir.c
+++ b/drivers/media/rc/sunxi-cir.c
@@ -72,12 +72,8 @@
/* CIR_REG register idle threshold */
#define REG_CIR_ITHR(val)(((val) << 8) & (GENMASK(15, 8)))
-/* Required frequency for IR0 or IR1 clock in CIR mode */
+/* Required frequency for IR0 or IR1 clock in CIR mode (default) */
#define SUNXI_IR_BASE_CLK 800
-/* Frequency after IR internal divider */
-#define SUNXI_IR_CLK (SUNXI_IR_BASE_CLK / 64)
-/* Sample period in ns */
-#define SUNXI_IR_SAMPLE (10ul / SUNXI_IR_CLK)
/* Noise threshold in samples */
#define SUNXI_IR_RXNOISE 1
/* Idle Threshold in samples */
@@ -122,7 +118,8 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
/* for each bit in fifo */
dt = readb(ir->base + SUNXI_IR_RXFIFO_REG);
rawir.pulse = (dt & 0x80) != 0;
- rawir.duration = ((dt & 0x7f) + 1) * SUNXI_IR_SAMPLE;
+ rawir.duration = ((dt & 0x7f) + 1) *
+ir->rc->rx_resolution;
ir_raw_event_store_with_filter(ir->rc, );
}
}
@@ -148,6 +145,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)
struct device_node *dn = dev->of_node;
struct resource *res;
struct sunxi_ir *ir;
+ u32 b_clk_freq = SUNXI_IR_BASE_CLK;
ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL);
if (!ir)
@@ -172,6 +170,9 @@ static int sunxi_ir_probe(struct platform_device *pdev)
return PTR_ERR(ir->clk);
}
+ /* Base clock frequency (optional) */
+ of_property_read_u32(dn, "clock-frequency", _clk_freq);
+
/* Reset (optional) */
ir->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
if (IS_ERR(ir->rst))
@@ -180,11 +181,12 @@ static int sunxi_ir_probe(struct platform_device *pdev)
if (ret)
return ret;
- ret = clk_set_rate(ir->clk, SUNXI_IR_BASE_CLK);
+ ret = clk_set_rate(ir->clk, b_clk_freq);
if (ret) {
dev_err(dev, "set ir base clock failed!\n");
goto exit_reset_assert;
}
+ dev_dbg(dev, "set base clock frequency to %d Hz.\n", b_clk_freq);
if (clk_prepare_enable(ir->apb_clk)) {
dev_err(dev, "try to enable apb_ir_clk failed\n");
@@ -225,7 +227,8 @@ static int sunxi_ir_probe(struct platform_device *pdev)
ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
ir->rc->dev.parent = dev;
ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
- ir->rc->rx_resolution = SUNXI_IR_SAMPLE;
+ /* Frequency after IR internal divider with sample period in ns */
+ ir->rc->rx_resolution = (10ul / (b_clk_freq / 64));
ir->rc->timeout = MS_TO_NS(SUNXI_IR_TIMEOUT);
ir->rc->driver_name = SUNXI_IR_DEV;
--
2.11.0
[RESEND PATCH v5 0/6] IR support for A83T
This patch series adds support for the sunxi A83T ir module and enhances the sunxi-ir driver. Right now the base clock frequency for the ir driver is a hard coded define and is set to 8 MHz. This works for the most common ir receivers. On the Sinovoip Bananapi M3 the ir receiver needs, a 3 MHz base clock frequency to work without problems with this driver. This patch series adds support for an optinal property that makes it able to override the default base clock frequency and enables the ir interface on the a83t and the Bananapi M3. changes since v4: * rename cir pin from cir_pins to r_cir_pin * drop unit-adress from r_cir_pin * add a83t compatible to the cir node * move muxing options to dtsi * rename cir label and reorder it in the bananpim3.dts file changes since v3: * collecting all acks & reviewd by * fixed typos changes since v2: * reorder cir pin (alphabetical) * fix typo in documentation changes since v1: * fix typos, reword Documentation * initialize 'b_clk_freq' to 'SUNXI_IR_BASE_CLK' & remove if statement * change dev_info() to dev_dbg() * change naming to cir* in dts/dtsi * Added acked Ackedi-by to related patch * use whole memory block instead of registers needed + fix for h3/h5 changes since rfc: * The property is now optinal. If the property is not available in the dtb the driver uses the default base clock frequency. * the driver prints out the the selected base clock frequency. * changed devicetree property from base-clk-frequency to clock-frequency Regards, Philipp Philipp Rossak (6): media: rc: update sunxi-ir driver to get base clock frequency from devicetree media: dt: bindings: Update binding documentation for sunxi IR controller arm: dts: sun8i: a83t: Add the cir pin for the A83T arm: dts: sun8i: a83t: Add support for the cir interface arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller arm: dts: sun8i: h3-h5: ir register size should be the whole memory block Documentation/devicetree/bindings/media/sunxi-ir.txt | 3 +++ arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 5 + arch/arm/boot/dts/sun8i-a83t.dtsi| 18 ++ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +- drivers/media/rc/sunxi-cir.c | 19 +++ 5 files changed, 38 insertions(+), 9 deletions(-) -- 2.11.0
[RESEND PATCH v5 6/6] arm: dts: sun8i: h3-h5: ir register size should be the whole memory block
The size of the register should be the size of the whole memory block, not just the registers, that are needed. Signed-off-by: Philipp Rossak <embe...@gmail.com> --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 7a83b15225c7..22f6e126b8df 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -712,7 +712,7 @@ clock-names = "apb", "ir"; resets = <_ccu RST_APB0_IR>; interrupts = ; - reg = <0x01f02000 0x40>; + reg = <0x01f02000 0x400>; status = "disabled"; }; -- 2.11.0
[RESEND PATCH v5 4/6] arm: dts: sun8i: a83t: Add support for the cir interface
The cir interface is like on the H3 located at 0x01f02000 and is exactly
the same. This patch adds support for the ir interface on the A83T.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index f7f78a27e21d..1e04a5cfd32d 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -704,6 +704,19 @@
#reset-cells = <1>;
};
+ r_cir: ir@1f02000 {
+ compatible = "allwinner,sun8i-a83t-ir",
+"allwinner,sun5i-a13-ir";
+ clocks = <_ccu CLK_APB0_IR>, <_ccu CLK_IR>;
+ clock-names = "apb", "ir";
+ resets = <_ccu RST_APB0_IR>;
+ interrupts = ;
+ reg = <0x01f02000 0x400>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_cir_pin>;
+ status = "disabled";
+ };
+
r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun8i-a83t-r-pinctrl";
reg = <0x01f02c00 0x400>;
--
2.11.0
[RESEND PATCH v5 3/6] arm: dts: sun8i: a83t: Add the cir pin for the A83T
The CIR Pin of the A83T is located at PL12.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 7f4955a5fab7..f7f78a27e21d 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -716,6 +716,11 @@
interrupt-controller;
#interrupt-cells = <3>;
+ r_cir_pin: r-cir-pin {
+ pins = "PL12";
+ function = "s_cir_rx";
+ };
+
r_rsb_pins: r-rsb-pins {
pins = "PL0", "PL1";
function = "s_rsb";
--
2.11.0
[RESEND PATCH v5 2/6] media: dt: bindings: Update binding documentation for sunxi IR controller
This patch updates documentation for Device-Tree bindings for sunxi IR
controller and adds the new optional property for the base clock
frequency.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
Documentation/devicetree/bindings/media/sunxi-ir.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt
b/Documentation/devicetree/bindings/media/sunxi-ir.txt
index 91648c569b1e..278098987edb 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
@@ -11,6 +11,8 @@ Required properties:
Optional properties:
- linux,rc-map-name: see rc.txt file in the same directory.
- resets : phandle + reset specifier pair
+- clock-frequency : IR Receiver clock frequency, in Hertz. Defaults to 8 MHz
+if missing.
Example:
@@ -18,6 +20,7 @@ ir0: ir@1c21800 {
compatible = "allwinner,sun4i-a10-ir";
clocks = <_gates 6>, <_clk>;
clock-names = "apb", "ir";
+ clock-frequency = <300>;
resets = <_rst 1>;
interrupts = <0 5 1>;
reg = <0x01C21800 0x40>;
--
2.11.0
[RESEND PATCH v5 5/6] arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller
The Bananapi M3 has an onboard IR receiver.
This enables the onboard IR receiver subnode.
Unlike the other IR receivers this one needs a base clock frequency
of 300 Hz (3 MHz), to be able to work.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
index 6550bf0e594b..26c015fd4f4d 100644
--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
@@ -145,6 +145,11 @@
status = "okay";
};
+_cir {
+ clock-frequency = <300>;
+ status = "okay";
+};
+
_rsb {
status = "okay";
--
2.11.0
Re: [PATCH v5 0/6] IR support for A83T
On 30.01.2018 18:46, Philipp Rossak wrote: This patch series adds support for the sunxi A83T ir module and enhances the sunxi-ir driver. Right now the base clock frequency for the ir driver is a hard coded define and is set to 8 MHz. This works for the most common ir receivers. On the Sinovoip Bananapi M3 the ir receiver needs, a 3 MHz base clock frequency to work without problems with this driver. This patch series adds support for an optinal property that makes it able to override the default base clock frequency and enables the ir interface on the a83t and the Bananapi M3. changes since v4: * rename cir pin from cir_pins to r_cir_pin * drop unit-adress from r_cir_pin * add a83t compatible to the cir node * move muxing options to dtsi * rename cir label and reorder it in the bananpim3.dts file changes since v3: * collecting all acks & reviewd by * fixed typos changes since v2: * reorder cir pin (alphabetical) * fix typo in documentation changes since v1: * fix typos, reword Documentation * initialize 'b_clk_freq' to 'SUNXI_IR_BASE_CLK' & remove if statement * change dev_info() to dev_dbg() * change naming to cir* in dts/dtsi * Added acked Ackedi-by to related patch * use whole memory block instead of registers needed + fix for h3/h5 changes since rfc: * The property is now optinal. If the property is not available in the dtb the driver uses the default base clock frequency. * the driver prints out the the selected base clock frequency. * changed devicetree property from base-clk-frequency to clock-frequency Regards, Philipp Philipp Rossak (6): media: rc: update sunxi-ir driver to get base clock frequency from devicetree media: dt: bindings: Update binding documentation for sunxi IR controller arm: dts: sun8i: a83t: Add the cir pin for the A83T arm: dts: sun8i: a83t: Add support for the cir interface arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller arm: dts: sun8i: h3-h5: ir register size should be the whole memory block Documentation/devicetree/bindings/media/sunxi-ir.txt | 3 +++ arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 5 + arch/arm/boot/dts/sun8i-a83t.dtsi| 18 ++ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +- drivers/media/rc/sunxi-cir.c | 19 +++ 5 files changed, 38 insertions(+), 9 deletions(-) Hey, RC1 is now out, thus I would like to ask you to have a look at this patch series again. Some patches still miss an acked-by. It would be nice if we could schedule this for v4.17. Thanks, Philipp
[PATCH v5 0/6] IR support for A83T
This patch series adds support for the sunxi A83T ir module and enhances the sunxi-ir driver. Right now the base clock frequency for the ir driver is a hard coded define and is set to 8 MHz. This works for the most common ir receivers. On the Sinovoip Bananapi M3 the ir receiver needs, a 3 MHz base clock frequency to work without problems with this driver. This patch series adds support for an optinal property that makes it able to override the default base clock frequency and enables the ir interface on the a83t and the Bananapi M3. changes since v4: * rename cir pin from cir_pins to r_cir_pin * drop unit-adress from r_cir_pin * add a83t compatible to the cir node * move muxing options to dtsi * rename cir label and reorder it in the bananpim3.dts file changes since v3: * collecting all acks & reviewd by * fixed typos changes since v2: * reorder cir pin (alphabetical) * fix typo in documentation changes since v1: * fix typos, reword Documentation * initialize 'b_clk_freq' to 'SUNXI_IR_BASE_CLK' & remove if statement * change dev_info() to dev_dbg() * change naming to cir* in dts/dtsi * Added acked Ackedi-by to related patch * use whole memory block instead of registers needed + fix for h3/h5 changes since rfc: * The property is now optinal. If the property is not available in the dtb the driver uses the default base clock frequency. * the driver prints out the the selected base clock frequency. * changed devicetree property from base-clk-frequency to clock-frequency Regards, Philipp Philipp Rossak (6): media: rc: update sunxi-ir driver to get base clock frequency from devicetree media: dt: bindings: Update binding documentation for sunxi IR controller arm: dts: sun8i: a83t: Add the cir pin for the A83T arm: dts: sun8i: a83t: Add support for the cir interface arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller arm: dts: sun8i: h3-h5: ir register size should be the whole memory block Documentation/devicetree/bindings/media/sunxi-ir.txt | 3 +++ arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 5 + arch/arm/boot/dts/sun8i-a83t.dtsi| 18 ++ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +- drivers/media/rc/sunxi-cir.c | 19 +++ 5 files changed, 38 insertions(+), 9 deletions(-) -- 2.11.0
[PATCH v5 2/6] media: dt: bindings: Update binding documentation for sunxi IR controller
This patch updates documentation for Device-Tree bindings for sunxi IR
controller and adds the new optional property for the base clock
frequency.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
Documentation/devicetree/bindings/media/sunxi-ir.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt
b/Documentation/devicetree/bindings/media/sunxi-ir.txt
index 91648c569b1e..278098987edb 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
@@ -11,6 +11,8 @@ Required properties:
Optional properties:
- linux,rc-map-name: see rc.txt file in the same directory.
- resets : phandle + reset specifier pair
+- clock-frequency : IR Receiver clock frequency, in Hertz. Defaults to 8 MHz
+if missing.
Example:
@@ -18,6 +20,7 @@ ir0: ir@1c21800 {
compatible = "allwinner,sun4i-a10-ir";
clocks = <_gates 6>, <_clk>;
clock-names = "apb", "ir";
+ clock-frequency = <300>;
resets = <_rst 1>;
interrupts = <0 5 1>;
reg = <0x01C21800 0x40>;
--
2.11.0
[PATCH v5 1/6] media: rc: update sunxi-ir driver to get base clock frequency from devicetree
This patch updates the sunxi-ir driver to set the base clock frequency from
devicetree.
This is necessary since there are different ir receivers on the
market, that operate with different frequencies. So this value could be
set if the attached ir receiver needs a different base clock frequency,
than the default 8 MHz.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Reviewed-by: Andi Shyti <andi.sh...@samsung.com>
Acked-by: Sean Young <s...@mess.org>
---
drivers/media/rc/sunxi-cir.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index 97f367b446c4..f500cea228a9 100644
--- a/drivers/media/rc/sunxi-cir.c
+++ b/drivers/media/rc/sunxi-cir.c
@@ -72,12 +72,8 @@
/* CIR_REG register idle threshold */
#define REG_CIR_ITHR(val)(((val) << 8) & (GENMASK(15, 8)))
-/* Required frequency for IR0 or IR1 clock in CIR mode */
+/* Required frequency for IR0 or IR1 clock in CIR mode (default) */
#define SUNXI_IR_BASE_CLK 800
-/* Frequency after IR internal divider */
-#define SUNXI_IR_CLK (SUNXI_IR_BASE_CLK / 64)
-/* Sample period in ns */
-#define SUNXI_IR_SAMPLE (10ul / SUNXI_IR_CLK)
/* Noise threshold in samples */
#define SUNXI_IR_RXNOISE 1
/* Idle Threshold in samples */
@@ -122,7 +118,8 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
/* for each bit in fifo */
dt = readb(ir->base + SUNXI_IR_RXFIFO_REG);
rawir.pulse = (dt & 0x80) != 0;
- rawir.duration = ((dt & 0x7f) + 1) * SUNXI_IR_SAMPLE;
+ rawir.duration = ((dt & 0x7f) + 1) *
+ir->rc->rx_resolution;
ir_raw_event_store_with_filter(ir->rc, );
}
}
@@ -148,6 +145,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)
struct device_node *dn = dev->of_node;
struct resource *res;
struct sunxi_ir *ir;
+ u32 b_clk_freq = SUNXI_IR_BASE_CLK;
ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL);
if (!ir)
@@ -172,6 +170,9 @@ static int sunxi_ir_probe(struct platform_device *pdev)
return PTR_ERR(ir->clk);
}
+ /* Base clock frequency (optional) */
+ of_property_read_u32(dn, "clock-frequency", _clk_freq);
+
/* Reset (optional) */
ir->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
if (IS_ERR(ir->rst))
@@ -180,11 +181,12 @@ static int sunxi_ir_probe(struct platform_device *pdev)
if (ret)
return ret;
- ret = clk_set_rate(ir->clk, SUNXI_IR_BASE_CLK);
+ ret = clk_set_rate(ir->clk, b_clk_freq);
if (ret) {
dev_err(dev, "set ir base clock failed!\n");
goto exit_reset_assert;
}
+ dev_dbg(dev, "set base clock frequency to %d Hz.\n", b_clk_freq);
if (clk_prepare_enable(ir->apb_clk)) {
dev_err(dev, "try to enable apb_ir_clk failed\n");
@@ -225,7 +227,8 @@ static int sunxi_ir_probe(struct platform_device *pdev)
ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
ir->rc->dev.parent = dev;
ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
- ir->rc->rx_resolution = SUNXI_IR_SAMPLE;
+ /* Frequency after IR internal divider with sample period in ns */
+ ir->rc->rx_resolution = (10ul / (b_clk_freq / 64));
ir->rc->timeout = MS_TO_NS(SUNXI_IR_TIMEOUT);
ir->rc->driver_name = SUNXI_IR_DEV;
--
2.11.0
[PATCH v5 3/6] arm: dts: sun8i: a83t: Add the cir pin for the A83T
The CIR Pin of the A83T is located at PL12.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 7f4955a5fab7..f7f78a27e21d 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -716,6 +716,11 @@
interrupt-controller;
#interrupt-cells = <3>;
+ r_cir_pin: r-cir-pin {
+ pins = "PL12";
+ function = "s_cir_rx";
+ };
+
r_rsb_pins: r-rsb-pins {
pins = "PL0", "PL1";
function = "s_rsb";
--
2.11.0
[PATCH v5 4/6] arm: dts: sun8i: a83t: Add support for the cir interface
The cir interface is like on the H3 located at 0x01f02000 and is exactly
the same. This patch adds support for the ir interface on the A83T.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index f7f78a27e21d..1e04a5cfd32d 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -704,6 +704,19 @@
#reset-cells = <1>;
};
+ r_cir: ir@1f02000 {
+ compatible = "allwinner,sun8i-a83t-ir",
+"allwinner,sun5i-a13-ir";
+ clocks = <_ccu CLK_APB0_IR>, <_ccu CLK_IR>;
+ clock-names = "apb", "ir";
+ resets = <_ccu RST_APB0_IR>;
+ interrupts = ;
+ reg = <0x01f02000 0x400>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_cir_pin>;
+ status = "disabled";
+ };
+
r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun8i-a83t-r-pinctrl";
reg = <0x01f02c00 0x400>;
--
2.11.0
[PATCH v5 5/6] arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller
The Bananapi M3 has an onboard IR receiver.
This enables the onboard IR receiver subnode.
Unlike the other IR receivers this one needs a base clock frequency
of 300 Hz (3 MHz), to be able to work.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
index 6550bf0e594b..26c015fd4f4d 100644
--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
@@ -145,6 +145,11 @@
status = "okay";
};
+_cir {
+ clock-frequency = <300>;
+ status = "okay";
+};
+
_rsb {
status = "okay";
--
2.11.0
[PATCH v5 6/6] arm: dts: sun8i: h3-h5: ir register size should be the whole memory block
The size of the register should be the size of the whole memory block, not just the registers, that are needed. Signed-off-by: Philipp Rossak <embe...@gmail.com> --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 7a83b15225c7..22f6e126b8df 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -712,7 +712,7 @@ clock-names = "apb", "ir"; resets = <_ccu RST_APB0_IR>; interrupts = ; - reg = <0x01f02000 0x40>; + reg = <0x01f02000 0x400>; status = "disabled"; }; -- 2.11.0
[PATCH v4 0/6] arm: sunxi: IR support for A83T
This patch series adds support for the sunxi A83T ir module and enhances the sunxi-ir driver. Right now the base clock frequency for the ir driver is a hard coded define and is set to 8 MHz. This works for the most common ir receivers. On the Sinovoip Bananapi M3 the ir receiver needs, a 3 MHz base clock frequency to work without problems with this driver. This patch series adds support for an optinal property that makes it able to override the default base clock frequency and enables the ir interface on the a83t and the Bananapi M3. In general this is a resend of the v3 Patchseries, but with collected acked-by and reviewed-by and some typos fixed. changes since v3: * collecting all acks & reviewd by * fixed typos changes since v2: * reorder cir pin (alphabetical) * fix typo in documentation changes since v1: * fix typos, reword Documentation * initialize 'b_clk_freq' to 'SUNXI_IR_BASE_CLK' & remove if statement * change dev_info() to dev_dbg() * change naming to cir* in dts/dtsi * Added acked Ackedi-by to related patch * use whole memory block instead of registers needed + fix for h3/h5 changes since rfc: * The property is now optinal. If the property is not available in the dtb the driver uses the default base clock frequency. * the driver prints out the the selected base clock frequency. * changed devicetree property from base-clk-frequency to clock-frequency Regards, Philipp Philipp Rossak (6): media: rc: update sunxi-ir driver to get base clock frequency from devicetree media: dt: bindings: Update binding documentation for sunxi IR controller arm: dts: sun8i: a83t: Add the cir pin for the A83T arm: dts: sun8i: a83t: Add support for the cir interface arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller arm: dts: sun8i: h3-h8: ir register size should be the whole memory block Documentation/devicetree/bindings/media/sunxi-ir.txt | 3 +++ arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 7 +++ arch/arm/boot/dts/sun8i-a83t.dtsi| 15 +++ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +- drivers/media/rc/sunxi-cir.c | 19 +++ 5 files changed, 37 insertions(+), 9 deletions(-) -- 2.11.0
[PATCH v4 2/6] media: dt: bindings: Update binding documentation for sunxi IR controller
This patch updates documentation for Device-Tree bindings for sunxi IR
controller and adds the new optional property for the base clock
frequency.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
Documentation/devicetree/bindings/media/sunxi-ir.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt
b/Documentation/devicetree/bindings/media/sunxi-ir.txt
index 91648c569b1e..278098987edb 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
@@ -11,6 +11,8 @@ Required properties:
Optional properties:
- linux,rc-map-name: see rc.txt file in the same directory.
- resets : phandle + reset specifier pair
+- clock-frequency : IR Receiver clock frequency, in Hertz. Defaults to 8 MHz
+if missing.
Example:
@@ -18,6 +20,7 @@ ir0: ir@1c21800 {
compatible = "allwinner,sun4i-a10-ir";
clocks = <_gates 6>, <_clk>;
clock-names = "apb", "ir";
+ clock-frequency = <300>;
resets = <_rst 1>;
interrupts = <0 5 1>;
reg = <0x01C21800 0x40>;
--
2.11.0
[PATCH v4 1/6] media: rc: update sunxi-ir driver to get base clock frequency from devicetree
This patch updates the sunxi-ir driver to set the base clock frequency from
devicetree.
This is necessary since there are different ir receivers on the
market, that operate with different frequencies. So this value could be
set if the attached ir receiver needs a different base clock frequency,
than the default 8 MHz.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Reviewed-by: Andi Shyti <andi.sh...@samsung.com>
Acked-by: Sean Young <s...@mess.org>
---
drivers/media/rc/sunxi-cir.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index 97f367b446c4..f500cea228a9 100644
--- a/drivers/media/rc/sunxi-cir.c
+++ b/drivers/media/rc/sunxi-cir.c
@@ -72,12 +72,8 @@
/* CIR_REG register idle threshold */
#define REG_CIR_ITHR(val)(((val) << 8) & (GENMASK(15, 8)))
-/* Required frequency for IR0 or IR1 clock in CIR mode */
+/* Required frequency for IR0 or IR1 clock in CIR mode (default) */
#define SUNXI_IR_BASE_CLK 800
-/* Frequency after IR internal divider */
-#define SUNXI_IR_CLK (SUNXI_IR_BASE_CLK / 64)
-/* Sample period in ns */
-#define SUNXI_IR_SAMPLE (10ul / SUNXI_IR_CLK)
/* Noise threshold in samples */
#define SUNXI_IR_RXNOISE 1
/* Idle Threshold in samples */
@@ -122,7 +118,8 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
/* for each bit in fifo */
dt = readb(ir->base + SUNXI_IR_RXFIFO_REG);
rawir.pulse = (dt & 0x80) != 0;
- rawir.duration = ((dt & 0x7f) + 1) * SUNXI_IR_SAMPLE;
+ rawir.duration = ((dt & 0x7f) + 1) *
+ir->rc->rx_resolution;
ir_raw_event_store_with_filter(ir->rc, );
}
}
@@ -148,6 +145,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)
struct device_node *dn = dev->of_node;
struct resource *res;
struct sunxi_ir *ir;
+ u32 b_clk_freq = SUNXI_IR_BASE_CLK;
ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL);
if (!ir)
@@ -172,6 +170,9 @@ static int sunxi_ir_probe(struct platform_device *pdev)
return PTR_ERR(ir->clk);
}
+ /* Base clock frequency (optional) */
+ of_property_read_u32(dn, "clock-frequency", _clk_freq);
+
/* Reset (optional) */
ir->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
if (IS_ERR(ir->rst))
@@ -180,11 +181,12 @@ static int sunxi_ir_probe(struct platform_device *pdev)
if (ret)
return ret;
- ret = clk_set_rate(ir->clk, SUNXI_IR_BASE_CLK);
+ ret = clk_set_rate(ir->clk, b_clk_freq);
if (ret) {
dev_err(dev, "set ir base clock failed!\n");
goto exit_reset_assert;
}
+ dev_dbg(dev, "set base clock frequency to %d Hz.\n", b_clk_freq);
if (clk_prepare_enable(ir->apb_clk)) {
dev_err(dev, "try to enable apb_ir_clk failed\n");
@@ -225,7 +227,8 @@ static int sunxi_ir_probe(struct platform_device *pdev)
ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
ir->rc->dev.parent = dev;
ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
- ir->rc->rx_resolution = SUNXI_IR_SAMPLE;
+ /* Frequency after IR internal divider with sample period in ns */
+ ir->rc->rx_resolution = (10ul / (b_clk_freq / 64));
ir->rc->timeout = MS_TO_NS(SUNXI_IR_TIMEOUT);
ir->rc->driver_name = SUNXI_IR_DEV;
--
2.11.0
[PATCH v4 4/6] arm: dts: sun8i: a83t: Add support for the cir interface
The cir interface is like on the H3 located at 0x01f02000 and is exactly
the same. This patch adds support for the ir interface on the A83T.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 06e96db7c41a..ddc0d592107f 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -605,6 +605,16 @@
#reset-cells = <1>;
};
+ cir: cir@01f02000 {
+ compatible = "allwinner,sun5i-a13-ir";
+ clocks = <_ccu CLK_APB0_IR>, <_ccu CLK_IR>;
+ clock-names = "apb", "ir";
+ resets = <_ccu RST_APB0_IR>;
+ interrupts = ;
+ reg = <0x01f02000 0x400>;
+ status = "disabled";
+ };
+
r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun8i-a83t-r-pinctrl";
reg = <0x01f02c00 0x400>;
--
2.11.0
[PATCH v4 3/6] arm: dts: sun8i: a83t: Add the cir pin for the A83T
The CIR Pin of the A83T is located at PL12.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index de5119a2a91c..06e96db7c41a 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -617,6 +617,11 @@
interrupt-controller;
#interrupt-cells = <3>;
+ cir_pins: cir-pins@0 {
+ pins = "PL12";
+ function = "s_cir_rx";
+ };
+
r_rsb_pins: r-rsb-pins {
pins = "PL0", "PL1";
function = "s_rsb";
--
2.11.0
[PATCH v5 5/6] arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller
The Bananapi M3 has an onboard IR receiver.
This enables the onboard IR receiver subnode.
Unlike the other IR receivers this one needs a base clock frequency
of 300 Hz (3 MHz), to be able to work.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
index 6550bf0e594b..ffc6445fd281 100644
--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
@@ -82,6 +82,13 @@
};
};
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ clock-frequency = <300>;
+ status = "okay";
+};
+
{
/* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */
status = "okay";
--
2.11.0
[PATCH v4 6/6] arm: dts: sun8i: h3-h8: ir register size should be the whole memory block
The size of the register should be the size of the whole memory block, not just the registers, that are needed. Signed-off-by: Philipp Rossak <embe...@gmail.com> --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 8d40c00d64bb..a9caeda4a574 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -674,7 +674,7 @@ clock-names = "apb", "ir"; resets = <_ccu RST_APB0_IR>; interrupts = ; - reg = <0x01f02000 0x40>; + reg = <0x01f02000 0x400>; status = "disabled"; }; -- 2.11.0
Re: [PATCH v3 0/6] arm: sunxi: IR support for A83T
On 05.01.2018 15:59, Maxime Ripard wrote: Hi, On Fri, Jan 05, 2018 at 12:02:53PM +, Sean Young wrote: On Tue, Dec 19, 2017 at 09:07:41AM +0100, Philipp Rossak wrote: This patch series adds support for the sunxi A83T ir module and enhances the sunxi-ir driver. Right now the base clock frequency for the ir driver is a hard coded define and is set to 8 MHz. This works for the most common ir receivers. On the Sinovoip Bananapi M3 the ir receiver needs, a 3 MHz base clock frequency to work without problems with this driver. This patch series adds support for an optinal property that makes it able to override the default base clock frequency and enables the ir interface on the a83t and the Bananapi M3. changes since v2: * reorder cir pin (alphabetical) * fix typo in documentation changes since v1: * fix typos, reword Documentation * initialize 'b_clk_freq' to 'SUNXI_IR_BASE_CLK' & remove if statement * change dev_info() to dev_dbg() * change naming to cir* in dts/dtsi * Added acked Ackedi-by to related patch * use whole memory block instead of registers needed + fix for h3/h5 changes since rfc: * The property is now optinal. If the property is not available in the dtb the driver uses the default base clock frequency. * the driver prints out the the selected base clock frequency. * changed devicetree property from base-clk-frequency to clock-frequency Regards, Philipp Philipp Rossak (6): media: rc: update sunxi-ir driver to get base clock frequency from devicetree media: dt: bindings: Update binding documentation for sunxi IR controller arm: dts: sun8i: a83t: Add the cir pin for the A83T arm: dts: sun8i: a83t: Add support for the cir interface arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller arm: dts: sun8i: h3-h8: ir register size should be the whole memory block I can take this series (through rc-core, i.e. linux-media), but I need an maintainer Acked-by: for the sun[x8]i dts changes (all four patches). We'll merge them through our tree. We usually have a rather big number of patches around, so we'd be better off avoiding conflicts :) Philipp, can you resubmit the DTs as soon as -rc1 is out? Thanks! Maxime Yes, I can do this! Regards, Philipp
[PATCH v3 3/6] arm: dts: sun8i: a83t: Add the cir pin for the A83T
The CIR Pin of the A83T is located at PL12.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index de5119a2a91c..06e96db7c41a 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -617,6 +617,11 @@
interrupt-controller;
#interrupt-cells = <3>;
+ cir_pins: cir-pins@0 {
+ pins = "PL12";
+ function = "s_cir_rx";
+ };
+
r_rsb_pins: r-rsb-pins {
pins = "PL0", "PL1";
function = "s_rsb";
--
2.11.0
[PATCH v3 0/6] arm: sunxi: IR support for A83T
This patch series adds support for the sunxi A83T ir module and enhances the sunxi-ir driver. Right now the base clock frequency for the ir driver is a hard coded define and is set to 8 MHz. This works for the most common ir receivers. On the Sinovoip Bananapi M3 the ir receiver needs, a 3 MHz base clock frequency to work without problems with this driver. This patch series adds support for an optinal property that makes it able to override the default base clock frequency and enables the ir interface on the a83t and the Bananapi M3. changes since v2: * reorder cir pin (alphabetical) * fix typo in documentation changes since v1: * fix typos, reword Documentation * initialize 'b_clk_freq' to 'SUNXI_IR_BASE_CLK' & remove if statement * change dev_info() to dev_dbg() * change naming to cir* in dts/dtsi * Added acked Ackedi-by to related patch * use whole memory block instead of registers needed + fix for h3/h5 changes since rfc: * The property is now optinal. If the property is not available in the dtb the driver uses the default base clock frequency. * the driver prints out the the selected base clock frequency. * changed devicetree property from base-clk-frequency to clock-frequency Regards, Philipp Philipp Rossak (6): media: rc: update sunxi-ir driver to get base clock frequency from devicetree media: dt: bindings: Update binding documentation for sunxi IR controller arm: dts: sun8i: a83t: Add the cir pin for the A83T arm: dts: sun8i: a83t: Add support for the cir interface arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller arm: dts: sun8i: h3-h8: ir register size should be the whole memory block Documentation/devicetree/bindings/media/sunxi-ir.txt | 3 +++ arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 7 +++ arch/arm/boot/dts/sun8i-a83t.dtsi| 15 +++ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +- drivers/media/rc/sunxi-cir.c | 19 +++ 5 files changed, 37 insertions(+), 9 deletions(-) -- 2.11.0
[PATCH v3 1/6] media: rc: update sunxi-ir driver to get base clock frequency from devicetree
This patch updates the sunxi-ir driver to set the base clock frequency from
devicetree.
This is necessary since there are different ir receivers on the
market, that operate with different frequencies. So this value could be
set if the attached ir receiver needs a different base clock frequency,
than the default 8 MHz.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
drivers/media/rc/sunxi-cir.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index 97f367b446c4..f500cea228a9 100644
--- a/drivers/media/rc/sunxi-cir.c
+++ b/drivers/media/rc/sunxi-cir.c
@@ -72,12 +72,8 @@
/* CIR_REG register idle threshold */
#define REG_CIR_ITHR(val)(((val) << 8) & (GENMASK(15, 8)))
-/* Required frequency for IR0 or IR1 clock in CIR mode */
+/* Required frequency for IR0 or IR1 clock in CIR mode (default) */
#define SUNXI_IR_BASE_CLK 800
-/* Frequency after IR internal divider */
-#define SUNXI_IR_CLK (SUNXI_IR_BASE_CLK / 64)
-/* Sample period in ns */
-#define SUNXI_IR_SAMPLE (10ul / SUNXI_IR_CLK)
/* Noise threshold in samples */
#define SUNXI_IR_RXNOISE 1
/* Idle Threshold in samples */
@@ -122,7 +118,8 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
/* for each bit in fifo */
dt = readb(ir->base + SUNXI_IR_RXFIFO_REG);
rawir.pulse = (dt & 0x80) != 0;
- rawir.duration = ((dt & 0x7f) + 1) * SUNXI_IR_SAMPLE;
+ rawir.duration = ((dt & 0x7f) + 1) *
+ir->rc->rx_resolution;
ir_raw_event_store_with_filter(ir->rc, );
}
}
@@ -148,6 +145,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)
struct device_node *dn = dev->of_node;
struct resource *res;
struct sunxi_ir *ir;
+ u32 b_clk_freq = SUNXI_IR_BASE_CLK;
ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL);
if (!ir)
@@ -172,6 +170,9 @@ static int sunxi_ir_probe(struct platform_device *pdev)
return PTR_ERR(ir->clk);
}
+ /* Base clock frequency (optional) */
+ of_property_read_u32(dn, "clock-frequency", _clk_freq);
+
/* Reset (optional) */
ir->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
if (IS_ERR(ir->rst))
@@ -180,11 +181,12 @@ static int sunxi_ir_probe(struct platform_device *pdev)
if (ret)
return ret;
- ret = clk_set_rate(ir->clk, SUNXI_IR_BASE_CLK);
+ ret = clk_set_rate(ir->clk, b_clk_freq);
if (ret) {
dev_err(dev, "set ir base clock failed!\n");
goto exit_reset_assert;
}
+ dev_dbg(dev, "set base clock frequency to %d Hz.\n", b_clk_freq);
if (clk_prepare_enable(ir->apb_clk)) {
dev_err(dev, "try to enable apb_ir_clk failed\n");
@@ -225,7 +227,8 @@ static int sunxi_ir_probe(struct platform_device *pdev)
ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
ir->rc->dev.parent = dev;
ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
- ir->rc->rx_resolution = SUNXI_IR_SAMPLE;
+ /* Frequency after IR internal divider with sample period in ns */
+ ir->rc->rx_resolution = (10ul / (b_clk_freq / 64));
ir->rc->timeout = MS_TO_NS(SUNXI_IR_TIMEOUT);
ir->rc->driver_name = SUNXI_IR_DEV;
--
2.11.0
[PATCH v3 4/6] arm: dts: sun8i: a83t: Add support for the cir interface
The cir interface is like on the H3 located at 0x01f02000 and is exactly
the same. This patch adds support for the ir interface on the A83T.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 06e96db7c41a..ddc0d592107f 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -605,6 +605,16 @@
#reset-cells = <1>;
};
+ cir: cir@01f02000 {
+ compatible = "allwinner,sun5i-a13-ir";
+ clocks = <_ccu CLK_APB0_IR>, <_ccu CLK_IR>;
+ clock-names = "apb", "ir";
+ resets = <_ccu RST_APB0_IR>;
+ interrupts = ;
+ reg = <0x01f02000 0x400>;
+ status = "disabled";
+ };
+
r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun8i-a83t-r-pinctrl";
reg = <0x01f02c00 0x400>;
--
2.11.0
[PATCH v3 5/6] arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller
The Bananapi M3 has an onboard IR receiver.
This enables the onboard IR receiver subnode.
Unlike the other IR receivers this one needs a base clock frequency
of 300 Hz (3 MHz), to be able to work.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
index 6550bf0e594b..ffc6445fd281 100644
--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
@@ -82,6 +82,13 @@
};
};
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ clock-frequency = <300>;
+ status = "okay";
+};
+
{
/* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */
status = "okay";
--
2.11.0
[PATCH v3 6/6] arm: dts: sun8i: h3-h8: ir register size should be the whole memory block
The size of the register should be the size of the whole memory block, not just the registers, that are needed. Signed-off-by: Philipp Rossak <embe...@gmail.com> --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 8d40c00d64bb..a9caeda4a574 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -674,7 +674,7 @@ clock-names = "apb", "ir"; resets = <_ccu RST_APB0_IR>; interrupts = ; - reg = <0x01f02000 0x40>; + reg = <0x01f02000 0x400>; status = "disabled"; }; -- 2.11.0
[PATCH v3 2/6] media: dt: bindings: Update binding documentation for sunxi IR controller
This patch updates documentation for Device-Tree bindings for sunxi IR
controller and adds the new optional property for the base clock
frequency.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
Documentation/devicetree/bindings/media/sunxi-ir.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt
b/Documentation/devicetree/bindings/media/sunxi-ir.txt
index 91648c569b1e..278098987edb 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
@@ -11,6 +11,8 @@ Required properties:
Optional properties:
- linux,rc-map-name: see rc.txt file in the same directory.
- resets : phandle + reset specifier pair
+- clock-frequency : IR Receiver clock frequency, in Hertz. Defaults to 8 MHz
+if missing.
Example:
@@ -18,6 +20,7 @@ ir0: ir@1c21800 {
compatible = "allwinner,sun4i-a10-ir";
clocks = <_gates 6>, <_clk>;
clock-names = "apb", "ir";
+ clock-frequency = <300>;
resets = <_rst 1>;
interrupts = <0 5 1>;
reg = <0x01C21800 0x40>;
--
2.11.0
[PATCH v2 1/6] media: rc: update sunxi-ir driver to get base clock frequency from devicetree
This patch updates the sunxi-ir driver to set the base clock frequency from
devicetree.
This is necessary since there are different ir receivers on the
market, that operate with different frequencies. So this value could be
set if the attached ir receiver needs a different base clock frequency,
than the default 8 MHz.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
drivers/media/rc/sunxi-cir.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index 97f367b446c4..f500cea228a9 100644
--- a/drivers/media/rc/sunxi-cir.c
+++ b/drivers/media/rc/sunxi-cir.c
@@ -72,12 +72,8 @@
/* CIR_REG register idle threshold */
#define REG_CIR_ITHR(val)(((val) << 8) & (GENMASK(15, 8)))
-/* Required frequency for IR0 or IR1 clock in CIR mode */
+/* Required frequency for IR0 or IR1 clock in CIR mode (default) */
#define SUNXI_IR_BASE_CLK 800
-/* Frequency after IR internal divider */
-#define SUNXI_IR_CLK (SUNXI_IR_BASE_CLK / 64)
-/* Sample period in ns */
-#define SUNXI_IR_SAMPLE (10ul / SUNXI_IR_CLK)
/* Noise threshold in samples */
#define SUNXI_IR_RXNOISE 1
/* Idle Threshold in samples */
@@ -122,7 +118,8 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
/* for each bit in fifo */
dt = readb(ir->base + SUNXI_IR_RXFIFO_REG);
rawir.pulse = (dt & 0x80) != 0;
- rawir.duration = ((dt & 0x7f) + 1) * SUNXI_IR_SAMPLE;
+ rawir.duration = ((dt & 0x7f) + 1) *
+ir->rc->rx_resolution;
ir_raw_event_store_with_filter(ir->rc, );
}
}
@@ -148,6 +145,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)
struct device_node *dn = dev->of_node;
struct resource *res;
struct sunxi_ir *ir;
+ u32 b_clk_freq = SUNXI_IR_BASE_CLK;
ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL);
if (!ir)
@@ -172,6 +170,9 @@ static int sunxi_ir_probe(struct platform_device *pdev)
return PTR_ERR(ir->clk);
}
+ /* Base clock frequency (optional) */
+ of_property_read_u32(dn, "clock-frequency", _clk_freq);
+
/* Reset (optional) */
ir->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
if (IS_ERR(ir->rst))
@@ -180,11 +181,12 @@ static int sunxi_ir_probe(struct platform_device *pdev)
if (ret)
return ret;
- ret = clk_set_rate(ir->clk, SUNXI_IR_BASE_CLK);
+ ret = clk_set_rate(ir->clk, b_clk_freq);
if (ret) {
dev_err(dev, "set ir base clock failed!\n");
goto exit_reset_assert;
}
+ dev_dbg(dev, "set base clock frequency to %d Hz.\n", b_clk_freq);
if (clk_prepare_enable(ir->apb_clk)) {
dev_err(dev, "try to enable apb_ir_clk failed\n");
@@ -225,7 +227,8 @@ static int sunxi_ir_probe(struct platform_device *pdev)
ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
ir->rc->dev.parent = dev;
ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
- ir->rc->rx_resolution = SUNXI_IR_SAMPLE;
+ /* Frequency after IR internal divider with sample period in ns */
+ ir->rc->rx_resolution = (10ul / (b_clk_freq / 64));
ir->rc->timeout = MS_TO_NS(SUNXI_IR_TIMEOUT);
ir->rc->driver_name = SUNXI_IR_DEV;
--
2.11.0
[PATCH v2 0/6] arm: sunxi: IR support for A83T
This patch series adds support for the sunxi A83T ir module and enhances the sunxi-ir driver. Right now the base clock frequency for the ir driver is a hard coded define and is set to 8 MHz. This works for the most common ir receivers. On the Sinovoip Bananapi M3 the ir receiver needs, a 3 MHz base clock frequency to work without problems with this driver. This patch series adds support for an optinal property that makes it able to override the default base clock frequency and enables the ir interface on the a83t and the Bananapi M3. changes since v1: * fix typos, reword Documentation * initialize 'b_clk_freq' to 'SUNXI_IR_BASE_CLK' & remove if statement * change dev_info() to dev_dbg() * change naming to cir* in dts/dtsi * Added acked Ackedi-by to related patch * use whole memory block instead of registers needed + fix for h3/h5 changes since rfc: * The property is now optinal. If the property is not available in the dtb the driver uses the default base clock frequency. * the driver prints out the the selected base clock frequency. * changed devicetree property from base-clk-frequency to clock-frequency Regards, Philipp Philipp Rossak (6): media: rc: update sunxi-ir driver to get base clock frequency from devicetree media: dt: bindings: Update binding documentation for sunxi IR controller arm: dts: sun8i: a83t: Add the cir pin for the A83T arm: dts: sun8i: a83t: Add support for the cir interface arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller arm: dts: sun8i: h3-h8: ir register size should be the whole memory block Documentation/devicetree/bindings/media/sunxi-ir.txt | 3 +++ arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 7 +++ arch/arm/boot/dts/sun8i-a83t.dtsi| 15 +++ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +- drivers/media/rc/sunxi-cir.c | 19 +++ 5 files changed, 37 insertions(+), 9 deletions(-) -- 2.11.0
[PATCH v2 5/6] arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller
The Bananapi M3 has an onboard IR receiver.
This enables the onboard IR receiver subnode.
Unlike the other IR receivers this one needs a base clock frequency
of 300 Hz (3 MHz), to be able to work.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Chen-Yu Tsai <w...@csie.org>
---
arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
index 6550bf0e594b..ffc6445fd281 100644
--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
@@ -82,6 +82,13 @@
};
};
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ clock-frequency = <300>;
+ status = "okay";
+};
+
{
/* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */
status = "okay";
--
2.11.0
[PATCH v2 6/6] arm: dts: sun8i: h3-h8: ir register size should be the whole memory block
The size of the register should be the size of the whole memory block, not just the registers, that are needed. Signed-off-by: Philipp Rossak <embe...@gmail.com> --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 8d40c00d64bb..a9caeda4a574 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -674,7 +674,7 @@ clock-names = "apb", "ir"; resets = <_ccu RST_APB0_IR>; interrupts = ; - reg = <0x01f02000 0x40>; + reg = <0x01f02000 0x400>; status = "disabled"; }; -- 2.11.0
[PATCH v2 2/6] media: dt: bindings: Update binding documentation for sunxi IR controller
This patch updates documentation for Device-Tree bindings for sunxi IR
controller and adds the new optional property for the base clock
frequency.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
Documentation/devicetree/bindings/media/sunxi-ir.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt
b/Documentation/devicetree/bindings/media/sunxi-ir.txt
index 91648c569b1e..3d7f18780fae 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
@@ -11,6 +11,8 @@ Required properties:
Optional properties:
- linux,rc-map-name: see rc.txt file in the same directory.
- resets : phandle + reset specifier pair
+- clock-frequency : IR Receiver clock frequency, in Herz. Defaults to 8 MHz
+if missing.
Example:
@@ -18,6 +20,7 @@ ir0: ir@1c21800 {
compatible = "allwinner,sun4i-a10-ir";
clocks = <_gates 6>, <_clk>;
clock-names = "apb", "ir";
+ clock-frequency = <300>;
resets = <_rst 1>;
interrupts = <0 5 1>;
reg = <0x01C21800 0x40>;
--
2.11.0
[PATCH v2 3/6] arm: dts: sun8i: a83t: Add the cir pin for the A83T
The CIR Pin of the A83T is located at PL12.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index de5119a2a91c..feffca8a9a24 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -623,6 +623,11 @@
drive-strength = <20>;
bias-pull-up;
};
+
+ cir_pins: cir-pins@0 {
+ pins = "PL12";
+ function = "s_cir_rx";
+ };
};
r_rsb: rsb@1f03400 {
--
2.11.0
[PATCH v2 4/6] arm: dts: sun8i: a83t: Add support for the cir interface
The cir interface is like on the H3 located at 0x01f02000 and is exactly
the same. This patch adds support for the ir interface on the A83T.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index feffca8a9a24..089c270a7f3c 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -605,6 +605,16 @@
#reset-cells = <1>;
};
+ cir: cir@01f02000 {
+ compatible = "allwinner,sun5i-a13-ir";
+ clocks = <_ccu CLK_APB0_IR>, <_ccu CLK_IR>;
+ clock-names = "apb", "ir";
+ resets = <_ccu RST_APB0_IR>;
+ interrupts = ;
+ reg = <0x01f02000 0x400>;
+ status = "disabled";
+ };
+
r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun8i-a83t-r-pinctrl";
reg = <0x01f02c00 0x400>;
--
2.11.0
Re: [PATCH 1/5] media: rc: update sunxi-ir driver to get base clock frequency from devicetree
Hey Andi,
thanks for the feedback. I will fix that in the next version of this
patch series!
On 18.12.2017 03:44, Andi Shyti wrote:
Hi Philipp,
just a couple of small nitpicks.
+ u32 b_clk_freq;
[...]
+ /* Base clock frequency (optional) */
+ if (of_property_read_u32(dn, "clock-frequency", _clk_freq)) {
+ b_clk_freq = SUNXI_IR_BASE_CLK;
+ }
+
how about you intialize 'b_clk_freq' to 'SUNXI_IR_BASE_CLK' and
just call 'of_property_read_u32' without if statement.
'b_clk_freq' value should not be changed if "clock-frequency"
is not present in the DTS.
This might avoid misinterpretation from static analyzers that
might think that 'b_clk_freq' is used uninitialized.
+ dev_info(dev, "set base clock frequency to %d Hz.\n", b_clk_freq);
Please use dev_dbg().
Andi
--
Philipp
[PATCH 2/5] media: dt: bindings: Update binding documentation for sunxi IR controller
This patch updates documentation for Device-Tree bindings for sunxi IR
controller and adds the new optional property for the base clock
frequency.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
Documentation/devicetree/bindings/media/sunxi-ir.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt
b/Documentation/devicetree/bindings/media/sunxi-ir.txt
index 91648c569b1e..9f45bab07d6e 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
@@ -11,6 +11,7 @@ Required properties:
Optional properties:
- linux,rc-map-name: see rc.txt file in the same directory.
- resets : phandle + reset specifier pair
+- clock-frequency : overrides the default base clock frequency (8 MHz)
Example:
@@ -18,6 +19,7 @@ ir0: ir@1c21800 {
compatible = "allwinner,sun4i-a10-ir";
clocks = <_gates 6>, <_clk>;
clock-names = "apb", "ir";
+ clock-frequency = <300>;
resets = <_rst 1>;
interrupts = <0 5 1>;
reg = <0x01C21800 0x40>;
--
2.11.0
[PATCH 1/5] media: rc: update sunxi-ir driver to get base clock frequency from devicetree
This patch updates the sunxi-ir driver to set the base clock frequency from
devicetree.
This is neccessary since there are different ir recievers on the
market, that operate with different frequencys. So this value could be
set if the attached ir receiver needs an other base clock frequency,
than the default 8 MHz.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
drivers/media/rc/sunxi-cir.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index 97f367b446c4..9bbe55a76860 100644
--- a/drivers/media/rc/sunxi-cir.c
+++ b/drivers/media/rc/sunxi-cir.c
@@ -72,12 +72,8 @@
/* CIR_REG register idle threshold */
#define REG_CIR_ITHR(val)(((val) << 8) & (GENMASK(15, 8)))
-/* Required frequency for IR0 or IR1 clock in CIR mode */
+/* Required frequency for IR0 or IR1 clock in CIR mode (default) */
#define SUNXI_IR_BASE_CLK 800
-/* Frequency after IR internal divider */
-#define SUNXI_IR_CLK (SUNXI_IR_BASE_CLK / 64)
-/* Sample period in ns */
-#define SUNXI_IR_SAMPLE (10ul / SUNXI_IR_CLK)
/* Noise threshold in samples */
#define SUNXI_IR_RXNOISE 1
/* Idle Threshold in samples */
@@ -122,7 +118,7 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
/* for each bit in fifo */
dt = readb(ir->base + SUNXI_IR_RXFIFO_REG);
rawir.pulse = (dt & 0x80) != 0;
- rawir.duration = ((dt & 0x7f) + 1) * SUNXI_IR_SAMPLE;
+ rawir.duration = ((dt & 0x7f) + 1) *
ir->rc->rx_resolution;
ir_raw_event_store_with_filter(ir->rc, );
}
}
@@ -148,6 +144,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)
struct device_node *dn = dev->of_node;
struct resource *res;
struct sunxi_ir *ir;
+ u32 b_clk_freq;
ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL);
if (!ir)
@@ -172,6 +169,11 @@ static int sunxi_ir_probe(struct platform_device *pdev)
return PTR_ERR(ir->clk);
}
+ /* Base clock frequency (optional) */
+ if (of_property_read_u32(dn, "clock-frequency", _clk_freq)) {
+ b_clk_freq = SUNXI_IR_BASE_CLK;
+ }
+
/* Reset (optional) */
ir->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
if (IS_ERR(ir->rst))
@@ -180,11 +182,12 @@ static int sunxi_ir_probe(struct platform_device *pdev)
if (ret)
return ret;
- ret = clk_set_rate(ir->clk, SUNXI_IR_BASE_CLK);
+ ret = clk_set_rate(ir->clk, b_clk_freq);
if (ret) {
dev_err(dev, "set ir base clock failed!\n");
goto exit_reset_assert;
}
+ dev_info(dev, "set base clock frequency to %d Hz.\n", b_clk_freq);
if (clk_prepare_enable(ir->apb_clk)) {
dev_err(dev, "try to enable apb_ir_clk failed\n");
@@ -225,7 +228,8 @@ static int sunxi_ir_probe(struct platform_device *pdev)
ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
ir->rc->dev.parent = dev;
ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
- ir->rc->rx_resolution = SUNXI_IR_SAMPLE;
+ /* Frequency after IR internal divider with sample period in ns */
+ ir->rc->rx_resolution = (10ul / (b_clk_freq / 64));
ir->rc->timeout = MS_TO_NS(SUNXI_IR_TIMEOUT);
ir->rc->driver_name = SUNXI_IR_DEV;
--
2.11.0
[PATCH 3/5] arm: dts: sun8i: a83t: Add the ir pin for the A83T
The CIR Pin of the A83T is located at PL12.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index a384b766f3dc..954c2393325f 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -521,6 +521,11 @@
drive-strength = <20>;
bias-pull-up;
};
+
+ ir_pins_a: ir@0 {
+ pins = "PL12";
+ function = "s_cir_rx";
+ };
};
r_rsb: rsb@1f03400 {
--
2.11.0
[PATCH 4/5] arm: dts: sun8i: a83t: Add support for the ir interface
The ir interface is like on the H3 located at 0x01f02000 and is exactly
the same. This patch adds support for the ir interface on the A83T.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 954c2393325f..9e7ed3b9a6b8 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -503,6 +503,16 @@
#reset-cells = <1>;
};
+ ir: ir@01f02000 {
+ compatible = "allwinner,sun5i-a13-ir";
+ clocks = <_ccu CLK_APB0_IR>, <_ccu CLK_IR>;
+ clock-names = "apb", "ir";
+ resets = <_ccu RST_APB0_IR>;
+ interrupts = ;
+ reg = <0x01f02000 0x40>;
+ status = "disabled";
+ };
+
r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun8i-a83t-r-pinctrl";
reg = <0x01f02c00 0x400>;
--
2.11.0
[PATCH 0/5] arm: sunxi: IR support for A83T
This patch series adds support for the sunxi A83T ir module and enhances the sunxi-ir driver. Right now the base clock frequency for the ir driver is a hard coded define and is set to 8 MHz. This works for the most common ir receivers. On the Sinovoip Bananapi M3 the ir receiver needs, a 3 MHz base clock frequency to work without problems with this driver. This patch series adds support for an optinal property that makes it able to override the default base clock frequency and enables the ir interface on the a83t and the Bananapi M3. changes since rfc: * The property is now optinal. If the property is not available in the dtb the driver uses the default base clock frequency. * the driver prints out the the selected base clock frequency. * changed devicetree property from base-clk-frequency to clock-frequency Regards, Philipp rfc: https://www.mail-archive.com/linux-media@vger.kernel.org/msg123359.html Philipp Rossak (5): media: rc: update sunxi-ir driver to get base clock frequency from devicetree media: dt: bindings: Update binding documentation for sunxi IR controller arm: dts: sun8i: a83t: Add the ir pin for the A83T arm: dts: sun8i: a83t: Add support for the ir interface arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller Documentation/devicetree/bindings/media/sunxi-ir.txt | 2 ++ arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 7 +++ arch/arm/boot/dts/sun8i-a83t.dtsi| 15 +++ drivers/media/rc/sunxi-cir.c | 20 4 files changed, 36 insertions(+), 8 deletions(-) -- 2.11.0
[PATCH 5/5] arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller
The Bananapi M3 has an onboard IR receiver.
This enables the onboard IR receiver subnode.
Other than the other IR receivers this one needs a base clock frequency
of 300 Hz (3 MHz), to be able to work.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
index 6550bf0e594b..2bf25ca64133 100644
--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
@@ -100,6 +100,13 @@
status = "okay";
};
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins_a>;
+ clock-frequency = <300>;
+ status = "okay";
+};
+
{
rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
--
2.11.0
Re: [RFC 1/5] [media] rc: update sunxi-ir driver to get base frequency from devicetree
Hey Mauro,
Thanks for your fast feedback!
I will rework the driver like you suggested it.
Does somebody have any concerns about the Devicetree property
(base-clk-frequency = < frequency >;)?
Regards,
Philipp
On 16.12.2017 10:18, Mauro Carvalho Chehab wrote:
Em Sat, 16 Dec 2017 03:49:10 +0100
Philipp Rossak <embe...@gmail.com> escreveu:
Hi Phillip,
This is not a full review of this patchset. I just want to point you
that you should keep supporting existing DT files.
This patch updates the sunxi-ir driver to set the ir base clock from
devicetree.
This is neccessary since there are different ir recievers on the
market, that operate with different frequencys. So this value needs to
be set depending on the attached receiver.
Please don't break backward compatibility with old DT files. In this
specific case, it seems simple enough to be backward-compatible.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
drivers/media/rc/sunxi-cir.c | 20 +++-
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index 97f367b446c4..55b53d6463e9 100644
--- a/drivers/media/rc/sunxi-cir.c
+++ b/drivers/media/rc/sunxi-cir.c
@@ -72,12 +72,6 @@
/* CIR_REG register idle threshold */
#define REG_CIR_ITHR(val)(((val) << 8) & (GENMASK(15, 8)))
-/* Required frequency for IR0 or IR1 clock in CIR mode */
-#define SUNXI_IR_BASE_CLK 800
-/* Frequency after IR internal divider */
-#define SUNXI_IR_CLK (SUNXI_IR_BASE_CLK / 64)
Keep those to definitions...
-/* Sample period in ns */
-#define SUNXI_IR_SAMPLE (10ul / SUNXI_IR_CLK)
/* Noise threshold in samples */
#define SUNXI_IR_RXNOISE 1
/* Idle Threshold in samples */
@@ -122,7 +116,7 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
/* for each bit in fifo */
dt = readb(ir->base + SUNXI_IR_RXFIFO_REG);
rawir.pulse = (dt & 0x80) != 0;
- rawir.duration = ((dt & 0x7f) + 1) * SUNXI_IR_SAMPLE;
+ rawir.duration = ((dt & 0x7f) + 1) *
ir->rc->rx_resolution;
ir_raw_event_store_with_filter(ir->rc, );
}
}
@@ -148,6 +142,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)
struct device_node *dn = dev->of_node;
struct resource *res;
struct sunxi_ir *ir;
+ u32 b_clk_freq;
ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL);
if (!ir)
@@ -172,6 +167,12 @@ static int sunxi_ir_probe(struct platform_device *pdev)
return PTR_ERR(ir->clk);
}
+ /* Required frequency for IR0 or IR1 clock in CIR mode */
+ if (of_property_read_u32(dn, "base-clk-frequency", _clk_freq)) {
+ dev_err(dev, "failed to get ir base clock frequency.\n");
+ return -ENODATA;
+ }
+
And here, instead of returning an error, if the property can't be read,
it means it is an older DT file. Just default to SUNXI_IR_BASE_CLK.
This will make it backward-compatible with old DT files that don't have
such property.
Regards,
Mauro
/* Reset (optional) */
ir->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
if (IS_ERR(ir->rst))
@@ -180,7 +181,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)
if (ret)
return ret;
- ret = clk_set_rate(ir->clk, SUNXI_IR_BASE_CLK);
+ ret = clk_set_rate(ir->clk, b_clk_freq);
if (ret) {
dev_err(dev, "set ir base clock failed!\n");
goto exit_reset_assert;
@@ -225,7 +226,8 @@ static int sunxi_ir_probe(struct platform_device *pdev)
ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
ir->rc->dev.parent = dev;
ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
- ir->rc->rx_resolution = SUNXI_IR_SAMPLE;
+ /* Frequency after IR internal divider with sample period in ns */
+ ir->rc->rx_resolution = (10ul / (b_clk_freq / 64));
ir->rc->timeout = MS_TO_NS(SUNXI_IR_TIMEOUT);
ir->rc->driver_name = SUNXI_IR_DEV;
Thanks,
Mauro
[RFC 4/5] ARM: dts: sun8i: a83t: Add support for the ir interface
The ir interface is like the H3 at 0x01f02000 located and is exactly
the same. This patch adds support for the ir interface on the A83T.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 5edb645b506f..5dbf2f0891c1 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -470,6 +470,16 @@
#reset-cells = <1>;
};
+ ir: ir@01f02000 {
+ compatible = "allwinner,sun5i-a13-ir";
+ clocks = <_ccu CLK_APB0_IR>, <_ccu CLK_IR>;
+ clock-names = "apb", "ir";
+ resets = <_ccu RST_APB0_IR>;
+ interrupts = ;
+ reg = <0x01f02000 0x40>;
+ status = "disabled";
+ };
+
r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun8i-a83t-r-pinctrl";
reg = <0x01f02c00 0x400>;
--
2.11.0
[RFC 5/5] ARM: dts: sun8i: a83t: bananapi-m3: Enable IR controller
The Bananapi M3 has an onboard IR receiver.
This enables the onboard IR receiver subnode.
Other than the other IR receivers this one needs a base clock frequency
of 300 Hz (3 MHz), to be able to work.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 7 +++
arch/arm/boot/dts/sun8i-a83t.dtsi| 2 +-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
index c606af3dbfed..2c92c501cd59 100644
--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
@@ -88,6 +88,13 @@
/* TODO GL830 USB-to-SATA bridge downstream w/ GPIO power controls */
};
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins_a>;
+ base-clk-frequency = <300>;
+ status = "okay";
+};
+
{
pinctrl-names = "default";
pinctrl-0 = <_pins>;
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 5dbf2f0891c1..679ce3a66b4b 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -470,7 +470,7 @@
#reset-cells = <1>;
};
- ir: ir@01f02000 {
+ ir: ir@1f02000 {
compatible = "allwinner,sun5i-a13-ir";
clocks = <_ccu CLK_APB0_IR>, <_ccu CLK_IR>;
clock-names = "apb", "ir";
--
2.11.0
[RFC 2/5] [media] dt: bindings: Update binding documentation for sunxi IR controller
This patch updates documentation for Device-Tree bindings for sunxi IR
controller and adds the new requiered property for the base clock frequency.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
Documentation/devicetree/bindings/media/sunxi-ir.txt | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt
b/Documentation/devicetree/bindings/media/sunxi-ir.txt
index 91648c569b1e..5f4960c61245 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
@@ -1,12 +1,13 @@
Device-Tree bindings for SUNXI IR controller found in sunXi SoC family
Required properties:
-- compatible : "allwinner,sun4i-a10-ir" or "allwinner,sun5i-a13-ir"
-- clocks : list of clock specifiers, corresponding to
- entries in clock-names property;
-- clock-names : should contain "apb" and "ir" entries;
-- interrupts : should contain IR IRQ number;
-- reg : should contain IO map address for IR.
+- compatible : "allwinner,sun4i-a10-ir" or "allwinner,sun5i-a13-ir"
+- clocks : list of clock specifiers, corresponding to
+ entries in clock-names property;
+- clock-names: should contain "apb" and "ir" entries;
+- interrupts : should contain IR IRQ number;
+- reg: should contain IO map address for IR.
+- base-clk-frequency : should contain the base clock frequency
Optional properties:
- linux,rc-map-name: see rc.txt file in the same directory.
@@ -21,5 +22,6 @@ ir0: ir@1c21800 {
resets = <_rst 1>;
interrupts = <0 5 1>;
reg = <0x01C21800 0x40>;
+ base-clk-frequency = <800>;
linux,rc-map-name = "rc-rc6-mce";
};
--
2.11.0
[RFC 3/5] ARM: dts: sun8i: a83t: Add the ir pin for the A83T
The CIR Pin of the A83T is located at PL12
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 19acae1b4089..5edb645b506f 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -488,6 +488,11 @@
drive-strength = <20>;
bias-pull-up;
};
+
+ ir_pins_a: ir@0 {
+ pins = "PL12";
+ function = "s_cir_rx";
+ };
};
r_rsb: rsb@1f03400 {
--
2.11.0
[RFC 1/5] [media] rc: update sunxi-ir driver to get base frequency from devicetree
This patch updates the sunxi-ir driver to set the ir base clock from
devicetree.
This is neccessary since there are different ir recievers on the
market, that operate with different frequencys. So this value needs to
be set depending on the attached receiver.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
drivers/media/rc/sunxi-cir.c | 20 +++-
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index 97f367b446c4..55b53d6463e9 100644
--- a/drivers/media/rc/sunxi-cir.c
+++ b/drivers/media/rc/sunxi-cir.c
@@ -72,12 +72,6 @@
/* CIR_REG register idle threshold */
#define REG_CIR_ITHR(val)(((val) << 8) & (GENMASK(15, 8)))
-/* Required frequency for IR0 or IR1 clock in CIR mode */
-#define SUNXI_IR_BASE_CLK 800
-/* Frequency after IR internal divider */
-#define SUNXI_IR_CLK (SUNXI_IR_BASE_CLK / 64)
-/* Sample period in ns */
-#define SUNXI_IR_SAMPLE (10ul / SUNXI_IR_CLK)
/* Noise threshold in samples */
#define SUNXI_IR_RXNOISE 1
/* Idle Threshold in samples */
@@ -122,7 +116,7 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
/* for each bit in fifo */
dt = readb(ir->base + SUNXI_IR_RXFIFO_REG);
rawir.pulse = (dt & 0x80) != 0;
- rawir.duration = ((dt & 0x7f) + 1) * SUNXI_IR_SAMPLE;
+ rawir.duration = ((dt & 0x7f) + 1) *
ir->rc->rx_resolution;
ir_raw_event_store_with_filter(ir->rc, );
}
}
@@ -148,6 +142,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)
struct device_node *dn = dev->of_node;
struct resource *res;
struct sunxi_ir *ir;
+ u32 b_clk_freq;
ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL);
if (!ir)
@@ -172,6 +167,12 @@ static int sunxi_ir_probe(struct platform_device *pdev)
return PTR_ERR(ir->clk);
}
+ /* Required frequency for IR0 or IR1 clock in CIR mode */
+ if (of_property_read_u32(dn, "base-clk-frequency", _clk_freq)) {
+ dev_err(dev, "failed to get ir base clock frequency.\n");
+ return -ENODATA;
+ }
+
/* Reset (optional) */
ir->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
if (IS_ERR(ir->rst))
@@ -180,7 +181,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)
if (ret)
return ret;
- ret = clk_set_rate(ir->clk, SUNXI_IR_BASE_CLK);
+ ret = clk_set_rate(ir->clk, b_clk_freq);
if (ret) {
dev_err(dev, "set ir base clock failed!\n");
goto exit_reset_assert;
@@ -225,7 +226,8 @@ static int sunxi_ir_probe(struct platform_device *pdev)
ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
ir->rc->dev.parent = dev;
ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
- ir->rc->rx_resolution = SUNXI_IR_SAMPLE;
+ /* Frequency after IR internal divider with sample period in ns */
+ ir->rc->rx_resolution = (10ul / (b_clk_freq / 64));
ir->rc->timeout = MS_TO_NS(SUNXI_IR_TIMEOUT);
ir->rc->driver_name = SUNXI_IR_DEV;
--
2.11.0
[RFC 0/5] IR support for A83T - sunxi-ir driver update
This patch series adds support for the sunxi A83T ir module and enhances the sunxi-ir driver. Right now the base clock frequency for the ir driver is a hard coded define and is set to 8 MHz. This works for the most common ir receivers. On the Sinovoip Bananapi M3 the ir receiver needs, a 3 MHz base clock frequency to work without problems with this driver (like in the legacy kernel). To fix this issue I reworked the driver that this value could be set over the devicetree. About 37 devices would have a devicetree change if this patch series would be applied. Therfore I would like to ask you to give me some feedback about the patch series, before I finialize it. Thanks in advance! Philipp Philipp Rossak (5): [media] rc: update sunxi-ir driver to get base frequency from devicetree [media] dt: bindings: Update binding documentation for sunxi IR controller ARM: dts: sun8i: a83t: Add the ir pin for the A83T ARM: dts: sun8i: a83t: Add support for the ir interface ARM: dts: sun8i: a83t: bananapi-m3: Enable IR controller Documentation/devicetree/bindings/media/sunxi-ir.txt | 14 -- arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 7 +++ arch/arm/boot/dts/sun8i-a83t.dtsi| 15 +++ drivers/media/rc/sunxi-cir.c | 20 +++- 4 files changed, 41 insertions(+), 15 deletions(-) -- 2.11.0
