[PATCH 1/3] ARM: OMAP: OneNAND for OMAP3
Update OneNAND support for OMAP3.
Signed-off-by: Adrian Hunter [EMAIL PROTECTED]
---
drivers/mtd/onenand/omap2.c | 588 +--
1 files changed, 404 insertions(+), 184 deletions(-)
diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index ba83900..b1f0df1 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -1,7 +1,7 @@
/*
* linux/drivers/mtd/onenand/omap2.c
*
- * OneNAND driver for OMAP2
+ * OneNAND driver for OMAP2 / OMAP3
*
* Copyright (C) 2005-2006 Nokia Corporation
*
@@ -47,7 +47,7 @@
#include asm/arch/board.h
-#define DRIVER_NAME omap2-onenand
+#define DRIVER_NAME omap2-onenand
#define ONENAND_IO_SIZE SZ_128K
#define ONENAND_BUFRAM_SIZE (1024 * 5)
@@ -67,36 +67,50 @@ struct omap2_onenand {
int (*setup)(void __iomem *base, int freq);
};
-static unsigned short omap2_onenand_readw(void __iomem *addr)
+static void omap2_onenand_dma_cb(int lch, u16 ch_status, void *data)
{
- return readw(addr);
+ struct omap2_onenand *c = data;
+
+ complete(c-dma_done);
}
-static void omap2_onenand_writew(unsigned short value, void __iomem *addr)
+static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id)
{
- writew(value, addr);
+ struct omap2_onenand *c = dev_id;
+
+ complete(c-irq_done);
+
+ return IRQ_HANDLED;
}
-static void omap2_onenand_dma_cb(int lch, u16 ch_status, void *data)
+static inline unsigned short read_reg(struct omap2_onenand *c, int reg)
{
- struct omap2_onenand *info = data;
-
- complete(info-dma_done);
+ return readw(c-onenand.base + reg);
}
-static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id)
+static inline void write_reg(struct omap2_onenand *c, unsigned short value,
+int reg)
{
- struct omap2_onenand *info = dev_id;
+ writew(value, c-onenand.base + reg);
+}
- complete(info-irq_done);
+static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int
intr)
+{
+ printk(KERN_ERR onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n,
+ msg, state, ctrl, intr);
+}
- return IRQ_HANDLED;
+static void wait_warn(char *msg, int state, unsigned int ctrl,
+ unsigned int intr)
+{
+ printk(KERN_WARNING onenand_wait: %s! state %d ctrl 0x%04x
+ intr 0x%04x\n, msg, state, ctrl, intr);
}
static int omap2_onenand_wait(struct mtd_info *mtd, int state)
{
- struct omap2_onenand *info = container_of(mtd, struct omap2_onenand,
mtd);
- unsigned int interrupt = 0;
+ struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
+ unsigned int intr = 0;
unsigned int ctrl;
unsigned long timeout;
u32 syscfg;
@@ -106,17 +120,17 @@ static int omap2_onenand_wait(struct mtd_info *mtd, int
state)
for (i = 0; i 20; i++) {
udelay(1);
- interrupt = omap2_onenand_readw(info-onenand.base +
ONENAND_REG_INTERRUPT);
- if (interrupt ONENAND_INT_MASTER)
+ intr = read_reg(c, ONENAND_REG_INTERRUPT);
+ if (intr ONENAND_INT_MASTER)
break;
}
- ctrl = omap2_onenand_readw(info-onenand.base +
ONENAND_REG_CTRL_STATUS);
+ ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
if (ctrl ONENAND_CTRL_ERROR) {
- printk(KERN_ERR onenand_wait: reset error! ctrl 0x%04x intr
0x%04x\n, ctrl, interrupt);
+ wait_err(controller error, state, ctrl, intr);
return -EIO;
}
- if (!(interrupt ONENAND_INT_RESET)) {
- printk(KERN_ERR onenand_wait: reset timeout! ctrl 0x%04x
intr 0x%04x\n, ctrl, interrupt);
+ if (!(intr ONENAND_INT_RESET)) {
+ wait_err(timeout, state, ctrl, intr);
return -EIO;
}
return 0;
@@ -124,88 +138,103 @@ static int omap2_onenand_wait(struct mtd_info *mtd, int
state)
if (state != FL_READING) {
int result;
+
/* Turn interrupts on */
- syscfg = omap2_onenand_readw(info-onenand.base +
ONENAND_REG_SYS_CFG1);
+ syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
syscfg |= ONENAND_SYS_CFG1_IOBE;
- omap2_onenand_writew(syscfg, info-onenand.base +
ONENAND_REG_SYS_CFG1);
+ write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
- INIT_COMPLETION(info-irq_done);
- if (info-gpio_irq) {
- result = omap_get_gpio_datain(info-gpio_irq);
+ INIT_COMPLETION(c-irq_done);
+ if (c-gpio_irq) {
+ result = omap_get_gpio_datain(c-gpio_irq);
if (result ==
[PATCH 2/3] ARM: OMAP: Add fields to GPMC for OMAP3
Add fields wr_access and wr_data_mux_bus.
Signed-off-by: Adrian Hunter [EMAIL PROTECTED]
---
arch/arm/mach-omap2/gpmc.c |5 +
include/asm-arm/arch-omap/gpmc.h |4
2 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 83984f7..3edcc17 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -217,6 +217,11 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings
*t)
GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
+ if (cpu_is_omap34xx()) {
+ GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
+ GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
+ }
+
/* caller is expected to have initialized CONFIG1 to cover
* at least sync vs async
*/
diff --git a/include/asm-arm/arch-omap/gpmc.h b/include/asm-arm/arch-omap/gpmc.h
index 53dc246..2aa1920 100644
--- a/include/asm-arm/arch-omap/gpmc.h
+++ b/include/asm-arm/arch-omap/gpmc.h
@@ -84,6 +84,10 @@ struct gpmc_timings {
u16 access; /* Start-cycle to first data valid delay */
u16 rd_cycle; /* Total read cycle time */
u16 wr_cycle; /* Total write cycle time */
+
+ /* The following are only on OMAP3430 */
+ u16 wr_access; /* WRACCESSTIME */
+ u16 wr_data_mux_bus;/* WRDATAONADMUXBUS */
};
extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
--
1.5.4.3
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[PATCH 3/3] ARM: OMAP: Update OneNAND support
Signed-off-by: Adrian Hunter [EMAIL PROTECTED]
---
arch/arm/mach-omap2/board-n800-flash.c | 241 +++-
include/asm-arm/arch-omap/onenand.h|3 +
include/linux/mtd/onenand_regs.h |2 +
3 files changed, 182 insertions(+), 64 deletions(-)
diff --git a/arch/arm/mach-omap2/board-n800-flash.c
b/arch/arm/mach-omap2/board-n800-flash.c
index f7403b9..fbf83b3 100644
--- a/arch/arm/mach-omap2/board-n800-flash.c
+++ b/arch/arm/mach-omap2/board-n800-flash.c
@@ -19,13 +19,12 @@
#include asm/arch/board.h
#include asm/arch/gpmc.h
-static struct mtd_partition n800_partitions[8];
+struct mtd_partition n800_partitions[ONENAND_MAX_PARTITIONS];
-static int n800_onenand_setup(void __iomem *, int freq);
+int n800_onenand_setup(void __iomem *, int freq);
static struct omap_onenand_platform_data n800_onenand_data = {
.cs = 0,
- .gpio_irq = 26,
.parts = n800_partitions,
.nr_parts = 0, /* filled later */
.onenand_setup = n800_onenand_setup,
@@ -39,6 +38,55 @@ static struct platform_device n800_onenand_device = {
},
};
+static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
+{
+ struct gpmc_timings t;
+
+ const int t_cer = 15;
+ const int t_avdp = 12;
+ const int t_aavdh = 7;
+ const int t_ce = 76;
+ const int t_aa = 76;
+ const int t_oe = 20;
+ const int t_cez = 20; /* max of t_cez, t_oez */
+ const int t_ds = 30;
+ const int t_wpl = 40;
+ const int t_wph = 30;
+
+ memset(t, 0, sizeof(t));
+ t.sync_clk = 0;
+ t.cs_on = 0;
+ t.adv_on = 0;
+
+ /* Read */
+ t.adv_rd_off = gpmc_round_ns_to_ticks(max_t(int, t_avdp, t_cer));
+ t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(t_aavdh);
+ t.access = t.adv_on + gpmc_round_ns_to_ticks(t_aa);
+ t.access = max_t(int, t.access, t.cs_on + gpmc_round_ns_to_ticks(t_ce));
+ t.access = max_t(int, t.access, t.oe_on + gpmc_round_ns_to_ticks(t_oe));
+ t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
+ t.cs_rd_off = t.oe_off;
+ t.rd_cycle = t.cs_rd_off + gpmc_round_ns_to_ticks(t_cez);
+
+ /* Write */
+ t.adv_wr_off = t.adv_rd_off;
+ t.we_on = t.oe_on;
+ if (cpu_is_omap34xx()) {
+ t.wr_data_mux_bus = t.we_on;
+ t.wr_access = t.we_on + gpmc_round_ns_to_ticks(t_ds);
+ }
+ t.we_off = t.we_on + gpmc_round_ns_to_ticks(t_wpl);
+ t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph);
+ t.wr_cycle = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez);
+
+ /* Configure GPMC for asynchronous read */
+ gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
+ GPMC_CONFIG1_DEVICESIZE_16 |
+ GPMC_CONFIG1_MUXADDDATA);
+
+ return gpmc_cs_set_timings(cs, t);
+}
+
static unsigned short omap2_onenand_readw(void __iomem *addr)
{
return readw(addr);
@@ -49,54 +97,121 @@ static void omap2_onenand_writew(unsigned short value,
void __iomem *addr)
writew(value, addr);
}
+static void set_onenand_cfg(void __iomem *onenand_base, int latency,
+ int sync_write, int hf)
+{
+ u32 reg;
+
+ reg = omap2_onenand_readw(onenand_base + ONENAND_REG_SYS_CFG1);
+ reg = ~((0x7 ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 9));
+ reg |= (latency ONENAND_SYS_CFG1_BRL_SHIFT) |
+ ONENAND_SYS_CFG1_SYNC_READ |
+ ONENAND_SYS_CFG1_BL_16;
+ if (sync_write)
+ reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
+ else
+ reg = ~ONENAND_SYS_CFG1_SYNC_WRITE;
+ if (hf)
+ reg |= ONENAND_SYS_CFG1_HF;
+ else
+ reg = ~ONENAND_SYS_CFG1_HF;
+ omap2_onenand_writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
+}
+
static int omap2_onenand_set_sync_mode(int cs, void __iomem *onenand_base,
int freq)
{
struct gpmc_timings t;
- int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_avdp, t_wpl, t_wea;
+ const int t_cer = 15;
+ const int t_avdp = 12;
+ const int t_cez = 20; /* max of t_cez, t_oez */
+ const int t_ds = 30;
+ const int t_wpl = 40;
+ const int t_wph = 30;
+ int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
- int err;
+ int err, ticks_cez, sync_write = 0, first_time = 0, hf = 0;
u32 reg;
-again:
+ if (!freq) {
+ /* Very first call freq is not known */
+ err = omap2_onenand_set_async_mode(cs, onenand_base);
+ if (err)
+ return err;
+ reg = omap2_onenand_readw(onenand_base +
+ ONENAND_REG_VERSION_ID);
+ switch ((reg 4) 0xf) {
+ case 0:
+ freq = 40;
RE: Problems with USB Gadget on the OMAP3EVM
Also increase MUSB_LOGLEVEL to 3 in your .config file and reabuild that 2.6.22.18 kernel. Don't bother re-building the kernel. You could just do an echo D3 /proc/driver/musb_hdrc or even D5 for more detail. If low-level debug is not enabled, you can echo 8 /proc/sys/kernel/printk and you should be able to see the debug prints. Those might be useful. This should work on the linux-omap kernel as well. By the way, does g_file_storage work on this board? - Anand Hello everyone, Thank you very much for the comments and suggestions. The version of Linux kernel on the native host Fedora Core 5 machine is the default 2.6.9-1.667 kernel that comes with the FC5 release. Keeping in mind where we are, this does sound like an ancient kernel. However, I have USB networking with Gadget drivers working on this same machine with OMAP5912 OSK, OMAP2430 SDP and another custom OMAP2430 based board. Nevertheless, I decided to upgrade to a more recent version of the Linux kernel on the host system. I will test the setup once again and update the observation. Meanwhile, I tested the setup with a Windows XP host machine and these are the observations: On insertion of the USB cable to the Win XP host machine, the OMAP3EVM board gets detected as 'RNDIS/Ethernet' Device. I go through the driver installation (driver used is file Documentation/usb/linux.inf from the standard Linux kernel sources). After the installation is complete, I get an error from the Windows XP system saying An error was encountered while installing the driver and the hardware might not function as intended Thank you all, Regards, Kanagesh -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] Move voltage controller configuration to pm34xx.c
On ti, 2008-08-05 at 13:55 +0300, ext Tony Lindgren wrote:
* Peter 'p2' De Schrijver [EMAIL PROTECTED] [080731 16:39]:
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/mach-omap2/smartreflex.c | 60
-
1 files changed, 0 insertions(+), 60 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex.c
b/arch/arm/mach-omap2/smartreflex.c
index b41fe96..7e4f9a4 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -362,64 +362,6 @@ static void sr_configure_vp(int srid)
}
}
-static void sr_configure_vc(void)
-{
- prm_write_mod_reg((R_SRI2C_SLAVE_ADDR OMAP3430_SMPS_SA1_SHIFT) |
- (R_SRI2C_SLAVE_ADDR OMAP3430_SMPS_SA0_SHIFT),
- OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_SA_OFFSET);
-
- prm_write_mod_reg((R_VDD2_SR_CONTROL OMAP3430_VOLRA1_SHIFT) |
- (R_VDD1_SR_CONTROL OMAP3430_VOLRA0_SHIFT),
- OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET);
-
- prm_write_mod_reg((OMAP3430_VC_CMD_VAL0_ON
- OMAP3430_VC_CMD_ON_SHIFT) |
- (OMAP3430_VC_CMD_VAL0_ONLP OMAP3430_VC_CMD_ONLP_SHIFT) |
- (OMAP3430_VC_CMD_VAL0_RET OMAP3430_VC_CMD_RET_SHIFT) |
- (OMAP3430_VC_CMD_VAL0_OFF OMAP3430_VC_CMD_OFF_SHIFT),
- OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_0_OFFSET);
-
- prm_write_mod_reg((OMAP3430_VC_CMD_VAL1_ON
- OMAP3430_VC_CMD_ON_SHIFT) |
- (OMAP3430_VC_CMD_VAL1_ONLP OMAP3430_VC_CMD_ONLP_SHIFT) |
- (OMAP3430_VC_CMD_VAL1_RET OMAP3430_VC_CMD_RET_SHIFT) |
- (OMAP3430_VC_CMD_VAL1_OFF OMAP3430_VC_CMD_OFF_SHIFT),
- OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_1_OFFSET);
-
- prm_write_mod_reg(OMAP3430_CMD1 | OMAP3430_RAV1,
- OMAP3430_GR_MOD,
- OMAP3_PRM_VC_CH_CONF_OFFSET);
-
- prm_write_mod_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN | OMAP3430_SREN,
- OMAP3430_GR_MOD,
- OMAP3_PRM_VC_I2C_CFG_OFFSET);
-
- /* Setup voltctrl and other setup times */
- /* XXX CONFIG_SYSOFFMODE has not been implemented yet */
-#ifdef CONFIG_OMAP_SYSOFFMODE
- prm_write_mod_reg(OMAP3430_AUTO_OFF | OMAP3430_AUTO_RET |
- OMAP3430_SEL_OFF, OMAP3430_GR_MOD,
- OMAP3_PRM_VOLTCTRL_OFFSET);
-
- prm_write_mod_reg(OMAP3430_CLKSETUP_DURATION, OMAP3430_GR_MOD,
- OMAP3_PRM_CLKSETUP_OFFSET);
- prm_write_mod_reg((OMAP3430_VOLTSETUP_TIME2
- OMAP3430_SETUP_TIME2_SHIFT) |
- (OMAP3430_VOLTSETUP_TIME1
- OMAP3430_SETUP_TIME1_SHIFT),
- OMAP3430_GR_MOD, OMAP3_PRM_VOLTSETUP1_OFFSET);
-
- prm_write_mod_reg(OMAP3430_VOLTOFFSET_DURATION, OMAP3430_GR_MOD,
- OMAP3_PRM_VOLTOFFSET_OFFSET);
- prm_write_mod_reg(OMAP3430_VOLTSETUP2_DURATION, OMAP3430_GR_MOD,
- OMAP3_PRM_VOLTSETUP2_OFFSET);
-#else
- prm_set_mod_reg_bits(OMAP3430_AUTO_RET, OMAP3430_GR_MOD,
- OMAP3_PRM_VOLTCTRL_OFFSET);
-#endif
-
-}
-
static void sr_configure(struct omap_sr *sr)
{
u32 sr_config;
@@ -845,8 +787,6 @@ static int __init omap3_sr_init(void)
sr_set_nvalues(sr2);
sr_configure_vp(SR2);
- sr_configure_vc();
-
/* Enable SR on T2 */
ret = twl4030_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, RdReg,
R_DCDC_GLOBAL_CFG);
This patch does not seem to move code, it just removes it. Can you do
the patches where the first patch just moves the existing code, then
the second patch adds the new changes? That way it's easier to read.
Peter is on vacation, but I have made the changes you asked. I'll send
the updated patches shortly.
Br,
Kalle
Thanks,
Tony
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Re: [PATCH 0/2] Add PM early init
Here is an update for Peter's patch-set implementing the early voltage controller initialization. Applies over l-o master branch. Boot tested on sdp board. Br, Kalle On to, 2008-07-31 at 16:37 +0300, ext Peter 'p2' De Schrijver wrote: This patchset add an early init function to initialize the voltage controller and the off mode polarity before the drivers depending on these features are enabled. Peter 'p2' De Schrijver (2): Move voltage controller configuration to pm34xx.c Add early init for voltage controller configuration and off mode polarity. arch/arm/mach-omap2/pm34xx.c | 71 + arch/arm/mach-omap2/smartreflex.c | 60 --- 2 files changed, 71 insertions(+), 60 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] Add early init for voltage controller configuration and off mode polarity.
From: ext Peter 'p2' De Schrijver [EMAIL PROTECTED]
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
Signed-off-by: Kalle Jokiniemi [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm34xx.c | 12
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index a6cfc46..fc72c11 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -484,3 +484,15 @@ static void __init configure_vc(void)
#endif
}
+
+static int __init omap3_pm_early_init(void)
+{
+ prm_clear_mod_reg_bits(OMAP3430_OFFMODE_POL, OMAP3430_GR_MOD,
+ OMAP3_PRM_POLCTRL_OFFSET);
+
+ configure_vc();
+
+ return 0;
+}
+
+arch_initcall(omap3_pm_early_init);
--
1.5.4.3
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[PATCH 1/2] Move voltage controller configuration to pm34xx.c
From: ext Peter 'p2' De Schrijver [EMAIL PROTECTED]
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
Signed-off-by: Kalle Jokiniemi [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm34xx.c | 57 +++
arch/arm/mach-omap2/smartreflex.c | 60 -
2 files changed, 57 insertions(+), 60 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 4d5f619..a6cfc46 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -427,3 +427,60 @@ err2:
}
return ret;
}
+
+static void __init configure_vc(void)
+{
+ prm_write_mod_reg((R_SRI2C_SLAVE_ADDR OMAP3430_SMPS_SA1_SHIFT) |
+ (R_SRI2C_SLAVE_ADDR OMAP3430_SMPS_SA0_SHIFT),
+ OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_SA_OFFSET);
+ prm_write_mod_reg((R_VDD2_SR_CONTROL OMAP3430_VOLRA1_SHIFT) |
+ (R_VDD1_SR_CONTROL OMAP3430_VOLRA0_SHIFT),
+ OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET);
+
+ prm_write_mod_reg((OMAP3430_VC_CMD_VAL0_ON
+ OMAP3430_VC_CMD_ON_SHIFT) |
+ (OMAP3430_VC_CMD_VAL0_ONLP OMAP3430_VC_CMD_ONLP_SHIFT) |
+ (OMAP3430_VC_CMD_VAL0_RET OMAP3430_VC_CMD_RET_SHIFT) |
+ (OMAP3430_VC_CMD_VAL0_OFF OMAP3430_VC_CMD_OFF_SHIFT),
+ OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_0_OFFSET);
+
+ prm_write_mod_reg((OMAP3430_VC_CMD_VAL1_ON
+ OMAP3430_VC_CMD_ON_SHIFT) |
+ (OMAP3430_VC_CMD_VAL1_ONLP OMAP3430_VC_CMD_ONLP_SHIFT) |
+ (OMAP3430_VC_CMD_VAL1_RET OMAP3430_VC_CMD_RET_SHIFT) |
+ (OMAP3430_VC_CMD_VAL1_OFF OMAP3430_VC_CMD_OFF_SHIFT),
+ OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_1_OFFSET);
+
+ prm_write_mod_reg(OMAP3430_CMD1 | OMAP3430_RAV1,
+ OMAP3430_GR_MOD,
+ OMAP3_PRM_VC_CH_CONF_OFFSET);
+
+ prm_write_mod_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN | OMAP3430_SREN,
+ OMAP3430_GR_MOD,
+ OMAP3_PRM_VC_I2C_CFG_OFFSET);
+
+ /* Setup voltctrl and other setup times */
+
+#ifdef CONFIG_OMAP_SYSOFFMODE
+ prm_write_mod_reg(OMAP3430_AUTO_OFF | OMAP3430_AUTO_RET |
+ OMAP3430_SEL_OFF, OMAP3430_GR_MOD,
+ OMAP3_PRM_VOLTCTRL_OFFSET);
+
+ prm_write_mod_reg(OMAP3430_CLKSETUP_DURATION, OMAP3430_GR_MOD,
+ OMAP3_PRM_CLKSETUP_OFFSET);
+ prm_write_mod_reg((OMAP3430_VOLTSETUP_TIME2
+ OMAP3430_SETUP_TIME2_SHIFT) |
+ (OMAP3430_VOLTSETUP_TIME1
+ OMAP3430_SETUP_TIME1_SHIFT),
+ OMAP3430_GR_MOD, OMAP3_PRM_VOLTSETUP1_OFFSET);
+
+ prm_write_mod_reg(OMAP3430_VOLTOFFSET_DURATION, OMAP3430_GR_MOD,
+ OMAP3_PRM_VOLTOFFSET_OFFSET);
+ prm_write_mod_reg(OMAP3430_VOLTSETUP2_DURATION, OMAP3430_GR_MOD,
+ OMAP3_PRM_VOLTSETUP2_OFFSET);
+#else
+ prm_set_mod_reg_bits(OMAP3430_AUTO_RET, OMAP3430_GR_MOD,
+ OMAP3_PRM_VOLTCTRL_OFFSET);
+#endif
+
+}
diff --git a/arch/arm/mach-omap2/smartreflex.c
b/arch/arm/mach-omap2/smartreflex.c
index f460831..5b15d18 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -364,64 +364,6 @@ static void sr_configure_vp(int srid)
}
}
-static void sr_configure_vc(void)
-{
- prm_write_mod_reg((R_SRI2C_SLAVE_ADDR OMAP3430_SMPS_SA1_SHIFT) |
- (R_SRI2C_SLAVE_ADDR OMAP3430_SMPS_SA0_SHIFT),
- OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_SA_OFFSET);
-
- prm_write_mod_reg((R_VDD2_SR_CONTROL OMAP3430_VOLRA1_SHIFT) |
- (R_VDD1_SR_CONTROL OMAP3430_VOLRA0_SHIFT),
- OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET);
-
- prm_write_mod_reg((OMAP3430_VC_CMD_VAL0_ON
- OMAP3430_VC_CMD_ON_SHIFT) |
- (OMAP3430_VC_CMD_VAL0_ONLP OMAP3430_VC_CMD_ONLP_SHIFT) |
- (OMAP3430_VC_CMD_VAL0_RET OMAP3430_VC_CMD_RET_SHIFT) |
- (OMAP3430_VC_CMD_VAL0_OFF OMAP3430_VC_CMD_OFF_SHIFT),
- OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_0_OFFSET);
-
- prm_write_mod_reg((OMAP3430_VC_CMD_VAL1_ON
- OMAP3430_VC_CMD_ON_SHIFT) |
- (OMAP3430_VC_CMD_VAL1_ONLP OMAP3430_VC_CMD_ONLP_SHIFT) |
- (OMAP3430_VC_CMD_VAL1_RET OMAP3430_VC_CMD_RET_SHIFT) |
- (OMAP3430_VC_CMD_VAL1_OFF OMAP3430_VC_CMD_OFF_SHIFT),
- OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_1_OFFSET);
-
- prm_write_mod_reg(OMAP3430_CMD1 | OMAP3430_RAV1,
- OMAP3430_GR_MOD,
- OMAP3_PRM_VC_CH_CONF_OFFSET);
-
- prm_write_mod_reg(OMAP3430_MCODE_SHIFT |
Re: [Resending - PATCH] OMAP2EVM: add LCD panel support
* arun c [EMAIL PROTECTED] [080806 08:15]:
omap2evm LCD supports VGA and QVGA resolution, by default its in VGA mode.
Thanks, pushing today.
Tony
Signed-off-by: Arun C [EMAIL PROTECTED]
---
arch/arm/mach-omap2/board-omap2evm.c | 15 +++-
drivers/video/omap/Makefile |2 +
drivers/video/omap/lcd_omap2evm.c| 195
++
3 files changed, 210 insertions(+), 2 deletions(-)
create mode 100644 drivers/video/omap/lcd_omap2evm.c
diff --git a/arch/arm/mach-omap2/board-omap2evm.c
b/arch/arm/mach-omap2/board-omap2evm.c
index 0baf704..13c53cc 100644
--- a/arch/arm/mach-omap2/board-omap2evm.c
+++ b/arch/arm/mach-omap2/board-omap2evm.c
@@ -62,6 +62,15 @@ static inline void __init omap2evm_init_smc911x(void)
}
+static struct platform_device omap2_evm_lcd_device = {
+ .name = omap2evm_lcd,
+ .id = -1,
+};
+
+static struct omap_lcd_config omap2_evm_lcd_config __initdata = {
+ .ctrl_name = internal,
+};
+
static void __init omap2_evm_init_irq(void)
{
omap2_init_common_hw(NULL);
@@ -75,7 +84,8 @@ static struct omap_uart_config omap2_evm_uart_config
__initdata = {
};
static struct omap_board_config_kernel omap2_evm_config[] __initdata = {
- {OMAP_TAG_UART, omap2_evm_uart_config},
+ { OMAP_TAG_UART,omap2_evm_uart_config },
+ { OMAP_TAG_LCD, omap2_evm_lcd_config },
};
static int __init omap2_evm_i2c_init(void)
@@ -90,7 +100,8 @@ static int __init omap2_evm_i2c_init(void)
}
static struct platform_device *omap2_evm_devices[] __initdata = {
-omap2evm_smc911x_device,
+ omap2_evm_lcd_device,
+ omap2evm_smc911x_device,
};
static void __init omap2_evm_init(void)
diff --git a/drivers/video/omap/Makefile b/drivers/video/omap/Makefile
index fe7ee5d..662dff9 100644
--- a/drivers/video/omap/Makefile
+++ b/drivers/video/omap/Makefile
@@ -31,6 +31,8 @@ objs-y$(CONFIG_MACH_SX1) += lcd_sx1.o
objs-y$(CONFIG_MACH_OMAP_APOLLON) += lcd_apollon.o
objs-y$(CONFIG_MACH_OMAP_2430SDP) += lcd_2430sdp.o
objs-y$(CONFIG_MACH_OMAP_3430SDP) += lcd_2430sdp.o
+objs-y$(CONFIG_MACH_OMAP2EVM) += lcd_omap2evm.o
+objs-y$(CONFIG_MACH_OMAP_3430SDP) += lcd_3430sdp.o
objs-y$(CONFIG_MACH_OMAP3EVM) += lcd_omap3evm.o
objs-y$(CONFIG_MACH_OMAP3_BEAGLE) += lcd_omap3beagle.o
objs-y$(CONFIG_FB_OMAP_LCD_MIPID) += lcd_mipid.o
diff --git a/drivers/video/omap/lcd_omap2evm.c
b/drivers/video/omap/lcd_omap2evm.c
new file mode 100644
index 000..8311cac
--- /dev/null
+++ b/drivers/video/omap/lcd_omap2evm.c
@@ -0,0 +1,195 @@
+/*
+ * LCD panel support for the MISTRAL OMAP2EVM board
+ *
+ * Author: Arun C [EMAIL PROTECTED]
+ *
+ * Derived from drivers/video/omap/lcd_omap3evm.c
+ * Derived from drivers/video/omap/lcd-apollon.c
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/i2c/twl4030.h
+
+#include asm/arch/gpio.h
+#include asm/arch/mux.h
+#include asm/arch/omapfb.h
+#include asm/mach-types.h
+
+#define LCD_PANEL_ENABLE_GPIO154
+#define LCD_PANEL_LR 128
+#define LCD_PANEL_UD 129
+#define LCD_PANEL_INI152
+#define LCD_PANEL_QVGA 148
+#define LCD_PANEL_RESB 153
+
+#define LCD_XRES 480
+#define LCD_YRES 640
+#define LCD_PIXCLOCK_MAX 2 /* in kHz */
+
+#define TWL_LED_LEDEN0x00
+#define TWL_PWMA_PWMAON 0x00
+#define TWL_PWMA_PWMAOFF 0x01
+
+static unsigned int bklight_level;
+
+static int omap2evm_panel_init(struct lcd_panel *panel,
+ struct omapfb_device *fbdev)
+{
+ omap_request_gpio(LCD_PANEL_ENABLE_GPIO);
+ omap_request_gpio(LCD_PANEL_LR);
+ omap_request_gpio(LCD_PANEL_UD);
+ omap_request_gpio(LCD_PANEL_INI);
+ omap_request_gpio(LCD_PANEL_QVGA);
+ omap_request_gpio(LCD_PANEL_RESB);
+
+ omap_set_gpio_direction(LCD_PANEL_ENABLE_GPIO, 0);
+ omap_set_gpio_direction(LCD_PANEL_LR, 0);
+ omap_set_gpio_direction(LCD_PANEL_UD, 0);
+ omap_set_gpio_direction(LCD_PANEL_INI, 0);
+ omap_set_gpio_direction(LCD_PANEL_QVGA, 0);
+
Re: [PATCH] Added support for OMAP35x processor series
* Kridner, Jason [EMAIL PROTECTED] [080805 17:12]:
No, ROM CRC is useful for detecting between some device revisions, but not
OMAp3430 vs OMAP3530.
- Original Message -
From: Koen Kooi [EMAIL PROTECTED]
To: linux-omap@vger.kernel.org linux-omap@vger.kernel.org
Cc: Kridner, Jason
Sent: Tue Aug 05 05:10:40 2008
Subject: Re: [PATCH] Added support for OMAP35x processor series
Op 5 aug 2008, om 11:50 heeft Igor Stoppa het volgende geschreven:
On Tue, 2008-08-05 at 15:09 +0530, ext Premi, Sanjeev wrote:
This patch is needed to ensure that we can make decisions based on
the processor capabilities.
E.g. OMAP3503 does not contain a DSP. We shouldn't be trying to
disable/ manage the clocks for
DSP on this processor. Same for SGX.
Why can't the detection happen at runtime?
AIUI the ID bits are the same (linux misdetect the 3530 on my beagle
for a 3430). I heard that the only definitive way to do it at runtime
is to CRC check the ROM code.
Jason, is that correct?
Well if there's no way to detect certain omaps during runtime, please
patch arch/arm/plat-omap/common.c to have something like struct
omap_globals omap3503_globals.
BTW, why can't the dsp code detect if the DSP is there or not?
Tony
regards,
Koen
Enabling NEON is support iby default is just based on the number of
requests I have been getting
from various users.
Huh?
--
Cheers, Igor
---
Igor Stoppa
Maemo Software - Nokia Devices RD - Helsinki
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Re: Problems with USB Gadget on the OMAP3EVM
On Wed, Aug 06, 2008 at 01:27:40PM +0530, ext Gadiyar, Anand wrote: Also increase MUSB_LOGLEVEL to 3 in your .config file and reabuild that 2.6.22.18 kernel. Don't bother re-building the kernel. You could just do an echo D3 /proc/driver/musb_hdrc or even D5 for more detail. If low-level debug is not enabled, you can echo 8 /proc/sys/kernel/printk and you should be able to see the debug prints. Those might be useful. This should work on the linux-omap kernel as well. By the way, does g_file_storage work on this board? Didn't know you guys had that on your tree as well. Good to know :-) -- balbi -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM MMU: add strongly-ordered memory type
On Mon, 2008-08-04 at 17:40 -0600, Paul Walmsley wrote:
Add the MT_MEMORY_STRONGLY_ORDERED memory type for ARM strongly ordered
memory.
This is used on OMAP3 for on-board SRAM. On OMAP, SRAM is used for code
that changes the SDRAM controller's clock, temporarily blocking access to
SDRAM. During this period, as code executes from SRAM, the ARM cache
controller can attempt to write dirty cache lines back to SDRAM to make
room for SRAM cache lines, causing the MPU subsystem to hang. To avoid
this, we mark SRAM as strongly- ordered memory.
Why not use normal uncached memory? Strongly ordered is pretty
inefficient as it cannot do any reordering or write buffer merging (it's
like having a memory barrier before and after each instruction).
Speculative accesses are not allowed either. Strongly ordered memory is
not really meant for executing code from.
+ [MT_MEMORY_STRONGLY_ORDERED] = {
+ .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE |
+ PMD_SECT_UNCACHED,
You can add PMD_SECT_TEX(1) for normal uncached memory.
--
Catalin
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RE: [PATCH] Added support for OMAP35x processor series
Well if there's no way to detect certain omaps during runtime, please patch arch/arm/plat-omap/common.c to have something like struct omap_globals omap3503_globals. There was no need to re-define these structures for the current series of the OMAP35x processors. Hence, it was left as it. BTW, why can't the dsp code detect if the DSP is there or not? (Assuming you mean the code running on ARM that looks for the DSP/SGX/...) The detection was based on the chip ID. This happens to be same for OMAP34XX and OMAP35X. ~sanjeev -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Tony Lindgren Sent: Wednesday, August 06, 2008 2:37 PM To: Kridner, Jason Cc: '[EMAIL PROTECTED]'; 'linux-omap@vger.kernel.org' Subject: Re: [PATCH] Added support for OMAP35x processor series * Kridner, Jason [EMAIL PROTECTED] [080805 17:12]: No, ROM CRC is useful for detecting between some device revisions, but not OMAp3430 vs OMAP3530. - Original Message - From: Koen Kooi [EMAIL PROTECTED] To: linux-omap@vger.kernel.org linux-omap@vger.kernel.org Cc: Kridner, Jason Sent: Tue Aug 05 05:10:40 2008 Subject: Re: [PATCH] Added support for OMAP35x processor series Op 5 aug 2008, om 11:50 heeft Igor Stoppa het volgende geschreven: On Tue, 2008-08-05 at 15:09 +0530, ext Premi, Sanjeev wrote: This patch is needed to ensure that we can make decisions based on the processor capabilities. E.g. OMAP3503 does not contain a DSP. We shouldn't be trying to disable/ manage the clocks for DSP on this processor. Same for SGX. Why can't the detection happen at runtime? AIUI the ID bits are the same (linux misdetect the 3530 on my beagle for a 3430). I heard that the only definitive way to do it at runtime is to CRC check the ROM code. Jason, is that correct? Well if there's no way to detect certain omaps during runtime, please patch arch/arm/plat-omap/common.c to have something like struct omap_globals omap3503_globals. BTW, why can't the dsp code detect if the DSP is there or not? Tony To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH] ARM MMU: add strongly-ordered memory type
On Tue, 2008-08-05 at 07:15 -0500, Woodruff, Richard wrote: Is the controller allowed to write dirty cache lines out at any time it likes? Surely a better fix is to drain the cache of the changes before changing the clock for the SDRAM? - Previously the SRAM was marked as cached. _Execution_ using that attribute will generate line fetches to SRAM. This will cause displacement write-outs of resident DDR lines. Similarly, _load/store_ sequences in that code have the same effect. This cast outs dead lock the CPU and it can't fetch to progress. [...] * Flushing the entire L1 L2 cache frequently is very expensive and better not done if you don't have. Also, it is not sufficient for the context-restore path which needs to NOT live in DDR. The code need to execute in a non-cached region. I don't think there is any guarantee that dirty cache line won't be evicted to SDRAM even if your code uses uncached memory only. The CPU is allowed to do speculative reads from the normal cached memory and these reads may force a dirty cache line to be written back to memory. You may need to do at least a cache clean operation (invalidate not necessary). -- Catalin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] Added support for OMAP35x processor series
* Premi, Sanjeev [EMAIL PROTECTED] [080806 12:55]: Well if there's no way to detect certain omaps during runtime, please patch arch/arm/plat-omap/common.c to have something like struct omap_globals omap3503_globals. There was no need to re-define these structures for the current series of the OMAP35x processors. Hence, it was left as it. What exactly do you need to define then for various 35xx processors that's different from 34xx? BTW, why can't the dsp code detect if the DSP is there or not? (Assuming you mean the code running on ARM that looks for the DSP/SGX/...) The detection was based on the chip ID. This happens to be same for OMAP34XX and OMAP35X. How about trying to read the DSP revision register or something similar? Tony ~sanjeev -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Tony Lindgren Sent: Wednesday, August 06, 2008 2:37 PM To: Kridner, Jason Cc: '[EMAIL PROTECTED]'; 'linux-omap@vger.kernel.org' Subject: Re: [PATCH] Added support for OMAP35x processor series * Kridner, Jason [EMAIL PROTECTED] [080805 17:12]: No, ROM CRC is useful for detecting between some device revisions, but not OMAp3430 vs OMAP3530. - Original Message - From: Koen Kooi [EMAIL PROTECTED] To: linux-omap@vger.kernel.org linux-omap@vger.kernel.org Cc: Kridner, Jason Sent: Tue Aug 05 05:10:40 2008 Subject: Re: [PATCH] Added support for OMAP35x processor series Op 5 aug 2008, om 11:50 heeft Igor Stoppa het volgende geschreven: On Tue, 2008-08-05 at 15:09 +0530, ext Premi, Sanjeev wrote: This patch is needed to ensure that we can make decisions based on the processor capabilities. E.g. OMAP3503 does not contain a DSP. We shouldn't be trying to disable/ manage the clocks for DSP on this processor. Same for SGX. Why can't the detection happen at runtime? AIUI the ID bits are the same (linux misdetect the 3530 on my beagle for a 3430). I heard that the only definitive way to do it at runtime is to CRC check the ROM code. Jason, is that correct? Well if there's no way to detect certain omaps during runtime, please patch arch/arm/plat-omap/common.c to have something like struct omap_globals omap3503_globals. BTW, why can't the dsp code detect if the DSP is there or not? Tony To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH RFC] MUSB: Fix index register corruption seen with g_ether and Windows host
On Tue, Aug 05, 2008 at 09:18:14PM +0530, ext Gadiyar, Anand wrote: If Indexed Mode register accesses are enabled, the ep0_rxstate() function calls musb_g_ep0_giveback() before writing to the CSR register. When control returns to this ep0_rxstate, the index register contents are over-written. This causes the CSR register write to fail. Fixed by writing the correct value into the index register before writing to the CSR. This was observed only in ep0_rxstate() with g_ether loaded and the device connected to a MS Windows host PC. Anticipatively fixed ep0_txstate() as well. Hi, can you mail me (only) this patch as an attachement or put it somewhere i can download ? -- balbi -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH RFC] MUSB: Fix index register corruption seen with g_ether and Windows host
On Wed, Aug 06, 2008 at 01:47:33PM +0300, Felipe Balbi wrote: Hi, can you mail me (only) this patch as an attachement or put it somewhere i can download ? eheh, forget it, did it by hand :-p -- balbi -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] Enable SYSOFFMODE use
On ti, 2008-08-05 at 13:50 +0300, ext Tony Lindgren wrote: * Peter 'p2' De Schrijver [EMAIL PROTECTED] [080721 19:03]: Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED] --- arch/arm/mach-omap2/smartreflex.c | 10 +- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c index 0f3a659..b41fe96 100644 --- a/arch/arm/mach-omap2/smartreflex.c +++ b/arch/arm/mach-omap2/smartreflex.c @@ -396,17 +396,17 @@ static void sr_configure_vc(void) /* Setup voltctrl and other setup times */ /* XXX CONFIG_SYSOFFMODE has not been implemented yet */ -#ifdef CONFIG_SYSOFFMODE - prm_write_mod_reg(OMAP3430_AUTO_OFF | OMAP3430_AUTO_RET, - OMAP3430_GR_MOD, +#ifdef CONFIG_OMAP_SYSOFFMODE + prm_write_mod_reg(OMAP3430_AUTO_OFF | OMAP3430_AUTO_RET | + OMAP3430_SEL_OFF, OMAP3430_GR_MOD, OMAP3_PRM_VOLTCTRL_OFFSET); prm_write_mod_reg(OMAP3430_CLKSETUP_DURATION, OMAP3430_GR_MOD, OMAP3_PRM_CLKSETUP_OFFSET); prm_write_mod_reg((OMAP3430_VOLTSETUP_TIME2 - OMAP3430_VOLTSETUP_TIME2_OFFSET) | + OMAP3430_SETUP_TIME2_SHIFT) | (OMAP3430_VOLTSETUP_TIME1 - OMAP3430_VOLTSETUP_TIME1_OFFSET), + OMAP3430_SETUP_TIME1_SHIFT), OMAP3430_GR_MOD, OMAP3_PRM_VOLTSETUP1_OFFSET); prm_write_mod_reg(OMAP3430_VOLTOFFSET_DURATION, OMAP3430_GR_MOD, Do we need the CONFIG_SYSOFFMODE option? How about just add /sys/power/off_while_idle and if that's set to 1 then allow off mode? I would say no, we don't need the CONFIG_SYSOFFMODE option. I think we can always use 0 volt sys off mode for suspend, since it's user activated and the wake-up latency is still in range of only few ms. Dynamic idle is bit different, because the system would have to be idle a lot longer for the 0V off mode to pay off (when comparing to sleep voltage off mode). We could have an extra C-state in the upcoming cpu-idle driver for 0 volt off-mode. Richard, Rajendra, any thoughts? If that's not feasible, the off_while_idle sysfs interface can be created. Br, Kalle Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH] ARM MMU: add strongly-ordered memory type
Why not use normal uncached memory? Strongly ordered is pretty inefficient as it cannot do any reordering or write buffer merging (it's like having a memory barrier before and after each instruction). Speculative accesses are not allowed either. Strongly ordered memory is not really meant for executing code from. It could be. This is a discussion we were having off line. The code in question is a small bit of assembly interacting with hardware mainly and has not been audited for full pipeline/buffering correctness. Most of the weak memory attributes in newer ARMs are not exploited today in tree. I'll guess this was more a correctness and capability judgment from Russell. Regards, Richard W. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/4] 34XX: PM: Workaround for taking care of gpio clocks
In omap3 gpios 2-6 are in per domain. Functional clocks for these
should be disabled. This patch is needed until gpio driver disables
gpio clocks.
GPIO modules in PER domain are not able to act as a wake up source if
PER domain is in retention. PER domain sleep transition before MPU is
prevented by leaving icks active. PER domain still enters retention
together with MPU. When this happens IOPAD wake up mechanism is used
for gpios.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm34xx.c | 58 ---
1 files changed, 55 insertions(+), 3 deletions(-)
Index: linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c
===
--- linux-omap-2.6.orig/arch/arm/mach-omap2/pm34xx.c2008-08-06
18:07:34.0 +0530
+++ linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c 2008-08-06 18:07:49.0
+0530
@@ -47,12 +47,42 @@ struct power_state {
static LIST_HEAD(pwrst_list);
-static void (*_omap_sram_idle)(u32 *addr, int save_state);
+void (*_omap_sram_idle)(u32 *addr, int save_state, int disable_clocks);
static void (*saved_idle)(void);
static struct powerdomain *mpu_pwrdm;
+/* XXX This is for gpio fclk hack. Will be removed as gpio driver
+ * handles fcks correctly */
+#define NUM_OF_PERGPIOS 5
+static struct clk *gpio_fcks[NUM_OF_PERGPIOS];
+
+/* XXX This is for gpio fclk hack. Will be removed as gpio driver
+ * handles fcks correctly */
+static void per_gpio_clk_enable(void)
+{
+ int i;
+ for (i = 1; i NUM_OF_PERGPIOS + 1; i++)
+ clk_enable(gpio_fcks[i-1]);
+}
+
+/* XXX This is for gpio fclk hack. Will be removed as gpio driver
+ * handles fcks correctly */
+static void per_gpio_clk_disable(void)
+{
+ int i;
+ for (i = 1; i NUM_OF_PERGPIOS + 1; i++)
+ clk_disable(gpio_fcks[i-1]);
+}
+
+/* XXX This is for gpio fclk hack. Will be removed as gpio driver
+ * handles fcks correctly */
+static void gpio_fclk_mask(u32 *fclk)
+{
+ *fclk = ~(0x1f 13);
+}
+
/* PRCM Interrupt Handler for wakeups */
static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
{
@@ -169,7 +199,17 @@ static void omap_sram_idle(void)
omap2_gpio_prepare_for_retention();
- _omap_sram_idle(NULL, save_state);
+ /* XXX This is for gpio fclk hack. Will be removed as gpio driver
+* handles fcks correctly */
+ if (clocks_off_while_idle)
+ per_gpio_clk_disable();
+
+ _omap_sram_idle(NULL, save_state, clocks_off_while_idle);
+
+ /* XXX This is for gpio fclk hack. Will be removed as gpio driver
+* handles fcks correctly */
+ if (clocks_off_while_idle)
+ per_gpio_clk_enable();
omap2_gpio_resume_after_retention();
}
@@ -197,6 +237,10 @@ static int omap3_fclks_active(void)
CM_FCLKEN);
fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
CM_FCLKEN);
+
+ if (clocks_off_while_idle)
+ gpio_fclk_mask(fck_per);
+
if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
fck_cam | fck_per | fck_usbhost)
return 1;
@@ -412,7 +456,8 @@ static int __init pwrdms_setup(struct po
int __init omap3_pm_init(void)
{
struct power_state *pwrst;
- int ret;
+ char clk_name[11];
+ int ret, i;
printk(KERN_ERR Power Management for TI OMAP3.\n);
@@ -448,6 +493,13 @@ int __init omap3_pm_init(void)
pm_idle = omap3_pm_idle;
+ /* XXX This is for gpio fclk hack. Will be removed as gpio driver
+* handles fcks correctly */
+ for (i = 1; i NUM_OF_PERGPIOS + 1; i++) {
+ sprintf(clk_name, gpio%d_fck, i + 1);
+ gpio_fcks[i-1] = clk_get(NULL, clk_name);
+ }
+
err1:
return ret;
err2:
--
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[PATCH 3/4] Added sleep support to UART
From: Tero Kristo [EMAIL PROTECTED]
UART usage (e.g. serial console) now denies sleep for 5 seconds. This
makes it possible to use serial console when dynamic idle is
enabled. Write 1 to /sys/power/clocks_off_while_sleep to enable uart
clock disable on idle. Without this omap won't enter retention.
Also moved code from pm-debug.c to serial.c, and made pm24xx.c use
this new implementation.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm-debug.c | 132 -
arch/arm/mach-omap2/pm.h |8 --
arch/arm/mach-omap2/pm24xx.c | 53 -
arch/arm/mach-omap2/pm34xx.c | 26 --
arch/arm/mach-omap2/serial.c | 148 +
include/asm-arm/arch-omap/common.h |3
6 files changed, 202 insertions(+), 168 deletions(-)
Index: linux-omap-2.6/arch/arm/mach-omap2/pm-debug.c
===
--- linux-omap-2.6.orig/arch/arm/mach-omap2/pm-debug.c 2008-08-06
18:07:31.0 +0530
+++ linux-omap-2.6/arch/arm/mach-omap2/pm-debug.c 2008-08-06
18:08:02.0
+0530
@@ -37,138 +37,6 @@
#ifdef CONFIG_PM_DEBUG
int omap2_pm_debug = 0;
-static int serial_console_clock_disabled;
-static int serial_console_uart;
-static unsigned int serial_console_next_disable;
-
-static struct clk *console_iclk, *console_fclk;
-
-static void serial_console_kick(void)
-{
- serial_console_next_disable = omap2_read_32k_sync_counter();
- /* Keep the clocks on for 4 secs */
- serial_console_next_disable += 4 * 32768;
-}
-
-static void serial_wait_tx(void)
-{
- static const unsigned long uart_bases[3] = {
- 0x4806a000, 0x4806c000, 0x4806e000
- };
- unsigned long lsr_reg;
- int looped = 0;
-
- /* Wait for TX FIFO and THR to get empty */
- lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 2));
- while ((__raw_readb(lsr_reg) 0x60) != 0x60)
- looped = 1;
- if (looped)
- serial_console_kick();
-}
-
-u32 omap2_read_32k_sync_counter(void)
-{
-return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010);
-}
-
-void serial_console_fclk_mask(u32 *f1, u32 *f2)
-{
- switch (serial_console_uart) {
- case 1:
- *f1 = ~(1 21);
- break;
- case 2:
- *f1 = ~(1 22);
- break;
- case 3:
- *f2 = ~(1 2);
- break;
- }
-}
-
-void serial_console_sleep(int enable)
-{
- if (console_iclk == NULL || console_fclk == NULL)
- return;
-
- if (enable) {
- BUG_ON(serial_console_clock_disabled);
- if (clk_get_usecount(console_fclk) == 0)
- return;
- if ((int) serial_console_next_disable - (int)
omap2_read_32k_sync_counter()
= 0)
- return;
- serial_wait_tx();
- clk_disable(console_iclk);
- clk_disable(console_fclk);
- serial_console_clock_disabled = 1;
- } else {
- int serial_wakeup = 0;
- u32 l;
-
- switch (serial_console_uart) {
- case 1:
- l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
- if (l OMAP24XX_ST_UART1)
- serial_wakeup = 1;
- break;
- case 2:
- l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
- if (l OMAP24XX_ST_UART2)
- serial_wakeup = 1;
- break;
- case 3:
- l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKST2);
- if (l OMAP24XX_ST_UART3)
- serial_wakeup = 1;
- break;
- }
- if (serial_wakeup)
- serial_console_kick();
- if (!serial_console_clock_disabled)
- return;
- clk_enable(console_iclk);
- clk_enable(console_fclk);
- serial_console_clock_disabled = 0;
- }
-}
-
-void pm_init_serial_console(void)
-{
- const struct omap_serial_console_config *conf;
- char name[16];
-
- conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
- struct omap_serial_console_config);
- if (conf == NULL)
- return;
- if (conf-console_uart 3 || conf-console_uart 1)
- return;
- serial_console_uart = conf-console_uart;
- sprintf(name, uart%d_fck, conf-console_uart);
- console_fclk = clk_get(NULL, name);
- if (IS_ERR(console_fclk))
- console_fclk = NULL;
- name[6] = 'i';
- console_iclk = clk_get(NULL, name);
- if (IS_ERR(console_fclk))
- console_iclk = NULL;
- if
RE: Problems with USB Gadget on the OMAP3EVM
Kanagesh, You can give it a shot using a different cable - I have seen similar issues when using a faulty cable. Regards, Pratheesh -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Gupta, Ajay Kumar Sent: Wednesday, August 06, 2008 6:12 PM To: kanagesh radhakrishnan Cc: linux-omap@vger.kernel.org Subject: RE: Problems with USB Gadget on the OMAP3EVM Kanagesh, I tested it with Windows XP machine and it works all fine. I had to use linux.inf file which is at Documetation\usb\ folder. linux.inf file should have same VID/PID as reported by gadget rndis driver to host. Regards, Ajay -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of kanagesh radhakrishnan Sent: Wednesday, August 06, 2008 10:43 AM To: [EMAIL PROTECTED] Cc: linux-omap@vger.kernel.org Subject: Re: Problems with USB Gadget on the OMAP3EVM On 8/5/08, Felipe Balbi [EMAIL PROTECTED] wrote: Hi, On Tue, Aug 05, 2008 at 04:47:02PM +0530, ext kanagesh radhakrishnan wrote: Running the Test - On the OMAP3EVM Target ### On successful boot with this kernel on the target board, after plugging in the USB cable, the following messages appear on the console: musb_stage2_irq 863: SUSPEND (b_idle) devctl 99 power e0 musb_stage0_irq 722: BUS RESET musb_stage0_irq 722: BUS RESET musb_stage0_irq 722: BUS RESET musb_stage0_irq 722: BUS RESET musb_stage0_irq 722: BUS RESET musb_stage0_irq 722: BUS RESET musb_stage0_irq 722: BUS RESET musb_stage0_irq 722: BUS RESET usb0: high speed config #2: 100 mA, Ethernet Gadget, using RNDIS musb_stage0_irq 722: BUS RESET musb_stage0_irq 722: BUS RESET musb_stage2_irq 863: SUSPEND (b_peripheral) devctl 99 power f0 I then setup an IP address for the usb0 interface with the following command: [EMAIL PROTECTED] /]# /sbin/ifconfig usb0 192.168.1.1 up netmask 255.255.255.0 On the Linux Host machine ### On insertion of the USB cable, 'dmesg' shows the following messages: usb 1-2: new high speed USB device using address 3 usb 1-2: configuration #1 chosen from 2 choices usb 1-2: can't set config #1, error -71 That's weird since gadget api set config 2 as your dmesg states. usb0: high speed config #2: 100 mA, Ethernet Gadget, using RNDIS The Problem --- On an attempt to setup an IP address for the usb0 interface, I get the following error: usb0: unknown interface: No such device SIOCSIFADDR: No such device usb0: unknown interface: No such device SIOCSIFNETMASK: No such device SIOCGIFADDR: No such device SIOCSIFBROADCAST: No such device Looks like the problem is in the host side usbnet.ko. What kernel version is in your host machine ? The Test Setup -- Host Linux machine running Fedora Core 5. Manually loaded the module usbnet.ko. Which kernel version is in this fedora core 5 ?? Target # OMAP3EVM running OMAP35x_SDK_0.9.8 firmware: x-load, u-boot and kernel (linux-2.6.22.18) Dip switches (SW4) set to boot from NAND flash (0101) Although my end objective is to test the USB functionality with TWL4030 USB transceiver, I wanted to verify if USB functions as expected through ISP1504 transceiver on my board with the SDK_0.9.8. Has anyone tested the USB Gadget setup on the OMAP3EVM boards? I'd strongly suggest you to try out current linux-omap code [1] and check if it works fine. Also increase MUSB_LOGLEVEL to 3 in your .config file and reabuild that 2.6.22.18 kernel. When you clone linux omap with: $ git clone http://www.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6.git You can make omap3_evm_defconfig and later make menuconfig to choose the gadget driver you want. [1] http://git.kernel.org/?p=linux/kernel/git/tmlind/linux-omap-2.6.git;a=summary -- balbi Hello everyone, Thank you very much for the comments and suggestions. The version of Linux kernel on the native host Fedora Core 5 machine is the default 2.6.9-1.667 kernel that comes with the FC5 release. Keeping in mind where we are, this does sound like an ancient kernel. However, I have USB networking with Gadget drivers working on this same machine with OMAP5912 OSK, OMAP2430 SDP and another custom OMAP2430 based board. Nevertheless, I decided to upgrade to a more recent version of the Linux kernel on the host system. I will test the setup once again and update the observation. Meanwhile, I tested the setup with a Windows XP host machine and these are the observations: On insertion of the USB cable to the Win XP host machine, the OMAP3EVM board gets detected as 'RNDIS/Ethernet' Device. I go through the driver installation (driver used is file Documentation/usb/linux.inf from the standard Linux kernel sources).
[PATCH 00/11] OMAP3 CPUidle patches - ver 2
Hi, Re-posting a refreshed version of these patches. regards Rajendra Hi, I am sending an updated patch set for CPUidle which includes all fixes/comments posted on the previous set by Jouni/Richard W/Peter and others. The Following are the fixes 1) Uart clock enable/disable moved out of the context save/restore patch 2) GPIO IRQENABLE save/restore fix from Richard 3) Fixes from Jouni which do the following 1. Add wkdep between neon and mpu 2. Add wkdep between per and core 3. Deny hwsup mode before writing next pwrst state 4. Make sure that order in idle loop is such that clocks are _really_ enabled before accessing registers (serial gpio). 4) Safe state idle fix from Richard 5) Uart smart-force fix from Richard 6) Toggle IO-PAD enable/disable in idle As earlier these patches apply on top of Jouni's workaround patch set ([PATCH 0/6] 34XX: PM: Workarounds to get omap3 to retention 4th.) The following is neccessay even with a minimal config to achieve OFF. $ echo 1 /sys/power/sleep_while_idle $ echo 1 /sys/power/clocks_off_while_idle regards, Rajendra -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 02/11] per/neon and core handling in idle
This patches adds handling of PER/NEON and CORE domain in idle.
Signed-off-by: Rajendra Nayak [EMAIL PROTECTED]
---
arch/arm/mach-omap2/cpuidle34xx.c | 98 +++---
arch/arm/mach-omap2/cpuidle34xx.h |6 +-
arch/arm/mach-omap2/pm34xx.c | 58 ++
3 files changed, 121 insertions(+), 41 deletions(-)
Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c
===
--- linux-omap-2.6.orig/arch/arm/mach-omap2/cpuidle34xx.c 2008-08-06
18:09:32.0 +0530
+++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c2008-08-06
18:09:48.0 +0530
@@ -26,6 +26,8 @@
#include asm/arch/pm.h
#include asm/arch/prcm.h
#include asm/arch/powerdomain.h
+#include asm/arch/clockdomain.h
+#include asm/arch/gpio.h
#include cpuidle34xx.h
#ifdef CONFIG_CPU_IDLE
@@ -35,6 +37,8 @@ struct omap3_processor_cx current_cx_sta
static int omap3_idle_bm_check(void)
{
+ if (!omap3_can_sleep())
+ return 1;
return 0;
}
@@ -46,34 +50,86 @@ static int omap3_enter_idle(struct cpuid
{
struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
struct timespec ts_preidle, ts_postidle, ts_idle;
- struct powerdomain *mpu_pd;
+ struct powerdomain *mpu_pd, *core_pd, *per_pd, *neon_pd;
+ int per_pwrst, neon_pwrst;
current_cx_state = *cx;
- /* Used to keep track of the total time in idle */
- getnstimeofday(ts_preidle);
-
-
if (cx-type == OMAP3_STATE_C0) {
/* Do nothing for C0, not even a wfi */
return 0;
}
+ /* Used to keep track of the total time in idle */
+ getnstimeofday(ts_preidle);
+
mpu_pd = pwrdm_lookup(mpu_pwrdm);
+ core_pd = pwrdm_lookup(core_pwrdm);
+ per_pd = pwrdm_lookup(per_pwrdm);
+ neon_pd = pwrdm_lookup(neon_pwrdm);
+
+ /* Reset previous power state registers */
+ pwrdm_clear_all_prev_pwrst(mpu_pd);
+ pwrdm_clear_all_prev_pwrst(neon_pd);
+ pwrdm_clear_all_prev_pwrst(core_pd);
+ pwrdm_clear_all_prev_pwrst(per_pd);
+
+ if (omap_irq_pending())
+ return 0;
+
+ per_pwrst = pwrdm_read_pwrst(per_pd);
+ neon_pwrst = pwrdm_read_pwrst(neon_pd);
+
/* Program MPU to target state */
- if (cx-mpu_state PWRDM_POWER_ON)
+ if (cx-mpu_state PWRDM_POWER_ON) {
+ if (neon_pwrst == PWRDM_POWER_ON)
+ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_RET);
pwrdm_set_next_pwrst(mpu_pd, cx-mpu_state);
+ }
+
+ /* Program CORE and PER to target state */
+ if (cx-core_state PWRDM_POWER_ON) {
+ if (per_pwrst == PWRDM_POWER_ON) {
+ omap2_gpio_prepare_for_retention();
+ if (clocks_off_while_idle) {
+ per_gpio_clk_disable();
+ omap_serial_enable_clocks(0);
+ }
+ }
+ pwrdm_set_next_pwrst(core_pd, cx-core_state);
+ }
/* Execute ARM wfi */
omap_sram_idle();
- /* Program MPU to ON */
- if (cx-mpu_state PWRDM_POWER_ON)
+ /* Program MPU/NEON to ON */
+ if (cx-mpu_state PWRDM_POWER_ON) {
+ if (neon_pwrst == PWRDM_POWER_ON)
+ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_ON);
pwrdm_set_next_pwrst(mpu_pd, PWRDM_POWER_ON);
+ }
+
+ if (cx-core_state PWRDM_POWER_ON) {
+ if (per_pwrst == PWRDM_POWER_ON) {
+ if (clocks_off_while_idle) {
+ omap_serial_enable_clocks(1);
+ per_gpio_clk_enable();
+ }
+ omap2_gpio_resume_after_retention();
+ }
+ pwrdm_set_next_pwrst(core_pd, PWRDM_POWER_ON);
+ }
+
+ pr_debug(MPU prev st:%x,NEON prev st:%x\n,
+ pwrdm_read_prev_pwrst(mpu_pd),
+ pwrdm_read_prev_pwrst(neon_pd));
+ pr_debug(PER prev st:%x,CORE prev st:%x\n,
+ pwrdm_read_prev_pwrst(per_pd),
+ pwrdm_read_prev_pwrst(core_pd));
getnstimeofday(ts_postidle);
ts_idle = timespec_sub(ts_postidle, ts_preidle);
- return timespec_to_ns(ts_idle);
+ return (u32)timespec_to_ns(ts_idle)/1000;
}
static int omap3_enter_idle_bm(struct cpuidle_device *dev,
@@ -130,7 +186,7 @@ void omap_init_power_states(void)
omap3_power_states[0].threshold = 0;
omap3_power_states[0].mpu_state = PWRDM_POWER_ON;
omap3_power_states[0].core_state = PWRDM_POWER_ON;
- omap3_power_states[0].flags = CPUIDLE_FLAG_TIME_VALID;
+ omap3_power_states[0].flags = CPUIDLE_FLAG_SHALLOW;
/* C1 . MPU WFI + Core active */
[PATCH 03/11] menuconfig updates for cpuidle
This patch enables the cpuidle option in menuconfig and selects the menu governor Signed-off-by: Rajendra Nayak [EMAIL PROTECTED] --- arch/arm/Kconfig| 10 ++ drivers/cpuidle/Kconfig | 26 +- 2 files changed, 31 insertions(+), 5 deletions(-) Index: linux-omap-2.6/arch/arm/Kconfig === --- linux-omap-2.6.orig/arch/arm/Kconfig2008-08-06 18:07:31.0 +0530 +++ linux-omap-2.6/arch/arm/Kconfig 2008-08-06 18:09:56.0 +0530 @@ -954,6 +954,16 @@ config ATAGS_PROC endmenu +if (ARCH_OMAP) + +menu CPUIdle + +source drivers/cpuidle/Kconfig + +endmenu + +endif + if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA) menu CPU Frequency scaling Index: linux-omap-2.6/drivers/cpuidle/Kconfig === --- linux-omap-2.6.orig/drivers/cpuidle/Kconfig 2008-08-06 18:07:31.0 +0530 +++ linux-omap-2.6/drivers/cpuidle/Kconfig 2008-08-06 18:09:56.0 +0530 @@ -1,20 +1,36 @@ +menu CPU idle PM support config CPU_IDLE bool CPU idle PM support - default ACPI + default n help CPU idle is a generic framework for supporting software-controlled idle processor power management. It includes modular cross-platform governors that can be swapped during runtime. - If you're using an ACPI-enabled platform, you should say Y here. + If you're using a mobile platform that supports CPU idle PM (e.g. + an ACPI-capable notebook), you should say Y here. + +if CPU_IDLE + +comment Governors config CPU_IDLE_GOV_LADDER - bool + bool ladder depends on CPU_IDLE - default y + default n config CPU_IDLE_GOV_MENU - bool + bool menu depends on CPU_IDLE NO_HZ default y +help + This cpuidle governor evaluates all available states and chooses the + deepest state that meets all of the following constraints: BM activity, + expected time until next timer interrupt, and last break event time + delta. It is designed to minimize power consumption. Currently + dynticks is required. + +endif # CPU_IDLE + +endmenu -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 04/11] sdrc register defs
This patch adds some missing sdrc register definitions
Signed-off-by: Rajendra Nayak [EMAIL PROTECTED]
---
arch/arm/mach-omap2/sram34xx.S |4 ++--
include/asm-arm/arch-omap/sdrc.h | 13 +++--
2 files changed, 13 insertions(+), 4 deletions(-)
Index: linux-omap-2.6/arch/arm/mach-omap2/sram34xx.S
===
--- linux-omap-2.6.orig/arch/arm/mach-omap2/sram34xx.S 2008-08-06
18:07:31.0 +0530
+++ linux-omap-2.6/arch/arm/mach-omap2/sram34xx.S 2008-08-06
18:10:18.0
+0530
@@ -165,9 +165,9 @@ omap3_cm_iclken1_core:
omap3_sdrc_rfr_ctrl:
.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
omap3_sdrc_actim_ctrla:
- .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A)
+ .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
omap3_sdrc_actim_ctrlb:
- .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B)
+ .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
omap3_sdrc_dlla_status:
.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
omap3_sdrc_dlla_ctrl:
Index: linux-omap-2.6/include/asm-arm/arch-omap/sdrc.h
===
--- linux-omap-2.6.orig/include/asm-arm/arch-omap/sdrc.h2008-08-06
18:07:31.0 +0530
+++ linux-omap-2.6/include/asm-arm/arch-omap/sdrc.h 2008-08-06
18:10:18.0 +0530
@@ -21,15 +21,24 @@
/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
#define SDRC_SYSCONFIG 0x010
+#define SDRC_CS_CFG0x040
+#define SDRC_SHARING 0x044
+#define SDRC_ERR_TYPE 0x04C
#define SDRC_DLLA_CTRL 0x060
#define SDRC_DLLA_STATUS 0x064
#define SDRC_DLLB_CTRL 0x068
#define SDRC_DLLB_STATUS 0x06C
#define SDRC_POWER 0x070
+#define SDRC_MCFG_00x080
#define SDRC_MR_0 0x084
-#define SDRC_ACTIM_CTRL_A 0x09c
-#define SDRC_ACTIM_CTRL_B 0x0a0
+#define SDRC_ACTIM_CTRL_A_00x09c
+#define SDRC_ACTIM_CTRL_B_00x0a0
#define SDRC_RFR_CTRL_00x0a4
+#define SDRC_MCFG_10x0B0
+#define SDRC_MR_1 0x0B4
+#define SDRC_ACTIM_CTRL_A_10x0C4
+#define SDRC_ACTIM_CTRL_B_10x0C8
+#define SDRC_RFR_CTRL_10x0D4
/*
* These values represent the number of memory clock cycles between
--
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[PATCH 07/11] gpmc context save/restore
This patch adds the context save restore functions for GPMC
Signed-off-by: Rajendra Nayak [EMAIL PROTECTED]
---
arch/arm/mach-omap2/gpmc.c | 80 +++
include/asm-arm/arch-omap/gpmc.h | 14 ++
2 files changed, 94 insertions(+)
Index: linux-omap-2.6/arch/arm/mach-omap2/gpmc.c
===
--- linux-omap-2.6.orig/arch/arm/mach-omap2/gpmc.c 2008-08-06
18:07:31.0 +0530
+++ linux-omap-2.6/arch/arm/mach-omap2/gpmc.c 2008-08-06 18:11:07.0
+0530
@@ -54,6 +54,21 @@
#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
#define GPMC_SECTION_SHIFT 28 /* 128 MB */
+/*
+ * Structure to save/restore gpmc context
+ * to support core off
+ */
+static struct gpmc_context {
+ u32 sysconfig;
+ u32 irqenable;
+ u32 timeout_ctrl;
+ u32 config;
+ u32 prefetch_config1;
+ u32 prefetch_config2;
+ u32 prefetch_control;
+ struct gpmc_cs_config cs_context[GPMC_CS_NUM];
+} gpmc_ctx;
+
static struct resource gpmc_mem_root;
static struct resource gpmc_cs_mem[GPMC_CS_NUM];
static DEFINE_SPINLOCK(gpmc_mem_lock);
@@ -432,3 +447,68 @@ void __init gpmc_init(void)
gpmc_mem_init();
}
+
+void omap_save_gpmc_ctx()
+{
+ int i;
+ gpmc_ctx.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
+ gpmc_ctx.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
+ gpmc_ctx.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
+ gpmc_ctx.config = gpmc_read_reg(GPMC_CONFIG);
+ gpmc_ctx.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
+ gpmc_ctx.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
+ gpmc_ctx.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
+ for (i = 0; i GPMC_CS_NUM; i++) {
+ gpmc_ctx.cs_context[i].is_valid =
+ (gpmc_cs_read_reg(i, GPMC_CS_CONFIG7))
+(1 6);
+ if (gpmc_ctx.cs_context[i].is_valid) {
+ gpmc_ctx.cs_context[i].gpmc_config1 =
+ gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
+ gpmc_ctx.cs_context[i].gpmc_config2 =
+ gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
+ gpmc_ctx.cs_context[i].gpmc_config3 =
+ gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
+ gpmc_ctx.cs_context[i].gpmc_config4 =
+ gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
+ gpmc_ctx.cs_context[i].gpmc_config5 =
+ gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
+ gpmc_ctx.cs_context[i].gpmc_config6 =
+ gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
+ gpmc_ctx.cs_context[i].gpmc_config7 =
+ gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
+ }
+ }
+}
+
+void omap_restore_gpmc_ctx()
+{
+ int i;
+ gpmc_write_reg(GPMC_SYSCONFIG, gpmc_ctx.sysconfig);
+ gpmc_write_reg(GPMC_IRQENABLE, gpmc_ctx.irqenable);
+ gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_ctx.timeout_ctrl);
+ gpmc_write_reg(GPMC_CONFIG, gpmc_ctx.config);
+ gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_ctx.prefetch_config1);
+ gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_ctx.prefetch_config2);
+ gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_ctx.prefetch_control);
+ for (i = 0; i GPMC_CS_NUM; i++) {
+ if (gpmc_ctx.cs_context[i].is_valid) {
+ gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
+ gpmc_ctx.cs_context[i].gpmc_config1);
+ gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
+ gpmc_ctx.cs_context[i].gpmc_config2);
+ gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
+ gpmc_ctx.cs_context[i].gpmc_config3);
+ gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
+ gpmc_ctx.cs_context[i].gpmc_config4);
+ gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
+ gpmc_ctx.cs_context[i].gpmc_config5);
+ gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
+ gpmc_ctx.cs_context[i].gpmc_config6);
+ gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
+ gpmc_ctx.cs_context[i].gpmc_config7);
+ }
+ }
+}
+
+
Index: linux-omap-2.6/include/asm-arm/arch-omap/gpmc.h
===
--- linux-omap-2.6.orig/include/asm-arm/arch-omap/gpmc.h2008-08-06
18:07:31.0 +0530
+++ linux-omap-2.6/include/asm-arm/arch-omap/gpmc.h 2008-08-06
18:11:07.0 +0530
@@ -86,6 +86,18 @@
[PATCH 08/11] serial context save/restore
This patch adds the context save restore functions for UART
Signed-off-by: Rajendra Nayak [EMAIL PROTECTED]
---
arch/arm/mach-omap2/serial.c | 62 +++
include/linux/serial_reg.h |1
2 files changed, 63 insertions(+)
Index: linux-omap-2.6/arch/arm/mach-omap2/serial.c
===
--- linux-omap-2.6.orig/arch/arm/mach-omap2/serial.c2008-08-06
18:08:02.0 +0530
+++ linux-omap-2.6/arch/arm/mach-omap2/serial.c 2008-08-06 18:11:15.0
+0530
@@ -83,6 +83,16 @@ static const u32 omap34xx_uart_padconf[O
CONTROL_PADCONF_UART3_RX
};
+struct omap_uart_regs {
+ u16 dll;
+ u16 dlh;
+ u16 ier;
+ u16 sysc;
+ u16 scr;
+ u16 wer;
+};
+static struct omap_uart_regs uart_ctx[OMAP_MAX_NR_PORTS];
+
static struct plat_serial8250_port serial_platform_data[] = {
{
.membase= (__force void __iomem
*)IO_ADDRESS(OMAP_UART1_BASE),
@@ -293,6 +303,58 @@ void __init omap_serial_init(void)
omap_serial_kick();
}
+void omap_save_uart_ctx(int unum)
+{
+ u16 lcr = 0;
+
+ struct plat_serial8250_port *p = serial_platform_data + unum;
+
+ if (uart_ick[unum] == NULL)
+ return;
+
+ lcr = serial_read_reg(p, UART_LCR);
+ serial_write_reg(p, UART_LCR, 0xBF);
+ uart_ctx[unum].dll = serial_read_reg(p, UART_DLL);
+ uart_ctx[unum].dlh = serial_read_reg(p, UART_DLM);
+ serial_write_reg(p, UART_LCR, lcr);
+ uart_ctx[unum].ier = serial_read_reg(p, UART_IER);
+ uart_ctx[unum].sysc = serial_read_reg(p, UART_OMAP_SYSC);
+ uart_ctx[unum].scr = serial_read_reg(p, UART_OMAP_SCR);
+ uart_ctx[unum].wer = serial_read_reg(p, UART_OMAP_WER);
+}
+EXPORT_SYMBOL(omap_save_uart_ctx);
+
+void omap_restore_uart_ctx(int unum)
+{
+ u16 efr = 0;
+
+ struct plat_serial8250_port *p = serial_platform_data + unum;
+
+ if (uart_ick[unum] == NULL)
+ return;
+
+ serial_write_reg(p, UART_OMAP_MDR1, 0x7);
+ serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
+ efr = serial_read_reg(p, UART_EFR);
+ serial_write_reg(p, UART_EFR, UART_EFR_ECB);
+ serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
+ serial_write_reg(p, UART_IER, 0x0);
+ serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
+ serial_write_reg(p, UART_DLL, uart_ctx[unum].dll);
+ serial_write_reg(p, UART_DLM, uart_ctx[unum].dlh);
+ serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
+ serial_write_reg(p, UART_IER, uart_ctx[unum].ier);
+ serial_write_reg(p, UART_FCR, 0xA1);
+ serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
+ serial_write_reg(p, UART_EFR, efr);
+ serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
+ serial_write_reg(p, UART_OMAP_SCR, uart_ctx[unum].scr);
+ serial_write_reg(p, UART_OMAP_WER, uart_ctx[unum].wer);
+ serial_write_reg(p, UART_OMAP_SYSC, uart_ctx[unum].sysc);
+ serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
+}
+EXPORT_SYMBOL(omap_restore_uart_ctx);
+
static struct platform_device serial_device = {
.name = serial8250,
.id = PLAT8250_DEV_PLATFORM,
Index: linux-omap-2.6/include/linux/serial_reg.h
===
--- linux-omap-2.6.orig/include/linux/serial_reg.h 2008-08-06
18:07:31.0 +0530
+++ linux-omap-2.6/include/linux/serial_reg.h 2008-08-06 18:11:15.0
+0530
@@ -323,6 +323,7 @@
#define UART_OMAP_MVER 0x14/* Module version register */
#define UART_OMAP_SYSC 0x15/* System configuration register */
#define UART_OMAP_SYSS 0x16/* System status register */
+#define UART_OMAP_WER 0x17/* Wake-up enable register */
#endif /* _LINUX_SERIAL_REG_H */
--
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[PATCH 09/11] gpio context save/restore
This patch adds the context save restore functions for GPIO
Signed-off-by: Rajendra Nayak [EMAIL PROTECTED]
---
arch/arm/plat-omap/gpio.c | 94 +
include/asm-arm/arch-omap/common.h |2
2 files changed, 96 insertions(+)
Index: linux-omap-2.6/arch/arm/plat-omap/gpio.c
===
--- linux-omap-2.6.orig/arch/arm/plat-omap/gpio.c 2008-08-06
18:07:31.0
+0530
+++ linux-omap-2.6/arch/arm/plat-omap/gpio.c2008-08-06 18:11:21.0
+0530
@@ -102,6 +102,7 @@
#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
#define OMAP24XX_GPIO_IRQENABLE2 0x002c
#define OMAP24XX_GPIO_IRQENABLE1 0x001c
+#define OMAP24XX_GPIO_WAKE_EN 0x0020
#define OMAP24XX_GPIO_CTRL 0x0030
#define OMAP24XX_GPIO_OE 0x0034
#define OMAP24XX_GPIO_DATAIN 0x0038
@@ -217,8 +218,26 @@ static struct gpio_bank gpio_bank_34xx[6
{ OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160,
METHOD_GPIO_24XX },
};
+struct gpio_restore_regs {
+ u32 gpio_sysconfig;
+ u32 gpio_irqenable1;
+ u32 gpio_irqenable2;
+ u32 gpio_wake_en;
+ u32 gpio_ctrl;
+ u32 gpio_oe;
+ u32 gpio_leveldetect0;
+ u32 gpio_leveldetect1;
+ u32 gpio_risingdetect;
+ u32 gpio_fallingdetect;
+ u32 gpio_dataout;
+ u32 gpio_setwkuena;
+ u32 gpio_setdataout;
+};
+static struct gpio_restore_regs gpio_restore_banks[6];
#endif
+
+
static struct gpio_bank *gpio_bank;
static int gpio_bank_count;
@@ -1705,6 +1724,81 @@ void omap2_gpio_resume_after_retention(v
#endif
+#ifdef CONFIG_ARCH_OMAP34XX
+/* save the registers of bank 2-6 */
+void omap_gpio_save(void)
+{
+ int i;
+ /* saving banks from 2-6 only */
+ for (i = 1; i gpio_bank_count; i++) {
+ struct gpio_bank *bank = gpio_bank[i];
+ gpio_restore_banks[i].gpio_sysconfig =
+ __raw_readl(bank-base + OMAP24XX_GPIO_SYSCONFIG);
+ gpio_restore_banks[i].gpio_irqenable1 =
+ __raw_readl(bank-base + OMAP24XX_GPIO_IRQENABLE1);
+ gpio_restore_banks[i].gpio_irqenable2 =
+ __raw_readl(bank-base + OMAP24XX_GPIO_IRQENABLE2);
+ gpio_restore_banks[i].gpio_wake_en =
+ __raw_readl(bank-base + OMAP24XX_GPIO_WAKE_EN);
+ gpio_restore_banks[i].gpio_ctrl =
+ __raw_readl(bank-base + OMAP24XX_GPIO_CTRL);
+ gpio_restore_banks[i].gpio_oe =
+ __raw_readl(bank-base + OMAP24XX_GPIO_OE);
+ gpio_restore_banks[i].gpio_leveldetect0 =
+ __raw_readl(bank-base + OMAP24XX_GPIO_LEVELDETECT0);
+ gpio_restore_banks[i].gpio_leveldetect1 =
+ __raw_readl(bank-base + OMAP24XX_GPIO_LEVELDETECT1);
+ gpio_restore_banks[i].gpio_risingdetect =
+ __raw_readl(bank-base + OMAP24XX_GPIO_RISINGDETECT);
+ gpio_restore_banks[i].gpio_fallingdetect =
+ __raw_readl(bank-base + OMAP24XX_GPIO_FALLINGDETECT);
+ gpio_restore_banks[i].gpio_dataout =
+ __raw_readl(bank-base + OMAP24XX_GPIO_DATAOUT);
+ gpio_restore_banks[i].gpio_setwkuena =
+ __raw_readl(bank-base + OMAP24XX_GPIO_SETWKUENA);
+ gpio_restore_banks[i].gpio_setdataout =
+ __raw_readl(bank-base + OMAP24XX_GPIO_SETDATAOUT);
+ }
+}
+EXPORT_SYMBOL(omap_gpio_save);
+
+/* restore the required registers of bank 2-6 */
+void omap_gpio_restore(void)
+{
+ int i;
+ for (i = 1; i gpio_bank_count; i++) {
+ struct gpio_bank *bank = gpio_bank[i];
+ __raw_writel(gpio_restore_banks[i].gpio_sysconfig,
+ bank-base + OMAP24XX_GPIO_SYSCONFIG);
+ __raw_writel(gpio_restore_banks[i].gpio_irqenable1,
+ bank-base + OMAP24XX_GPIO_IRQENABLE1);
+ __raw_writel(gpio_restore_banks[i].gpio_irqenable2,
+ bank-base + OMAP24XX_GPIO_IRQENABLE2);
+ __raw_writel(gpio_restore_banks[i].gpio_wake_en,
+ bank-base + OMAP24XX_GPIO_WAKE_EN);
+ __raw_writel(gpio_restore_banks[i].gpio_ctrl,
+ bank-base + OMAP24XX_GPIO_CTRL);
+ __raw_writel(gpio_restore_banks[i].gpio_oe,
+ bank-base + OMAP24XX_GPIO_OE);
+ __raw_writel(gpio_restore_banks[i].gpio_leveldetect0,
+ bank-base + OMAP24XX_GPIO_LEVELDETECT0);
+ __raw_writel(gpio_restore_banks[i].gpio_leveldetect1,
+ bank-base + OMAP24XX_GPIO_LEVELDETECT1);
+
[PATCH 10/11] i2c context save/restore
This patch does i2c init/re-init for every transfer Signed-off-by: Rajendra Nayak [EMAIL PROTECTED] --- drivers/i2c/busses/i2c-omap.c |2 ++ 1 files changed, 2 insertions(+) Index: linux-omap-2.6/drivers/i2c/busses/i2c-omap.c === --- linux-omap-2.6.orig/drivers/i2c/busses/i2c-omap.c 2008-08-06 18:07:31.0 +0530 +++ linux-omap-2.6/drivers/i2c/busses/i2c-omap.c2008-08-06 18:11:28.0 +0530 @@ -496,6 +496,8 @@ omap_i2c_xfer(struct i2c_adapter *adap, omap_i2c_unidle(dev); + omap_i2c_init(dev); + if ((r = omap_i2c_wait_for_bb(dev)) 0) goto out; -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 11/11] CORE context save/restore
This patch adds the CORE context save/restore routines
- save/restores the following
1) PRCM registers
2) INTC context
3) System Control module context
4) Padconf
Signed-off-by: Rajendra Nayak [EMAIL PROTECTED]
---
arch/arm/mach-omap2/cpuidle34xx.c | 612 +++-
arch/arm/mach-omap2/cpuidle34xx.h | 33 +
arch/arm/mach-omap2/pm34xx.c| 158 -
arch/arm/mach-omap2/prm.h |2
arch/arm/mach-omap2/serial.c| 19 -
arch/arm/mach-omap2/sleep34xx.S | 12
arch/arm/plat-omap/sram.c |9
drivers/serial/8250.c | 20 +
include/asm-arm/arch-omap/common.h |2
include/asm-arm/arch-omap/control.h | 22 +
include/asm-arm/arch-omap/prcm.h| 58 +++
11 files changed, 767 insertions(+), 180 deletions(-)
Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c
===
--- linux-omap-2.6.orig/arch/arm/mach-omap2/cpuidle34xx.c 2008-08-06
18:10:59.0 +0530
+++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c2008-08-06
18:11:36.0 +0530
@@ -28,7 +28,382 @@
#include asm/arch/powerdomain.h
#include asm/arch/clockdomain.h
#include asm/arch/gpio.h
+#include asm/arch/gpmc.h
+#include asm/arch/control.h
+#include linux/sched.h
#include cpuidle34xx.h
+#include cm.h
+#include cm-regbits-34xx.h
+#include prm-regbits-34xx.h
+#include prm.h
+#include pm.h
+#include clock34xx.h
+
+static int padconf_saved;
+void omap3_save_prcm_ctx(void)
+{
+ prcm_sleep_save[1] = omap_readl(INTC_MIR_0);
+ prcm_sleep_save[2] = omap_readl(INTC_MIR_1);
+ prcm_sleep_save[3] = omap_readl(INTC_MIR_2);
+ prcm_sleep_save[4] = omap_readl(CONTROL_PADCONF_SYS_NIRQ);
+ prcm_sleep_save[5] = omap_readl(OMAP34XX_GPIO1_IRQENABLE1);
+ prcm_sleep_save[6] = omap_readl(OMAP34XX_GPIO1_WAKEUPEN);
+ prcm_sleep_save[7] = cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
+ prcm_sleep_save[8] = __raw_readl(OMAP3430_CM_SYSCONFIG);
+ prcm_sleep_save[9] = cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
+ prcm_sleep_save[10] = cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
+ prcm_sleep_save[11] = cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
+ prcm_sleep_save[12] = cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
+ prcm_sleep_save[13] = cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
+ prcm_sleep_save[14] = cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
+ prcm_sleep_save[15] = cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSTCTRL);
+ prcm_sleep_save[16] = cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
+ prcm_sleep_save[17] = cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
+ prcm_sleep_save[18] = __raw_readl(OMAP3430_CM_POLCTRL);
+ prcm_sleep_save[19] = cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
+ prcm_sleep_save[20] = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
+ prcm_sleep_save[21] = cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
+ prcm_sleep_save[22] = cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
+ prcm_sleep_save[23] = cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
+ prcm_sleep_save[24] = cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
+ prcm_sleep_save[25] = cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
+ prcm_sleep_save[26] = cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
+ prcm_sleep_save[27] = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
+ CM_FCLKEN);
+ prcm_sleep_save[28] = cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
+ prcm_sleep_save[29] = cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
+ prcm_sleep_save[30] = cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
+ prcm_sleep_save[31] = cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
+ prcm_sleep_save[32] = cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
+ prcm_sleep_save[33] = cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
+ prcm_sleep_save[34] = cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
+ prcm_sleep_save[35] = cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
+ prcm_sleep_save[36] = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
+ CM_ICLKEN);
+ prcm_sleep_save[37] = cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
+ prcm_sleep_save[38] = cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
+ prcm_sleep_save[39] = cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
+ prcm_sleep_save[40] = cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSTCTRL);
+ prcm_sleep_save[41] = cm_read_mod_reg(MPU_MOD, CM_CLKSTCTRL);
+ prcm_sleep_save[42] = cm_read_mod_reg(CORE_MOD, CM_CLKSTCTRL);
+ prcm_sleep_save[43] = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
+ CM_CLKSTCTRL);
+ prcm_sleep_save[44] = cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSTCTRL);
+ prcm_sleep_save[45] =
[PATCH 06/11] mpu off state enabled
This patch updates the CPUidle code to handle MPU OFF related C states
Signed-off-by: Rajendra Nayak [EMAIL PROTECTED]
---
arch/arm/mach-omap2/cpuidle34xx.c | 19 +++
arch/arm/mach-omap2/cpuidle34xx.h |5 +
2 files changed, 20 insertions(+), 4 deletions(-)
Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c
===
--- linux-omap-2.6.orig/arch/arm/mach-omap2/cpuidle34xx.c 2008-08-06
18:09:48.0 +0530
+++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c2008-08-06
18:10:59.0 +0530
@@ -82,8 +82,12 @@ static int omap3_enter_idle(struct cpuid
/* Program MPU to target state */
if (cx-mpu_state PWRDM_POWER_ON) {
- if (neon_pwrst == PWRDM_POWER_ON)
- pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_RET);
+ if (neon_pwrst == PWRDM_POWER_ON) {
+ if (cx-mpu_state == PWRDM_POWER_RET)
+ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_RET);
+ else if (cx-mpu_state == PWRDM_POWER_OFF)
+ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_OFF);
+ }
pwrdm_set_next_pwrst(mpu_pd, cx-mpu_state);
}
@@ -99,9 +103,13 @@ static int omap3_enter_idle(struct cpuid
pwrdm_set_next_pwrst(core_pd, cx-core_state);
}
+ *(scratchpad_restore_addr) = restore_pointer_address;
+
/* Execute ARM wfi */
omap_sram_idle();
+ *(scratchpad_restore_addr) = 0x0;
+
/* Program MPU/NEON to ON */
if (cx-mpu_state PWRDM_POWER_ON) {
if (neon_pwrst == PWRDM_POWER_ON)
@@ -211,7 +219,7 @@ void omap_init_power_states(void)
CPUIDLE_FLAG_BALANCED;
/* C3 . MPU OFF + Core active */
- omap3_power_states[3].valid = 0;
+ omap3_power_states[3].valid = 1;
omap3_power_states[3].type = OMAP3_STATE_C3;
omap3_power_states[3].sleep_latency = 1500;
omap3_power_states[3].wakeup_latency = 1800;
@@ -233,7 +241,7 @@ void omap_init_power_states(void)
CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM;
/* C5 . MPU OFF + Core CSWR */
- omap3_power_states[5].valid = 0;
+ omap3_power_states[5].valid = 1;
omap3_power_states[5].type = OMAP3_STATE_C5;
omap3_power_states[5].sleep_latency = 3000;
omap3_power_states[5].wakeup_latency = 8500;
@@ -270,6 +278,9 @@ int omap3_idle_init(void)
struct cpuidle_state *state;
struct cpuidle_device *dev;
+ clear_scratchpad_contents();
+ save_scratchpad_contents();
+
omap_init_power_states();
cpuidle_register_driver(omap3_idle_driver);
Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h
===
--- linux-omap-2.6.orig/arch/arm/mach-omap2/cpuidle34xx.h 2008-08-06
18:09:48.0 +0530
+++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h2008-08-06
18:10:59.0 +0530
@@ -40,6 +40,11 @@ extern void per_gpio_clk_enable(void);
extern void per_gpio_clk_disable(void);
extern void omap_serial_enable_clocks(int enable);
extern int omap3_can_sleep();
+extern void clear_scratchpad_contents(void);
+extern void save_scratchpad_contents(void);
+extern u32 *scratchpad_restore_addr;
+extern u32 restore_pointer_address;
+
struct omap3_processor_cx {
u8 valid;
u8 type;
--
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[PATCH 06/11] mpu off state enabled
This patch updates the CPUidle code to handle MPU OFF related C states
Signed-off-by: Rajendra Nayak [EMAIL PROTECTED]
---
arch/arm/mach-omap2/cpuidle34xx.c | 19 +++
arch/arm/mach-omap2/cpuidle34xx.h |5 +
2 files changed, 20 insertions(+), 4 deletions(-)
Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c
===
--- linux-omap-2.6.orig/arch/arm/mach-omap2/cpuidle34xx.c 2008-08-06
18:09:48.0 +0530
+++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c2008-08-06
18:10:59.0 +0530
@@ -82,8 +82,12 @@ static int omap3_enter_idle(struct cpuid
/* Program MPU to target state */
if (cx-mpu_state PWRDM_POWER_ON) {
- if (neon_pwrst == PWRDM_POWER_ON)
- pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_RET);
+ if (neon_pwrst == PWRDM_POWER_ON) {
+ if (cx-mpu_state == PWRDM_POWER_RET)
+ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_RET);
+ else if (cx-mpu_state == PWRDM_POWER_OFF)
+ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_OFF);
+ }
pwrdm_set_next_pwrst(mpu_pd, cx-mpu_state);
}
@@ -99,9 +103,13 @@ static int omap3_enter_idle(struct cpuid
pwrdm_set_next_pwrst(core_pd, cx-core_state);
}
+ *(scratchpad_restore_addr) = restore_pointer_address;
+
/* Execute ARM wfi */
omap_sram_idle();
+ *(scratchpad_restore_addr) = 0x0;
+
/* Program MPU/NEON to ON */
if (cx-mpu_state PWRDM_POWER_ON) {
if (neon_pwrst == PWRDM_POWER_ON)
@@ -211,7 +219,7 @@ void omap_init_power_states(void)
CPUIDLE_FLAG_BALANCED;
/* C3 . MPU OFF + Core active */
- omap3_power_states[3].valid = 0;
+ omap3_power_states[3].valid = 1;
omap3_power_states[3].type = OMAP3_STATE_C3;
omap3_power_states[3].sleep_latency = 1500;
omap3_power_states[3].wakeup_latency = 1800;
@@ -233,7 +241,7 @@ void omap_init_power_states(void)
CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM;
/* C5 . MPU OFF + Core CSWR */
- omap3_power_states[5].valid = 0;
+ omap3_power_states[5].valid = 1;
omap3_power_states[5].type = OMAP3_STATE_C5;
omap3_power_states[5].sleep_latency = 3000;
omap3_power_states[5].wakeup_latency = 8500;
@@ -270,6 +278,9 @@ int omap3_idle_init(void)
struct cpuidle_state *state;
struct cpuidle_device *dev;
+ clear_scratchpad_contents();
+ save_scratchpad_contents();
+
omap_init_power_states();
cpuidle_register_driver(omap3_idle_driver);
Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h
===
--- linux-omap-2.6.orig/arch/arm/mach-omap2/cpuidle34xx.h 2008-08-06
18:09:48.0 +0530
+++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h2008-08-06
18:10:59.0 +0530
@@ -40,6 +40,11 @@ extern void per_gpio_clk_enable(void);
extern void per_gpio_clk_disable(void);
extern void omap_serial_enable_clocks(int enable);
extern int omap3_can_sleep();
+extern void clear_scratchpad_contents(void);
+extern void save_scratchpad_contents(void);
+extern u32 *scratchpad_restore_addr;
+extern u32 restore_pointer_address;
+
struct omap3_processor_cx {
u8 valid;
u8 type;
--
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Fwd: how to use omap 2430 character led
CAn anyone tell me howto use the character lcd display on omap 2430 board. i want to test it and use it at assembly level i am writing it in the memory locations but im not getting any output. do we have to do any initializations to run this code on the board ? like mux config ? im creating a bin image and trying to run it in the ram directly. do i have to initialisze the pad ? i dono much, im a newbie to omaps -- with regards vishal -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: About to tag v2.6.26-omap1, patch queue deleted, please check and repost
On Tue, Aug 5, 2008 at 11:41 PM, Dirk Behme [EMAIL PROTECTED] wrote: Gadiyar, Anand wrote: Hi all, I've pushed all the patches I have in my omap inbox, except for the omap serial driver that I want to look more. I've tried to comment on the ones that did not get pushed, then erased everything from my omap inbox. Some drivers should get integrated via other mailing lists, and some debug patches can probably stay as debug patches, and some patches I probably have accidentally deleted :) And the PM patches I lost track of, so those should be reposted. So please check your patches, and repost your patches if something is left out. Also please check that things work for your board, let's try to tag v2.6.26-omap1 within next few days so we can move on again. Cheers, Tony Boot tested on 3430SDP with the defconfig. Things work okay so far. Same with BeagleBoard. Dirk -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Hi all, Boot tested on omap2evm with defconfig. The printks from omapfb(irq errors) is stalling the console sometimes, otherwise everything seems to be fine. Regards, Arun C -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[RESUBMIT][PATCH 0/8][GIT 3/4+] Bridge cleanup patches
Hi, These are the latest set of patches that contain changes to dspbridge code. They are used to fix some of the warnings and errors reported from various code check tools, like checkpatch and sparse. They also remove some code that is now obsolete and try to make bridge code more understandable and clean. The patch order is: BRD001-ARM-OMAP-checkpatch-cleanup.patch BRD002-ARM-OMAP-compilation-fixes.patch BRD003-ARM-OMAP-remove-unused-headers.patch BRD004-ARM-OMAP-remove-unused-code.patch BRD005-ARM-OMAP-remove-dynload-flags.patch BRD006-ARM-OMAP-remove-commented-out-code.patch BRD007-ARM-OMAP-remove_CFG_GetDSPProcs.patch BRD008-ARM-OMAP-add-debug-option.patch (on behalf of Felipe Contreras) You can find them at: http://omapzoom.org/gf/project/omapbridge/frs/?action=FrsReleaseBrowsefrs_package_id=16 - omar -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH][GIT 3/4+] dspbridge custom bool types cleanup
Hi, This patch replaces bool typedefs with the ones from the kernel, as reported by checkpatch tool. It should be applied on top of the latest set of cleanup patches (BRD001 to BRD007) and after Felipe's Kbuild patch (BRD008). As it is quite big, you can found it at: http://omapzoom.org/gf/project/omapbridge/frs/?action=FrsReleaseBrowsefrs_package_id=16 It is named: BRD009-ARM-OMAP-removed_custom_bool_types.patch This patch will break compatibility with the previous API and Samples tarballs on omapzoom. The tarballs with new API and Samples to support this will be uploaded very soon! You will be able to download them from: http://omapzoom.org/gf/project/omapbridge/frs/ Use these API and samples tarballs after applying this patch. I'll send a mail as soon as this tarball is ready. - omar -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH][GIT 3/4+] Remove build warnings from dspbridge code
Hi, The following patch fixes warnings present at building stages. Cleaning up the code to remove minor issues and an unnecessary header file. Placed under: http://omapzoom.org/gf/project/omapbridge/frs/?action=FrsReleaseBrowsefrs_package_id=16 Named: BRD010-ARM-OMAP-cleanup_warnings.patch - omar --- Index: omapkernel/drivers/dsp/dspbridge/mpu_driver/inc/dbc.h === --- omapkernel.orig/drivers/dsp/dspbridge/mpu_driver/inc/dbc.h 2008-08-06 09:49:03.0 -0500 +++ omapkernel/drivers/dsp/dspbridge/mpu_driver/inc/dbc.h 2008-08-06 09:59:14.0 -0500 @@ -39,6 +39,10 @@ #ifndef DBC_ #define DBC_ +#ifndef GT_TRACE +#define GT_TRACE 0 /* 0 = trace compiled out; 1 = trace active */ +#endif + /* Assertion Macros: */ #if GT_TRACE Index: omapkernel/drivers/dsp/dspbridge/mpu_driver/inc/dbtype.h === --- omapkernel.orig/drivers/dsp/dspbridge/mpu_driver/inc/dbtype.h 2008-08-06 09:49:03.0 -0500 +++ omapkernel/drivers/dsp/dspbridge/mpu_driver/inc/dbtype.h2008-08-06 09:59:14.0 -0500 @@ -87,7 +87,6 @@ #ifndef OMAPBRIDGE_TYPES #define OMAPBRIDGE_TYPES -typedef int BOOL; /* f*/ typedef volatile unsigned short REG_UWORD16; #endif Index: omapkernel/drivers/dsp/dspbridge/mpu_driver/inc/dynamic_loader.h === --- omapkernel.orig/drivers/dsp/dspbridge/mpu_driver/inc/dynamic_loader.h 2008-08-06 09:49:03.0 -0500 +++ omapkernel/drivers/dsp/dspbridge/mpu_driver/inc/dynamic_loader.h 2008-08-06 09:59:14.0 -0500 @@ -18,7 +18,7 @@ #ifndef _DYNAMIC_LOADER_H_ #define _DYNAMIC_LOADER_H_ -#include stdarg.h +#include linux/kernel.h #include linux/types.h /* Index: omapkernel/drivers/dsp/dspbridge/mpu_driver/inc/gp.h === --- omapkernel.orig/drivers/dsp/dspbridge/mpu_driver/inc/gp.h 2008-08-06 09:49:03.0 -0500 +++ /dev/null 1970-01-01 00:00:00.0 + @@ -1,33 +0,0 @@ -/* - * dspbridge/mpu_driver/inc/gp.h - * - * DSP-BIOS Bridge driver support functions for TI OMAP processors. - * - * Copyright (C) 2005-2006 Texas Instruments, Inc. - * - * This package is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -/* - * gp.h - *! Revision History - *! - */ - -#ifndef GP_ -#define GP_ - -#include stdarg.h - -/* - * GP_snprintf - */ -#define GP_snprintf snprintf - -#endif Index: omapkernel/drivers/dsp/dspbridge/mpu_driver/inc/io_sm.h === --- omapkernel.orig/drivers/dsp/dspbridge/mpu_driver/inc/io_sm.h 2008-08-06 09:49:03.0 -0500 +++ omapkernel/drivers/dsp/dspbridge/mpu_driver/inc/io_sm.h 2008-08-06 09:59:14.0 -0500 @@ -115,24 +115,6 @@ extern void IO_DPC(IN OUT void *pRefData); /* - * IO_IVADPC - * Purpose: - * Deferred procedure call for shared memory channel driver ISR. Carries - * out the dispatch of I/O. - * Parameters: - * pRefData: Pointer to reference data registered via a call to - * DPC_Create(). - * Returns: - * Requires: - * Must not block. - * Must not acquire resources. - * All data touched must be locked in memory if running in kernel mode. - * Ensures: - * Non-preemptible (but interruptible). - */ - extern void IO_IVADPC(IN OUT void *pRefData); - -/* * IO_ISR * Purpose: * Main interrupt handler for the shared memory WMD channel manager. @@ -153,26 +135,6 @@ extern bool IO_ISR(IN void *pRefData); /* - * IO_IVAISR - * Purpose: - * Main interrupt handler for the shared memory WMD channel manager. - * Calls the WMD's CHNLSM_ISR to determine if this interrupt is ours, then - * schedules a DPC to dispatch I/O.. - * Parameters: - * pRefData: Pointer to the channel manager object for this board. - * Set in an initial call to ISR_Install(). - * Returns: - * TRUE if interrupt handled; FALSE otherwise. - * Requires: - * Must be in locked memory if executing in kernel mode. - * Must only call functions which are in locked memory if Kernel mode. - * Must only call asynchronous services. - * Interrupts are disabled and EOI for this interrupt has been sent. - * Ensures: - */ - extern BOOL IO_IVAISR(IN void *pRefData); - -/* * IO_RequestChnl *
Re: About to tag v2.6.26-omap1, patch queue deleted, please check and repost
On an omap3evm with the defconfig, the kernel is failing to identify a jffs2 filesystem. It's booting from NFS just fine. I had built the latest code checked into linux-omap last week - file system booting had been working, IIRC. Loading TI reference 2.6.22 kernel finds the file system just fine as well. I'll begin looking into this next week if someone else doesn't beat me to it. Texas Instruments X-Loader 1.41 Detected Samsung MuxOneNAND1G Flash Starting OS Bootloader... U-Boot 1.1.4 (Jun 6 2008 - 18:25:31) OMAP3-GP rev 2, CPU-OPP2 L3-165MHz OMAP3EVM 1.0 Version + mPOP (Boot ONND) DRAM: 128 MB OneNAND Manufacturer: Samsung (0xec) Muxed OneNAND 128MB 1.8V 16-bit (0x30) OneNAND version = 0x0221 Scanning device for bad blocks num of blocks = 2048 In:serial Out: serial Err: serial Reseting CHIP... Done LAN9x18 (0x01150002) detected. Setting mac address: 00:50:c2:7e:86:9f start Auto negotiation... (take ~2sec) Auto negotiation complete, 100BaseTX, full duplex Hit any key to stop autoboot: 0 OMAP3EVM # run boot_fs Done ## Booting image at 8000 ... Image Name: Linux-2.6.26-omap1-04784-g040378 Image Type: ARM Linux Kernel Image (uncompressed) Data Size:1515692 Bytes = 1.4 MB Load Address: 80008000 Entry Point: 80008000 Verifying Checksum ... OK OK Starting kernel ... Uncompressing Linux. . done, booting the kernel. 5Linux version 2.6.26-omap1-04784-g040378c-dirty ([EMAIL PROTECTED]) (gcc v ersion 4.2.1 (CodeSourcery Sourcery G++ Lite 2007q3-51)) #3 Tue Aug 5 14:45:54 E DT 2008 CPU: ARMv7 Processor [411fc082] revision 2 (ARMv7), cr=00c5387f Machine: OMAP3 EVM Memory policy: ECC disabled, Data cache writeback 7On node 0 totalpages: 32768 7 DMA zone: 256 pages used for memmap 7 DMA zone: 0 pages reserved 7 DMA zone: 32512 pages, LIFO batch:7 7 Normal zone: 0 pages used for memmap 7 Movable zone: 0 pages used for memmap 6OMAP3430 ES2.2 6SRAM: Mapped pa 0x4020 to va 0xd700 size: 0x10 CPU0: D VIPT write-through cache CPU0: cache: 768 bytes, associativity 1, 8 byte lines, 64 sets Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512 5Kernel command line: mem=128M console=ttyS0,115200n8 noinitrd root=/dev/mtdbl ock4 rw rootfstype=jffs2 ip=10.51.0.10:10.51.0.30:10.2.8.1:255.255.252.0:omap-ev m0:eth0:on 6Clocking rate (Crystal/DPLL/ARM core): 26.0/332/500 MHz 6GPMC revision 5.0 6IRQ: Found an INTC at 0xd820 (revision 4.0) with 96 interrupts 6Total of 96 interrupts on 1 active controller 6OMAP34xx GPIO hardware version 2.5 PID hash table entries: 512 (order: 9, 2048 bytes) Console: colour dummy device 80x30 6Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) 6Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) 6Memory: 128MB = 128MB total 5Memory: 126720KB available (2776K code, 230K data, 116K init) 7Calibrating delay loop... 498.87 BogoMIPS (lpj=1945600) Mount-cache hash table entries: 512 6CPU: Testing write buffer coherency: ok 6net_namespace: 192 bytes 6NET: Registered protocol family 16 4Warning: L2 cache not enabled. Check your bootloader. L2 off results in perfo rmance loss 6OMAP DMA hardware revision 4.0 3USB: No board-specific platform config found 6i2c_omap i2c_omap.1: bus 1 rev3.12 at 2600 kHz 6i2c_omap i2c_omap.2: bus 2 rev3.12 at 400 kHz 6i2c_omap i2c_omap.3: bus 3 rev3.12 at 400 kHz 6TWL4030: TRY attach Slave TWL4030-ID0 on Adapter OMAP I2C adapter [1] 6TWL4030: TRY attach Slave TWL4030-ID1 on Adapter OMAP I2C adapter [1] 6TWL4030: TRY attach Slave TWL4030-ID2 on Adapter OMAP I2C adapter [1] 6TWL4030: TRY attach Slave TWL4030-ID3 on Adapter OMAP I2C adapter [1] 6Initialized TWL4030 USB module 5SCSI subsystem initialized 6NET: Registered protocol family 2 7Switched to high resolution mode on CPU 0 6IP route cache hash table entries: 1024 (order: 0, 4096 bytes) 6TCP established hash table entries: 4096 (order: 3, 32768 bytes) 6TCP bind hash table entries: 4096 (order: 2, 16384 bytes) 6TCP: Hash tables configured (established 4096 bind 4096) 6TCP reno registered 6NET: Registered protocol family 1 4NetWinder Floating Point Emulator V0.97 (double precision) 5VFS: Disk quotas dquot_6.5.1 Dquot-cache hash table entries: 1024 (order 0, 4096 bytes) 6JFFS2 version 2.2. (NAND) �© 2001-2006 Red Hat, Inc. 6msgmni has been set to 247 6io scheduler noop registered 6io scheduler anticipatory registered (default) 6io scheduler deadline registered 6io scheduler cfq registered 6omapfb: configured for panel omap3evm 6omapfb: DISPC version 3.0 initialized 6omapfb: Framebuffer initialized. Total vram 614400 planes 1 6omapfb: Pixclock 24000 kHz hfreq 45.2 kHz vfreq 70.3 Hz 6Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing enabled 6serial8250.0: ttyS0 at MMIO 0x4806a000 (irq = 72) is a
