[PATCH 2/2] DSPBRIDGE: Set VDD1 OPP1 while MPU initiated OFF mode
Signed-off-by: Ameya Palande ameya.pala...@nokia.com
---
drivers/dsp/bridge/wmd/tiomap3430_pwr.c | 15 ++-
1 files changed, 14 insertions(+), 1 deletions(-)
diff --git a/drivers/dsp/bridge/wmd/tiomap3430_pwr.c
b/drivers/dsp/bridge/wmd/tiomap3430_pwr.c
index 7aa58d1..dfac5b6 100644
--- a/drivers/dsp/bridge/wmd/tiomap3430_pwr.c
+++ b/drivers/dsp/bridge/wmd/tiomap3430_pwr.c
@@ -292,8 +292,21 @@ DSP_STATUS SleepDSP(struct WMD_DEV_CONTEXT *pDevContext,
IN u32 dwCmd,
/* Turn off DSP Peripheral clocks */
status = DSP_PeripheralClocks_Disable(pDevContext, NULL);
- if (DSP_FAILED(status))
+ if (DSP_FAILED(status)) {
DBG_Trace(DBG_LEVEL7, SleepDSP- FAILED\n);
+ return status;
+ }
+#ifdef CONFIG_BRIDGE_DVFS
+ else if (targetPwrState == HW_PWR_STATE_OFF) {
+ struct dspbridge_platform_data *pdata =
+ omap_dspbridge_dev-dev.platform_data;
+ /*
+* Set the OPP to low level before moving to OFF mode
+*/
+ if (pdata-dsp_set_min_opp)
+ (*pdata-dsp_set_min_opp)(VDD1_OPP1);
+ }
+#endif /* CONFIG_BRIDGE_DVFS */
}
#endif /* CONFIG_PM */
return status;
--
1.6.2.4
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[PATCH 1/2] DSPBRIDGE: Cleanup SleepDSP
Signed-off-by: Ameya Palande ameya.pala...@nokia.com
---
drivers/dsp/bridge/wmd/tiomap3430_pwr.c | 33 ++
1 files changed, 20 insertions(+), 13 deletions(-)
diff --git a/drivers/dsp/bridge/wmd/tiomap3430_pwr.c
b/drivers/dsp/bridge/wmd/tiomap3430_pwr.c
index b81df8c..7aa58d1 100644
--- a/drivers/dsp/bridge/wmd/tiomap3430_pwr.c
+++ b/drivers/dsp/bridge/wmd/tiomap3430_pwr.c
@@ -204,20 +204,21 @@ DSP_STATUS SleepDSP(struct WMD_DEV_CONTEXT *pDevContext,
IN u32 dwCmd,
struct CFG_HOSTRES resources;
struct DEH_MGR *hDehMgr;
u16 usCount = TIHELEN_ACKTIMEOUT;
- enum HW_PwrState_t pwrState;
- enum HW_PwrState_t targetPwrState;
+ enum HW_PwrState_t pwrState, targetPwrState;
- status = CFG_GetHostResources(
-(struct CFG_DEVNODE *)DRV_GetFirstDevExtension(), resources);
- if (DSP_FAILED(status))
- return status;
DBG_Trace(DBG_LEVEL7, SleepDSP- Enter function \n);
- /* next, check if sleep code is valid... */
+ /* Check if sleep code is valid */
if ((dwCmd != PWR_DEEPSLEEP) (dwCmd != PWR_EMERGENCYDEEPSLEEP)) {
DBG_Trace(DBG_LEVEL7, SleepDSP- Illegal sleep command\n);
return DSP_EINVALIDARG;
}
+
+ status = CFG_GetHostResources(
+(struct CFG_DEVNODE *)DRV_GetFirstDevExtension(), resources);
+ if (DSP_FAILED(status))
+ return status;
+
switch (pDevContext-dwBrdState) {
case BRD_RUNNING:
status = HW_MBOX_saveSettings(resources.dwMboxBase);
@@ -245,7 +246,6 @@ DSP_STATUS SleepDSP(struct WMD_DEV_CONTEXT *pDevContext, IN
u32 dwCmd,
break;
case BRD_HIBERNATION:
case BRD_DSP_HIBERNATION:
- status = HW_MBOX_saveSettings(resources.dwMboxBase);
/* Already in Hibernation, so just return */
DBG_Trace(DBG_LEVEL7, SleepDSP- DSP already in
hibernation\n);
@@ -259,17 +259,22 @@ DSP_STATUS SleepDSP(struct WMD_DEV_CONTEXT *pDevContext,
IN u32 dwCmd,
SleepDSP- Bridge in Illegal state\n);
return DSP_EFAIL;
}
+
/* Get the PRCM DSP power domain status */
HW_PWR_IVA2StateGet(resources.dwPrmBase, HW_PWR_DOMAIN_DSP,
- pwrState);
- /* Wait for DSP to move into Standby state, how much time
-* should we wait?*/
+ pwrState);
+
+ /*
+* Wait for DSP to move into Standby state, how much time
+* should we wait?
+*/
while ((pwrState != targetPwrState) --usCount) {
udelay(500);
HW_PWR_IVA2StateGet(resources.dwPrmBase, HW_PWR_DOMAIN_DSP,
pwrState);
}
- if (usCount == 0) {
+
+ if (!usCount) {
DBG_Trace(DBG_LEVEL7, SleepDSP: Timed out Waiting for DSP
STANDBY %x \n, pwrState);
DEV_GetDehMgr(pDevContext-hDevObject, hDehMgr);
@@ -278,17 +283,19 @@ DSP_STATUS SleepDSP(struct WMD_DEV_CONTEXT *pDevContext,
IN u32 dwCmd,
} else {
DBG_Trace(DBG_LEVEL7, SleepDSP: DSP STANDBY Pwr state %x \n,
pwrState);
+
/* Update the Bridger Driver state */
if (enable_off_mode)
pDevContext-dwBrdState = BRD_HIBERNATION;
else
pDevContext-dwBrdState = BRD_RETENTION;
+
/* Turn off DSP Peripheral clocks */
status = DSP_PeripheralClocks_Disable(pDevContext, NULL);
if (DSP_FAILED(status))
DBG_Trace(DBG_LEVEL7, SleepDSP- FAILED\n);
}
-#endif
+#endif /* CONFIG_PM */
return status;
}
--
1.6.2.4
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Re: OMAP PM question
ext Peter Barada wrote: Kevin, I'm trying to port over the 2.6.30 OMAP PM branch on Logic's SOM, pulled from just a few days ago before the rebase to 2.6.31-rc1: http://git.kernel.org/?p=linux/kernel/git/khilman/linux-omap-pm.git;a=commit;h=e0cffc298098263630b83c458b8fce754badb9a3 Unfortunately It doesn't go into retention due to MPU_CLK being defined as virt_pcrm_set where no virt_pcrm_set exists for OMAP3. Once I changed MPU_CLK to arm_fck for OMAP3 as suggested by Rajendra in http://patchwork.kernel.org/patch/18626/ the board goes into retention, but it won't resume on a serial RX event. I wonder if Rajendra's change is correct. 1) Which config did you use on the PM tree in the 2.6.30 timeframe so can start over from a known config/board description (that goes into retention and comes back out) instead of what I rolled from the rx51 for Logic's OMAP35x SOM. Looking in arch/arm/configs, the only omap3 config that has CONFIG_PM=y is for the evm. Is this the one? 2) Is there anything special necessary to have a serial RX event force a wakeup? 3) Do you have a wake-on-timer patch that works in this tree? 4) I've noticed the board hangs after a while of inactivity on the serial power - I've tried cranking up the DEFAULT_TIMEOUT in arch/arm/mach-omap2/serial.c to (50 * HZ), and then disabling the timeout by echo 0 /sys/devices/platform/serial/8250.0/sleep_timeout, but the hang still happens after a period of inactivity - characters typed at ttyS0 don't get echoed back. How do I enable wake on serial, or is it on by default? Hi Peter, I was facing similar problems with RX51 boards. The following procedure resolved my problems. 1) use 2008q3 compiler (should work with 2009q1 also I guess, but I've not tested it) 2) Reset your tree to Kevin's PM branch. This should incorporate the latest fix http://git.kernel.org/?p=linux/kernel/git/tmlind/linux-omap-2.6.git;a=commit;h=7e7377395d6b4576341a6939bf2179f3946f2ea0 3) use omap3_pm_defconfig, Then change the CONFIG_OMAP_LL_DEBUG_UART to suit your board's serial UART (1, 2 or 3) and also the CMDLINE to suit your board. cheers, -roger -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC][PATCH 0/4] TWL6030 patch series
On Fri, Jul 24, 2009 at 09:46:27AM +0530, Shilimkar, Santosh wrote: Mark, Liam, Can you please your comments of regulator patches. I'd really like to see the ifdefs go as someone else requested earlier in the thread. Allowing both twl4030 and twl6030 support to be built simultaneously is much nicer from a maintinance perspective and will scale better as further devices are added to the family. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/1] DSPBRIDGE: expose DSP_TRACEBUF as kernel config option
From: Hiroshi DOYU hiroshi.d...@nokia.com
CONFIG_DSP_TRACEBUF is introduced as a kernel config option to save
some amount of unused memory and #ifndef DSP_TRACEBUF_DISABLED was
not easy to understand.
Signed-off-by: Hiroshi DOYU hiroshi.d...@nokia.com
---
drivers/dsp/bridge/Kconfig |7 +++
drivers/dsp/bridge/wmd/io_sm.c | 21 +
2 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/dsp/bridge/Kconfig b/drivers/dsp/bridge/Kconfig
index 2fed82c..a43b19d 100644
--- a/drivers/dsp/bridge/Kconfig
+++ b/drivers/dsp/bridge/Kconfig
@@ -34,3 +34,10 @@ config BRIDGE_DEBUG
depends on MPU_BRIDGE
help
Say Y to enable Bridge debugging capabilities
+
+config DSP_TRACEBUF
+ bool DSP Debug Trace Support
+ depends on BRIDGE_DEBUG
+ help
+ Say Y to enable DSP debugging capabilities. baseimage needs
+ to be built with debug option.
diff --git a/drivers/dsp/bridge/wmd/io_sm.c b/drivers/dsp/bridge/wmd/io_sm.c
index d8ae1f1..cd58cce 100644
--- a/drivers/dsp/bridge/wmd/io_sm.c
+++ b/drivers/dsp/bridge/wmd/io_sm.c
@@ -138,7 +138,7 @@ struct IO_MGR {
u32 dQuePowerMbxVal[MAX_PM_REQS];
u32 iQuePowerHead;
u32 iQuePowerTail;
-#ifndef DSP_TRACEBUF_DISABLED
+#ifdef CONFIG_DSP_TRACEBUF
u32 ulTraceBufferBegin; /* Trace message start address */
u32 ulTraceBufferEnd; /* Trace message end address */
u32 ulTraceBufferCurrent; /* Trace message current address */
@@ -169,9 +169,9 @@ static u32 ReadData(struct WMD_DEV_CONTEXT *hDevContext,
void *pDest,
static u32 WriteData(struct WMD_DEV_CONTEXT *hDevContext, void *pDest,
void *pSrc, u32 uSize);
static struct workqueue_struct *bridge_workqueue;
-#ifndef DSP_TRACEBUF_DISABLED
+
void PrintDSPDebugTrace(struct IO_MGR *hIOMgr);
-#endif
+
/* Bus Addr (cached kernel)*/
static DSP_STATUS registerSHMSegs(struct IO_MGR *hIOMgr,
@@ -255,7 +255,7 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr,
PREPARE_WORK(pIOMgr-io_workq, (void *)IO_DispatchPM);
/* Initialize CHNL_MGR object:*/
-#ifndef DSP_TRACEBUF_DISABLED
+#ifdef CONFIG_DSP_TRACEBUF
pIOMgr-pMsg = NULL;
#endif
pIOMgr-hChnlMgr = hChnlMgr;
@@ -330,7 +330,7 @@ DSP_STATUS WMD_IO_Destroy(struct IO_MGR *hIOMgr)
/* Linux function to uninstall ISR */
free_irq(INT_MAIL_MPU_IRQ, (void *)hIOMgr);
(void)DPC_Destroy(hIOMgr-hDPC);
-#ifndef DSP_TRACEBUF_DISABLED
+#ifdef CONFIG_DSP_TRACEBUF
if (hIOMgr-pMsg)
MEM_Free(hIOMgr-pMsg);
#endif
@@ -448,7 +448,7 @@ func_cont1:
}
}
if (DSP_SUCCEEDED(status)) {
-#ifndef DSP_TRACEBUF_DISABLED
+#ifdef CONFIG_DSP_TRACEBUF
status = COD_GetSymValue(hCodMan, DSP_TRACESEC_END, ulShm0End);
DBG_Trace(DBG_LEVEL7, _BRIDGE_TRACE_END value = %x \n,
ulShm0End);
@@ -775,7 +775,7 @@ func_cont:
0x%x\n, hMsgMgr-uMaxMsgs);
memset((void *) hIOMgr-pSharedMem, 0, sizeof(struct SHM));
}
-#ifndef DSP_TRACEBUF_DISABLED
+#ifdef CONFIG_DSP_TRACEBUF
if (DSP_SUCCEEDED(status)) {
/* Get the start address of trace buffer */
if (DSP_SUCCEEDED(status)) {
@@ -989,15 +989,12 @@ void IO_DPC(IN OUT void *pRefData)
IO_DispatchMsg(pIOMgr, pMsgMgr);
}
#endif
-#ifndef DSP_TRACEBUF_DISABLED
+#ifdef CONFIG_DSP_TRACEBUF
if (pIOMgr-wIntrVal MBX_DBG_CLASS) {
/* notify DSP Trace message */
if (pIOMgr-wIntrVal MBX_DBG_SYSPRINTF)
PrintDSPDebugTrace(pIOMgr);
}
-#endif
-
-#ifndef DSP_TRACEBUF_DISABLED
PrintDSPDebugTrace(pIOMgr);
#endif
}
@@ -1767,7 +1764,7 @@ DSP_STATUS WMD_IO_GetProcLoad(IN struct IO_MGR *hIOMgr,
return DSP_SOK;
}
-#ifndef DSP_TRACEBUF_DISABLED
+#ifdef CONFIG_DSP_TRACEBUF
void PrintDSPDebugTrace(struct IO_MGR *hIOMgr)
{
u32 ulNewMessageLength = 0, ulGPPCurPointer;
--
1.6.0.4
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Re: [PATCH]OMAP4: McSPI Support for OMAP4430
David, This patch adds McSPI support for OMAP4430 SDP platform. All the base addresses are changed between OMAP1/2/3 and OMAP4.The fields of the resource structures are filled at runtime to have McSPI support on OMAP4. Signed-off-by: Syed Rafiuddin rafiuddin.s...@ti.com Acked-by: Kevin Hilman khil...@deeprootsystems.com Acked-by: Tony Lindgren t...@atomide.com Acked-by: David Brownell davi...@pacbell.net Acked-by: Santosh Shilimkar santosh.shilim...@ti.com --- Haven't seen any comment on my patch, but didn't see it in git either. Is there anything that I need to resolve? Else can this patch get merged. Regards, Syed Rafiuddin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RESUBMIT][PATCH-v2][RFC] OMAP4: I2C Support for OMAP4430
Hi Ben, This patch adds OMAP4 support to the I2C driver. All I2C register addresses are different between OMAP1/2/3 and OMAP4. In order to not have #ifdef's at various places in code, as well as to support multi-OMAP build, Array's are created to hold the register addresses. Signed-off-by: Syed Rafiuddin rafiuddin.s...@ti.com --- No comment received on this patch, Is there anything that I need to resolve? Else can this patch get merged. Regards, Syed Rafiuddin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/44] includecheck: fix multiple includes
On Thu, Jul 09, 2009 at 06:28:31AM +0200, ext Jaswinder Singh Rajput wrote: On Wed, 2009-07-08 at 22:13 +0100, Russell King wrote: On Wed, Jul 08, 2009 at 11:30:59PM +0530, Jaswinder Singh Rajput wrote: I am still waiting ACK/NAK for : includecheck fix: arm, misc.c includecheck fix: arm, atomic.h includecheck fix: arm, board-dm355-evm.c includecheck fix: arm, board-dm355-leopard.c includecheck fix: arm, board-dm644x-evm.c includecheck fix: arm, board-dm646x-evm.c includecheck fix: arm, board-sffsdr.c includecheck fix: arm, mach-mx3/devices.c includecheck fix: arm, mach-omap1/mcbsp.c includecheck fix: arm, mach-omap2/mcbsp.c includecheck fix: arm, plat-s3c64xx/pm.c includecheck fix: arm, plat-stmp3xxx/pinmux.c You're still waiting because apparantly you never sent this set anywhere near any ARM people before. For the first two, I'll ack them: Acked-by: Russell King rmk+ker...@arm.linux.org.uk The remainder look sane to me, but you'll have to seek acks from the individual platform maintainer(s). OK, adding some more ARM people and ARM lists to get remaining ACK/NAK. Patches are already posted to LKML and also available at : http://git.kernel.org/?p=linux/kernel/git/jaswinder/headers-check-2.6.git;a=summary In case if you are not able to find these patches let me know. Thanks, In behalf of mach-omap[1,2]/mcbsp.c: Acked-by: Eduardo Valentin eduardo.valen...@nokia.com -- JSR -- Eduardo Valentin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/44] includecheck: fix multiple includes
Hello all, On Fri, 2009-07-24 at 17:45 +0300, Eduardo Valentin wrote: On Thu, Jul 09, 2009 at 06:28:31AM +0200, ext Jaswinder Singh Rajput wrote: On Wed, 2009-07-08 at 22:13 +0100, Russell King wrote: On Wed, Jul 08, 2009 at 11:30:59PM +0530, Jaswinder Singh Rajput wrote: I am still waiting ACK/NAK for : includecheck fix: arm, misc.c includecheck fix: arm, atomic.h includecheck fix: arm, board-dm355-evm.c includecheck fix: arm, board-dm355-leopard.c includecheck fix: arm, board-dm644x-evm.c includecheck fix: arm, board-dm646x-evm.c includecheck fix: arm, board-sffsdr.c includecheck fix: arm, mach-mx3/devices.c includecheck fix: arm, mach-omap1/mcbsp.c includecheck fix: arm, mach-omap2/mcbsp.c includecheck fix: arm, plat-s3c64xx/pm.c includecheck fix: arm, plat-stmp3xxx/pinmux.c You're still waiting because apparantly you never sent this set anywhere near any ARM people before. For the first two, I'll ack them: Acked-by: Russell King rmk+ker...@arm.linux.org.uk The remainder look sane to me, but you'll have to seek acks from the individual platform maintainer(s). OK, adding some more ARM people and ARM lists to get remaining ACK/NAK. Patches are already posted to LKML and also available at : http://git.kernel.org/?p=linux/kernel/git/jaswinder/headers-check-2.6.git;a=summary In case if you are not able to find these patches let me know. Thanks, In behalf of mach-omap[1,2]/mcbsp.c: Acked-by: Eduardo Valentin eduardo.valen...@nokia.com These patches are still not applied anywhere, If you want you can apply respective patch in your respective trees. Thanks, -- JSR -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC][PATCH 0/3]ARM:OMAP4 iommu-provide support for OMAP4
Hi, This series of patches provides IOMMU support for OMAP4 co-processors (Ducati and Tesla). This series is based of kernel.org 2.6.31-rc1 kernel. [PATCH 1/3] ARM:OMAP4 iommu:changes in iommu for OMAP4 [PATCH 2/3] ARM:OMAP4 iommu:add omap4 support in iommu [PATCH 3/3] ARM:OMAP4 iommu:provide build support for omap4 iommu Summary of changes = arch/arm/mach-omap2/Makefile |2 +- arch/arm/mach-omap2/iommu2.c |8 +-- arch/arm/mach-omap2/omap4-iommu.c | 112 arch/arm/plat-omap/Kconfig |8 +-- arch/arm/plat-omap/include/mach/irqs.h |2 +- arch/arm/plat-omap/iommu.c | 12 +--- 6 files changed, 9 insertions(+), 135 deletions(-) The patches can be pulled from git://dev.omapzoom.org/pub/scm/tisyslink/kernel-syslink.git upstream May I request you to please provide your comments. Thank you, Best regards, Hari -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC][PATCH 1/3] ARM:OMAP4 iommu:changes in iommu for OMAP4
This patch has the changes to iommu module to make
iommu functional on OMAP4 simulator. The changes
included using stubbed clock interface and commenting
out reading the MMU soft reset register.
Signed-off-by: Hari Kanigeri h-kanige...@ti.com
---
arch/arm/mach-omap2/iommu2.c |8 ++--
arch/arm/plat-omap/iommu.c | 12 +---
2 files changed, 15 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
index 015f22a..01cb15d 100644
--- a/arch/arm/mach-omap2/iommu2.c
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -80,12 +80,16 @@ static int omap2_iommu_enable(struct iommu *obj)
if (l MMU_SYS_RESETDONE)
break;
} while (time_after(jiffies, timeout));
-
+/* FIXME: Hack till the reading the MMU status register
+ * is resolved in Simulator. Simulator doesn't update
+ * the STATUS register.
+ */
+#ifndef CONFIG_ARCH_OMAP4
if (!(l MMU_SYS_RESETDONE)) {
dev_err(obj-dev, can't take mmu out of reset\n);
return -ENODEV;
}
-
+#endif
l = iommu_read_reg(obj, MMU_REVISION);
dev_info(obj-dev, %s: version %d.%d\n, obj-name,
(l 4) 0xf, l 0xf);
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index 4cf449f..b62a087 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -861,9 +861,15 @@ static int __devinit omap_iommu_probe(struct
platform_device *pdev)
if (!obj)
return -ENOMEM;
- obj-clk = clk_get(pdev-dev, pdata-clk_name);
- if (IS_ERR(obj-clk))
- goto err_clk;
+ /*
+* FIX-ME: Replace with correct clk node when clk
+* framework is available
+*/
+ if (!cpu_is_omap44xx()) {
+ obj-clk = clk_get(pdev-dev, pdata-clk_name);
+ if (IS_ERR(obj-clk))
+ goto err_clk;
+ }
obj-nr_tlb_entries = pdata-nr_tlb_entries;
obj-name = pdata-name;
--
1.5.4.3
Thank you,
Best regards,
Hari
0001-ARM-OMAP4-iommu-changes-in-iommu-for-OMAP4.patch
Description: 0001-ARM-OMAP4-iommu-changes-in-iommu-for-OMAP4.patch
[RFC][PATCH 2/3] ARM:OMAP4 iommu:add omap4 support in iommu
This patch adds omap4 support in iommu
module. This creates OMAP4 platform specific file
for iommu and defines the Ducati MMU fault interrupt.
Signed-off-by: Hari Kanigeri h-kanige...@ti.com
---
arch/arm/mach-omap2/omap4-iommu.c | 112
arch/arm/plat-omap/include/mach/irqs.h |2 +-
2 files changed, 113 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-omap2/omap4-iommu.c
diff --git a/arch/arm/mach-omap2/omap4-iommu.c
b/arch/arm/mach-omap2/omap4-iommu.c
new file mode 100644
index 000..5a782df
--- /dev/null
+++ b/arch/arm/mach-omap2/omap4-iommu.c
@@ -0,0 +1,112 @@
+/*
+ * omap iommu: omap4 device registration
+ *
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Written by Hari Kanigeri h-kanige...@ti.com
+ *
+ * Added support for OMAP4. This is based on original file
+ * omap3-iommu.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/platform_device.h
+
+#include mach/iommu.h
+#include mach/irqs.h
+
+#define OMAP4_MMU1_BASE0x55082000
+#define OMAP4_MMU2_BASE0x4A066000
+
+#define OMAP4_MMU1_IRQ INT_44XX_DUCATI_MMU_IRQ
+#define OMAP4_MMU2_IRQ INT_44XX_DSP_MMU
+
+
+
+static unsigned long iommu_base[] __initdata = {
+ OMAP4_MMU1_BASE,
+ OMAP4_MMU2_BASE,
+};
+
+static int iommu_irq[] __initdata = {
+ OMAP4_MMU1_IRQ,
+ OMAP4_MMU2_IRQ,
+};
+
+static const struct iommu_platform_data omap4_iommu_pdata[] __initconst = {
+ {
+ .name = ducati,
+ .nr_tlb_entries = 32,
+ .clk_name = ducati_ick,
+ },
+#if defined(CONFIG_MPU_TESLA_IOMMU)
+ {
+ .name = tesla,
+ .nr_tlb_entries = 32,
+ .clk_name = tesla_ick,
+ },
+#endif
+};
+#define NR_IOMMU_DEVICES ARRAY_SIZE(omap4_iommu_pdata)
+
+static struct platform_device *omap4_iommu_pdev[NR_IOMMU_DEVICES];
+
+static int __init omap4_iommu_init(void)
+{
+ int i, err;
+
+ for (i = 0; i NR_IOMMU_DEVICES; i++) {
+ struct platform_device *pdev;
+ struct resource res[2];
+
+ pdev = platform_device_alloc(omap-iommu, i);
+ if (!pdev) {
+ err = -ENOMEM;
+ goto err_out;
+ }
+
+ memset(res, 0, sizeof(res));
+ res[0].start = iommu_base[i];
+ res[0].end = iommu_base[i] + MMU_REG_SIZE - 1;
+ res[0].flags = IORESOURCE_MEM;
+ res[1].start = res[1].end = iommu_irq[i];
+ res[1].flags = IORESOURCE_IRQ;
+
+ err = platform_device_add_resources(pdev, res,
+ ARRAY_SIZE(res));
+ if (err)
+ goto err_out;
+ err = platform_device_add_data(pdev, omap4_iommu_pdata[i],
+ sizeof(omap4_iommu_pdata[0]));
+ if (err)
+ goto err_out;
+ err = platform_device_add(pdev);
+ if (err)
+ goto err_out;
+ omap4_iommu_pdev[i] = pdev;
+ }
+ return 0;
+
+err_out:
+ while (i--)
+ platform_device_put(omap4_iommu_pdev[i]);
+ return err;
+}
+module_init(omap4_iommu_init);
+
+static void __exit omap4_iommu_exit(void)
+{
+ int i;
+
+ for (i = 0; i NR_IOMMU_DEVICES; i++)
+ platform_device_unregister(omap4_iommu_pdev[i]);
+}
+module_exit(omap4_iommu_exit);
+
+MODULE_AUTHOR(Hiroshi DOYU, Hari Kanigeri);
+MODULE_DESCRIPTION(omap iommu: omap4 device registration);
+MODULE_LICENSE(GPL v2);
+
diff --git a/arch/arm/plat-omap/include/mach/irqs.h
b/arch/arm/plat-omap/include/mach/irqs.h
index fb7cb77..34b6d09 100644
--- a/arch/arm/plat-omap/include/mach/irqs.h
+++ b/arch/arm/plat-omap/include/mach/irqs.h
@@ -511,7 +511,7 @@
#define INT_44XX_TLL_IRQ (78 + IRQ_GIC_START)
#define INT_44XX_PARTHASH_IRQ (79 + IRQ_GIC_START)
#define INT_44XX_MMC3_IRQ (94 + IRQ_GIC_START)
-
+#define INT_44XX_DUCATI_MMU_IRQ(100 + IRQ_GIC_START)
/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
* 16 MPUIO lines */
--
1.5.4.3
Thank you,
Best regards,
Hari
0002-ARM-OMAP4-iommu-add-omap4-support-in-iommu.patch
Description: 0002-ARM-OMAP4-iommu-add-omap4-support-in-iommu.patch
[RFC][PATCH 3/3]ARM:OMAP4 iommu:provide build support for omap4 iommu
This patch provides build support to build OMAP4 IOMMU module. This also adds the changes to Kconfig file to make iommu option visible in menuconfig. Signed-off-by: Hari Kanigeri h-kanige...@ti.com --- arch/arm/mach-omap2/Makefile |2 +- arch/arm/plat-omap/Kconfig |8 ++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 735bae5..59e0865 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -41,7 +41,7 @@ obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o iommu-y+= iommu2.o iommu-$(CONFIG_ARCH_OMAP3) += omap3-iommu.o - +iommu-$(CONFIG_ARCH_OMAP4) += omap4-iommu.o obj-$(CONFIG_OMAP_IOMMU) += $(iommu-y) # Specific board support diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index efe85d0..00d7a1e 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -118,8 +118,12 @@ config OMAP_MBOX_FWK DSP, IVA1.0 and IVA2 in OMAP1/2/3. config OMAP_IOMMU - tristate - + tristate iommu +depends on ARCH_OMAP + default y + help + Select this option if you want to use IOMMU support for the + Camera in OMAP3, and for Ducati processor in OMAP4. choice prompt System timer default OMAP_MPU_TIMER -- 1.5.4.3 Thank you, Best regards, Hari 0003-ARM-OMAP4-iommu-provide-build-support-for-omap4-iom.patch Description: 0003-ARM-OMAP4-iommu-provide-build-support-for-omap4-iom.patch
RE: [PATCH 1/1] DSPBRIDGE: expose DSP_TRACEBUF as kernel config option
Hi Doyu-san,
CONFIG_DSP_TRACEBUF is introduced as a kernel config option to save
some amount of unused memory and #ifndef DSP_TRACEBUF_DISABLED was
not easy to understand.
I think we just use the Bridge DEBUG flag that is used in Bridge instead of
introducing a new flag.
Thank you,
Best regards,
Hari
-Original Message-
From: Hiroshi DOYU [mailto:hiroshi.d...@nokia.com]
Sent: Friday, July 24, 2009 5:24 AM
To: linux-omap@vger.kernel.org
Cc: ameya.pala...@nokia.com; Kanigeri, Hari; Guzman Lugo, Fernando;
Ramirez Luna, Omar; Hiroshi DOYU
Subject: [PATCH 1/1] DSPBRIDGE: expose DSP_TRACEBUF as kernel config
option
From: Hiroshi DOYU hiroshi.d...@nokia.com
CONFIG_DSP_TRACEBUF is introduced as a kernel config option to save
some amount of unused memory and #ifndef DSP_TRACEBUF_DISABLED was
not easy to understand.
Signed-off-by: Hiroshi DOYU hiroshi.d...@nokia.com
---
drivers/dsp/bridge/Kconfig |7 +++
drivers/dsp/bridge/wmd/io_sm.c | 21 +
2 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/dsp/bridge/Kconfig b/drivers/dsp/bridge/Kconfig
index 2fed82c..a43b19d 100644
--- a/drivers/dsp/bridge/Kconfig
+++ b/drivers/dsp/bridge/Kconfig
@@ -34,3 +34,10 @@ config BRIDGE_DEBUG
depends on MPU_BRIDGE
help
Say Y to enable Bridge debugging capabilities
+
+config DSP_TRACEBUF
+ bool DSP Debug Trace Support
+ depends on BRIDGE_DEBUG
+ help
+ Say Y to enable DSP debugging capabilities. baseimage needs
+ to be built with debug option.
diff --git a/drivers/dsp/bridge/wmd/io_sm.c
b/drivers/dsp/bridge/wmd/io_sm.c
index d8ae1f1..cd58cce 100644
--- a/drivers/dsp/bridge/wmd/io_sm.c
+++ b/drivers/dsp/bridge/wmd/io_sm.c
@@ -138,7 +138,7 @@ struct IO_MGR {
u32 dQuePowerMbxVal[MAX_PM_REQS];
u32 iQuePowerHead;
u32 iQuePowerTail;
-#ifndef DSP_TRACEBUF_DISABLED
+#ifdef CONFIG_DSP_TRACEBUF
u32 ulTraceBufferBegin; /* Trace message start address */
u32 ulTraceBufferEnd; /* Trace message end address */
u32 ulTraceBufferCurrent; /* Trace message current address */
@@ -169,9 +169,9 @@ static u32 ReadData(struct WMD_DEV_CONTEXT
*hDevContext, void *pDest,
static u32 WriteData(struct WMD_DEV_CONTEXT *hDevContext, void *pDest,
void *pSrc, u32 uSize);
static struct workqueue_struct *bridge_workqueue;
-#ifndef DSP_TRACEBUF_DISABLED
+
void PrintDSPDebugTrace(struct IO_MGR *hIOMgr);
-#endif
+
/* Bus Addr (cached kernel)*/
static DSP_STATUS registerSHMSegs(struct IO_MGR *hIOMgr,
@@ -255,7 +255,7 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr,
PREPARE_WORK(pIOMgr-io_workq, (void *)IO_DispatchPM);
/* Initialize CHNL_MGR object:*/
-#ifndef DSP_TRACEBUF_DISABLED
+#ifdef CONFIG_DSP_TRACEBUF
pIOMgr-pMsg = NULL;
#endif
pIOMgr-hChnlMgr = hChnlMgr;
@@ -330,7 +330,7 @@ DSP_STATUS WMD_IO_Destroy(struct IO_MGR *hIOMgr)
/* Linux function to uninstall ISR */
free_irq(INT_MAIL_MPU_IRQ, (void *)hIOMgr);
(void)DPC_Destroy(hIOMgr-hDPC);
-#ifndef DSP_TRACEBUF_DISABLED
+#ifdef CONFIG_DSP_TRACEBUF
if (hIOMgr-pMsg)
MEM_Free(hIOMgr-pMsg);
#endif
@@ -448,7 +448,7 @@ func_cont1:
}
}
if (DSP_SUCCEEDED(status)) {
-#ifndef DSP_TRACEBUF_DISABLED
+#ifdef CONFIG_DSP_TRACEBUF
status = COD_GetSymValue(hCodMan, DSP_TRACESEC_END,
ulShm0End);
DBG_Trace(DBG_LEVEL7, _BRIDGE_TRACE_END value = %x \n,
ulShm0End);
@@ -775,7 +775,7 @@ func_cont:
0x%x\n, hMsgMgr-uMaxMsgs);
memset((void *) hIOMgr-pSharedMem, 0, sizeof(struct SHM));
}
-#ifndef DSP_TRACEBUF_DISABLED
+#ifdef CONFIG_DSP_TRACEBUF
if (DSP_SUCCEEDED(status)) {
/* Get the start address of trace buffer */
if (DSP_SUCCEEDED(status)) {
@@ -989,15 +989,12 @@ void IO_DPC(IN OUT void *pRefData)
IO_DispatchMsg(pIOMgr, pMsgMgr);
}
#endif
-#ifndef DSP_TRACEBUF_DISABLED
+#ifdef CONFIG_DSP_TRACEBUF
if (pIOMgr-wIntrVal MBX_DBG_CLASS) {
/* notify DSP Trace message */
if (pIOMgr-wIntrVal MBX_DBG_SYSPRINTF)
PrintDSPDebugTrace(pIOMgr);
}
-#endif
-
-#ifndef DSP_TRACEBUF_DISABLED
PrintDSPDebugTrace(pIOMgr);
#endif
}
@@ -1767,7 +1764,7 @@ DSP_STATUS WMD_IO_GetProcLoad(IN struct IO_MGR
*hIOMgr,
return DSP_SOK;
}
-#ifndef DSP_TRACEBUF_DISABLED
+#ifdef CONFIG_DSP_TRACEBUF
void PrintDSPDebugTrace(struct IO_MGR *hIOMgr)
{
u32 ulNewMessageLength = 0, ulGPPCurPointer;
--
1.6.0.4
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[RFC/RFT v2 0/4] PRCM interrupt handler updates/fixes/cleanups
This series incoporates various changes/updates/fixes to the PRCM interrupt handler. Applies to current PM branch. These could use some extra review and especially some testing. I did some basic testing on 3430SDP (es3.0) and Zoom2 (es3.1) Updates from previous series: I added a reworked version of Vikram's USBHOST fix. Kevin Jon Hunter (1): OMAP3: PM: Prevent hang in prcm_interrupt_handler Paul Walmsley (2): OMAP3: PM: PRCM interrupt: check MPUGRPSEL register OMAP3: PM: PRCM interrupt: only handle selected PRCM interrupts Vikram Pandita (1): OMAP3: PM: USBHOST: clear wakeup events on both hosts arch/arm/mach-omap2/pm34xx.c | 177 +++--- 1 files changed, 96 insertions(+), 81 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC/RFT 1/4] OMAP3: PM: Prevent hang in prcm_interrupt_handler
From: Jon Hunter jon-hun...@ti.com
There are two scenarios where a race condition could result in a hang
in the prcm_interrupt handler. These are:
1). Waiting for PRM_IRQSTATUS_MPU register to clear.
Bit 0 of the PRM_IRQSTATUS_MPU register indicates that a wake-up event
is pending for the MPU. This bit can only be cleared if the all the
wake-up events latched in the various PM_WKST_x registers have been
cleared. If a wake-up event occurred during the processing of the prcm
interrupt handler, after the corresponding PM_WKST_x register was
checked but before the PRM_IRQSTATUS_MPU was cleared, then the CPU
would be stuck forever waiting for bit 0 in PRM_IRQSTATUS_MPU to be
cleared.
2). Waiting for the PM_WKST_x register to clear.
Some power domains have more than one wake-up source. The PM_WKST_x
registers indicate the source of a wake-up event and need to be cleared
after a wake-up event occurs. When the PM_WKST_x registers are read and
before they are cleared, it is possible that another wake-up event
could occur causing another bit to be set in one of the PM_WKST_x
registers. If this did occur after reading a PM_WKST_x register then
the CPU would miss this event and get stuck forever in a loop waiting
for that PM_WKST_x register to clear.
This patch address the above race conditions that would result in a
hang.
Signed-off-by: Jon Hunter jon-hun...@ti.com
---
arch/arm/mach-omap2/pm34xx.c | 143 ++
1 files changed, 60 insertions(+), 83 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 14f10bc..f6cc71a 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -194,97 +194,74 @@ static void omap3_save_secure_ram_context(u32
target_mpu_state)
}
}
-/* PRCM Interrupt Handler for wakeups */
-static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
+/*
+ * PRCM Interrupt Handler Helper Function
+ *
+ * The purpose of this function is to clear any wake-up events latched
+ * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
+ * may occur whilst attempting to clear a PM_WKST_x register and thus
+ * set another bit in this register. A while loop is used to ensure
+ * that any peripheral wake-up events occurring while attempting to
+ * clear the PM_WKST_x are detected and cleared.
+ */
+static void prcm_clear_mod_irqs(s16 module, u8 regs)
{
- u32 wkst, irqstatus_mpu;
- u32 fclk, iclk;
-
- /* WKUP */
- wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST);
- if (wkst) {
- iclk = cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
- fclk = cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
- cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_ICLKEN);
- cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_FCLKEN);
- prm_write_mod_reg(wkst, WKUP_MOD, PM_WKST);
- while (prm_read_mod_reg(WKUP_MOD, PM_WKST))
- cpu_relax();
- cm_write_mod_reg(iclk, WKUP_MOD, CM_ICLKEN);
- cm_write_mod_reg(fclk, WKUP_MOD, CM_FCLKEN);
- }
+ u32 wkst, fclk, iclk;
+ u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
+ u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
+ u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
- /* CORE */
- wkst = prm_read_mod_reg(CORE_MOD, PM_WKST1);
- if (wkst) {
- iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
- fclk = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
- cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN1);
- cm_set_mod_reg_bits(wkst, CORE_MOD, CM_FCLKEN1);
- prm_write_mod_reg(wkst, CORE_MOD, PM_WKST1);
- while (prm_read_mod_reg(CORE_MOD, PM_WKST1))
- cpu_relax();
- cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN1);
- cm_write_mod_reg(fclk, CORE_MOD, CM_FCLKEN1);
- }
- wkst = prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3);
+ wkst = prm_read_mod_reg(module, wkst_off);
if (wkst) {
- iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
- fclk = cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
- cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN3);
- cm_set_mod_reg_bits(wkst, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
- prm_write_mod_reg(wkst, CORE_MOD, OMAP3430ES2_PM_WKST3);
- while (prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3))
- cpu_relax();
- cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN3);
- cm_write_mod_reg(fclk, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
- }
-
- /* PER */
- wkst = prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST);
- if (wkst) {
- iclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
- fclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
-
[RFC/RFT 2/4] OMAP3: PM: PRCM interrupt: check MPUGRPSEL register
From: Paul Walmsley p...@pwsan.com
PM_WKST register contents should be ANDed with the contents of the
MPUGRPSEL registers. Otherwise the MPU PRCM interrupt handler could
wind up clearing wakeup events meant for the IVA PRCM interrupt
handler. For a production version of this patch, we should not read
MPUGRPSEL from the PRM, since those reads are very slow; rather, we
should use a cached version from struct powerdomain (not yet
implemented)
---
arch/arm/mach-omap2/pm34xx.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index f6cc71a..25372b7 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -210,8 +210,11 @@ static void prcm_clear_mod_irqs(s16 module, u8 regs)
u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
+ u16 grpsel_off = (regs == 3) ?
+ OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
wkst = prm_read_mod_reg(module, wkst_off);
+ wkst = prm_read_mod_reg(module, grpsel_off);
if (wkst) {
iclk = cm_read_mod_reg(module, iclk_off);
fclk = cm_read_mod_reg(module, fclk_off);
--
1.6.3.3
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[RFC/RFT 3/4] OMAP3: PM: PRCM interrupt: only handle selected PRCM interrupts
From: Paul Walmsley p...@pwsan.com
Clearing wakeup sources is now only done when the PRM indicates a
wakeup source interrupt. Since we don't handle any other types of
PRCM interrupts right now, warn if we get any other type of PRCM
interrupt. Either code needs to be added to the PRCM interrupt
handler to react to these, or these other interrupts should be masked
off at init.
---
arch/arm/mach-omap2/pm34xx.c | 46 +
1 files changed, 37 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 25372b7..348a683 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -204,7 +204,7 @@ static void omap3_save_secure_ram_context(u32
target_mpu_state)
* that any peripheral wake-up events occurring while attempting to
* clear the PM_WKST_x are detected and cleared.
*/
-static void prcm_clear_mod_irqs(s16 module, u8 regs)
+static int prcm_clear_mod_irqs(s16 module, u8 regs)
{
u32 wkst, fclk, iclk;
u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
@@ -212,6 +212,7 @@ static void prcm_clear_mod_irqs(s16 module, u8 regs)
u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
u16 grpsel_off = (regs == 3) ?
OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
+ int c = 0;
wkst = prm_read_mod_reg(module, wkst_off);
wkst = prm_read_mod_reg(module, grpsel_off);
@@ -223,10 +224,28 @@ static void prcm_clear_mod_irqs(s16 module, u8 regs)
cm_set_mod_reg_bits(wkst, module, fclk_off);
prm_write_mod_reg(wkst, module, wkst_off);
wkst = prm_read_mod_reg(module, wkst_off);
+ c++;
}
cm_write_mod_reg(iclk, module, iclk_off);
cm_write_mod_reg(fclk, module, fclk_off);
}
+
+ return c;
+}
+
+static int _prcm_int_handle_wakeup(void)
+{
+ int c;
+
+ c = prcm_clear_mod_irqs(WKUP_MOD, 1);
+ c += prcm_clear_mod_irqs(CORE_MOD, 1);
+ c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
+ if (omap_rev() OMAP3430_REV_ES1_0) {
+ c += prcm_clear_mod_irqs(CORE_MOD, 3);
+ c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
+ }
+
+ return c;
}
/*
@@ -249,18 +268,27 @@ static void prcm_clear_mod_irqs(s16 module, u8 regs)
static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
{
u32 irqstatus_mpu;
+ int c = 0;
do {
- prcm_clear_mod_irqs(WKUP_MOD, 1);
- prcm_clear_mod_irqs(CORE_MOD, 1);
- prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
- if (omap_rev() OMAP3430_REV_ES1_0) {
- prcm_clear_mod_irqs(CORE_MOD, 3);
- prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
- }
-
irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+
+ if (irqstatus_mpu (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) {
+ c = _prcm_int_handle_wakeup();
+
+ /*
+* Is the MPU PRCM interrupt handler racing with the
+* IVA2 PRCM interrupt handler ?
+*/
+ WARN(c == 0, prcm: WARNING: PRCM indicated MPU wakeup
+but no wakeup sources are marked\n);
+ } else {
+ /* XXX we need to expand our PRCM interrupt handler */
+ WARN(1, prcm: WARNING: PRCM interrupt received, but
+no code to handle it (%08x)\n, irqstatus_mpu);
+ }
+
prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
--
1.6.3.3
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[RFC/RFT 4/4] OMAP3: PM: USBHOST: clear wakeup events on both hosts
From: Vikram Pandita vikram.pand...@ti.com
USBHOST module has 2 fclocks (for HOST1 and HOST2), only one iclock
and only a single bit in the WKST register to indicate a wakeup event.
Because of the single WKST bit, we cannot know whether a wakeup event
was on HOST1 or HOST2, so enable both fclocks before clearing the
wakeup event to ensure both hosts can properly clear the event.
Signed-off-by: Vikram Pandita vikram.pand...@ti.com
---
arch/arm/mach-omap2/pm34xx.c | 13 ++---
1 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 348a683..9ce651a 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -206,7 +206,7 @@ static void omap3_save_secure_ram_context(u32
target_mpu_state)
*/
static int prcm_clear_mod_irqs(s16 module, u8 regs)
{
- u32 wkst, fclk, iclk;
+ u32 wkst, fclk, iclk, clken;
u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
@@ -220,8 +220,15 @@ static int prcm_clear_mod_irqs(s16 module, u8 regs)
iclk = cm_read_mod_reg(module, iclk_off);
fclk = cm_read_mod_reg(module, fclk_off);
while (wkst) {
- cm_set_mod_reg_bits(wkst, module, iclk_off);
- cm_set_mod_reg_bits(wkst, module, fclk_off);
+ clken = wkst;
+ cm_set_mod_reg_bits(clken, module, iclk_off);
+ /*
+* For USBHOST, we don't know whether HOST1 or
+* HOST2 woke us up, so enable both f-clocks
+*/
+ if (module == OMAP3430ES2_USBHOST_MOD)
+ clken |= 1 OMAP3430ES2_EN_USBHOST2_SHIFT;
+ cm_set_mod_reg_bits(clken, module, fclk_off);
prm_write_mod_reg(wkst, module, wkst_off);
wkst = prm_read_mod_reg(module, wkst_off);
c++;
--
1.6.3.3
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Re: [PATCH 1/1] DSPBRIDGE: expose DSP_TRACEBUF as kernel config option
Hi Hari, From: ext Kanigeri, Hari h-kanige...@ti.com Subject: RE: [PATCH 1/1] DSPBRIDGE: expose DSP_TRACEBUF as kernel config option Date: Fri, 24 Jul 2009 19:28:47 +0200 Hi Doyu-san, CONFIG_DSP_TRACEBUF is introduced as a kernel config option to save some amount of unused memory and #ifndef DSP_TRACEBUF_DISABLED was not easy to understand. I think we just use the Bridge DEBUG flag that is used in Bridge instead of introducing a new flag. It might be better if CONFIG_DSP_TRACEBUF had the dependecy on DEBUG/CONFIG_BRIDGE_DEBUG, but it's not unfortunately. The problem here is that now all TRACEBUF code is always compiled in in spite of setting DEBUG. It doesn't print anything, but just wastes some memory. I'll remove a new Kconfig entry and just add the dependency of CONFIG_DSP_TRACEBUF on CONFIG_BRIDGE_DEBUG. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC][PATCH 3/3]ARM:OMAP4 iommu:provide build support for omap4 iommu
From: ext Kanigeri, Hari h-kanige...@ti.com Subject: [RFC][PATCH 3/3]ARM:OMAP4 iommu:provide build support for omap4 iommu Date: Fri, 24 Jul 2009 19:22:56 +0200 This patch provides build support to build OMAP4 IOMMU module. This also adds the changes to Kconfig file to make iommu option visible in menuconfig. Signed-off-by: Hari Kanigeri h-kanige...@ti.com --- arch/arm/mach-omap2/Makefile |2 +- arch/arm/plat-omap/Kconfig |8 ++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 735bae5..59e0865 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -41,7 +41,7 @@ obj-$(CONFIG_ARCH_OMAP3)+= clock34xx.o iommu-y += iommu2.o iommu-$(CONFIG_ARCH_OMAP3) += omap3-iommu.o - +iommu-$(CONFIG_ARCH_OMAP4) += omap4-iommu.o obj-$(CONFIG_OMAP_IOMMU) += $(iommu-y) # Specific board support diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index efe85d0..00d7a1e 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -118,8 +118,12 @@ config OMAP_MBOX_FWK DSP, IVA1.0 and IVA2 in OMAP1/2/3. config OMAP_IOMMU - tristate - + tristate iommu +depends on ARCH_OMAP Is the above dependecy necessary? + default y + help + Select this option if you want to use IOMMU support for the + Camera in OMAP3, and for Ducati processor in OMAP4. So here, it goes visible because iommu will be an independent character device, right? choice prompt System timer default OMAP_MPU_TIMER -- 1.5.4.3 Thank you, Best regards, Hari -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC][PATCH 2/3] ARM:OMAP4 iommu:add omap4 support in iommu
From: ext Kanigeri, Hari h-kanige...@ti.com
Subject: [RFC][PATCH 2/3] ARM:OMAP4 iommu:add omap4 support in iommu
Date: Fri, 24 Jul 2009 19:22:32 +0200
This patch adds omap4 support in iommu
module. This creates OMAP4 platform specific file
for iommu and defines the Ducati MMU fault interrupt.
Signed-off-by: Hari Kanigeri h-kanige...@ti.com
---
arch/arm/mach-omap2/omap4-iommu.c | 112
arch/arm/plat-omap/include/mach/irqs.h |2 +-
2 files changed, 113 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-omap2/omap4-iommu.c
diff --git a/arch/arm/mach-omap2/omap4-iommu.c
b/arch/arm/mach-omap2/omap4-iommu.c
new file mode 100644
index 000..5a782df
--- /dev/null
+++ b/arch/arm/mach-omap2/omap4-iommu.c
@@ -0,0 +1,112 @@
+/*
+ * omap iommu: omap4 device registration
+ *
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Written by Hari Kanigeri h-kanige...@ti.com
+ *
+ * Added support for OMAP4. This is based on original file
+ * omap3-iommu.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/platform_device.h
+
+#include mach/iommu.h
+#include mach/irqs.h
+
+#define OMAP4_MMU1_BASE 0x55082000
+#define OMAP4_MMU2_BASE 0x4A066000
+
+#define OMAP4_MMU1_IRQ INT_44XX_DUCATI_MMU_IRQ
+#define OMAP4_MMU2_IRQ INT_44XX_DSP_MMU
+
+
+
+static unsigned long iommu_base[] __initdata = {
+ OMAP4_MMU1_BASE,
+ OMAP4_MMU2_BASE,
+};
+
+static int iommu_irq[] __initdata = {
+ OMAP4_MMU1_IRQ,
+ OMAP4_MMU2_IRQ,
+};
+
+static const struct iommu_platform_data omap4_iommu_pdata[] __initconst = {
+ {
+ .name = ducati,
+ .nr_tlb_entries = 32,
+ .clk_name = ducati_ick,
+ },
+#if defined(CONFIG_MPU_TESLA_IOMMU)
+ {
+ .name = tesla,
+ .nr_tlb_entries = 32,
+ .clk_name = tesla_ick,
+ },
+#endif
+};
If iommu is used as a character device driver, is the above config still
necessary?
+#define NR_IOMMU_DEVICES ARRAY_SIZE(omap4_iommu_pdata)
+
+static struct platform_device *omap4_iommu_pdev[NR_IOMMU_DEVICES];
+
+static int __init omap4_iommu_init(void)
+{
+ int i, err;
+
+ for (i = 0; i NR_IOMMU_DEVICES; i++) {
+ struct platform_device *pdev;
+ struct resource res[2];
+
+ pdev = platform_device_alloc(omap-iommu, i);
+ if (!pdev) {
+ err = -ENOMEM;
+ goto err_out;
+ }
+
+ memset(res, 0, sizeof(res));
+ res[0].start = iommu_base[i];
+ res[0].end = iommu_base[i] + MMU_REG_SIZE - 1;
+ res[0].flags = IORESOURCE_MEM;
+ res[1].start = res[1].end = iommu_irq[i];
+ res[1].flags = IORESOURCE_IRQ;
+
+ err = platform_device_add_resources(pdev, res,
+ ARRAY_SIZE(res));
+ if (err)
+ goto err_out;
+ err = platform_device_add_data(pdev, omap4_iommu_pdata[i],
+sizeof(omap4_iommu_pdata[0]));
+ if (err)
+ goto err_out;
+ err = platform_device_add(pdev);
+ if (err)
+ goto err_out;
+ omap4_iommu_pdev[i] = pdev;
+ }
+ return 0;
+
+err_out:
+ while (i--)
+ platform_device_put(omap4_iommu_pdev[i]);
+ return err;
+}
+module_init(omap4_iommu_init);
+
+static void __exit omap4_iommu_exit(void)
+{
+ int i;
+
+ for (i = 0; i NR_IOMMU_DEVICES; i++)
+ platform_device_unregister(omap4_iommu_pdev[i]);
+}
+module_exit(omap4_iommu_exit);
+
+MODULE_AUTHOR(Hiroshi DOYU, Hari Kanigeri);
+MODULE_DESCRIPTION(omap iommu: omap4 device registration);
+MODULE_LICENSE(GPL v2);
+
diff --git a/arch/arm/plat-omap/include/mach/irqs.h
b/arch/arm/plat-omap/include/mach/irqs.h
index fb7cb77..34b6d09 100644
--- a/arch/arm/plat-omap/include/mach/irqs.h
+++ b/arch/arm/plat-omap/include/mach/irqs.h
@@ -511,7 +511,7 @@
#define INT_44XX_TLL_IRQ (78 + IRQ_GIC_START)
#define INT_44XX_PARTHASH_IRQ(79 + IRQ_GIC_START)
#define INT_44XX_MMC3_IRQ(94 + IRQ_GIC_START)
-
+#define INT_44XX_DUCATI_MMU_IRQ (100 + IRQ_GIC_START)
/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
* 16 MPUIO lines */
--
1.5.4.3
Thank you,
Best regards,
Hari
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Re: [RFC][PATCH 2/3] ARM:OMAP4 iommu:add omap4 support in iommu
On Fri, Jul 24, 2009 at 07:22:32PM +0200, ext Kanigeri, Hari wrote:
This patch adds omap4 support in iommu
module. This creates OMAP4 platform specific file
for iommu and defines the Ducati MMU fault interrupt.
Signed-off-by: Hari Kanigeri h-kanige...@ti.com
---
arch/arm/mach-omap2/omap4-iommu.c | 112
arch/arm/plat-omap/include/mach/irqs.h |2 +-
2 files changed, 113 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-omap2/omap4-iommu.c
diff --git a/arch/arm/mach-omap2/omap4-iommu.c
b/arch/arm/mach-omap2/omap4-iommu.c
new file mode 100644
index 000..5a782df
--- /dev/null
+++ b/arch/arm/mach-omap2/omap4-iommu.c
@@ -0,0 +1,112 @@
+/*
+ * omap iommu: omap4 device registration
+ *
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Written by Hari Kanigeri h-kanige...@ti.com
+ *
+ * Added support for OMAP4. This is based on original file
+ * omap3-iommu.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/platform_device.h
+
+#include mach/iommu.h
+#include mach/irqs.h
+
+#define OMAP4_MMU1_BASE 0x55082000
+#define OMAP4_MMU2_BASE 0x4A066000
+
+#define OMAP4_MMU1_IRQ INT_44XX_DUCATI_MMU_IRQ
+#define OMAP4_MMU2_IRQ INT_44XX_DSP_MMU
+
+
+
+static unsigned long iommu_base[] __initdata = {
+ OMAP4_MMU1_BASE,
+ OMAP4_MMU2_BASE,
+};
+
+static int iommu_irq[] __initdata = {
+ OMAP4_MMU1_IRQ,
+ OMAP4_MMU2_IRQ,
+};
these two looks really odd :-s
+
+static const struct iommu_platform_data omap4_iommu_pdata[] __initconst = {
+ {
+ .name = ducati,
+ .nr_tlb_entries = 32,
+ .clk_name = ducati_ick,
passing clk names should be avoided. use clkdev.
+ },
+#if defined(CONFIG_MPU_TESLA_IOMMU)
this ifdef looks odd.
--
balbi
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Re: [RFC][PATCH 1/3] ARM:OMAP4 iommu:changes in iommu for OMAP4
From: ext Kanigeri, Hari h-kanige...@ti.com
Subject: [RFC][PATCH 1/3] ARM:OMAP4 iommu:changes in iommu for OMAP4
Date: Fri, 24 Jul 2009 19:22:09 +0200
This patch has the changes to iommu module to make
iommu functional on OMAP4 simulator. The changes
included using stubbed clock interface and commenting
out reading the MMU soft reset register.
Signed-off-by: Hari Kanigeri h-kanige...@ti.com
---
arch/arm/mach-omap2/iommu2.c |8 ++--
arch/arm/plat-omap/iommu.c | 12 +---
2 files changed, 15 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
index 015f22a..01cb15d 100644
--- a/arch/arm/mach-omap2/iommu2.c
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -80,12 +80,16 @@ static int omap2_iommu_enable(struct iommu *obj)
if (l MMU_SYS_RESETDONE)
break;
} while (time_after(jiffies, timeout));
-
+/* FIXME: Hack till the reading the MMU status register
+ * is resolved in Simulator. Simulator doesn't update
+ * the STATUS register.
+ */
+#ifndef CONFIG_ARCH_OMAP4
if (!(l MMU_SYS_RESETDONE)) {
What about the following?
if (!cpu_is_omap44xx() !(l MMU_SYS_RESETDONE)) {
dev_err(obj-dev, can't take mmu out of reset\n);
return -ENODEV;
}
-
+#endif
l = iommu_read_reg(obj, MMU_REVISION);
dev_info(obj-dev, %s: version %d.%d\n, obj-name,
(l 4) 0xf, l 0xf);
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index 4cf449f..b62a087 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -861,9 +861,15 @@ static int __devinit omap_iommu_probe(struct
platform_device *pdev)
if (!obj)
return -ENOMEM;
- obj-clk = clk_get(pdev-dev, pdata-clk_name);
- if (IS_ERR(obj-clk))
- goto err_clk;
+ /*
+ * FIX-ME: Replace with correct clk node when clk
+ * framework is available
+ */
+ if (!cpu_is_omap44xx()) {
+ obj-clk = clk_get(pdev-dev, pdata-clk_name);
+ if (IS_ERR(obj-clk))
+ goto err_clk;
+ }
obj-nr_tlb_entries = pdata-nr_tlb_entries;
obj-name = pdata-name;
--
1.5.4.3
Thank you,
Best regards,
Hari
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Re: [RFC][PATCH 2/3] ARM:OMAP4 iommu:add omap4 support in iommu
Hi Felipe,
From: Balbi Felipe (Nokia-D/Helsinki) felipe.ba...@nokia.com
Subject: Re: [RFC][PATCH 2/3] ARM:OMAP4 iommu:add omap4 support in iommu
Date: Fri, 24 Jul 2009 20:27:02 +0200
On Fri, Jul 24, 2009 at 07:22:32PM +0200, ext Kanigeri, Hari wrote:
This patch adds omap4 support in iommu
module. This creates OMAP4 platform specific file
for iommu and defines the Ducati MMU fault interrupt.
Signed-off-by: Hari Kanigeri h-kanige...@ti.com
---
arch/arm/mach-omap2/omap4-iommu.c | 112
arch/arm/plat-omap/include/mach/irqs.h |2 +-
2 files changed, 113 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-omap2/omap4-iommu.c
diff --git a/arch/arm/mach-omap2/omap4-iommu.c
b/arch/arm/mach-omap2/omap4-iommu.c
new file mode 100644
index 000..5a782df
--- /dev/null
+++ b/arch/arm/mach-omap2/omap4-iommu.c
@@ -0,0 +1,112 @@
+/*
+ * omap iommu: omap4 device registration
+ *
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Written by Hari Kanigeri h-kanige...@ti.com
+ *
+ * Added support for OMAP4. This is based on original file
+ * omap3-iommu.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/platform_device.h
+
+#include mach/iommu.h
+#include mach/irqs.h
+
+#define OMAP4_MMU1_BASE0x55082000
+#define OMAP4_MMU2_BASE0x4A066000
+
+#define OMAP4_MMU1_IRQ INT_44XX_DUCATI_MMU_IRQ
+#define OMAP4_MMU2_IRQ INT_44XX_DSP_MMU
+
+
+
+static unsigned long iommu_base[] __initdata = {
+ OMAP4_MMU1_BASE,
+ OMAP4_MMU2_BASE,
+};
+
+static int iommu_irq[] __initdata = {
+ OMAP4_MMU1_IRQ,
+ OMAP4_MMU2_IRQ,
+};
these two looks really odd :-s
I think that the above just follows Russeell's proposal as below:
http://lists.arm.linux.org.uk/lurker/message/20090516.092036.df9420d1.en.html
+
+static const struct iommu_platform_data omap4_iommu_pdata[] __initconst = {
+ {
+ .name = ducati,
+ .nr_tlb_entries = 32,
+ .clk_name = ducati_ick,
passing clk names should be avoided. use clkdev.
+ },
+#if defined(CONFIG_MPU_TESLA_IOMMU)
this ifdef looks odd.
--
balbi
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Re: [RFC][PATCH 2/3] ARM:OMAP4 iommu:add omap4 support in iommu
hi,
On Fri, Jul 24, 2009 at 08:47:57PM +0200, Doyu Hiroshi (Nokia-D/Helsinki) wrote:
+static unsigned long iommu_base[] __initdata = {
+ OMAP4_MMU1_BASE,
+ OMAP4_MMU2_BASE,
+};
+
+static int iommu_irq[] __initdata = {
+ OMAP4_MMU1_IRQ,
+ OMAP4_MMU2_IRQ,
+};
these two looks really odd :-s
I think that the above just follows Russeell's proposal as below:
http://lists.arm.linux.org.uk/lurker/message/20090516.092036.df9420d1.en.html
I see... still looks odd though.
--
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Re: [PATCH 1/1] DSPBRIDGE: expose DSP_TRACEBUF as kernel config option
From: Hiroshi DOYU hiroshi.d...@nokia.com Subject: Re: [PATCH 1/1] DSPBRIDGE: expose DSP_TRACEBUF as kernel config option Date: Fri, 24 Jul 2009 21:00:05 +0300 (EEST) Hi Hari, From: ext Kanigeri, Hari h-kanige...@ti.com Subject: RE: [PATCH 1/1] DSPBRIDGE: expose DSP_TRACEBUF as kernel config option Date: Fri, 24 Jul 2009 19:28:47 +0200 Hi Doyu-san, CONFIG_DSP_TRACEBUF is introduced as a kernel config option to save some amount of unused memory and #ifndef DSP_TRACEBUF_DISABLED was not easy to understand. I think we just use the Bridge DEBUG flag that is used in Bridge instead of introducing a new flag. It might be better if CONFIG_DSP_TRACEBUF had the dependecy on DEBUG/CONFIG_BRIDGE_DEBUG, but it's not unfortunately. The problem here is that now all TRACEBUF code is always compiled in in spite of setting DEBUG. It doesn't print anything, but just wastes some memory. I'll remove a new Kconfig entry and just add the dependency of CONFIG_DSP_TRACEBUF on CONFIG_BRIDGE_DEBUG. How about the following change? Modified drivers/dsp/bridge/Kconfig diff --git a/drivers/dsp/bridge/Kconfig b/drivers/dsp/bridge/Kconfig index a43b19d..d73b097 100644 --- a/drivers/dsp/bridge/Kconfig +++ b/drivers/dsp/bridge/Kconfig @@ -32,12 +32,9 @@ config BRIDGE_MEMPOOL_SIZE config BRIDGE_DEBUG bool DSP Bridge Debug Support depends on MPU_BRIDGE + select DSP_TRACEBUF help Say Y to enable Bridge debugging capabilities config DSP_TRACEBUF - bool DSP Debug Trace Support - depends on BRIDGE_DEBUG - help - Say Y to enable DSP debugging capabilities. baseimage needs - to be built with debug option. +bool -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 20/32] omap_hsmmc: put MMC regulator to sleep
On Fri, 10 Jul 2009 15:42:27 +0300
Adrian Hunter adrian.hun...@nokia.com wrote:
+static int omap_mmc_regsleep_to_enabled(struct mmc_omap_host *host)
+{
+ unsigned long timeout;
+
+ dev_dbg(mmc_dev(host-mmc), REGSLEEP - ENABLED\n);
+
+ clk_enable(host-fclk);
+ clk_enable(host-iclk);
+
+ if (clk_enable(host-dbclk))
+ dev_dbg(mmc_dev(host-mmc),
+ Enabling debounce clk failed\n);
+
+ omap_mmc_restore_ctx(host);
+
+ /*
+ * We turned off interrupts and bus power. Interrupts
+ * are turned on by 'mmc_omap_start_command()' so we
+ * just need to turn on the bus power here.
+ */
+ OMAP_HSMMC_WRITE(host-base, HCTL,
+ OMAP_HSMMC_READ(host-base, HCTL) | SDBP);
+
+ timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
+ while ((OMAP_HSMMC_READ(host-base, HCTL) SDBP) != SDBP
+time_before(jiffies, timeout))
+ ;
+
+ if (mmc_slot(host).set_sleep)
+ mmc_slot(host).set_sleep(host-dev, host-slot_id,
+ 0, host-vdd, 0);
+
+ host-dpm_state = ENABLED;
+
+ return 0;
+}
We take no action if the wait for SDBP timed out?
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Re: [PATCH 26/32] omap_hsmmc: prevent races with irq handler
On Fri, 10 Jul 2009 15:43:09 +0300 Adrian Hunter adrian.hun...@nokia.com wrote: From 242fae6293adec671b14354f215217354f5076a0 Mon Sep 17 00:00:00 2001 From: Adrian Hunter adrian.hun...@nokia.com Date: Sat, 16 May 2009 10:32:34 +0300 Subject: [PATCH] omap_hsmmc: prevent races with irq handler If an unexpected interrupt occurs while preparing the next request, an oops can occur. For example, a new request is setting up DMA for data transfer so host-data is not NULL. An unexpected transfer complete (TC) interrupt comes along and the interrupt handler sets host-data to NULL. Oops! Prevent that by disabling interrupts while setting up a new request. Signed-off-by: Adrian Hunter adrian.hun...@nokia.com --- drivers/mmc/host/omap_hsmmc.c | 16 1 files changed, 16 insertions(+), 0 deletions(-) diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index 28563d6..38e1410 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -452,6 +452,13 @@ mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd, if (host-use_dma) cmdreg |= DMA_EN; + /* + * In an interrupt context (i.e. STOP command), the interrupt is already + * enabled, otherwise it is not (i.e. new request). + */ + if (!in_interrupt()) + enable_irq(host-irq); + OMAP_HSMMC_WRITE(host-base, ARG, cmd-arg); OMAP_HSMMC_WRITE(host-base, CMD, cmdreg); } @@ -1011,6 +1018,13 @@ static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req) struct mmc_omap_host *host = mmc_priv(mmc); int err; + /* + * Prevent races with the interrupt handler because of unexpected + * interrupts, but not if we are already in interrupt context i.e. + * retries. + */ + if (!in_interrupt()) + disable_irq(host-irq); WARN_ON(host-mrq != NULL); host-mrq = req; err = mmc_omap_prepare_data(host, req); @@ -1019,6 +1033,8 @@ static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req) if (req-data) req-data-error = err; host-mrq = NULL; + if (!in_interrupt()) + enable_irq(host-irq); mmc_request_done(mmc, req); return; } That seems pretty crude. Disabling an interrupt line can be expensive, and will shut off any other innocent devices which share the line. The usual and superior way of fixing races such as this is spin_lock_irq[save](). -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH 1/1] DSPBRIDGE: expose DSP_TRACEBUF as kernel config option
Hiroshi, The problem here is that now all TRACEBUF code is always compiled in in spite of setting DEBUG. It doesn't print anything, but just wastes some memory That's not true. DSP_TRACEBUF is used to print the traces from DSP. This is used by Socket node developers to print their traces from DSP to console. If you enable DT=1 GT trace, then you get all the prints from DSP, which is extremely useful for DSP Developers. Thank you, Best regards, Hari -Original Message- From: Hiroshi DOYU [mailto:hiroshi.d...@nokia.com] Sent: Friday, July 24, 2009 1:00 PM To: Kanigeri, Hari Cc: linux-omap@vger.kernel.org; ameya.pala...@nokia.com; Guzman Lugo, Fernando; Ramirez Luna, Omar Subject: Re: [PATCH 1/1] DSPBRIDGE: expose DSP_TRACEBUF as kernel config option Hi Hari, From: ext Kanigeri, Hari h-kanige...@ti.com Subject: RE: [PATCH 1/1] DSPBRIDGE: expose DSP_TRACEBUF as kernel config option Date: Fri, 24 Jul 2009 19:28:47 +0200 Hi Doyu-san, CONFIG_DSP_TRACEBUF is introduced as a kernel config option to save some amount of unused memory and #ifndef DSP_TRACEBUF_DISABLED was not easy to understand. I think we just use the Bridge DEBUG flag that is used in Bridge instead of introducing a new flag. It might be better if CONFIG_DSP_TRACEBUF had the dependecy on DEBUG/CONFIG_BRIDGE_DEBUG, but it's not unfortunately. The problem here is that now all TRACEBUF code is always compiled in in spite of setting DEBUG. It doesn't print anything, but just wastes some memory. I'll remove a new Kconfig entry and just add the dependency of CONFIG_DSP_TRACEBUF on CONFIG_BRIDGE_DEBUG. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: n800 can't mount rootfs
Hello Kalle, On Sat, 6 Jun 2009, Kalle Valo wrote: I tested linux-omap (commit 151c7a7fc) on n800 and it can't mount rootfs anymore. Below is the full bootlog. Unfortunately I don't have time to debug this right now, but I can test patches if needed. [0.00] Linux version 2.6.30-rc8-omap1 (kv...@tikku) (gcc version 4.3.2 (Sourcery G++ Lite 2008q3-66) ) #2 Sat Jun 6 10:28:29 EEST 2009 [0.00] CPU: ARMv6-compatible processor [4107b362] revision 2 (ARMv6TEJ), cr=00c5387f [0.00] CPU: VIPT aliasing data cache, VIPT aliasing instruction cache [0.00] Machine: Nokia N800 [0.00] Memory policy: ECC disabled, Data cache writeback [0.00] OMAP24206 [0.00] SRAM: Mapped pa 0x4020 to va 0xe300 size: 0x10 [0.00] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512 [0.00] Kernel command line: root=1f03 rootfstype=jffs2 [0.00] NR_IRQS:368 [0.00] Clocking rate (Crystal/DPLL/MPU): 19.2/658/329 MHz [0.00] GPMC revision 2.0 [0.00] IRQ: Found an INTC at 0xd80fe000 (revision 2.0) with 96 interrupts [0.00] Total of 96 interrupts on 1 active controller [0.00] OMAP242x GPIO hardware version 1.8 [0.00] PID hash table entries: 512 (order: 9, 2048 bytes) [0.00] OMAP clockevent source: GPTIMER1 at 32000 Hz [0.00] Console: colour dummy device 80x30 [0.00] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) [0.00] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) [0.00] Memory: 64MB 64MB = 128MB total [0.00] Memory: 126392KB available (2896K code, 238K data, 120K init, 0K highmem) [0.00] Calibrating delay loop... 320.37 BogoMIPS (lpj=1253376) [0.00] Security Framework initialized [0.00] Mount-cache hash table entries: 512 [0.00] CPU: Testing write buffer coherency: ok [0.00] net_namespace: 668 bytes [0.00] NET: Registered protocol family 16 [0.00] TUSB 6010 [0.00] kobject (c031e048): tried to init an initialized object, something is seriously wrong. [0.00] [c002c674] (unwind_backtrace+0x0/0xdc) from [c0103654] (kobject_init+0x38/0x70) [0.00] [c0103654] (kobject_init+0x38/0x70) from [c013fbfc] (device_initialize+0x20/0x70) [0.00] [c013fbfc] (device_initialize+0x20/0x70) from [c0143408] (platform_device_register+0x10/0x1c) [0.00] [c0143408] (platform_device_register+0x10/0x1c) from [c000e7a0] (gpmc_onenand_init+0x4c/0x74) [0.00] [c000e7a0] (gpmc_onenand_init+0x4c/0x74) from [c000b13c] (customize_machine+0x18/0x24) [0.00] [c000b13c] (customize_machine+0x18/0x24) from [c00262bc] (do_one_initcall+0x54/0x194) [0.00] [c00262bc] (do_one_initcall+0x54/0x194) from [c00083b8] (kernel_init+0x70/0xe4) [0.00] [c00083b8] (kernel_init+0x70/0xe4) from [c004d498] (do_exit+0x0/0x580) [0.00] [c004d498] (do_exit+0x0/0x580) from [0001] (0x1) [0.00] [ cut here ] I get the same thing on N800 (compiling at 7c5cb7862d32cb344be7831d466535d5255e35ac). - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] OMAP2: N800: don't try to initialize OneNAND twice
board-n800.c calls board_onenand_init() twice. The second time fails during boot with: kobject (c031e048): tried to init an initialized object, something is seriously wrong. with backtrace, etc. board_onenand_init() should not be called twice. Patch tested on N800. Problem originally found by Kalle Valo kalle.v...@iki.fi Signed-off-by: Paul Walmsley p...@pwsan.com Cc: Kalle Valo kalle.v...@iki.fi --- arch/arm/mach-omap2/board-n800.c |1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/board-n800.c b/arch/arm/mach-omap2/board-n800.c index fee6c62..bea182d 100644 --- a/arch/arm/mach-omap2/board-n800.c +++ b/arch/arm/mach-omap2/board-n800.c @@ -566,7 +566,6 @@ static void __init nokia_n800_init(void) n800_ts_set_config(); tea5761_dev_init(); - board_onenand_init(); } void __init nokia_n800_map_io(void) -- 1.6.3.3.334.g916e1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: n800 can't mount rootfs
On Fri, 24 Jul 2009, Paul Walmsley wrote: On Sat, 6 Jun 2009, Kalle Valo wrote: [0.00] kobject (c031e048): tried to init an initialized object, something is seriously wrong. [0.00] [c002c674] (unwind_backtrace+0x0/0xdc) from [c0103654] (kobject_init+0x38/0x70) [0.00] [c0103654] (kobject_init+0x38/0x70) from [c013fbfc] (device_initialize+0x20/0x70) [0.00] [c013fbfc] (device_initialize+0x20/0x70) from [c0143408] (platform_device_register+0x10/0x1c) [0.00] [c0143408] (platform_device_register+0x10/0x1c) from [c000e7a0] (gpmc_onenand_init+0x4c/0x74) [0.00] [c000e7a0] (gpmc_onenand_init+0x4c/0x74) from [c000b13c] (customize_machine+0x18/0x24) [0.00] [c000b13c] (customize_machine+0x18/0x24) from [c00262bc] (do_one_initcall+0x54/0x194) [0.00] [c00262bc] (do_one_initcall+0x54/0x194) from [c00083b8] (kernel_init+0x70/0xe4) [0.00] [c00083b8] (kernel_init+0x70/0xe4) from [c004d498] (do_exit+0x0/0x580) [0.00] [c004d498] (do_exit+0x0/0x580) from [0001] (0x1) [0.00] [ cut here ] I get the same thing on N800 (compiling at 7c5cb7862d32cb344be7831d466535d5255e35ac). For the archives: this is fixed by diff --git a/arch/arm/mach-omap2/board-n800.c b/arch/arm/mach-omap2/board-n800.c index fee6c62..bea182d 100644 --- a/arch/arm/mach-omap2/board-n800.c +++ b/arch/arm/mach-omap2/board-n800.c @@ -566,7 +566,6 @@ static void __init nokia_n800_init(void) n800_ts_set_config(); tea5761_dev_init(); - board_onenand_init(); } void __init nokia_n800_map_io(void) - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/8] Fixes for OMAP2/3 SDRC/clock for 2.6.31-rc*
This series contains fixes for 2.6.31-rc* for the OMAP2/3 SDRC SDRAM controller and the OMAP2/3 clock code. Boot-tested on BeagleBoard rev C2 and N800. Additional CORE DVFS testing run on BeagleBoard rev C2. - Paul --- size: textdata bss dec hex filename 3451158 197824 104656 3753638 3946a6 vmlinux.beagle.orig 3452322 198592 104656 3755570 394e32 vmlinux.beagle Jean Pihet (2): OMAP3 SDRC: add support for 2 SDRAM chip selects OMAP3: Setup MUX settings for SDRC CKE signals Paul Walmsley (4): OMAP2/3 SDRC: don't set SDRC_POWER.PWDENA on boot OMAP2/3 clock: split, rename omap2_wait_clock_ready() OMAP2 clock: 2430 I2CHS uses non-standard CM_IDLEST register OMAP3 clock: correct module IDLEST bits: SSI; DSS; USBHOST; HSOTGUSB Rajendra Nayak (2): OMAP3 SDRC: Fix freeze when scaling CORE dpll to 83Mhz OMAP3 SDRC: Move the clk stabilization delay to the right place arch/arm/mach-omap2/board-2430sdp.c |2 arch/arm/mach-omap2/board-3430sdp.c |2 arch/arm/mach-omap2/board-4430sdp.c |2 arch/arm/mach-omap2/board-apollon.c |2 arch/arm/mach-omap2/board-generic.c |2 arch/arm/mach-omap2/board-h4.c |2 arch/arm/mach-omap2/board-ldp.c |2 arch/arm/mach-omap2/board-omap3beagle.c |7 + arch/arm/mach-omap2/board-omap3evm.c |2 arch/arm/mach-omap2/board-omap3pandora.c |8 +- arch/arm/mach-omap2/board-overo.c|8 +- arch/arm/mach-omap2/board-rx51.c |6 + arch/arm/mach-omap2/board-zoom2.c|2 arch/arm/mach-omap2/clock.c | 156 +++--- arch/arm/mach-omap2/clock.h |6 + arch/arm/mach-omap2/clock24xx.c | 37 +++ arch/arm/mach-omap2/clock24xx.h |4 - arch/arm/mach-omap2/clock34xx.c | 155 +++--- arch/arm/mach-omap2/clock34xx.h | 85 ++-- arch/arm/mach-omap2/io.c |5 + arch/arm/mach-omap2/mux.c|6 + arch/arm/mach-omap2/prcm.c | 43 arch/arm/mach-omap2/sdrc.c | 68 + arch/arm/mach-omap2/sram34xx.S | 143 +--- arch/arm/plat-omap/include/mach/clock.h |2 arch/arm/plat-omap/include/mach/io.h |3 - arch/arm/plat-omap/include/mach/mux.h|4 + arch/arm/plat-omap/include/mach/prcm.h |1 arch/arm/plat-omap/include/mach/sdrc.h | 11 ++ arch/arm/plat-omap/include/mach/sram.h | 23 ++-- arch/arm/plat-omap/sram.c| 30 +++--- 31 files changed, 623 insertions(+), 206 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/8] OMAP3: Setup MUX settings for SDRC CKE signals
From: Jean Pihet jpi...@mvista.com
This patches ensures the MUX settings are correct for the SDRC
CKE signals to SDRAM. This allows the self-refresh to work when
2 chip-selects are in use.
A warning is thrown away in case the initial muxing is incorrect,
in order to track faulty or old-dated bootloaders.
Note: The CONFIG_OMAP_MUX and CONFIG_OMAP_MUX_WARNINGS options
must be enabled for the mux code to have effect.
Signed-off-by: Jean Pihet jpi...@mvista.com
Signed-off-by: Paul Walmsley p...@pwsan.com
---
arch/arm/mach-omap2/board-omap3beagle.c |4
arch/arm/mach-omap2/board-omap3pandora.c |5 +
arch/arm/mach-omap2/board-overo.c|5 +
arch/arm/mach-omap2/board-rx51.c |4
arch/arm/mach-omap2/mux.c|6 ++
arch/arm/plat-omap/include/mach/mux.h|4
6 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c
b/arch/arm/mach-omap2/board-omap3beagle.c
index 4abefd9..e00ba12 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -409,6 +409,10 @@ static void __init omap3_beagle_init(void)
usb_musb_init();
omap3beagle_flash_init();
+
+ /* Ensure SDRC pins are mux'd for self-refresh */
+ omap_cfg_reg(H16_34XX_SDRC_CKE0);
+ omap_cfg_reg(H17_34XX_SDRC_CKE1);
}
static void __init omap3_beagle_map_io(void)
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c
b/arch/arm/mach-omap2/board-omap3pandora.c
index 9b991ce..864ee3d 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -40,6 +40,7 @@
#include mach/mcspi.h
#include mach/usb.h
#include mach/keypad.h
+#include mach/mux.h
#include sdram-micron-mt46h32m32lf-6.h
#include mmc-twl4030.h
@@ -398,6 +399,10 @@ static void __init omap3pandora_init(void)
omap3pandora_ads7846_init();
pandora_keys_gpio_init();
usb_musb_init();
+
+ /* Ensure SDRC pins are mux'd for self-refresh */
+ omap_cfg_reg(H16_34XX_SDRC_CKE0);
+ omap_cfg_reg(H17_34XX_SDRC_CKE1);
}
static void __init omap3pandora_map_io(void)
diff --git a/arch/arm/mach-omap2/board-overo.c
b/arch/arm/mach-omap2/board-overo.c
index 44bc1c5..6b171b3 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -44,6 +44,7 @@
#include mach/gpmc.h
#include mach/hardware.h
#include mach/nand.h
+#include mach/mux.h
#include mach/usb.h
#include sdram-micron-mt46h32m32lf-6.h
@@ -396,6 +397,10 @@ static void __init overo_init(void)
overo_ads7846_init();
overo_init_smsc911x();
+ /* Ensure SDRC pins are mux'd for self-refresh */
+ omap_cfg_reg(H16_34XX_SDRC_CKE0);
+ omap_cfg_reg(H17_34XX_SDRC_CKE1);
+
if ((gpio_request(OVERO_GPIO_W2W_NRESET,
OVERO_GPIO_W2W_NRESET) == 0)
(gpio_direction_output(OVERO_GPIO_W2W_NRESET, 1) == 0)) {
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 591ae8a..1c9e07f 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -75,6 +75,10 @@ static void __init rx51_init(void)
omap_serial_init();
usb_musb_init();
rx51_peripherals_init();
+
+ /* Ensure SDRC pins are mux'd for self-refresh */
+ omap_cfg_reg(H16_34XX_SDRC_CKE0);
+ omap_cfg_reg(H17_34XX_SDRC_CKE1);
}
static void __init rx51_map_io(void)
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 026c4fc..43d6b92 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -486,6 +486,12 @@ MUX_CFG_34XX(H19_34XX_GPIO164_OUT, 0x19c,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
MUX_CFG_34XX(J25_34XX_GPIO170, 0x1c6,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
+
+/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
+MUX_CFG_34XX(H16_34XX_SDRC_CKE0, 0x262,
+ OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
+MUX_CFG_34XX(H17_34XX_SDRC_CKE1, 0x264,
+ OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
};
#define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins)
diff --git a/arch/arm/plat-omap/include/mach/mux.h
b/arch/arm/plat-omap/include/mach/mux.h
index 85a6217..80281c4 100644
--- a/arch/arm/plat-omap/include/mach/mux.h
+++ b/arch/arm/plat-omap/include/mach/mux.h
@@ -853,6 +853,10 @@ enum omap34xx_index {
AE5_34XX_GPIO143,
H19_34XX_GPIO164_OUT,
J25_34XX_GPIO170,
+
+ /* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
+ H16_34XX_SDRC_CKE0,
+ H17_34XX_SDRC_CKE1,
};
struct omap_mux_cfg {
--
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[PATCH 3/8] OMAP2/3 SDRC: don't set SDRC_POWER.PWDENA on boot
Stop setting SDRC_POWER.PWDENA on boot. There is a nasty erratum (34xx erratum 1.150) that can cause memory corruption if PWDENA is enabled. Based originally on a patch from Samu P. Onkalo samu.p.onk...@nokia.com. Tested on BeagleBoard rev C2. Signed-off-by: Paul Walmsley p...@pwsan.com Cc: Samu P. Onkalo samu.p.onk...@nokia.com --- arch/arm/mach-omap2/sdrc.c |5 - arch/arm/mach-omap2/sram34xx.S |2 -- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c index 2e9e38d..9e3bd4f 100644 --- a/arch/arm/mach-omap2/sdrc.c +++ b/arch/arm/mach-omap2/sdrc.c @@ -125,8 +125,11 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, sdrc_init_params_cs1 = sdrc_cs1; /* XXX Enable SRFRONIDLEREQ here also? */ + /* +* PWDENA should not be set due to 34xx erratum 1.150 - PWDENA +* can cause random memory corruption +*/ l = (1 SDRC_POWER_EXTCLKDIS_SHIFT) | - (1 SDRC_POWER_PWDENA_SHIFT) | (1 SDRC_POWER_PAGEPOLICY_SHIFT); sdrc_write_reg(l, SDRC_POWER); } diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index 3aef744..9c2d046 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -58,7 +58,6 @@ /* SDRC_POWER bit settings */ #define SRFRONIDLEREQ_MASK 0x40 -#define PWDENA_MASK0x4 /* CM_IDLEST1_CORE bit settings */ #define ST_SDRC_MASK 0x2 @@ -160,7 +159,6 @@ sdram_in_selfrefresh: ldr r12, [r11] @ read the contents of SDRC_POWER mov r9, r12 @ keep a copy of SDRC_POWER bits orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle - bic r12, r12, #PWDENA_MASK @ clear PWDENA str r12, [r11] @ write back to SDRC_POWER register ldr r12, [r11] @ posted-write barrier for SDRC idle_sdrc: -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 5/8] OMAP3 SDRC: Move the clk stabilization delay to the right place
From: Rajendra Nayak rna...@ti.com The clock stabilization delay post a M2 divider change is needed even before a SDRC interface clock re-enable and not only before jumping back to SDRAM. Signed-off-by: Rajendra Nayak rna...@ti.com Signed-off-by: Paul Walmsley p...@pwsan.com --- arch/arm/mach-omap2/sram34xx.S |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index e6b1125..82aa4a3 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -127,6 +127,8 @@ skip_cs1_params: blnelock_dll bl sdram_in_selfrefresh@ put SDRAM in self refresh, idle SDRC bl configure_core_dpll @ change the DPLL3 M2 divider + mov r12, r2 + bl wait_clk_stable @ wait for SDRC to stabilize bl enable_sdrc @ take SDRC out of idle cmp r1, #SDRC_UNLOCK_DLL@ wait for DLL status to change bleqwait_dll_unlock @@ -134,8 +136,6 @@ skip_cs1_params: cmp r3, #1 @ if increasing SDRC clk rate, beq return_to_sdram @ return to SDRAM code, otherwise, bl configure_sdrc @ reprogram SDRC regs now - mov r12, r2 - bl wait_clk_stable @ wait for SDRC to stabilize return_to_sdram: isb @ prevent speculative exec past here mov r0, #0 @ return value -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/8] OMAP3 SDRC: add support for 2 SDRAM chip selects
From: Jean Pihet jpi...@mvista.com
Some OMAP3 boards (Beagle Cx, Overo, RX51, Pandora) have 2
SDRAM parts connected to the SDRC.
This patch adds the following:
- add a new argument of type omap_sdrc_params struct*
to omap2_init_common_hw and omap2_sdrc_init for the 2nd CS params
- adapted the OMAP boards files to the new prototype of
omap2_init_common_hw
- add the SDRC 2nd CS registers offsets defines
- adapt the sram sleep code to configure the SDRC for the 2nd CS
Note: If the 2nd param to omap2_init_common_hw is NULL, then the
parameters are not programmed into the SDRC CS1 registers
Tested on 3430 SDP and Beagleboard rev C2 and B5, with
suspend/resume and frequency changes (cpufreq).
Signed-off-by: Jean Pihet jpi...@mvista.com
Signed-off-by: Paul Walmsley p...@pwsan.com
---
arch/arm/mach-omap2/board-2430sdp.c |2
arch/arm/mach-omap2/board-3430sdp.c |2
arch/arm/mach-omap2/board-4430sdp.c |2
arch/arm/mach-omap2/board-apollon.c |2
arch/arm/mach-omap2/board-generic.c |2
arch/arm/mach-omap2/board-h4.c |2
arch/arm/mach-omap2/board-ldp.c |2
arch/arm/mach-omap2/board-omap3beagle.c |3 -
arch/arm/mach-omap2/board-omap3evm.c |2
arch/arm/mach-omap2/board-omap3pandora.c |3 -
arch/arm/mach-omap2/board-overo.c|3 -
arch/arm/mach-omap2/board-rx51.c |2
arch/arm/mach-omap2/board-zoom2.c|2
arch/arm/mach-omap2/clock34xx.c | 37 ++--
arch/arm/mach-omap2/io.c |5 +
arch/arm/mach-omap2/sdrc.c | 63 +-
arch/arm/mach-omap2/sram34xx.S | 137 +++---
arch/arm/plat-omap/include/mach/io.h |3 -
arch/arm/plat-omap/include/mach/sdrc.h | 11 ++
arch/arm/plat-omap/include/mach/sram.h | 23 +++--
arch/arm/plat-omap/sram.c| 30 ---
21 files changed, 236 insertions(+), 102 deletions(-)
diff --git a/arch/arm/mach-omap2/board-2430sdp.c
b/arch/arm/mach-omap2/board-2430sdp.c
index 9c3fdcd..8ec2a13 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -141,7 +141,7 @@ static inline void board_smc91x_init(void)
static void __init omap_2430sdp_init_irq(void)
{
- omap2_init_common_hw(NULL);
+ omap2_init_common_hw(NULL, NULL);
omap_init_irq();
omap_gpio_init();
}
diff --git a/arch/arm/mach-omap2/board-3430sdp.c
b/arch/arm/mach-omap2/board-3430sdp.c
index 496a90e..ac262cd 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -169,7 +169,7 @@ static struct platform_device *sdp3430_devices[] __initdata
= {
static void __init omap_3430sdp_init_irq(void)
{
- omap2_init_common_hw(hyb18m512160af6_sdrc_params);
+ omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL);
omap_init_irq();
omap_gpio_init();
}
diff --git a/arch/arm/mach-omap2/board-4430sdp.c
b/arch/arm/mach-omap2/board-4430sdp.c
index 57e477b..b0c7402 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -59,7 +59,7 @@ static void __init gic_init_irq(void)
static void __init omap_4430sdp_init_irq(void)
{
- omap2_init_common_hw(NULL);
+ omap2_init_common_hw(NULL, NULL);
#ifdef CONFIG_OMAP_32K_TIMER
omap2_gp_clockevent_set_gptimer(1);
#endif
diff --git a/arch/arm/mach-omap2/board-apollon.c
b/arch/arm/mach-omap2/board-apollon.c
index 06dfba8..dcfc20d 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -250,7 +250,7 @@ out:
static void __init omap_apollon_init_irq(void)
{
- omap2_init_common_hw(NULL);
+ omap2_init_common_hw(NULL, NULL);
omap_init_irq();
omap_gpio_init();
apollon_init_smc91x();
diff --git a/arch/arm/mach-omap2/board-generic.c
b/arch/arm/mach-omap2/board-generic.c
index 3492162..fd00aa0 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -33,7 +33,7 @@
static void __init omap_generic_init_irq(void)
{
- omap2_init_common_hw(NULL);
+ omap2_init_common_hw(NULL, NULL);
omap_init_irq();
}
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index e7d017c..7b1d61d 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -270,7 +270,7 @@ static void __init h4_init_flash(void)
static void __init omap_h4_init_irq(void)
{
- omap2_init_common_hw(NULL);
+ omap2_init_common_hw(NULL, NULL);
omap_init_irq();
omap_gpio_init();
h4_init_flash();
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index d8bc0a7..ea383f8 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -270,7 +270,7 @@ static inline void __init ldp_init_smsc911x(void)
static void __init omap_ldp_init_irq(void)
{
-
[PATCH 7/8] OMAP2 clock: 2430 I2CHS uses non-standard CM_IDLEST register
OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the CM_*CLKEN bits
are in CM_{I,F}CLKEN2_CORE [1]. Fix by implementing a custom clkops
.find_idlest function to return the correct slave IDLEST register.
...
1. OMAP2430 Multimedia Device Package-on-Package (POP) Silicon Revision 2.1
(Rev. V) Technical Reference Manual, tables 4-99 and 4-105.
Signed-off-by: Paul Walmsley p...@pwsan.com
---
arch/arm/mach-omap2/clock24xx.c | 37 +++--
arch/arm/mach-omap2/clock24xx.h |4 ++--
2 files changed, 37 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index 44de027..bc5d3ac 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -30,6 +30,7 @@
#include mach/clock.h
#include mach/sram.h
+#include mach/prcm.h
#include asm/div64.h
#include asm/clkdev.h
@@ -43,6 +44,18 @@
static const struct clkops clkops_oscck;
static const struct clkops clkops_fixed;
+static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
+ void __iomem **idlest_reg,
+ u8 *idlest_bit);
+
+/* 2430 I2CHS has non-standard IDLEST register */
+static const struct clkops clkops_omap2430_i2chs_wait = {
+ .enable = omap2_dflt_clk_enable,
+ .disable= omap2_dflt_clk_disable,
+ .find_idlest= omap2430_clk_i2chs_find_idlest,
+ .find_companion = omap2_clk_dflt_find_companion,
+};
+
#include clock24xx.h
struct omap_clk {
@@ -240,6 +253,26 @@ static void __iomem *prcm_clksrc_ctrl;
*-*/
/**
+ * omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS
+ * @clk: struct clk * being enabled
+ * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
+ * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
+ *
+ * OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the
+ * CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE. This custom function
+ * passes back the correct CM_IDLEST register address for I2CHS
+ * modules. No return value.
+ */
+static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
+ void __iomem **idlest_reg,
+ u8 *idlest_bit)
+{
+ *idlest_reg = OMAP_CM_REGADDR(CORE_MOD, CM_IDLEST);
+ *idlest_bit = clk-enable_bit;
+}
+
+
+/**
* omap2xxx_clk_get_core_rate - return the CORE_CLK rate
* @clk: pointer to the combined dpll_ck + core_ck (currently dpll_ck)
*
@@ -325,8 +358,8 @@ static int omap2_clk_fixed_enable(struct clk *clk)
else if (clk == apll54_ck)
cval = OMAP24XX_ST_54M_APLL;
- omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
- clk-name);
+ omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
+clk-name);
/*
* REVISIT: Should we return an error code if omap2_wait_clock_ready()
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 458f00c..d19cf7a 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -2337,7 +2337,7 @@ static struct clk i2c2_fck = {
static struct clk i2chs2_fck = {
.name = i2c_fck,
- .ops= clkops_omap2_dflt_wait,
+ .ops= clkops_omap2430_i2chs_wait,
.id = 2,
.parent = func_96m_ck,
.clkdm_name = core_l4_clkdm,
@@ -2370,7 +2370,7 @@ static struct clk i2c1_fck = {
static struct clk i2chs1_fck = {
.name = i2c_fck,
- .ops= clkops_omap2_dflt_wait,
+ .ops= clkops_omap2430_i2chs_wait,
.id = 1,
.parent = func_96m_ck,
.clkdm_name = core_l4_clkdm,
--
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[PATCH 4/8] OMAP3 SDRC: Fix freeze when scaling CORE dpll to 83Mhz
From: Rajendra Nayak rna...@ti.com This patch fixes a bug in the CORE dpll scaling sequence which was errouneously clearing some bits in the SDRC DLLA CTRL register and hence causing a freeze. The issue was observed only on platforms which scale CORE dpll to 83Mhz and hence program the DLL in fixed delay mode. Issue reported by Limei Wang e12...@motorola.com, with debugging assistance from Richard Woodruff r-woodru...@ti.com and Girish Ghongdemath giris...@ti.com. Signed-off-by: Rajendra Nayak rna...@ti.com Cc: Limei Wang e12...@motorola.com Cc: Richard Woodruff r-woodru...@ti.com Cc: Girish Ghongdemath giris...@ti.com Signed-off-by: Paul Walmsley p...@pwsan.com [p...@pwsan.com: updated patch description to include collaboration credits] --- arch/arm/mach-omap2/sram34xx.S |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index 9c2d046..e6b1125 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -143,7 +143,7 @@ return_to_sdram: unlock_dll: ldr r11, omap3_sdrc_dlla_ctrl ldr r12, [r11] - and r12, r12, #FIXEDDELAY_MASK + bic r12, r12, #FIXEDDELAY_MASK orr r12, r12, #FIXEDDELAY_DEFAULT orr r12, r12, #DLLIDLE_MASK str r12, [r11] @ (no OCP barrier needed) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 8/8] OMAP3 clock: correct module IDLEST bits: SSI; DSS; USBHOST; HSOTGUSB
Fix two bugs in the OMAP3 clock tree pertaining to the SSI, DSS,
USBHOST, and HSOTGUSB devices. These devices are both interconnect
initiators and targets. Without this patch, clk_enable()s on clocks for
these modules can be very high latency (potentially up to ~200
milliseconds) and message such as the following are generated:
Clock usbhost_48m_fck didn't enable in 10 tries
Two bugs are fixed by this patch. First, OMAP hardware only supports
target CM_IDLEST register bits on ES2+ chips and beyond. ES1 chips
should not wait for these clocks to enable. So, split the appropriate
clocks into ES1 and ES2+ variants, so that kernels running on ES1
devices won't try to wait.
Second, the current heuristic in omap2_clk_dflt_find_idlest() will
fail for these clocks. It assumes that the CM_IDLEST bit to wait upon
is the same as the CM_*CLKEN bit, which is false[1]. Fix by
implementing custom clkops .find_idlest function pointers for the
appropriate clocks that return the correct slave IDLEST bit shift.
This was originally fixed in the linux-omap kernel during 2.6.29 in a
slightly different manner[2][3].
In the medium-term future, all of the module IDLEST code will
eventually be moved to the omap_hwmod code.
Problem reported by Jarkko Nikula jhnik...@gmail.com:
http://marc.info/?l=linux-omapm=124306184903679w=2
...
1. See for example 34xx TRM Revision P Table 4-213 and 4-217 (for the
DSS case).
2. http://www.spinics.net/lists/linux-omap/msg05512.html et seq.
3. http://lkml.indiana.edu/hypermail/linux/kernel/0901.3/01498.html
Signed-off-by: Paul Walmsley p...@pwsan.com
Cc: Jarkko Nikula jhnik...@gmail.com
---
arch/arm/mach-omap2/clock34xx.c | 118 +--
arch/arm/mach-omap2/clock34xx.h | 85
2 files changed, 185 insertions(+), 18 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 1c6480d..cd7819c 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -2,7 +2,7 @@
* OMAP3-specific clock framework functions
*
* Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2008 Nokia Corporation
+ * Copyright (C) 2007-2009 Nokia Corporation
*
* Written by Paul Walmsley
* Testing and integration fixes by Jouni Högander
@@ -41,6 +41,37 @@
static const struct clkops clkops_noncore_dpll_ops;
+static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
+ void __iomem **idlest_reg,
+ u8 *idlest_bit);
+static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
+ void __iomem **idlest_reg,
+ u8 *idlest_bit);
+static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
+ void __iomem **idlest_reg,
+ u8 *idlest_bit);
+
+static const struct clkops clkops_omap3430es2_ssi_wait = {
+ .enable = omap2_dflt_clk_enable,
+ .disable= omap2_dflt_clk_disable,
+ .find_idlest= omap3430es2_clk_ssi_find_idlest,
+ .find_companion = omap2_clk_dflt_find_companion,
+};
+
+static const struct clkops clkops_omap3430es2_hsotgusb_wait = {
+ .enable = omap2_dflt_clk_enable,
+ .disable= omap2_dflt_clk_disable,
+ .find_idlest= omap3430es2_clk_hsotgusb_find_idlest,
+ .find_companion = omap2_clk_dflt_find_companion,
+};
+
+static const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
+ .enable = omap2_dflt_clk_enable,
+ .disable= omap2_dflt_clk_disable,
+ .find_idlest= omap3430es2_clk_dss_usbhost_find_idlest,
+ .find_companion = omap2_clk_dflt_find_companion,
+};
+
#include clock34xx.h
struct omap_clk {
@@ -157,10 +188,13 @@ static struct omap_clk omap34xx_clks[] = {
CLK(NULL, fshostusb_fck, fshostusb_fck, CK_3430ES1),
CLK(NULL, core_12m_fck, core_12m_fck, CK_343X),
CLK(omap_hdq.0, fck,hdq_fck, CK_343X),
- CLK(NULL, ssi_ssr_fck, ssi_ssr_fck, CK_343X),
- CLK(NULL, ssi_sst_fck, ssi_sst_fck, CK_343X),
+ CLK(NULL, ssi_ssr_fck, ssi_ssr_fck_3430es1, CK_3430ES1),
+ CLK(NULL, ssi_ssr_fck, ssi_ssr_fck_3430es2, CK_3430ES2),
+ CLK(NULL, ssi_sst_fck, ssi_sst_fck_3430es1, CK_3430ES1),
+ CLK(NULL, ssi_sst_fck, ssi_sst_fck_3430es2, CK_3430ES2),
CLK(NULL, core_l3_ick, core_l3_ick, CK_343X),
- CLK(musb_hdrc,ick, hsotgusb_ick, CK_343X),
+ CLK(musb_hdrc,ick, hsotgusb_ick_3430es1, CK_3430ES1),
+ CLK(musb_hdrc,ick, hsotgusb_ick_3430es2, CK_3430ES2),
CLK(NULL, sdrc_ick, sdrc_ick, CK_343X),
CLK(NULL, gpmc_fck, gpmc_fck,
[PATCH] OMAP2: N800: Fix compilation after recent omap2_init_common_hw() changes
This patch is intended to be applied after the 2.6.31-rc OMAP2/3
SDRC/clock fixes series is merged to mainline. Since N800 support is not
yet in mainline, this chunk had to be split out from Jean's original patch
into a linux-omap specific patch.
Update board-n800.c after recent omap2_init_common_hw() changes.
This code was written by Jean Pihet jpi...@mvista.com.
Signed-off-by: Jean Pihet jpi...@mvista.com
Signed-off-by: Paul Walmsley p...@pwsan.com
---
arch/arm/mach-omap2/board-n800.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/board-n800.c b/arch/arm/mach-omap2/board-n800.c
index 23296e9..fee6c62 100644
--- a/arch/arm/mach-omap2/board-n800.c
+++ b/arch/arm/mach-omap2/board-n800.c
@@ -64,7 +64,7 @@ struct omap_tmp105_config {
void __init nokia_n800_init_irq(void)
{
- omap2_init_common_hw(NULL);
+ omap2_init_common_hw(NULL, NULL);
omap_init_irq();
omap_gpio_init();
--
1.6.3.3.334.g916e1
--
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Re: [PATCH 1/1] DSPBRIDGE: expose DSP_TRACEBUF as kernel config option
From: ext Kanigeri, Hari h-kanige...@ti.com
Subject: RE: [PATCH 1/1] DSPBRIDGE: expose DSP_TRACEBUF as kernel config option
Date: Sat, 25 Jul 2009 02:43:41 +0200
Hiroshi,
The problem here is that now all TRACEBUF code is always compiled in
in spite of setting DEBUG. It doesn't print anything, but just
wastes some memory
That's not true. DSP_TRACEBUF is used to print the traces from DSP. This is
used by Socket node developers to print their traces from DSP to console.
If you enable DT=1 GT trace, then you get all the prints from DSP, which is
extremely useful for DSP Developers.
I understand that DSP_TRACEBUF is useful. But now DSP_TRACEBUF is
always complied in and it cannot print anything without defining
GT_TRACE, IOW, without defining CONFIG_DSP_DEBUG. This is the matter of
dependency of those DEFINEs, DSP_TRACEBUF and DEBUG. Kconfig can describe
those dependency. I am proposing to set the dependency of DSP_TRACEBUF
on CONFIG_DSP_DEBUG, to save some memory instead of keeping unused
code(ex: PrintDSPDebugTrace()) in this driver.
Without defining GT_TRACE, DSP_TRACEBUF won't print anything
because PrintDSPDebugTrace() uses GT_0trace to print and GT_?trace()
is set as below,
arch/arm/plat-omap/include/dspbridge/gt.h:
...
#ifndef GT_TRACE
#define GT_TRACE 0 /* 0 = trace compiled out; 1 = trace
active */
#endif
...
#if GT_TRACE == 0
...
#define GT_0trace(mask, class, format) do {} while (0)
#define GT_1trace(mask, class, format, arg1) do {} while (0)
...
And GT_TRACE depends on CONFIG_BRIDGE_DEBUG as below,
drivers/dsp/bridge/Kbuild:
...
ifeq ($(CONFIG_BRIDGE_DEBUG),y)
ccflags-y += -DGT_TRACE -DDEBUG
endif
...
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