Re: [PATCH 04/17] phy: omap-usb2: use omap_usb_power_off to power off the PHY during probe
On Tue, 23 Jun 2015 17:28:49 +0530 Kishon Vijay Abraham I kis...@ti.com wrote: No functional change. Previously omap_control_phy_power() was used to power off the PHY during probe. But once phy-omap-usb2 driver is adapted to use syscon, omap_control_phy_power() cannot be used. Hence used omap_usb_power_off to power off the PHY. Signed-off-by: Kishon Vijay Abraham I kis...@ti.com Acked-by: Roger Quadros rog...@ti.com cheers, -roger --- drivers/phy/phy-omap-usb2.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c index c1a4686..b5c266a 100644 --- a/drivers/phy/phy-omap-usb2.c +++ b/drivers/phy/phy-omap-usb2.c @@ -241,7 +241,6 @@ static int omap_usb2_probe(struct platform_device *pdev) } phy-control_dev = control_pdev-dev; - omap_control_phy_power(phy-control_dev, 0); otg-set_host = omap_usb_set_host; otg-set_peripheral = omap_usb_set_peripheral; @@ -261,6 +260,7 @@ static int omap_usb2_probe(struct platform_device *pdev) } phy_set_drvdata(generic_phy, phy); + omap_usb_power_off(generic_phy); phy_provider = devm_of_phy_provider_register(phy-dev, of_phy_simple_xlate); -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 05/17] phy: omap-usb2: Add a new compatible string for USB2 PHY2
On Tue, 23 Jun 2015 17:28:50 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
The USB2 PHY2 has a different register map compared to USB2 PHY1
to power on/off the PHY. In order to handle it, add a new
compatible string.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt |2 ++
drivers/phy/phy-omap-usb2.c |9 +
2 files changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 52c7a92..b9101b9 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -31,6 +31,8 @@ OMAP USB2 PHY
Required properties:
- compatible: Should be ti,omap-usb2
+Should be ti,dra7x-usb2-phy2 for the 2nd instance of USB2 PHY
+ in DRA7x
- reg : Address and length of the register set for the device.
- #phy-cells: determine the number of cells that should be given in the
phandle while referencing this phy.
diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
index b5c266a..2f7220f 100644
--- a/drivers/phy/phy-omap-usb2.c
+++ b/drivers/phy/phy-omap-usb2.c
@@ -159,6 +159,11 @@ static const struct usb_phy_data dra7x_usb2_data = {
.flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
};
+static const struct usb_phy_data dra7x_usb2_phy2_data = {
+ .label = dra7x_usb2_phy2,
+ .flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
Isn't it better to define the register map in usb_phy_data
so that you don't need to check for compatible flag everytime?
+};
+
static const struct usb_phy_data am437x_usb2_data = {
.label = am437x_usb2,
.flags = 0,
@@ -178,6 +183,10 @@ static const struct of_device_id omap_usb2_id_table[] = {
.data = dra7x_usb2_data,
},
{
+ .compatible = ti,dra7x-usb2-phy2,
+ .data = dra7x_usb2_phy2_data,
+ },
+ {
.compatible = ti,am437x-usb2,
.data = am437x_usb2_data,
},
--
1.7.9.5
cheers,
-roger
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Re: [PATCH 06/17] phy: omap-usb2: use *syscon* framework to power on/off the PHY
Hi,
On Wednesday 24 June 2015 05:03 PM, Roger Quadros wrote:
On Tue, 23 Jun 2015 17:28:51 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
Deprecate using phy-omap-control driver to power on/off the PHY,
and use *syscon* framework to do the same. This handles
powering on/off the PHY for the USB2 PHYs used in various TI SoCs.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt |6 +-
drivers/phy/phy-omap-usb2.c | 101
++
include/linux/phy/omap_usb.h | 18
3 files changed, 107 insertions(+), 18 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index b9101b9..5bfe461 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -42,10 +42,14 @@ Required properties:
* wkupclk - wakeup clock.
* refclk - reference clock (optional).
-Optional properties:
+Deprecated properties:
- ctrl-module : phandle of the control module used by PHY driver to power
on
the PHY.
+Recommended properies:
+- syscon-phy-power : phandle/offset pair. Phandle to the system control
+ module and the register offset to power on/off the PHY.
+
This is usually a subnode of ocp2scp to which it is connected.
usb2phy@4a0ad080 {
diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
index 2f7220f..180b066 100644
--- a/drivers/phy/phy-omap-usb2.c
+++ b/drivers/phy/phy-omap-usb2.c
@@ -29,6 +29,8 @@
#include linux/delay.h
#include linux/phy/omap_control_phy.h
#include linux/phy/phy.h
+#include linux/mfd/syscon.h
+#include linux/regmap.h
#include linux/of_platform.h
#define USB2PHY_DISCON_BYP_LATCH (1 31)
@@ -97,22 +99,65 @@ static int omap_usb_set_peripheral(struct usb_otg *otg,
return 0;
}
-static int omap_usb_power_off(struct phy *x)
+static int omap_usb_phy_power(struct omap_usb *phy, int on)
{
-struct omap_usb *phy = phy_get_drvdata(x);
+u32 val = 0;
+u32 mask;
+int ret;
-omap_control_phy_power(phy-control_dev, 0);
+if (phy-syscon_phy_power) {
+switch (phy-type) {
+case TYPE_USB2:
+mask = OMAP_DEV_PHY_PD;
+if (!on)
+val = OMAP_DEV_PHY_PD;
+break;
+case TYPE_DRA7USB2:
+mask = OMAP_USB2_PHY_PD;
+if (!on)
+val = OMAP_USB2_PHY_PD;
+break;
+case TYPE_AM437USB2:
+mask = AM437X_USB2_PHY_PD |
+AM437X_USB2_OTG_PD |
+AM437X_USB2_OTGVDET_EN |
+AM437X_USB2_OTGSESSEND_EN;
+if (on) {
+val = AM437X_USB2_OTGVDET_EN |
+AM437X_USB2_OTGSESSEND_EN;
+} else {
+val = AM437X_USB2_PHY_PD | AM437X_USB2_OTG_PD;
+}
+break;
+default:
+dev_err(phy-dev, %s: type %d not recognized\n,
+__func__, phy-type);
+return -EINVAL;
+}
+
+ret = regmap_update_bits(phy-syscon_phy_power, phy-power_reg,
+ mask, val);
+if (ret 0)
+return ret;
+} else {
+omap_control_phy_power(phy-control_dev, on);
+}
return 0;
}
-static int omap_usb_power_on(struct phy *x)
+static int omap_usb_power_off(struct phy *x)
{
struct omap_usb *phy = phy_get_drvdata(x);
-omap_control_phy_power(phy-control_dev, 1);
+return omap_usb_phy_power(phy, false);
+}
-return 0;
+static int omap_usb_power_on(struct phy *x)
+{
+struct omap_usb *phy = phy_get_drvdata(x);
+
+return omap_usb_phy_power(phy, true);
}
static int omap_usb_init(struct phy *x)
@@ -147,26 +192,31 @@ static struct phy_ops ops = {
static const struct usb_phy_data omap_usb2_data = {
.label = omap_usb2,
.flags = OMAP_USB2_HAS_START_SRP | OMAP_USB2_HAS_SET_VBUS,
+.type = TYPE_USB2,
};
static const struct usb_phy_data omap5_usb2_data = {
.label = omap5_usb2,
.flags = 0,
+.type = TYPE_USB2,
};
static const struct usb_phy_data dra7x_usb2_data = {
.label = dra7x_usb2,
.flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
+.type = TYPE_USB2,
};
static const struct usb_phy_data dra7x_usb2_phy2_data = {
.label = dra7x_usb2_phy2,
.flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
+.type = TYPE_DRA7USB2,
};
static const struct usb_phy_data am437x_usb2_data = {
.label = am437x_usb2,
Re: [PATCH 03/17] phy: ti-pipe3: use *syscon* framework to set PCS value of the PHY
On Tue, 23 Jun 2015 17:28:48 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
Deprecate using phy-omap-control driver to set PCS value of the PHY
and start using *syscon* framework to do the same.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt |2 ++
drivers/phy/phy-ti-pipe3.c | 32
+-
2 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index d3ad3bf..52c7a92 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -83,6 +83,8 @@ Optional properties:
- syscon-pllreset: Handle to system control region that contains the
CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0
register that contains the SATA_PLL_SOFT_RESET bit. Only valid for
sata_phy.
+ - syscon-pcs : phandle/offset pair. Phandle to the system control module
and the
+ register offset to write the PCS delay value.
What is PCS?
Is this valid only for PCIe? If yes we could mention it here.
Deprecated properties:
- ctrl-module : phandle of the control module used by PHY driver to power on
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index 78bac00..e2f9ad7 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -65,6 +65,9 @@
#define PIPE3_PHY_TX_RX_POWERON 0x3
#define PIPE3_PHY_TX_RX_POWEROFF 0x0
+#define PCIE_PCS_MASK0xFF
+#define PCIE_PCS_DELAY_COUNT_SHIFT 0x10
+
/*
* This is an Empirical value that works, need to confirm the actual
* value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
@@ -96,9 +99,11 @@ struct ti_pipe3 {
struct clk *div_clk;
struct pipe3_dpll_map *dpll_map;
struct regmap *phy_power_syscon; /* ctrl. reg. acces */
+ struct regmap *pcs_syscon; /* ctrl. reg. acces */
struct regmap *dpll_reset_syscon; /* ctrl. reg. acces */
unsigned intdpll_reset_reg; /* reg. index within syscon */
unsigned intpower_reg; /* power reg. index within syscon */
+ unsigned intpcie_pcs_reg; /* pcs reg. index in syscon */
boolsata_refclk_enabled;
};
@@ -271,7 +276,16 @@ static int ti_pipe3_init(struct phy *x)
* 18-1804.
*/
if (of_device_is_compatible(phy-dev-of_node, ti,phy-pipe3-pcie)) {
- omap_control_pcie_pcs(phy-control_dev, 0x96);
+ if (phy-pcs_syscon) {
+ val = 0x96 OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT;
+ ret = regmap_update_bits(phy-pcs_syscon,
+ phy-pcie_pcs_reg,
+ PCIE_PCS_MASK, val);
+ if (ret 0)
+ return ret;
+ } else {
+ omap_control_pcie_pcs(phy-control_dev, 0x96);
+ }
return 0;
}
@@ -455,6 +469,22 @@ static int ti_pipe3_probe(struct platform_device *pdev)
dev_err(pdev-dev, unable to get div-clk\n);
return PTR_ERR(phy-div_clk);
}
+
+ phy-pcs_syscon = syscon_regmap_lookup_by_phandle(node,
+ syscon-pcs);
+ if (IS_ERR(phy-pcs_syscon)) {
+ dev_dbg(pdev-dev,
+ can't get syscon-pcs, using omap control\n);
+ phy-pcs_syscon = NULL;
+ } else {
+ if (of_property_read_u32_index(node,
+syscon-pcs, 1,
+phy-pcie_pcs_reg)) {
+ dev_err(pdev-dev,
+ couldn't get pcie pcs reg. offset\n);
+ return -EINVAL;
+ }
+ }
} else {
phy-div_clk = ERR_PTR(-ENODEV);
}
--
1.7.9.5
Other than that,
Acked-by: Roger Quadros rog...@ti.com
cheers,
-roger
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Re: [PATCH 07/17] usb: musb: omap2430: use *syscon* framework to write to mailbox register
* Kishon Vijay Abraham I kis...@ti.com [150623 05:02]: Deprecate using phy-omap-control driver to write to the mailbox register and start using *syscon* framework to do the same. All this stuff needs to go to some generic syscon USB phy driver. Let's not start adding phy specific stuff to a USB driver. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 08/17] ARM: dts: dra7: Add dt node for the sycon pcie
On Wed, 24 Jun 2015 14:50:17 +0300
Roger Quadros rog...@ti.com wrote:
On Tue, 23 Jun 2015 17:28:53 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
Add new device tree node for the control module register space where
PCIe registers are present.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 260f300..3f434f7 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -291,6 +291,11 @@
reg = 0x4a002e00 0x7c;
};
+ dra7_ctrl_pcie: tisyscon@4a003c00 {
+ compatible = syscon;
+ reg = 0x4a003c00 0x48;
+ };
+
Why do you need to start from 0x4a003c00?
CTRL_CORE_PCIESS1_PCS1 is at 0x4a003c24
Also, why can't this dra7_ctrl_pcie node be where scm_conf is.
sdma: dma-controller@4a056000 {
compatible = ti,omap4430-sdma;
reg = 0x4a056000 0x1000;
--
1.7.9.5
cheers,
-roger
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Re: [PATCH 17/17] ARM: dts: omap4: Use syscon-otghs instead of ctrl-module in USB node
On Wed, 24 Jun 2015 03:41:16 -0700
Tony Lindgren t...@atomide.com wrote:
* Kishon Vijay Abraham I kis...@ti.com [150623 05:02]:
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -852,12 +852,6 @@
};
};
- omap_control_usbotg: control-phy@4a00233c {
- compatible = ti,control-phy-otghs;
- reg = 0x4a00233c 0x4;
- reg-names = otghs_control;
- };
-
usb_otg_hs: usb_otg_hs@4a0ab000 {
compatible = ti,omap4-musb;
reg = 0x4a0ab000 0x7ff;
@@ -870,7 +864,7 @@
multipoint = 1;
num-eps = 16;
ram-bits = 12;
- ctrl-module = omap_control_usbotg;
+ syscon-otghs = scm_conf 0x33c;
};
aes: aes@4b501000 {
We should still keep a separate entry for the phy in the dtsi
files. And the phy should be a child of the scm_conf area in the
dtsi file.
The PHY already has a separate entry with its own set of registers.
Just that some bits have been shoved into the control module space
not only for PHY but for other modules as well like DSS, DCAN, etc.
This is because the scm and usb_otg_hs are separate devices and
can be clocked separately. So the phy driver needs to be a
separate driver to avoid spaghetti code and issues with clocking.
for the PHY register space this is already done.
But for the register bits that lie in control module space isn't that
taken care by syscon driver?
cheers,
-roger
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Re: [PATCH 08/17] ARM: dts: dra7: Add dt node for the sycon pcie
* Roger Quadros rog...@ti.com [150624 04:58]:
On Wed, 24 Jun 2015 14:50:17 +0300
Roger Quadros rog...@ti.com wrote:
On Tue, 23 Jun 2015 17:28:53 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
Add new device tree node for the control module register space where
PCIe registers are present.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 260f300..3f434f7 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -291,6 +291,11 @@
reg = 0x4a002e00 0x7c;
};
+ dra7_ctrl_pcie: tisyscon@4a003c00 {
+ compatible = syscon;
+ reg = 0x4a003c00 0x48;
+ };
+
Why do you need to start from 0x4a003c00?
CTRL_CORE_PCIESS1_PCS1 is at 0x4a003c24
Also, why can't this dra7_ctrl_pcie node be where scm_conf is.
Yes all the scm children should be under scm@2000 entry in the
dra7.dtsi file.
And BTW, there's nothing stopping a driver doing of_ioremap
on a larger range and be a child under scm@2000 in the dra7.dtsi
if that range is dedicated to a single driver.
My take is we should only use regmap for the scm_conf area
in general.
Regards,
Tony
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Re: [PATCH 06/17] phy: omap-usb2: use *syscon* framework to power on/off the PHY
On Tue, 23 Jun 2015 17:28:51 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
Deprecate using phy-omap-control driver to power on/off the PHY,
and use *syscon* framework to do the same. This handles
powering on/off the PHY for the USB2 PHYs used in various TI SoCs.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt |6 +-
drivers/phy/phy-omap-usb2.c | 101
++
include/linux/phy/omap_usb.h | 18
3 files changed, 107 insertions(+), 18 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index b9101b9..5bfe461 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -42,10 +42,14 @@ Required properties:
* wkupclk - wakeup clock.
* refclk - reference clock (optional).
-Optional properties:
+Deprecated properties:
- ctrl-module : phandle of the control module used by PHY driver to power on
the PHY.
+Recommended properies:
+- syscon-phy-power : phandle/offset pair. Phandle to the system control
+ module and the register offset to power on/off the PHY.
+
This is usually a subnode of ocp2scp to which it is connected.
usb2phy@4a0ad080 {
diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
index 2f7220f..180b066 100644
--- a/drivers/phy/phy-omap-usb2.c
+++ b/drivers/phy/phy-omap-usb2.c
@@ -29,6 +29,8 @@
#include linux/delay.h
#include linux/phy/omap_control_phy.h
#include linux/phy/phy.h
+#include linux/mfd/syscon.h
+#include linux/regmap.h
#include linux/of_platform.h
#define USB2PHY_DISCON_BYP_LATCH (1 31)
@@ -97,22 +99,65 @@ static int omap_usb_set_peripheral(struct usb_otg *otg,
return 0;
}
-static int omap_usb_power_off(struct phy *x)
+static int omap_usb_phy_power(struct omap_usb *phy, int on)
{
- struct omap_usb *phy = phy_get_drvdata(x);
+ u32 val = 0;
+ u32 mask;
+ int ret;
- omap_control_phy_power(phy-control_dev, 0);
+ if (phy-syscon_phy_power) {
+ switch (phy-type) {
+ case TYPE_USB2:
+ mask = OMAP_DEV_PHY_PD;
+ if (!on)
+ val = OMAP_DEV_PHY_PD;
+ break;
+ case TYPE_DRA7USB2:
+ mask = OMAP_USB2_PHY_PD;
+ if (!on)
+ val = OMAP_USB2_PHY_PD;
+ break;
+ case TYPE_AM437USB2:
+ mask = AM437X_USB2_PHY_PD |
+ AM437X_USB2_OTG_PD |
+ AM437X_USB2_OTGVDET_EN |
+ AM437X_USB2_OTGSESSEND_EN;
+ if (on) {
+ val = AM437X_USB2_OTGVDET_EN |
+ AM437X_USB2_OTGSESSEND_EN;
+ } else {
+ val = AM437X_USB2_PHY_PD | AM437X_USB2_OTG_PD;
+ }
+ break;
+ default:
+ dev_err(phy-dev, %s: type %d not recognized\n,
+ __func__, phy-type);
+ return -EINVAL;
+ }
+
+ ret = regmap_update_bits(phy-syscon_phy_power, phy-power_reg,
+ mask, val);
+ if (ret 0)
+ return ret;
+ } else {
+ omap_control_phy_power(phy-control_dev, on);
+ }
return 0;
}
-static int omap_usb_power_on(struct phy *x)
+static int omap_usb_power_off(struct phy *x)
{
struct omap_usb *phy = phy_get_drvdata(x);
- omap_control_phy_power(phy-control_dev, 1);
+ return omap_usb_phy_power(phy, false);
+}
- return 0;
+static int omap_usb_power_on(struct phy *x)
+{
+ struct omap_usb *phy = phy_get_drvdata(x);
+
+ return omap_usb_phy_power(phy, true);
}
static int omap_usb_init(struct phy *x)
@@ -147,26 +192,31 @@ static struct phy_ops ops = {
static const struct usb_phy_data omap_usb2_data = {
.label = omap_usb2,
.flags = OMAP_USB2_HAS_START_SRP | OMAP_USB2_HAS_SET_VBUS,
+ .type = TYPE_USB2,
};
static const struct usb_phy_data omap5_usb2_data = {
.label = omap5_usb2,
.flags = 0,
+ .type = TYPE_USB2,
};
static const struct usb_phy_data dra7x_usb2_data = {
.label = dra7x_usb2,
.flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
+ .type = TYPE_USB2,
};
static const struct usb_phy_data dra7x_usb2_phy2_data = {
.label = dra7x_usb2_phy2,
.flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
+ .type = TYPE_DRA7USB2,
};
static const struct usb_phy_data am437x_usb2_data = {
.label = am437x_usb2,
Re: [PATCH v2] usb: dwc3: pci: make better use of gpiod API
On Tue, Jun 23, 2015 at 02:25:06PM +0200, Uwe Kleine-König wrote: Since 39b2bbe3d715 (gpio: add flags argument to gpiod_get*() functions) which appeared in v3.17-rc1, the gpiod_get* functions take an additional parameter that allows to specify direction and initial value for output. Use this additional parameter and the _optional variant to simplify the driver and improve error handling. Also expand the comment to explain why it's not sensible to switch to devm_gpiod_get and why the gpiod_put is also necessary. Furthermore this is one caller less that stops us making the flags argument to gpiod_get*() mandatory. Signed-off-by: Uwe Kleine-König u.kleine-koe...@pengutronix.de Tested-by: Heikki Krogerus heikki.kroge...@linux.intel.com Thanks, -- heikki -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 17/17] ARM: dts: omap4: Use syscon-otghs instead of ctrl-module in USB node
* Kishon Vijay Abraham I kis...@ti.com [150623 05:02]:
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -852,12 +852,6 @@
};
};
- omap_control_usbotg: control-phy@4a00233c {
- compatible = ti,control-phy-otghs;
- reg = 0x4a00233c 0x4;
- reg-names = otghs_control;
- };
-
usb_otg_hs: usb_otg_hs@4a0ab000 {
compatible = ti,omap4-musb;
reg = 0x4a0ab000 0x7ff;
@@ -870,7 +864,7 @@
multipoint = 1;
num-eps = 16;
ram-bits = 12;
- ctrl-module = omap_control_usbotg;
+ syscon-otghs = scm_conf 0x33c;
};
aes: aes@4b501000 {
We should still keep a separate entry for the phy in the dtsi
files. And the phy should be a child of the scm_conf area in the
dtsi file.
This is because the scm and usb_otg_hs are separate devices and
can be clocked separately. So the phy driver needs to be a
separate driver to avoid spaghetti code and issues with clocking.
Regards,
Tony
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Re: [PATCH 02/17] phy: ti-pipe3: use *syscon* framework to power on/off the PHY
Hi,
On Tuesday 23 June 2015 08:23 PM, Roger Quadros wrote:
Hi Kishon,
On Tue, 23 Jun 2015 17:28:47 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
Deprecate using phy-omap-control driver to power on/off the PHY and
use *syscon* framework to do the same.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 10 ++-
drivers/phy/phy-ti-pipe3.c | 91 ++
2 files changed, 86 insertions(+), 15 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index f0f5537..d3ad3bf 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -77,8 +77,6 @@ Required properties:
* div-clk - apll clock
Optional properties:
- - ctrl-module : phandle of the control module used by PHY driver to power on
- the PHY.
- id: If there are multiple instance of the same type, in order to
differentiate between each instance id can be used (e.g., multi-lane PCIe
PHY). If id is not provided, it is set to default value of '1'.
@@ -86,6 +84,14 @@ Optional properties:
CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0
register that contains the SATA_PLL_SOFT_RESET bit. Only valid for
sata_phy.
+Deprecated properties:
+ - ctrl-module : phandle of the control module used by PHY driver to power on
+ the PHY.
+
+Recommended properies:
+ - syscon-phy-power : phandle/offset pair. Phandle to the system control
+ module and the register offset to power on/off the PHY.
+
This is usually a subnode of ocp2scp to which it is connected.
usb3phy@4a084400 {
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index d784426..78bac00 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -56,6 +56,15 @@
#define SATA_PLL_SOFT_RESET BIT(18)
+#define PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
+#define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 14
+
+#define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC0
+#define PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT22
+
+#define PIPE3_PHY_TX_RX_POWERON0x3
+#define PIPE3_PHY_TX_RX_POWEROFF 0x0
+
/*
* This is an Empirical value that works, need to confirm the actual
* value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
@@ -86,8 +95,10 @@ struct ti_pipe3 {
struct clk *refclk;
struct clk *div_clk;
struct pipe3_dpll_map *dpll_map;
+ struct regmap *phy_power_syscon; /* ctrl. reg. acces */
struct regmap *dpll_reset_syscon; /* ctrl. reg. acces */
unsigned intdpll_reset_reg; /* reg. index within syscon */
+ unsigned intpower_reg; /* power reg. index within syscon */
boolsata_refclk_enabled;
};
@@ -144,18 +155,49 @@ static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy);
static int ti_pipe3_power_off(struct phy *x)
{
+ u32 val;
+ int ret;
struct ti_pipe3 *phy = phy_get_drvdata(x);
- omap_control_phy_power(phy-control_dev, 0);
+ if (phy-phy_power_syscon) {
+ val = PIPE3_PHY_TX_RX_POWEROFF
+ PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
+
+ ret = regmap_update_bits(phy-phy_power_syscon, phy-power_reg,
+PIPE3_PHY_PWRCTL_CLK_CMD_MASK, val);
+ if (ret 0)
+ return ret;
+ } else {
+ omap_control_phy_power(phy-control_dev, 0);
+ }
return 0;
}
static int ti_pipe3_power_on(struct phy *x)
{
+ u32 val;
+ u32 mask;
+ int ret;
+ unsigned long rate;
struct ti_pipe3 *phy = phy_get_drvdata(x);
- omap_control_phy_power(phy-control_dev, 1);
+ if (phy-phy_power_syscon) {
+ rate = clk_get_rate(phy-sys_clk);
what if clk_get_rate() returns 0?
hmm.. If '0' is an error value of clk_get_rate() then it would be good to
return with an error message.
+ rate = rate / 100;
+ mask = OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
+ OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK;
+ val = PIPE3_PHY_TX_RX_POWERON
+ PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
+ val |= rate OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
+
+ ret = regmap_update_bits(phy-phy_power_syscon, phy-power_reg,
+mask, val);
+ if (ret 0)
+ return ret;
+ } else {
+ omap_control_phy_power(phy-control_dev, 1);
+ }
return 0;
}
@@ -417,19 +459,42 @@ static int ti_pipe3_probe(struct platform_device *pdev)
phy-div_clk = ERR_PTR(-ENODEV);
}
- control_node = of_parse_phandle(node,
Re: [PATCH 17/17] ARM: dts: omap4: Use syscon-otghs instead of ctrl-module in USB node
* Kishon Vijay Abraham I kis...@ti.com [150624 04:23]:
On Wednesday 24 June 2015 04:11 PM, Tony Lindgren wrote:
* Kishon Vijay Abraham I kis...@ti.com [150623 05:02]:
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -852,12 +852,6 @@
};
};
- omap_control_usbotg: control-phy@4a00233c {
- compatible = ti,control-phy-otghs;
- reg = 0x4a00233c 0x4;
- reg-names = otghs_control;
- };
-
usb_otg_hs: usb_otg_hs@4a0ab000 {
compatible = ti,omap4-musb;
reg = 0x4a0ab000 0x7ff;
@@ -870,7 +864,7 @@
multipoint = 1;
num-eps = 16;
ram-bits = 12;
- ctrl-module = omap_control_usbotg;
+ syscon-otghs = scm_conf 0x33c;
};
aes: aes@4b501000 {
We should still keep a separate entry for the phy in the dtsi
files. And the phy should be a child of the scm_conf area in the
dtsi file.
This is because the scm and usb_otg_hs are separate devices and
can be clocked separately. So the phy driver needs to be a
separate driver to avoid spaghetti code and issues with clocking.
AFAIK SCM is clocked by L4CFG_L4_GICLK which is either free running or is
managed automatically by the HW i.e gated when there is no access to the
CTRL_MODULE_CORE registers.
The point is they are separate devices on the interconnect. And we
don't want to add dependencies between separate devices. And there
is nothing stopping us from starting to idle the SCM module.
Having a separate control-PHY driver only to do a regmap update to SCM is
unnecessary IMHO.
Not true. The phy driver can be generic and used by multiple platforms.
And the phy driver should be capable of idling the phy separately
independent of the USB module. And the phy driver should be able to
tell the system things like ID pin status, VBUS status and so on.
So to summarize, we are _not_ going to start tinkering with the sycon
registers directly from random device drivers in a separate IO space.
Anything using the syscon registers must implement a driver for some
Linux generic framework such as phy, clock, or regulator framework.
Regards,
Tony
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Re: [PATCH V2 4/5] drivers/rtc/rtc-ds1307.c: Support optional wakeup interrupt source
* Nishanth Menon n...@ti.com [150623 09:21]: With the recent pinctrl-single changes, SoCs such as Texas Instrument's OMAP processors can treat wake-up events from deeper idle states as interrupts. Let's add support for the optional second interrupt for wake-up using the generic wakeirq support added in commit 4990d4fe327b (PM / Wakeirq: Add automated device wake IRQ handling) Finally, to pass the wake-up interrupt in the dts file, interrupts-extended property needs to be passed. This is similar in approach to commit 2a0b965cfb6e (serial: omap: Add support for optional wake-up) + ee83bd3b6483 (serial: omap: Switch wake-up interrupt to generic wakeirq) The wakeirq related changes look good to me: Acked-by: Tony Lindgren t...@atomide.com -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 11/17] ARM: dts: dra7: Use ti,dra7x-usb2-phy2 compatible string for USB2 PHY2
On Tue, 23 Jun 2015 17:28:56 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
The USB2 PHY2 has a different register map compared to USB2 PHY1
to power on/off the PHY. In order to handle it, use the new compatible
string ti,dra7x-usb2-phy2 for the second instance of USB2 PHY.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index f69db70..a8ee829 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1235,7 +1235,7 @@
};
usb2_phy2: phy@4a085000 {
- compatible = ti,omap-usb2;
+ compatible = ti,dra7x-usb2-phy2,
ti,omap-usb2;
Why do you want to retain ti,omap-usb2.
It is not backward compatible with it right?
reg = 0x4a085000 0x400;
ctrl-module = omap_control_usb2phy2;
clocks = usb_phy2_always_on_clk32k,
--
1.7.9.5
cheers,
-roger
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Re: [PATCH 09/17] ARM: dts: dra7: Use syscon-phy-power instead of ctrl-module in SATA PHY node
On Wed, 24 Jun 2015 15:06:02 +0300
Roger Quadros rog...@ti.com wrote:
On Tue, 23 Jun 2015 17:28:54 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
Add syscon-phy-power property and remove the deprecated ctrl-module
property from SATA PHY node. Since omap_control_sata note is no longer
used, remove it.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Acked-by: Roger Quadros rog...@ti.com
One comment though.
---
arch/arm/boot/dts/dra7.dtsi | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 3f434f7..92e0741 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1115,14 +1115,6 @@
status = disabled;
};
- omap_control_sata: control-phy@4a002374 {
- compatible = ti,control-phy-pipe3;
- reg = 0x4a002374 0x4;
- reg-names = power;
- clocks = sys_clkin1;
- clock-names = sysclk;
- };
-
/* OCP2SCP3 */
ocp2scp@4a09 {
compatible = ti,omap-ocp2scp;
@@ -1137,7 +1129,7 @@
0x4A096400 0x64, /* phy_tx */
0x4A096800 0x40; /* pll_ctrl */
reg-names = phy_rx, phy_tx, pll_ctrl;
- ctrl-module = omap_control_sata;
+ syscon-phy-power = dra7_ctrl_core 0x374;
why can't we use scm_conf instead of dra7_ctrl_core?
dra7_ctrl_core seems to be redundant and wrongly placed.
clocks = sys_clkin1, sata_ref_clk;
clock-names = sysclk, refclk;
syscon-pllreset = dra7_ctrl_core 0x3fc;
--
1.7.9.5
cheers,
-roger
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Re: [PATCH 17/17] ARM: dts: omap4: Use syscon-otghs instead of ctrl-module in USB node
Hi Tony,
On Wednesday 24 June 2015 04:11 PM, Tony Lindgren wrote:
* Kishon Vijay Abraham I kis...@ti.com [150623 05:02]:
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -852,12 +852,6 @@
};
};
- omap_control_usbotg: control-phy@4a00233c {
- compatible = ti,control-phy-otghs;
- reg = 0x4a00233c 0x4;
- reg-names = otghs_control;
- };
-
usb_otg_hs: usb_otg_hs@4a0ab000 {
compatible = ti,omap4-musb;
reg = 0x4a0ab000 0x7ff;
@@ -870,7 +864,7 @@
multipoint = 1;
num-eps = 16;
ram-bits = 12;
- ctrl-module = omap_control_usbotg;
+ syscon-otghs = scm_conf 0x33c;
};
aes: aes@4b501000 {
We should still keep a separate entry for the phy in the dtsi
files. And the phy should be a child of the scm_conf area in the
dtsi file.
This is because the scm and usb_otg_hs are separate devices and
can be clocked separately. So the phy driver needs to be a
separate driver to avoid spaghetti code and issues with clocking.
AFAIK SCM is clocked by L4CFG_L4_GICLK which is either free running or is
managed automatically by the HW i.e gated when there is no access to the
CTRL_MODULE_CORE registers.
Having a separate control-PHY driver only to do a regmap update to SCM is
unnecessary IMHO.
Thanks
Kishon
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Re: [PATCH 08/17] ARM: dts: dra7: Add dt node for the sycon pcie
On Tue, 23 Jun 2015 17:28:53 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
Add new device tree node for the control module register space where
PCIe registers are present.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 260f300..3f434f7 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -291,6 +291,11 @@
reg = 0x4a002e00 0x7c;
};
+ dra7_ctrl_pcie: tisyscon@4a003c00 {
+ compatible = syscon;
+ reg = 0x4a003c00 0x48;
+ };
+
Why do you need to start from 0x4a003c00?
CTRL_CORE_PCIESS1_PCS1 is at 0x4a003c24
sdma: dma-controller@4a056000 {
compatible = ti,omap4430-sdma;
reg = 0x4a056000 0x1000;
--
1.7.9.5
cheers,
-roger
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Re: [PATCH 09/17] ARM: dts: dra7: Use syscon-phy-power instead of ctrl-module in SATA PHY node
On Tue, 23 Jun 2015 17:28:54 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
Add syscon-phy-power property and remove the deprecated ctrl-module
property from SATA PHY node. Since omap_control_sata note is no longer
used, remove it.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Acked-by: Roger Quadros rog...@ti.com
cheers,
-roger
---
arch/arm/boot/dts/dra7.dtsi | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 3f434f7..92e0741 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1115,14 +1115,6 @@
status = disabled;
};
- omap_control_sata: control-phy@4a002374 {
- compatible = ti,control-phy-pipe3;
- reg = 0x4a002374 0x4;
- reg-names = power;
- clocks = sys_clkin1;
- clock-names = sysclk;
- };
-
/* OCP2SCP3 */
ocp2scp@4a09 {
compatible = ti,omap-ocp2scp;
@@ -1137,7 +1129,7 @@
0x4A096400 0x64, /* phy_tx */
0x4A096800 0x40; /* pll_ctrl */
reg-names = phy_rx, phy_tx, pll_ctrl;
- ctrl-module = omap_control_sata;
+ syscon-phy-power = dra7_ctrl_core 0x374;
clocks = sys_clkin1, sata_ref_clk;
clock-names = sysclk, refclk;
syscon-pllreset = dra7_ctrl_core 0x3fc;
--
1.7.9.5
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Re: [PATCH 08/17] ARM: dts: dra7: Add dt node for the sycon pcie
On Wed, 24 Jun 2015 05:09:39 -0700
Tony Lindgren t...@atomide.com wrote:
* Roger Quadros rog...@ti.com [150624 04:58]:
On Wed, 24 Jun 2015 14:50:17 +0300
Roger Quadros rog...@ti.com wrote:
On Tue, 23 Jun 2015 17:28:53 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
Add new device tree node for the control module register space where
PCIe registers are present.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 260f300..3f434f7 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -291,6 +291,11 @@
reg = 0x4a002e00 0x7c;
};
+ dra7_ctrl_pcie: tisyscon@4a003c00 {
+ compatible = syscon;
+ reg = 0x4a003c00 0x48;
+ };
+
Why do you need to start from 0x4a003c00?
CTRL_CORE_PCIESS1_PCS1 is at 0x4a003c24
Also, why can't this dra7_ctrl_pcie node be where scm_conf is.
Yes all the scm children should be under scm@2000 entry in the
dra7.dtsi file.
And BTW, there's nothing stopping a driver doing of_ioremap
on a larger range and be a child under scm@2000 in the dra7.dtsi
if that range is dedicated to a single driver.
Agreed.
My take is we should only use regmap for the scm_conf area
in general.
+1
should we get rid of dra7_ctrl_core and dra7_ctrl_general?
or move them to scm node?
cheers,
-roger
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Re: [PATCH 08/17] ARM: dts: dra7: Add dt node for the sycon pcie
* Roger Quadros rog...@ti.com [150624 05:21]: On Wed, 24 Jun 2015 05:09:39 -0700 Tony Lindgren t...@atomide.com wrote: My take is we should only use regmap for the scm_conf area in general. +1 should we get rid of dra7_ctrl_core and dra7_ctrl_general? or move them to scm node? Well at least move them. And if there are clear dedicated register ranges there claimed only by a single device driver, then those drivers should be just regular loadable driver modules doing of_ioremap on the range. And in that case they can be removed. We have examples of both in dra7.dtsi, pbias_regulator using the scm_conf via syscon, and then dra7_pmx_core ioremapping a dedicated register range. So unless there are other messy register ranges like the scm_conf area then there should not be need for other syscon areas. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 07/17] usb: musb: omap2430: use *syscon* framework to write to mailbox register
Hi Tony, On Wednesday 24 June 2015 05:19 PM, Tony Lindgren wrote: * Kishon Vijay Abraham I kis...@ti.com [150623 05:02]: Deprecate using phy-omap-control driver to write to the mailbox register and start using *syscon* framework to do the same. All this stuff needs to go to some generic syscon USB phy driver. Let's not start adding phy specific stuff to a USB driver. Mailbox register is actually part of OMAP USB glue that should be written in order to inform the usbmode to the MUSB core. Thanks Kishon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 07/17] usb: musb: omap2430: use *syscon* framework to write to mailbox register
On Tue, 23 Jun 2015 17:28:52 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
Deprecate using phy-omap-control driver to write to the mailbox register
and start using *syscon* framework to do the same.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/usb/omap-usb.txt |7 +-
drivers/usb/musb/omap2430.c| 118
2 files changed, 102 insertions(+), 23 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt
b/Documentation/devicetree/bindings/usb/omap-usb.txt
index 38d9bb8..c001306 100644
--- a/Documentation/devicetree/bindings/usb/omap-usb.txt
+++ b/Documentation/devicetree/bindings/usb/omap-usb.txt
@@ -20,10 +20,15 @@ OMAP MUSB GLUE
- phy-names : the names of the PHY corresponding to the PHYs present in the
*phy* phandle.
-Optional properties:
+Optional Properties:
+Deprecated properties:
- ctrl-module : phandle of the control module this glue uses to write to
mailbox
+Recommended properies:
+ - syscon-otghs : phandle/offset pair. Phandle to the system control module
and the
+ register offset of the mailbox.
+
SOC specific device node entry
usb_otg_hs: usb_otg_hs@4a0ab000 {
compatible = ti,omap4-musb;
diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
index cc752d8..bcd6d1e 100644
--- a/drivers/usb/musb/omap2430.c
+++ b/drivers/usb/musb/omap2430.c
@@ -39,16 +39,27 @@
#include linux/usb/musb-omap.h
#include linux/phy/omap_control_phy.h
#include linux/of_platform.h
+#include linux/regmap.h
+#include linux/mfd/syscon.h
#include musb_core.h
#include omap2430.h
+#define OMAP2430_MUSB_MODE_MASK 0x1f
+#define OMAP2430_MUSB_AVALID (0x1 0)
+#define OMAP2430_MUSB_BVALID (0x1 1)
+#define OMAP2430_MUSB_VBUSVALID (0x1 2)
+#define OMAP2430_MUSB_SESSEND(0x1 3)
+#define OMAP2430_MUSB_IDDIG (0x1 4)
+
struct omap2430_glue {
struct device *dev;
struct platform_device *musb;
enum omap_musb_vbus_id_status status;
struct work_struct omap_musb_mailbox_work;
struct device *control_otghs;
+ struct regmap *syscon_otghs; /* ctrl. reg. acces */
+ unsigned intotghs_reg; /* otghs reg. index within syscon */
};
#define glue_to_musb(g) platform_get_drvdata(g-musb)
@@ -253,6 +264,47 @@ void omap_musb_mailbox(enum omap_musb_vbus_id_status
status)
}
EXPORT_SYMBOL_GPL(omap_musb_mailbox);
+static void omap2430_musb_set_usbmode(struct omap2430_glue *glue,
+ enum omap_control_usb_mode mode)
+{
+ u32 val;
+ int ret;
+
+ if (glue-syscon_otghs) {
+ switch (mode) {
+ case USB_MODE_HOST:
+ val = OMAP2430_MUSB_AVALID | OMAP2430_MUSB_VBUSVALID;
+ break;
+
+ case USB_MODE_DEVICE:
+ val = OMAP2430_MUSB_IDDIG | OMAP2430_MUSB_AVALID |
+ OMAP2430_MUSB_VBUSVALID;
+ break;
+
+ case USB_MODE_DISCONNECT:
+ val = OMAP2430_MUSB_IDDIG | OMAP2430_MUSB_SESSEND;
+ break;
+
+ default:
+ dev_dbg(glue-dev, Invalid mode\n);
+ goto err_regmap_update;
+ }
+
+ ret = regmap_update_bits(glue-syscon_otghs,
+ glue-otghs_reg,
+ OMAP2430_MUSB_MODE_MASK, val);
+ if (ret 0)
+ goto err_regmap_update;
+ } else {
+ omap_control_usb_set_mode(glue-control_otghs, mode);
+ }
+
+ return;
+
+err_regmap_update:
+ dev_err(glue-dev, Failed to set mode to %d\n, mode);
+}
+
static void omap_musb_set_mailbox(struct omap2430_glue *glue)
{
struct musb *musb = glue_to_musb(glue);
@@ -270,8 +322,7 @@ static void omap_musb_set_mailbox(struct omap2430_glue
*glue)
musb-xceiv-last_event = USB_EVENT_ID;
if (musb-gadget_driver) {
pm_runtime_get_sync(dev);
- omap_control_usb_set_mode(glue-control_otghs,
- USB_MODE_HOST);
+ omap2430_musb_set_usbmode(glue, USB_MODE_HOST);
omap2430_musb_set_vbus(musb, 1);
}
break;
@@ -284,7 +335,7 @@ static void omap_musb_set_mailbox(struct omap2430_glue
*glue)
musb-xceiv-last_event = USB_EVENT_VBUS;
if (musb-gadget_driver)
pm_runtime_get_sync(dev);
- omap_control_usb_set_mode(glue-control_otghs, USB_MODE_DEVICE);
+ omap2430_musb_set_usbmode(glue, USB_MODE_DEVICE);
break;
case OMAP_MUSB_ID_FLOAT:
@@ -301,8 +352,7 @@ static void
Re: [PATCH 07/17] usb: musb: omap2430: use *syscon* framework to write to mailbox register
Hi,
On Wednesday 24 June 2015 05:09 PM, Roger Quadros wrote:
On Tue, 23 Jun 2015 17:28:52 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
Deprecate using phy-omap-control driver to write to the mailbox register
and start using *syscon* framework to do the same.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/usb/omap-usb.txt |7 +-
drivers/usb/musb/omap2430.c| 118
2 files changed, 102 insertions(+), 23 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt
b/Documentation/devicetree/bindings/usb/omap-usb.txt
index 38d9bb8..c001306 100644
--- a/Documentation/devicetree/bindings/usb/omap-usb.txt
+++ b/Documentation/devicetree/bindings/usb/omap-usb.txt
@@ -20,10 +20,15 @@ OMAP MUSB GLUE
- phy-names : the names of the PHY corresponding to the PHYs present in the
*phy* phandle.
-Optional properties:
+Optional Properties:
+Deprecated properties:
- ctrl-module : phandle of the control module this glue uses to write to
mailbox
+Recommended properies:
+ - syscon-otghs : phandle/offset pair. Phandle to the system control module
and the
+ register offset of the mailbox.
+
SOC specific device node entry
usb_otg_hs: usb_otg_hs@4a0ab000 {
compatible = ti,omap4-musb;
diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
index cc752d8..bcd6d1e 100644
--- a/drivers/usb/musb/omap2430.c
+++ b/drivers/usb/musb/omap2430.c
@@ -39,16 +39,27 @@
#include linux/usb/musb-omap.h
#include linux/phy/omap_control_phy.h
#include linux/of_platform.h
+#include linux/regmap.h
+#include linux/mfd/syscon.h
#include musb_core.h
#include omap2430.h
+#define OMAP2430_MUSB_MODE_MASK 0x1f
+#define OMAP2430_MUSB_AVALID(0x1 0)
+#define OMAP2430_MUSB_BVALID(0x1 1)
+#define OMAP2430_MUSB_VBUSVALID (0x1 2)
+#define OMAP2430_MUSB_SESSEND (0x1 3)
+#define OMAP2430_MUSB_IDDIG (0x1 4)
+
struct omap2430_glue {
struct device *dev;
struct platform_device *musb;
enum omap_musb_vbus_id_status status;
struct work_struct omap_musb_mailbox_work;
struct device *control_otghs;
+struct regmap *syscon_otghs; /* ctrl. reg. acces */
+unsigned intotghs_reg; /* otghs reg. index within syscon */
};
#define glue_to_musb(g) platform_get_drvdata(g-musb)
@@ -253,6 +264,47 @@ void omap_musb_mailbox(enum omap_musb_vbus_id_status
status)
}
EXPORT_SYMBOL_GPL(omap_musb_mailbox);
+static void omap2430_musb_set_usbmode(struct omap2430_glue *glue,
+ enum omap_control_usb_mode mode)
+{
+u32 val;
+int ret;
+
+if (glue-syscon_otghs) {
+switch (mode) {
+case USB_MODE_HOST:
+val = OMAP2430_MUSB_AVALID | OMAP2430_MUSB_VBUSVALID;
+break;
+
+case USB_MODE_DEVICE:
+val = OMAP2430_MUSB_IDDIG | OMAP2430_MUSB_AVALID |
+OMAP2430_MUSB_VBUSVALID;
+break;
+
+case USB_MODE_DISCONNECT:
+val = OMAP2430_MUSB_IDDIG | OMAP2430_MUSB_SESSEND;
+break;
+
+default:
+dev_dbg(glue-dev, Invalid mode\n);
+goto err_regmap_update;
+}
+
+ret = regmap_update_bits(glue-syscon_otghs,
+ glue-otghs_reg,
+ OMAP2430_MUSB_MODE_MASK, val);
+if (ret 0)
+goto err_regmap_update;
+} else {
+omap_control_usb_set_mode(glue-control_otghs, mode);
+}
+
+return;
+
+err_regmap_update:
+dev_err(glue-dev, Failed to set mode to %d\n, mode);
+}
+
static void omap_musb_set_mailbox(struct omap2430_glue *glue)
{
struct musb *musb = glue_to_musb(glue);
@@ -270,8 +322,7 @@ static void omap_musb_set_mailbox(struct omap2430_glue
*glue)
musb-xceiv-last_event = USB_EVENT_ID;
if (musb-gadget_driver) {
pm_runtime_get_sync(dev);
-omap_control_usb_set_mode(glue-control_otghs,
-USB_MODE_HOST);
+omap2430_musb_set_usbmode(glue, USB_MODE_HOST);
omap2430_musb_set_vbus(musb, 1);
}
break;
@@ -284,7 +335,7 @@ static void omap_musb_set_mailbox(struct omap2430_glue
*glue)
musb-xceiv-last_event = USB_EVENT_VBUS;
if (musb-gadget_driver)
pm_runtime_get_sync(dev);
-omap_control_usb_set_mode(glue-control_otghs, USB_MODE_DEVICE);
+omap2430_musb_set_usbmode(glue, USB_MODE_DEVICE);
break;
case OMAP_MUSB_ID_FLOAT:
@@ -301,8 +352,7
Re: [PATCH 08/17] ARM: dts: dra7: Add dt node for the sycon pcie
Hi,
On Wednesday 24 June 2015 05:26 PM, Roger Quadros wrote:
On Wed, 24 Jun 2015 14:50:17 +0300
Roger Quadros rog...@ti.com wrote:
On Tue, 23 Jun 2015 17:28:53 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
Add new device tree node for the control module register space where
PCIe registers are present.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 260f300..3f434f7 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -291,6 +291,11 @@
reg = 0x4a002e00 0x7c;
};
+ dra7_ctrl_pcie: tisyscon@4a003c00 {
+ compatible = syscon;
+ reg = 0x4a003c00 0x48;
+ };
+
Why do you need to start from 0x4a003c00?
CTRL_CORE_PCIESS1_PCS1 is at 0x4a003c24
Also, why can't this dra7_ctrl_pcie node be where scm_conf is.
Yes. I think that's the right thing to do. I saw dra7_ctrl_core and
dra7_ctrl_general and added it.
Thanks
Kishon
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Re: [PATCH 03/17] phy: ti-pipe3: use *syscon* framework to set PCS value of the PHY
Hi,
On Wednesday 24 June 2015 04:04 PM, Roger Quadros wrote:
On Tue, 23 Jun 2015 17:28:48 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
Deprecate using phy-omap-control driver to set PCS value of the PHY
and start using *syscon* framework to do the same.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt |2 ++
drivers/phy/phy-ti-pipe3.c | 32
+-
2 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index d3ad3bf..52c7a92 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -83,6 +83,8 @@ Optional properties:
- syscon-pllreset: Handle to system control region that contains the
CTRL_CORE_SMA_SW_0 register and register offset to the
CTRL_CORE_SMA_SW_0
register that contains the SATA_PLL_SOFT_RESET bit. Only valid for
sata_phy.
+ - syscon-pcs : phandle/offset pair. Phandle to the system control module
and the
+ register offset to write the PCS delay value.
What is PCS?
IIRC physical coding subsystem.
Is this valid only for PCIe? If yes we could mention it here.
This is introduced specifically for PCIe. But there are other PCS registers
with a different register map altogether for USB. I'm not sure if we will ever
have to do those settings.
Thanks
Kishon
Deprecated properties:
- ctrl-module : phandle of the control module used by PHY driver to power
on
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index 78bac00..e2f9ad7 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -65,6 +65,9 @@
#define PIPE3_PHY_TX_RX_POWERON0x3
#define PIPE3_PHY_TX_RX_POWEROFF 0x0
+#define PCIE_PCS_MASK 0xFF
+#define PCIE_PCS_DELAY_COUNT_SHIFT 0x10
+
/*
* This is an Empirical value that works, need to confirm the actual
* value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
@@ -96,9 +99,11 @@ struct ti_pipe3 {
struct clk *div_clk;
struct pipe3_dpll_map *dpll_map;
struct regmap *phy_power_syscon; /* ctrl. reg. acces */
+struct regmap *pcs_syscon; /* ctrl. reg. acces */
struct regmap *dpll_reset_syscon; /* ctrl. reg. acces */
unsigned intdpll_reset_reg; /* reg. index within syscon */
unsigned intpower_reg; /* power reg. index within syscon */
+unsigned intpcie_pcs_reg; /* pcs reg. index in syscon */
boolsata_refclk_enabled;
};
@@ -271,7 +276,16 @@ static int ti_pipe3_init(struct phy *x)
* 18-1804.
*/
if (of_device_is_compatible(phy-dev-of_node, ti,phy-pipe3-pcie)) {
-omap_control_pcie_pcs(phy-control_dev, 0x96);
+if (phy-pcs_syscon) {
+val = 0x96 OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT;
+ret = regmap_update_bits(phy-pcs_syscon,
+ phy-pcie_pcs_reg,
+ PCIE_PCS_MASK, val);
+if (ret 0)
+return ret;
+} else {
+omap_control_pcie_pcs(phy-control_dev, 0x96);
+}
return 0;
}
@@ -455,6 +469,22 @@ static int ti_pipe3_probe(struct platform_device *pdev)
dev_err(pdev-dev, unable to get div-clk\n);
return PTR_ERR(phy-div_clk);
}
+
+phy-pcs_syscon = syscon_regmap_lookup_by_phandle(node,
+ syscon-pcs);
+if (IS_ERR(phy-pcs_syscon)) {
+dev_dbg(pdev-dev,
+ can't get syscon-pcs, using omap control\n);
+phy-pcs_syscon = NULL;
+} else {
+if (of_property_read_u32_index(node,
+ syscon-pcs, 1,
+ phy-pcie_pcs_reg)) {
+dev_err(pdev-dev,
+couldn't get pcie pcs reg. offset\n);
+return -EINVAL;
+}
+}
} else {
phy-div_clk = ERR_PTR(-ENODEV);
}
--
1.7.9.5
Other than that,
Acked-by: Roger Quadros rog...@ti.com
cheers,
-roger
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Re: [PATCH 08/17] ARM: dts: dra7: Add dt node for the sycon pcie
Hi,
On Wednesday 24 June 2015 05:20 PM, Roger Quadros wrote:
On Tue, 23 Jun 2015 17:28:53 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
Add new device tree node for the control module register space where
PCIe registers are present.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 260f300..3f434f7 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -291,6 +291,11 @@
reg = 0x4a002e00 0x7c;
};
+dra7_ctrl_pcie: tisyscon@4a003c00 {
+compatible = syscon;
+reg = 0x4a003c00 0x48;
+};
+
Why do you need to start from 0x4a003c00?
CTRL_CORE_PCIESS1_PCS1 is at 0x4a003c24
Actually wanted to have minimum number of syscon dt nodes. So thought even
others can use dra7_ctrl_pcie phandle. But I looked only at dra7_ctrl_core and
dra7_ctrl_general and not scm_conf :-(
Thanks
Kishon
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Re: [PATCH 11/17] ARM: dts: dra7: Use ti,dra7x-usb2-phy2 compatible string for USB2 PHY2
On Wed, 24 Jun 2015 18:40:31 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
Hi,
On Wednesday 24 June 2015 05:37 PM, Roger Quadros wrote:
On Tue, 23 Jun 2015 17:28:56 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
The USB2 PHY2 has a different register map compared to USB2 PHY1
to power on/off the PHY. In order to handle it, use the new compatible
string ti,dra7x-usb2-phy2 for the second instance of USB2 PHY.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index f69db70..a8ee829 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1235,7 +1235,7 @@
};
usb2_phy2: phy@4a085000 {
- compatible = ti,omap-usb2;
+ compatible = ti,dra7x-usb2-phy2,
ti,omap-usb2;
Why do you want to retain ti,omap-usb2.
It is not backward compatible with it right?
The newer dtbs will anyway have ti,dra7x-usb2-phy2, so ti,omap-usb2 was
kept just for legacy reasons.
OK then.
cheers,
-roger
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Re: [PATCH V2 0/5] drivers/rtc/rtc-ds1307.c: Basic cleanups and support for wakeupirq
Hi, On Tue, Jun 23, 2015 at 11:15:09AM -0500, Nishanth Menon wrote: Hi, Here is the revamp of the patch posted eariler to support wakeupirq. This series does a few cleanups as well prior to introducing the generic apis required to support the wakeirq mechanism used on certain TI SoCs. Cleanups done here are just minimal set of the cleanups we discussed in [2]. Series is based on next-20150623 Test log: http://pastebin.ubuntu.com/11763002/ NOTE1: I have only tested in mcp79410 device, and not on other ds1307-rtc driver compatbile devices as I dont have any other. additional testing might be nice to have. NOTE2: there are additional fixes that linux-next seems to need but those are in omap-rtc, cpufreq etc, but those are not related by the ds-1307. V1: https://patchwork.kernel.org/patch/4759171/ NOTE: Patch 5/5 of the series is meant to indicate the usage, and will be reposted along with other wakeup sources to be enabled once the driver changes are accepted. Felipe Balbi (1): drivers/rtc/rtc-ds1307.c: Convert to threaded IRQ Nishanth Menon (4): drivers/rtc/rtc-ds1307.c: Switch to managed irq allocation drivers/rtc/rtc-ds1307.c: Sort the headers drivers/rtc/rtc-ds1307.c: Support optional wakeup interrupt source for the series, except the patch which I wrote : Acked-by: Felipe Balbi ba...@ti.com -- balbi signature.asc Description: Digital signature
[4.2-rc1][PATCH] gpio: omap: add missed spin_unlock_irqrestore in omap_gpio_irq_type
From: Grygorii Strashko grygorii.stras...@linaro.org
Add missed spin_unlock_irqrestore in omap_gpio_irq_type when
omap_set_gpio_triggering() is failed.
It fixes static checker warning:
drivers/gpio/gpio-omap.c:523 omap_gpio_irq_type()
warn: inconsistent returns 'spin_lock:bank-lock'.
This fixes commit:
1562e4618ded ('gpio: omap: fix error handling in omap_gpio_irq_type')
Reported-by: Javier Martinez Canillas jav...@dowhile0.org
Signed-off-by: Grygorii Strashko grygorii.stras...@linaro.org
---
drivers/gpio/gpio-omap.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index b0c57d5..a0ad803 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -500,8 +500,10 @@ static int omap_gpio_irq_type(struct irq_data *d, unsigned
type)
spin_lock_irqsave(bank-lock, flags);
retval = omap_set_gpio_triggering(bank, offset, type);
- if (retval)
+ if (retval) {
+ spin_unlock_irqrestore(bank-lock, flags);
goto error;
+ }
omap_gpio_init_irq(bank, offset);
if (!omap_gpio_is_input(bank, offset)) {
spin_unlock_irqrestore(bank-lock, flags);
--
2.4.4
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Re: [PATCH 11/17] ARM: dts: dra7: Use ti,dra7x-usb2-phy2 compatible string for USB2 PHY2
Hi,
On Wednesday 24 June 2015 05:37 PM, Roger Quadros wrote:
On Tue, 23 Jun 2015 17:28:56 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
The USB2 PHY2 has a different register map compared to USB2 PHY1
to power on/off the PHY. In order to handle it, use the new compatible
string ti,dra7x-usb2-phy2 for the second instance of USB2 PHY.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index f69db70..a8ee829 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1235,7 +1235,7 @@
};
usb2_phy2: phy@4a085000 {
-compatible = ti,omap-usb2;
+compatible = ti,dra7x-usb2-phy2,
ti,omap-usb2;
Why do you want to retain ti,omap-usb2.
It is not backward compatible with it right?
The newer dtbs will anyway have ti,dra7x-usb2-phy2, so ti,omap-usb2 was
kept just for legacy reasons.
Thanks
Kishon
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Re: [PATCH 09/17] ARM: dts: dra7: Use syscon-phy-power instead of ctrl-module in SATA PHY node
On Wednesday 24 June 2015 05:42 PM, Roger Quadros wrote:
On Wed, 24 Jun 2015 15:06:02 +0300
Roger Quadros rog...@ti.com wrote:
On Tue, 23 Jun 2015 17:28:54 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
Add syscon-phy-power property and remove the deprecated ctrl-module
property from SATA PHY node. Since omap_control_sata note is no longer
used, remove it.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Acked-by: Roger Quadros rog...@ti.com
One comment though.
---
arch/arm/boot/dts/dra7.dtsi | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 3f434f7..92e0741 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1115,14 +1115,6 @@
status = disabled;
};
- omap_control_sata: control-phy@4a002374 {
- compatible = ti,control-phy-pipe3;
- reg = 0x4a002374 0x4;
- reg-names = power;
- clocks = sys_clkin1;
- clock-names = sysclk;
- };
-
/* OCP2SCP3 */
ocp2scp@4a09 {
compatible = ti,omap-ocp2scp;
@@ -1137,7 +1129,7 @@
0x4A096400 0x64, /* phy_tx */
0x4A096800 0x40; /* pll_ctrl */
reg-names = phy_rx, phy_tx, pll_ctrl;
- ctrl-module = omap_control_sata;
+ syscon-phy-power = dra7_ctrl_core 0x374;
why can't we use scm_conf instead of dra7_ctrl_core?
dra7_ctrl_core seems to be redundant and wrongly placed.
Agreed!
Thanks
Kishon
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Re: [PATCH 03/17] phy: ti-pipe3: use *syscon* framework to set PCS value of the PHY
On Wed, 24 Jun 2015 18:46:08 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
Hi,
On Wednesday 24 June 2015 04:04 PM, Roger Quadros wrote:
On Tue, 23 Jun 2015 17:28:48 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
Deprecate using phy-omap-control driver to set PCS value of the PHY
and start using *syscon* framework to do the same.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt |2 ++
drivers/phy/phy-ti-pipe3.c | 32
+-
2 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index d3ad3bf..52c7a92 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -83,6 +83,8 @@ Optional properties:
- syscon-pllreset: Handle to system control region that contains the
CTRL_CORE_SMA_SW_0 register and register offset to the
CTRL_CORE_SMA_SW_0
register that contains the SATA_PLL_SOFT_RESET bit. Only valid for
sata_phy.
+ - syscon-pcs : phandle/offset pair. Phandle to the system control module
and the
+ register offset to write the PCS delay value.
What is PCS?
IIRC physical coding subsystem.
Is this valid only for PCIe? If yes we could mention it here.
This is introduced specifically for PCIe. But there are other PCS registers
with a different register map altogether for USB. I'm not sure if we will ever
have to do those settings.
OK then let's not say it is PCIe specific.
cheers,
-roger
Deprecated properties:
- ctrl-module : phandle of the control module used by PHY driver to
power on
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index 78bac00..e2f9ad7 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -65,6 +65,9 @@
#define PIPE3_PHY_TX_RX_POWERON 0x3
#define PIPE3_PHY_TX_RX_POWEROFF 0x0
+#define PCIE_PCS_MASK 0xFF
+#define PCIE_PCS_DELAY_COUNT_SHIFT0x10
+
/*
* This is an Empirical value that works, need to confirm the actual
* value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
@@ -96,9 +99,11 @@ struct ti_pipe3 {
struct clk *div_clk;
struct pipe3_dpll_map *dpll_map;
struct regmap *phy_power_syscon; /* ctrl. reg. acces */
+ struct regmap *pcs_syscon; /* ctrl. reg. acces */
struct regmap *dpll_reset_syscon; /* ctrl. reg. acces */
unsigned intdpll_reset_reg; /* reg. index within syscon */
unsigned intpower_reg; /* power reg. index within syscon */
+ unsigned intpcie_pcs_reg; /* pcs reg. index in syscon */
boolsata_refclk_enabled;
};
@@ -271,7 +276,16 @@ static int ti_pipe3_init(struct phy *x)
* 18-1804.
*/
if (of_device_is_compatible(phy-dev-of_node, ti,phy-pipe3-pcie)) {
- omap_control_pcie_pcs(phy-control_dev, 0x96);
+ if (phy-pcs_syscon) {
+ val = 0x96 OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT;
+ ret = regmap_update_bits(phy-pcs_syscon,
+ phy-pcie_pcs_reg,
+ PCIE_PCS_MASK, val);
+ if (ret 0)
+ return ret;
+ } else {
+ omap_control_pcie_pcs(phy-control_dev, 0x96);
+ }
return 0;
}
@@ -455,6 +469,22 @@ static int ti_pipe3_probe(struct platform_device
*pdev)
dev_err(pdev-dev, unable to get div-clk\n);
return PTR_ERR(phy-div_clk);
}
+
+ phy-pcs_syscon = syscon_regmap_lookup_by_phandle(node,
+syscon-pcs);
+ if (IS_ERR(phy-pcs_syscon)) {
+ dev_dbg(pdev-dev,
+ can't get syscon-pcs, using omap control\n);
+ phy-pcs_syscon = NULL;
+ } else {
+ if (of_property_read_u32_index(node,
+ syscon-pcs, 1,
+ phy-pcie_pcs_reg)) {
+ dev_err(pdev-dev,
+ couldn't get pcie pcs reg. offset\n);
+ return -EINVAL;
+ }
+ }
} else {
phy-div_clk = ERR_PTR(-ENODEV);
}
--
1.7.9.5
Other than that,
Acked-by: Roger Quadros rog...@ti.com
cheers,
-roger
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Re: [PATCH V2 4/5] drivers/rtc/rtc-ds1307.c: Support optional wakeup interrupt source
On 06/23/2015 07:15 PM, Nishanth Menon wrote:
With the recent pinctrl-single changes, SoCs such as Texas
Instrument's OMAP processors can treat wake-up events from deeper idle
states as interrupts.
Let's add support for the optional second interrupt for wake-up using
the generic wakeirq support added in commit 4990d4fe327b (PM /
Wakeirq: Add automated device wake IRQ handling)
Finally, to pass the wake-up interrupt in the dts file,
interrupts-extended property needs to be passed.
This is similar in approach to commit 2a0b965cfb6e (serial: omap: Add
support for optional wake-up) + ee83bd3b6483 (serial: omap: Switch
wake-up interrupt to generic wakeirq)
Signed-off-by: Nishanth Menon n...@ti.com
---
Changes since V1:
- dropped the need for specific suspend-resume handlers generic api
has adequate hooks for those
- little more code flow cleanups.
V1: https://patchwork.kernel.org/patch/4759171/
drivers/rtc/rtc-ds1307.c | 41 ++---
1 file changed, 38 insertions(+), 3 deletions(-)
diff --git a/drivers/rtc/rtc-ds1307.c b/drivers/rtc/rtc-ds1307.c
index b03880fc32b5..b00d97dbf955 100644
--- a/drivers/rtc/rtc-ds1307.c
+++ b/drivers/rtc/rtc-ds1307.c
@@ -15,6 +15,9 @@
#include linux/i2c.h
#include linux/init.h
#include linux/module.h
+#include linux/of_device.h
+#include linux/of_irq.h
+#include linux/pm_wakeirq.h
#include linux/rtc/ds1307.h
#include linux/rtc.h
#include linux/slab.h
@@ -114,6 +117,7 @@ struct ds1307 {
#define HAS_ALARM 1 /* bit 1 == irq claimed */
struct i2c_client *client;
struct rtc_device *rtc;
+ int wakeirq;
s32 (*read_block_data)(const struct i2c_client *client, u8 command,
u8 length, u8 *values);
s32 (*write_block_data)(const struct i2c_client *client, u8 command,
@@ -1156,6 +1160,8 @@ read_rtc:
}
if (want_irq) {
+ struct device_node *node = client-dev.of_node;
+
err = devm_request_threaded_irq(client-dev,
client-irq, NULL, irq_handler,
IRQF_SHARED | IRQF_ONESHOT,
@@ -1163,13 +1169,36 @@ read_rtc:
if (err) {
client-irq = 0;
dev_err(client-dev, unable to request IRQ!\n);
- } else {
+ goto no_irq;
+ }
+
+ set_bit(HAS_ALARM, ds1307-flags);
+ dev_dbg(client-dev, got IRQ %d\n, client-irq);
- set_bit(HAS_ALARM, ds1307-flags);
- dev_dbg(client-dev, got IRQ %d\n, client-irq);
+ /* Currently supported by OF code only! */
+ if (!node)
+ goto no_irq;
+
+ ds1307-wakeirq = of_irq_get(node, 1);
+ if (ds1307-wakeirq = 0) {
+ if (ds1307-wakeirq == -EPROBE_DEFER) {
+ err = ds1307-wakeirq;
+ goto exit;
+ }
+ ds1307-wakeirq = 0;
+ goto no_irq;
+ }
Might be above code could be done a little bit simpler?
err = of_irq_get(node, 1);
if (err = 0) {
if (err == -EPROBE_DEFER)
goto exit;
goto no_irq;
}
ds1307-wakeirq = err;
+
+ err = dev_pm_set_dedicated_wake_irq(client-dev,
+ ds1307-wakeirq);
+ if (err) {
+ dev_err(client-dev, unable to setup wakeIRQ %d\n,
+ err);
+ goto exit;
}
}
+no_irq:
if (chip-nvram_size) {
ds1307-nvram = devm_kzalloc(client-dev,
@@ -1206,6 +1235,9 @@ read_rtc:
return 0;
exit:
+ if (ds1307-wakeirq)
+ dev_pm_clear_wake_irq(client-dev);
+
return err;
}
@@ -1213,6 +1245,9 @@ static int ds1307_remove(struct i2c_client *client)
{
struct ds1307 *ds1307 = i2c_get_clientdata(client);
+ if (ds1307-wakeirq)
+ dev_pm_clear_wake_irq(client-dev);
+
if (test_and_clear_bit(HAS_NVRAM, ds1307-flags))
sysfs_remove_bin_file(client-dev.kobj, ds1307-nvram);
--
regards,
-grygorii
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Re: [PATCH 05/17] phy: omap-usb2: Add a new compatible string for USB2 PHY2
Hi,
On Wednesday 24 June 2015 04:33 PM, Roger Quadros wrote:
On Tue, 23 Jun 2015 17:28:50 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
The USB2 PHY2 has a different register map compared to USB2 PHY1
to power on/off the PHY. In order to handle it, add a new
compatible string.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt |2 ++
drivers/phy/phy-omap-usb2.c |9 +
2 files changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 52c7a92..b9101b9 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -31,6 +31,8 @@ OMAP USB2 PHY
Required properties:
- compatible: Should be ti,omap-usb2
+ Should be ti,dra7x-usb2-phy2 for the 2nd instance of USB2 PHY
+in DRA7x
- reg : Address and length of the register set for the device.
- #phy-cells: determine the number of cells that should be given in the
phandle while referencing this phy.
diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
index b5c266a..2f7220f 100644
--- a/drivers/phy/phy-omap-usb2.c
+++ b/drivers/phy/phy-omap-usb2.c
@@ -159,6 +159,11 @@ static const struct usb_phy_data dra7x_usb2_data = {
.flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
};
+static const struct usb_phy_data dra7x_usb2_phy2_data = {
+.label = dra7x_usb2_phy2,
+.flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
Isn't it better to define the register map in usb_phy_data
so that you don't need to check for compatible flag everytime?
We could may be define it for DRA7x USB2 PHYs but for am437x-usb2, it might not
be good.
Thanks
Kishon
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Re: [PATCH V2 0/5] drivers/rtc/rtc-ds1307.c: Basic cleanups and support for wakeupirq
On 06/24/2015 05:34 PM, Felipe Balbi wrote: Hi, On Tue, Jun 23, 2015 at 11:15:09AM -0500, Nishanth Menon wrote: Hi, Here is the revamp of the patch posted eariler to support wakeupirq. This series does a few cleanups as well prior to introducing the generic apis required to support the wakeirq mechanism used on certain TI SoCs. Cleanups done here are just minimal set of the cleanups we discussed in [2]. Series is based on next-20150623 Test log: http://pastebin.ubuntu.com/11763002/ NOTE1: I have only tested in mcp79410 device, and not on other ds1307-rtc driver compatbile devices as I dont have any other. additional testing might be nice to have. NOTE2: there are additional fixes that linux-next seems to need but those are in omap-rtc, cpufreq etc, but those are not related by the ds-1307. V1: https://patchwork.kernel.org/patch/4759171/ NOTE: Patch 5/5 of the series is meant to indicate the usage, and will be reposted along with other wakeup sources to be enabled once the driver changes are accepted. Felipe Balbi (1): drivers/rtc/rtc-ds1307.c: Convert to threaded IRQ Nishanth Menon (4): drivers/rtc/rtc-ds1307.c: Switch to managed irq allocation drivers/rtc/rtc-ds1307.c: Sort the headers drivers/rtc/rtc-ds1307.c: Support optional wakeup interrupt source for the series, except the patch which I wrote : Acked-by: Felipe Balbi ba...@ti.com With minor comment to patch 4: Reviewed-by: Grygorii Strashko grygorii.stras...@ti.com -- regards, -grygorii -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RESEND] [PATCH v2 1/2] arm: devtree: Set system_rev from DT revision
* Pali Rohár pali.ro...@gmail.com [150506 04:45]: On Wednesday 06 May 2015 13:04:01 Arnd Bergmann wrote: It needs to be done in this code, so system_rev variable is set properly... What I mean is which code accesses this variable that early? ATAG code is doing it at same early stage, so I added it to same early stage... Yes we should do this early like the other atags. Also, it seems strange to have a string property and then use kstrtouint to convert it into a number. I think it should either be specified in a DT binding to be a string and then have the kernel not assume that it is a number, or we should define it to be binary. Arnd Variable system_rev is number and it always was. So chaning type will break more parts. And it is string DT property to be human readable. Some other developers suggested for v2 to change it to string (from number). Both of them would be human readable, you just use something else to read them ;-) If we have a string here, we should just change all uses of system_rev in the kernel accordingly, there are only a few of them: Let's just keep it as a hex as it was. After all it's an existing interface in /proc that user space programs may expect to be in hex format already. Pali, care to repost the whole set again right after -rc1 with with rev property naming and documentation added? Just keep it as hex and let's forget any string conversion. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] arm: devtree: Save atags if are in DT atags field
* Arnd Bergmann a...@arndb.de [150515 13:11]: On Friday 15 May 2015 21:50:06 Pali Rohár wrote: @@ -256,5 +257,10 @@ const struct machine_desc * __init setup_machine_fdt(unsigned int dt_phys) system_rev = 0; } + /* Save atags */ + prop = of_get_flat_dt_prop(dt_root, atags, NULL); + if (prop) + save_atags((void *)prop); + return mdesc; How about checking whether this is actually running on the one board that needs it first? I'd rather not introduce something that may end up being considered an ABI on other machines. It seems having this within CONFIG_ARM_ATAG_DTB_COMPAT should be enough here. Regards, Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/2] arm: boot: store ATAG structure into DT atags field
* Arnd Bergmann a...@arndb.de [150515 13:23]:
On Friday 15 May 2015 22:16:24 Pali Rohár wrote:
On Friday 15 May 2015 22:12:41 Arnd Bergmann wrote:
On Friday 15 May 2015 21:50:07 Pali Rohár wrote:
}
}
+ /* include the terminating ATAG_NONE */
+ atag_size = (char *)atag - (char *)atag_list +
sizeof(struct tag_header); + setprop(fdt, /, atags,
atag_list, atag_size);
+
if (memcount) {
setprop(fdt, /memory, reg, mem_reg_property,
4 * memcount * memsize);
The property should probably have a DT binding, and be named
linux,atags.
It may also help to check if the linux,atags property already
exists and not create it otherwise. That way we can put it into the
n900 dts file and have it updated by the compat code, but not expose
the atags on other platforms unless they opt in.
Using linux,atags sounds good to me. And yes checking it with
getprop before doing setprop makes sense.
Maybe what would help: Is there a way to tell decompressor/kernel to not
touch atag memory and then after kernel/board-code starts it save copy
of atags? I think it is not possible right now, but correct me if I'm
wrong...
I don't think that is possible without an incompatible change to the
boot protocol.
Agreed, let's keep the changes to minimum.
Looks like with the comments posted all the pending four patches
from Pali become quite a minimal set of three patches if we keep
the rev string as hex.
Regrds,
Tony
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Re: [PATCH V2 4/5] drivers/rtc/rtc-ds1307.c: Support optional wakeup interrupt source
On 06/24/2015 10:36 AM, Grygorii Strashko wrote:
On 06/23/2015 07:15 PM, Nishanth Menon wrote:
[...]
+ds1307-wakeirq = of_irq_get(node, 1);
+if (ds1307-wakeirq = 0) {
+if (ds1307-wakeirq == -EPROBE_DEFER) {
+err = ds1307-wakeirq;
+goto exit;
+}
+ds1307-wakeirq = 0;
+goto no_irq;
+}
Might be above code could be done a little bit simpler?
err = of_irq_get(node, 1);
if (err = 0) {
if (err == -EPROBE_DEFER)
goto exit;
goto no_irq;
I had considered it, but problem with this approach is that is err
does not get reset back to 0 and probe will fail as it flows through
the rest of the code.. which is not our intent.
}
ds1307-wakeirq = err;
--
Regards,
Nishanth Menon
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Re: [PATCH 02/13] dmaengine: Introduce dma_request_slave_channel_compat_reason()
On Mon, Jun 22, 2015 at 02:31:00PM +0300, Peter Ujfalusi wrote: On 06/12/2015 03:58 PM, Vinod Koul wrote: Sorry this slipped thru I was away for a week anyways ;) Thinking about it again, I think we should coverge to two APIs and mark the legacy depracuated and look to convert folks and phase that out Currently, w/o this series we have these APIs: /* to be used with DT/ACPI */ dma_request_slave_channel(dev, name) /* NULL on failure */ dma_request_slave_channel_reason(dev, name) /* error code on failure */ /* Legacy mode only - no DT/ACPI lookup */ dma_request_channel(mask, fn, fn_param) /* NULL on failure */ /* to be used with DT/ACPI or legacy boot */ dma_request_slave_channel_compat(mask, fn, fn_param, dev, name) /* NULL on failure */ To request _any_ channel to be used for memcpy one has to use dma_request_channel(mask, NULL, NULL); If I did not missed something. I dont think so :) As we need different types of parameters for DT/ACPI and legacy (non DT/ACPI lookup) and the good API names are already taken, we might need to settle: /* to be used with DT/ACPI */ dma_request_slave_channel(dev, name) /* error code on failure */ - Convert users to check IS_ERR_OR_NULL() instead against NULL - Mark dma_request_slave_channel_reason() deprecated and convert the current users /* to be used with DT/ACPI or legacy boot */ dma_request_slave_channel_compat(mask, fn, fn_param, dev, name) /* error code on failure */ - Convert users to check IS_ERR_OR_NULL() instead against NULL - Do not try legacy mode if either OF or ACPI failed because of real error Should we keep the filter fn and an API for this, I am still not too sure about that part. Anyway users should be on DT/ACPI. if someone wants filter then let them use dma_request_channel() /* Legacy mode only - no DT/ACPI lookup */ dma_request_channel_legacy(mask, fn, fn_param) /* error code on failure */ - convert users of dma_request_channel() - mark dma_request_channel() deprecated Why should we create a new API, how about marking dma_request_channel() as legacy and generic memcpy API and let other users be migrated? /* to be used to get a channel for memcpy for example */ dma_request_any_channel(mask) /* error code on failure */ - Convert current dma_request_channel(mask, NULL, NULL) users I know, any of the other function could be prepared to handle this when parameters are missing, but it is a bit cleaner to have separate API for this. Though it has merits but adds another API. We cna have internal _dma_request_xxx API where parameters are missing and clean but to users single API might be a better idea It would be nice to find another name for the dma_request_slave_channel_compat() so with the new name we could have chance to rearrange the parameters: (dev, name, mask, fn, fn_param) We would end up with the following APIs, all returning with error code on failure: dma_request_slave_channel(dev, name); dma_request_channel_legacy(mask, fn, fn_param); dma_request_slave_channel_compat(mask, fn, fn_param, dev, name); dma_request_any_channel(mask); This is good idea but still we end up with 4 APIs. Why not just converge to two API, one legacy + memcpy + filer fn and one untimate API for slave? Internally we may have 4 APIs for cleaner handling... Thoughts... ?? -- ~Vinod -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V2 4/5] drivers/rtc/rtc-ds1307.c: Support optional wakeup interrupt source
On 06/24/2015 07:07 PM, Nishanth Menon wrote:
On 06/24/2015 10:36 AM, Grygorii Strashko wrote:
On 06/23/2015 07:15 PM, Nishanth Menon wrote:
[...]
+ ds1307-wakeirq = of_irq_get(node, 1);
+ if (ds1307-wakeirq = 0) {
+ if (ds1307-wakeirq == -EPROBE_DEFER) {
+ err = ds1307-wakeirq;
+ goto exit;
+ }
+ ds1307-wakeirq = 0;
+ goto no_irq;
+ }
Might be above code could be done a little bit simpler?
err = of_irq_get(node, 1);
if (err = 0) {
if (err == -EPROBE_DEFER)
goto exit;
goto no_irq;
I had considered it, but problem with this approach is that is err
does not get reset back to 0 and probe will fail as it flows through
the rest of the code.. which is not our intent.
}
ds1307-wakeirq = err;
As I can see from final code (after applying all patches) - It should work.
But I will not insist :)
--
regards,
-grygorii
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Re: [PATCH V2 4/5] drivers/rtc/rtc-ds1307.c: Support optional wakeup interrupt source
On 11:07-20150624, Nishanth Menon wrote:
On 06/24/2015 10:36 AM, Grygorii Strashko wrote:
On 06/23/2015 07:15 PM, Nishanth Menon wrote:
[...]
+ ds1307-wakeirq = of_irq_get(node, 1);
+ if (ds1307-wakeirq = 0) {
+ if (ds1307-wakeirq == -EPROBE_DEFER) {
+ err = ds1307-wakeirq;
+ goto exit;
+ }
+ ds1307-wakeirq = 0;
+ goto no_irq;
+ }
Might be above code could be done a little bit simpler?
err = of_irq_get(node, 1);
if (err = 0) {
if (err == -EPROBE_DEFER)
goto exit;
goto no_irq;
I had considered it, but problem with this approach is that is err
does not get reset back to 0 and probe will fail as it flows through
the rest of the code.. which is not our intent.
I am wrong here - code just returns 0 and ignores err. So, how about
the following patch instead: (Alexandre, please do let me know if the
entire series needs to be reposted):
- improvement as suggested
- Picked up previous acks
- cleanup in probe does not need dev_pm_clear_wake_irq.
--8---
From 12367f8edffc25613f6f920d9bd7b69dfed57ce1 Mon Sep 17 00:00:00 2001
From: Nishanth Menon n...@ti.com
Date: Mon, 22 Jun 2015 14:13:19 -0500
Subject: [PATCH V3] drivers/rtc/rtc-ds1307.c: Support optional wakeup interrupt
source
With the recent pinctrl-single changes, SoCs such as Texas
Instrument's OMAP processors can treat wake-up events from deeper idle
states as interrupts.
Let's add support for the optional second interrupt for wake-up using
the generic wakeirq support added in commit 4990d4fe327b (PM /
Wakeirq: Add automated device wake IRQ handling)
Finally, to pass the wake-up interrupt in the dts file,
interrupts-extended property needs to be passed.
This is similar in approach to commit 2a0b965cfb6e (serial: omap: Add
support for optional wake-up) + ee83bd3b6483 (serial: omap: Switch
wake-up interrupt to generic wakeirq)
Acked-by: Tony Lindgren t...@atomide.com
Acked-by: Felipe Balbi ba...@ti.com
Signed-off-by: Nishanth Menon n...@ti.com
---
drivers/rtc/rtc-ds1307.c | 36 +---
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/drivers/rtc/rtc-ds1307.c b/drivers/rtc/rtc-ds1307.c
index b03880fc32b5..e16989c48a90 100644
--- a/drivers/rtc/rtc-ds1307.c
+++ b/drivers/rtc/rtc-ds1307.c
@@ -15,6 +15,9 @@
#include linux/i2c.h
#include linux/init.h
#include linux/module.h
+#include linux/of_device.h
+#include linux/of_irq.h
+#include linux/pm_wakeirq.h
#include linux/rtc/ds1307.h
#include linux/rtc.h
#include linux/slab.h
@@ -114,6 +117,7 @@ struct ds1307 {
#define HAS_ALARM 1 /* bit 1 == irq claimed */
struct i2c_client *client;
struct rtc_device *rtc;
+ int wakeirq;
s32 (*read_block_data)(const struct i2c_client *client, u8 command,
u8 length, u8 *values);
s32 (*write_block_data)(const struct i2c_client *client, u8 command,
@@ -1156,6 +1160,8 @@ read_rtc:
}
if (want_irq) {
+ struct device_node *node = client-dev.of_node;
+
err = devm_request_threaded_irq(client-dev,
client-irq, NULL, irq_handler,
IRQF_SHARED | IRQF_ONESHOT,
@@ -1163,13 +1169,34 @@ read_rtc:
if (err) {
client-irq = 0;
dev_err(client-dev, unable to request IRQ!\n);
- } else {
+ goto no_irq;
+ }
- set_bit(HAS_ALARM, ds1307-flags);
- dev_dbg(client-dev, got IRQ %d\n, client-irq);
+ set_bit(HAS_ALARM, ds1307-flags);
+ dev_dbg(client-dev, got IRQ %d\n, client-irq);
+
+ /* Currently supported by OF code only! */
+ if (!node)
+ goto no_irq;
+
+ err = of_irq_get(node, 1);
+ if (err = 0) {
+ if (err == -EPROBE_DEFER)
+ goto exit;
+ goto no_irq;
+ }
+ ds1307-wakeirq = err;
+
+ err = dev_pm_set_dedicated_wake_irq(client-dev,
+ ds1307-wakeirq);
+ if (err) {
+ dev_err(client-dev, unable to setup wakeIRQ %d!\n,
+ err);
+ goto exit;
}
}
+no_irq:
if (chip-nvram_size) {
ds1307-nvram = devm_kzalloc(client-dev,
@@ -1213,6 +1240,9 @@ static int ds1307_remove(struct i2c_client *client)
{
struct ds1307 *ds1307 = i2c_get_clientdata(client
[PATCH 1/1] arm: dts: am43xx-clock: Add qspi clock node.
From: Sourav Poddar sourav.pod...@ti.com
Add clock node for qspi controller driver on am437x.
Cc: Keerthy j-keer...@ti.com
Cc: Tero Kristo t-kri...@ti.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/am4372.dtsi| 2 ++
arch/arm/boot/dts/am43xx-clocks.dtsi | 8
2 files changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 649e7b9..8ab7831 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -903,6 +903,8 @@
#address-cells = 1;
#size-cells = 0;
ti,hwmods = qspi;
+ clocks = qspi_fclk;
+ clock-names = fck;
interrupts = 0 138 0x4;
num-cs = 4;
status = disabled;
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi
b/arch/arm/boot/dts/am43xx-clocks.dtsi
index cc88728..1506585 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -763,4 +763,12 @@
ti,bit-shift = 8;
reg = 0x8a68;
};
+
+ qspi_fclk: qspi_fclk {
+ #clock-cells = 0;
+ compatible = ti,fixed-factor-clock;
+ clocks = dpll_per_m2_div4_ck;
+ clock-mult = 1;
+ clock-div = 1;
+ };
};
--
2.4.2.387.gf86f31a
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