[PATCH V4] OMAP3+: SR Layer Cleanup
To set sr ntarget values for all volt_domain,
volt_table is retrieved by doing a look_up of 'vdd_name'
field from omap_hwmod but voltage domain pointer does not
belong to omap_hwmod and is not used anywhere else.
As a part of voltage layer and SR Layer clean up volt
pointer is removed from omap_hwmod and added in dev
attributes of SR.
Tested on OMAP3630 SDP and OMAP4430 SDP Board
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
Acked by: Nishanth Menon n...@ti.com
Cc: Benoit Cousson b-cous...@ti.com
Cc: Paul Walmsley p...@pwsan.com
---
V4:
Fixed comments like checking for NULL pointers
and following conventions in naming the instances
recommended by Todd Poynor and Benoit Cousson.
V3:
Changed the Subject and Rephrased Commit log as reviewed
by Nishanth Menon.
V2:
Rebased on latest 'pm-wip/voltdm_a' branch.
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 17 +
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 19 ---
arch/arm/mach-omap2/smartreflex.h| 10 ++
arch/arm/mach-omap2/sr_device.c | 11 +++
arch/arm/plat-omap/include/plat/omap_hwmod.h |1 -
5 files changed, 46 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 3cd91ac..b1b11de 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -29,6 +29,7 @@
#include omap_hwmod_common_data.h
+#include smartreflex.h
#include prm-regbits-34xx.h
#include cm-regbits-34xx.h
#include wd_timer.h
@@ -2904,6 +2905,10 @@ static struct omap_hwmod_class
omap36xx_smartreflex_hwmod_class = {
};
/* SR1 */
+static struct omap_smartreflex_dev_attr sr1_dev_attr = {
+ .sensor_voltdm_name = mpu_iva,
+};
+
static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
omap3_l4_core__sr1,
};
@@ -2912,7 +2917,6 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
.name = sr1_hwmod,
.class = omap34xx_smartreflex_hwmod_class,
.main_clk = sr1_fck,
- .vdd_name = mpu_iva,
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -2924,6 +2928,7 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
},
.slaves = omap3_sr1_slaves,
.slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
+ .dev_attr = sr1_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
CHIP_IS_OMAP3430ES3_0 |
CHIP_IS_OMAP3430ES3_1),
@@ -2934,7 +2939,6 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
.name = sr1_hwmod,
.class = omap36xx_smartreflex_hwmod_class,
.main_clk = sr1_fck,
- .vdd_name = mpu_iva,
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -2946,10 +2950,15 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
},
.slaves = omap3_sr1_slaves,
.slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
+ .dev_attr = sr1_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
};
/* SR2 */
+static struct omap_smartreflex_dev_attr sr2_dev_attr = {
+ .sensor_voltdm_name= core,
+};
+
static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
omap3_l4_core__sr2,
};
@@ -2958,7 +2967,6 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
.name = sr2_hwmod,
.class = omap34xx_smartreflex_hwmod_class,
.main_clk = sr2_fck,
- .vdd_name = core,
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -2970,6 +2978,7 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
},
.slaves = omap3_sr2_slaves,
.slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
+ .dev_attr = sr2_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
CHIP_IS_OMAP3430ES3_0 |
CHIP_IS_OMAP3430ES3_1),
@@ -2980,7 +2989,6 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
.name = sr2_hwmod,
.class = omap36xx_smartreflex_hwmod_class,
.main_clk = sr2_fck,
- .vdd_name = core,
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -2992,6 +3000,7 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
},
.slaves = omap3_sr2_slaves,
.slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
+ .dev_attr = sr2_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
};
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 3e88dd3..78b6860 100644
--- a/arch
[PATCH V3] OMAP3+: SR Layer Cleanup
To set sr ntarget values for all volt_domain,
volt_table is retrieved by doing a look_up of 'vdd_name'
field from omap_hwmod but voltage domain pointer does not
belong to omap_hwmod and is not used anywhere else.
As a part of voltage layer and SR Layer clean up volt
pointer is removed from omap_hwmod and added in dev
attributes of SR.
Tested on OMAP3630 SDP and OMAP4430 SDP Board
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
Cc: Nishanth Menon n...@ti.com
---
V3:
Changed the Subject and Rephrased Commit log as reviewed
by Nishanth Menon.
V2:
Rebased on latest 'pm-wip/voltdm_a' branch.
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 17 +
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 19 ---
arch/arm/mach-omap2/smartreflex.h| 10 ++
arch/arm/mach-omap2/sr_device.c | 11 +++
arch/arm/plat-omap/include/plat/omap_hwmod.h |1 -
5 files changed, 46 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 3cd91ac..6a704bd 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -29,6 +29,7 @@
#include omap_hwmod_common_data.h
+#include smartreflex.h
#include prm-regbits-34xx.h
#include cm-regbits-34xx.h
#include wd_timer.h
@@ -2904,6 +2905,10 @@ static struct omap_hwmod_class
omap36xx_smartreflex_hwmod_class = {
};
/* SR1 */
+static struct omap_sr_dev_attr sr1_dev_attr = {
+ .voltdm_name = mpu_iva,
+};
+
static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
omap3_l4_core__sr1,
};
@@ -2912,7 +2917,6 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
.name = sr1_hwmod,
.class = omap34xx_smartreflex_hwmod_class,
.main_clk = sr1_fck,
- .vdd_name = mpu_iva,
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -2924,6 +2928,7 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
},
.slaves = omap3_sr1_slaves,
.slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
+ .dev_attr = sr1_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
CHIP_IS_OMAP3430ES3_0 |
CHIP_IS_OMAP3430ES3_1),
@@ -2934,7 +2939,6 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
.name = sr1_hwmod,
.class = omap36xx_smartreflex_hwmod_class,
.main_clk = sr1_fck,
- .vdd_name = mpu_iva,
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -2946,10 +2950,15 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
},
.slaves = omap3_sr1_slaves,
.slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
+ .dev_attr = sr1_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
};
/* SR2 */
+static struct omap_sr_dev_attr sr2_dev_attr = {
+ .voltdm_name= core,
+};
+
static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
omap3_l4_core__sr2,
};
@@ -2958,7 +2967,6 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
.name = sr2_hwmod,
.class = omap34xx_smartreflex_hwmod_class,
.main_clk = sr2_fck,
- .vdd_name = core,
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -2970,6 +2978,7 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
},
.slaves = omap3_sr2_slaves,
.slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
+ .dev_attr = sr2_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
CHIP_IS_OMAP3430ES3_0 |
CHIP_IS_OMAP3430ES3_1),
@@ -2980,7 +2989,6 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
.name = sr2_hwmod,
.class = omap36xx_smartreflex_hwmod_class,
.main_clk = sr2_fck,
- .vdd_name = core,
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -2992,6 +3000,7 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
},
.slaves = omap3_sr2_slaves,
.slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
+ .dev_attr = sr2_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
};
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 3e88dd3..1331b39 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -30,6 +30,7 @@
#include omap_hwmod_common_data.h
+#include smartreflex.h
#include cm1_44xx.h
#include cm2_44xx.h
#include prm44xx.h
@@ -3775,6 +3776,10 @@ static
[PATCH] OMAP: Added recalculation of clock rate in 'clk_set_rate'
From: Gulati, Shweta shweta.gul...@ti.com
Core Clk Tree shows incorrect Clk rates at OPP50, as
in commit e07f469d284ca3d1f5dcf5438c22982be98bc071
calling of 'recalc' in API clk_set_rate is unintentionally
removed, because of which clock's tree rates get goofed
up when DVFS happens. This Patch adds recalc API back.
Tested on OMAP3630 SDP Board.
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
Cc: Rajendra Nayak rna...@ti.com
Cc: Paul Wamsley p...@pwsan.com
---
arch/arm/plat-omap/clock.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index c9122dd..5a0d06b 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -130,8 +130,11 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
spin_lock_irqsave(clockfw_lock, flags);
ret = arch_clock-clk_set_rate(clk, rate);
- if (ret == 0)
+ if (ret == 0) {
+ if (clk-recalc)
+ clk-rate = clk-recalc(clk);
propagate_rate(clk);
+ }
spin_unlock_irqrestore(clockfw_lock, flags);
return ret;
--
1.7.0.4
--
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[PATCH V2] OMAP2+: SR Layer Cleanup.
As a part of Voltage Layer Cleanup Patches,
submitted by Kevin Hilman, Voltage domain
Information is removed from hwmod,
So the patch removes 'vdd_name' info from omap_hwmod
and adds that info into dev_attr as SR code uses vdd_name
to get voltagedomain sructure info.
Tested on OMAP3630 SDP and OMAP4430 SDP Board
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
---
V2:
Rebased on latest 'pm-wip/voltdm_a' branch.
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 17 +
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 19 ---
arch/arm/mach-omap2/smartreflex.h| 10 ++
arch/arm/mach-omap2/sr_device.c | 11 +++
arch/arm/plat-omap/include/plat/omap_hwmod.h |1 -
5 files changed, 46 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 3cd91ac..6a704bd 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -29,6 +29,7 @@
#include omap_hwmod_common_data.h
+#include smartreflex.h
#include prm-regbits-34xx.h
#include cm-regbits-34xx.h
#include wd_timer.h
@@ -2904,6 +2905,10 @@ static struct omap_hwmod_class
omap36xx_smartreflex_hwmod_class = {
};
/* SR1 */
+static struct omap_sr_dev_attr sr1_dev_attr = {
+ .voltdm_name = mpu_iva,
+};
+
static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
omap3_l4_core__sr1,
};
@@ -2912,7 +2917,6 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
.name = sr1_hwmod,
.class = omap34xx_smartreflex_hwmod_class,
.main_clk = sr1_fck,
- .vdd_name = mpu_iva,
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -2924,6 +2928,7 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
},
.slaves = omap3_sr1_slaves,
.slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
+ .dev_attr = sr1_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
CHIP_IS_OMAP3430ES3_0 |
CHIP_IS_OMAP3430ES3_1),
@@ -2934,7 +2939,6 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
.name = sr1_hwmod,
.class = omap36xx_smartreflex_hwmod_class,
.main_clk = sr1_fck,
- .vdd_name = mpu_iva,
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -2946,10 +2950,15 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
},
.slaves = omap3_sr1_slaves,
.slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
+ .dev_attr = sr1_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
};
/* SR2 */
+static struct omap_sr_dev_attr sr2_dev_attr = {
+ .voltdm_name= core,
+};
+
static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
omap3_l4_core__sr2,
};
@@ -2958,7 +2967,6 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
.name = sr2_hwmod,
.class = omap34xx_smartreflex_hwmod_class,
.main_clk = sr2_fck,
- .vdd_name = core,
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -2970,6 +2978,7 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
},
.slaves = omap3_sr2_slaves,
.slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
+ .dev_attr = sr2_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
CHIP_IS_OMAP3430ES3_0 |
CHIP_IS_OMAP3430ES3_1),
@@ -2980,7 +2989,6 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
.name = sr2_hwmod,
.class = omap36xx_smartreflex_hwmod_class,
.main_clk = sr2_fck,
- .vdd_name = core,
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -2992,6 +3000,7 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
},
.slaves = omap3_sr2_slaves,
.slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
+ .dev_attr = sr2_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
};
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 3e88dd3..1331b39 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -30,6 +30,7 @@
#include omap_hwmod_common_data.h
+#include smartreflex.h
#include cm1_44xx.h
#include cm2_44xx.h
#include prm44xx.h
@@ -3775,6 +3776,10 @@ static struct omap_hwmod_class
omap44xx_smartreflex_hwmod_class = {
};
/* smartreflex_core */
+static struct omap_sr_dev_attr sr_core_dev_attr = {
+ .voltdm_name = core,
+};
+
static
[PATCH] OMAP2+: SR Layer Cleanup.
As a part of Voltage Layer Cleanup Patches,
submitted by Kevin Hilman, Voltage domain
Information is removed from hwmod,
So the patch removes 'vdd_name' info from omap_hwmod
and adds that info into dev_attr as SR code uses vdd_name
to get voltagedomain sructure info.
Tested on OMAP3630 SDP and OMAP4430 SDP Board
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
---
It apllies over Voltage Layer Cleanup Patch by
Kevin Hilman:
https://patchwork.kernel.org/patch/657421/
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 17 +
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 19 ---
arch/arm/mach-omap2/smartreflex.h| 10 ++
arch/arm/mach-omap2/sr_device.c | 11 +++
arch/arm/plat-omap/include/plat/omap_hwmod.h |1 -
5 files changed, 46 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index c819c30..e88f819 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -29,6 +29,7 @@
#include omap_hwmod_common_data.h
+#include smartreflex.h
#include prm-regbits-34xx.h
#include cm-regbits-34xx.h
#include wd_timer.h
@@ -2901,6 +2902,10 @@ static struct omap_hwmod_class
omap36xx_smartreflex_hwmod_class = {
};
/* SR1 */
+static struct omap_sr_dev_attr sr1_dev_attr = {
+ .voltdm_name = mpu,
+};
+
static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
omap3_l4_core__sr1,
};
@@ -2909,7 +2914,6 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
.name = sr1_hwmod,
.class = omap34xx_smartreflex_hwmod_class,
.main_clk = sr1_fck,
- .vdd_name = mpu,
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -2921,6 +2925,7 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
},
.slaves = omap3_sr1_slaves,
.slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
+ .dev_attr = sr1_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
CHIP_IS_OMAP3430ES3_0 |
CHIP_IS_OMAP3430ES3_1),
@@ -2931,7 +2936,6 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
.name = sr1_hwmod,
.class = omap36xx_smartreflex_hwmod_class,
.main_clk = sr1_fck,
- .vdd_name = mpu,
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -2943,10 +2947,15 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
},
.slaves = omap3_sr1_slaves,
.slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
+ .dev_attr = sr1_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
};
/* SR2 */
+static struct omap_sr_dev_attr sr2_dev_attr = {
+ .voltdm_name= core,
+};
+
static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
omap3_l4_core__sr2,
};
@@ -2955,7 +2964,6 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
.name = sr2_hwmod,
.class = omap34xx_smartreflex_hwmod_class,
.main_clk = sr2_fck,
- .vdd_name = core,
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -2967,6 +2975,7 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
},
.slaves = omap3_sr2_slaves,
.slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
+ .dev_attr = sr2_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
CHIP_IS_OMAP3430ES3_0 |
CHIP_IS_OMAP3430ES3_1),
@@ -2977,7 +2986,6 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
.name = sr2_hwmod,
.class = omap36xx_smartreflex_hwmod_class,
.main_clk = sr2_fck,
- .vdd_name = core,
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -2989,6 +2997,7 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
},
.slaves = omap3_sr2_slaves,
.slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
+ .dev_attr = sr2_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
};
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 3e88dd3..1331b39 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -30,6 +30,7 @@
#include omap_hwmod_common_data.h
+#include smartreflex.h
#include cm1_44xx.h
#include cm2_44xx.h
#include prm44xx.h
@@ -3775,6 +3776,10 @@ static struct omap_hwmod_class
omap44xx_smartreflex_hwmod_class = {
};
/* smartreflex_core */
+static struct omap_sr_dev_attr sr_core_dev_attr
[PATCH V2] OMAP4: Intialize IVA Device in addition to DSP device.
OMAP4 has two different Devices IVA and DSP. DSP is bound
with IVA for DVFS. The registration of IVA dev in API
'omap2_init_processor_devices' was missing. Init dev for
'iva_dev' is added.
This also fixes the following error seen during boot as
omap2_set_init_voltage can now find the iva device
omap2_set_init_voltage: Invalid parameters!
omap2_set_init_voltage: Unable to put vdd_iva to its init voltage
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
---
Tested on OMAP4430 SDP Board.
Baseline:
http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git
Branch :pm-core
V2:
Rephrased the Commit log.
arch/arm/mach-omap2/pm.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 30af335..49486f5 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -89,6 +89,7 @@ static void omap2_init_processor_devices(void)
if (cpu_is_omap44xx()) {
_init_omap_device(l3_main_1, l3_dev);
_init_omap_device(dsp, dsp_dev);
+ _init_omap_device(iva, iva_dev);
} else {
_init_omap_device(l3_main, l3_dev);
}
--
1.7.0.4
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[PATCH V3 2/3] OMAP4: Update Voltage Rail Values for MPU, IVA and CORE
Update MPU, IVA and CORE voltage Rail values obtained from
OMAP4430 Data Manual Operating Condition Addendum_v0.4.
Tested on OMAP4430 SDP Board.
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
---
V3:
Update CORE Voltages as well
in sync with V0.4 of OMAP4 Data Manual.
V2:
Fixed Comments from Nishanth Menon.
arch/arm/mach-omap2/opp4xxx_data.c | 18 +-
1 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c
b/arch/arm/mach-omap2/opp4xxx_data.c
index ed0efdb..aa624d1 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -30,10 +30,10 @@
* voltage dependent data for each VDD.
*/
-#define OMAP4430_VDD_MPU_OPP50_UV 93
-#define OMAP4430_VDD_MPU_OPP100_UV 110
-#define OMAP4430_VDD_MPU_OPPTURBO_UV 126
-#define OMAP4430_VDD_MPU_OPPNITRO_UV 135
+#define OMAP4430_VDD_MPU_OPP50_UV 1025000
+#define OMAP4430_VDD_MPU_OPP100_UV 120
+#define OMAP4430_VDD_MPU_OPPTURBO_UV 1313000
+#define OMAP4430_VDD_MPU_OPPNITRO_UV 1375000
struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = {
VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV,
OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c),
@@ -43,9 +43,9 @@ struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = {
VOLT_DATA_DEFINE(0, 0, 0, 0),
};
-#define OMAP4430_VDD_IVA_OPP50_UV 93
-#define OMAP4430_VDD_IVA_OPP100_UV 110
-#define OMAP4430_VDD_IVA_OPPTURBO_UV 126
+#define OMAP4430_VDD_IVA_OPP50_UV 1013000
+#define OMAP4430_VDD_IVA_OPP100_UV 1188000
+#define OMAP4430_VDD_IVA_OPPTURBO_UV 130
struct omap_volt_data omap44xx_vdd_iva_volt_data[] = {
VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV,
OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c),
@@ -54,8 +54,8 @@ struct omap_volt_data omap44xx_vdd_iva_volt_data[] = {
VOLT_DATA_DEFINE(0, 0, 0, 0),
};
-#define OMAP4430_VDD_CORE_OPP50_UV 93
-#define OMAP4430_VDD_CORE_OPP100_UV110
+#define OMAP4430_VDD_CORE_OPP50_UV 1025000
+#define OMAP4430_VDD_CORE_OPP100_UV120
struct omap_volt_data omap44xx_vdd_core_volt_data[] = {
VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP50_UV,
OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c),
--
1.7.0.4
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[PATCH] OMAP4: Intialize IVA Device in addition to DSP device.
OMAP4 has two different Devices IVA and DSP. DSP is bound
with MPU for DVFS and IVA has its own well defined OPPs.
This Patch adds IVA init to 'omap2_init_processor_devices'
and make sure that API 'omap2_set_init_voltage' is called
for apt dev pointer.
It fixes Error logs:
omap2_set_init_voltage: Invalid parameters!
omap2_set_init_voltage: Unable to put vdd_iva to its init voltage
Tested on OMAP4430 SDP Board.
Baseline:
http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git
Branch :pm-core
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
---
arch/arm/mach-omap2/pm.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 30af335..49486f5 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -89,6 +89,7 @@ static void omap2_init_processor_devices(void)
if (cpu_is_omap44xx()) {
_init_omap_device(l3_main_1, l3_dev);
_init_omap_device(dsp, dsp_dev);
+ _init_omap_device(iva, iva_dev);
} else {
_init_omap_device(l3_main, l3_dev);
}
--
1.7.0.4
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[PATCH V2 0/3]: OMAP4: Update OPP Table and Voltage Rail Values
The Series Updates OPP Table for MPU, add OPP enteries for IVA and update Voltage Rail values for MPU/IVA. It is based on the Patch which replaces Voltage values with Macros, Submitted by Nishanth Menon https://patchwork.kernel.org/patch/607541/ Branch: pm-core Tested on OMAP4430 SDP. V2: Rebased on pm-core and incorporated comments from Nishanth Menon. Shweta Gulati (3): OMAP4: Enable 800 MHz and 1 GHz OPP for OMAP4. OMAP4: Update Voltage Rail Values for MPU/IVA OMAP4: Add IVA OPP enteries. arch/arm/mach-omap2/opp4xxx_data.c | 26 -- 1 files changed, 16 insertions(+), 10 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V2 1/3] OMAP4: Enable 800 MHz and 1 GHz MPU-OPP
Almost all OMAP4 boards support OPP 800 MHz and OPP 1 GHz.
Enable them in OPP Table. For small minority of boards which use
OMAP4430-800 MHz device OPP 1GHz is not supported,
OPP 1GHz should be disabled from board file.
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
Cc: linux-arm-ker...@lists.infradead.org
---
arch/arm/mach-omap2/opp4xxx_data.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c
b/arch/arm/mach-omap2/opp4xxx_data.c
index 57f1498..93b9744 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -71,9 +71,9 @@ static struct omap_opp_def __initdata omap44xx_opp_def_list[]
= {
/* MPU OPP2 - OPP100 */
OPP_INITIALIZER(mpu, true, 6, OMAP4430_VDD_MPU_OPP100_UV),
/* MPU OPP3 - OPP-Turbo */
- OPP_INITIALIZER(mpu, false, 8, OMAP4430_VDD_MPU_OPPTURBO_UV),
+ OPP_INITIALIZER(mpu, true, 8, OMAP4430_VDD_MPU_OPPTURBO_UV),
/* MPU OPP4 - OPP-SB */
- OPP_INITIALIZER(mpu, false, 100800, OMAP4430_VDD_MPU_OPPNITRO_UV),
+ OPP_INITIALIZER(mpu, true, 100800, OMAP4430_VDD_MPU_OPPNITRO_UV),
/* L3 OPP1 - OPP50 */
OPP_INITIALIZER(l3_main_1, true, 1,
OMAP4430_VDD_CORE_OPP50_UV),
/* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
--
1.7.0.4
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[PATCH V2 2/3] OMAP4: Update Voltage Rail Values for MPU/IVA
Update MPU/IVA voltage Rail values obtained from
OMAP4430 Data Manual Operating Condition Addendum_v0.3.
Tested on OMAP4430 SDP Board.
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
Cc: linux-arm-ker...@lists.infradead.org
---
arch/arm/mach-omap2/opp4xxx_data.c | 14 +++---
1 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c
b/arch/arm/mach-omap2/opp4xxx_data.c
index 93b9744..36a4517 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -31,10 +31,10 @@
* voltage dependent data for each VDD.
*/
-#define OMAP4430_VDD_MPU_OPP50_UV 93
-#define OMAP4430_VDD_MPU_OPP100_UV 110
-#define OMAP4430_VDD_MPU_OPPTURBO_UV 126
-#define OMAP4430_VDD_MPU_OPPNITRO_UV 135
+#define OMAP4430_VDD_MPU_OPP50_UV 1025000
+#define OMAP4430_VDD_MPU_OPP100_UV 120
+#define OMAP4430_VDD_MPU_OPPTURBO_UV 1313000
+#define OMAP4430_VDD_MPU_OPPNITRO_UV 1375000
struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = {
VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV,
OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c),
@@ -44,9 +44,9 @@ struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = {
VOLT_DATA_DEFINE(0, 0, 0, 0),
};
-#define OMAP4430_VDD_IVA_OPP50_UV 93
-#define OMAP4430_VDD_IVA_OPP100_UV 110
-#define OMAP4430_VDD_IVA_OPPTURBO_UV 126
+#define OMAP4430_VDD_IVA_OPP50_UV 1013000
+#define OMAP4430_VDD_IVA_OPP100_UV 1188000
+#define OMAP4430_VDD_IVA_OPPTURBO_UV 130
struct omap_volt_data omap44xx_vdd_iva_volt_data[] = {
VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV,
OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c),
--
1.7.0.4
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[PATCH V2 3/3] OMAP4: Add IVA OPP enteries.
This Patch adds OPP enteries for IVA in OMAP4 OPP Table
Tested on OMAP4430 SDP Board.
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
Cc: linux-arm-ker...@lists.infradead.org
---
arch/arm/mach-omap2/opp4xxx_data.c |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c
b/arch/arm/mach-omap2/opp4xxx_data.c
index 36a4517..ba5eddd 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -78,7 +78,13 @@ static struct omap_opp_def __initdata
omap44xx_opp_def_list[] = {
OPP_INITIALIZER(l3_main_1, true, 1,
OMAP4430_VDD_CORE_OPP50_UV),
/* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
OPP_INITIALIZER(l3_main_1, true, 2,
OMAP4430_VDD_CORE_OPP100_UV),
- /* TODO: add IVA, DSP, aess, fdif, gpu */
+ /* IVA OPP1 - OPP50 */
+ OPP_INITIALIZER(iva, true, 13300, OMAP4430_VDD_IVA_OPP50_UV),
+ /* IVA OPP2 - OPP100 */
+ OPP_INITIALIZER(iva, true, 26610, OMAP4430_VDD_IVA_OPP100_UV),
+ /* IVA OPP3 - OPP-Turbo */
+ OPP_INITIALIZER(iva, false, 33200, OMAP4430_VDD_IVA_OPPTURBO_UV),
+ /* TODO: add DSP, aess, fdif, gpu */
};
/**
--
1.7.0.4
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[PATCH] OMAP4: Add IVA OPP enteries with Updated Voltage Rail Values.
This Patch adds OPP enteries for IVA in OMAP4 OPP Table
and updates IVA voltage Rail values obtained from latest
OMAP4430 Data Manual Operating Condition Addendum.
Tested on OMAP4430 SDP Board.
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
---
arch/arm/mach-omap2/opp4xxx_data.c|8 +++-
arch/arm/plat-omap/include/plat/voltage.h |6 +++---
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c
b/arch/arm/mach-omap2/opp4xxx_data.c
index 48d79e5..3e0fbdc 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -38,7 +38,13 @@ static struct omap_opp_def __initdata
omap44xx_opp_def_list[] = {
OPP_INITIALIZER(l3_main_1, true, 1,
OMAP4430_VDD_CORE_OPP50_UV),
/* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
OPP_INITIALIZER(l3_main_1, true, 2,
OMAP4430_VDD_CORE_OPP100_UV),
- /* TODO: add IVA, DSP, aess, fdif, gpu */
+ /* IVA OPP1 - OPP50 */
+ OPP_INITIALIZER(iva, true, 13300, OMAP4430_VDD_IVA_OPP50_UV),
+ /* IVA OPP2 - OPP100 */
+ OPP_INITIALIZER(iva, true, 26610, OMAP4430_VDD_IVA_OPP100_UV),
+ /* IVA OPP3 - OPP-Turbo */
+ OPP_INITIALIZER(iva, false, 33200, OMAP4430_VDD_IVA_OPPTURBO_UV),
+ /* TODO: add DSP, aess, fdif, gpu */
};
/**
diff --git a/arch/arm/plat-omap/include/plat/voltage.h
b/arch/arm/plat-omap/include/plat/voltage.h
index 4d9bab1..27555ce 100644
--- a/arch/arm/plat-omap/include/plat/voltage.h
+++ b/arch/arm/plat-omap/include/plat/voltage.h
@@ -51,9 +51,9 @@
#define OMAP4430_VDD_MPU_OPPTURBO_UV 1313000
#define OMAP4430_VDD_MPU_OPPNITRO_UV 1375000
-#define OMAP4430_VDD_IVA_OPP50_UV 93
-#define OMAP4430_VDD_IVA_OPP100_UV 110
-#define OMAP4430_VDD_IVA_OPPTURBO_UV 126
+#define OMAP4430_VDD_IVA_OPP50_UV 1013000
+#define OMAP4430_VDD_IVA_OPP100_UV 1188000
+#define OMAP4430_VDD_IVA_OPPTURBO_UV 130
#define OMAP4430_VDD_CORE_OPP50_UV 93
#define OMAP4430_VDD_CORE_OPP100_UV110
--
1.7.0.4
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[PATCH V4] OMAP3: PM: Set/clear T2 bit for Smartreflex on TWL
From: Thara Gopinath th...@ti.com
Voltage control on TWL can be done using VMODE/I2C1/I2C_SR.
Since almost all platforms use I2C_SR on omap3, omap3_twl_init by
default expects that OMAP's I2C_SR is plugged in to TWL's I2C
and calls omap3_twl_set_sr_bit. On platforms where I2C_SR is not connected,
the board files are expected to call omap3_twl_set_sr_bit(false) to
ensure that I2C_SR path is not set for voltage control and prevent
the default behavior of omap3_twl_init.
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Thara Gopinath th...@ti.com
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
Cc: linux-arm-ker...@lists.infradead.org
---
This patch is based on LO PM Branch and Smartreflex has been
tested on OMAP3430 SDP, OMAP3630 SDP and boot tested on
OMAP2430 SDP.
arch/arm/mach-omap2/omap_twl.c | 60
arch/arm/mach-omap2/pm.h |1 +
2 files changed, 61 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
index 00e1d2b..b341c36 100644
--- a/arch/arm/mach-omap2/omap_twl.c
+++ b/arch/arm/mach-omap2/omap_twl.c
@@ -59,8 +59,15 @@
static bool is_offset_valid;
static u8 smps_offset;
+/*
+ * Flag to ensure Smartreflex bit in TWL
+ * being cleared in board file is not overwritten.
+ */
+static bool __initdata twl_sr_enable_autoinit;
+#define TWL4030_DCDC_GLOBAL_CFG0x06
#define REG_SMPS_OFFSET 0xE0
+#define SMARTREFLEX_ENABLE BIT(3)
static unsigned long twl4030_vsel_to_uv(const u8 vsel)
{
@@ -269,6 +276,18 @@ int __init omap3_twl_init(void)
omap3_core_volt_info.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
}
+ /*
+* The smartreflex bit on twl4030 specifies if the setting of voltage
+* is done over the I2C_SR path. Since this setting is independent of
+* the actual usage of smartreflex AVS module, we enable TWL SR bit
+* by default irrespective of whether smartreflex AVS module is enabled
+* on the OMAP side or not. This is because without this bit enabled,
+* the voltage scaling through vp forceupdate/bypass mechanism of
+* voltage scaling will not function on TWL over I2C_SR.
+*/
+ if (!twl_sr_enable_autoinit)
+ omap3_twl_set_sr_bit(true);
+
voltdm = omap_voltage_domain_lookup(mpu);
omap_voltage_register_pmic(voltdm, omap3_mpu_volt_info);
@@ -277,3 +296,44 @@ int __init omap3_twl_init(void)
return 0;
}
+
+/**
+ * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL
+ * @enable: enable SR mode in twl or not
+ *
+ * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure
+ * voltage scaling through OMAP SR works. Else, the smartreflex bit
+ * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but
+ * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct
+ * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages,
+ * in those scenarios this bit is to be cleared (enable = false).
+ *
+ * Returns 0 on sucess, error is returned if I2C read/write fails.
+ */
+int __init omap3_twl_set_sr_bit(bool enable)
+{
+ u8 temp;
+ int ret;
+ if (twl_sr_enable_autoinit)
+ pr_warning(%s: unexpected multiple calls\n, __func__);
+
+ ret = twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, temp,
+ TWL4030_DCDC_GLOBAL_CFG);
+ if (ret)
+ goto err;
+
+ if (enable)
+ temp |= SMARTREFLEX_ENABLE;
+ else
+ temp = ~SMARTREFLEX_ENABLE;
+
+ ret = twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, temp,
+ TWL4030_DCDC_GLOBAL_CFG);
+ if (!ret) {
+ twl_sr_enable_autoinit = true;
+ return 0;
+ }
+err:
+ pr_err(%s: Error access to TWL4030 (%d)\n, __func__, ret);
+ return ret;
+}
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 39580e6..797bfd1 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -127,6 +127,7 @@ static inline void omap_enable_smartreflex_on_init(void) {}
#ifdef CONFIG_TWL4030_CORE
extern int omap3_twl_init(void);
extern int omap4_twl_init(void);
+extern int omap3_twl_set_sr_bit(bool enable);
#else
static inline int omap3_twl_init(void)
{
--
1.7.0.4
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[PATCH] OMAP: Fix Memory Leaks in Smartreflex driver
This Patch frees all the dynamically allocated memory
which couldn't have been released in some error hitting cases.
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
Cc: linux-arm-ker...@lists.infradead.org
---
arch/arm/mach-omap2/smartreflex.c | 18 --
1 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex.c
b/arch/arm/mach-omap2/smartreflex.c
index a1f532e..5af8829 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -284,6 +284,7 @@ error:
dev_err(sr_info-pdev-dev, %s: ERROR in registering
interrupt handler. Smartreflex will
not function as desired\n, __func__);
+ kfree(name);
kfree(sr_info);
return ret;
}
@@ -881,7 +882,7 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
ret = sr_late_init(sr_info);
if (ret) {
pr_warning(%s: Error in SR late init\n, __func__);
- return ret;
+ goto err_release_region;
}
}
@@ -892,14 +893,17 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
* not try to create rest of the debugfs entries.
*/
vdd_dbg_dir = omap_voltage_get_dbgdir(sr_info-voltdm);
- if (!vdd_dbg_dir)
- return -EINVAL;
+ if (!vdd_dbg_dir) {
+ ret = -EINVAL;
+ goto err_release_region;
+ }
dbg_dir = debugfs_create_dir(smartreflex, vdd_dbg_dir);
if (IS_ERR(dbg_dir)) {
dev_err(pdev-dev, %s: Unable to create debugfs directory\n,
__func__);
- return PTR_ERR(dbg_dir);
+ ret = PTR_ERR(dbg_dir);
+ goto err_release_region;
}
(void) debugfs_create_file(autocomp, S_IRUGO | S_IWUSR, dbg_dir,
@@ -915,7 +919,8 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
if (IS_ERR(nvalue_dir)) {
dev_err(pdev-dev, %s: Unable to create debugfs directory
for n-values\n, __func__);
- return PTR_ERR(nvalue_dir);
+ ret = PTR_ERR(nvalue_dir);
+ goto err_release_region;
}
omap_voltage_get_volttable(sr_info-voltdm, volt_data);
@@ -924,7 +929,8 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
corresponding vdd vdd_%s. Cannot create debugfs
entries for n-values\n,
__func__, sr_info-voltdm-name);
- return -ENODATA;
+ ret = -ENODATA;
+ goto err_release_region;
}
for (i = 0; i sr_info-nvalue_count; i++) {
--
1.7.0.4
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[PATCH 0/3]: Update OPP Table and Voltage Rail Values
The series mainly does below: OMAP4 only - Update MPU VOltage rail values for all OPPs - Enable OPP-Nitro and OPP-Turbo for all boards OMAP2PLUS -Replace hardcoded Voltage values in OPP Table with Voltage Macros. Baseline: git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git Branch: pm Tested on OMAP4430 SDP, OMAP3630 SDP and OMAP3430 SDP. Shweta Gulati (2): OMAP4: Revise MPU Voltage rail values. OMAP4: Enable Turbo and Nitro OPP for OMAP4 Vishwanath BS (1): OMAP2+: Replace Voltage values with Macros. arch/arm/mach-omap2/opp3xxx_data.c| 47 +++-- arch/arm/mach-omap2/opp4xxx_data.c| 13 arch/arm/plat-omap/include/plat/voltage.h |8 ++-- 3 files changed, 35 insertions(+), 33 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/3] OMAP4: Revise MPU Voltage rail values.
MPU voltage rail values are updated according to latest OMAP4430 Data Manual Operating Condition Addendum. Signed-off-by: Shweta Gulati shweta.gul...@ti.com --- arch/arm/plat-omap/include/plat/voltage.h |8 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h index 5bd204e..4d9bab1 100644 --- a/arch/arm/plat-omap/include/plat/voltage.h +++ b/arch/arm/plat-omap/include/plat/voltage.h @@ -46,10 +46,10 @@ #define OMAP3630_VDD_CORE_OPP50_UV 100 #define OMAP3630_VDD_CORE_OPP100_UV120 -#define OMAP4430_VDD_MPU_OPP50_UV 93 -#define OMAP4430_VDD_MPU_OPP100_UV 110 -#define OMAP4430_VDD_MPU_OPPTURBO_UV 126 -#define OMAP4430_VDD_MPU_OPPNITRO_UV 135 +#define OMAP4430_VDD_MPU_OPP50_UV 1025000 +#define OMAP4430_VDD_MPU_OPP100_UV 120 +#define OMAP4430_VDD_MPU_OPPTURBO_UV 1313000 +#define OMAP4430_VDD_MPU_OPPNITRO_UV 1375000 #define OMAP4430_VDD_IVA_OPP50_UV 93 #define OMAP4430_VDD_IVA_OPP100_UV 110 -- 1.7.0.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/3] OMAP2+: Replace Voltage values with Macros.
From: Vishwanath BS vishwanath...@ti.com
Currently voltage values on opp tables are hardcoded. As these voltage values
are anyway defined in voltage.h as macros, opp table can reuse these values.
This will avoid opp table and voltage layer having conflicting values.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
---
arch/arm/mach-omap2/opp3xxx_data.c | 47 ++-
arch/arm/mach-omap2/opp4xxx_data.c | 13 +
2 files changed, 31 insertions(+), 29 deletions(-)
diff --git a/arch/arm/mach-omap2/opp3xxx_data.c
b/arch/arm/mach-omap2/opp3xxx_data.c
index fd3a1af..e3ea9ba 100644
--- a/arch/arm/mach-omap2/opp3xxx_data.c
+++ b/arch/arm/mach-omap2/opp3xxx_data.c
@@ -19,21 +19,22 @@
#include linux/module.h
#include plat/cpu.h
+#include plat/voltage.h
#include omap_opp_data.h
#include pm.h
static struct omap_opp_def __initdata omap34xx_opp_def_list[] = {
/* MPU OPP1 */
- OPP_INITIALIZER(mpu, true, 12500, 975000),
+ OPP_INITIALIZER(mpu, true, 12500, OMAP3430_VDD_MPU_OPP1_UV),
/* MPU OPP2 */
- OPP_INITIALIZER(mpu, true, 25000, 1075000),
+ OPP_INITIALIZER(mpu, true, 25000, OMAP3430_VDD_MPU_OPP2_UV),
/* MPU OPP3 */
- OPP_INITIALIZER(mpu, true, 5, 120),
+ OPP_INITIALIZER(mpu, true, 5, OMAP3430_VDD_MPU_OPP3_UV),
/* MPU OPP4 */
- OPP_INITIALIZER(mpu, true, 55000, 127),
+ OPP_INITIALIZER(mpu, true, 55000, OMAP3430_VDD_MPU_OPP4_UV),
/* MPU OPP5 */
- OPP_INITIALIZER(mpu, true, 6, 135),
+ OPP_INITIALIZER(mpu, true, 6, OMAP3430_VDD_MPU_OPP5_UV),
/*
* L3 OPP1 - 41.5 MHz is disabled because: The voltage for that OPP is
@@ -43,47 +44,47 @@ static struct omap_opp_def __initdata
omap34xx_opp_def_list[] = {
* impact that frequency will do to the MPU and the whole system in
* general.
*/
- OPP_INITIALIZER(l3_main, false, 4150, 975000),
+ OPP_INITIALIZER(l3_main, false, 4150, OMAP3430_VDD_CORE_OPP1_UV),
/* L3 OPP2 */
- OPP_INITIALIZER(l3_main, true, 8300, 105),
+ OPP_INITIALIZER(l3_main, true, 8300, OMAP3430_VDD_CORE_OPP2_UV),
/* L3 OPP3 */
- OPP_INITIALIZER(l3_main, true, 16600, 115),
+ OPP_INITIALIZER(l3_main, true, 16600, OMAP3430_VDD_CORE_OPP3_UV),
/* DSP OPP1 */
- OPP_INITIALIZER(iva, true, 9000, 975000),
+ OPP_INITIALIZER(iva, true, 9000, OMAP3430_VDD_MPU_OPP1_UV),
/* DSP OPP2 */
- OPP_INITIALIZER(iva, true, 18000, 1075000),
+ OPP_INITIALIZER(iva, true, 18000, OMAP3430_VDD_MPU_OPP2_UV),
/* DSP OPP3 */
- OPP_INITIALIZER(iva, true, 36000, 120),
+ OPP_INITIALIZER(iva, true, 36000, OMAP3430_VDD_MPU_OPP3_UV),
/* DSP OPP4 */
- OPP_INITIALIZER(iva, true, 4, 127),
+ OPP_INITIALIZER(iva, true, 4, OMAP3430_VDD_MPU_OPP4_UV),
/* DSP OPP5 */
- OPP_INITIALIZER(iva, true, 43000, 135),
+ OPP_INITIALIZER(iva, true, 43000, OMAP3430_VDD_MPU_OPP5_UV),
};
static struct omap_opp_def __initdata omap36xx_opp_def_list[] = {
/* MPU OPP1 - OPP50 */
- OPP_INITIALIZER(mpu, true, 3, 1012500),
+ OPP_INITIALIZER(mpu, true, 3, OMAP3630_VDD_MPU_OPP50_UV),
/* MPU OPP2 - OPP100 */
- OPP_INITIALIZER(mpu, true, 6, 120),
+ OPP_INITIALIZER(mpu, true, 6, OMAP3630_VDD_MPU_OPP100_UV),
/* MPU OPP3 - OPP-Turbo */
- OPP_INITIALIZER(mpu, false, 8, 1325000),
+ OPP_INITIALIZER(mpu, false, 8, OMAP3630_VDD_MPU_OPP120_UV),
/* MPU OPP4 - OPP-SB */
- OPP_INITIALIZER(mpu, false, 10, 1375000),
+ OPP_INITIALIZER(mpu, false, 10, OMAP3630_VDD_MPU_OPP1G_UV),
/* L3 OPP1 - OPP50 */
- OPP_INITIALIZER(l3_main, true, 1, 100),
+ OPP_INITIALIZER(l3_main, true, 1, OMAP3630_VDD_CORE_OPP50_UV),
/* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
- OPP_INITIALIZER(l3_main, true, 2, 120),
+ OPP_INITIALIZER(l3_main, true, 2,
OMAP3630_VDD_CORE_OPP100_UV),
/* DSP OPP1 - OPP50 */
- OPP_INITIALIZER(iva, true, 26000, 1012500),
+ OPP_INITIALIZER(iva, true, 26000, OMAP3630_VDD_MPU_OPP50_UV),
/* DSP OPP2 - OPP100 */
- OPP_INITIALIZER(iva, true, 52000, 120),
+ OPP_INITIALIZER(iva, true, 52000, OMAP3630_VDD_MPU_OPP100_UV),
/* DSP OPP3 - OPP-Turbo */
- OPP_INITIALIZER(iva, false, 66000, 1325000),
+ OPP_INITIALIZER(iva, false, 66000, OMAP3630_VDD_MPU_OPP120_UV),
/* DSP OPP4 - OPP-SB */
- OPP_INITIALIZER(iva, false, 8, 1375000),
+ OPP_INITIALIZER(iva, false, 8, OMAP3630_VDD_MPU_OPP1G_UV),
};
/**
diff
[PATCH 3/3] OMAP4: Enable Turbo and Nitro OPP for OMAP4
All OMAP4 boards support OPP-Turbo (800M) and OPP-Nitro (1G).
Enable them by default in OPPTable. For 800Mhz devices where
OPP-Nitro is not supported, OPP-Nitro should be disabled
from board file.
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
---
arch/arm/mach-omap2/opp4xxx_data.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c
b/arch/arm/mach-omap2/opp4xxx_data.c
index 705fe9a..48d79e5 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -31,9 +31,9 @@ static struct omap_opp_def __initdata omap44xx_opp_def_list[]
= {
/* MPU OPP2 - OPP100 */
OPP_INITIALIZER(mpu, true, 6, OMAP4430_VDD_MPU_OPP100_UV),
/* MPU OPP3 - OPP-Turbo */
- OPP_INITIALIZER(mpu, false, 8, OMAP4430_VDD_MPU_OPPTURBO_UV),
+ OPP_INITIALIZER(mpu, true, 8, OMAP4430_VDD_MPU_OPPTURBO_UV),
/* MPU OPP4 - OPP-SB */
- OPP_INITIALIZER(mpu, false, 100800, OMAP4430_VDD_MPU_OPPNITRO_UV),
+ OPP_INITIALIZER(mpu, true, 100800, OMAP4430_VDD_MPU_OPPNITRO_UV),
/* L3 OPP1 - OPP50 */
OPP_INITIALIZER(l3_main_1, true, 1,
OMAP4430_VDD_CORE_OPP50_UV),
/* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
--
1.7.0.4
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[PATCH] OMAP: Fix Memory Leaks in Smartreflex driver.
This Patch frees all the dynamically allocated memory
which couldn't have been released in some error hitting cases.
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
---
arch/arm/mach-omap2/smartreflex.c | 18 --
1 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex.c
b/arch/arm/mach-omap2/smartreflex.c
index d7deadf..a904625 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -282,6 +282,7 @@ error:
dev_err(sr_info-pdev-dev, %s: ERROR in registering
interrupt handler. Smartreflex will
not function as desired\n, __func__);
+ kfree(name);
kfree(sr_info);
return ret;
}
@@ -880,7 +881,7 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
ret = sr_late_init(sr_info);
if (ret) {
pr_warning(%s: Error in SR late init\n, __func__);
- return ret;
+ goto err_release_region;
}
}
@@ -891,14 +892,17 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
* not try to create rest of the debugfs entries.
*/
vdd_dbg_dir = omap_voltage_get_dbgdir(sr_info-voltdm);
- if (!vdd_dbg_dir)
- return -EINVAL;
+ if (!vdd_dbg_dir) {
+ ret = -EINVAL;
+ goto err_release_region;
+ }
dbg_dir = debugfs_create_dir(smartreflex, vdd_dbg_dir);
if (IS_ERR(dbg_dir)) {
dev_err(pdev-dev, %s: Unable to create debugfs directory\n,
__func__);
- return PTR_ERR(dbg_dir);
+ ret = PTR_ERR(dbg_dir);
+ goto err_release_region;
}
(void) debugfs_create_file(autocomp, S_IRUGO | S_IWUGO, dbg_dir,
@@ -914,7 +918,8 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
if (IS_ERR(nvalue_dir)) {
dev_err(pdev-dev, %s: Unable to create debugfs directory
for n-values\n, __func__);
- return PTR_ERR(nvalue_dir);
+ ret = PTR_ERR(nvalue_dir);
+ goto err_release_region;
}
omap_voltage_get_volttable(sr_info-voltdm, volt_data);
@@ -923,7 +928,8 @@ static int __init omap_sr_probe(struct platform_device
*pdev)
corresponding vdd vdd_%s. Cannot create debugfs
entries for n-values\n,
__func__, sr_info-voltdm-name);
- return -ENODATA;
+ ret = -ENODATA;
+ goto err_release_region;
}
for (i = 0; i sr_info-nvalue_count; i++) {
--
1.7.0.4
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[PATCH V4] OMAP3: PM: Set/clear T2 bit for Smartreflex on TWL
From: Thara Gopinath th...@ti.com
Voltage control on TWL can be done using VMODE/I2C1/I2C_SR.
Since almost all platforms use I2C_SR on omap3, omap3_twl_init by
default expects that OMAP's I2C_SR is plugged in to TWL's I2C
and calls omap3_twl_set_sr_bit. On platforms where I2C_SR is not connected,
the board files are expected to call omap3_twl_set_sr_bit(false) to
ensure that I2C_SR path is not set for voltage control and prevent
the default behavior of omap3_twl_init.
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Thara Gopinath th...@ti.com
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
---
This patch is based on LO PM Branch and Smartreflex has been
tested on OMAP3430 SDP, OMAP3630 SDP and boot tested on
OMAP2430 SDP.
arch/arm/mach-omap2/omap_twl.c | 61
arch/arm/mach-omap2/pm.h |1 +
2 files changed, 62 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
index 00e1d2b..87e07da 100644
--- a/arch/arm/mach-omap2/omap_twl.c
+++ b/arch/arm/mach-omap2/omap_twl.c
@@ -59,8 +59,15 @@
static bool is_offset_valid;
static u8 smps_offset;
+/*
+ * Flag to ensure Smartreflex bit in TWL
+ * being cleared in board file is not overwritten.
+ */
+static bool __initdata twl_sr_enable_autoinit;
+#define TWL4030_DCDC_GLOBAL_CFG0x06
#define REG_SMPS_OFFSET 0xE0
+#define SMARTREFLEX_ENABLE BIT(3)
static unsigned long twl4030_vsel_to_uv(const u8 vsel)
{
@@ -269,6 +276,18 @@ int __init omap3_twl_init(void)
omap3_core_volt_info.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
}
+ /*
+* The smartreflex bit on twl4030 specifies if the setting of voltage
+* is done over the I2C_SR path. Since this setting is independent of
+* the actual usage of smartreflex AVS module, we enable TWL SR bit
+* by default irrespective of whether smartreflex AVS module is enabled
+* on the OMAP side or not. This is because without this bit enabled,
+* the voltage scaling through vp forceupdate/bypass mechanism of
+* voltage scaling will not function on TWL over I2C_SR.
+*/
+ if (!twl_sr_enable_autoinit)
+ omap3_twl_set_sr_bit(true);
+
voltdm = omap_voltage_domain_lookup(mpu);
omap_voltage_register_pmic(voltdm, omap3_mpu_volt_info);
@@ -277,3 +296,45 @@ int __init omap3_twl_init(void)
return 0;
}
+
+/**
+ * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL
+ * @enable: enable SR mode in twl or not
+ *
+ * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure
+ * voltage scaling through OMAP SR works. Else, the smartreflex bit
+ * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but
+ * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct
+ * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages,
+ * in those scenarios this bit is to be cleared (enable = false).
+ *
+ * Returns 0 on sucess, error is returned if I2C read/write fails.
+ */
+int __init omap3_twl_set_sr_bit(bool enable)
+{
+ u8 temp;
+ int ret;
+ if (twl_sr_enable_autoinit)
+ pr_warning(%s: unexpected multiple calls\n, __func__);
+
+ ret = twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, temp,
+ TWL4030_DCDC_GLOBAL_CFG);
+ if (ret)
+ goto err;
+
+ if (enable)
+ temp |= SMARTREFLEX_ENABLE;
+ else
+ temp = ~SMARTREFLEX_ENABLE;
+
+ ret = twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, temp,
+ TWL4030_DCDC_GLOBAL_CFG);
+ if (!ret) {
+ twl_sr_enable_autoinit = true;
+ return 0;
+ }
+err:
+ pr_err(%s: Error access to TWL4030 (%d)\n, __func__, ret);
+ return ret;
+}
+
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 39580e6..797bfd1 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -127,6 +127,7 @@ static inline void omap_enable_smartreflex_on_init(void) {}
#ifdef CONFIG_TWL4030_CORE
extern int omap3_twl_init(void);
extern int omap4_twl_init(void);
+extern int omap3_twl_set_sr_bit(bool enable);
#else
static inline int omap3_twl_init(void)
{
--
1.7.0.4
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[PATCH V3] OMAP3: PM: Set/clear T2 bit for Smartreflex on TWL
From: Thara Gopinath th...@ti.com
The smartreflex bit on twl4030 specifies if the setting of voltage
is done over the I2C_SR path. Given that there are platforms that
do not use I2C_SR path for voltage scaling, a new function
'omap3_twl_set_sr_bit' with parameter to set/clear SR bit has been
provided for flexibility. It is called with appropriate param
for platforms where voltage is not scaled using I2C_SR path
from board file, to make sure this bit is not overwritten in
'omap3_twl_init'.
This patch is based on LO PM Branch and Smartreflex has been
tested on OMAP3430 SDP, OMAP3630 SDP and boot tested on
OMAP2430 SDP.
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Thara Gopinath th...@ti.com
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
---
arch/arm/mach-omap2/omap_twl.c | 60
arch/arm/mach-omap2/pm.h |1 +
2 files changed, 61 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
index 00e1d2b..8b24839 100644
--- a/arch/arm/mach-omap2/omap_twl.c
+++ b/arch/arm/mach-omap2/omap_twl.c
@@ -59,8 +59,15 @@
static bool is_offset_valid;
static u8 smps_offset;
+/*
+ * Flag to ensure Smartreflex bit in TWL
+ * being cleared in board file is not overwritten.
+ */
+static bool __initdata twl_sr_enable_autoinit;
+#define TWL4030_DCDC_GLOBAL_CFG0x06
#define REG_SMPS_OFFSET 0xE0
+#define SMARTREFLEX_ENABLE BIT(3)
static unsigned long twl4030_vsel_to_uv(const u8 vsel)
{
@@ -269,6 +276,18 @@ int __init omap3_twl_init(void)
omap3_core_volt_info.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
}
+ /*
+* The smartreflex bit on twl4030 specifies if the setting of voltage
+* is done over the I2C_SR path. Since this setting is independent of
+* the actual usage of smartreflex AVS module, we enable TWL SR bit
+* by default irrespective of whether smartreflex AVS module is enabled
+* on the OMAP side or not. This is because without this bit enabled,
+* the voltage scaling through vp forceupdate/bypass mechanism of
+* voltage scaling will not function on TWL over I2C_SR.
+*/
+ if (!twl_sr_enable_autoinit)
+ omap3_twl_set_sr_bit(true);
+
voltdm = omap_voltage_domain_lookup(mpu);
omap_voltage_register_pmic(voltdm, omap3_mpu_volt_info);
@@ -277,3 +296,44 @@ int __init omap3_twl_init(void)
return 0;
}
+
+/**
+ * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL
+ * @enable: enable SR mode in twl or not
+ *
+ * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure
+ * voltage scaling through OMAP SR works. Else, the smartreflex bit
+ * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but
+ * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct
+ * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages,
+ * in those scenarios this bit is to be cleared (enable = false).
+ *
+ * Returns 0 on sucess, error is returned if I2C read/write fails.
+ */
+int __init omap3_twl_set_sr_bit(bool enable)
+{
+ u8 temp;
+ int ret;
+ if (twl_sr_enable_autoinit)
+ pr_warning(%s: unexpected multiple calls\n, __func__);
+
+ ret = twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, temp,
+ TWL4030_DCDC_GLOBAL_CFG);
+ if (ret)
+ goto err;
+
+ if (enable)
+ temp |= SMARTREFLEX_ENABLE;
+ else
+ temp = ~SMARTREFLEX_ENABLE;
+
+ ret = twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, temp,
+ TWL4030_DCDC_GLOBAL_CFG);
+ if (!ret) {
+ twl_sr_enable_autoinit = true;
+ return 0;
+ }
+err:
+ pr_err(%s: Error access to TWL4030 (%d)\n, __func__, ret);
+ return ret;
+}
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 39580e6..797bfd1 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -127,6 +127,7 @@ static inline void omap_enable_smartreflex_on_init(void) {}
#ifdef CONFIG_TWL4030_CORE
extern int omap3_twl_init(void);
extern int omap4_twl_init(void);
+extern int omap3_twl_set_sr_bit(bool enable);
#else
static inline int omap3_twl_init(void)
{
--
1.7.0.4
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[PATCH V2] OMAP3: PM: Set/reset T2 bit for Smartreflex on TWL.
From: Thara Gopinath th...@ti.com
The smartreflex bit on twl4030 needs to be enabled by default irrespective
of whether smartreflex module is enabled on the OMAP side or not.
This is because without this bit enabled the voltage scaling through
vp forceupdate does not function properly on OMAP3.API added
'omap3_twl_set_sr_bit' with parameter to set/clear SR bit. It is cleared
for platforms where voltage is not scaled using vpforceupdate
or vc_bypass Method. In those cases 'omap3_twl_set_sr_bit' is called
from board file, to make sure this bit is not overwritten in
'omap3_twl_init', a flag 'twl_sr_enable'
is added.
This patch is based on LO PM Branch and Smartreflex has been
tested on OMAP3430 SDP, OMAP3630 SDP and boot tested on
OMAP2430 SDP.
Signed-off-by: Thara Gopinath th...@ti.com
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
---
arch/arm/mach-omap2/omap_twl.c | 62
arch/arm/mach-omap2/pm.h |1 +
2 files changed, 63 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
index 00e1d2b..871a349 100644
--- a/arch/arm/mach-omap2/omap_twl.c
+++ b/arch/arm/mach-omap2/omap_twl.c
@@ -59,8 +59,15 @@
static bool is_offset_valid;
static u8 smps_offset;
+/*
+ * Flag to ensure Smartreflex bit in TWL
+ * being cleared in board file is not overwritten.
+ */
+static bool twl_sr_enable = true;
+#define TWL4030_DCDC_GLOBAL_CFG0x06
#define REG_SMPS_OFFSET 0xE0
+#define SMARTREFLEX_ENABLE BIT(3)
static unsigned long twl4030_vsel_to_uv(const u8 vsel)
{
@@ -269,6 +276,16 @@ int __init omap3_twl_init(void)
omap3_core_volt_info.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
}
+ /*
+* The smartreflex bit on twl4030 needs to be enabled by
+* default irrespective of whether smartreflex module is
+* enabled on the OMAP side or not. This is because without
+* this bit enabled the voltage scaling through
+* vp forceupdate does not function properly on OMAP3.
+*/
+ if (twl_sr_enable)
+ omap3_twl_set_sr_bit(1);
+
voltdm = omap_voltage_domain_lookup(mpu);
omap_voltage_register_pmic(voltdm, omap3_mpu_volt_info);
@@ -277,3 +294,48 @@ int __init omap3_twl_init(void)
return 0;
}
+
+/**
+ * omap3_twl_set_sr_bit() - API to Set/Clear SR bit on TWL
+ * @flag: Flag to Set/Clear SR bit
+ *
+ * If flag is non zero, enables Smartreflex bit on TWL 4030
+ * to make sure voltage scaling through Vp forceupdate works.
+ * Else, the smartreflex bit on twl4030 is
+ * cleared as there are platforms which use
+ * OMAP3 and T2 but use Synchronized Scaling Hardware
+ * Strategy (ENABLE_VMODE=1) and Direct Strategy Software
+ * Scaling Mode (ENABLE_VMODE=0), for setting the voltages,
+ * in those scenarios this bit is to be cleared.
+ * API returns 0 on sucess, error is returned
+ * if I2C read/write fails.
+ */
+
+int omap3_twl_set_sr_bit(u8 flag)
+{
+ u8 temp;
+ int ret;
+
+ ret = twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, temp,
+ TWL4030_DCDC_GLOBAL_CFG);
+ if (ret)
+ goto err;
+
+ if (flag) {
+ temp |= SMARTREFLEX_ENABLE;
+ twl_sr_enable = true;
+ } else {
+ temp = ~SMARTREFLEX_ENABLE;
+ twl_sr_enable = false;
+ }
+
+ ret = twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, temp,
+ TWL4030_DCDC_GLOBAL_CFG);
+ if (ret) {
+err:
+ pr_err(%s: Unable to Read/Write to TWL4030 through I2C bus
+ \n, __func__);
+ return -EINVAL;
+ }
+ return 0;
+}
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 704766b..c98be66 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -127,6 +127,7 @@ static inline void omap_enable_smartreflex_on_init(void) {}
#ifdef CONFIG_TWL4030_CORE
extern int omap3_twl_init(void);
extern int omap4_twl_init(void);
+extern int omap3_twl_set_sr_bit(u8 flag);
#else
static inline int omap3_twl_init(void)
{
--
1.7.0.4
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[PATCH] OMAP3: PM: Adding T2 enabling of smartreflex
From: Thara Gopinath th...@ti.com
The smartreflex bit on twl4030 needs to be enabled by default irrespective
of whether smartreflex module is enabled on the OMAP side or not.
This is because without this bit enabled the voltage scaling through
vp forceupdate does not function properly on OMAP3. There are two
APIs being added 'omap3_twl_enable_sr' to set SR bit and other API
'omap3_twl_disable_sr' to disable SR bit for platforms where voltage
is not scaled using vpforceupdate or vc_bypass Method.
This patch is based on LO PM Branch and Smartreflex has been
tested on OMAP3430 SDP, OMAP3630 SDP and boot tested on
OMAP2430 SDP.
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
Signed-off-by: Thara Gopinath th...@ti.com
---
arch/arm/mach-omap2/omap_twl.c | 46
arch/arm/mach-omap2/pm.h |2 +
2 files changed, 48 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
index 00e1d2b..5b3ca56 100644
--- a/arch/arm/mach-omap2/omap_twl.c
+++ b/arch/arm/mach-omap2/omap_twl.c
@@ -60,7 +60,9 @@
static bool is_offset_valid;
static u8 smps_offset;
+#define TWL4030_DCDC_GLOBAL_CFG0x06
#define REG_SMPS_OFFSET 0xE0
+#define SMARTREFLEX_ENABLE BIT(3)
static unsigned long twl4030_vsel_to_uv(const u8 vsel)
{
@@ -269,6 +271,15 @@ int __init omap3_twl_init(void)
omap3_core_volt_info.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
}
+ /*
+* The smartreflex bit on twl4030 needs to be enabled by
+* default irrespective of whether smartreflex module is
+* enabled on the OMAP side or not. This is because without
+* this bit enabled the voltage scaling through
+* vp forceupdate does not function properly on OMAP3.
+*/
+ omap3_twl_enable_sr();
+
voltdm = omap_voltage_domain_lookup(mpu);
omap_voltage_register_pmic(voltdm, omap3_mpu_volt_info);
@@ -277,3 +288,38 @@ int __init omap3_twl_init(void)
return 0;
}
+
+/*
+ * The smartreflex bit on twl4030 is enabled in twl_init
+ * but there are platforms which use OMAP3 and T2 but use
+ * Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and
+ * Direct Strategy Software Scaling Mode (ENABLE_VMODE=0).
+ * for setting the voltages of T2, in those scenarios this bit
+ * is to be cleared.
+ */
+void omap3_twl_disable_sr()
+{
+ u8 temp;
+
+ twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, temp,
+ TWL4030_DCDC_GLOBAL_CFG);
+ temp = ~SMARTREFLEX_ENABLE;
+ twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, temp,
+ TWL4030_DCDC_GLOBAL_CFG);
+}
+
+/*
+ * To enable Smartreflex bit on TWl 4030 to make sure
+ * voltage scaling through Vp forceupdate works.
+ */
+
+void omap3_twl_enable_sr()
+{
+ u8 temp;
+
+ twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, temp,
+ TWL4030_DCDC_GLOBAL_CFG);
+ temp |= SMARTREFLEX_ENABLE;
+ twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, temp,
+ TWL4030_DCDC_GLOBAL_CFG);
+}
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 704766b..8500356 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -127,6 +127,8 @@ static inline void omap_enable_smartreflex_on_init(void) {}
#ifdef CONFIG_TWL4030_CORE
extern int omap3_twl_init(void);
extern int omap4_twl_init(void);
+extern void omap3_twl_disable_sr(void);
+extern void omap3_twl_enable_sr(void);
#else
static inline int omap3_twl_init(void)
{
--
1.7.0.4
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[PATCH] OMAP4 PM: To correct voltages in MPU OPP Table
From: Shweta Gulati shweta.gul...@ti.com
There is a mismatch in voltages specified in OPP table of MPU
and voltage specified in voltage table 'omap44xx_vdd_mpu_volt_data'
This Patch corrects MPU OPP Table as
well as enable OPP-Turbo and OPP-SB for MPU by default.
Signed-off-by: Thara Gopinath th...@ti.com
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
---
The patch is generated on top of Kevin's PM branch. It's needed for SR
functionality on the current pm branch. Have tested SR with this patch
with different OPP configurations from boot loader.
arch/arm/mach-omap2/opp4xxx_data.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c
b/arch/arm/mach-omap2/opp4xxx_data.c
index a11fa56..4f35361 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -25,13 +25,13 @@
static struct omap_opp_def __initdata omap44xx_opp_def_list[] = {
/* MPU OPP1 - OPP50 */
- OPP_INITIALIZER(mpu, true, 3, 110),
+ OPP_INITIALIZER(mpu, true, 3, 93),
/* MPU OPP2 - OPP100 */
- OPP_INITIALIZER(mpu, true, 6, 120),
+ OPP_INITIALIZER(mpu, true, 6, 110),
/* MPU OPP3 - OPP-Turbo */
- OPP_INITIALIZER(mpu, false, 8, 126),
+ OPP_INITIALIZER(mpu, true, 8, 126),
/* MPU OPP4 - OPP-SB */
- OPP_INITIALIZER(mpu, false, 100800, 135),
+ OPP_INITIALIZER(mpu, true, 100800, 135),
/* L3 OPP1 - OPP50 */
OPP_INITIALIZER(l3_main_1, true, 1, 93),
/* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
--
1.7.0.4
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[PATCHv2 1/2]OMAP3: PM: To put all the powerdomains in OFF mode instead of Ret
From: Shweta Gulati shweta.gul...@ti.com
According to Defect OMAPS00210499 CAM, DSS and USBHOST should stay
in OFF state instead of Retention in OS Idle Path.
This Patch puts all the powerdomain in OFF state by default
in pm init code and ensures that Mpu next state is OFF only
before it goes to Suspend/Idle and RET initiallly as that
could have caused system to hang if ROM code issues WFI.
Signed-off-by: Vishwanath BS vishwanath...@ti.com
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
---
Index: kernel-omap3/arch/arm/mach-omap2/cpuidle34xx.c
===
--- kernel-omap3.orig/arch/arm/mach-omap2/cpuidle34xx.c
+++ kernel-omap3/arch/arm/mach-omap2/cpuidle34xx.c
@@ -144,7 +144,7 @@ static int omap3_enter_idle(struct cpuid
local_irq_disable();
local_fiq_disable();
- if (!enable_off_mode) {
+ if (disable_off_mode) {
if (mpu_state PWRDM_POWER_RET)
mpu_state = PWRDM_POWER_RET;
if (core_state PWRDM_POWER_RET)
Index: kernel-omap3/arch/arm/mach-omap2/pm-debug.c
===
--- kernel-omap3.orig/arch/arm/mach-omap2/pm-debug.c
+++ kernel-omap3/arch/arm/mach-omap2/pm-debug.c
@@ -548,7 +548,7 @@ static int option_set(void *data, u64 va
*option = val;
- if (option == enable_off_mode)
+ if (option == disable_off_mode)
omap3_pm_off_mode_enable(val);
return 0;
}
@@ -597,8 +597,8 @@ static int __init pm_dbg_init(void)
}
- (void) debugfs_create_file(enable_off_mode, S_IRUGO | S_IWUGO, d,
- enable_off_mode, pm_dbg_option_fops);
+ (void) debugfs_create_file(disable_off_mode, S_IRUGO | S_IWUGO, d,
+ disable_off_mode, pm_dbg_option_fops);
(void) debugfs_create_file(sleep_while_idle, S_IRUGO | S_IWUGO, d,
sleep_while_idle, pm_dbg_option_fops);
(void) debugfs_create_file(enable_oswr, S_IRUGO | S_IWUGO, d,
Index: kernel-omap3/arch/arm/mach-omap2/pm.h
===
--- kernel-omap3.orig/arch/arm/mach-omap2/pm.h
+++ kernel-omap3/arch/arm/mach-omap2/pm.h
@@ -13,7 +13,7 @@
#include plat/powerdomain.h
-extern u32 enable_off_mode;
+extern u32 disable_off_mode;
extern u32 sleep_while_idle;
extern u32 enable_oswr;
extern u32 voltage_off_while_idle;
Index: kernel-omap3/arch/arm/mach-omap2/pm34xx.c
===
--- kernel-omap3.orig/arch/arm/mach-omap2/pm34xx.c
+++ kernel-omap3/arch/arm/mach-omap2/pm34xx.c
@@ -74,7 +74,7 @@ static inline bool is_suspending(void)
#define OMAP3630_EFUSE_CNTRL 0x48002A8C
#define ABO_LDO_TRANXDONE_TIMEOUT 100
-u32 enable_off_mode;
+u32 disable_off_mode;
u32 sleep_while_idle;
u32 enable_oswr;
u32 wakeup_timer_seconds;
@@ -811,6 +811,14 @@ static int omap3_pm_suspend(void)
goto restore;
}
}
+ if (!disable_off_mode) {
+ list_for_each_entry(pwrst, pwrst_list, node) {
+ if (!strcmp(mpu_pwrdm, pwrst-pwrdm-name) ||
+ !strcmp(core_pwrdm, pwrst-pwrdm-name))
+ pwrdm_set_next_pwrst(pwrst-pwrdm,
+ PWRDM_POWER_OFF);
+ }
+ }
omap_uart_prepare_suspend();
omap3_intc_suspend();
@@ -1193,15 +1201,15 @@ static void __init prcm_setup_regs(void)
omap3_d2d_idle();
}
-void omap3_pm_off_mode_enable(int enable)
+void omap3_pm_off_mode_enable(int disable)
{
struct power_state *pwrst;
u32 state;
- if (enable)
- state = PWRDM_POWER_OFF;
- else
+ if (disable)
state = PWRDM_POWER_RET;
+ else
+ state = PWRDM_POWER_OFF;
#ifdef CONFIG_OMAP_PM_SRF
resource_lock_opp(VDD1_OPP);
@@ -1308,7 +1316,8 @@ static int __init pwrdms_setup(struct po
if (!pwrst)
return -ENOMEM;
pwrst-pwrdm = pwrdm;
- if (strcmp(iva2_pwrdm, pwrdm-name))
+ if (!strcmp(mpu_pwrdm, pwrdm-name) ||
+ !strcmp(core_pwrdm, pwrdm-name))
pwrst-next_state = PWRDM_POWER_RET;
else
pwrst-next_state = PWRDM_POWER_OFF;
Index: kernel-omap3/arch/arm/mach-omap2/resource34xx.c
===
--- kernel-omap3.orig/arch/arm/mach-omap2/resource34xx.c
+++ kernel-omap3/arch/arm/mach-omap2/resource34xx.c
@@ -109,7 +109,7 @@ void init_pd_latency(struct shared_resou
struct pd_latency_db *pd_lat_db;
resp-no_of_users = 0;
- if (enable_off_mode)
+ if (!disable_off_mode)
resp-curr_level = PD_LATENCY_OFF;
else
[PATCH V2] OMAP3: PM: Workaround for DPLL3 Lock issue
From: Vishwanath Sripathy vishwanath...@ti.com
OMAP3430/3630 has a Silicon bug because of which SDRC is
released from IDLE even before Core DPLL has locked. This leads
to undefined behaviour of SDRC DLL.
This patch has workaround for the same.
Description of WA for 3430:
Initialization:
Disable DPLL3 automatic mode by default. Issue will not be faced as
DPLL3
is always locked.
Before CORE Voltage Domain (VDD2) Sleep Transition to RETENTION or OFF mode:
1. Reduce DPLL3 M2 Frequency to get L3 running at OPP2 Frequency
(by changing M2 Divider value). This is increasing the period duration
of
one L3 clock cycle.
o In case of CORE is at OPP3 (166...@1.15v):
Lower the frequency to 83MHz.
o In case of CORE is at OPP2 (83...@1.05v):
Keep the frequency as it is (83MHz).
2. Increase CORE Voltage to 1.2V. This is reducing the timing duration of
the
critical path signal which will now fit to one L3 clock cycle.
3. Enable DPLL3 Automatic mode. This will ensure proper transition to
RETENTION or OFF mode.
After CORE Voltage Domain Wakeup Transition from RETENTION or OFF mode:
1. Disable DPLL3 Automatic mode.
2. Restore previous DPLL3 M2 Frequency and CORE Voltage values.
Description of WA for 3630:
Initialization:
Disable DPLL3 automatic mode by default. Issue will not be faced as
DPLL3 is always locked.
Before CORE Voltage Domain(VDD2) Sleep Transition to RETENTION or OFF mode:
1. Reduce DPLL3 M2 Frequency to get L3 running at OPP50 Frequency
(by changing M2 Divider value) and set VDD2 Voltage for OPP100.
This is increasing the period duration of one L3 clock cycle and
reducing
the timing duration of the critical path signal which will now fit to
one
L3 clock cycle.
o In case of CORE is at OPP100 (L3=200MHz, VDD2=1.1375V):
Lower the frequency to 100MHz.
Keep the voltage as it is (1.1375V).
o In case of CORE is at OPP50 (L3=100MHz, VDD2=0.93V):
Keep the frequency as it is (100MHz).
Increase the voltage to 1.1375V.
2. Enable DPLL3 Automatic mode. This will ensure proper transition to
RETENTION or OFF mode.
After CORE Voltage Domain Wakeup Transition from RETENTION or OFF mode:
1. Disable DPLL3 Automatic mode.
2. Restore previous DPLL3 M2 Frequency and CORE Voltage values.
Also OSWR should not be attempted if DPLL3 has locked. This should be done as
part of OSWR patch series.
Patch tested on 3430SDP and 3630 ZOOM3.
Signed-off-by: Vishwanath Sripathy vishwanath...@ti.com
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
---
Index: linux-omap-pm/arch/arm/mach-omap2/pm.h
===
--- linux-omap-pm.orig/arch/arm/mach-omap2/pm.h
+++ linux-omap-pm/arch/arm/mach-omap2/pm.h
@@ -60,6 +60,10 @@ struct prm_setup_vc {
extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
+extern int program_vdd2_opp_3430(void);
+extern int reprogram_vdd2_opp_3430(int restore);
+extern int program_vdd2_opp_3630(void);
+extern int reprogram_vdd2_opp_3630(int restore);
extern u32 wakeup_timer_seconds;
extern struct omap_dm_timer *gptimer_wakeup;
Index: linux-omap-pm/arch/arm/mach-omap2/pm34xx.c
===
--- linux-omap-pm.orig/arch/arm/mach-omap2/pm34xx.c
+++ linux-omap-pm/arch/arm/mach-omap2/pm34xx.c
@@ -56,6 +56,7 @@
#include sdrc.h
#include omap3-opp.h
+
#ifdef CONFIG_SUSPEND
static suspend_state_t suspend_state = PM_SUSPEND_ON;
static inline bool is_suspending(void)
@@ -363,6 +364,8 @@ void omap_sram_idle(void)
u32 sdrc_pwr = 0;
int per_state_modified = 0;
unsigned int start =0, end = 0;
+ u32 fclk_status = 0;
+ int restore = 1;
if (!_omap_sram_idle)
return;
@@ -415,15 +418,6 @@ void omap_sram_idle(void)
if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON)
omap2_clkdm_deny_idle(mpu_pwrdm-pwrdm_clkdms[0]);
- /*
-* Disable smartreflex before entering WFI.
-* Only needed if we are going to enter retention or off.
-*/
- if (mpu_next_state = PWRDM_POWER_RET)
- omap_smartreflex_disable(VDD1, 1);
- if (core_next_state = PWRDM_POWER_RET)
- omap_smartreflex_disable(VDD2, 1);
-
/* CORE */
if (core_next_state PWRDM_POWER_ON) {
omap_uart_prepare_idle(0);
@@ -447,6 +441,31 @@ void omap_sram_idle(void)
prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
omap3_enable_io_chain();
}
+ /*
+* Disable smartreflex before entering WFI.
+* Only needed
[PATCH v3 OMAP3 PM]: Remove IVA state conflict between PM and DspBridge code
From: Shweta Gulati shweta.gul...@ti.com
This version of patch incorporates review comments which includes
shifting the code change in specific function 'omap3_iva_idle' and
removing iva_pwrdm from pwrst_list rather than checking all the pwrdms
in list to exclude iva_pwrdm.
The PM code should not set latency on IVA power state based on
the flag 'enable_off_mode'.This is taken care of in this version.
Signed-off-by: Sripathy Vishwanath vishwanath...@ti.com
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
---
Index: linux-omap-pm/arch/arm/mach-omap2/pm34xx.c
===
--- linux-omap-pm.orig/arch/arm/mach-omap2/pm34xx.c
+++ linux-omap-pm/arch/arm/mach-omap2/pm34xx.c
@@ -786,6 +786,12 @@ static void __init omap3_iva_idle(void)
OMAP3430_RST2_IVA2 |
OMAP3430_RST3_IVA2,
OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
+ /* Put the IVA2 In Idle */
+ prm_rmw_mod_reg_bits(OMAP3430_LASTPOWERSTATEENTERED_MASK, 0,
+ OMAP3430_IVA2_MOD, OMAP2_PM_PWSTCTRL);
+ /* Make Clock transition Automatic*/
+ cm_rmw_mod_reg_bits(OMAP3430_CLKTRCTRL_IVA2_MASK, 0x3,
+ OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
}
static void __init omap3_d2d_idle(void)
@@ -1074,8 +1080,11 @@ static int __init pwrdms_setup(struct po
if (!pwrst)
return -ENOMEM;
pwrst-pwrdm = pwrdm;
- pwrst-next_state = PWRDM_POWER_RET;
- list_add(pwrst-node, pwrst_list);
+ if (strcmp(iva2_pwrdm, pwrdm-name)) {
+ pwrst-next_state = PWRDM_POWER_RET;
+ list_add(pwrst-node, pwrst_list);
+ } else
+pwrst-next_state = PWRDM_POWER_OFF;
if (pwrdm_has_hdwr_sar(pwrdm))
pwrdm_enable_hdwr_sar(pwrdm);
Index: linux-omap-pm/arch/arm/mach-omap2/resource34xx.c
===
--- linux-omap-pm.orig/arch/arm/mach-omap2/resource34xx.c
+++ linux-omap-pm/arch/arm/mach-omap2/resource34xx.c
@@ -140,7 +140,8 @@ int set_pd_latency(struct shared_resourc
}
if (!enable_off_mode pd_lat_level == PD_LATENCY_OFF)
- pd_lat_level = PD_LATENCY_RET;
+ if (strcmp(iva2_pwrdm, pwrdm-name))
+ pd_lat_level = PD_LATENCY_RET;
resp-curr_level = pd_lat_level;
set_pwrdm_state(pwrdm, pd_lat_level);
--
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