Re: [PATCH v3 2/4] ARM: dts: am437x-gp-evm: add support for parallel NAND flash
* Tony Lindgren t...@atomide.com [140507 14:20]:
* Gupta, Pekon pe...@ti.com [140507 12:20]:
From: Tony Lindgren [mailto:t...@atomide.com]
* Pekon Gupta pe...@ti.com [140422 00:34]:
+gpmc {
+status = okay;
+pinctrl-names = default;
+pinctrl-0 = nand_flash_x8;
+ranges = 0 0 0x0800 0x1000; /* CS0: NAND */
Please use the minimum size 16MB GPMC range here, NAND only
has few registers addressable unlike NOR that actually uses the
whole range.
+nand@0,0 {
+reg = 0 0 0; /* CS0, offset 0 */
Then here map the true size of the NAND device IO register area.
BTW, we should do the similar changes to other files so we can
unify the GPMC partitioning a bit. But that's unsafe to do until
we have fixed the issue of mapping GPMC devices to a different
location from the bootloader location.
I have found the fix of this issue in gpmc_cs_remap() just testing it
using beaglebone NOR cape. I'll post that separately, once I'm confident.
OK that's great. Yet another issue I've noticed is that u-boot
seems to program 37xx L3 to run at 200 MHz and the LAN9220
timings overflow the GPMC registers as 200 / 5 = 32.
And looks like we have a build warning in the -rc cycle with
omap2plus_defconfig:
drivers/mtd/nand/omap2.c:1250:12: warning: ‘erased_sector_bitflips’ defined but
not used [-Wunused-function]
Can you please fix that if not already fixed?
Tony
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RE: [PATCH v3 2/4] ARM: dts: am437x-gp-evm: add support for parallel NAND flash
Hi Tony, And looks like we have a build warning in the -rc cycle with omap2plus_defconfig: drivers/mtd/nand/omap2.c:1250:12: warning: ‘erased_sector_bitflips’ defined but not used [- Wunused-function] Can you please fix that if not already fixed? Yes, this is already fixed and is in MTD Maintainer's tree [1]. As this warning was introduced in MTD patches, so fix is also coming via that sub-system. http://lists.infradead.org/pipermail/linux-mtd/2014-April/053330.html with regards, pekon
RE: [PATCH v3 2/4] ARM: dts: am437x-gp-evm: add support for parallel NAND flash
From: Tony Lindgren [mailto:t...@atomide.com]
* Pekon Gupta pe...@ti.com [140422 00:34]:
+gpmc {
+status = okay;
+pinctrl-names = default;
+pinctrl-0 = nand_flash_x8;
+ranges = 0 0 0x0800 0x1000; /* CS0: NAND */
Please use the minimum size 16MB GPMC range here, NAND only
has few registers addressable unlike NOR that actually uses the
whole range.
+nand@0,0 {
+reg = 0 0 0; /* CS0, offset 0 */
Then here map the true size of the NAND device IO register area.
BTW, we should do the similar changes to other files so we can
unify the GPMC partitioning a bit. But that's unsafe to do until
we have fixed the issue of mapping GPMC devices to a different
location from the bootloader location.
I have found the fix of this issue in gpmc_cs_remap() just testing it
using beaglebone NOR cape. I'll post that separately, once I'm confident.
But for now, I'll re-send just these patches for NAND DT node with
your feedbacks incorporated, so that NAND is stable on these
platforms / boards from 3.16 onwards.
with regards, pekon
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Re: [PATCH v3 2/4] ARM: dts: am437x-gp-evm: add support for parallel NAND flash
* Gupta, Pekon pe...@ti.com [140507 12:20]:
From: Tony Lindgren [mailto:t...@atomide.com]
* Pekon Gupta pe...@ti.com [140422 00:34]:
+gpmc {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = nand_flash_x8;
+ ranges = 0 0 0x0800 0x1000; /* CS0: NAND */
Please use the minimum size 16MB GPMC range here, NAND only
has few registers addressable unlike NOR that actually uses the
whole range.
+ nand@0,0 {
+ reg = 0 0 0; /* CS0, offset 0 */
Then here map the true size of the NAND device IO register area.
BTW, we should do the similar changes to other files so we can
unify the GPMC partitioning a bit. But that's unsafe to do until
we have fixed the issue of mapping GPMC devices to a different
location from the bootloader location.
I have found the fix of this issue in gpmc_cs_remap() just testing it
using beaglebone NOR cape. I'll post that separately, once I'm confident.
OK that's great. Yet another issue I've noticed is that u-boot
seems to program 37xx L3 to run at 200 MHz and the LAN9220
timings overflow the GPMC registers as 200 / 5 = 32.
But for now, I'll re-send just these patches for NAND DT node with
your feedbacks incorporated, so that NAND is stable on these
platforms / boards from 3.16 onwards.
OK sounds good to me.
Tony
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Re: [PATCH v3 2/4] ARM: dts: am437x-gp-evm: add support for parallel NAND flash
* Pekon Gupta pe...@ti.com [140422 00:34]:
+gpmc {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = nand_flash_x8;
+ ranges = 0 0 0x0800 0x1000; /* CS0: NAND */
Please use the minimum size 16MB GPMC range here, NAND only
has few registers addressable unlike NOR that actually uses the
whole range.
+ nand@0,0 {
+ reg = 0 0 0; /* CS0, offset 0 */
Then here map the true size of the NAND device IO register area.
BTW, we should do the similar changes to other files so we can
unify the GPMC partitioning a bit. But that's unsafe to do until
we have fixed the issue of mapping GPMC devices to a different
location from the bootloader location.
Regards,
Tony
--
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the body of a message to majord...@vger.kernel.org
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[PATCH v3 2/4] ARM: dts: am437x-gp-evm: add support for parallel NAND flash
Adds pinmux and DT node for Micron (MT29F4G08AB) x8 NAND device present on
am437x-gp-evm board.
(1) As NAND Flash data lines are muxed with eMMC, Thus at a given time either
eMMC or NAND can be enabled. Selection between eMMC and NAND is controlled:
(a) By dynamically driving following GPIO pin from software
SPI2_CS0(GPIO) == 0 NAND is selected (default)
SPI2_CS0(GPIO) == 1 eMMC is selected
(b) By statically using Jumper (J89) on the board
(2) As NAND device connnected to this board has page-size=4K and oob-size=224,
So ROM code expects boot-loaders to be flashed in BCH16 ECC scheme for
NAND boot.
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/am437x-gp-evm.dts | 107
1 file changed, 107 insertions(+)
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp-evm.dts
index df8798e..0027ea7 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -81,6 +81,27 @@
0x164 MUX_MODE0 /*
eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
;
};
+
+ nand_flash_x8: nand_flash_x8 {
+ pinctrl-single,pins =
+ 0x26C(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /*
spi2_cs0.gpio/eMMCorNANDsel */
+ 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
+ 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
+ 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
+ 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
+ 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
+ 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
+ 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
+ 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
+ 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /*
gpmc_wait0.gpmc_wait0 */
+ 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7)/*
gpmc_wpn.gpmc_wpn */
+ 0x7c (PIN_OUTPUT | MUX_MODE0) /*
gpmc_csn0.gpmc_csn0 */
+ 0x90 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_advn_ale.gpmc_advn_ale */
+ 0x94 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_oen_ren.gpmc_oen_ren */
+ 0x98 (PIN_OUTPUT | MUX_MODE0) /*
gpmc_wen.gpmc_wen */
+ 0x9c (PIN_OUTPUT | MUX_MODE0) /*
gpmc_be0n_cle.gpmc_be0n_cle */
+ ;
+ };
};
i2c0 {
@@ -125,3 +146,89 @@
pinctrl-0 = mmc1_pins;
cd-gpios = gpio0 6 GPIO_ACTIVE_HIGH;
};
+
+elm {
+ status = okay;
+};
+
+gpmc {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = nand_flash_x8;
+ ranges = 0 0 0x0800 0x1000; /* CS0: NAND */
+ nand@0,0 {
+ reg = 0 0 0; /* CS0, offset 0 */
+ ti,nand-ecc-opt = bch8;
+ ti,elm-id = elm;
+ nand-bus-width = 8;
+ gpmc,device-width = 1;
+ gpmc,sync-clk-ps = 0;
+ gpmc,cs-on-ns = 0;
+ gpmc,cs-rd-off-ns = 40;
+ gpmc,cs-wr-off-ns = 40;
+ gpmc,adv-on-ns = 0;
+ gpmc,adv-rd-off-ns = 25;
+ gpmc,adv-wr-off-ns = 25;
+ gpmc,we-on-ns = 0;
+ gpmc,we-off-ns = 20;
+ gpmc,oe-on-ns = 3;
+ gpmc,oe-off-ns = 30;
+ gpmc,access-ns = 30;
+ gpmc,rd-cycle-ns = 40;
+ gpmc,wr-cycle-ns = 40;
+ gpmc,wait-on-read = true;
+ gpmc,wait-on-write = true;
+ gpmc,bus-turnaround-ns = 0;
+ gpmc,cycle2cycle-delay-ns = 0;
+ gpmc,clk-activation-ns = 0;
+ gpmc,wait-monitoring-ns = 0;
+ gpmc,wr-access-ns = 40;
+ gpmc,wr-data-mux-bus-ns = 0;
+ /* MTD partition table */
+ /* All SPL-* partitions are sized to minimal length
+* which can be independently programmable. For
+* NAND flash this is equal to size of erase-block */
+ #address-cells = 1;
+ #size-cells = 1;
+ partition@0 {
+ label = NAND.SPL;
+ reg = 0x 0x0004;
+ };
+ partition@1 {
+ label = NAND.SPL.backup1;
+ reg = 0x0004 0x0004;
+ };
+ partition@2 {
+ label = NAND.SPL.backup2;
+ reg = 0x0008 0x0004;
+ };
+ partition@3 {
+ label = NAND.SPL.backup3;
+ reg = 0x000C 0x0004;
+ };
+
