RE: [PATCH V2] OMAP3: PM: Workaround for DPLL3 Lock issue
Kevin, -Original Message- From: Kevin Hilman [mailto:khil...@deeprootsystems.com] Sent: Tuesday, May 18, 2010 10:07 PM To: Sripathy, Vishwanath Cc: Gulati, Shweta; linux-omap@vger.kernel.org Subject: Re: [PATCH V2] OMAP3: PM: Workaround for DPLL3 Lock issue Sripathy, Vishwanath vishwanath...@ti.com writes: All that being said, why is the voltage level being programmed here? It seems to me that all of this errata handling should be self-contained in the voltage layer. I am not sure if entire errata can be contained in voltage layer. This is because we are performing DVFS operation in CPU Idle path which involves both Frequency and Voltage scaling. So currently this has been done in resource34xx.c where DVFS is implemented. What I mean is that there seems to be no good reason to be calling these from pm34xx.c, they should be called where voltage scaling is done. Sorry I still do not understand how errata can be invoked from Voltage scaling. Pls note that errata has to be applied only when Core is entering retention or off which can be detected only in omap_sram_idle function. Errata is tightly coupled with CPU idle path. Vishwa Kevin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V2] OMAP3: PM: Workaround for DPLL3 Lock issue
Hi Vishwa, On 5/13/2010 12:12 PM, shweta gulati wrote: From: Vishwanath Sripathyvishwanath...@ti.com OMAP3430/3630 has a Silicon bug because of which SDRC is released from IDLE even before Core DPLL has locked. This leads to undefined behaviour of SDRC DLL. This patch has workaround for the same. Description of WA for 3430: Initialization: Disable DPLL3 automatic mode by default. Issue will not be faced as DPLL3 is always locked. Before CORE Voltage Domain (VDD2) Sleep Transition to RETENTION or OFF mode: 1. Reduce DPLL3 M2 Frequency to get L3 running at OPP2 Frequency (by changing M2 Divider value). This is increasing the period duration of one L3 clock cycle. o In case of CORE is at OPP3 (166...@1.15v): Lower the frequency to 83MHz. o In case of CORE is at OPP2 (83...@1.05v): Keep the frequency as it is (83MHz). 2. Increase CORE Voltage to 1.2V. This is reducing the timing duration of the critical path signal which will now fit to one L3 clock cycle. 3. Enable DPLL3 Automatic mode. This will ensure proper transition to RETENTION or OFF mode. After CORE Voltage Domain Wakeup Transition from RETENTION or OFF mode: 1. Disable DPLL3 Automatic mode. 2. Restore previous DPLL3 M2 Frequency and CORE Voltage values. Description of WA for 3630: Initialization: Disable DPLL3 automatic mode by default. Issue will not be faced as DPLL3 is always locked. Before CORE Voltage Domain(VDD2) Sleep Transition to RETENTION or OFF mode: 1. Reduce DPLL3 M2 Frequency to get L3 running at OPP50 Frequency (by changing M2 Divider value) and set VDD2 Voltage for OPP100. This is increasing the period duration of one L3 clock cycle and reducing the timing duration of the critical path signal which will now fit to one L3 clock cycle. o In case of CORE is at OPP100 (L3=200MHz, VDD2=1.1375V): Lower the frequency to 100MHz. Keep the voltage as it is (1.1375V). o In case of CORE is at OPP50 (L3=100MHz, VDD2=0.93V): Keep the frequency as it is (100MHz). Increase the voltage to 1.1375V. 2. Enable DPLL3 Automatic mode. This will ensure proper transition to RETENTION or OFF mode. After CORE Voltage Domain Wakeup Transition from RETENTION or OFF mode: 1. Disable DPLL3 Automatic mode. 2. Restore previous DPLL3 M2 Frequency and CORE Voltage values. Also OSWR should not be attempted if DPLL3 has locked. This should be done as part of OSWR patch series. Patch tested on 3430SDP and 3630 ZOOM3. Do you have a more accurate description of the bug? What is the defect ID? The subject is about DPLL3 lock issue, and the description is all about the transition to CORE RET or OFF and playing with voltage... and why OSWR is affected as well? I'm a little bit confused by that... Is this bug dependent of the target power state? What about INACTIVE? Why setting the CORE at 1.2v when the description is only considering 1.1375v? Thanks, Benoit -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH V2] OMAP3: PM: Workaround for DPLL3 Lock issue
Hi Benoit, -Original Message- From: Cousson, Benoit Sent: Wednesday, May 19, 2010 5:28 PM To: Gulati, Shweta Cc: linux-omap@vger.kernel.org; Sripathy, Vishwanath Subject: Re: [PATCH V2] OMAP3: PM: Workaround for DPLL3 Lock issue Hi Vishwa, On 5/13/2010 12:12 PM, shweta gulati wrote: From: Vishwanath Sripathyvishwanath...@ti.com OMAP3430/3630 has a Silicon bug because of which SDRC is released from IDLE even before Core DPLL has locked. This leads to undefined behaviour of SDRC DLL. This patch has workaround for the same. Description of WA for 3430: Initialization: Disable DPLL3 automatic mode by default. Issue will not be faced as DPLL3 is always locked. Before CORE Voltage Domain (VDD2) Sleep Transition to RETENTION or OFF mode: 1. Reduce DPLL3 M2 Frequency to get L3 running at OPP2 Frequency (by changing M2 Divider value). This is increasing the period duration of one L3 clock cycle. o In case of CORE is at OPP3 (166...@1.15v): Lower the frequency to 83MHz. o In case of CORE is at OPP2 (83...@1.05v): Keep the frequency as it is (83MHz). 2. Increase CORE Voltage to 1.2V. This is reducing the timing duration of the critical path signal which will now fit to one L3 clock cycle. 3. Enable DPLL3 Automatic mode. This will ensure proper transition to RETENTION or OFF mode. After CORE Voltage Domain Wakeup Transition from RETENTION or OFF mode: 1. Disable DPLL3 Automatic mode. 2. Restore previous DPLL3 M2 Frequency and CORE Voltage values. Description of WA for 3630: Initialization: Disable DPLL3 automatic mode by default. Issue will not be faced as DPLL3 is always locked. Before CORE Voltage Domain(VDD2) Sleep Transition to RETENTION or OFF mode: 1. Reduce DPLL3 M2 Frequency to get L3 running at OPP50 Frequency (by changing M2 Divider value) and set VDD2 Voltage for OPP100. This is increasing the period duration of one L3 clock cycle and reducing the timing duration of the critical path signal which will now fit to one L3 clock cycle. o In case of CORE is at OPP100 (L3=200MHz, VDD2=1.1375V): Lower the frequency to 100MHz. Keep the voltage as it is (1.1375V). o In case of CORE is at OPP50 (L3=100MHz, VDD2=0.93V): Keep the frequency as it is (100MHz). Increase the voltage to 1.1375V. 2. Enable DPLL3 Automatic mode. This will ensure proper transition to RETENTION or OFF mode. After CORE Voltage Domain Wakeup Transition from RETENTION or OFF mode: 1. Disable DPLL3 Automatic mode. 2. Restore previous DPLL3 M2 Frequency and CORE Voltage values. Also OSWR should not be attempted if DPLL3 has locked. This should be done as part of OSWR patch series. Patch tested on 3430SDP and 3630 ZOOM3. Do you have a more accurate description of the bug? What is the defect ID? Defect Id is i581. The subject is about DPLL3 lock issue, and the description is all about the transition to CORE RET or OFF and playing with voltage... and why OSWR is affected as well? I'm a little bit confused by that... Is this bug dependent of the target power state? What about INACTIVE? The root cause of the issue is that SDRC IDLEREQ is deasserted before DPLL3 has locked. Because of this DLL may/may not lock based on Process Voltage Temperature conditions. The bug can occur when DPLL3 automatic transition is enabled. So DPLL3 automatic transition is disabled by default and it is enabled only when system is entering ret/off state (to facilitate voltage scaling). So when system is entering ret/off state, WA is applied (since DPLL3 autoidle is enabled, we can possibly hit the issue; hence the WA) Regarding OSWR, as per errata i580, DPLL3 cannot be kept Locked when CORE is in OSWR state if DPLL3 is set in Manual Lock mode. So if DPLL3 autoidle is not enabled (manual lock mode), then we should not attempt to goto Core OSWR. Why setting the CORE at 1.2v when the description is only considering 1.1375v? For OMAP3430, as per errata VDD2 should be set to 1.2V before attempting off/retention. 1.1375V applies for OMAP3630. Regards Vishwa Thanks, Benoit -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V2] OMAP3: PM: Workaround for DPLL3 Lock issue
On 5/19/2010 3:50 PM, Sripathy, Vishwanath wrote: Hi Benoit, -Original Message- From: Cousson, Benoit Sent: Wednesday, May 19, 2010 5:28 PM To: Gulati, Shweta Cc: linux-omap@vger.kernel.org; Sripathy, Vishwanath Subject: Re: [PATCH V2] OMAP3: PM: Workaround for DPLL3 Lock issue Hi Vishwa, On 5/13/2010 12:12 PM, shweta gulati wrote: From: Vishwanath Sripathyvishwanath...@ti.com OMAP3430/3630 has a Silicon bug because of which SDRC is released from IDLE even before Core DPLL has locked. This leads to undefined behaviour of SDRC DLL. This patch has workaround for the same. Description of WA for 3430: Initialization: Disable DPLL3 automatic mode by default. Issue will not be faced as DPLL3 is always locked. Before CORE Voltage Domain (VDD2) Sleep Transition to RETENTION or OFF mode: 1. Reduce DPLL3 M2 Frequency to get L3 running at OPP2 Frequency (by changing M2 Divider value). This is increasing the period duration of one L3 clock cycle. o In case of CORE is at OPP3 (166...@1.15v): Lower the frequency to 83MHz. o In case of CORE is at OPP2 (83...@1.05v): Keep the frequency as it is (83MHz). 2. Increase CORE Voltage to 1.2V. This is reducing the timing duration of the critical path signal which will now fit to one L3 clock cycle. 3. Enable DPLL3 Automatic mode. This will ensure proper transition to RETENTION or OFF mode. After CORE Voltage Domain Wakeup Transition from RETENTION or OFF mode: 1. Disable DPLL3 Automatic mode. 2. Restore previous DPLL3 M2 Frequency and CORE Voltage values. Description of WA for 3630: Initialization: Disable DPLL3 automatic mode by default. Issue will not be faced as DPLL3 is always locked. Before CORE Voltage Domain(VDD2) Sleep Transition to RETENTION or OFF mode: 1. Reduce DPLL3 M2 Frequency to get L3 running at OPP50 Frequency (by changing M2 Divider value) and set VDD2 Voltage for OPP100. This is increasing the period duration of one L3 clock cycle and reducing the timing duration of the critical path signal which will now fit to one L3 clock cycle. o In case of CORE is at OPP100 (L3=200MHz, VDD2=1.1375V): Lower the frequency to 100MHz. Keep the voltage as it is (1.1375V). o In case of CORE is at OPP50 (L3=100MHz, VDD2=0.93V): Keep the frequency as it is (100MHz). Increase the voltage to 1.1375V. 2. Enable DPLL3 Automatic mode. This will ensure proper transition to RETENTION or OFF mode. After CORE Voltage Domain Wakeup Transition from RETENTION or OFF mode: 1. Disable DPLL3 Automatic mode. 2. Restore previous DPLL3 M2 Frequency and CORE Voltage values. Also OSWR should not be attempted if DPLL3 has locked. This should be done as part of OSWR patch series. Patch tested on 3430SDP and 3630 ZOOM3. Do you have a more accurate description of the bug? What is the defect ID? Defect Id is i581. The subject is about DPLL3 lock issue, and the description is all about the transition to CORE RET or OFF and playing with voltage... and why OSWR is affected as well? I'm a little bit confused by that... Is this bug dependent of the target power state? What about INACTIVE? The root cause of the issue is that SDRC IDLEREQ is deasserted before DPLL3 has locked. Because of this DLL may/may not lock based on Process Voltage Temperature conditions. The bug can occur when DPLL3 automatic transition is enabled. So DPLL3 automatic transition is disabled by default and it is enabled only when system is entering ret/off state (to facilitate voltage scaling). So when system is entering ret/off state, WA is applied (since DPLL3 autoidle is enabled, we can possibly hit the issue; hence the WA) Thanks, but that still not explain why this WA is considered only for device transition to RET or OFF. The DPLL3 can got to idle as soon as the CORE is INACTIVE. How this case is handled? Why is it depend of the voltage? Am I missing something? After checking the errata, it looks like there is no further explanation than this one: These cases cannot be executed if only Power Domain transition is targeted which does not explain anything:-( I'll check that with Hayati. Regarding OSWR, as per errata i580, DPLL3 cannot be kept Locked when CORE is in OSWR state if DPLL3 is set in Manual Lock mode. So if DPLL3 autoidle is not enabled (manual lock mode), then we should not attempt to goto Core OSWR. Why setting the CORE at 1.2v when the description is only considering 1.1375v? For OMAP3430, as per errata VDD2 should be set to 1.2V before attempting off/retention. 1.1375V applies for OMAP3630. Oops, I missed the 3430 vs 3630 different paragraphs, you should maybe improve the readability of the description... or maybe it is just me:-) Thanks, Benoit
RE: [PATCH V2] OMAP3: PM: Workaround for DPLL3 Lock issue
Hi Benoit, -Original Message- From: Cousson, Benoit Sent: Wednesday, May 19, 2010 8:00 PM To: Sripathy, Vishwanath Cc: Gulati, Shweta; linux-omap@vger.kernel.org Subject: Re: [PATCH V2] OMAP3: PM: Workaround for DPLL3 Lock issue On 5/19/2010 3:50 PM, Sripathy, Vishwanath wrote: Hi Benoit, -Original Message- From: Cousson, Benoit Sent: Wednesday, May 19, 2010 5:28 PM To: Gulati, Shweta Cc: linux-omap@vger.kernel.org; Sripathy, Vishwanath Subject: Re: [PATCH V2] OMAP3: PM: Workaround for DPLL3 Lock issue Hi Vishwa, On 5/13/2010 12:12 PM, shweta gulati wrote: From: Vishwanath Sripathyvishwanath...@ti.com OMAP3430/3630 has a Silicon bug because of which SDRC is released from IDLE even before Core DPLL has locked. This leads to undefined behaviour of SDRC DLL. This patch has workaround for the same. Description of WA for 3430: Initialization: Disable DPLL3 automatic mode by default. Issue will not be faced as DPLL3 is always locked. Before CORE Voltage Domain (VDD2) Sleep Transition to RETENTION or OFF mode: 1.Reduce DPLL3 M2 Frequency to get L3 running at OPP2 Frequency (by changing M2 Divider value). This is increasing the period duration of one L3 clock cycle. o In case of CORE is at OPP3 (166...@1.15v): Lower the frequency to 83MHz. o In case of CORE is at OPP2 (83...@1.05v): Keep the frequency as it is (83MHz). 2.Increase CORE Voltage to 1.2V. This is reducing the timing duration of the critical path signal which will now fit to one L3 clock cycle. 3.Enable DPLL3 Automatic mode. This will ensure proper transition to RETENTION or OFF mode. After CORE Voltage Domain Wakeup Transition from RETENTION or OFF mode: 1.Disable DPLL3 Automatic mode. 2.Restore previous DPLL3 M2 Frequency and CORE Voltage values. Description of WA for 3630: Initialization: Disable DPLL3 automatic mode by default. Issue will not be faced as DPLL3 is always locked. Before CORE Voltage Domain(VDD2) Sleep Transition to RETENTION or OFF mode: 1.Reduce DPLL3 M2 Frequency to get L3 running at OPP50 Frequency (by changing M2 Divider value) and set VDD2 Voltage for OPP100. This is increasing the period duration of one L3 clock cycle and reducing the timing duration of the critical path signal which will now fit to one L3 clock cycle. o In case of CORE is at OPP100 (L3=200MHz, VDD2=1.1375V): Lower the frequency to 100MHz. Keep the voltage as it is (1.1375V). o In case of CORE is at OPP50 (L3=100MHz, VDD2=0.93V): Keep the frequency as it is (100MHz). Increase the voltage to 1.1375V. 2.Enable DPLL3 Automatic mode. This will ensure proper transition to RETENTION or OFF mode. After CORE Voltage Domain Wakeup Transition from RETENTION or OFF mode: 1.Disable DPLL3 Automatic mode. 2.Restore previous DPLL3 M2 Frequency and CORE Voltage values. Also OSWR should not be attempted if DPLL3 has locked. This should be done as part of OSWR patch series. Patch tested on 3430SDP and 3630 ZOOM3. Do you have a more accurate description of the bug? What is the defect ID? Defect Id is i581. The subject is about DPLL3 lock issue, and the description is all about the transition to CORE RET or OFF and playing with voltage... and why OSWR is affected as well? I'm a little bit confused by that... Is this bug dependent of the target power state? What about INACTIVE? The root cause of the issue is that SDRC IDLEREQ is deasserted before DPLL3 has locked. Because of this DLL may/may not lock based on Process Voltage Temperature conditions. The bug can occur when DPLL3 automatic transition is enabled. So DPLL3 automatic transition is disabled by default and it is enabled only when system is entering ret/off state (to facilitate voltage scaling). So when system is entering ret/off state, WA is applied (since DPLL3 autoidle is enabled, we can possibly hit the issue; hence the WA) Thanks, but that still not explain why this WA is considered only for device transition to RET or OFF. The DPLL3 can got to idle as soon as the CORE is INACTIVE. How this case is handled? DPLL3 auto idle is disabled when Core is in ON or INACTIVE state. So DPLL3 cannot goto idle state. We enable DPPL3 auto idle only when Core is about to enter RET or OFF state (otherwise VDD2 will not be able to scale the voltage down). Why is it depend of the voltage? Am I missing something? After checking the errata, it looks like there is no further explanation than this one: These cases cannot be executed if only Power Domain transition is targeted which does not explain anything:-( I'll check that with Hayati. Apparently by increasing
Re: [PATCH V2] OMAP3: PM: Workaround for DPLL3 Lock issue
On 5/19/2010 4:37 PM, Sripathy, Vishwanath wrote: Hi Benoit, -Original Message- From: Cousson, Benoit Sent: Wednesday, May 19, 2010 8:00 PM To: Sripathy, Vishwanath Cc: Gulati, Shweta; linux-omap@vger.kernel.org Subject: Re: [PATCH V2] OMAP3: PM: Workaround for DPLL3 Lock issue On 5/19/2010 3:50 PM, Sripathy, Vishwanath wrote: Hi Benoit, -Original Message- From: Cousson, Benoit Sent: Wednesday, May 19, 2010 5:28 PM To: Gulati, Shweta Cc: linux-omap@vger.kernel.org; Sripathy, Vishwanath Subject: Re: [PATCH V2] OMAP3: PM: Workaround for DPLL3 Lock issue Hi Vishwa, On 5/13/2010 12:12 PM, shweta gulati wrote: From: Vishwanath Sripathyvishwanath...@ti.com OMAP3430/3630 has a Silicon bug because of which SDRC is released from IDLE even before Core DPLL has locked. This leads to undefined behaviour of SDRC DLL. This patch has workaround for the same. Description of WA for 3430: Initialization: Disable DPLL3 automatic mode by default. Issue will not be faced as DPLL3 is always locked. Before CORE Voltage Domain (VDD2) Sleep Transition to RETENTION or OFF mode: 1. Reduce DPLL3 M2 Frequency to get L3 running at OPP2 Frequency (by changing M2 Divider value). This is increasing the period duration of one L3 clock cycle. o In case of CORE is at OPP3 (166...@1.15v): Lower the frequency to 83MHz. o In case of CORE is at OPP2 (83...@1.05v): Keep the frequency as it is (83MHz). 2. Increase CORE Voltage to 1.2V. This is reducing the timing duration of the critical path signal which will now fit to one L3 clock cycle. 3. Enable DPLL3 Automatic mode. This will ensure proper transition to RETENTION or OFF mode. After CORE Voltage Domain Wakeup Transition from RETENTION or OFF mode: 1. Disable DPLL3 Automatic mode. 2. Restore previous DPLL3 M2 Frequency and CORE Voltage values. Description of WA for 3630: Initialization: Disable DPLL3 automatic mode by default. Issue will not be faced as DPLL3 is always locked. Before CORE Voltage Domain(VDD2) Sleep Transition to RETENTION or OFF mode: 1. Reduce DPLL3 M2 Frequency to get L3 running at OPP50 Frequency (by changing M2 Divider value) and set VDD2 Voltage for OPP100. This is increasing the period duration of one L3 clock cycle and reducing the timing duration of the critical path signal which will now fit to one L3 clock cycle. o In case of CORE is at OPP100 (L3=200MHz, VDD2=1.1375V): Lower the frequency to 100MHz. Keep the voltage as it is (1.1375V). o In case of CORE is at OPP50 (L3=100MHz, VDD2=0.93V): Keep the frequency as it is (100MHz). Increase the voltage to 1.1375V. 2. Enable DPLL3 Automatic mode. This will ensure proper transition to RETENTION or OFF mode. After CORE Voltage Domain Wakeup Transition from RETENTION or OFF mode: 1. Disable DPLL3 Automatic mode. 2. Restore previous DPLL3 M2 Frequency and CORE Voltage values. Also OSWR should not be attempted if DPLL3 has locked. This should be done as part of OSWR patch series. Patch tested on 3430SDP and 3630 ZOOM3. Do you have a more accurate description of the bug? What is the defect ID? Defect Id is i581. The subject is about DPLL3 lock issue, and the description is all about the transition to CORE RET or OFF and playing with voltage... and why OSWR is affected as well? I'm a little bit confused by that... Is this bug dependent of the target power state? What about INACTIVE? The root cause of the issue is that SDRC IDLEREQ is deasserted before DPLL3 has locked. Because of this DLL may/may not lock based on Process Voltage Temperature conditions. The bug can occur when DPLL3 automatic transition is enabled. So DPLL3 automatic transition is disabled by default and it is enabled only when system is entering ret/off state (to facilitate voltage scaling). So when system is entering ret/off state, WA is applied (since DPLL3 autoidle is enabled, we can possibly hit the issue; hence the WA) Thanks, but that still not explain why this WA is considered only for device transition to RET or OFF. The DPLL3 can got to idle as soon as the CORE is INACTIVE. How this case is handled? DPLL3 auto idle is disabled when Core is in ON or INACTIVE state. So DPLL3 cannot goto idle state. We enable DPPL3 auto idle only when Core is about to enter RET or OFF state (otherwise VDD2 will not be able to scale the voltage down). Why did you prevent that mode for INACTIVE? If I remember well, during the early measurement we did on 3430, the DPLL consumption in locked mode is around 5mw, so you can save a good amount of power for very low load use cases. Did you try to enable that in CPUIdle to check the power saving you can achieve with that mode? Benoit -- To unsubscribe from
RE: [PATCH V2] OMAP3: PM: Workaround for DPLL3 Lock issue
Kevin,
-Original Message-
From: Kevin Hilman [mailto:khil...@deeprootsystems.com]
Sent: Friday, May 14, 2010 11:28 PM
To: Gulati, Shweta
Cc: linux-omap@vger.kernel.org; Sripathy, Vishwanath
Subject: Re: [PATCH V2] OMAP3: PM: Workaround for DPLL3 Lock issue
shweta gulati shweta.gul...@ti.com writes:
From: Vishwanath Sripathy vishwanath...@ti.com
OMAP3430/3630 has a Silicon bug because of which SDRC is
released from IDLE even before Core DPLL has locked. This leads
to undefined behaviour of SDRC DLL.
This patch has workaround for the same.
Description of WA for 3430:
Initialization:
Disable DPLL3 automatic mode by default. Issue will not be faced as
DPLL3
is always locked.
Before CORE Voltage Domain (VDD2) Sleep Transition to RETENTION or OFF mode:
1. Reduce DPLL3 M2 Frequency to get L3 running at OPP2 Frequency
(by changing M2 Divider value). This is increasing the period duration
of
one L3 clock cycle.
o In case of CORE is at OPP3 (166...@1.15v):
Lower the frequency to 83MHz.
o In case of CORE is at OPP2 (83...@1.05v):
Keep the frequency as it is (83MHz).
2. Increase CORE Voltage to 1.2V. This is reducing the timing duration of
the
critical path signal which will now fit to one L3 clock cycle.
3. Enable DPLL3 Automatic mode. This will ensure proper transition to
RETENTION or OFF mode.
After CORE Voltage Domain Wakeup Transition from RETENTION or OFF mode:
1. Disable DPLL3 Automatic mode.
2. Restore previous DPLL3 M2 Frequency and CORE Voltage values.
Description of WA for 3630:
Initialization:
Disable DPLL3 automatic mode by default. Issue will not be faced as
DPLL3 is
always locked.
Before CORE Voltage Domain(VDD2) Sleep Transition to RETENTION or OFF mode:
1. Reduce DPLL3 M2 Frequency to get L3 running at OPP50 Frequency
(by changing M2 Divider value) and set VDD2 Voltage for OPP100.
This is increasing the period duration of one L3 clock cycle and
reducing
the timing duration of the critical path signal which will now fit to
one
L3 clock cycle.
o In case of CORE is at OPP100 (L3=200MHz, VDD2=1.1375V):
Lower the frequency to 100MHz.
Keep the voltage as it is (1.1375V).
o In case of CORE is at OPP50 (L3=100MHz, VDD2=0.93V):
Keep the frequency as it is (100MHz).
Increase the voltage to 1.1375V.
2. Enable DPLL3 Automatic mode. This will ensure proper transition to
RETENTION or OFF mode.
After CORE Voltage Domain Wakeup Transition from RETENTION or OFF mode:
1. Disable DPLL3 Automatic mode.
2. Restore previous DPLL3 M2 Frequency and CORE Voltage values.
Also OSWR should not be attempted if DPLL3 has locked. This should be done
as
part of OSWR patch series.
Patch tested on 3430SDP and 3630 ZOOM3.
Signed-off-by: Vishwanath Sripathy vishwanath...@ti.com
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
---
This patch appears to depend on Thara's SR series. Please state
dependencies here.
OK
Index: linux-omap-pm/arch/arm/mach-omap2/pm.h
=
==
--- linux-omap-pm.orig/arch/arm/mach-omap2/pm.h
+++ linux-omap-pm/arch/arm/mach-omap2/pm.h
@@ -60,6 +60,10 @@ struct prm_setup_vc {
extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int
state);
+extern int program_vdd2_opp_3430(void);
+extern int reprogram_vdd2_opp_3430(int restore);
+extern int program_vdd2_opp_3630(void);
+extern int reprogram_vdd2_opp_3630(int restore);
extern u32 wakeup_timer_seconds;
extern struct omap_dm_timer *gptimer_wakeup;
Index: linux-omap-pm/arch/arm/mach-omap2/pm34xx.c
=
==
--- linux-omap-pm.orig/arch/arm/mach-omap2/pm34xx.c
+++ linux-omap-pm/arch/arm/mach-omap2/pm34xx.c
@@ -56,6 +56,7 @@
#include sdrc.h
#include omap3-opp.h
+
stray whitespace change
#ifdef CONFIG_SUSPEND
static suspend_state_t suspend_state = PM_SUSPEND_ON;
static inline bool is_suspending(void)
@@ -363,6 +364,8 @@ void omap_sram_idle(void)
u32 sdrc_pwr = 0;
int per_state_modified = 0;
unsigned int start =0, end = 0;
+ u32 fclk_status = 0;
+ int restore = 1;
if (!_omap_sram_idle)
return;
@@ -415,15 +418,6 @@ void omap_sram_idle(void)
if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON)
omap2_clkdm_deny_idle(mpu_pwrdm-pwrdm_clkdms[0]);
- /*
-* Disable smartreflex before entering WFI.
-* Only needed if we are going to enter retention or off.
-*/
- if (mpu_next_state = PWRDM_POWER_RET)
- omap_smartreflex_disable(VDD1, 1
Re: [PATCH V2] OMAP3: PM: Workaround for DPLL3 Lock issue
Sripathy, Vishwanath vishwanath...@ti.com writes: All that being said, why is the voltage level being programmed here? It seems to me that all of this errata handling should be self-contained in the voltage layer. I am not sure if entire errata can be contained in voltage layer. This is because we are performing DVFS operation in CPU Idle path which involves both Frequency and Voltage scaling. So currently this has been done in resource34xx.c where DVFS is implemented. What I mean is that there seems to be no good reason to be calling these from pm34xx.c, they should be called where voltage scaling is done. Kevin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V2] OMAP3: PM: Workaround for DPLL3 Lock issue
shweta gulati shweta.gul...@ti.com writes:
From: Vishwanath Sripathy vishwanath...@ti.com
OMAP3430/3630 has a Silicon bug because of which SDRC is
released from IDLE even before Core DPLL has locked. This leads
to undefined behaviour of SDRC DLL.
This patch has workaround for the same.
Description of WA for 3430:
Initialization:
Disable DPLL3 automatic mode by default. Issue will not be faced as
DPLL3
is always locked.
Before CORE Voltage Domain (VDD2) Sleep Transition to RETENTION or OFF mode:
1.Reduce DPLL3 M2 Frequency to get L3 running at OPP2 Frequency
(by changing M2 Divider value). This is increasing the period duration
of
one L3 clock cycle.
o In case of CORE is at OPP3 (166...@1.15v):
Lower the frequency to 83MHz.
o In case of CORE is at OPP2 (83...@1.05v):
Keep the frequency as it is (83MHz).
2.Increase CORE Voltage to 1.2V. This is reducing the timing duration of
the
critical path signal which will now fit to one L3 clock cycle.
3.Enable DPLL3 Automatic mode. This will ensure proper transition to
RETENTION or OFF mode.
After CORE Voltage Domain Wakeup Transition from RETENTION or OFF mode:
1.Disable DPLL3 Automatic mode.
2.Restore previous DPLL3 M2 Frequency and CORE Voltage values.
Description of WA for 3630:
Initialization:
Disable DPLL3 automatic mode by default. Issue will not be faced as
DPLL3 is always locked.
Before CORE Voltage Domain(VDD2) Sleep Transition to RETENTION or OFF mode:
1.Reduce DPLL3 M2 Frequency to get L3 running at OPP50 Frequency
(by changing M2 Divider value) and set VDD2 Voltage for OPP100.
This is increasing the period duration of one L3 clock cycle and
reducing
the timing duration of the critical path signal which will now fit to
one
L3 clock cycle.
o In case of CORE is at OPP100 (L3=200MHz, VDD2=1.1375V):
Lower the frequency to 100MHz.
Keep the voltage as it is (1.1375V).
o In case of CORE is at OPP50 (L3=100MHz, VDD2=0.93V):
Keep the frequency as it is (100MHz).
Increase the voltage to 1.1375V.
2.Enable DPLL3 Automatic mode. This will ensure proper transition to
RETENTION or OFF mode.
After CORE Voltage Domain Wakeup Transition from RETENTION or OFF mode:
1.Disable DPLL3 Automatic mode.
2.Restore previous DPLL3 M2 Frequency and CORE Voltage values.
Also OSWR should not be attempted if DPLL3 has locked. This should be done as
part of OSWR patch series.
Patch tested on 3430SDP and 3630 ZOOM3.
Signed-off-by: Vishwanath Sripathy vishwanath...@ti.com
Signed-off-by: Shweta Gulati shweta.gul...@ti.com
---
This patch appears to depend on Thara's SR series. Please state
dependencies here.
Index: linux-omap-pm/arch/arm/mach-omap2/pm.h
===
--- linux-omap-pm.orig/arch/arm/mach-omap2/pm.h
+++ linux-omap-pm/arch/arm/mach-omap2/pm.h
@@ -60,6 +60,10 @@ struct prm_setup_vc {
extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
+extern int program_vdd2_opp_3430(void);
+extern int reprogram_vdd2_opp_3430(int restore);
+extern int program_vdd2_opp_3630(void);
+extern int reprogram_vdd2_opp_3630(int restore);
extern u32 wakeup_timer_seconds;
extern struct omap_dm_timer *gptimer_wakeup;
Index: linux-omap-pm/arch/arm/mach-omap2/pm34xx.c
===
--- linux-omap-pm.orig/arch/arm/mach-omap2/pm34xx.c
+++ linux-omap-pm/arch/arm/mach-omap2/pm34xx.c
@@ -56,6 +56,7 @@
#include sdrc.h
#include omap3-opp.h
+
stray whitespace change
#ifdef CONFIG_SUSPEND
static suspend_state_t suspend_state = PM_SUSPEND_ON;
static inline bool is_suspending(void)
@@ -363,6 +364,8 @@ void omap_sram_idle(void)
u32 sdrc_pwr = 0;
int per_state_modified = 0;
unsigned int start =0, end = 0;
+ u32 fclk_status = 0;
+ int restore = 1;
if (!_omap_sram_idle)
return;
@@ -415,15 +418,6 @@ void omap_sram_idle(void)
if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON)
omap2_clkdm_deny_idle(mpu_pwrdm-pwrdm_clkdms[0]);
- /*
- * Disable smartreflex before entering WFI.
- * Only needed if we are going to enter retention or off.
- */
- if (mpu_next_state = PWRDM_POWER_RET)
- omap_smartreflex_disable(VDD1, 1);
- if (core_next_state = PWRDM_POWER_RET)
- omap_smartreflex_disable(VDD2, 1);
-
/* CORE */
if (core_next_state PWRDM_POWER_ON) {
omap_uart_prepare_idle(0);
@@ -447,6 +441,31 @@ void omap_sram_idle(void)
prm_set_mod_reg_bits(OMAP3430_EN_IO,
