RE: [PATCHV4] OMAP3: SDRC : Errata 1.176 Fix - Accesses to DDR stall in SDRC after a Warm-reset
Vishwa, On Wed, 22 Sep 2010, Sripathy, Vishwanath wrote: -Original Message- From: Paul Walmsley [mailto:p...@pwsan.com] Sent: Wednesday, September 22, 2010 6:37 AM To: Sripathy, Vishwanath Cc: Reddy, Teerth; linux-omap@vger.kernel.org Subject: RE: [PATCHV4] OMAP3: SDRC : Errata 1.176 Fix - Accesses to DDR stall in SDRC after a Warm-reset Hello Vishwa, Thanks for the info. a few quick questions: On Thu, 16 Sep 2010, Sripathy, Vishwanath wrote: -Original Message- From: Paul Walmsley [mailto:p...@pwsan.com] Sent: Thursday, September 16, 2010 3:05 AM On Tue, 25 May 2010, Reddy, Teerth wrote: -Original Message- From: Paul Walmsley [mailto:p...@pwsan.com] Sent: Wednesday, May 19, 2010 6:03 AM To: Reddy, Teerth On Fri, 23 Apr 2010, Reddy, Teerth wrote: From: Teerth Reddy tee...@ti.com This patch has the workaround for errata 1.176. What's the current status of this patch? Still waiting for an updated version. We have realized that this errata is not applicable if reset is triggered via dpll3 reset. The rootcasuse of the issues was that incase of warm reset, SDRC is not sensitive to the warm reset, but the interconect is reset on the fly, thus causing a misalignment between SDRC logic, interconect logic and DDR memory state. Hence the workaround was proposed. However, incase of dpll3 reset, sdrc also gets reset. In omap_prcm_arch_reset, system reset is triggered via dpll3 reset, so this WA is not applicable. 1. So by warm reset, are you referring to the software warm reset triggered by GLOBAL_SW_RST, or by another mechanism? Yes, warm reset by means of GLOBAL_SW_RST. 2. If GLOBAL_SW_RST, what do you think about adding a brief comment in the code warning people not to use GLOBAL_SW_RST unless they implement the Errata 1.176 sequence? Yes, a note can be added. I will send a patch with this comment. Any progress on this? - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCHV4] OMAP3: SDRC : Errata 1.176 Fix - Accesses to DDR stall in SDRC after a Warm-reset
Hello Vishwa, Thanks for the info. a few quick questions: On Thu, 16 Sep 2010, Sripathy, Vishwanath wrote: -Original Message- From: Paul Walmsley [mailto:p...@pwsan.com] Sent: Thursday, September 16, 2010 3:05 AM On Tue, 25 May 2010, Reddy, Teerth wrote: -Original Message- From: Paul Walmsley [mailto:p...@pwsan.com] Sent: Wednesday, May 19, 2010 6:03 AM To: Reddy, Teerth On Fri, 23 Apr 2010, Reddy, Teerth wrote: From: Teerth Reddy tee...@ti.com This patch has the workaround for errata 1.176. What's the current status of this patch? Still waiting for an updated version. We have realized that this errata is not applicable if reset is triggered via dpll3 reset. The rootcasuse of the issues was that incase of warm reset, SDRC is not sensitive to the warm reset, but the interconect is reset on the fly, thus causing a misalignment between SDRC logic, interconect logic and DDR memory state. Hence the workaround was proposed. However, incase of dpll3 reset, sdrc also gets reset. In omap_prcm_arch_reset, system reset is triggered via dpll3 reset, so this WA is not applicable. 1. So by warm reset, are you referring to the software warm reset triggered by GLOBAL_SW_RST, or by another mechanism? 2. If GLOBAL_SW_RST, what do you think about adding a brief comment in the code warning people not to use GLOBAL_SW_RST unless they implement the Errata 1.176 sequence? - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCHV4] OMAP3: SDRC : Errata 1.176 Fix - Accesses to DDR stall in SDRC after a Warm-reset
Hi Paul, -Original Message- From: Paul Walmsley [mailto:p...@pwsan.com] Sent: Wednesday, September 22, 2010 6:37 AM To: Sripathy, Vishwanath Cc: Reddy, Teerth; linux-omap@vger.kernel.org Subject: RE: [PATCHV4] OMAP3: SDRC : Errata 1.176 Fix - Accesses to DDR stall in SDRC after a Warm-reset Hello Vishwa, Thanks for the info. a few quick questions: On Thu, 16 Sep 2010, Sripathy, Vishwanath wrote: -Original Message- From: Paul Walmsley [mailto:p...@pwsan.com] Sent: Thursday, September 16, 2010 3:05 AM On Tue, 25 May 2010, Reddy, Teerth wrote: -Original Message- From: Paul Walmsley [mailto:p...@pwsan.com] Sent: Wednesday, May 19, 2010 6:03 AM To: Reddy, Teerth On Fri, 23 Apr 2010, Reddy, Teerth wrote: From: Teerth Reddy tee...@ti.com This patch has the workaround for errata 1.176. What's the current status of this patch? Still waiting for an updated version. We have realized that this errata is not applicable if reset is triggered via dpll3 reset. The rootcasuse of the issues was that incase of warm reset, SDRC is not sensitive to the warm reset, but the interconect is reset on the fly, thus causing a misalignment between SDRC logic, interconect logic and DDR memory state. Hence the workaround was proposed. However, incase of dpll3 reset, sdrc also gets reset. In omap_prcm_arch_reset, system reset is triggered via dpll3 reset, so this WA is not applicable. 1. So by warm reset, are you referring to the software warm reset triggered by GLOBAL_SW_RST, or by another mechanism? Yes, warm reset by means of GLOBAL_SW_RST. 2. If GLOBAL_SW_RST, what do you think about adding a brief comment in the code warning people not to use GLOBAL_SW_RST unless they implement the Errata 1.176 sequence? Yes, a note can be added. I will send a patch with this comment. Vishwa - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCHV4] OMAP3: SDRC : Errata 1.176 Fix - Accesses to DDR stall in SDRC after a Warm-reset
Teerth, Vishwa, On Tue, 25 May 2010, Reddy, Teerth wrote: -Original Message- From: Paul Walmsley [mailto:p...@pwsan.com] Sent: Wednesday, May 19, 2010 6:03 AM To: Reddy, Teerth Cc: linux-omap@vger.kernel.org; Sripathy, Vishwanath Subject: Re: [PATCHV4] OMAP3: SDRC : Errata 1.176 Fix - Accesses to DDR stall in SDRC after a Warm-reset On Fri, 23 Apr 2010, Reddy, Teerth wrote: From: Teerth Reddy tee...@ti.com This patch has the workaround for errata 1.176. What's the current status of this patch? Still waiting for an updated version. - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCHV4] OMAP3: SDRC : Errata 1.176 Fix - Accesses to DDR stall in SDRC after a Warm-reset
Paul, -Original Message- From: Paul Walmsley [mailto:p...@pwsan.com] Sent: Thursday, September 16, 2010 3:05 AM To: Reddy, Teerth Cc: linux-omap@vger.kernel.org; Sripathy, Vishwanath Subject: RE: [PATCHV4] OMAP3: SDRC : Errata 1.176 Fix - Accesses to DDR stall in SDRC after a Warm-reset Teerth, Vishwa, On Tue, 25 May 2010, Reddy, Teerth wrote: -Original Message- From: Paul Walmsley [mailto:p...@pwsan.com] Sent: Wednesday, May 19, 2010 6:03 AM To: Reddy, Teerth Cc: linux-omap@vger.kernel.org; Sripathy, Vishwanath Subject: Re: [PATCHV4] OMAP3: SDRC : Errata 1.176 Fix - Accesses to DDR stall in SDRC after a Warm-reset On Fri, 23 Apr 2010, Reddy, Teerth wrote: From: Teerth Reddy tee...@ti.com This patch has the workaround for errata 1.176. What's the current status of this patch? Still waiting for an updated version. We have realized that this errata is not applicable if reset is triggered via dpll3 reset. The rootcasuse of the issues was that incase of warm reset, SDRC is not sensitive to the warm reset, but the interconect is reset on the fly, thus causing a misalignment between SDRC logic, interconect logic and DDR memory state. Hence the workaround was proposed. However, incase of dpll3 reset, sdrc also gets reset. In omap_prcm_arch_reset, system reset is triggered via dpll3 reset, so this WA is not applicable. Regards Vishwa - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCHV4] OMAP3: SDRC : Errata 1.176 Fix - Accesses to DDR stall in SDRC after a Warm-reset
Paul, -Original Message- From: Paul Walmsley [mailto:p...@pwsan.com] Sent: Wednesday, May 19, 2010 6:03 AM To: Reddy, Teerth Cc: linux-omap@vger.kernel.org; Sripathy, Vishwanath Subject: Re: [PATCHV4] OMAP3: SDRC : Errata 1.176 Fix - Accesses to DDR stall in SDRC after a Warm-reset Hello Teerth, On Fri, 23 Apr 2010, Reddy, Teerth wrote: From: Teerth Reddy tee...@ti.com This patch has the workaround for errata 1.176. In some cases, user is not able to access DDR memory after warm-reset.This situation occurs while the warm-reset happens during a read access to DDR memory. In that particular conditions, DDR memory does not respond to a corrupted read command due to the warm reset occurence but SDRC is waiting for read completion.SDRC is not sensitive to the warm reset, but the interconect is reset on the fly, thus causing a misalignment between SDRC logic, interconect logic and DDR memory state. Root cause description: A corrupted read transaction is issued to a closed row: (address0, bank0) instead of the expected read access, violating protocol. Failure signature: Once the failure occurs and system has restarted, memory content is not accessible.SDRC registers can be accessed successfully, until 1st access to memory location is performed. After 1st access to memory is done, SDRC is stuck. WORKAROUND Steps to perform before a SW reset is trigged, if user needs to generate a SW reset and keep DDR memory content: 1. Enable self-refresh on idle request 2. Put SDRC in idle 3. Wait until SDRC goes to idle 4. Generate SW reset Steps to perform after warm reset occurs: If HW warm reset is the source, apply below steps before any accesses to SDRAM: 1. Reset SMS and SDRC 2. Re-initialize SMS, SDRC and memory This would need the u-boot/x-loader workaround changes as well for the reboot to work correctly. Thanks to Paul Walmsley p...@pwsan.com for suggesting usefull changes. Signed-off-by: Teerth Reddy tee...@ti.com This patch doesn't work on the BeagleBoard Rev C2 here. After running 'init 6' to reboot the system, the kernel hangs after: Rebooting... Restarting system. Could you please doublecheck this patch? This is not working on Zoom3 too. There is not much change with the rebase on latest LO. The previous version did work fine. Will debug to check what changes are causing this hang. This patch also adds a sparse warning - please fix that too, - Paul Regards Teerth -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHV4] OMAP3: SDRC : Errata 1.176 Fix - Accesses to DDR stall in SDRC after a Warm-reset
Hello Teerth, On Fri, 23 Apr 2010, Reddy, Teerth wrote: From: Teerth Reddy tee...@ti.com This patch has the workaround for errata 1.176. In some cases, user is not able to access DDR memory after warm-reset.This situation occurs while the warm-reset happens during a read access to DDR memory. In that particular conditions, DDR memory does not respond to a corrupted read command due to the warm reset occurence but SDRC is waiting for read completion.SDRC is not sensitive to the warm reset, but the interconect is reset on the fly, thus causing a misalignment between SDRC logic, interconect logic and DDR memory state. Root cause description: A corrupted read transaction is issued to a closed row: (address0, bank0) instead of the expected read access, violating protocol. Failure signature: Once the failure occurs and system has restarted, memory content is not accessible.SDRC registers can be accessed successfully, until 1st access to memory location is performed. After 1st access to memory is done, SDRC is stuck. WORKAROUND Steps to perform before a SW reset is trigged, if user needs to generate a SW reset and keep DDR memory content: 1. Enable self-refresh on idle request 2. Put SDRC in idle 3. Wait until SDRC goes to idle 4. Generate SW reset Steps to perform after warm reset occurs: If HW warm reset is the source, apply below steps before any accesses to SDRAM: 1. Reset SMS and SDRC 2. Re-initialize SMS, SDRC and memory This would need the u-boot/x-loader workaround changes as well for the reboot to work correctly. Thanks to Paul Walmsley p...@pwsan.com for suggesting usefull changes. Signed-off-by: Teerth Reddy tee...@ti.com This patch doesn't work on the BeagleBoard Rev C2 here. After running 'init 6' to reboot the system, the kernel hangs after: Rebooting... Restarting system. Could you please doublecheck this patch? This patch also adds a sparse warning - please fix that too, - Paul -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
