[RFC PATCH 1/2] usb: dwc3: ep0: preparation for implementing chained TRB
No functional change. Modified few things so that there are no
code duplication while implementing chained TRB.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/usb/dwc3/ep0.c | 23 ++-
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index 2ef3c8d..24b7925 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -779,7 +779,10 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
struct usb_request *ur;
struct dwc3_trb *trb;
struct dwc3_ep *ep0;
- u32 transferred;
+ unsignedtransfer_size = 0;
+ unsignedmaxp;
+ void*buf;
+ u32 transferred = 0;
u32 status;
u32 length;
u8 epnum;
@@ -808,16 +811,17 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
}
ur = r-request;
+ buf = ur-buf;
length = trb-size DWC3_TRB_SIZE_MASK;
- if (dwc-ep0_bounced) {
- unsigned transfer_size = ur-length;
- unsigned maxp = ep0-endpoint.maxpacket;
+ maxp = ep0-endpoint.maxpacket;
- transfer_size += (maxp - (transfer_size % maxp));
- transferred = min_t(u32, ur-length,
- transfer_size - length);
+ if (dwc-ep0_bounced) {
+ transfer_size = roundup((ur-length - transfer_size),
+ maxp);
+ transferred = min_t(u32, ur-length - transferred,
+ transfer_size - length);
memcpy(ur-buf, dwc-ep0_bounce, transferred);
} else {
transferred = ur-length - length;
@@ -927,7 +931,7 @@ static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
DWC3_TRBCTL_CONTROL_DATA);
} else if (!IS_ALIGNED(req-request.length, dep-endpoint.maxpacket)
(dep-number == 0)) {
- u32 transfer_size;
+ u32 transfer_size = 0;
u32 maxpacket;
ret = usb_gadget_map_request(dwc-gadget, req-request,
@@ -940,7 +944,8 @@ static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
WARN_ON(req-request.length DWC3_EP0_BOUNCE_SIZE);
maxpacket = dep-endpoint.maxpacket;
- transfer_size = roundup(req-request.length, maxpacket);
+ transfer_size = roundup((req-request.length - transfer_size),
+ maxpacket);
dwc-ep0_bounced = true;
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC PATCH 2/2] usb: dwc3: Add chained TRB support for ep0
dwc3 can do only max packet aligned transfers. So in case request length
is not max packet aligned and is bigger than DWC3_EP0_BOUNCE_SIZE
two chained TRBs is required to handle the transfer.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
*) Did eumeration testing with g_zero in kernel
*) Similar patch was added in u-boot. With DFU, was able to create a scenario
where the request length is not max packet aligned and is bigger than
DWC3_EP0_BOUNCE_SIZE (512 bytes). In that case, 2 chained TRBs will be used.
drivers/usb/dwc3/ep0.c| 65 +
drivers/usb/dwc3/gadget.c |2 +-
2 files changed, 49 insertions(+), 18 deletions(-)
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index 24b7925..3b728b8 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -56,7 +56,7 @@ static const char *dwc3_ep0_state_string(enum dwc3_ep0_state
state)
}
static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
- u32 len, u32 type)
+ u32 len, u32 type, unsigned chain)
{
struct dwc3_gadget_ep_cmd_params params;
struct dwc3_trb *trb;
@@ -70,7 +70,10 @@ static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum,
dma_addr_t buf_dma,
return 0;
}
- trb = dwc-ep0_trb;
+ trb = dwc-ep0_trb[dep-free_slot];
+
+ if (chain)
+ dep-free_slot++;
trb-bpl = lower_32_bits(buf_dma);
trb-bph = upper_32_bits(buf_dma);
@@ -78,10 +81,17 @@ static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum,
dma_addr_t buf_dma,
trb-ctrl = type;
trb-ctrl |= (DWC3_TRB_CTRL_HWO
- | DWC3_TRB_CTRL_LST
- | DWC3_TRB_CTRL_IOC
| DWC3_TRB_CTRL_ISP_IMI);
+ if (chain)
+ trb-ctrl |= DWC3_TRB_CTRL_CHN;
+ else
+ trb-ctrl |= (DWC3_TRB_CTRL_IOC
+ | DWC3_TRB_CTRL_LST);
+
+ if (chain)
+ return 0;
+
memset(params, 0, sizeof(params));
params.param0 = upper_32_bits(dwc-ep0_trb_addr);
params.param1 = lower_32_bits(dwc-ep0_trb_addr);
@@ -302,7 +312,7 @@ void dwc3_ep0_out_start(struct dwc3 *dwc)
int ret;
ret = dwc3_ep0_start_trans(dwc, 0, dwc-ctrl_req_addr, 8,
- DWC3_TRBCTL_CONTROL_SETUP);
+ DWC3_TRBCTL_CONTROL_SETUP, false);
WARN_ON(ret 0);
}
@@ -817,6 +827,22 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
maxp = ep0-endpoint.maxpacket;
+ /* Handle the first TRB before handling the bounce buffer if the request
+* length is greater than the bounce buffer size
+*/
+ if (!IS_ALIGNED(ur-length, maxp)
+ ur-length DWC3_EP0_BOUNCE_SIZE) {
+ transfer_size = (ur-length / maxp) * maxp;
+ transferred = transfer_size - length;
+ buf = (u8 *)buf + transferred;
+ ur-actual += transferred;
+
+ trb++;
+ length = trb-size DWC3_TRB_SIZE_MASK;
+
+ ep0-free_slot = 0;
+ }
+
if (dwc-ep0_bounced) {
transfer_size = roundup((ur-length - transfer_size),
maxp);
@@ -844,7 +870,7 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
ret = dwc3_ep0_start_trans(dwc, epnum,
dwc-ctrl_req_addr, 0,
- DWC3_TRBCTL_CONTROL_DATA);
+ DWC3_TRBCTL_CONTROL_DATA, false);
WARN_ON(ret 0);
}
}
@@ -928,7 +954,7 @@ static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
if (req-request.length == 0) {
ret = dwc3_ep0_start_trans(dwc, dep-number,
dwc-ctrl_req_addr, 0,
- DWC3_TRBCTL_CONTROL_DATA);
+ DWC3_TRBCTL_CONTROL_DATA, false);
} else if (!IS_ALIGNED(req-request.length, dep-endpoint.maxpacket)
(dep-number == 0)) {
u32 transfer_size = 0;
@@ -941,22 +967,26 @@ static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
return;
}
- WARN_ON(req-request.length DWC3_EP0_BOUNCE_SIZE);
-
maxpacket = dep-endpoint.maxpacket;
+
+ if (req-request.length DWC3_EP0_BOUNCE_SIZE) {
+ transfer_size = (req-request.length / maxpacket) *
+ maxpacket;
+ ret = dwc3_ep0_start_trans(dwc, dep-number,
+ req-request.dma,
+ transfer_size
Re: [PATCH] ARM: dra7xx: hwmod: drop .modulemode from pcie1/2 hwmods
Hi,
On Tuesday 03 February 2015 09:21 PM, grygorii.stras...@linaro.org wrote:
From: Grygorii Strashko grygorii.stras...@linaro.org
Now DRA7xx pcie1/2 hwmods define PRCM configuration as following:
.clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
.rstctrl_offs = DRA7XX_RM_L3INIT_RSTCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
which is completely wrong because DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET
is clockdomain ctrl register and NOT module ctrl register.
And they have diffrent allowed values for bits[0,1]:
CLKTRCTRL MODULEMODE
0x0: NO_SLEEP 0x0: Module is disabled by SW.
0x1: SW_SLEEP 0x1: Module is managed automatically by HW
0x2: SW_WKUP 0x2: Module is explicitly enabled.
0x3: HW_AUTO 0x3: Reserved
As result, following message can be seen during suspend:
omap_hwmod: pcie1: _wait_target_disable failed
Fix it by removing .modulemode from pcie1/2 hwmods and, in that
way, prevent clockdomain ctrl register writing from HWMOD core.
Looks correct except for one change.
Acked-by: Kishon Vijay Abraham I kis...@ti.com
Signed-off-by: Grygorii Strashko grygorii.stras...@linaro.org
---
More over, it looks like pcie1/2 hwmods are fake and have to be dropped at
all.
The real HWMODs are PCIESS1/2.
Not sure I get this. You mean dra7xx_pcie1_hwmod should be replaced with
dra7xx_pciess1_hwmod? Or you mean an entire new hwmod is missing?
Please note we still have to enable the clock domain and main clock. We've also
purposefully omitted sysconfig from hwmod data since pcie reset
(RM_PCIESS_RSTCTRL) should be done before accessing the syconfig register and
the infrastructure for that is currently not present.
Unfortunatelly, not all information on PCIE is public, so
I could be wrong here.
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index ffd6604..a428b2d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1478,7 +1478,6 @@ static struct omap_hwmod dra7xx_pcie1_hwmod = {
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
I think the entire .prcm can be removed here.
},
},
};
@@ -1492,7 +1491,6 @@ static struct omap_hwmod dra7xx_pcie2_hwmod = {
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
},
},
};
Thanks
Kishon
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: dra7xx: hwmod: drop .modulemode from pcie1/2 hwmods
+tero
Hi,
On Monday 09 February 2015 08:22 PM, grygorii.stras...@linaro.org wrote:
On 02/09/2015 09:24 PM, Kishon Vijay Abraham I wrote:
Hi,
On Monday 09 February 2015 03:58 PM, grygorii.stras...@linaro.org wrote:
Hi Kishon,
On 02/09/2015 04:50 PM, Kishon Vijay Abraham I wrote:
On Tuesday 03 February 2015 09:21 PM, grygorii.stras...@linaro.org
wrote:
From: Grygorii Strashko grygorii.stras...@linaro.org
Now DRA7xx pcie1/2 hwmods define PRCM configuration as following:
.clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
.rstctrl_offs = DRA7XX_RM_L3INIT_RSTCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
which is completely wrong because DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET
is clockdomain ctrl register and NOT module ctrl register.
And they have diffrent allowed values for bits[0,1]:
CLKTRCTRL MODULEMODE
0x0: NO_SLEEP 0x0: Module is disabled by SW.
0x1: SW_SLEEP 0x1: Module is managed automatically by HW
0x2: SW_WKUP 0x2: Module is explicitly enabled.
0x3: HW_AUTO 0x3: Reserved
As result, following message can be seen during suspend:
omap_hwmod: pcie1: _wait_target_disable failed
Fix it by removing .modulemode from pcie1/2 hwmods and, in that
way, prevent clockdomain ctrl register writing from HWMOD core.
Looks correct except for one change.
Acked-by: Kishon Vijay Abraham I kis...@ti.com
Signed-off-by: Grygorii Strashko grygorii.stras...@linaro.org
---
More over, it looks like pcie1/2 hwmods are fake and have to be
dropped at all.
The real HWMODs are PCIESS1/2.
Not sure I get this. You mean dra7xx_pcie1_hwmod should be
replaced with
dra7xx_pciess1_hwmod? Or you mean an entire new hwmod is missing?
Please note we still have to enable the clock domain and main clock.
We've also
purposefully omitted sysconfig from hwmod data since pcie reset
(RM_PCIESS_RSTCTRL) should be done before accessing the syconfig
register and
the infrastructure for that is currently not present.
What I'm trying to say is that now PM control data mixed between
pcieX and pcieX-phy hwmods.
After this patch pcieX hwmods will actually do nothing (I assume
that pciex-phy will be
enabled before pcieX), and probably can be removed if pcie_clkdm
could be attached to pcieX-phy hwmod
instead.
More over, now, pcie_clkdm is connected to pcieX hwmod while
MODULEMODE register is controlled
by pciex-phy hwmod, so when pciess is going to be enabled the
l3init_clkdm will be waken-up by
hwmode core and not pcie_clkdm - as I can remember this is not good
(we should alway wake-up clockdomain
and keep it in SWSUP mode while changing MODULEMODE and SYSC
registers).
static struct omap_hwmod dra7xx_pcie1_hwmod = {
.name= pcie1,
.class= dra7xx_pcie_hwmod_class,
.clkdm_name= pcie_clkdm,
.main_clk= l4_root_clk_div,
static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
.name= pcie1-phy,
.class= dra7xx_pcie_phy_hwmod_class,
.clkdm_name= l3init_clkdm,
.main_clk= l4_root_clk_div,
So, in my opinion, some rework may be needed here.
Am I right?
you are right. We should have a single hwmod like dra7xx_pciess1_hwmod
whose
clkdm should be pcie_clkdm and whose clkctrl_offs should be
DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET (for controlling MODULEMODE).
PCIE PHY
shouldn't have a hwmod entry at all.
Thanks
Kishon
Could this patch be applied any way? It fixes real issue for me.
A proper fix should look something like below IMO
Thanks
Kishon
From 1c177d37ac46885a4dc17bacec33071ac23c56da Mon Sep 17 00:00:00 2001
From: Kishon Vijay Abraham I kis...@ti.com
Date: Thu, 12 Feb 2015 11:55:08 +0530
Subject: [RFC PATCH] ARM: DRA7: hwmod_data: Fix hwmod data for pcie
Fixed hwmod data for pcie by having the correct module mode offset.
Previously this module mode offset was part of pcie PHY which was wrong.
Now this module mode offset was moved to pcie hwmod and removed the
hwmod data
for pcie phy. While at that renamed pcie_hwmod to pciess_hwmod in order
to match with the name given in TRM.
This helps to get rid of the following warning
omap_hwmod: pcie1: _wait_target_disable failed
[grygorii.stras...@linaro.org: Found the issue that actually caused
omap_hwmod: pcie1: _wait_target_disable failed]
Signed-off-by: Grygorii Strashko grygorii.stras...@linaro.org
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
this patch was created on 3.14 kernel after applying reset framework patches
required for testing PCIe. I can port this to mainline if this patch is
fine.
arch/arm/boot/dts/dra7.dtsi |2 -
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 107
+++--
2 files changed, 26 insertions(+), 83 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index a4b1337..d7a1ff9 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1364,7 +1364,6
[PATCH 1/2] ARM: DRA7: hwmod_data: Fix hwmod data for pcie
Fixed hwmod data for pcie by having the correct module mode offset.
Previously this module mode offset was part of pcie PHY which was wrong.
Now this module mode offset was moved to pcie hwmod and removed the hwmod data
for pcie phy. While at that renamed pcie_hwmod to pciess_hwmod in order
to match with the name given in TRM.
This helps to get rid of the following warning
omap_hwmod: pcie1: _wait_target_disable failed
[grygorii.stras...@linaro.org: Found the issue that actually caused
omap_hwmod: pcie1: _wait_target_disable failed]
Signed-off-by: Grygorii Strashko grygorii.stras...@linaro.org
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 103 +++--
1 file changed, 24 insertions(+), 79 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index e8692e7..16fe7a1 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1466,55 +1466,18 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
*
*/
-static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
+static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
.name = pcie,
};
/* pcie1 */
-static struct omap_hwmod dra7xx_pcie1_hwmod = {
+static struct omap_hwmod dra7xx_pciess1_hwmod = {
.name = pcie1,
- .class = dra7xx_pcie_hwmod_class,
+ .class = dra7xx_pciess_hwmod_class,
.clkdm_name = pcie_clkdm,
.main_clk = l4_root_clk_div,
.prcm = {
.omap4 = {
- .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* pcie2 */
-static struct omap_hwmod dra7xx_pcie2_hwmod = {
- .name = pcie2,
- .class = dra7xx_pcie_hwmod_class,
- .clkdm_name = pcie_clkdm,
- .main_clk = l4_root_clk_div,
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'PCIE PHY' class
- *
- */
-
-static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
- .name = pcie-phy,
-};
-
-/* pcie1 phy */
-static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
- .name = pcie1-phy,
- .class = dra7xx_pcie_phy_hwmod_class,
- .clkdm_name = l3init_clkdm,
- .main_clk = l4_root_clk_div,
- .prcm = {
- .omap4 = {
.clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
.context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
@@ -1522,11 +1485,11 @@ static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
},
};
-/* pcie2 phy */
-static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {
- .name = pcie2-phy,
- .class = dra7xx_pcie_phy_hwmod_class,
- .clkdm_name = l3init_clkdm,
+/* pcie2 */
+static struct omap_hwmod dra7xx_pciess2_hwmod = {
+ .name = pcie2,
+ .class = dra7xx_pciess_hwmod_class,
+ .clkdm_name = pcie_clkdm,
.main_clk = l4_root_clk_div,
.prcm = {
.omap4 = {
@@ -2877,50 +2840,34 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3
= {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l3_main_1 - pcie1 */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = {
+/* l3_main_1 - pciess1 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
.master = dra7xx_l3_main_1_hwmod,
- .slave = dra7xx_pcie1_hwmod,
+ .slave = dra7xx_pciess1_hwmod,
.clk= l3_iclk_div,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_cfg - pcie1 */
-static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
+/* l4_cfg - pciess1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
.master = dra7xx_l4_cfg_hwmod,
- .slave = dra7xx_pcie1_hwmod,
+ .slave = dra7xx_pciess1_hwmod,
.clk= l4_root_clk_div,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l3_main_1 - pcie2 */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = {
+/* l3_main_1 - pciess2 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
.master = dra7xx_l3_main_1_hwmod,
- .slave = dra7xx_pcie2_hwmod,
+ .slave = dra7xx_pciess2_hwmod,
.clk= l3_iclk_div,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* l4_cfg - pcie2 */
-static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
- .master = dra7xx_l4_cfg_hwmod
[PATCH 2/2] ARM: dts: dra7: remove ti,hwmod property from pcie phy
Now that we don't have hwmod entry for pcie PHY remove the
ti,hwmod property from PCIE PHY's
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi |2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 5827fed..18a904d 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -,7 +,6 @@
wkupclk, refclk,
div-clk, phy-div;
#phy-cells = 0;
- ti,hwmods = pcie1-phy;
};
pcie2_phy: pciephy@4a095000 {
@@ -1130,7 +1129,6 @@
wkupclk, refclk,
div-clk, phy-div;
#phy-cells = 0;
- ti,hwmods = pcie2-phy;
status = disabled;
};
};
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] phy: ti-pipe3: Disable clocks on system suspend
Hi Roger,
On Friday 19 December 2014 05:35 PM, Roger Quadros wrote:
On system suspend, the runtime_suspend() driver hook doesn't get
called and so the clocks are not disabled in the driver.
This causes the L3INIT_960M_GFCLK and L3INIT_480M_GFCLK to remain
active on the DRA7 platform while in system suspend.
Add suspend/resume hooks to the driver.
In case of pcie-phy, the runtime_suspend hook gets called after
This contradicts with the first line of your commit message. Is pcie-phy driver
is an exception?
Thanks
Kishon
the suspend hook so we introduce a flag phy-enabled to keep
track if our clocks are enabled or not to prevent multiple
enable/disables.
Move enabling/disabling clock code into helper functions.
Reported-by: Nishant Menon n...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/phy/phy-ti-pipe3.c | 99
+++---
1 file changed, 77 insertions(+), 22 deletions(-)
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index 1387b4d..e60ff14 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -28,6 +28,7 @@
#include linux/delay.h
#include linux/phy/omap_control_phy.h
#include linux/of_platform.h
+#include linux/spinlock.h
#define PLL_STATUS 0x0004
#define PLL_GO 0x0008
@@ -83,6 +84,8 @@ struct ti_pipe3 {
struct clk *div_clk;
struct pipe3_dpll_map *dpll_map;
u8 id;
+ bool enabled;
+ spinlock_t lock;/* serialize clock enable/disable */
};
static struct pipe3_dpll_map dpll_map_usb[] = {
@@ -303,6 +306,7 @@ static int ti_pipe3_probe(struct platform_device *pdev)
return -ENOMEM;
phy-dev= pdev-dev;
+ spin_lock_init(phy-lock);
if (!of_device_is_compatible(node, ti,phy-pipe3-pcie)) {
match = of_match_device(of_match_ptr(ti_pipe3_id_table),
@@ -425,24 +429,14 @@ static int ti_pipe3_remove(struct platform_device *pdev)
#ifdef CONFIG_PM
-static int ti_pipe3_runtime_suspend(struct device *dev)
+static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy)
{
- struct ti_pipe3 *phy = dev_get_drvdata(dev);
-
- if (!IS_ERR(phy-wkupclk))
- clk_disable_unprepare(phy-wkupclk);
- if (!IS_ERR(phy-refclk))
- clk_disable_unprepare(phy-refclk);
- if (!IS_ERR(phy-div_clk))
- clk_disable_unprepare(phy-div_clk);
-
- return 0;
-}
+ int ret = 0;
+ unsigned long flags;
-static int ti_pipe3_runtime_resume(struct device *dev)
-{
- u32 ret = 0;
- struct ti_pipe3 *phy = dev_get_drvdata(dev);
+ spin_lock_irqsave(phy-lock, flags);
+ if (phy-enabled)
+ goto err1;
if (!IS_ERR(phy-refclk)) {
ret = clk_prepare_enable(phy-refclk);
@@ -467,6 +461,9 @@ static int ti_pipe3_runtime_resume(struct device *dev)
goto err3;
}
}
+
+ phy-enabled = true;
+ spin_unlock_irqrestore(phy-lock, flags);
return 0;
err3:
@@ -478,19 +475,77 @@ err2:
clk_disable_unprepare(phy-refclk);
err1:
+ spin_unlock_irqrestore(phy-lock, flags);
+ return ret;
+}
+
+static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(phy-lock, flags);
+ if (!phy-enabled) {
+ spin_unlock_irqrestore(phy-lock, flags);
+ return;
+ }
+
+ if (!IS_ERR(phy-wkupclk))
+ clk_disable_unprepare(phy-wkupclk);
+ if (!IS_ERR(phy-refclk))
+ clk_disable_unprepare(phy-refclk);
+ if (!IS_ERR(phy-div_clk))
+ clk_disable_unprepare(phy-div_clk);
+ phy-enabled = false;
+ spin_unlock_irqrestore(phy-lock, flags);
+}
+
+static int ti_pipe3_runtime_suspend(struct device *dev)
+{
+ struct ti_pipe3 *phy = dev_get_drvdata(dev);
+
+ ti_pipe3_disable_clocks(phy);
+ return 0;
+}
+
+static int ti_pipe3_runtime_resume(struct device *dev)
+{
+ struct ti_pipe3 *phy = dev_get_drvdata(dev);
+ int ret = 0;
+
+ ret = ti_pipe3_enable_clocks(phy);
return ret;
}
+static int ti_pipe3_suspend(struct device *dev)
+{
+ struct ti_pipe3 *phy = dev_get_drvdata(dev);
+
+ ti_pipe3_disable_clocks(phy);
+ return 0;
+}
+
+static int ti_pipe3_resume(struct device *dev)
+{
+ struct ti_pipe3 *phy = dev_get_drvdata(dev);
+ int ret;
+
+ ret = ti_pipe3_enable_clocks(phy);
+ if (ret)
+ return ret;
+
+ pm_runtime_disable(dev);
+ pm_runtime_set_active(dev);
+ pm_runtime_enable(dev);
+ return 0;
+}
+#endif
+
static const struct dev_pm_ops ti_pipe3_pm_ops = {
SET_RUNTIME_PM_OPS(ti_pipe3_runtime_suspend,
ti_pipe3_runtime_resume, NULL)
+
Re: [PATCH v2 2/2] phy: ti-pipe3: Fix SATA across suspend/resume
Hi Roger,
On Thursday 08 January 2015 04:47 PM, Roger Quadros wrote:
Failed test case: Boot without SATA drive connected. Suspend/resume
the board and then connect SATA drive. It fails to enumerate.
Due to Errata i783 SATA Lockup After SATA DPLL Unlock/Relock
we can't allow SATA DPLL to be in the unlocked state.
The SATA refclk (sata_ref_clk) is the source of the SATA_DPLL.
Till now this clock was controlled by the AHCI SATA driver and was being
shut off during system suspend (if the SATA drive was not already attached)
causing the SATA DPLL to be unlocked and so causing errata i783.
To prevent sata_ref_clk from being disabled, we move the control of
this clock from the SATA AHCI driver to the SATA PHY driver and prevent
it from being disabled.
This also fixes the issue of SATA not working on OMAP5/DRA7 when
AHCI platform driver is built as a module.
I feel the dt patches and the PHY patches can go separately. Can you split and
re-send?
Thanks
Kishon
Signed-off-by: Roger Quadros rog...@ti.com
---
v2: don't bail out for missing refclk on SATA phy to work with older broken
DTBs.
arch/arm/boot/dts/dra7.dtsi | 4 ++--
arch/arm/boot/dts/omap5.dtsi | 4 ++--
drivers/phy/phy-ti-pipe3.c | 57
+++-
3 files changed, 45 insertions(+), 20 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 22771bc..8d2a635 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1090,8 +1090,8 @@
0x4A096800 0x40; /* pll_ctrl */
reg-names = phy_rx, phy_tx, pll_ctrl;
ctrl-module = omap_control_sata;
- clocks = sys_clkin1;
- clock-names = sysclk;
+ clocks = sys_clkin1, sata_ref_clk;
+ clock-names = sysclk, refclk;
#phy-cells = 0;
};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index b321fdf..bb498e7 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -929,8 +929,8 @@
0x4A096800 0x40; /* pll_ctrl */
reg-names = phy_rx, phy_tx, pll_ctrl;
ctrl-module = omap_control_sata;
- clocks = sys_clkin;
- clock-names = sysclk;
+ clocks = sys_clkin, sata_ref_clk;
+ clock-names = sysclk, refclk;
#phy-cells = 0;
};
};
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index e60ff14..456dec2 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -85,6 +85,7 @@ struct ti_pipe3 {
struct pipe3_dpll_map *dpll_map;
u8 id;
bool enabled;
+ bool refclk_enabled;/* this flag is needed specifically for SATA */
spinlock_t lock;/* serialize clock enable/disable */
};
@@ -333,21 +334,24 @@ static int ti_pipe3_probe(struct platform_device *pdev)
}
}
+ phy-refclk = devm_clk_get(phy-dev, refclk);
+ if (IS_ERR(phy-refclk)) {
+ dev_err(pdev-dev, unable to get refclk\n);
+ /* older DTBs have missing refclk in SATA PHY
+ * so don't bail out in case of SATA PHY.
+ */
+ if (!of_device_is_compatible(node, ti,phy-pipe3-sata))
+ return PTR_ERR(phy-refclk);
+ }
+
if (!of_device_is_compatible(node, ti,phy-pipe3-sata)) {
phy-wkupclk = devm_clk_get(phy-dev, wkupclk);
if (IS_ERR(phy-wkupclk)) {
dev_err(pdev-dev, unable to get wkupclk\n);
return PTR_ERR(phy-wkupclk);
}
-
- phy-refclk = devm_clk_get(phy-dev, refclk);
- if (IS_ERR(phy-refclk)) {
- dev_err(pdev-dev, unable to get refclk\n);
- return PTR_ERR(phy-refclk);
- }
} else {
phy-wkupclk = ERR_PTR(-ENODEV);
- phy-refclk = ERR_PTR(-ENODEV);
}
if (of_device_is_compatible(node, ti,phy-pipe3-pcie)) {
@@ -428,6 +432,29 @@ static int ti_pipe3_remove(struct platform_device *pdev)
}
#ifdef CONFIG_PM
+static int ti_pipe3_enable_refclk(struct ti_pipe3 *phy)
+{
+ if (!IS_ERR(phy-refclk) !phy-refclk_enabled) {
+ int ret;
+
+ ret = clk_prepare_enable(phy-refclk);
+ if (ret) {
+ dev_err(phy-dev, Failed to enable refclk %d\n, ret);
+ return ret;
+ }
+ phy-refclk_enabled = true;
+ }
+
+
Re: [PATCH] ARM: dra7xx: hwmod: drop .modulemode from pcie1/2 hwmods
Hi Paul,
On Thursday 12 February 2015 10:15 PM, Paul Walmsley wrote:
On Thu, 12 Feb 2015, Paul Walmsley wrote:
On Fri, 13 Feb 2015, grygorii.stras...@linaro.org wrote:
On 02/12/2015 11:08 PM, Paul Walmsley wrote:
Thanks guys.
On Thu, 12 Feb 2015, grygorii.stras...@linaro.org wrote:
Looks good for me and seems working.
Grygorii, can I add your Acked-by?
- Paul
There is my Signed-off-by :)
OK thanks, queued for v3.20-rc.
Actually, could you guys test the updated patch? It had to be changed to
apply on mainline and I don't have a DRA7xx board to test.
We don't use resets used here in mainline. I'll send an updated patch for
mainline.
Thanks
Kishon
- Paul
From 0f9a1ee083a7adbb2c867d5c8d25d7e5fcb38b07 Mon Sep 17 00:00:00 2001
From: Kishon Vijay Abraham I kis...@ti.com
Date: Thu, 12 Feb 2015 09:29:31 -0700
Subject: [PATCH] ARM: DRA7: hwmod_data: Fix hwmod data for pcie
Fixed hwmod data for pcie by having the correct module mode offset.
Previously this module mode offset was part of pcie PHY which was wrong.
Now this module mode offset was moved to pcie hwmod and removed the
hwmod data
for pcie phy. While at that renamed pcie_hwmod to pciess_hwmod in order
to match with the name given in TRM.
This helps to get rid of the following warning
omap_hwmod: pcie1: _wait_target_disable failed
[grygorii.stras...@linaro.org: Found the issue that actually caused
omap_hwmod: pcie1: _wait_target_disable failed]
Signed-off-by: Grygorii Strashko grygorii.stras...@linaro.org
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
[p...@pwsan.com: updated to apply on mainline]
---
arch/arm/boot/dts/dra7.dtsi | 2 -
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 111 ++
2 files changed, 35 insertions(+), 78 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 5827fedafd43..18a904db32bb 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -,7 +,6 @@
wkupclk, refclk,
div-clk, phy-div;
#phy-cells = 0;
- ti,hwmods = pcie1-phy;
};
pcie2_phy: pciephy@4a095000 {
@@ -1130,7 +1129,6 @@
wkupclk, refclk,
div-clk, phy-div;
#phy-cells = 0;
- ti,hwmods = pcie2-phy;
status = disabled;
};
};
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index e8692e7675b8..6a74a7ea8c95 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1466,29 +1466,43 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
*
*/
-static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
+static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
.name = pcie,
};
/* pcie1 */
-static struct omap_hwmod dra7xx_pcie1_hwmod = {
+static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
+ { .name = pcie, .rst_shift = 0 },
+};
+
+static struct omap_hwmod dra7xx_pciess1_hwmod = {
.name = pcie1,
- .class = dra7xx_pcie_hwmod_class,
+ .class = dra7xx_pciess_hwmod_class,
.clkdm_name = pcie_clkdm,
.main_clk = l4_root_clk_div,
+ .rst_lines = dra7xx_pciess1_resets,
+ .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets),
.prcm = {
.omap4 = {
- .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
+ .clkctrl_offs =
DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
+ .context_offs =
DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* pcie2 */
-static struct omap_hwmod dra7xx_pcie2_hwmod = {
+
+static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
+ { .name = pcie, .rst_shift = 1 },
+};
+
+static struct omap_hwmod dra7xx_pciess2_hwmod = {
.name = pcie2,
- .class = dra7xx_pcie_hwmod_class,
+ .class = dra7xx_pciess_hwmod_class,
.clkdm_name = pcie_clkdm,
+ .rst_lines = dra7xx_pciess2_resets,
+ .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets),
.main_clk = l4_root_clk_div,
.prcm = {
.omap4 = {
@@ -1498,44 +1512,7 @@ static struct omap_hwmod dra7xx_pcie2_hwmod = {
},
};
-/*
- * 'PCIE PHY' class
- *
- */
-static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
- .name = pcie-phy,
-};
-
-/* pcie1 phy */
-static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
- .name
Re: [PATCH] ARM: dra7xx: hwmod: drop .modulemode from pcie1/2 hwmods
Hi,
On Monday 09 February 2015 03:58 PM, grygorii.stras...@linaro.org wrote:
Hi Kishon,
On 02/09/2015 04:50 PM, Kishon Vijay Abraham I wrote:
On Tuesday 03 February 2015 09:21 PM, grygorii.stras...@linaro.org wrote:
From: Grygorii Strashko grygorii.stras...@linaro.org
Now DRA7xx pcie1/2 hwmods define PRCM configuration as following:
.clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
.rstctrl_offs = DRA7XX_RM_L3INIT_RSTCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
which is completely wrong because DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET
is clockdomain ctrl register and NOT module ctrl register.
And they have diffrent allowed values for bits[0,1]:
CLKTRCTRL MODULEMODE
0x0: NO_SLEEP 0x0: Module is disabled by SW.
0x1: SW_SLEEP 0x1: Module is managed automatically by HW
0x2: SW_WKUP 0x2: Module is explicitly enabled.
0x3: HW_AUTO 0x3: Reserved
As result, following message can be seen during suspend:
omap_hwmod: pcie1: _wait_target_disable failed
Fix it by removing .modulemode from pcie1/2 hwmods and, in that
way, prevent clockdomain ctrl register writing from HWMOD core.
Looks correct except for one change.
Acked-by: Kishon Vijay Abraham I kis...@ti.com
Signed-off-by: Grygorii Strashko grygorii.stras...@linaro.org
---
More over, it looks like pcie1/2 hwmods are fake and have to be dropped at
all.
The real HWMODs are PCIESS1/2.
Not sure I get this. You mean dra7xx_pcie1_hwmod should be replaced with
dra7xx_pciess1_hwmod? Or you mean an entire new hwmod is missing?
Please note we still have to enable the clock domain and main clock. We've
also
purposefully omitted sysconfig from hwmod data since pcie reset
(RM_PCIESS_RSTCTRL) should be done before accessing the syconfig register and
the infrastructure for that is currently not present.
What I'm trying to say is that now PM control data mixed between pcieX and
pcieX-phy hwmods.
After this patch pcieX hwmods will actually do nothing (I assume that
pciex-phy will be
enabled before pcieX), and probably can be removed if pcie_clkdm could be
attached to pcieX-phy hwmod
instead.
More over, now, pcie_clkdm is connected to pcieX hwmod while MODULEMODE
register is controlled
by pciex-phy hwmod, so when pciess is going to be enabled the
l3init_clkdm will be waken-up by
hwmode core and not pcie_clkdm - as I can remember this is not good (we
should alway wake-up clockdomain
and keep it in SWSUP mode while changing MODULEMODE and SYSC registers).
static struct omap_hwmod dra7xx_pcie1_hwmod = {
.name = pcie1,
.class = dra7xx_pcie_hwmod_class,
.clkdm_name = pcie_clkdm,
.main_clk = l4_root_clk_div,
static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
.name = pcie1-phy,
.class = dra7xx_pcie_phy_hwmod_class,
.clkdm_name = l3init_clkdm,
.main_clk = l4_root_clk_div,
So, in my opinion, some rework may be needed here.
Am I right?
you are right. We should have a single hwmod like dra7xx_pciess1_hwmod whose
clkdm should be pcie_clkdm and whose clkctrl_offs should be
DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET (for controlling MODULEMODE). PCIE PHY
shouldn't have a hwmod entry at all.
Thanks
Kishon
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] gpio: pcf857x: restore the initial line state of all pcf lines
Hi,
On Thursday 18 December 2014 07:41 PM, Nishanth Menon wrote:
On 12/18/2014 12:18 AM, Kishon Vijay Abraham I wrote:
On Tuesday 16 December 2014 02:20 AM, Nishanth Menon wrote:
On 12/12/2014 02:06 AM, Kishon Vijay Abraham I wrote:
The reset values for all the PCF lines are high and hence on shutdown
we should drive all the lines high in order to bring it to the reset state.
This is actually required since pcf doesn't have a reset line and even
after
warm reset (by invoking reboot in prompt) the pcf lines maintains it's
previous programmed state. This becomes a problem if the boards are
designed
to work with the default initial state.
DRA7XX_evm uses PCF8575 and one of the PCF output lines feeds to MMC/SD and
this line should be driven high in order for the MMC/SD to be detected.
This line is modelled as regulator and the hsmmc driver takes care of
enabling
and disabling it. In the case of 'reboot', during shutdown path as part of
it's
cleanup process the hsmmc driver disables this regulator. This makes MMC
boot
not functional.
Fixed it by driving high all the pcf lines.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/gpio/gpio-pcf857x.c |9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpio/gpio-pcf857x.c b/drivers/gpio/gpio-pcf857x.c
index 236708a..00b15b2 100644
--- a/drivers/gpio/gpio-pcf857x.c
+++ b/drivers/gpio/gpio-pcf857x.c
@@ -448,6 +448,14 @@ static int pcf857x_remove(struct i2c_client *client)
return status;
}
+static void pcf857x_shutdown(struct i2c_client *client)
+{
+ struct pcf857x *gpio = i2c_get_clientdata(client);
+
+ /* Drive all the I/O lines high */
+ gpio-write(gpio-client, BIT(gpio-chip.ngpio) - 1);
you might force a contention here - depending on System configuration.
example:
+---+
| |
| U1 | +--+ +---+
| +- | | |
+---+ | | | |
| Switch-+SoC|
+---+ | | | |
| | | | | |
| U2-+--^---+ +---+
| ||
| ||
+---+|
+--+--+
| |
| PCF |
| |
+-+
At low, SoC pin is connected to U2 as drive. when reset to high, you
now have U1 driving to the same pin that SoC has, potentially
resulting in contention.
Unfortunately, at this level, you do not know what the state of the
system is, blindly forcing a pin level will potentially cause
contention risk depending on pin configuration.
Assume we are doing a reset when the system is powered on, irrespective of
the
state of the system, we'll be forcing the pin level to the default state.
Yes, I dont deny that system will be fine *after* reset sequence is
started or completed. However there is a duration between the pcf
shutdown handler is called and the final reset handler is invoked -
that is the duration when the contention might cause device behavior.
Essentially ignoring the state various drivers have asked PCF to setup
the pins and doing a hands down configuration may have side effects we
cant properly expect.
The solution might be to invoke the shutdown handler of the various drivers
using the PCF before the shutdown handler of the PCF driver itself gets
invoked? But I'm not sure how can that be achieved in linux kernel :-(
Thanks
Kishon
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] gpio: pcf857x: restore the initial line state of all pcf lines
Hi,
On Wednesday 18 March 2015 05:51 PM, Linus Walleij wrote:
On Mon, Mar 16, 2015 at 9:46 AM, Kishon Vijay Abraham I kis...@ti.com wrote:
On Wednesday 14 January 2015 05:28 PM, Linus Walleij wrote:
#include linux/reboot.h
static int foo_reboot_handler(struct notifier_block *this,
unsigned long code,
void *unused)
{
pr_crit(do some last minute stuff\n);
return NOTIFY_OK;
}
static struct notifier_block foo_reboot_notifier = {
.notifier_call = foo_reboot_handler,
};
register_reboot_notifier(foo_reboot_notifier);
Added debug prints and found the reboot notifier gets invoked before the
shutdown handler which means some stuff can be done after this reboot
notifier:-(
Specify exactly what stuff may happen after the reboot notifier.
okay, it's assumed the device may be used (active) till the shutdown handler
of that particular device is called.
In this particular case we are restoring the initial line state of all pcf
lines even though we don't know if the devices connected to it are still being
active, which might cause a contention as explained by NM [1]
If the reboot notifier gets invoked after the shutdown handler then we could
be sure that restoring the initial line state of the pcf lines wouldn't affect
the devices connected to it.
Thanks
Kishon
[1] - http://www.spinics.net/lists/linux-mmc/msg29855.html
Of course stuff happens both before and after the reboot
notifier, the question is exactly what, that may conflict with this.
Yours,
Linus Walleij
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] phy: Add a driver for dm816x USB PHY
Hi Tony,
On Wednesday 18 March 2015 05:42 AM, Tony Lindgren wrote:
Add a minimal driver for dm816x USB. This makes USB work on dm816x
without any other changes needed as it can use the existing musb_dsps
glue layer for the USB controller.
Note that this phy is different from dm814x and am335x.
Cc: Bin Liu binml...@gmail.com
Cc: Brian Hutchinson b.hutch...@gmail.com
Cc: Felipe Balbi ba...@ti.com
Cc: Matthijs van Duin matthijsvand...@gmail.com
Cc: Paul Bolle pebo...@tiscali.nl
Cc: Rusty Russell ru...@rustcorp.com.au
Signed-off-by: Tony Lindgren t...@atomide.com
---
.../devicetree/bindings/phy/dm816x-phy.txt | 24 ++
drivers/phy/Kconfig| 7 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-dm816x-usb.c | 304 +
4 files changed, 336 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/dm816x-phy.txt
create mode 100644 drivers/phy/phy-dm816x-usb.c
diff --git a/Documentation/devicetree/bindings/phy/dm816x-phy.txt
b/Documentation/devicetree/bindings/phy/dm816x-phy.txt
new file mode 100644
index 000..2fe3d11
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/dm816x-phy.txt
@@ -0,0 +1,24 @@
+Device tree binding documentation for am816x USB PHY
+=
+
+Required properties:
+- compatible : should be ti,dm816x-usb-phy
+- reg : offset and length of the PHY register set.
+- reg-names : name for the phy registers
+- clocks : phandle to the clock
+- clock-names : name of the clock
+- syscon: phandle for the syscon node to access misc registers
+- #phy-cells : from the generic PHY bindings, must be 1
should be '0'
+- syscon: phandle for the syscon node to access misc registers
+
+Example:
+
+usb_phy0: usb-phy@20 {
+ compatible = ti,dm8168-usb-phy;
+ reg = 0x20 0x8;
+ reg-names = phy;
+ clocks = main_fapll 6;
+ clock-names = refclk;
+ #phy-cells = 0;
+ syscon = scm_conf;
+};
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 2962de2..c858c2b 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -35,6 +35,13 @@ config ARMADA375_USBCLUSTER_PHY
depends on OF
select GENERIC_PHY
+config PHY_DM816X_USB
+ tristate TI dm816x USB PHY driver
+ depends on ARCH_OMAP2PLUS
+ select GENERIC_PHY
+ help
+ Enable this for dm81xx USB to work.
+
config PHY_EXYNOS_MIPI_VIDEO
tristate S5P/EXYNOS SoC series MIPI CSI-2/DSI PHY driver
depends on HAS_IOMEM
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index f080e1b..dab6665 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_GENERIC_PHY) += phy-core.o
obj-$(CONFIG_PHY_BERLIN_USB) += phy-berlin-usb.o
obj-$(CONFIG_PHY_BERLIN_SATA) += phy-berlin-sata.o
+obj-$(CONFIG_PHY_DM816X_USB) += phy-dm816x-usb.o
obj-$(CONFIG_ARMADA375_USBCLUSTER_PHY)+= phy-armada375-usb2.o
obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o
obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
diff --git a/drivers/phy/phy-dm816x-usb.c b/drivers/phy/phy-dm816x-usb.c
new file mode 100644
index 000..2fc276d
--- /dev/null
+++ b/drivers/phy/phy-dm816x-usb.c
@@ -0,0 +1,304 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/regmap.h
+
+#include linux/slab.h
+#include linux/of.h
+#include linux/io.h
+#include linux/usb/phy_companion.h
+#include linux/clk.h
+#include linux/err.h
+#include linux/pm_runtime.h
+#include linux/delay.h
+#include linux/phy/phy.h
+#include linux/of_platform.h
+
+#include linux/mfd/syscon.h
+
+/*
+ * TRM has two sets of USB_CTRL registers.. The correct register bits
+ * are in TRM section 24.9.8.2 USB_CTRL Register. The TRM documents the
+ * phy as being SR70LX Synopsys USB 2.0 OTG nanoPHY. It also seems at
+ * least dm816x rev c ignores writes to USB_CTRL register, but the TI
+ * kernel is writing to those so it's possible that later revisions
+ * have worknig USB_CTRL register.
+ *
+ * Also note that At least USB_CTRL register seems to be dm816x specific
+ * according to the TRM. It's possible that USBPHY_CTRL is more generic,
+ * but that would have to be checked against the SR70LX documentation
+ * which does not seem to be publicly available.
+ *
+ * Finally, the phy on dm814x
[RESEND PATCH 2/2] bus: ocp2scp: SYNC2 value should be changed to 0x6
As per the TRMs of AM572x, OMAP4430, OMAP4460, OMAP543x, the value of
SYNC2 must be set to 0x6 in order to ensure correct operation.
So modified the SYNC2 value of OCP2SCP TIMING register to 0x6 in all the
platforms that use OCP2SCP driver except AM437x. Also introduced a new
compatible property since we don't want to modify the OCP2SCP TIMING
register for AM437x.
The sections in TRM where the above caution can be found is mentioned below.
AM572x TRM SPRUHZ6 (http://www.ti.com/lit/ug/spruhz6/spruhz6.pdf) under
section 26.3.2.2, table 26-26.
OMAP4430 TRM SWPU231AP (http://www.ti.com/lit/ug/swpu231ap/swpu231ap.pdf)
under section 23.12.6.2.2 , Table 23-1213.
OMAP4460 TRM SWPU235AB (http://www.ti.com/lit/ug/swpu235ab/swpu235ab.pdf)
under section 23.12.6.2.2, Table 23-1213.
OMAP543x TRM SWPU249 (http://www.ti.com/lit/pdf/swpu249)
under section 27.3.2.2, Table 27-27.
Cc: Arnd Bergmann a...@arndb.de
Cc: Greg Kroah-Hartman gre...@linuxfoundation.org
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Signed-off-by: Praneeth Bajjuri prane...@ti.com
---
drivers/bus/omap-ocp2scp.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/drivers/bus/omap-ocp2scp.c b/drivers/bus/omap-ocp2scp.c
index 723ec06..9f18569 100644
--- a/drivers/bus/omap-ocp2scp.c
+++ b/drivers/bus/omap-ocp2scp.c
@@ -16,6 +16,7 @@
*
*/
+#include linux/io.h
#include linux/module.h
#include linux/platform_device.h
#include linux/err.h
@@ -23,6 +24,9 @@
#include linux/of.h
#include linux/of_platform.h
+#define OCP2SCP_TIMING 0x18
+#define SYNC2_MASK 0xf
+
static int ocp2scp_remove_devices(struct device *dev, void *c)
{
struct platform_device *pdev = to_platform_device(dev);
@@ -35,6 +39,9 @@ static int ocp2scp_remove_devices(struct device *dev, void *c)
static int omap_ocp2scp_probe(struct platform_device *pdev)
{
int ret;
+ u32 reg;
+ void __iomem *regs;
+ struct resource *res;
struct device_node *np = pdev-dev.of_node;
if (np) {
@@ -47,6 +54,32 @@ static int omap_ocp2scp_probe(struct platform_device *pdev)
}
pm_runtime_enable(pdev-dev);
+ /*
+* As per AM572x TRM: http://www.ti.com/lit/ug/spruhz6/spruhz6.pdf
+* under section 26.3.2.2, table 26-26 OCP2SCP TIMING Caution;
+* As per OMAP4430 TRM: http://www.ti.com/lit/ug/swpu231ap/swpu231ap.pdf
+* under section 23.12.6.2.2 , Table 23-1213 OCP2SCP TIMING Caution;
+* As per OMAP4460 TRM: http://www.ti.com/lit/ug/swpu235ab/swpu235ab.pdf
+* under section 23.12.6.2.2, Table 23-1213 OCP2SCP TIMING Caution;
+* As per OMAP543x TRM http://www.ti.com/lit/pdf/swpu249
+* under section 27.3.2.2, Table 27-27 OCP2SCP TIMING Caution;
+*
+* Read path of OCP2SCP is not working properly due to low reset value
+* of SYNC2 parameter in OCP2SCP. Suggested reset value is 0x6 or more.
+*/
+ if (!of_device_is_compatible(np, ti,am437x-ocp2scp)) {
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ regs = devm_ioremap_resource(pdev-dev, res);
+ if (IS_ERR(regs))
+ goto err0;
+
+ pm_runtime_get_sync(pdev-dev);
+ reg = readl_relaxed(regs + OCP2SCP_TIMING);
+ reg = ~(SYNC2_MASK);
+ reg |= 0x6;
+ writel_relaxed(reg, regs + OCP2SCP_TIMING);
+ pm_runtime_put_sync(pdev-dev);
+ }
return 0;
@@ -67,6 +100,7 @@ static int omap_ocp2scp_remove(struct platform_device *pdev)
#ifdef CONFIG_OF
static const struct of_device_id omap_ocp2scp_id_table[] = {
{ .compatible = ti,omap-ocp2scp },
+ { .compatible = ti,am437x-ocp2scp },
{}
};
MODULE_DEVICE_TABLE(of, omap_ocp2scp_id_table);
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[RESEND PATCH 1/2] ARM: dts: am4372: Add ti,am437x-ocp2scp as compatible string for OCP2SCP
Added a new compatible string ti,am437x-ocp2scp for OCP2SCP module.
This is needed since except for the OCP2SCP used in AM437x, SYNC2 value
in OCP2SCP TIMING should be changed whereas the default value is sufficient
in AM437x.
Cc: Tony Lindgren t...@atomide.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
.../devicetree/bindings/bus/omap-ocp2scp.txt |3 ++-
arch/arm/boot/dts/am4372.dtsi |4 ++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
b/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
index 63dd805..18729f6 100644
--- a/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
+++ b/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
@@ -1,7 +1,8 @@
* OMAP OCP2SCP - ocp interface to scp interface
properties:
-- compatible : Should be ti,omap-ocp2scp
+- compatible : Should be ti,am437x-ocp2scp for AM437x processor
+ Should be ti,omap-ocp2scp for all others
- reg : Address and length of the register set for the device
- #address-cells, #size-cells : Must be present if the device has sub-nodes
- ranges : the child address space are mapped 1:1 onto the parent address space
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 1943fc3..286e317 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -787,7 +787,7 @@
};
ocp2scp0: ocp2scp@483a8000 {
- compatible = ti,omap-ocp2scp;
+ compatible = ti,am437x-ocp2scp, ti,omap-ocp2scp;
#address-cells = 1;
#size-cells = 1;
ranges;
@@ -806,7 +806,7 @@
};
ocp2scp1: ocp2scp@483e8000 {
- compatible = ti,omap-ocp2scp;
+ compatible = ti,am437x-ocp2scp, ti,omap-ocp2scp;
#address-cells = 1;
#size-cells = 1;
ranges;
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] gpio: pcf857x: restore the initial line state of all pcf lines
Hi,
On Wednesday 14 January 2015 05:28 PM, Linus Walleij wrote:
On Mon, Jan 5, 2015 at 7:26 AM, Kishon Vijay Abraham I kis...@ti.com wrote:
On Thursday 18 December 2014 07:41 PM, Nishanth Menon wrote:
On 12/18/2014 12:18 AM, Kishon Vijay Abraham I wrote:
On Tuesday 16 December 2014 02:20 AM, Nishanth Menon wrote:
On 12/12/2014 02:06 AM, Kishon Vijay Abraham I wrote:
The reset values for all the PCF lines are high and hence on shutdown
we should drive all the lines high in order to bring it to the reset state.
This is actually required since pcf doesn't have a reset line and even after
warm reset (by invoking reboot in prompt) the pcf lines maintains it's
previous programmed state. This becomes a problem if the boards are designed
to work with the default initial state.
DRA7XX_evm uses PCF8575 and one of the PCF output lines feeds to MMC/SD and
this line should be driven high in order for the MMC/SD to be detected.
This line is modelled as regulator and the hsmmc driver takes care of enabling
and disabling it. In the case of 'reboot', during shutdown path as part of it's
cleanup process the hsmmc driver disables this regulator. This makes MMC boot
not functional.
Fixed it by driving high all the pcf lines.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/gpio/gpio-pcf857x.c |9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpio/gpio-pcf857x.c b/drivers/gpio/gpio-pcf857x.c
index 236708a..00b15b2 100644
--- a/drivers/gpio/gpio-pcf857x.c
+++ b/drivers/gpio/gpio-pcf857x.c
@@ -448,6 +448,14 @@ static int pcf857x_remove(struct i2c_client *client)
return status;
}
+static void pcf857x_shutdown(struct i2c_client *client)
+{
+ struct pcf857x *gpio = i2c_get_clientdata(client);
+
+ /* Drive all the I/O lines high */
+ gpio-write(gpio-client, BIT(gpio-chip.ngpio) - 1);
you might force a contention here - depending on System configuration.
example:
+---+
| |
| U1 | +--+ +---+
| +- | | |
+---+ | | | |
| Switch-+SoC|
+---+ | | | |
| | | | | |
| U2-+--^---+ +---+
| ||
| ||
+---+|
+--+--+
| |
| PCF |
| |
+-+
At low, SoC pin is connected to U2 as drive. when reset to high, you
now have U1 driving to the same pin that SoC has, potentially
resulting in contention.
Unfortunately, at this level, you do not know what the state of the
system is, blindly forcing a pin level will potentially cause
contention risk depending on pin configuration.
Assume we are doing a reset when the system is powered on, irrespective of the
state of the system, we'll be forcing the pin level to the default state.
Yes, I dont deny that system will be fine *after* reset sequence is
started or completed. However there is a duration between the pcf
shutdown handler is called and the final reset handler is invoked -
that is the duration when the contention might cause device behavior.
Essentially ignoring the state various drivers have asked PCF to setup
the pins and doing a hands down configuration may have side effects we
cant properly expect.
The solution might be to invoke the shutdown handler of the various drivers
using the PCF before the shutdown handler of the PCF driver itself gets
invoked? But I'm not sure how can that be achieved in linux kernel :-(
#include linux/reboot.h
static int foo_reboot_handler(struct notifier_block *this,
unsigned long code,
void *unused)
{
pr_crit(do some last minute stuff\n);
return NOTIFY_OK;
}
static struct notifier_block foo_reboot_notifier = {
.notifier_call = foo_reboot_handler,
};
register_reboot_notifier(foo_reboot_notifier);
Added debug prints and found the reboot notifier gets invoked before the
shutdown handler which means some stuff can be done after this reboot
notifier:-(
Thanks
Kishon
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] phy: Add a driver for dm816x USB PHY
Hi Tony,
On Tuesday 10 March 2015 02:21 AM, Tony Lindgren wrote:
Add a minimal driver for dm816x USB. Otherwise we can just use
the existing musb_am335x and musb_dsps on dm816x.
If we can use an existing driver, I'd prefer that.
Cc: Brian Hutchinson b.hutch...@gmail.com
Cc: Felipe Balbi ba...@ti.com
Signed-off-by: Tony Lindgren t...@atomide.com
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/dm816x-phy.txt
@@ -0,0 +1,24 @@
+Device tree binding documentation for am816x USB PHY
+=
+
+Required properties:
+- compatible : should be ti,dm816x-usb-phy
+- reg : offset and length of the PHY register set.
+- reg-names : name for the phy registers
+- clocks : phandle to the clock
+- clock-names : name of the clock
+- syscon: phandle for the syscon node to access misc registers
+- #phy-cells : from the generic PHY bindings, must be 1
+- syscon: phandle for the syscon node to access misc registers
+
+Example:
+
+usb_phy0: usb-phy@20 {
+ compatible = ti,dm8168-usb-phy;
+ reg = 0x20 0x8;
+ reg-names = phy;
+ clocks = main_fapll 6;
+ clock-names = refclk;
+ #phy-cells = 0;
+ syscon = scm_conf;
+};
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -35,6 +35,13 @@ config ARMADA375_USBCLUSTER_PHY
depends on OF
select GENERIC_PHY
+config PHY_DM816X_USB
+ tristate TI dm816x USB PHY driver
+ depends on ARCH_OMAP2PLUS
+ select GENERIC_PHY
+ help
+ Enable this for dm81xx USB to work.
+
config PHY_EXYNOS_MIPI_VIDEO
tristate S5P/EXYNOS SoC series MIPI CSI-2/DSI PHY driver
depends on HAS_IOMEM
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_GENERIC_PHY) += phy-core.o
obj-$(CONFIG_PHY_BERLIN_USB) += phy-berlin-usb.o
obj-$(CONFIG_PHY_BERLIN_SATA) += phy-berlin-sata.o
+obj-$(CONFIG_PHY_DM816X_USB) += phy-dm816x-usb.o
obj-$(CONFIG_ARMADA375_USBCLUSTER_PHY)+= phy-armada375-usb2.o
obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o
obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
--- /dev/null
+++ b/drivers/phy/phy-dm816x-usb.c
@@ -0,0 +1,295 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/regmap.h
+
+#include linux/slab.h
+#include linux/of.h
+#include linux/io.h
+#include linux/usb/phy_companion.h
+#include linux/clk.h
+#include linux/err.h
+#include linux/pm_runtime.h
+#include linux/delay.h
+#include linux/phy/phy.h
+#include linux/of_platform.h
+
+#include linux/mfd/syscon.h
+
+/*
+ * TRM has two sets of USB_CTRL registers.. The correct register bits
+ * are in TRM section 24.9.8.2 USB_CTRL Register.
+ */
+#define DM816X_USB_CTRL_PHYCLKSRC BIT(8) /* 1 = PLL ref clock */
+#define DM816X_USB_CTRL_PHYSLEEP1 BIT(1)
+#define DM816X_USB_CTRL_PHYSLEEP0 BIT(0)
+
+#define DM816X_USBPHY_CTRL_TXRISETUNE 1
+#define DM816X_USBPHY_CTRL_TXVREFTUNE 0xc
+#define DM816X_USBPHY_CTRL_TXPREEMTUNE 0x2
+
+struct dm816x_usb_phy {
+ struct regmap *syscon;
+ struct device *dev;
+ unsigned int instance;
+ struct clk *refclk;
+ struct usb_phy phy;
+ unsigned int usb_ctrl; /* Shared between phy0 and phy1 */
+ unsigned int usbphy_ctrl;
+};
+
+static int dm816x_usb_phy_set_host(struct usb_otg *otg, struct usb_bus *host)
+{
+ otg-host = host;
+ if (!host)
+ otg-state = OTG_STATE_UNDEFINED;
+
+ return 0;
+}
+
+static int dm816x_usb_phy_set_peripheral(struct usb_otg *otg,
+struct usb_gadget *gadget)
+{
+ otg-gadget = gadget;
+ if (!gadget)
+ otg-state = OTG_STATE_UNDEFINED;
+
+ return 0;
+}
+
+static int dm816x_usb_phy_power_off(struct phy *x)
+{
+ struct dm816x_usb_phy *phy = phy_get_drvdata(x);
+
+ pm_runtime_put(phy-dev);
phy core takes care of invoking pm_runtime_put on power_off.
So this function shouldn't be needed at all.
+
+ return 0;
+}
+
+static int dm816x_usb_phy_power_on(struct phy *x)
+{
+ struct dm816x_usb_phy *phy = phy_get_drvdata(x);
+
+ return pm_runtime_get_sync(phy-dev);
similarly on power_on, phy_core invokes pm_runtime_get_sync.
+}
+
+static int dm816x_usb_phy_init(struct phy *x)
+{
+ struct dm816x_usb_phy *phy = phy_get_drvdata(x);
+ unsigned int val;
+ int error;
+
+ error =
Re: [PATCH 2/2] ARM: dts: dra7: remove ti,hwmod property from pcie phy
Hi, On Thursday 19 March 2015 10:19 PM, Paul Walmsley wrote: On Thu, 19 Mar 2015, grygorii.stras...@linaro.org wrote: On 03/19/2015 05:45 PM, Paul Walmsley wrote: On Thu, 19 Mar 2015, grygorii.stras...@linaro.org wrote: On 03/19/2015 04:55 PM, Paul Walmsley wrote: On Wed, 18 Mar 2015, grygorii.stras...@linaro.org wrote: On 03/18/2015 06:57 PM, Tony Lindgren wrote: * Grygorii Strashko grygorii.stras...@ti.com [150318 09:37]: As I can see Patch 1 from this series was merged in 4.0-rc4, but this patch wasn't. As result, I can see below warning all the time during boot now: [0.594591] platform 4a094000.pciephy: Cannot lookup hwmod 'pcie1-phy' OK. Is this needed as a fix for the v4.0-rc series, or can this wait for v4.1? I think, Yes. These two patches should go all together, because they are interrelated. Does the warning result in a functional problem, or is it just a warning? PCE1 PHY device is not registered any more. How does the second patch fix that? I've re-checked it - sorry for disinfo. PHY devices are created, but omap_device_fail_pm_domain is assigned to them. As result Runtime PM is not working any more. [0.592501] platform 4a094000.pciephy: Cannot lookup hwmod 'pcie1-phy' [0.597510] pinctrl-single 4a003400.pinmux: 281 pins at pa fc003400 size 1124 [0.602794] ti-pipe3 4a094000.pciephy: _od_fail_runtime_resume: FIXME: missing hwmod/omap_dev info When ti,hwmods is not present PCI PHY will be added as regular Platform device and Runtime PM will work again. OK then it should definitely go up as a fix. Kishon, for future references, those two patches should have been combined into a single patch. As it stands now, if someone bisects down to that first patch, it sounds like PM will be at least partially broken. Too bad I don't have a DRA7xx board where things like this can be tested before being sent upstream. huh.. was under the assumption that patches for device tree and the kernel patches should be separate. And PCIE for DRA7xx was broken in mainline for quite sometime now because of reset framework support not added for DRA7xx. Thanks Kishon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: patch phy: Add a driver for dm816x USB PHY added to linux-phy tree
Hi Tony, On Thursday 26 March 2015 09:34 PM, Tony Lindgren wrote: * Matthijs van Duin matthijsvand...@gmail.com [150326 00:02]: On 26 March 2015 at 00:36, Kishon Vijay Abraham I kis...@ti.com wrote: Let me know if you find any problems with this patch. I spotted a minor issue in drivers/phy/Kconfig: + Enable this for dm81xx USB to work. This should say dm816x instead. Yes that's correct, the phy on dm814x seems to be like on am335x, not like on dm816x. Kishon, let me know if you prefer a follow-up patch to fix this. No. I've fixed this in my tree https://git.kernel.org/cgit/linux/kernel/git/kishon/linux-phy.git/commit /?h=nextid=9fa9fd4ffc90582091b8c6219f2054265f71e4ef I'm not seeing the original mail for this thread anywhere for some reason BTW. It does not seem to be in the mailing list archives either, well at least not yet. It's an automated mail that is sent to notify the authors and other who are explicitly added in the signed-off by section when a patch is being merged in the linux-phy tree. So it won't be in the mailing list archives. But I'm not sure why you didn't receive it :-( Thanks Kishon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3] phy: ti-pipe3: fix suspend
Hi Roger,
On Tuesday 12 May 2015 09:37 PM, Roger Quadros wrote:
Relying on PM-ops for shutting down PHY clocks was a
bad idea since the users (e.g. PCIe/SATA) might not
have been suspended by then.
The main culprit for not shutting down the clocks was
the stray pm_runtime_get() call in probe.
Fix the whole thing in the right way by getting rid
of that pm_runtime_get() call from probe and
removing all PM-ops. It is the sole responsibility
of the PHY user to properly turn OFF and de-initialize
the PHY as part of its suspend routine.
As PHY core serializes init/exit we don't need
to use a spinlock in this driver. So get rid of it.
Signed-off-by: Roger Quadros rog...@ti.com
Signed-off-by: Sekhar Nori nsek...@ti.com
---
drivers/phy/phy-ti-pipe3.c | 112 -
1 file changed, 18 insertions(+), 94 deletions(-)
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index 53f295c..e13a306 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -28,7 +28,6 @@
#include linux/delay.h
#include linux/phy/omap_control_phy.h
#include linux/of_platform.h
-#include linux/spinlock.h
#define PLL_STATUS 0x0004
#define PLL_GO 0x0008
@@ -83,10 +82,6 @@ struct ti_pipe3 {
struct clk *refclk;
struct clk *div_clk;
struct pipe3_dpll_map *dpll_map;
- boolenabled;
- spinlock_t lock; /* serialize clock enable/disable */
- /* the below flag is needed specifically for SATA */
- boolrefclk_enabled;
};
static struct pipe3_dpll_map dpll_map_usb[] = {
@@ -137,6 +132,9 @@ static struct pipe3_dpll_params
*ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
return NULL;
}
+static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy);
+static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy);
+
static int ti_pipe3_power_off(struct phy *x)
{
struct ti_pipe3 *phy = phy_get_drvdata(x);
@@ -217,6 +215,7 @@ static int ti_pipe3_init(struct phy *x)
u32 val;
int ret = 0;
+ ti_pipe3_enable_clocks(phy);
/*
* Set pcie_pcs register to 0x96 for proper functioning of phy
* as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table
@@ -277,6 +276,8 @@ static int ti_pipe3_exit(struct phy *x)
return -EBUSY;
}
+ ti_pipe3_disable_clocks(phy);
+
return 0;
}
static struct phy_ops ops = {
@@ -305,8 +306,7 @@ static int ti_pipe3_probe(struct platform_device *pdev)
if (!phy)
return -ENOMEM;
- phy-dev = pdev-dev;
- spin_lock_init(phy-lock);
+ phy-dev = pdev-dev;
this looks more of a cleanup.
if (!of_device_is_compatible(node, ti,phy-pipe3-pcie)) {
match = of_match_device(ti_pipe3_id_table, pdev-dev);
@@ -402,6 +402,9 @@ static int ti_pipe3_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, phy);
pm_runtime_enable(phy-dev);
+ /* Prevent auto-disable of refclk for SATA PHY due to Errata i783 */
+ if (of_device_is_compatible(node, ti,phy-pipe3-sata))
+ clk_prepare_enable(phy-refclk);
generic_phy = devm_phy_create(phy-dev, NULL, ops);
if (IS_ERR(generic_phy))
@@ -413,24 +416,19 @@ static int ti_pipe3_probe(struct platform_device *pdev)
if (IS_ERR(phy_provider))
return PTR_ERR(phy_provider);
- pm_runtime_get(pdev-dev);
-
return 0;
}
static int ti_pipe3_remove(struct platform_device *pdev)
{
- if (!pm_runtime_suspended(pdev-dev))
- pm_runtime_put(pdev-dev);
pm_runtime_disable(pdev-dev);
return 0;
}
-#ifdef CONFIG_PM
static int ti_pipe3_enable_refclk(struct ti_pipe3 *phy)
{
- if (!IS_ERR(phy-refclk) !phy-refclk_enabled) {
+ if (!IS_ERR(phy-refclk)) {
int ret;
ret = clk_prepare_enable(phy-refclk);
@@ -438,7 +436,6 @@ static int ti_pipe3_enable_refclk(struct ti_pipe3 *phy)
dev_err(phy-dev, Failed to enable refclk %d\n, ret);
return ret;
}
- phy-refclk_enabled = true;
}
return 0;
@@ -448,28 +445,21 @@ static void ti_pipe3_disable_refclk(struct ti_pipe3 *phy)
{
if (!IS_ERR(phy-refclk))
clk_disable_unprepare(phy-refclk);
-
- phy-refclk_enabled = false;
}
static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy)
{
int ret = 0;
- unsigned long flags;
-
- spin_lock_irqsave(phy-lock, flags);
- if (phy-enabled)
- goto err1;
ret = ti_pipe3_enable_refclk(phy);
we can enable refclk here itself instead of having a separate function it?
if (ret)
- goto err1;
+ return ret;
if (!IS_ERR(phy-wkupclk))
Re: [PATCH 2/3] phy: ti-pipe3: i783 workaround for SATA lockup after dpll unlock/relock
Hi Roger,
On Tuesday 12 May 2015 09:37 PM, Roger Quadros wrote:
SATA_PLL_SOFT_RESET bit of CTRL_CORE_SMA_SW_0 must be toggled
between a SATA DPLL unlock and re-lock to prevent SATA lockup.
Introduce a new DT parameter 'syscon-pllreset' to provide the syscon
regmap access to this register which sits in the control module.
If the register is not provided we fallback to the old behaviour
i.e. SATA DPLL refclk will not be disabled and we prevent SoC low
power states.
Signed-off-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 16 ++
drivers/phy/phy-ti-pipe3.c | 67
2 files changed, 74 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 305e3df..f0f5537 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -82,6 +82,9 @@ Optional properties:
- id: If there are multiple instance of the same type, in order to
differentiate between each instance id can be used (e.g., multi-lane PCIe
PHY). If id is not provided, it is set to default value of '1'.
+ - syscon-pllreset: Handle to system control region that contains the
+ CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0
+ register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy.
This is usually a subnode of ocp2scp to which it is connected.
@@ -100,3 +103,16 @@ usb3phy@4a084400 {
sysclk,
refclk;
};
+
+sata_phy: phy@4A096000 {
+ compatible = ti,phy-pipe3-sata;
+ reg = 0x4A096000 0x80, /* phy_rx */
+ 0x4A096400 0x64, /* phy_tx */
+ 0x4A096800 0x40; /* pll_ctrl */
+ reg-names = phy_rx, phy_tx, pll_ctrl;
+ ctrl-module = omap_control_sata;
+ clocks = sys_clkin1, sata_ref_clk;
+ clock-names = sysclk, refclk;
+ syscon-pllreset = dra7_ctrl_core 0x3fc;
+ #phy-cells = 0;
+};
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index e13a306..d730142 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -28,6 +28,8 @@
#include linux/delay.h
#include linux/phy/omap_control_phy.h
#include linux/of_platform.h
+#include linux/mfd/syscon.h
+#include linux/regmap.h
#define PLL_STATUS 0x0004
#define PLL_GO 0x0008
@@ -52,6 +54,8 @@
#define PLL_LOCK0x2
#define PLL_IDLE0x1
+#define SATA_PLL_SOFT_RESETBIT(18)
+
/*
* This is an Empirical value that works, need to confirm the actual
* value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
@@ -82,6 +86,9 @@ struct ti_pipe3 {
struct clk *refclk;
struct clk *div_clk;
struct pipe3_dpll_map *dpll_map;
+ struct regmap *dpll_reset_syscon; /* ctrl. reg. acces */
+ unsigned intdpll_reset_reg; /* reg. index within syscon */
+ boolsata_refclk_enabled;
};
static struct pipe3_dpll_map dpll_map_usb[] = {
@@ -249,11 +256,15 @@ static int ti_pipe3_exit(struct phy *x)
u32 val;
unsigned long timeout;
- /* SATA DPLL can't be powered down due to Errata i783 and PCIe
-* does not have internal DPLL
+ /* If dpll_reset_syscon is not present we wont power down SATA DPLL
+* due to Errata i783
*/
- if (of_device_is_compatible(phy-dev-of_node, ti,phy-pipe3-sata) ||
- of_device_is_compatible(phy-dev-of_node, ti,phy-pipe3-pcie))
+ if (of_device_is_compatible(phy-dev-of_node, ti,phy-pipe3-sata)
+ !phy-dpll_reset_syscon)
+ return 0;
+
+ /* PCIe doesn't have DPLL. FIXME: need to disable clocks though */
I think it's better to fix it in this patch itself.. to disable clocks for PCIe.
+ if (of_device_is_compatible(phy-dev-of_node, ti,phy-pipe3-pcie))
return 0;
/* Put DPLL in IDLE mode */
@@ -276,6 +287,14 @@ static int ti_pipe3_exit(struct phy *x)
return -EBUSY;
}
+ /* i783: SATA needs control bit toggle after PLL unlock */
+ if (of_device_is_compatible(phy-dev-of_node, ti,phy-pipe3-sata)) {
+ regmap_update_bits(phy-dpll_reset_syscon, phy-dpll_reset_reg,
+ SATA_PLL_SOFT_RESET, SATA_PLL_SOFT_RESET);
+ regmap_update_bits(phy-dpll_reset_syscon, phy-dpll_reset_reg,
+ SATA_PLL_SOFT_RESET, 0);
+ }
+
ti_pipe3_disable_clocks(phy);
return 0;
@@ -350,6 +369,21 @@ static int ti_pipe3_probe(struct platform_device *pdev)
}
} else {
phy-wkupclk = ERR_PTR(-ENODEV);
+ phy-dpll_reset_syscon = syscon_regmap_lookup_by_phandle(node,
Re: [RFC PATCH] usb: dwc3: ep0: Fix mem corruption on OUT transfers of more than 512 bytes
Hi, On Tuesday 09 June 2015 08:09 PM, Michael Trimarchi wrote: Hi On Jun 9, 2015 4:36 PM, Kishon Vijay Abraham I kis...@ti.com mailto:kis...@ti.com wrote: DWC3 uses bounce buffer to handle non max packet aligned OUT transfers and the size of bounce buffer is 512 bytes. However if the host initiates OUT transfers of size more than 512 bytes (and non max packet aligned), the driver throws a WARN dump but still programs the TRB to receive more than 512 bytes. This will cause bounce buffer to overflow and corrupt the adjacent memory locations which can be fatal. Fix it by programming the TRB to receive a maximum of DWC3_EP0_BOUNCE_SIZE (512) bytes. Signed-off-by: Kishon Vijay Abraham I kis...@ti.com mailto:kis...@ti.com --- Steps to see the issue (before this patch) 1) Insert g_zero in DUT 2) run './testusb -t 14 -c 1 -s 520 -v 1' in host (size should be 512) The test should FAIL since bounce buffer can handle only 512 bytes, but the test PASS. There is a WARN dump in DUT but still there will be memory corruption since the bounce buffer overflows. Tested this patch using USB3 Gen X CV (ch9 tests: usb2 and usb3, link layer testing and MSC tests) and using USB2 X CV (ch9 tests, MSC tests). After the patch, the tests timeout! ./testusb -t 14 -c 1 -s 514 -v 1 unknown speed /dev/bus/usb/001/0180 /dev/bus/usb/001/018 test 14 -- 110 (Connection timed out) IMO a patch to fix this is required for stable releases too. So If this patch is alright, I can post the patch cc'ing stable. While the actual fix would be to have chained TRB, I'm not sure if it can go to stable releases. drivers/usb/dwc3/ep0.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c index 2ef3c8d..8858c60 100644 --- a/drivers/usb/dwc3/ep0.c +++ b/drivers/usb/dwc3/ep0.c @@ -816,6 +816,11 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc, unsigned maxp = ep0-endpoint.maxpacket; transfer_size += (maxp - (transfer_size % maxp)); + + /* Maximum of DWC3_EP0_BOUNCE_SIZE can only be received */ + if (transfer_size DWC3_EP0_BOUNCE_SIZE) + transfer_size = DWC3_EP0_BOUNCE_SIZE; + Can you just use maxp in the correct way? what do you mean by correct way? Using roundup() to calculate transfer_size? Thanks Kishon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH] usb: dwc3: ep0: Fix mem corruption on OUT transfers of more than 512 bytes
Hi, On Tuesday 09 June 2015 08:29 PM, Alan Stern wrote: On Tue, 9 Jun 2015, Kishon Vijay Abraham I wrote: Hi, On Tuesday 09 June 2015 08:09 PM, Michael Trimarchi wrote: Hi On Jun 9, 2015 4:36 PM, Kishon Vijay Abraham I kis...@ti.com mailto:kis...@ti.com wrote: DWC3 uses bounce buffer to handle non max packet aligned OUT transfers and the size of bounce buffer is 512 bytes. However if the host initiates OUT transfers of size more than 512 bytes (and non max packet aligned), the driver throws a WARN dump but still programs the TRB to receive more than 512 bytes. This will cause bounce buffer to overflow and corrupt the adjacent memory locations which can be fatal. Fix it by programming the TRB to receive a maximum of DWC3_EP0_BOUNCE_SIZE (512) bytes. Signed-off-by: Kishon Vijay Abraham I kis...@ti.com mailto:kis...@ti.com --- Steps to see the issue (before this patch) 1) Insert g_zero in DUT 2) run './testusb -t 14 -c 1 -s 520 -v 1' in host (size should be 512) The test should FAIL since bounce buffer can handle only 512 bytes, but the test PASS. There is a WARN dump in DUT but still there will be memory corruption since the bounce buffer overflows. Tested this patch using USB3 Gen X CV (ch9 tests: usb2 and usb3, link layer testing and MSC tests) and using USB2 X CV (ch9 tests, MSC tests). After the patch, the tests timeout! ./testusb -t 14 -c 1 -s 514 -v 1 unknown speed /dev/bus/usb/001/0180 /dev/bus/usb/001/018 test 14 -- 110 (Connection timed out) IMO a patch to fix this is required for stable releases too. So If this patch is alright, I can post the patch cc'ing stable. While the actual fix would be to have chained TRB, I'm not sure if it can go to stable releases. drivers/usb/dwc3/ep0.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c index 2ef3c8d..8858c60 100644 --- a/drivers/usb/dwc3/ep0.c +++ b/drivers/usb/dwc3/ep0.c @@ -816,6 +816,11 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc, unsigned maxp = ep0-endpoint.maxpacket; transfer_size += (maxp - (transfer_size % maxp)); + + /* Maximum of DWC3_EP0_BOUNCE_SIZE can only be received */ + if (transfer_size DWC3_EP0_BOUNCE_SIZE) + transfer_size = DWC3_EP0_BOUNCE_SIZE; + Can you just use maxp in the correct way? what do you mean by correct way? Using roundup() to calculate transfer_size? Why not just make the bounce buffer size the same as the maxpacket size? In other words, 1024 bytes instead of 512, for ep0 on a USB-3 device. It would still be possible for the host to send data more than 1024 bytes no? When working with DFU gadget, I've seen host sends data upto 4KB. Changing the bounce buffer size might not be able to fix all the cases IMO. The actual fix will be something like [1] [1] - http://comments.gmane.org/gmane.linux.kernel/1883688 Thanks Kishon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC PATCH] usb: dwc3: ep0: Fix mem corruption on OUT transfers of more than 512 bytes
DWC3 uses bounce buffer to handle non max packet aligned OUT transfers and
the size of bounce buffer is 512 bytes. However if the host initiates OUT
transfers of size more than 512 bytes (and non max packet aligned), the
driver throws a WARN dump but still programs the TRB to receive more than
512 bytes. This will cause bounce buffer to overflow and corrupt the
adjacent memory locations which can be fatal.
Fix it by programming the TRB to receive a maximum of DWC3_EP0_BOUNCE_SIZE
(512) bytes.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Steps to see the issue (before this patch)
1) Insert g_zero in DUT
2) run './testusb -t 14 -c 1 -s 520 -v 1' in host (size should be 512)
The test should FAIL since bounce buffer can handle only 512 bytes, but the
test PASS. There is a WARN dump in DUT but still there will be memory
corruption since the bounce buffer overflows.
Tested this patch using USB3 Gen X CV (ch9 tests: usb2 and usb3, link layer
testing and MSC tests) and using USB2 X CV (ch9 tests, MSC tests).
After the patch, the tests timeout!
./testusb -t 14 -c 1 -s 514 -v 1
unknown speed /dev/bus/usb/001/0180
/dev/bus/usb/001/018 test 14 -- 110 (Connection timed out)
IMO a patch to fix this is required for stable releases too. So If this
patch is alright, I can post the patch cc'ing stable. While the actual fix
would be to have chained TRB, I'm not sure if it can go to stable
releases.
drivers/usb/dwc3/ep0.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index 2ef3c8d..8858c60 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -816,6 +816,11 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
unsigned maxp = ep0-endpoint.maxpacket;
transfer_size += (maxp - (transfer_size % maxp));
+
+ /* Maximum of DWC3_EP0_BOUNCE_SIZE can only be received */
+ if (transfer_size DWC3_EP0_BOUNCE_SIZE)
+ transfer_size = DWC3_EP0_BOUNCE_SIZE;
+
transferred = min_t(u32, ur-length,
transfer_size - length);
memcpy(ur-buf, dwc-ep0_bounce, transferred);
@@ -937,11 +942,14 @@ static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
return;
}
- WARN_ON(req-request.length DWC3_EP0_BOUNCE_SIZE);
-
maxpacket = dep-endpoint.maxpacket;
transfer_size = roundup(req-request.length, maxpacket);
+ if (transfer_size DWC3_EP0_BOUNCE_SIZE) {
+ dev_WARN(dwc-dev, bounce buf can't handle req len\n);
+ transfer_size = DWC3_EP0_BOUNCE_SIZE;
+ }
+
dwc-ep0_bounced = true;
/*
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH] usb: dwc3: ep0: Fix mem corruption on OUT transfers of more than 512 bytes
Hi, On Tuesday 09 June 2015 08:46 PM, Alan Stern wrote: On Tue, 9 Jun 2015, Kishon Vijay Abraham I wrote: Why not just make the bounce buffer size the same as the maxpacket size? In other words, 1024 bytes instead of 512, for ep0 on a USB-3 device. It would still be possible for the host to send data more than 1024 bytes no? Yes. When working with DFU gadget, I've seen host sends data upto 4KB. Changing the bounce buffer size might not be able to fix all the cases IMO. The actual fix will be something like [1] [1] - http://comments.gmane.org/gmane.linux.kernel/1883688 But with a bounce buffer that's only 512 bytes long, you can never send an entire packet's worth of data. If the bounce buffer is 1024 bytes for control endpoint, 512 bytes should be sufficient to send entire packet right? then you can send the entire first packet. When that's done, you can send the second packet. And so on. It wouldn't be quite as fast, but for ep0 that shouldn't matter. right! this is a variant of what I tried to implement in chained TRB [1]. $subject tries just to avoid memory corruption instead of actually trying to receive all the data. Thanks Kishon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/5] usb: dwc3: ep0: preparation for handling non maxpacket aligned transfers 512
No functional change. This is in preparation for handling non maxpacket
aligned transfers greater than bounce buffer size. This is basically to
avoid code duplication when using chained TRB transfers to handle
non maxpacket aligned transfers greater than bounce buffer size.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/usb/dwc3/ep0.c | 25 +
1 file changed, 17 insertions(+), 8 deletions(-)
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index 713e46a..4998074 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -779,7 +779,11 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
struct usb_request *ur;
struct dwc3_trb *trb;
struct dwc3_ep *ep0;
- u32 transferred;
+ unsignedtransfer_size = 0;
+ unsignedmaxp;
+ unsignedremaining_ur_length;
+ void*buf;
+ u32 transferred = 0;
u32 status;
u32 length;
u8 epnum;
@@ -808,20 +812,24 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
}
ur = r-request;
+ buf = ur-buf;
+ remaining_ur_length = ur-length;
length = trb-size DWC3_TRB_SIZE_MASK;
+ maxp = ep0-endpoint.maxpacket;
+
if (dwc-ep0_bounced) {
- unsigned maxp = ep0-endpoint.maxpacket;
- unsigned transfer_size = roundup(ur-length, maxp);
+ transfer_size = roundup((ur-length - transfer_size),
+ maxp);
/* Maximum of DWC3_EP0_BOUNCE_SIZE can only be received */
if (transfer_size DWC3_EP0_BOUNCE_SIZE)
transfer_size = DWC3_EP0_BOUNCE_SIZE;
- transferred = min_t(u32, ur-length,
- transfer_size - length);
- memcpy(ur-buf, dwc-ep0_bounce, transferred);
+ transferred = min_t(u32, remaining_ur_length,
+ transfer_size - length);
+ memcpy(buf, dwc-ep0_bounce, transferred);
} else {
transferred = ur-length - length;
}
@@ -930,7 +938,7 @@ static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
DWC3_TRBCTL_CONTROL_DATA);
} else if (!IS_ALIGNED(req-request.length, dep-endpoint.maxpacket)
(dep-number == 0)) {
- u32 transfer_size;
+ u32 transfer_size = 0;
u32 maxpacket;
ret = usb_gadget_map_request(dwc-gadget, req-request,
@@ -941,7 +949,8 @@ static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
}
maxpacket = dep-endpoint.maxpacket;
- transfer_size = roundup(req-request.length, maxpacket);
+ transfer_size = roundup((req-request.length - transfer_size),
+ maxpacket);
if (transfer_size DWC3_EP0_BOUNCE_SIZE) {
dev_WARN(dwc-dev, bounce buf can't handle req len\n);
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 5/5] usb: dwc3: ep0: handle non maxpacket aligned transfers 512
Use chained TRB mechanism to handle non maxpacket aligned transfers
greater than bounce buffer size. With this the first TRB will be programmed
to receive 'ALIGN(ur-length - maxp, maxp)' data and the second TRB
will be programmed to receive the remaining data using bounce buffer.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/usb/dwc3/ep0.c | 42 --
1 file changed, 28 insertions(+), 14 deletions(-)
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index 6847afe..4c777fe 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -830,13 +830,26 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
maxp = ep0-endpoint.maxpacket;
if (dwc-ep0_bounced) {
+ /*
+* Handle the first TRB before handling the bounce buffer if
+* the request length is greater than the bounce buffer size
+*/
+ if (ur-length DWC3_EP0_BOUNCE_SIZE) {
+ transfer_size = ALIGN(ur-length - maxp, maxp);
+ transferred = transfer_size - length;
+ buf = (u8 *)buf + transferred;
+ ur-actual += transferred;
+ remaining_ur_length -= transferred;
+
+ trb++;
+ length = trb-size DWC3_TRB_SIZE_MASK;
+
+ ep0-free_slot = 0;
+ }
+
transfer_size = roundup((ur-length - transfer_size),
maxp);
- /* Maximum of DWC3_EP0_BOUNCE_SIZE can only be received */
- if (transfer_size DWC3_EP0_BOUNCE_SIZE)
- transfer_size = DWC3_EP0_BOUNCE_SIZE;
-
transferred = min_t(u32, remaining_ur_length,
transfer_size - length);
memcpy(buf, dwc-ep0_bounce, transferred);
@@ -959,21 +972,22 @@ static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
}
maxpacket = dep-endpoint.maxpacket;
- transfer_size = roundup((req-request.length - transfer_size),
- maxpacket);
- if (transfer_size DWC3_EP0_BOUNCE_SIZE) {
- dev_WARN(dwc-dev, bounce buf can't handle req len\n);
- transfer_size = DWC3_EP0_BOUNCE_SIZE;
+ if (req-request.length DWC3_EP0_BOUNCE_SIZE) {
+ transfer_size = ALIGN(req-request.length - maxpacket,
+ maxpacket);
+ ret = dwc3_ep0_start_trans(dwc, dep-number,
+ req-request.dma,
+ transfer_size,
+ DWC3_TRBCTL_CONTROL_DATA,
+ true);
}
+ transfer_size = roundup((req-request.length - transfer_size),
+ maxpacket);
+
dwc-ep0_bounced = true;
- /*
-* REVISIT in case request length is bigger than
-* DWC3_EP0_BOUNCE_SIZE we will need two chained
-* TRBs to handle the transfer.
-*/
ret = dwc3_ep0_start_trans(dwc, dep-number,
dwc-ep0_bounce_addr, transfer_size,
DWC3_TRBCTL_CONTROL_DATA, false);
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/5] usb: dwc3; ep0: Modify _dwc3_ep0_start_trans_ API to take 'chain' parameter
No functional change. Added a new parameter in _dwc3_ep0_start_trans_ to
indicate whether the TRB is a chained TRB or last TRB. This is in
preparation for adding chained TRB support for ep0.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/usb/dwc3/ep0.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index 4998074..d1a2be1 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -56,7 +56,7 @@ static const char *dwc3_ep0_state_string(enum dwc3_ep0_state
state)
}
static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
- u32 len, u32 type)
+ u32 len, u32 type, unsigned chain)
{
struct dwc3_gadget_ep_cmd_params params;
struct dwc3_trb *trb;
@@ -302,7 +302,7 @@ void dwc3_ep0_out_start(struct dwc3 *dwc)
int ret;
ret = dwc3_ep0_start_trans(dwc, 0, dwc-ctrl_req_addr, 8,
- DWC3_TRBCTL_CONTROL_SETUP);
+ DWC3_TRBCTL_CONTROL_SETUP, false);
WARN_ON(ret 0);
}
@@ -851,7 +851,7 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
ret = dwc3_ep0_start_trans(dwc, epnum,
dwc-ctrl_req_addr, 0,
- DWC3_TRBCTL_CONTROL_DATA);
+ DWC3_TRBCTL_CONTROL_DATA, false);
WARN_ON(ret 0);
}
}
@@ -935,7 +935,7 @@ static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
if (req-request.length == 0) {
ret = dwc3_ep0_start_trans(dwc, dep-number,
dwc-ctrl_req_addr, 0,
- DWC3_TRBCTL_CONTROL_DATA);
+ DWC3_TRBCTL_CONTROL_DATA, false);
} else if (!IS_ALIGNED(req-request.length, dep-endpoint.maxpacket)
(dep-number == 0)) {
u32 transfer_size = 0;
@@ -966,7 +966,7 @@ static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
*/
ret = dwc3_ep0_start_trans(dwc, dep-number,
dwc-ep0_bounce_addr, transfer_size,
- DWC3_TRBCTL_CONTROL_DATA);
+ DWC3_TRBCTL_CONTROL_DATA, false);
} else {
ret = usb_gadget_map_request(dwc-gadget, req-request,
dep-number);
@@ -976,7 +976,8 @@ static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
}
ret = dwc3_ep0_start_trans(dwc, dep-number, req-request.dma,
- req-request.length, DWC3_TRBCTL_CONTROL_DATA);
+ req-request.length, DWC3_TRBCTL_CONTROL_DATA,
+ false);
}
WARN_ON(ret 0);
@@ -991,7 +992,7 @@ static int dwc3_ep0_start_control_status(struct dwc3_ep
*dep)
: DWC3_TRBCTL_CONTROL_STATUS2;
return dwc3_ep0_start_trans(dwc, dep-number,
- dwc-ctrl_req_addr, 0, type);
+ dwc-ctrl_req_addr, 0, type, false);
}
static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/5] usb: dwc3: ep0: use _roundup_ to calculate the transfer size
No functional change. Used _roundup_ macro to calculate the transfer
size aligned to maxpacket in dwc3_ep0_complete_data. It also makes it
similar to how transfer size is calculated in __dwc3_ep0_do_control_data.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/usb/dwc3/ep0.c |4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index 8858c60..713e46a 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -812,10 +812,8 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
length = trb-size DWC3_TRB_SIZE_MASK;
if (dwc-ep0_bounced) {
- unsigned transfer_size = ur-length;
unsigned maxp = ep0-endpoint.maxpacket;
-
- transfer_size += (maxp - (transfer_size % maxp));
+ unsigned transfer_size = roundup(ur-length, maxp);
/* Maximum of DWC3_EP0_BOUNCE_SIZE can only be received */
if (transfer_size DWC3_EP0_BOUNCE_SIZE)
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 4/5] usb: dwc3: ep0: Add chained TRB support
Add chained TRB support to ep0. Now TRB's can be chained just by
invoking _dwc3_ep0_start_trans_ with 'chain' parameter set to true.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/usb/dwc3/ep0.c| 16 +---
drivers/usb/dwc3/gadget.c |2 +-
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index d1a2be1..6847afe 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -70,7 +70,10 @@ static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum,
dma_addr_t buf_dma,
return 0;
}
- trb = dwc-ep0_trb;
+ trb = dwc-ep0_trb[dep-free_slot];
+
+ if (chain)
+ dep-free_slot++;
trb-bpl = lower_32_bits(buf_dma);
trb-bph = upper_32_bits(buf_dma);
@@ -78,10 +81,17 @@ static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum,
dma_addr_t buf_dma,
trb-ctrl = type;
trb-ctrl |= (DWC3_TRB_CTRL_HWO
- | DWC3_TRB_CTRL_LST
- | DWC3_TRB_CTRL_IOC
| DWC3_TRB_CTRL_ISP_IMI);
+ if (chain)
+ trb-ctrl |= DWC3_TRB_CTRL_CHN;
+ else
+ trb-ctrl |= (DWC3_TRB_CTRL_IOC
+ | DWC3_TRB_CTRL_LST);
+
+ if (chain)
+ return 0;
+
memset(params, 0, sizeof(params));
params.param0 = upper_32_bits(dwc-ep0_trb_addr);
params.param1 = lower_32_bits(dwc-ep0_trb_addr);
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 8946c32..b8d0a84 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -2677,7 +2677,7 @@ int dwc3_gadget_init(struct dwc3 *dwc)
goto err0;
}
- dwc-ep0_trb = dma_alloc_coherent(dwc-dev, sizeof(*dwc-ep0_trb),
+ dwc-ep0_trb = dma_alloc_coherent(dwc-dev, sizeof(*dwc-ep0_trb) * 2,
dwc-ep0_trb_addr, GFP_KERNEL);
if (!dwc-ep0_trb) {
dev_err(dwc-dev, failed to allocate ep0 trb\n);
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/5] usb: dwc3: handle non maxpacket aligned transfers 512
Patch series adds support to handle non maxpacket aligned transfers greater than bounce buffer size (512). It first adds chained TRB support and then uses it to handle non maxpacket aligned transfers greater than bounce buffer size. Also included a cleanup patch to use 'roundup' macro. This series is created after applying [1] Non maxpacket aligned transfers can be initiated by ./testusb -t 14 -c 1 -s 520 -v 1 Before this series: unknown speed /dev/bus/usb/001/0180 /dev/bus/usb/001/018 test 14 -- 110 (Connection timed out) After this series: unknown speed /dev/bus/usb/001/0230 /dev/bus/usb/001/023 test 14,0.000486 secs Tested this patch using USB3 Gen X CV (ch9 tests: usb2 and usb3, link layer testing and MSC tests) and using USB2 X CV (ch9 tests, MSC tests) and verified this doesn't cause additional failures. Lecroy compliance tests fail even without this patch series so deferred testing it. [1] - http://permalink.gmane.org/gmane.linux.kernel/1972684 Kishon Vijay Abraham I (5): usb: dwc3: ep0: use _roundup_ to calculate the transfer size usb: dwc3: ep0: preparation for handling non maxpacket aligned transfers 512 usb: dwc3; ep0: Modify _dwc3_ep0_start_trans_ API to take 'chain' parameter usb: dwc3: ep0: Add chained TRB support usb: dwc3: ep0: handle non maxpacket aligned transfers 512 drivers/usb/dwc3/ep0.c| 94 ++--- drivers/usb/dwc3/gadget.c |2 +- 2 files changed, 64 insertions(+), 32 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH] usb: dwc3: ep0: Fix mem corruption on OUT transfers of more than 512 bytes
Hi, On Tuesday 09 June 2015 10:54 PM, Alan Stern wrote: On Tue, 9 Jun 2015, Kishon Vijay Abraham I wrote: But with a bounce buffer that's only 512 bytes long, you can never send an entire packet's worth of data. If the bounce buffer is 1024 bytes for control endpoint, 512 bytes should be sufficient to send entire packet right? Yes, you're right. I had confused control endpoints with bulk endpoints, where the maxpacket size is 1024. Sorry for the mistake. no problem. then you can send the entire first packet. When that's done, you can send the second packet. And so on. It wouldn't be quite as fast, but for ep0 that shouldn't matter. right! this is a variant of what I tried to implement in chained TRB [1]. $subject tries just to avoid memory corruption instead of actually trying to receive all the data. Okay. If you take the $SUBJECT approach, I think it would be better for an URB submission to fail than for the host controller to send only part of the data. Could be but we also want to prevent mem corruption in the case of a faulty host to be more robust. Thanks Kishon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 05/17] phy: omap-usb2: Add a new compatible string for USB2 PHY2
The USB2 PHY2 has a different register map compared to USB2 PHY1
to power on/off the PHY. In order to handle it, add a new
compatible string.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt |2 ++
drivers/phy/phy-omap-usb2.c |9 +
2 files changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 52c7a92..b9101b9 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -31,6 +31,8 @@ OMAP USB2 PHY
Required properties:
- compatible: Should be ti,omap-usb2
+ Should be ti,dra7x-usb2-phy2 for the 2nd instance of USB2 PHY
+ in DRA7x
- reg : Address and length of the register set for the device.
- #phy-cells: determine the number of cells that should be given in the
phandle while referencing this phy.
diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
index b5c266a..2f7220f 100644
--- a/drivers/phy/phy-omap-usb2.c
+++ b/drivers/phy/phy-omap-usb2.c
@@ -159,6 +159,11 @@ static const struct usb_phy_data dra7x_usb2_data = {
.flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
};
+static const struct usb_phy_data dra7x_usb2_phy2_data = {
+ .label = dra7x_usb2_phy2,
+ .flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
+};
+
static const struct usb_phy_data am437x_usb2_data = {
.label = am437x_usb2,
.flags = 0,
@@ -178,6 +183,10 @@ static const struct of_device_id omap_usb2_id_table[] = {
.data = dra7x_usb2_data,
},
{
+ .compatible = ti,dra7x-usb2-phy2,
+ .data = dra7x_usb2_phy2_data,
+ },
+ {
.compatible = ti,am437x-usb2,
.data = am437x_usb2_data,
},
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 09/17] ARM: dts: dra7: Use syscon-phy-power instead of ctrl-module in SATA PHY node
Add syscon-phy-power property and remove the deprecated ctrl-module
property from SATA PHY node. Since omap_control_sata note is no longer
used, remove it.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 3f434f7..92e0741 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1115,14 +1115,6 @@
status = disabled;
};
- omap_control_sata: control-phy@4a002374 {
- compatible = ti,control-phy-pipe3;
- reg = 0x4a002374 0x4;
- reg-names = power;
- clocks = sys_clkin1;
- clock-names = sysclk;
- };
-
/* OCP2SCP3 */
ocp2scp@4a09 {
compatible = ti,omap-ocp2scp;
@@ -1137,7 +1129,7 @@
0x4A096400 0x64, /* phy_tx */
0x4A096800 0x40; /* pll_ctrl */
reg-names = phy_rx, phy_tx, pll_ctrl;
- ctrl-module = omap_control_sata;
+ syscon-phy-power = dra7_ctrl_core 0x374;
clocks = sys_clkin1, sata_ref_clk;
clock-names = sysclk, refclk;
syscon-pllreset = dra7_ctrl_core 0x3fc;
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 16/17] ARM: dts: omap4: Use syscon-phy-power instead of ctrl-module in USB PHY node
Add syscon-phy-power property and remove the deprecated ctrl-module
property from USB PHY dt node.
Since omap_control_usb2phy devicetree node is no longer used,
remove it.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/omap4.dtsi |8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index f884d6a..d0e0960 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -701,7 +701,7 @@
usb2_phy: usb2phy@4a0ad080 {
compatible = ti,omap-usb2;
reg = 0x4a0ad080 0x58;
- ctrl-module = omap_control_usb2phy;
+ syscon-phy-power = scm_conf 0x300;
clocks = usb_phy_cm_clk32k;
clock-names = wkupclk;
#phy-cells = 0;
@@ -852,12 +852,6 @@
};
};
- omap_control_usb2phy: control-phy@4a002300 {
- compatible = ti,control-phy-usb2;
- reg = 0x4a002300 0x4;
- reg-names = power;
- };
-
omap_control_usbotg: control-phy@4a00233c {
compatible = ti,control-phy-otghs;
reg = 0x4a00233c 0x4;
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 13/17] ARM: dts: am4372: Use syscon-phy-power instead of ctrl-module in USB PHY node
Add syscon-phy-power property and remove the deprecated ctrl-module
property from USB PHY device tree node.
Since am43xx_control_usb2phy1 and am43xx_control_usb2phy2
devicetree nodes are no longer used, remove it.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/am4372.dtsi | 16 ++--
1 file changed, 2 insertions(+), 14 deletions(-)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index c80a3e2..0754e0da 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -796,18 +796,6 @@
status = disabled;
};
- am43xx_control_usb2phy1: control-phy@44e10620 {
- compatible = ti,control-phy-usb2-am437;
- reg = 0x44e10620 0x4;
- reg-names = power;
- };
-
- am43xx_control_usb2phy2: control-phy@0x44e10628 {
- compatible = ti,control-phy-usb2-am437;
- reg = 0x44e10628 0x4;
- reg-names = power;
- };
-
ocp2scp0: ocp2scp@483a8000 {
compatible = ti,am437x-ocp2scp, ti,omap-ocp2scp;
#address-cells = 1;
@@ -818,7 +806,7 @@
usb2_phy1: phy@483a8000 {
compatible = ti,am437x-usb2;
reg = 0x483a8000 0x8000;
- ctrl-module = am43xx_control_usb2phy1;
+ syscon-phy-power = scm_conf 0x620;
clocks = usb_phy0_always_on_clk32k,
usb_otg_ss0_refclk960m;
clock-names = wkupclk, refclk;
@@ -837,7 +825,7 @@
usb2_phy2: phy@483e8000 {
compatible = ti,am437x-usb2;
reg = 0x483e8000 0x8000;
- ctrl-module = am43xx_control_usb2phy2;
+ syscon-phy-power = scm_conf 0x628;
clocks = usb_phy1_always_on_clk32k,
usb_otg_ss1_refclk960m;
clock-names = wkupclk, refclk;
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 17/17] ARM: dts: omap4: Use syscon-otghs instead of ctrl-module in USB node
Add syscon-otghs property and remove the deprecated ctrl-module
property from MUSB devicetree node.
Since omap_control_usbotg devicetree node is no longer used, remove
it.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/omap4.dtsi |8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index d0e0960..3bc77b1 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -852,12 +852,6 @@
};
};
- omap_control_usbotg: control-phy@4a00233c {
- compatible = ti,control-phy-otghs;
- reg = 0x4a00233c 0x4;
- reg-names = otghs_control;
- };
-
usb_otg_hs: usb_otg_hs@4a0ab000 {
compatible = ti,omap4-musb;
reg = 0x4a0ab000 0x7ff;
@@ -870,7 +864,7 @@
multipoint = 1;
num-eps = 16;
ram-bits = 12;
- ctrl-module = omap_control_usbotg;
+ syscon-otghs = scm_conf 0x33c;
};
aes: aes@4b501000 {
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 12/17] ARM: dts: dra7: Use syscon-phy-power instead of ctrl-module in USB PHY node
Add syscon-phy-power property and remove the deprecated ctrl-module
property from USB PHY devicetree nodes.
Since omap_control_usb2phy1, omap_control_usb3phy1 and
omap_control_usb2phy2 devicetree nodes are no longer used, remove it.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 24 +++-
1 file changed, 3 insertions(+), 21 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index a8ee829..e82ac00 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1196,24 +1196,6 @@
clocks = sys_32k_ck;
};
- omap_control_usb2phy1: control-phy@4a002300 {
- compatible = ti,control-phy-usb2;
- reg = 0x4a002300 0x4;
- reg-names = power;
- };
-
- omap_control_usb3phy1: control-phy@4a002370 {
- compatible = ti,control-phy-pipe3;
- reg = 0x4a002370 0x4;
- reg-names = power;
- };
-
- omap_control_usb2phy2: control-phy@0x4a002e74 {
- compatible = ti,control-phy-usb2-dra7;
- reg = 0x4a002e74 0x4;
- reg-names = power;
- };
-
/* OCP2SCP1 */
ocp2scp@4a08 {
compatible = ti,omap-ocp2scp;
@@ -1226,7 +1208,7 @@
usb2_phy1: phy@4a084000 {
compatible = ti,omap-usb2;
reg = 0x4a084000 0x400;
- ctrl-module = omap_control_usb2phy1;
+ syscon-phy-power = dra7_ctrl_core 0x300;
clocks = usb_phy1_always_on_clk32k,
usb_otg_ss1_refclk960m;
clock-names = wkupclk,
@@ -1237,7 +1219,7 @@
usb2_phy2: phy@4a085000 {
compatible = ti,dra7x-usb2-phy2,
ti,omap-usb2;
reg = 0x4a085000 0x400;
- ctrl-module = omap_control_usb2phy2;
+ syscon-phy-power = dra7_ctrl_general 0x74;
clocks = usb_phy2_always_on_clk32k,
usb_otg_ss2_refclk960m;
clock-names = wkupclk,
@@ -1251,7 +1233,7 @@
0x4a084800 0x64,
0x4a084c00 0x40;
reg-names = phy_rx, phy_tx, pll_ctrl;
- ctrl-module = omap_control_usb3phy1;
+ syscon-phy-power = dra7_ctrl_core 0x370;
clocks = usb_phy3_always_on_clk32k,
sys_clkin1,
usb_otg_ss1_refclk960m;
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 15/17] ARM: dts: OMAP5: Use syscon-phy-power instead of ctrl-module in SATA PHY node
Add syscon-phy-power property and remove the deprecated ctrl-module
property from SATA PHY node.
Since omap_control_sata devicetree node is no longer used, remove it.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/omap5.dtsi | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 9b50314..ca0a77f 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -944,14 +944,6 @@
#thermal-sensor-cells = 1;
};
- omap_control_sata: control-phy@4a002374 {
- compatible = ti,control-phy-pipe3;
- reg = 0x4a002374 0x4;
- reg-names = power;
- clocks = sys_clkin;
- clock-names = sysclk;
- };
-
/* OCP2SCP3 */
ocp2scp@4a09 {
compatible = ti,omap-ocp2scp;
@@ -966,7 +958,7 @@
0x4A096400 0x64, /* phy_tx */
0x4A096800 0x40; /* pll_ctrl */
reg-names = phy_rx, phy_tx, pll_ctrl;
- ctrl-module = omap_control_sata;
+ syscon-phy-power = scm_conf 0x374;
clocks = sys_clkin, sata_ref_clk;
clock-names = sysclk, refclk;
#phy-cells = 0;
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 08/17] ARM: dts: dra7: Add dt node for the sycon pcie
Add new device tree node for the control module register space where
PCIe registers are present.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 260f300..3f434f7 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -291,6 +291,11 @@
reg = 0x4a002e00 0x7c;
};
+ dra7_ctrl_pcie: tisyscon@4a003c00 {
+ compatible = syscon;
+ reg = 0x4a003c00 0x48;
+ };
+
sdma: dma-controller@4a056000 {
compatible = ti,omap4430-sdma;
reg = 0x4a056000 0x1000;
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 14/17] ARM: dts: OMAP5: Use syscon-phy-power instead of ctrl-module in USB PHY node
Add syscon-phy-power property and remove the deprecated ctrl-module
property from USB PHY devicetree node.
Since omap_control_usb2phy and omap_control_usb3phy devicetree nodes
are no longer used, remove it.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/omap5.dtsi | 16 ++--
1 file changed, 2 insertions(+), 14 deletions(-)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 7d24ae0..9b50314 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -846,18 +846,6 @@
hw-caps-temp-alert;
};
- omap_control_usb2phy: control-phy@4a002300 {
- compatible = ti,control-phy-usb2;
- reg = 0x4a002300 0x4;
- reg-names = power;
- };
-
- omap_control_usb3phy: control-phy@4a002370 {
- compatible = ti,control-phy-pipe3;
- reg = 0x4a002370 0x4;
- reg-names = power;
- };
-
usb3: omap_dwc3@4a02 {
compatible = ti,dwc3;
ti,hwmods = usb_otg_ss;
@@ -888,7 +876,7 @@
usb2_phy: usb2phy@4a084000 {
compatible = ti,omap-usb2;
reg = 0x4a084000 0x7c;
- ctrl-module = omap_control_usb2phy;
+ syscon-phy-power = scm_conf 0x300;
clocks = usb_phy_cm_clk32k,
usb_otg_ss_refclk960m;
clock-names = wkupclk, refclk;
#phy-cells = 0;
@@ -900,7 +888,7 @@
0x4a084800 0x64,
0x4a084c00 0x40;
reg-names = phy_rx, phy_tx, pll_ctrl;
- ctrl-module = omap_control_usb3phy;
+ syscon-phy-power = scm_conf 0x370;
clocks = usb_phy_cm_clk32k,
sys_clkin,
usb_otg_ss_refclk960m;
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 06/17] phy: omap-usb2: use *syscon* framework to power on/off the PHY
Deprecate using phy-omap-control driver to power on/off the PHY,
and use *syscon* framework to do the same. This handles
powering on/off the PHY for the USB2 PHYs used in various TI SoCs.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt |6 +-
drivers/phy/phy-omap-usb2.c | 101 ++
include/linux/phy/omap_usb.h | 18
3 files changed, 107 insertions(+), 18 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index b9101b9..5bfe461 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -42,10 +42,14 @@ Required properties:
* wkupclk - wakeup clock.
* refclk - reference clock (optional).
-Optional properties:
+Deprecated properties:
- ctrl-module : phandle of the control module used by PHY driver to power on
the PHY.
+Recommended properies:
+- syscon-phy-power : phandle/offset pair. Phandle to the system control
+ module and the register offset to power on/off the PHY.
+
This is usually a subnode of ocp2scp to which it is connected.
usb2phy@4a0ad080 {
diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
index 2f7220f..180b066 100644
--- a/drivers/phy/phy-omap-usb2.c
+++ b/drivers/phy/phy-omap-usb2.c
@@ -29,6 +29,8 @@
#include linux/delay.h
#include linux/phy/omap_control_phy.h
#include linux/phy/phy.h
+#include linux/mfd/syscon.h
+#include linux/regmap.h
#include linux/of_platform.h
#define USB2PHY_DISCON_BYP_LATCH (1 31)
@@ -97,22 +99,65 @@ static int omap_usb_set_peripheral(struct usb_otg *otg,
return 0;
}
-static int omap_usb_power_off(struct phy *x)
+static int omap_usb_phy_power(struct omap_usb *phy, int on)
{
- struct omap_usb *phy = phy_get_drvdata(x);
+ u32 val = 0;
+ u32 mask;
+ int ret;
- omap_control_phy_power(phy-control_dev, 0);
+ if (phy-syscon_phy_power) {
+ switch (phy-type) {
+ case TYPE_USB2:
+ mask = OMAP_DEV_PHY_PD;
+ if (!on)
+ val = OMAP_DEV_PHY_PD;
+ break;
+ case TYPE_DRA7USB2:
+ mask = OMAP_USB2_PHY_PD;
+ if (!on)
+ val = OMAP_USB2_PHY_PD;
+ break;
+ case TYPE_AM437USB2:
+ mask = AM437X_USB2_PHY_PD |
+ AM437X_USB2_OTG_PD |
+ AM437X_USB2_OTGVDET_EN |
+ AM437X_USB2_OTGSESSEND_EN;
+ if (on) {
+ val = AM437X_USB2_OTGVDET_EN |
+ AM437X_USB2_OTGSESSEND_EN;
+ } else {
+ val = AM437X_USB2_PHY_PD | AM437X_USB2_OTG_PD;
+ }
+ break;
+ default:
+ dev_err(phy-dev, %s: type %d not recognized\n,
+ __func__, phy-type);
+ return -EINVAL;
+ }
+
+ ret = regmap_update_bits(phy-syscon_phy_power, phy-power_reg,
+mask, val);
+ if (ret 0)
+ return ret;
+ } else {
+ omap_control_phy_power(phy-control_dev, on);
+ }
return 0;
}
-static int omap_usb_power_on(struct phy *x)
+static int omap_usb_power_off(struct phy *x)
{
struct omap_usb *phy = phy_get_drvdata(x);
- omap_control_phy_power(phy-control_dev, 1);
+ return omap_usb_phy_power(phy, false);
+}
- return 0;
+static int omap_usb_power_on(struct phy *x)
+{
+ struct omap_usb *phy = phy_get_drvdata(x);
+
+ return omap_usb_phy_power(phy, true);
}
static int omap_usb_init(struct phy *x)
@@ -147,26 +192,31 @@ static struct phy_ops ops = {
static const struct usb_phy_data omap_usb2_data = {
.label = omap_usb2,
.flags = OMAP_USB2_HAS_START_SRP | OMAP_USB2_HAS_SET_VBUS,
+ .type = TYPE_USB2,
};
static const struct usb_phy_data omap5_usb2_data = {
.label = omap5_usb2,
.flags = 0,
+ .type = TYPE_USB2,
};
static const struct usb_phy_data dra7x_usb2_data = {
.label = dra7x_usb2,
.flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
+ .type = TYPE_USB2,
};
static const struct usb_phy_data dra7x_usb2_phy2_data = {
.label = dra7x_usb2_phy2,
.flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
+ .type = TYPE_DRA7USB2,
};
static const struct usb_phy_data am437x_usb2_data = {
.label = am437x_usb2,
.flags = 0,
+ .type = TYPE_AM437USB2,
};
static const struct of_device_id omap_usb2_id_table
[PATCH 02/17] phy: ti-pipe3: use *syscon* framework to power on/off the PHY
Deprecate using phy-omap-control driver to power on/off the PHY and
use *syscon* framework to do the same.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 10 ++-
drivers/phy/phy-ti-pipe3.c | 91 ++
2 files changed, 86 insertions(+), 15 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index f0f5537..d3ad3bf 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -77,8 +77,6 @@ Required properties:
* div-clk - apll clock
Optional properties:
- - ctrl-module : phandle of the control module used by PHY driver to power on
- the PHY.
- id: If there are multiple instance of the same type, in order to
differentiate between each instance id can be used (e.g., multi-lane PCIe
PHY). If id is not provided, it is set to default value of '1'.
@@ -86,6 +84,14 @@ Optional properties:
CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0
register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy.
+Deprecated properties:
+ - ctrl-module : phandle of the control module used by PHY driver to power on
+ the PHY.
+
+Recommended properies:
+ - syscon-phy-power : phandle/offset pair. Phandle to the system control
+ module and the register offset to power on/off the PHY.
+
This is usually a subnode of ocp2scp to which it is connected.
usb3phy@4a084400 {
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index d784426..78bac00 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -56,6 +56,15 @@
#define SATA_PLL_SOFT_RESETBIT(18)
+#define PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
+#define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 14
+
+#define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC0
+#define PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT22
+
+#define PIPE3_PHY_TX_RX_POWERON0x3
+#define PIPE3_PHY_TX_RX_POWEROFF 0x0
+
/*
* This is an Empirical value that works, need to confirm the actual
* value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
@@ -86,8 +95,10 @@ struct ti_pipe3 {
struct clk *refclk;
struct clk *div_clk;
struct pipe3_dpll_map *dpll_map;
+ struct regmap *phy_power_syscon; /* ctrl. reg. acces */
struct regmap *dpll_reset_syscon; /* ctrl. reg. acces */
unsigned intdpll_reset_reg; /* reg. index within syscon */
+ unsigned intpower_reg; /* power reg. index within syscon */
boolsata_refclk_enabled;
};
@@ -144,18 +155,49 @@ static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy);
static int ti_pipe3_power_off(struct phy *x)
{
+ u32 val;
+ int ret;
struct ti_pipe3 *phy = phy_get_drvdata(x);
- omap_control_phy_power(phy-control_dev, 0);
+ if (phy-phy_power_syscon) {
+ val = PIPE3_PHY_TX_RX_POWEROFF
+ PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
+
+ ret = regmap_update_bits(phy-phy_power_syscon, phy-power_reg,
+PIPE3_PHY_PWRCTL_CLK_CMD_MASK, val);
+ if (ret 0)
+ return ret;
+ } else {
+ omap_control_phy_power(phy-control_dev, 0);
+ }
return 0;
}
static int ti_pipe3_power_on(struct phy *x)
{
+ u32 val;
+ u32 mask;
+ int ret;
+ unsigned long rate;
struct ti_pipe3 *phy = phy_get_drvdata(x);
- omap_control_phy_power(phy-control_dev, 1);
+ if (phy-phy_power_syscon) {
+ rate = clk_get_rate(phy-sys_clk);
+ rate = rate / 100;
+ mask = OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
+ OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK;
+ val = PIPE3_PHY_TX_RX_POWERON
+ PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
+ val |= rate OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
+
+ ret = regmap_update_bits(phy-phy_power_syscon, phy-power_reg,
+mask, val);
+ if (ret 0)
+ return ret;
+ } else {
+ omap_control_phy_power(phy-control_dev, 1);
+ }
return 0;
}
@@ -417,19 +459,42 @@ static int ti_pipe3_probe(struct platform_device *pdev)
phy-div_clk = ERR_PTR(-ENODEV);
}
- control_node = of_parse_phandle(node, ctrl-module, 0);
- if (!control_node) {
- dev_err(pdev-dev, Failed to get control device phandle\n);
- return -EINVAL;
- }
+ phy-phy_power_syscon = syscon_regmap_lookup_by_phandle(node,
+ syscon-phy-power
[PATCH 00/17] Deprecate phy-omap-control and use SYSCON
phy-omap-control driver was added when there was no proper infrastructure for doing control module initializations. Now with SYSCON framework being added to the kernel, phy-omap-control shouldn't be needed. This series is about adapting phy-omap-usb2, phy-ti-pipe3 and omap2430 to use SYSCON framework instead of phy-omap-control. However we can't remove the phy-omap-control driver altogether since that will break older dtbs. Performed USB enumeration testing in DRA72-EVM, AM43XX-EVM, OMAP5-uEVM and OMAP4 PANDA. Performed SATA enumeration testing in DRA72-EVM and OMAP5-uEVM Performed PCIe enumeration testing in DRA72-EVM. This patch series is developed on top of Linux 4.1-rc8 + http://lkml.iu.edu/hypermail/linux/kernel/1505.1/03099.html Kishon Vijay Abraham I (17): phy: ti-pipe3: use ti_pipe3_power_off to power off the PHY during probe phy: ti-pipe3: use *syscon* framework to power on/off the PHY phy: ti-pipe3: use *syscon* framework to set PCS value of the PHY phy: omap-usb2: use omap_usb_power_off to power off the PHY during probe phy: omap-usb2: Add a new compatible string for USB2 PHY2 phy: omap-usb2: use *syscon* framework to power on/off the PHY usb: musb: omap2430: use *syscon* framework to write to mailbox register ARM: dts: dra7: Add dt node for the sycon pcie ARM: dts: dra7: Use syscon-phy-power instead of ctrl-module in SATA PHY node ARM: dts: dra7: Use syscon-phy-power and syscon-pcs in PCIe PHY node ARM: dts: dra7: Use ti,dra7x-usb2-phy2 compatible string for USB2 PHY2 ARM: dts: dra7: Use syscon-phy-power instead of ctrl-module in USB PHY node ARM: dts: am4372: Use syscon-phy-power instead of ctrl-module in USB PHY node ARM: dts: OMAP5: Use syscon-phy-power instead of ctrl-module in USB PHY node ARM: dts: OMAP5: Use syscon-phy-power instead of ctrl-module in SATA PHY node ARM: dts: omap4: Use syscon-phy-power instead of ctrl-module in USB PHY node ARM: dts: omap4: Use syscon-otghs instead of ctrl-module in USB node Documentation/devicetree/bindings/phy/ti-phy.txt | 20 +++- Documentation/devicetree/bindings/usb/omap-usb.txt |7 +- arch/arm/boot/dts/am4372.dtsi | 16 +-- arch/arm/boot/dts/dra7.dtsi| 69 +++ arch/arm/boot/dts/omap4.dtsi | 16 +-- arch/arm/boot/dts/omap5.dtsi | 26 +--- drivers/phy/phy-omap-usb2.c| 112 +++--- drivers/phy/phy-ti-pipe3.c | 125 +--- drivers/usb/musb/omap2430.c| 118 ++ include/linux/phy/omap_usb.h | 18 +++ 10 files changed, 365 insertions(+), 162 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 11/17] ARM: dts: dra7: Use ti,dra7x-usb2-phy2 compatible string for USB2 PHY2
The USB2 PHY2 has a different register map compared to USB2 PHY1
to power on/off the PHY. In order to handle it, use the new compatible
string ti,dra7x-usb2-phy2 for the second instance of USB2 PHY.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index f69db70..a8ee829 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1235,7 +1235,7 @@
};
usb2_phy2: phy@4a085000 {
- compatible = ti,omap-usb2;
+ compatible = ti,dra7x-usb2-phy2,
ti,omap-usb2;
reg = 0x4a085000 0x400;
ctrl-module = omap_control_usb2phy2;
clocks = usb_phy2_always_on_clk32k,
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 04/17] phy: omap-usb2: use omap_usb_power_off to power off the PHY during probe
No functional change. Previously omap_control_phy_power() was used to power off the PHY during probe. But once phy-omap-usb2 driver is adapted to use syscon, omap_control_phy_power() cannot be used. Hence used omap_usb_power_off to power off the PHY. Signed-off-by: Kishon Vijay Abraham I kis...@ti.com --- drivers/phy/phy-omap-usb2.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c index c1a4686..b5c266a 100644 --- a/drivers/phy/phy-omap-usb2.c +++ b/drivers/phy/phy-omap-usb2.c @@ -241,7 +241,6 @@ static int omap_usb2_probe(struct platform_device *pdev) } phy-control_dev = control_pdev-dev; - omap_control_phy_power(phy-control_dev, 0); otg-set_host = omap_usb_set_host; otg-set_peripheral = omap_usb_set_peripheral; @@ -261,6 +260,7 @@ static int omap_usb2_probe(struct platform_device *pdev) } phy_set_drvdata(generic_phy, phy); + omap_usb_power_off(generic_phy); phy_provider = devm_of_phy_provider_register(phy-dev, of_phy_simple_xlate); -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 10/17] ARM: dts: dra7: Use syscon-phy-power and syscon-pcs in PCIe PHY node
Add syscon-phy-power property and syscon-pcs property which can
be used to perform the control module initializations and remove
the deprecated ctrl-module property from PCIe PHY dt nodes.
Phandle to sysclk clock node is also added to the PCIe PHY node
since some of the syscon initializations is based on system clock
frequency.
Since omap_control_pcie1phy and omap_control_pcie2phy devicetree
nodes are no longer used, remove it.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 28 +++-
1 file changed, 7 insertions(+), 21 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 92e0741..f69db70 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1141,16 +1141,18 @@
reg = 0x4a094000 0x80, /* phy_rx */
0x4a094400 0x64; /* phy_tx */
reg-names = phy_rx, phy_tx;
- ctrl-module = omap_control_pcie1phy;
+ syscon-phy-power = dra7_ctrl_pcie 0x40;
+ syscon-pcs = dra7_ctrl_pcie 0x34;
clocks = dpll_pcie_ref_ck,
dpll_pcie_ref_m2ldo_ck,
optfclk_pciephy1_32khz,
optfclk_pciephy1_clk,
optfclk_pciephy1_div_clk,
-optfclk_pciephy_div;
+optfclk_pciephy_div,
+sys_clkin1;
clock-names = dpll_ref, dpll_ref_m2,
wkupclk, refclk,
- div-clk, phy-div;
+ div-clk, phy-div, sysclk;
#phy-cells = 0;
};
@@ -1159,7 +1161,8 @@
reg = 0x4a095000 0x80, /* phy_rx */
0x4a095400 0x64; /* phy_tx */
reg-names = phy_rx, phy_tx;
- ctrl-module = omap_control_pcie2phy;
+ syscon-phy-power = dra7_ctrl_pcie 0x44;
+ syscon-pcs = dra7_ctrl_pcie 0x34;
clocks = dpll_pcie_ref_ck,
dpll_pcie_ref_m2ldo_ck,
optfclk_pciephy2_32khz,
@@ -1184,23 +1187,6 @@
ti,hwmods = sata;
};
- omap_control_pcie1phy: control-phy@0x4a003c40 {
- compatible = ti,control-phy-pcie;
- reg = 0x4a003c40 0x4, 0x4a003c14 0x4, 0x4a003c34
0x4;
- reg-names = power, control_sma, pcie_pcs;
- clocks = sys_clkin1;
- clock-names = sysclk;
- };
-
- omap_control_pcie2phy: control-pcie@0x4a003c44 {
- compatible = ti,control-phy-pcie;
- reg = 0x4a003c44 0x4, 0x4a003c14 0x4, 0x4a003c34
0x4;
- reg-names = power, control_sma, pcie_pcs;
- clocks = sys_clkin1;
- clock-names = sysclk;
- status = disabled;
- };
-
rtc: rtc@48838000 {
compatible = ti,am3352-rtc;
reg = 0x48838000 0x100;
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 07/17] usb: musb: omap2430: use *syscon* framework to write to mailbox register
Deprecate using phy-omap-control driver to write to the mailbox register
and start using *syscon* framework to do the same.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/usb/omap-usb.txt |7 +-
drivers/usb/musb/omap2430.c| 118
2 files changed, 102 insertions(+), 23 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt
b/Documentation/devicetree/bindings/usb/omap-usb.txt
index 38d9bb8..c001306 100644
--- a/Documentation/devicetree/bindings/usb/omap-usb.txt
+++ b/Documentation/devicetree/bindings/usb/omap-usb.txt
@@ -20,10 +20,15 @@ OMAP MUSB GLUE
- phy-names : the names of the PHY corresponding to the PHYs present in the
*phy* phandle.
-Optional properties:
+Optional Properties:
+Deprecated properties:
- ctrl-module : phandle of the control module this glue uses to write to
mailbox
+Recommended properies:
+ - syscon-otghs : phandle/offset pair. Phandle to the system control module
and the
+ register offset of the mailbox.
+
SOC specific device node entry
usb_otg_hs: usb_otg_hs@4a0ab000 {
compatible = ti,omap4-musb;
diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
index cc752d8..bcd6d1e 100644
--- a/drivers/usb/musb/omap2430.c
+++ b/drivers/usb/musb/omap2430.c
@@ -39,16 +39,27 @@
#include linux/usb/musb-omap.h
#include linux/phy/omap_control_phy.h
#include linux/of_platform.h
+#include linux/regmap.h
+#include linux/mfd/syscon.h
#include musb_core.h
#include omap2430.h
+#define OMAP2430_MUSB_MODE_MASK0x1f
+#define OMAP2430_MUSB_AVALID (0x1 0)
+#define OMAP2430_MUSB_BVALID (0x1 1)
+#define OMAP2430_MUSB_VBUSVALID(0x1 2)
+#define OMAP2430_MUSB_SESSEND (0x1 3)
+#define OMAP2430_MUSB_IDDIG(0x1 4)
+
struct omap2430_glue {
struct device *dev;
struct platform_device *musb;
enum omap_musb_vbus_id_status status;
struct work_struct omap_musb_mailbox_work;
struct device *control_otghs;
+ struct regmap *syscon_otghs; /* ctrl. reg. acces */
+ unsigned intotghs_reg; /* otghs reg. index within syscon */
};
#define glue_to_musb(g)platform_get_drvdata(g-musb)
@@ -253,6 +264,47 @@ void omap_musb_mailbox(enum omap_musb_vbus_id_status
status)
}
EXPORT_SYMBOL_GPL(omap_musb_mailbox);
+static void omap2430_musb_set_usbmode(struct omap2430_glue *glue,
+ enum omap_control_usb_mode mode)
+{
+ u32 val;
+ int ret;
+
+ if (glue-syscon_otghs) {
+ switch (mode) {
+ case USB_MODE_HOST:
+ val = OMAP2430_MUSB_AVALID | OMAP2430_MUSB_VBUSVALID;
+ break;
+
+ case USB_MODE_DEVICE:
+ val = OMAP2430_MUSB_IDDIG | OMAP2430_MUSB_AVALID |
+ OMAP2430_MUSB_VBUSVALID;
+ break;
+
+ case USB_MODE_DISCONNECT:
+ val = OMAP2430_MUSB_IDDIG | OMAP2430_MUSB_SESSEND;
+ break;
+
+ default:
+ dev_dbg(glue-dev, Invalid mode\n);
+ goto err_regmap_update;
+ }
+
+ ret = regmap_update_bits(glue-syscon_otghs,
+glue-otghs_reg,
+OMAP2430_MUSB_MODE_MASK, val);
+ if (ret 0)
+ goto err_regmap_update;
+ } else {
+ omap_control_usb_set_mode(glue-control_otghs, mode);
+ }
+
+ return;
+
+err_regmap_update:
+ dev_err(glue-dev, Failed to set mode to %d\n, mode);
+}
+
static void omap_musb_set_mailbox(struct omap2430_glue *glue)
{
struct musb *musb = glue_to_musb(glue);
@@ -270,8 +322,7 @@ static void omap_musb_set_mailbox(struct omap2430_glue
*glue)
musb-xceiv-last_event = USB_EVENT_ID;
if (musb-gadget_driver) {
pm_runtime_get_sync(dev);
- omap_control_usb_set_mode(glue-control_otghs,
- USB_MODE_HOST);
+ omap2430_musb_set_usbmode(glue, USB_MODE_HOST);
omap2430_musb_set_vbus(musb, 1);
}
break;
@@ -284,7 +335,7 @@ static void omap_musb_set_mailbox(struct omap2430_glue
*glue)
musb-xceiv-last_event = USB_EVENT_VBUS;
if (musb-gadget_driver)
pm_runtime_get_sync(dev);
- omap_control_usb_set_mode(glue-control_otghs, USB_MODE_DEVICE);
+ omap2430_musb_set_usbmode(glue, USB_MODE_DEVICE);
break;
case OMAP_MUSB_ID_FLOAT:
@@ -301,8 +352,7 @@ static void omap_musb_set_mailbox(struct omap2430_glue
*glue)
if (data-interface_type
[PATCH 03/17] phy: ti-pipe3: use *syscon* framework to set PCS value of the PHY
Deprecate using phy-omap-control driver to set PCS value of the PHY
and start using *syscon* framework to do the same.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt |2 ++
drivers/phy/phy-ti-pipe3.c | 32 +-
2 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index d3ad3bf..52c7a92 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -83,6 +83,8 @@ Optional properties:
- syscon-pllreset: Handle to system control region that contains the
CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0
register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy.
+ - syscon-pcs : phandle/offset pair. Phandle to the system control module and
the
+ register offset to write the PCS delay value.
Deprecated properties:
- ctrl-module : phandle of the control module used by PHY driver to power on
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index 78bac00..e2f9ad7 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -65,6 +65,9 @@
#define PIPE3_PHY_TX_RX_POWERON0x3
#define PIPE3_PHY_TX_RX_POWEROFF 0x0
+#define PCIE_PCS_MASK 0xFF
+#define PCIE_PCS_DELAY_COUNT_SHIFT 0x10
+
/*
* This is an Empirical value that works, need to confirm the actual
* value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
@@ -96,9 +99,11 @@ struct ti_pipe3 {
struct clk *div_clk;
struct pipe3_dpll_map *dpll_map;
struct regmap *phy_power_syscon; /* ctrl. reg. acces */
+ struct regmap *pcs_syscon; /* ctrl. reg. acces */
struct regmap *dpll_reset_syscon; /* ctrl. reg. acces */
unsigned intdpll_reset_reg; /* reg. index within syscon */
unsigned intpower_reg; /* power reg. index within syscon */
+ unsigned intpcie_pcs_reg; /* pcs reg. index in syscon */
boolsata_refclk_enabled;
};
@@ -271,7 +276,16 @@ static int ti_pipe3_init(struct phy *x)
* 18-1804.
*/
if (of_device_is_compatible(phy-dev-of_node, ti,phy-pipe3-pcie)) {
- omap_control_pcie_pcs(phy-control_dev, 0x96);
+ if (phy-pcs_syscon) {
+ val = 0x96 OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT;
+ ret = regmap_update_bits(phy-pcs_syscon,
+phy-pcie_pcs_reg,
+PCIE_PCS_MASK, val);
+ if (ret 0)
+ return ret;
+ } else {
+ omap_control_pcie_pcs(phy-control_dev, 0x96);
+ }
return 0;
}
@@ -455,6 +469,22 @@ static int ti_pipe3_probe(struct platform_device *pdev)
dev_err(pdev-dev, unable to get div-clk\n);
return PTR_ERR(phy-div_clk);
}
+
+ phy-pcs_syscon = syscon_regmap_lookup_by_phandle(node,
+ syscon-pcs);
+ if (IS_ERR(phy-pcs_syscon)) {
+ dev_dbg(pdev-dev,
+can't get syscon-pcs, using omap control\n);
+ phy-pcs_syscon = NULL;
+ } else {
+ if (of_property_read_u32_index(node,
+ syscon-pcs, 1,
+ phy-pcie_pcs_reg)) {
+ dev_err(pdev-dev,
+ couldn't get pcie pcs reg. offset\n);
+ return -EINVAL;
+ }
+ }
} else {
phy-div_clk = ERR_PTR(-ENODEV);
}
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 01/17] phy: ti-pipe3: use ti_pipe3_power_off to power off the PHY during probe
No functional change. Previously omap_control_phy_power() was used to power off the PHY during probe. But once PIPE3 driver is adapted to use syscon, omap_control_phy_power() cannot be used. Hence used ti_pipe3_power_off to power off the PHY. Signed-off-by: Kishon Vijay Abraham I kis...@ti.com --- drivers/phy/phy-ti-pipe3.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c index 08020dc..d784426 100644 --- a/drivers/phy/phy-ti-pipe3.c +++ b/drivers/phy/phy-ti-pipe3.c @@ -431,8 +431,6 @@ static int ti_pipe3_probe(struct platform_device *pdev) phy-control_dev = control_pdev-dev; - omap_control_phy_power(phy-control_dev, 0); - platform_set_drvdata(pdev, phy); pm_runtime_enable(phy-dev); @@ -451,6 +449,8 @@ static int ti_pipe3_probe(struct platform_device *pdev) return PTR_ERR(generic_phy); phy_set_drvdata(generic_phy, phy); + ti_pipe3_power_off(generic_phy); + phy_provider = devm_of_phy_provider_register(phy-dev, of_phy_simple_xlate); if (IS_ERR(phy_provider)) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 06/17] phy: omap-usb2: use *syscon* framework to power on/off the PHY
Hi,
On Wednesday 24 June 2015 05:03 PM, Roger Quadros wrote:
On Tue, 23 Jun 2015 17:28:51 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
Deprecate using phy-omap-control driver to power on/off the PHY,
and use *syscon* framework to do the same. This handles
powering on/off the PHY for the USB2 PHYs used in various TI SoCs.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt |6 +-
drivers/phy/phy-omap-usb2.c | 101
++
include/linux/phy/omap_usb.h | 18
3 files changed, 107 insertions(+), 18 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index b9101b9..5bfe461 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -42,10 +42,14 @@ Required properties:
* wkupclk - wakeup clock.
* refclk - reference clock (optional).
-Optional properties:
+Deprecated properties:
- ctrl-module : phandle of the control module used by PHY driver to power
on
the PHY.
+Recommended properies:
+- syscon-phy-power : phandle/offset pair. Phandle to the system control
+ module and the register offset to power on/off the PHY.
+
This is usually a subnode of ocp2scp to which it is connected.
usb2phy@4a0ad080 {
diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
index 2f7220f..180b066 100644
--- a/drivers/phy/phy-omap-usb2.c
+++ b/drivers/phy/phy-omap-usb2.c
@@ -29,6 +29,8 @@
#include linux/delay.h
#include linux/phy/omap_control_phy.h
#include linux/phy/phy.h
+#include linux/mfd/syscon.h
+#include linux/regmap.h
#include linux/of_platform.h
#define USB2PHY_DISCON_BYP_LATCH (1 31)
@@ -97,22 +99,65 @@ static int omap_usb_set_peripheral(struct usb_otg *otg,
return 0;
}
-static int omap_usb_power_off(struct phy *x)
+static int omap_usb_phy_power(struct omap_usb *phy, int on)
{
-struct omap_usb *phy = phy_get_drvdata(x);
+u32 val = 0;
+u32 mask;
+int ret;
-omap_control_phy_power(phy-control_dev, 0);
+if (phy-syscon_phy_power) {
+switch (phy-type) {
+case TYPE_USB2:
+mask = OMAP_DEV_PHY_PD;
+if (!on)
+val = OMAP_DEV_PHY_PD;
+break;
+case TYPE_DRA7USB2:
+mask = OMAP_USB2_PHY_PD;
+if (!on)
+val = OMAP_USB2_PHY_PD;
+break;
+case TYPE_AM437USB2:
+mask = AM437X_USB2_PHY_PD |
+AM437X_USB2_OTG_PD |
+AM437X_USB2_OTGVDET_EN |
+AM437X_USB2_OTGSESSEND_EN;
+if (on) {
+val = AM437X_USB2_OTGVDET_EN |
+AM437X_USB2_OTGSESSEND_EN;
+} else {
+val = AM437X_USB2_PHY_PD | AM437X_USB2_OTG_PD;
+}
+break;
+default:
+dev_err(phy-dev, %s: type %d not recognized\n,
+__func__, phy-type);
+return -EINVAL;
+}
+
+ret = regmap_update_bits(phy-syscon_phy_power, phy-power_reg,
+ mask, val);
+if (ret 0)
+return ret;
+} else {
+omap_control_phy_power(phy-control_dev, on);
+}
return 0;
}
-static int omap_usb_power_on(struct phy *x)
+static int omap_usb_power_off(struct phy *x)
{
struct omap_usb *phy = phy_get_drvdata(x);
-omap_control_phy_power(phy-control_dev, 1);
+return omap_usb_phy_power(phy, false);
+}
-return 0;
+static int omap_usb_power_on(struct phy *x)
+{
+struct omap_usb *phy = phy_get_drvdata(x);
+
+return omap_usb_phy_power(phy, true);
}
static int omap_usb_init(struct phy *x)
@@ -147,26 +192,31 @@ static struct phy_ops ops = {
static const struct usb_phy_data omap_usb2_data = {
.label = omap_usb2,
.flags = OMAP_USB2_HAS_START_SRP | OMAP_USB2_HAS_SET_VBUS,
+.type = TYPE_USB2,
};
static const struct usb_phy_data omap5_usb2_data = {
.label = omap5_usb2,
.flags = 0,
+.type = TYPE_USB2,
};
static const struct usb_phy_data dra7x_usb2_data = {
.label = dra7x_usb2,
.flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
+.type = TYPE_USB2,
};
static const struct usb_phy_data dra7x_usb2_phy2_data = {
.label = dra7x_usb2_phy2,
.flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
+.type = TYPE_DRA7USB2,
};
static const struct usb_phy_data am437x_usb2_data = {
.label = am437x_usb2
Re: [PATCH 02/17] phy: ti-pipe3: use *syscon* framework to power on/off the PHY
Hi,
On Tuesday 23 June 2015 08:23 PM, Roger Quadros wrote:
Hi Kishon,
On Tue, 23 Jun 2015 17:28:47 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
Deprecate using phy-omap-control driver to power on/off the PHY and
use *syscon* framework to do the same.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 10 ++-
drivers/phy/phy-ti-pipe3.c | 91 ++
2 files changed, 86 insertions(+), 15 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index f0f5537..d3ad3bf 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -77,8 +77,6 @@ Required properties:
* div-clk - apll clock
Optional properties:
- - ctrl-module : phandle of the control module used by PHY driver to power on
- the PHY.
- id: If there are multiple instance of the same type, in order to
differentiate between each instance id can be used (e.g., multi-lane PCIe
PHY). If id is not provided, it is set to default value of '1'.
@@ -86,6 +84,14 @@ Optional properties:
CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0
register that contains the SATA_PLL_SOFT_RESET bit. Only valid for
sata_phy.
+Deprecated properties:
+ - ctrl-module : phandle of the control module used by PHY driver to power on
+ the PHY.
+
+Recommended properies:
+ - syscon-phy-power : phandle/offset pair. Phandle to the system control
+ module and the register offset to power on/off the PHY.
+
This is usually a subnode of ocp2scp to which it is connected.
usb3phy@4a084400 {
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index d784426..78bac00 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -56,6 +56,15 @@
#define SATA_PLL_SOFT_RESET BIT(18)
+#define PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
+#define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 14
+
+#define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC0
+#define PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT22
+
+#define PIPE3_PHY_TX_RX_POWERON0x3
+#define PIPE3_PHY_TX_RX_POWEROFF 0x0
+
/*
* This is an Empirical value that works, need to confirm the actual
* value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
@@ -86,8 +95,10 @@ struct ti_pipe3 {
struct clk *refclk;
struct clk *div_clk;
struct pipe3_dpll_map *dpll_map;
+ struct regmap *phy_power_syscon; /* ctrl. reg. acces */
struct regmap *dpll_reset_syscon; /* ctrl. reg. acces */
unsigned intdpll_reset_reg; /* reg. index within syscon */
+ unsigned intpower_reg; /* power reg. index within syscon */
boolsata_refclk_enabled;
};
@@ -144,18 +155,49 @@ static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy);
static int ti_pipe3_power_off(struct phy *x)
{
+ u32 val;
+ int ret;
struct ti_pipe3 *phy = phy_get_drvdata(x);
- omap_control_phy_power(phy-control_dev, 0);
+ if (phy-phy_power_syscon) {
+ val = PIPE3_PHY_TX_RX_POWEROFF
+ PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
+
+ ret = regmap_update_bits(phy-phy_power_syscon, phy-power_reg,
+PIPE3_PHY_PWRCTL_CLK_CMD_MASK, val);
+ if (ret 0)
+ return ret;
+ } else {
+ omap_control_phy_power(phy-control_dev, 0);
+ }
return 0;
}
static int ti_pipe3_power_on(struct phy *x)
{
+ u32 val;
+ u32 mask;
+ int ret;
+ unsigned long rate;
struct ti_pipe3 *phy = phy_get_drvdata(x);
- omap_control_phy_power(phy-control_dev, 1);
+ if (phy-phy_power_syscon) {
+ rate = clk_get_rate(phy-sys_clk);
what if clk_get_rate() returns 0?
hmm.. If '0' is an error value of clk_get_rate() then it would be good to
return with an error message.
+ rate = rate / 100;
+ mask = OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
+ OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK;
+ val = PIPE3_PHY_TX_RX_POWERON
+ PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
+ val |= rate OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
+
+ ret = regmap_update_bits(phy-phy_power_syscon, phy-power_reg,
+mask, val);
+ if (ret 0)
+ return ret;
+ } else {
+ omap_control_phy_power(phy-control_dev, 1);
+ }
return 0;
}
@@ -417,19 +459,42 @@ static int ti_pipe3_probe(struct platform_device *pdev)
phy-div_clk = ERR_PTR(-ENODEV);
}
- control_node = of_parse_phandle(node, ctrl
Re: [PATCH 17/17] ARM: dts: omap4: Use syscon-otghs instead of ctrl-module in USB node
Hi Tony,
On Wednesday 24 June 2015 04:11 PM, Tony Lindgren wrote:
* Kishon Vijay Abraham I kis...@ti.com [150623 05:02]:
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -852,12 +852,6 @@
};
};
- omap_control_usbotg: control-phy@4a00233c {
- compatible = ti,control-phy-otghs;
- reg = 0x4a00233c 0x4;
- reg-names = otghs_control;
- };
-
usb_otg_hs: usb_otg_hs@4a0ab000 {
compatible = ti,omap4-musb;
reg = 0x4a0ab000 0x7ff;
@@ -870,7 +864,7 @@
multipoint = 1;
num-eps = 16;
ram-bits = 12;
- ctrl-module = omap_control_usbotg;
+ syscon-otghs = scm_conf 0x33c;
};
aes: aes@4b501000 {
We should still keep a separate entry for the phy in the dtsi
files. And the phy should be a child of the scm_conf area in the
dtsi file.
This is because the scm and usb_otg_hs are separate devices and
can be clocked separately. So the phy driver needs to be a
separate driver to avoid spaghetti code and issues with clocking.
AFAIK SCM is clocked by L4CFG_L4_GICLK which is either free running or is
managed automatically by the HW i.e gated when there is no access to the
CTRL_MODULE_CORE registers.
Having a separate control-PHY driver only to do a regmap update to SCM is
unnecessary IMHO.
Thanks
Kishon
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 07/17] usb: musb: omap2430: use *syscon* framework to write to mailbox register
Hi Tony, On Wednesday 24 June 2015 05:19 PM, Tony Lindgren wrote: * Kishon Vijay Abraham I kis...@ti.com [150623 05:02]: Deprecate using phy-omap-control driver to write to the mailbox register and start using *syscon* framework to do the same. All this stuff needs to go to some generic syscon USB phy driver. Let's not start adding phy specific stuff to a USB driver. Mailbox register is actually part of OMAP USB glue that should be written in order to inform the usbmode to the MUSB core. Thanks Kishon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 07/17] usb: musb: omap2430: use *syscon* framework to write to mailbox register
Hi,
On Wednesday 24 June 2015 05:09 PM, Roger Quadros wrote:
On Tue, 23 Jun 2015 17:28:52 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
Deprecate using phy-omap-control driver to write to the mailbox register
and start using *syscon* framework to do the same.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/usb/omap-usb.txt |7 +-
drivers/usb/musb/omap2430.c| 118
2 files changed, 102 insertions(+), 23 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt
b/Documentation/devicetree/bindings/usb/omap-usb.txt
index 38d9bb8..c001306 100644
--- a/Documentation/devicetree/bindings/usb/omap-usb.txt
+++ b/Documentation/devicetree/bindings/usb/omap-usb.txt
@@ -20,10 +20,15 @@ OMAP MUSB GLUE
- phy-names : the names of the PHY corresponding to the PHYs present in the
*phy* phandle.
-Optional properties:
+Optional Properties:
+Deprecated properties:
- ctrl-module : phandle of the control module this glue uses to write to
mailbox
+Recommended properies:
+ - syscon-otghs : phandle/offset pair. Phandle to the system control module
and the
+ register offset of the mailbox.
+
SOC specific device node entry
usb_otg_hs: usb_otg_hs@4a0ab000 {
compatible = ti,omap4-musb;
diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
index cc752d8..bcd6d1e 100644
--- a/drivers/usb/musb/omap2430.c
+++ b/drivers/usb/musb/omap2430.c
@@ -39,16 +39,27 @@
#include linux/usb/musb-omap.h
#include linux/phy/omap_control_phy.h
#include linux/of_platform.h
+#include linux/regmap.h
+#include linux/mfd/syscon.h
#include musb_core.h
#include omap2430.h
+#define OMAP2430_MUSB_MODE_MASK 0x1f
+#define OMAP2430_MUSB_AVALID(0x1 0)
+#define OMAP2430_MUSB_BVALID(0x1 1)
+#define OMAP2430_MUSB_VBUSVALID (0x1 2)
+#define OMAP2430_MUSB_SESSEND (0x1 3)
+#define OMAP2430_MUSB_IDDIG (0x1 4)
+
struct omap2430_glue {
struct device *dev;
struct platform_device *musb;
enum omap_musb_vbus_id_status status;
struct work_struct omap_musb_mailbox_work;
struct device *control_otghs;
+struct regmap *syscon_otghs; /* ctrl. reg. acces */
+unsigned intotghs_reg; /* otghs reg. index within syscon */
};
#define glue_to_musb(g) platform_get_drvdata(g-musb)
@@ -253,6 +264,47 @@ void omap_musb_mailbox(enum omap_musb_vbus_id_status
status)
}
EXPORT_SYMBOL_GPL(omap_musb_mailbox);
+static void omap2430_musb_set_usbmode(struct omap2430_glue *glue,
+ enum omap_control_usb_mode mode)
+{
+u32 val;
+int ret;
+
+if (glue-syscon_otghs) {
+switch (mode) {
+case USB_MODE_HOST:
+val = OMAP2430_MUSB_AVALID | OMAP2430_MUSB_VBUSVALID;
+break;
+
+case USB_MODE_DEVICE:
+val = OMAP2430_MUSB_IDDIG | OMAP2430_MUSB_AVALID |
+OMAP2430_MUSB_VBUSVALID;
+break;
+
+case USB_MODE_DISCONNECT:
+val = OMAP2430_MUSB_IDDIG | OMAP2430_MUSB_SESSEND;
+break;
+
+default:
+dev_dbg(glue-dev, Invalid mode\n);
+goto err_regmap_update;
+}
+
+ret = regmap_update_bits(glue-syscon_otghs,
+ glue-otghs_reg,
+ OMAP2430_MUSB_MODE_MASK, val);
+if (ret 0)
+goto err_regmap_update;
+} else {
+omap_control_usb_set_mode(glue-control_otghs, mode);
+}
+
+return;
+
+err_regmap_update:
+dev_err(glue-dev, Failed to set mode to %d\n, mode);
+}
+
static void omap_musb_set_mailbox(struct omap2430_glue *glue)
{
struct musb *musb = glue_to_musb(glue);
@@ -270,8 +322,7 @@ static void omap_musb_set_mailbox(struct omap2430_glue
*glue)
musb-xceiv-last_event = USB_EVENT_ID;
if (musb-gadget_driver) {
pm_runtime_get_sync(dev);
-omap_control_usb_set_mode(glue-control_otghs,
-USB_MODE_HOST);
+omap2430_musb_set_usbmode(glue, USB_MODE_HOST);
omap2430_musb_set_vbus(musb, 1);
}
break;
@@ -284,7 +335,7 @@ static void omap_musb_set_mailbox(struct omap2430_glue
*glue)
musb-xceiv-last_event = USB_EVENT_VBUS;
if (musb-gadget_driver)
pm_runtime_get_sync(dev);
-omap_control_usb_set_mode(glue-control_otghs, USB_MODE_DEVICE);
+omap2430_musb_set_usbmode(glue, USB_MODE_DEVICE);
break;
case OMAP_MUSB_ID_FLOAT:
@@ -301,8 +352,7
Re: [PATCH 08/17] ARM: dts: dra7: Add dt node for the sycon pcie
Hi,
On Wednesday 24 June 2015 05:26 PM, Roger Quadros wrote:
On Wed, 24 Jun 2015 14:50:17 +0300
Roger Quadros rog...@ti.com wrote:
On Tue, 23 Jun 2015 17:28:53 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
Add new device tree node for the control module register space where
PCIe registers are present.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 260f300..3f434f7 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -291,6 +291,11 @@
reg = 0x4a002e00 0x7c;
};
+ dra7_ctrl_pcie: tisyscon@4a003c00 {
+ compatible = syscon;
+ reg = 0x4a003c00 0x48;
+ };
+
Why do you need to start from 0x4a003c00?
CTRL_CORE_PCIESS1_PCS1 is at 0x4a003c24
Also, why can't this dra7_ctrl_pcie node be where scm_conf is.
Yes. I think that's the right thing to do. I saw dra7_ctrl_core and
dra7_ctrl_general and added it.
Thanks
Kishon
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 03/17] phy: ti-pipe3: use *syscon* framework to set PCS value of the PHY
Hi,
On Wednesday 24 June 2015 04:04 PM, Roger Quadros wrote:
On Tue, 23 Jun 2015 17:28:48 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
Deprecate using phy-omap-control driver to set PCS value of the PHY
and start using *syscon* framework to do the same.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt |2 ++
drivers/phy/phy-ti-pipe3.c | 32
+-
2 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index d3ad3bf..52c7a92 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -83,6 +83,8 @@ Optional properties:
- syscon-pllreset: Handle to system control region that contains the
CTRL_CORE_SMA_SW_0 register and register offset to the
CTRL_CORE_SMA_SW_0
register that contains the SATA_PLL_SOFT_RESET bit. Only valid for
sata_phy.
+ - syscon-pcs : phandle/offset pair. Phandle to the system control module
and the
+ register offset to write the PCS delay value.
What is PCS?
IIRC physical coding subsystem.
Is this valid only for PCIe? If yes we could mention it here.
This is introduced specifically for PCIe. But there are other PCS registers
with a different register map altogether for USB. I'm not sure if we will ever
have to do those settings.
Thanks
Kishon
Deprecated properties:
- ctrl-module : phandle of the control module used by PHY driver to power
on
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index 78bac00..e2f9ad7 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -65,6 +65,9 @@
#define PIPE3_PHY_TX_RX_POWERON0x3
#define PIPE3_PHY_TX_RX_POWEROFF 0x0
+#define PCIE_PCS_MASK 0xFF
+#define PCIE_PCS_DELAY_COUNT_SHIFT 0x10
+
/*
* This is an Empirical value that works, need to confirm the actual
* value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
@@ -96,9 +99,11 @@ struct ti_pipe3 {
struct clk *div_clk;
struct pipe3_dpll_map *dpll_map;
struct regmap *phy_power_syscon; /* ctrl. reg. acces */
+struct regmap *pcs_syscon; /* ctrl. reg. acces */
struct regmap *dpll_reset_syscon; /* ctrl. reg. acces */
unsigned intdpll_reset_reg; /* reg. index within syscon */
unsigned intpower_reg; /* power reg. index within syscon */
+unsigned intpcie_pcs_reg; /* pcs reg. index in syscon */
boolsata_refclk_enabled;
};
@@ -271,7 +276,16 @@ static int ti_pipe3_init(struct phy *x)
* 18-1804.
*/
if (of_device_is_compatible(phy-dev-of_node, ti,phy-pipe3-pcie)) {
-omap_control_pcie_pcs(phy-control_dev, 0x96);
+if (phy-pcs_syscon) {
+val = 0x96 OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT;
+ret = regmap_update_bits(phy-pcs_syscon,
+ phy-pcie_pcs_reg,
+ PCIE_PCS_MASK, val);
+if (ret 0)
+return ret;
+} else {
+omap_control_pcie_pcs(phy-control_dev, 0x96);
+}
return 0;
}
@@ -455,6 +469,22 @@ static int ti_pipe3_probe(struct platform_device *pdev)
dev_err(pdev-dev, unable to get div-clk\n);
return PTR_ERR(phy-div_clk);
}
+
+phy-pcs_syscon = syscon_regmap_lookup_by_phandle(node,
+ syscon-pcs);
+if (IS_ERR(phy-pcs_syscon)) {
+dev_dbg(pdev-dev,
+ can't get syscon-pcs, using omap control\n);
+phy-pcs_syscon = NULL;
+} else {
+if (of_property_read_u32_index(node,
+ syscon-pcs, 1,
+ phy-pcie_pcs_reg)) {
+dev_err(pdev-dev,
+couldn't get pcie pcs reg. offset\n);
+return -EINVAL;
+}
+}
} else {
phy-div_clk = ERR_PTR(-ENODEV);
}
--
1.7.9.5
Other than that,
Acked-by: Roger Quadros rog...@ti.com
cheers,
-roger
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 08/17] ARM: dts: dra7: Add dt node for the sycon pcie
Hi,
On Wednesday 24 June 2015 05:20 PM, Roger Quadros wrote:
On Tue, 23 Jun 2015 17:28:53 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
Add new device tree node for the control module register space where
PCIe registers are present.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 260f300..3f434f7 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -291,6 +291,11 @@
reg = 0x4a002e00 0x7c;
};
+dra7_ctrl_pcie: tisyscon@4a003c00 {
+compatible = syscon;
+reg = 0x4a003c00 0x48;
+};
+
Why do you need to start from 0x4a003c00?
CTRL_CORE_PCIESS1_PCS1 is at 0x4a003c24
Actually wanted to have minimum number of syscon dt nodes. So thought even
others can use dra7_ctrl_pcie phandle. But I looked only at dra7_ctrl_core and
dra7_ctrl_general and not scm_conf :-(
Thanks
Kishon
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 11/17] ARM: dts: dra7: Use ti,dra7x-usb2-phy2 compatible string for USB2 PHY2
Hi,
On Wednesday 24 June 2015 05:37 PM, Roger Quadros wrote:
On Tue, 23 Jun 2015 17:28:56 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
The USB2 PHY2 has a different register map compared to USB2 PHY1
to power on/off the PHY. In order to handle it, use the new compatible
string ti,dra7x-usb2-phy2 for the second instance of USB2 PHY.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index f69db70..a8ee829 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1235,7 +1235,7 @@
};
usb2_phy2: phy@4a085000 {
-compatible = ti,omap-usb2;
+compatible = ti,dra7x-usb2-phy2,
ti,omap-usb2;
Why do you want to retain ti,omap-usb2.
It is not backward compatible with it right?
The newer dtbs will anyway have ti,dra7x-usb2-phy2, so ti,omap-usb2 was
kept just for legacy reasons.
Thanks
Kishon
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 09/17] ARM: dts: dra7: Use syscon-phy-power instead of ctrl-module in SATA PHY node
On Wednesday 24 June 2015 05:42 PM, Roger Quadros wrote:
On Wed, 24 Jun 2015 15:06:02 +0300
Roger Quadros rog...@ti.com wrote:
On Tue, 23 Jun 2015 17:28:54 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
Add syscon-phy-power property and remove the deprecated ctrl-module
property from SATA PHY node. Since omap_control_sata note is no longer
used, remove it.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Acked-by: Roger Quadros rog...@ti.com
One comment though.
---
arch/arm/boot/dts/dra7.dtsi | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 3f434f7..92e0741 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1115,14 +1115,6 @@
status = disabled;
};
- omap_control_sata: control-phy@4a002374 {
- compatible = ti,control-phy-pipe3;
- reg = 0x4a002374 0x4;
- reg-names = power;
- clocks = sys_clkin1;
- clock-names = sysclk;
- };
-
/* OCP2SCP3 */
ocp2scp@4a09 {
compatible = ti,omap-ocp2scp;
@@ -1137,7 +1129,7 @@
0x4A096400 0x64, /* phy_tx */
0x4A096800 0x40; /* pll_ctrl */
reg-names = phy_rx, phy_tx, pll_ctrl;
- ctrl-module = omap_control_sata;
+ syscon-phy-power = dra7_ctrl_core 0x374;
why can't we use scm_conf instead of dra7_ctrl_core?
dra7_ctrl_core seems to be redundant and wrongly placed.
Agreed!
Thanks
Kishon
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 05/17] phy: omap-usb2: Add a new compatible string for USB2 PHY2
Hi,
On Wednesday 24 June 2015 04:33 PM, Roger Quadros wrote:
On Tue, 23 Jun 2015 17:28:50 +0530
Kishon Vijay Abraham I kis...@ti.com wrote:
The USB2 PHY2 has a different register map compared to USB2 PHY1
to power on/off the PHY. In order to handle it, add a new
compatible string.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt |2 ++
drivers/phy/phy-omap-usb2.c |9 +
2 files changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 52c7a92..b9101b9 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -31,6 +31,8 @@ OMAP USB2 PHY
Required properties:
- compatible: Should be ti,omap-usb2
+ Should be ti,dra7x-usb2-phy2 for the 2nd instance of USB2 PHY
+in DRA7x
- reg : Address and length of the register set for the device.
- #phy-cells: determine the number of cells that should be given in the
phandle while referencing this phy.
diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
index b5c266a..2f7220f 100644
--- a/drivers/phy/phy-omap-usb2.c
+++ b/drivers/phy/phy-omap-usb2.c
@@ -159,6 +159,11 @@ static const struct usb_phy_data dra7x_usb2_data = {
.flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
};
+static const struct usb_phy_data dra7x_usb2_phy2_data = {
+.label = dra7x_usb2_phy2,
+.flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
Isn't it better to define the register map in usb_phy_data
so that you don't need to check for compatible flag everytime?
We could may be define it for DRA7x USB2 PHYs but for am437x-usb2, it might not
be good.
Thanks
Kishon
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH 2/2] usb: dwc3: Add chained TRB support for ep0
Hi Felipe,
On Friday 06 February 2015 08:18 PM, Felipe Balbi wrote:
Hi,
On Fri, Feb 06, 2015 at 05:25:35PM +0530, Kishon Vijay Abraham I wrote:
dwc3 can do only max packet aligned transfers. So in case request length
is not max packet aligned and is bigger than DWC3_EP0_BOUNCE_SIZE
two chained TRBs is required to handle the transfer.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
*) Did eumeration testing with g_zero in kernel
*) Similar patch was added in u-boot. With DFU, was able to create a scenario
where the request length is not max packet aligned and is bigger than
DWC3_EP0_BOUNCE_SIZE (512 bytes). In that case, 2 chained TRBs will be used.
I really need a test case for this. If you have to patch g_zero to have
a configuration descriptor so large that it's over 512, so be it, but I
really need to have a test case exposing the problem.
sure.
I also need you to run full USB30CV (for USB2 and USB3 device), together
with Link Layer Tests (on USB3-only, clearly) using USB30CV and LeCroy's
compliance suite (there's a slight difference from USB30CV and LeCroy's
compliance, we must work with both because both are accepted test
vectors per USB-IF).
sure.
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index 24b7925..3b728b8 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -56,7 +56,7 @@ static const char *dwc3_ep0_state_string(enum dwc3_ep0_state
state)
}
static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t
buf_dma,
- u32 len, u32 type)
+ u32 len, u32 type, unsigned chain)
{
struct dwc3_gadget_ep_cmd_params params;
struct dwc3_trb *trb;
@@ -70,7 +70,10 @@ static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum,
dma_addr_t buf_dma,
return 0;
}
- trb = dwc-ep0_trb;
+ trb = dwc-ep0_trb[dep-free_slot];
+
+ if (chain)
+ dep-free_slot++;
trb-bpl = lower_32_bits(buf_dma);
trb-bph = upper_32_bits(buf_dma);
@@ -78,10 +81,17 @@ static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum,
dma_addr_t buf_dma,
trb-ctrl = type;
trb-ctrl |= (DWC3_TRB_CTRL_HWO
- | DWC3_TRB_CTRL_LST
- | DWC3_TRB_CTRL_IOC
| DWC3_TRB_CTRL_ISP_IMI);
+ if (chain)
+ trb-ctrl |= DWC3_TRB_CTRL_CHN;
+ else
+ trb-ctrl |= (DWC3_TRB_CTRL_IOC
+ | DWC3_TRB_CTRL_LST);
+
+ if (chain)
+ return 0;
+
memset(params, 0, sizeof(params));
params.param0 = upper_32_bits(dwc-ep0_trb_addr);
params.param1 = lower_32_bits(dwc-ep0_trb_addr);
@@ -302,7 +312,7 @@ void dwc3_ep0_out_start(struct dwc3 *dwc)
int ret;
ret = dwc3_ep0_start_trans(dwc, 0, dwc-ctrl_req_addr, 8,
- DWC3_TRBCTL_CONTROL_SETUP);
+ DWC3_TRBCTL_CONTROL_SETUP, false);
WARN_ON(ret 0);
}
@@ -817,6 +827,22 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
maxp = ep0-endpoint.maxpacket;
+ /* Handle the first TRB before handling the bounce buffer if the request
+* length is greater than the bounce buffer size
+*/
+ if (!IS_ALIGNED(ur-length, maxp)
+ ur-length DWC3_EP0_BOUNCE_SIZE) {
+ transfer_size = (ur-length / maxp) * maxp;
you can use ALIGN() for this which is more efficient. Note however that
this is not safe, see below.
right, I can achieve the same using ALIGN(ur-length - maxp, maxp);
+ transferred = transfer_size - length;
+ buf = (u8 *)buf + transferred;
+ ur-actual += transferred;
this is dangerous. The extra size is because you *must* align OUT to
wMaxPacketSize, so you cannot allow more than the original req-length
to be copied into buf. That bounce buffer, is really supposed to be a
Here we are not handling bounce buffer. The bounce buffer is used only for the
2nd TRB which actually programs to receive data that is less than bounce buffer
size. The 1st TRB will always be max packet aligned and the data is directly
copied to the request buffer. (However note that if the request length is less
than bounce buffer size, we'll use 1 TRB only)
To summarize..
We are splitting req-length into 2 TRB's if the req-length is not aligned to
wMaxPacketSize _and_ req-length is greater than bounce buffer size. By this
way we can make the 2nd TRB to receive data lesser than or equal to bounce
buffer size and the rest of it can be received using the 1st TRB.
Consider the following case.
ur-length = 612;
maxp = 512;
This case can't be handled by the existing bounce buffer mechanism since the
size of bounce buffer is only 512. So we program 2 TRB's.
First TRB
trb-size = 512; /* We don't need bounce buffer for this TRB since it is max
packet aligned. The data
Re: [PATCH 5/6] phy: twl4030-usb: add support for reading resistor on ID pin.
Hi,
On Thursday 16 April 2015 01:33 PM, NeilBrown wrote:
From: NeilBrown ne...@suse.de
The twl4030 phy can measure, with low precision, the
resistance-to-ground of the ID pin.
Add a function to read the value, and export the result
via sysfs.
Little sceptical about adding new sysfs entries. Do you have a good reason to
add this?
Thanks
Kishon
If the read fails, which it does sometimes, try again in 50msec.
Acked-by: Pavel Machek pa...@ucw.cz
Signed-off-by: NeilBrown ne...@suse.de
---
.../ABI/testing/sysfs-platform-twl4030-usb | 22 +++
drivers/phy/phy-twl4030-usb.c | 63
2 files changed, 85 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-platform-twl4030-usb
b/Documentation/ABI/testing/sysfs-platform-twl4030-usb
index 512c51be64ae..425d23676f8a 100644
--- a/Documentation/ABI/testing/sysfs-platform-twl4030-usb
+++ b/Documentation/ABI/testing/sysfs-platform-twl4030-usb
@@ -6,3 +6,25 @@ Description:
Possible values: on, off.
Changes are notified via select/poll.
+
+What: /sys/bus/platform/devices/*twl4030-usb/id
+Description:
+ Read-only report on measurement of USB-OTG ID pin.
+
+ The ID pin may be floating, grounded, or pulled to
+ ground by a resistor.
+
+ A very course grained reading of the resistance is
+ available. The numbers given in kilo-ohms are roughly
+ the center-point of the detected range.
+
+ Possible values are:
+ ground
+ 102k
+ 200k
+ 440k
+ floating
+ unknown
+
+ unknown indicates a problem with trying to detect
+ the resistance.
diff --git a/drivers/phy/phy-twl4030-usb.c b/drivers/phy/phy-twl4030-usb.c
index 3a707dd14238..1d6f3e70193e 100644
--- a/drivers/phy/phy-twl4030-usb.c
+++ b/drivers/phy/phy-twl4030-usb.c
@@ -379,6 +379,56 @@ static void twl4030_i2c_access(struct twl4030_usb *twl,
int on)
}
}
+enum twl4030_id_status {
+ TWL4030_GROUND,
+ TWL4030_102K,
+ TWL4030_200K,
+ TWL4030_440K,
+ TWL4030_FLOATING,
+ TWL4030_ID_UNKNOWN,
+};
+static char *twl4030_id_names[] = {
+ ground,
+ 102k,
+ 200k,
+ 440k,
+ floating,
+ unknown
+};
+
+enum twl4030_id_status twl4030_get_id(struct twl4030_usb *twl)
+{
+ int ret;
+
+ pm_runtime_get_sync(twl-dev);
+ if (twl-usb_mode == T2_USB_MODE_ULPI)
+ twl4030_i2c_access(twl, 1);
+ ret = twl4030_usb_read(twl, ULPI_OTG_CTRL);
+ if (ret 0 || !(ret ULPI_OTG_ID_PULLUP)) {
+ /* Need pull-up to read ID */
+ twl4030_usb_set_bits(twl, ULPI_OTG_CTRL,
+ULPI_OTG_ID_PULLUP);
+ mdelay(50);
+ }
+ ret = twl4030_usb_read(twl, ID_STATUS);
+ if (ret 0 || (ret 0x1f) == 0) {
+ mdelay(50);
+ ret = twl4030_usb_read(twl, ID_STATUS);
+ }
+
+ if (twl-usb_mode == T2_USB_MODE_ULPI)
+ twl4030_i2c_access(twl, 0);
+ pm_runtime_put_autosuspend(twl-dev);
+
+ if (ret 0)
+ return TWL4030_ID_UNKNOWN;
+ ret = ffs(ret) - 1;
+ if (ret TWL4030_GROUND || ret TWL4030_FLOATING)
+ return TWL4030_ID_UNKNOWN;
+
+ return ret;
+}
+
static void __twl4030_phy_power(struct twl4030_usb *twl, int on)
{
u8 pwr = twl4030_usb_read(twl, PHY_PWR_CTRL);
@@ -532,6 +582,16 @@ static ssize_t twl4030_usb_vbus_show(struct device *dev,
}
static DEVICE_ATTR(vbus, 0444, twl4030_usb_vbus_show, NULL);
+static ssize_t twl4030_usb_id_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct twl4030_usb *twl = dev_get_drvdata(dev);
+ return scnprintf(buf, PAGE_SIZE, %s\n,
+twl4030_id_names[twl4030_get_id(twl)]);
+}
+static DEVICE_ATTR(id, 0444, twl4030_usb_id_show, NULL);
+
static irqreturn_t twl4030_usb_irq(int irq, void *_twl)
{
struct twl4030_usb *twl = _twl;
@@ -709,6 +769,8 @@ static int twl4030_usb_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, twl);
if (device_create_file(pdev-dev, dev_attr_vbus))
dev_warn(pdev-dev, could not create sysfs file\n);
+ if (device_create_file(pdev-dev, dev_attr_id))
+ dev_warn(pdev-dev, could not create sysfs file\n);
ATOMIC_INIT_NOTIFIER_HEAD(twl-phy.notifier);
@@ -753,6 +815,7 @@ static int twl4030_usb_remove(struct platform_device *pdev)
pm_runtime_get_sync(twl-dev);
cancel_delayed_work(twl-id_workaround_work);
device_remove_file(twl-dev, dev_attr_vbus);
+ device_remove_file(twl-dev, dev_attr_id);
/* set transceiver mode to power on defaults */
twl4030_usb_set_mode(twl, -1);
--
To unsubscribe from this list: send the line
Re: [PATCH 5/6] phy: twl4030-usb: add support for reading resistor on ID pin.
Hi,
On Tuesday 02 June 2015 03:07 AM, NeilBrown wrote:
On Mon, 1 Jun 2015 19:06:52 +0530 Kishon Vijay Abraham I kis...@ti.com
wrote:
Hi,
On Thursday 16 April 2015 01:33 PM, NeilBrown wrote:
From: NeilBrown ne...@suse.de
The twl4030 phy can measure, with low precision, the
resistance-to-ground of the ID pin.
Add a function to read the value, and export the result
via sysfs.
Little sceptical about adding new sysfs entries. Do you have a good reason to
add this?
The hardware can report the value, so why not present it to user-space?
I originally used this with a udev rule which would configure the maximum
current based on the resistance measure - to work with the particular charger
hardware I have.
More recent patches try to do all of the max-current configuration in the
kernel, so I could live without exporting the value via sysfs if that is a
show-stopper.
I can't see where the scepticism comes from though. It is a well defined
and cleary documented feature of the hardware. Why not expose it?
ABI can never be removed or modified later. So should be really careful before
adding it.
Thanks
Kishon
Thanks,
NeilBrown
Thanks
Kishon
If the read fails, which it does sometimes, try again in 50msec.
Acked-by: Pavel Machek pa...@ucw.cz
Signed-off-by: NeilBrown ne...@suse.de
---
.../ABI/testing/sysfs-platform-twl4030-usb | 22 +++
drivers/phy/phy-twl4030-usb.c | 63
2 files changed, 85 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-platform-twl4030-usb
b/Documentation/ABI/testing/sysfs-platform-twl4030-usb
index 512c51be64ae..425d23676f8a 100644
--- a/Documentation/ABI/testing/sysfs-platform-twl4030-usb
+++ b/Documentation/ABI/testing/sysfs-platform-twl4030-usb
@@ -6,3 +6,25 @@ Description:
Possible values: on, off.
Changes are notified via select/poll.
+
+What: /sys/bus/platform/devices/*twl4030-usb/id
+Description:
+ Read-only report on measurement of USB-OTG ID pin.
+
+ The ID pin may be floating, grounded, or pulled to
+ ground by a resistor.
+
+ A very course grained reading of the resistance is
+ available. The numbers given in kilo-ohms are roughly
+ the center-point of the detected range.
+
+ Possible values are:
+ ground
+ 102k
+ 200k
+ 440k
+ floating
+ unknown
+
+ unknown indicates a problem with trying to detect
+ the resistance.
diff --git a/drivers/phy/phy-twl4030-usb.c b/drivers/phy/phy-twl4030-usb.c
index 3a707dd14238..1d6f3e70193e 100644
--- a/drivers/phy/phy-twl4030-usb.c
+++ b/drivers/phy/phy-twl4030-usb.c
@@ -379,6 +379,56 @@ static void twl4030_i2c_access(struct twl4030_usb *twl,
int on)
}
}
+enum twl4030_id_status {
+ TWL4030_GROUND,
+ TWL4030_102K,
+ TWL4030_200K,
+ TWL4030_440K,
+ TWL4030_FLOATING,
+ TWL4030_ID_UNKNOWN,
+};
+static char *twl4030_id_names[] = {
+ ground,
+ 102k,
+ 200k,
+ 440k,
+ floating,
+ unknown
+};
+
+enum twl4030_id_status twl4030_get_id(struct twl4030_usb *twl)
+{
+ int ret;
+
+ pm_runtime_get_sync(twl-dev);
+ if (twl-usb_mode == T2_USB_MODE_ULPI)
+ twl4030_i2c_access(twl, 1);
+ ret = twl4030_usb_read(twl, ULPI_OTG_CTRL);
+ if (ret 0 || !(ret ULPI_OTG_ID_PULLUP)) {
+ /* Need pull-up to read ID */
+ twl4030_usb_set_bits(twl, ULPI_OTG_CTRL,
+ULPI_OTG_ID_PULLUP);
+ mdelay(50);
+ }
+ ret = twl4030_usb_read(twl, ID_STATUS);
+ if (ret 0 || (ret 0x1f) == 0) {
+ mdelay(50);
+ ret = twl4030_usb_read(twl, ID_STATUS);
+ }
+
+ if (twl-usb_mode == T2_USB_MODE_ULPI)
+ twl4030_i2c_access(twl, 0);
+ pm_runtime_put_autosuspend(twl-dev);
+
+ if (ret 0)
+ return TWL4030_ID_UNKNOWN;
+ ret = ffs(ret) - 1;
+ if (ret TWL4030_GROUND || ret TWL4030_FLOATING)
+ return TWL4030_ID_UNKNOWN;
+
+ return ret;
+}
+
static void __twl4030_phy_power(struct twl4030_usb *twl, int on)
{
u8 pwr = twl4030_usb_read(twl, PHY_PWR_CTRL);
@@ -532,6 +582,16 @@ static ssize_t twl4030_usb_vbus_show(struct device *dev,
}
static DEVICE_ATTR(vbus, 0444, twl4030_usb_vbus_show, NULL);
+static ssize_t twl4030_usb_id_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct twl4030_usb *twl = dev_get_drvdata(dev);
+ return scnprintf(buf, PAGE_SIZE, %s\n,
+twl4030_id_names[twl4030_get_id(twl)]);
+}
+static DEVICE_ATTR(id, 0444, twl4030_usb_id_show, NULL);
+
static irqreturn_t twl4030_usb_irq(int irq, void *_twl)
{
struct twl4030_usb *twl = _twl;
@@ -709,6 +769,8
[PATCH 1/3] PCI: host: pci-dra7xx: Disable pm_runtime on get_sync failure
Fix the error handling code in case pm_runtime_get_sync fails. Now
when pm_runtime_get_sync fails pm_runtime_disable is invoked so that
there is no unbalanced pm_runtime_enable calls.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/pci/host/pci-dra7xx.c |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
index 80db09e..d8b6d66 100644
--- a/drivers/pci/host/pci-dra7xx.c
+++ b/drivers/pci/host/pci-dra7xx.c
@@ -384,7 +384,7 @@ static int __init dra7xx_pcie_probe(struct platform_device
*pdev)
ret = pm_runtime_get_sync(dev);
if (IS_ERR_VALUE(ret)) {
dev_err(dev, pm_runtime_get_sync failed\n);
- goto err_phy;
+ goto err_get_sync;
}
reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
@@ -401,6 +401,8 @@ static int __init dra7xx_pcie_probe(struct platform_device
*pdev)
err_add_port:
pm_runtime_put(dev);
+
+err_get_sync:
pm_runtime_disable(dev);
err_phy:
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/3] PCI: host: pci-dra7xx: add pm support to pci dra7xx
Add PM support to pci-dra7xx so that PCI clocks can be disabled
during suspend and enabled back during resume without affecting
PCI functionality.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/pci/host/pci-dra7xx.c | 74 +
1 file changed, 74 insertions(+)
diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
index d8b6d66..1f5c039 100644
--- a/drivers/pci/host/pci-dra7xx.c
+++ b/drivers/pci/host/pci-dra7xx.c
@@ -433,6 +433,79 @@ static int __exit dra7xx_pcie_remove(struct
platform_device *pdev)
return 0;
}
+#ifdef CONFIG_PM_SLEEP
+static int dra7xx_pcie_suspend(struct device *dev)
+{
+ struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
+ struct pcie_port *pp = dra7xx-pp;
+
+ dw_pcie_suspend_rc(pp);
+
+ return 0;
+}
+
+static int dra7xx_pcie_resume(struct device *dev)
+{
+ struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
+ struct pcie_port *pp = dra7xx-pp;
+
+ dw_pcie_resume_rc(pp);
+
+ return 0;
+}
+static int dra7xx_pcie_suspend_noirq(struct device *dev)
+{
+ struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
+ int count = dra7xx-phy_count;
+
+ while (count--) {
+ phy_power_off(dra7xx-phy[count]);
+ phy_exit(dra7xx-phy[count]);
+ }
+
+ return 0;
+}
+static int dra7xx_pcie_resume_noirq(struct device *dev)
+{
+ struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
+ int phy_count = dra7xx-phy_count;
+ int ret;
+ int i;
+
+ for (i = 0; i phy_count; i++) {
+ ret = phy_init(dra7xx-phy[i]);
+ if (ret 0)
+ goto err_phy;
+
+ ret = phy_power_on(dra7xx-phy[i]);
+ if (ret 0) {
+ phy_exit(dra7xx-phy[i]);
+ goto err_phy;
+ }
+ }
+
+ return 0;
+
+err_phy:
+ while (--i = 0) {
+ phy_power_off(dra7xx-phy[i]);
+ phy_exit(dra7xx-phy[i]);
+ }
+
+ return ret;
+}
+
+static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
+ .suspend_noirq = dra7xx_pcie_suspend_noirq,
+ .suspend = dra7xx_pcie_suspend,
+ .resume_noirq = dra7xx_pcie_resume_noirq,
+ .resume = dra7xx_pcie_resume,
+};
+#define DEV_PM_OPS (dra7xx_pcie_pm_ops)
+#else
+#define DEV_PM_OPS NULL
+#endif
+
static const struct of_device_id of_dra7xx_pcie_match[] = {
{ .compatible = ti,dra7-pcie, },
{},
@@ -444,6 +517,7 @@ static struct platform_driver dra7xx_pcie_driver = {
.driver = {
.name = dra7-pcie,
.of_match_table = of_dra7xx_pcie_match,
+ .pm = DEV_PM_OPS,
},
};
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/3] PCI: host: pcie-designware: add support for suspend and resume
Certain platforms require MSE bit to be cleared to set the master
in standby mode. (In DRA7xx TRM_vE, section 24.9.4.5.2.2.1 PCIe
Controller Master Standby Behavior advises to use the clearing
of the local MSE bit to set the master in standby. Without this
some of the clocks do not idle).
Cleared the MSE bit on suspend and enabled it back on resume.
This is required to get suspend/resume working.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Signed-off-by: Sekhar Nori nsek...@ti.com
---
drivers/pci/host/pcie-designware.c | 20
drivers/pci/host/pcie-designware.h |2 ++
2 files changed, 22 insertions(+)
diff --git a/drivers/pci/host/pcie-designware.c
b/drivers/pci/host/pcie-designware.c
index 69486be..cfb2bd6 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -811,6 +811,26 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
dw_pcie_writel_rc(pp, val, PCI_COMMAND);
}
+void dw_pcie_suspend_rc(struct pcie_port *pp)
+{
+ u32 val;
+
+ /* clear MSE */
+ dw_pcie_readl_rc(pp, PCI_COMMAND, val);
+ val = ~PCI_COMMAND_MEMORY;
+ dw_pcie_writel_rc(pp, val, PCI_COMMAND);
+}
+
+void dw_pcie_resume_rc(struct pcie_port *pp)
+{
+ u32 val;
+
+ /* set MSE */
+ dw_pcie_readl_rc(pp, PCI_COMMAND, val);
+ val |= PCI_COMMAND_MEMORY;
+ dw_pcie_writel_rc(pp, val, PCI_COMMAND);
+}
+
MODULE_AUTHOR(Jingoo Han jg1@samsung.com);
MODULE_DESCRIPTION(Designware PCIe host controller driver);
MODULE_LICENSE(GPL v2);
diff --git a/drivers/pci/host/pcie-designware.h
b/drivers/pci/host/pcie-designware.h
index d0bbd27..0df2dfa 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -83,5 +83,7 @@ void dw_pcie_msi_init(struct pcie_port *pp);
int dw_pcie_link_up(struct pcie_port *pp);
void dw_pcie_setup_rc(struct pcie_port *pp);
int dw_pcie_host_init(struct pcie_port *pp);
+void dw_pcie_suspend_rc(struct pcie_port *pp);
+void dw_pcie_resume_rc(struct pcie_port *pp);
#endif /* _PCIE_DESIGNWARE_H */
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/3] J6/J6Eco: Add PM support to PCIe
This series adds PM support to pci-dra7xx so that PCI clocks can be disabled during suspend and enabled back during resume without affecting PCI functionality. This series is dependent on [1] for proper PM functionality. [1] - http://newscentral.exsees.com/item/595269de5c35c59c386b91ce8efd9872-eedf6742bb6159c3b1a90625c4d43407 Kishon Vijay Abraham I (3): PCI: host: pci-dra7xx: Disable pm_runtime if get_sync failure PCI: host: pcie-designware: add support for suspend and resume PCI: host: pci-dra7xx: add pm support to pci dra7xx drivers/pci/host/pci-dra7xx.c | 78 +++- drivers/pci/host/pcie-designware.c | 20 + drivers/pci/host/pcie-designware.h |2 + 3 files changed, 99 insertions(+), 1 deletion(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/3] phy: ti-pipe3: i783 workaround for SATA lockup after dpll unlock/relock
Roger,
On Friday 22 May 2015 07:28 PM, Roger Quadros wrote:
Kishon,
On 22/05/15 14:34, Kishon Vijay Abraham I wrote:
Roger,
On Wednesday 20 May 2015 07:17 PM, Roger Quadros wrote:
Kishon,
On 20/05/15 16:19, Kishon Vijay Abraham I wrote:
Hi Roger,
On Tuesday 12 May 2015 09:37 PM, Roger Quadros wrote:
SATA_PLL_SOFT_RESET bit of CTRL_CORE_SMA_SW_0 must be toggled
between a SATA DPLL unlock and re-lock to prevent SATA lockup.
Introduce a new DT parameter 'syscon-pllreset' to provide the syscon
regmap access to this register which sits in the control module.
If the register is not provided we fallback to the old behaviour
i.e. SATA DPLL refclk will not be disabled and we prevent SoC low
power states.
Signed-off-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 16 ++
drivers/phy/phy-ti-pipe3.c | 67
2 files changed, 74 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 305e3df..f0f5537 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -82,6 +82,9 @@ Optional properties:
- id: If there are multiple instance of the same type, in order to
differentiate between each instance id can be used (e.g.,
multi-lane PCIe
PHY). If id is not provided, it is set to default value of '1'.
+ - syscon-pllreset: Handle to system control region that contains the
+ CTRL_CORE_SMA_SW_0 register and register offset to the
CTRL_CORE_SMA_SW_0
+ register that contains the SATA_PLL_SOFT_RESET bit. Only valid for
sata_phy.
This is usually a subnode of ocp2scp to which it is connected.
@@ -100,3 +103,16 @@ usb3phy@4a084400 {
sysclk,
refclk;
};
+
+sata_phy: phy@4A096000 {
+compatible = ti,phy-pipe3-sata;
+reg = 0x4A096000 0x80, /* phy_rx */
+ 0x4A096400 0x64, /* phy_tx */
+ 0x4A096800 0x40; /* pll_ctrl */
+reg-names = phy_rx, phy_tx, pll_ctrl;
+ctrl-module = omap_control_sata;
+clocks = sys_clkin1, sata_ref_clk;
+clock-names = sysclk, refclk;
+syscon-pllreset = dra7_ctrl_core 0x3fc;
+#phy-cells = 0;
+};
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index e13a306..d730142 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -28,6 +28,8 @@
#include linux/delay.h
#include linux/phy/omap_control_phy.h
#include linux/of_platform.h
+#include linux/mfd/syscon.h
+#include linux/regmap.h
#definePLL_STATUS0x0004
#definePLL_GO0x0008
@@ -52,6 +54,8 @@
#definePLL_LOCK0x2
#definePLL_IDLE0x1
+#define SATA_PLL_SOFT_RESETBIT(18)
+
/*
* This is an Empirical value that works, need to confirm the actual
* value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
@@ -82,6 +86,9 @@ struct ti_pipe3 {
struct clk*refclk;
struct clk*div_clk;
struct pipe3_dpll_map*dpll_map;
+struct regmap*dpll_reset_syscon; /* ctrl. reg. acces */
+unsigned intdpll_reset_reg; /* reg. index within syscon */
+boolsata_refclk_enabled;
};
static struct pipe3_dpll_map dpll_map_usb[] = {
@@ -249,11 +256,15 @@ static int ti_pipe3_exit(struct phy *x)
u32 val;
unsigned long timeout;
-/* SATA DPLL can't be powered down due to Errata i783 and PCIe
- * does not have internal DPLL
+/* If dpll_reset_syscon is not present we wont power down SATA DPLL
+ * due to Errata i783
*/
-if (of_device_is_compatible(phy-dev-of_node,
ti,phy-pipe3-sata) ||
-of_device_is_compatible(phy-dev-of_node, ti,phy-pipe3-pcie))
+if (of_device_is_compatible(phy-dev-of_node,
ti,phy-pipe3-sata)
+!phy-dpll_reset_syscon)
+return 0;
+
+/* PCIe doesn't have DPLL. FIXME: need to disable clocks though */
I think it's better to fix it in this patch itself.. to disable clocks
for PCIe.
+if (of_device_is_compatible(phy-dev-of_node, ti,phy-pipe3-pcie))
return 0;
/* Put DPLL in IDLE mode */
@@ -276,6 +287,14 @@ static int ti_pipe3_exit(struct phy *x)
return -EBUSY;
}
+/* i783: SATA needs control bit toggle after PLL unlock */
+if (of_device_is_compatible(phy-dev-of_node,
ti,phy-pipe3-sata)) {
+regmap_update_bits(phy-dpll_reset_syscon, phy-dpll_reset_reg,
+SATA_PLL_SOFT_RESET, SATA_PLL_SOFT_RESET);
+regmap_update_bits(phy-dpll_reset_syscon, phy-dpll_reset_reg,
+SATA_PLL_SOFT_RESET, 0);
+}
+
ti_pipe3_disable_clocks(phy);
return 0;
@@ -350,6 +369,21 @@ static int ti_pipe3_probe(struct platform_device
*pdev)
}
} else {
phy-wkupclk = ERR_PTR(-ENODEV);
+phy
Re: [PATCH 2/3] phy: ti-pipe3: i783 workaround for SATA lockup after dpll unlock/relock
Roger,
On Wednesday 20 May 2015 07:17 PM, Roger Quadros wrote:
Kishon,
On 20/05/15 16:19, Kishon Vijay Abraham I wrote:
Hi Roger,
On Tuesday 12 May 2015 09:37 PM, Roger Quadros wrote:
SATA_PLL_SOFT_RESET bit of CTRL_CORE_SMA_SW_0 must be toggled
between a SATA DPLL unlock and re-lock to prevent SATA lockup.
Introduce a new DT parameter 'syscon-pllreset' to provide the syscon
regmap access to this register which sits in the control module.
If the register is not provided we fallback to the old behaviour
i.e. SATA DPLL refclk will not be disabled and we prevent SoC low
power states.
Signed-off-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 16 ++
drivers/phy/phy-ti-pipe3.c | 67
2 files changed, 74 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 305e3df..f0f5537 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -82,6 +82,9 @@ Optional properties:
- id: If there are multiple instance of the same type, in order to
differentiate between each instance id can be used (e.g.,
multi-lane PCIe
PHY). If id is not provided, it is set to default value of '1'.
+ - syscon-pllreset: Handle to system control region that contains the
+ CTRL_CORE_SMA_SW_0 register and register offset to the
CTRL_CORE_SMA_SW_0
+ register that contains the SATA_PLL_SOFT_RESET bit. Only valid for
sata_phy.
This is usually a subnode of ocp2scp to which it is connected.
@@ -100,3 +103,16 @@ usb3phy@4a084400 {
sysclk,
refclk;
};
+
+sata_phy: phy@4A096000 {
+compatible = ti,phy-pipe3-sata;
+reg = 0x4A096000 0x80, /* phy_rx */
+ 0x4A096400 0x64, /* phy_tx */
+ 0x4A096800 0x40; /* pll_ctrl */
+reg-names = phy_rx, phy_tx, pll_ctrl;
+ctrl-module = omap_control_sata;
+clocks = sys_clkin1, sata_ref_clk;
+clock-names = sysclk, refclk;
+syscon-pllreset = dra7_ctrl_core 0x3fc;
+#phy-cells = 0;
+};
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index e13a306..d730142 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -28,6 +28,8 @@
#include linux/delay.h
#include linux/phy/omap_control_phy.h
#include linux/of_platform.h
+#include linux/mfd/syscon.h
+#include linux/regmap.h
#definePLL_STATUS0x0004
#definePLL_GO0x0008
@@ -52,6 +54,8 @@
#definePLL_LOCK0x2
#definePLL_IDLE0x1
+#define SATA_PLL_SOFT_RESETBIT(18)
+
/*
* This is an Empirical value that works, need to confirm the actual
* value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
@@ -82,6 +86,9 @@ struct ti_pipe3 {
struct clk*refclk;
struct clk*div_clk;
struct pipe3_dpll_map*dpll_map;
+struct regmap*dpll_reset_syscon; /* ctrl. reg. acces */
+unsigned intdpll_reset_reg; /* reg. index within syscon */
+boolsata_refclk_enabled;
};
static struct pipe3_dpll_map dpll_map_usb[] = {
@@ -249,11 +256,15 @@ static int ti_pipe3_exit(struct phy *x)
u32 val;
unsigned long timeout;
-/* SATA DPLL can't be powered down due to Errata i783 and PCIe
- * does not have internal DPLL
+/* If dpll_reset_syscon is not present we wont power down SATA DPLL
+ * due to Errata i783
*/
-if (of_device_is_compatible(phy-dev-of_node,
ti,phy-pipe3-sata) ||
-of_device_is_compatible(phy-dev-of_node, ti,phy-pipe3-pcie))
+if (of_device_is_compatible(phy-dev-of_node,
ti,phy-pipe3-sata)
+!phy-dpll_reset_syscon)
+return 0;
+
+/* PCIe doesn't have DPLL. FIXME: need to disable clocks though */
I think it's better to fix it in this patch itself.. to disable clocks
for PCIe.
+if (of_device_is_compatible(phy-dev-of_node, ti,phy-pipe3-pcie))
return 0;
/* Put DPLL in IDLE mode */
@@ -276,6 +287,14 @@ static int ti_pipe3_exit(struct phy *x)
return -EBUSY;
}
+/* i783: SATA needs control bit toggle after PLL unlock */
+if (of_device_is_compatible(phy-dev-of_node,
ti,phy-pipe3-sata)) {
+regmap_update_bits(phy-dpll_reset_syscon, phy-dpll_reset_reg,
+SATA_PLL_SOFT_RESET, SATA_PLL_SOFT_RESET);
+regmap_update_bits(phy-dpll_reset_syscon, phy-dpll_reset_reg,
+SATA_PLL_SOFT_RESET, 0);
+}
+
ti_pipe3_disable_clocks(phy);
return 0;
@@ -350,6 +369,21 @@ static int ti_pipe3_probe(struct platform_device
*pdev)
}
} else {
phy-wkupclk = ERR_PTR(-ENODEV);
+phy-dpll_reset_syscon = syscon_regmap_lookup_by_phandle(node,
+syscon-pllreset);
+if (IS_ERR(phy-dpll_reset_syscon
Re: [PATCH v2 3/3] ARM: dts: dra7: Add scm_conf@1c04 node
Hi Roger,
On Monday 27 July 2015 03:57 PM, Roger Quadros wrote:
This region contains CTRL_CORE_SMA_SW2..9 registers which
are not specific to any domain and can be reasonably
accessed via syscon driver.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 913032b..43b5074 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -149,6 +149,13 @@
pinctrl-single,register-width = 32;
pinctrl-single,function-mask =
0x3fff;
};
+
+ scm_conf1: scm_conf@1c04 {
+ compatible = syscon;
+ reg = 0x1c04 0x0020;
+ #address-cells = 1;
+ #size-cells = 1;
Why do you need address-cells and size-cells property here? AFAIK it is usually
used to decode childs reg property.
Thanks
Kishon
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] regulator: pbias: use untranslated address to program pbias regulator
Hi Mark Brown, On Friday 14 August 2015 11:30 PM, Mark Brown wrote: On Mon, Jul 27, 2015 at 04:54:09PM +0530, Kishon Vijay Abraham I wrote: vsel_reg and enable_reg of the pbias regulator descriptor should actually have the offset from syscon. However after the pbias device tree node I'm having a hard time understanding this statement, sorry. What makes you say that they shouild actually have the offset from syscon? What is the problem that this is supposed to fix? The register to program pbias regulator is 0x4A002E00. The syscon base address is 0x4a002000. So the vsel_reg and enable_reg should have the offset from syscon base address. regulator_enable_regmap gets the base address from 'regmap' and offset from 'enable_reg' in order to program the pbias regulator. But without this patch vsel_reg and enable_reg have the absolute address instead of just the offset. is moved as a child node of syscon, vsel_reg and enable_reg has the absolute address because of the address translation that happens while creating device from device tree node. So avoid using platform_get_resource and use of_get_address in order to get only the offset (untranslated address) and populate these in vsel_reg and enable_reg. This sounds like we're going in the wrong direction, we're moving from a more generic API to a firmware specific one. Why is this a good fix? platform_get_resource can be used if we need the absolute address but here we need only the offset. Thanks Kishon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] regulator: pbias: use untranslated address to program pbias regulator
Hi Mark Brown, On Wednesday 19 August 2015 11:41 PM, Mark Brown wrote: On Tue, Aug 18, 2015 at 11:23:54AM +0530, Kishon Vijay Abraham I wrote: On Friday 14 August 2015 11:30 PM, Mark Brown wrote: On Mon, Jul 27, 2015 at 04:54:09PM +0530, Kishon Vijay Abraham I wrote: is moved as a child node of syscon, vsel_reg and enable_reg has the absolute address because of the address translation that happens while creating device from device tree node. So avoid using platform_get_resource and use of_get_address in order to get only the offset (untranslated address) and populate these in vsel_reg and enable_reg. This sounds like we're going in the wrong direction, we're moving from a more generic API to a firmware specific one. Why is this a good fix? platform_get_resource can be used if we need the absolute address but here we need only the offset. So substract this address from the start of the resource to get the That would mean from the offset (provided in dt) get the absolute address and then again from the absolute address get the offset. offset? Or provide a wrapper function in the resource code which does Why not use 'of_get_address' which does the same thing? Moreover it's not a resource we are dealing with here. It's a resource only for the syscon driver. that. What you're saying above is pretty much this happens to work but my concern is that the solution that happens to work isn't really what we want to do. Not just makes this work, this is also the most reasonable solution available IMHO. The most ideal way would have been to use something like what Grygorii mentioned to use syscon = scm_conf 0xe00 and then use the phandle to get the offset. But then with this we'll be breaking older dtbs. Thanks Kishon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 00/16] omap_hsmmc: regulator usage cleanup and fixes
Hi Tony, On Friday 21 August 2015 01:11 PM, Tony Lindgren wrote: * Kishon Vijay Abraham I kis...@ti.com [150820 05:39]: Hi, On Monday 03 August 2015 05:56 PM, Kishon Vijay Abraham I wrote: Changes from v1: *) return on -EPROBE_DEFER and other fatal errors. (Don't return only if the return value is -ENODEV) *) Remove the beagle x15 dts patch. It can be part of a different series. *) Avoid using regulator_is_enabled for vqmmc since if the regulator is shared and the other users are not using regulator_is_enabled then there can be unbalanced regulator_enable/regulator_disable This patch series does the following *) Uses devm_regulator_get_optional() for vmmc and then removes the CONFIG_REGULATOR check altogether. *) return on -EPROBE_DEFER and any other fatal errors *) enable/disable vmmc_aux regulator based on prior state I've pushed this patch series to git://git.ti.com/linux-phy/linux-phy.git mmc_regulator_cleanup_fixes_v2 Please note the branch also has the pbias fixes [1] [2]. [1] - https://lkml.org/lkml/2015/7/27/358 [2] - https://lkml.org/lkml/2015/7/27/391 This series is in preparation for implementing the voltage switch sequence so that UHS cards can be supported. Did basic read/write test in J6, J6 Eco, Beagle-x15, AM437x EVM, Beaglebone black, OMAP5 uEVM and OMAP4 PANDA. I have now done read/write test in omap3 beagle-xm with this series! Great thanks for doing that. Also gave this series a try here with my off idle MMC SDIO WLAN card test and things still work for me. That's not really testing the PBIAS regulator though, but a good torture test for saving and restoring context. So FWIW: Tested-by: Tony Lindgren t...@atomide.com If you need a PM torture test for PBIAS regulator, you could try to do the following on your beagle xm MMC card with oamp2plus_defconfig: 1. Make sure EHCI modules are not loaded and OTG USB cable is not connected 2. Enable UART timeouts and off idle with something like: !/bin/bash uarts=$(find /sys/class/tty/tty[SO]*/device/power/ -type d) for uart in $uarts; do echo 3000 $uart/autosuspend_delay_ms 21 done modprobe leds-gpio modprobe ledtrig-default-on uarts=$(find /sys/class/tty/tty[SO]*/power/ -type d 2/dev/null) for uart in $uarts; do echo enabled $uart/wakeup 21 echo auto $uart/control 21 done echo 1 /sys/kernel/debug/pm_debug/enable_off_mode 3. Make sure you start seeing core_pwrdm OFF count increasing with cat /sys/kernel/debug/pm_debug/count MMC should keep on working when hitting idle, if not, something is not saved or restored properly. And SDIO WLAN cards should wake up the system and respond to ping if the wakeirq is configured in the dts file for the MMC controller. At least mwifiex_sdio cards work for this :) Thanks for the detailed explanation. Sure will add those tests. Cheers Kishon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] usb: musb: omap2430: use *syscon* framework API to write to mailbox register
Hi, On Thursday 06 August 2015 02:17 PM, Tony Lindgren wrote: * Kishon Vijay Abraham I kis...@ti.com [150805 07:10]: On Wednesday 05 August 2015 01:31 PM, Tony Lindgren wrote: We don't have syscon-otghs and to me it seems we need a PHY driver as I pointed out at: If *syscon-otghs* is not present, then it'll fall-back to using the *ctrl-module*. OK great. https://lkml.org/lkml/2015/6/24/231 Maybe I should have explained this in the previous thread. The *otghs* register that we are trying to access here does _not_ belong to the PHY. It acts as mailbox register from MUSB glue (TI integration layer) to MUSB core. That's why it's programmed in the TI glue layer (omap2430.c). Even when we were using the older API [omap_control_usb_set_mode()], we first call omap_musb_mailbox from the PHY drivers (phy-twl4030-usb.c, phy-twl6030-usb.c) and then omap_musb_mailbox in the TI glue writes to the control module instead of PHY drivers directly calling omap_control_usb_set_mode(). Hmm looking at Table 18-204. CONTROL_USBOTGHS_CONTROL it seems to mention transceiver for quite a few bitfields :) Probably what that register does is control a PHY over ULPI. OMAP4 uses UTMI PHY and it uses CONTROL_USBOTGHS_CONTROL too. So from Linux kernel point of view we're best off treating it as a PHY. It seems it should have a minimal PHY driver similar to what we have for dm816x control module in drivers/phy/phy-dm816x-usb.c. hmm.. IMHO CONTROL_USBOTGHS_CONTROL register belongs to the TI MUSB glue and should be programmed in omap2430.c. It's better to get the opinion of Felipe here. Felipe? For reference, here is the register bitfields pasted from 4460 TRM: Table 18-204. CONTROL_USBOTGHS_CONTROL, p3972 Physical Address 0x4A00 233C BIT NAMEDESCIPTION 8 DISCHRGVBUS ... OTG transceiver does (not) discharge VBUS ... 7 CHRGVBUS... OTG transceiver does (not) charge VBUS ... 6 IDPULLUP... OTG transceiver does (not) drive VBUS ... 4 IDDIG ... OTG transceiver does (not) apply a pullup to ID ... 3 SESSEND ... VBUS voltage is above/below VB_SESS_END ... 2 VBUSVALID ... VBUS is above the threshold ... 1 BVALID ... VBUS voltage is above/below VB_SESS_VLD ... 0 AVALID ... BUS voltage is above/below VA_SESS_VLD ... So how about just adding ONTROL_USBOTGHS_CONTROL support to the existing drivers/phy/phy-omap-usb2.c instead? It seems that it should allow us to completely get rid of the custom mailbox stuff for MUSB 2430 support? Not in phy-omap-usb2.c. It's the UTMI PHY driver and is not used by OMAP3 based boards (uses twl4030 ULPI PHY). CONTROL_USBOTGHS_CONTROL has to be programmed for OMAP3 also. Thanks Kishon -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 00/16] omap_hsmmc: regulator usage cleanup and fixes
Hi, On Monday 03 August 2015 05:56 PM, Kishon Vijay Abraham I wrote: Changes from v1: *) return on -EPROBE_DEFER and other fatal errors. (Don't return only if the return value is -ENODEV) *) Remove the beagle x15 dts patch. It can be part of a different series. *) Avoid using regulator_is_enabled for vqmmc since if the regulator is shared and the other users are not using regulator_is_enabled then there can be unbalanced regulator_enable/regulator_disable This patch series does the following *) Uses devm_regulator_get_optional() for vmmc and then removes the CONFIG_REGULATOR check altogether. *) return on -EPROBE_DEFER and any other fatal errors *) enable/disable vmmc_aux regulator based on prior state I've pushed this patch series to git://git.ti.com/linux-phy/linux-phy.git mmc_regulator_cleanup_fixes_v2 Please note the branch also has the pbias fixes [1] [2]. [1] - https://lkml.org/lkml/2015/7/27/358 [2] - https://lkml.org/lkml/2015/7/27/391 This series is in preparation for implementing the voltage switch sequence so that UHS cards can be supported. Did basic read/write test in J6, J6 Eco, Beagle-x15, AM437x EVM, Beaglebone black, OMAP5 uEVM and OMAP4 PANDA. I have now done read/write test in omap3 beagle-xm with this series! Thanks Kishon Kishon Vijay Abraham I (15): mmc: host: omap_hsmmc: use devm_regulator_get_optional() for vmmc mmc: host: omap_hsmmc: return on fatal errors from omap_hsmmc_reg_get mmc: host: omap_hsmmc: cleanup omap_hsmmc_reg_get() mmc: host: omap_hsmmc: use the ocrmask provided by the vmmc regulator mmc: host: omap_hsmmc: use mmc_host's vmmc and vqmmc mmc: host: omap_hsmmc: remove unnecessary pbias set_voltage mmc: host: omap_hsmmc: return error if any of the regulator APIs fail mmc: host: omap_hsmmc: add separate functions for enable/disable supply mmc: host: omap_hsmmc: add separate function to set pbias mmc: host: omap_hsmmc: avoid pbias regulator enable on power off mmc: host: omap_hsmmc: don't use -set_power to set initial regulator state mmc: host: omap_hsmmc: enable/disable vmmc_aux regulator based on previous state mmc: host: omap_hsmmc: use regulator_is_enabled to find pbias status mmc: host: omap_hsmmc: use ios-vdd for setting vmmc voltage mmc: host: omap_hsmmc: remove CONFIG_REGULATOR check Roger Quadros (1): mmc: host: omap_hsmmc: use mmc_of_parse_voltage to get ocr_avail .../devicetree/bindings/mmc/ti-omap-hsmmc.txt |2 + drivers/mmc/host/omap_hsmmc.c | 340 +--- 2 files changed, 224 insertions(+), 118 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] ARM: dts: am57xx-evm: Add 'gpios' property with gpio2_8
gpio2_8 is connected to the PCIe_RESETn line and it has to be driven low
in order to reset the PCIe cards. So added gpios property to pcie
dt node.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/am57xx-beagle-x15.dts |5 +
arch/arm/boot/dts/dra7.dtsi |2 +-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts
b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index a63bf78..a862a6e 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -693,3 +693,8 @@
};
};
};
+
+pcie1 {
+ gpios = gpio2 8 GPIO_ACTIVE_LOW;
+};
+
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 8f1e25b..37202b4 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -211,7 +211,7 @@
#address-cells = 1;
ranges = 0x5100 0x5100 0x3000
0x00x2000 0x1000;
- pcie@5100 {
+ pcie1: pcie@5100 {
compatible = ti,dra7-pcie;
reg = 0x5100 0x2000, 0x51002000 0x14c,
0x1000 0x2000;
reg-names = rc_dbics, ti_conf, config;
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 0/3] dra7xx: Add PM support to PCIe
This series adds PM support to pci-dra7xx so that PCI clocks can be disabled during suspend and enabled back during resume without affecting PCI functionality. Changes from v3: *) Fix compilation errors when individual patches are applied Changes from v2: *) Used SET_SYSTEM_SLEEP_PM_OPS and SET_NOIRQ_SYSTEM_SLEEP_PM_OPS for populating PM ops. Changes from v1: *) Moved resetting and setting of MSE bit to pci-dra7xx. The comment to reset and set ISE is not done now since I don't have a card with IO space. Once I get to test that, I'll post a separate patch for handling that. Kishon Vijay Abraham I (3): PCI: host: pci-dra7xx: Disable pm_runtime on get_sync failure PCI: host: pci-dra7xx: add pm support to pci dra7xx PCI: host: pci-dra7xx: Idle the module by disabling MSE bit drivers/pci/host/pci-dra7xx.c | 94 - 1 file changed, 93 insertions(+), 1 deletion(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 3/3] PCI: host: pci-dra7xx: Idle the module by disabling MSE bit
DRA7xx require MSE bit to be cleared to set the master in
standby mode. (In DRA7xx TRM_vE, section 24.9.4.5.2.2.1 PCIe
Controller Master Standby Behavior advises to use the clearing
of the local MSE bit to set the master in standby. Without this
some of the clocks do not idle).
Cleared the MSE bit on suspend and enabled it back on resume.
Clearing MSE bit is required to get clocks to be idled after
suspend.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Signed-off-by: Sekhar Nori nsek...@ti.com
---
drivers/pci/host/pci-dra7xx.c | 39 +++
1 file changed, 39 insertions(+)
diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
index 08b999a..773349f 100644
--- a/drivers/pci/host/pci-dra7xx.c
+++ b/drivers/pci/host/pci-dra7xx.c
@@ -83,6 +83,17 @@ static inline void dra7xx_pcie_writel(struct dra7xx_pcie
*pcie, u32 offset,
writel(value, pcie-base + offset);
}
+static inline u32 dra7xx_pcie_readl_rc(struct pcie_port *pp, u32 offset)
+{
+ return readl(pp-dbi_base + offset);
+}
+
+static inline void dra7xx_pcie_writel_rc(struct pcie_port *pp, u32 offset,
+u32 value)
+{
+ writel(value, pp-dbi_base + offset);
+}
+
static int dra7xx_pcie_link_up(struct pcie_port *pp)
{
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
@@ -434,6 +445,34 @@ static int __exit dra7xx_pcie_remove(struct
platform_device *pdev)
}
#ifdef CONFIG_PM_SLEEP
+static int dra7xx_pcie_suspend(struct device *dev)
+{
+ struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
+ struct pcie_port *pp = dra7xx-pp;
+ u32 val;
+
+ /* clear MSE */
+ val = dra7xx_pcie_readl_rc(pp, PCI_COMMAND);
+ val = ~PCI_COMMAND_MEMORY;
+ dra7xx_pcie_writel_rc(pp, PCI_COMMAND, val);
+
+ return 0;
+}
+
+static int dra7xx_pcie_resume(struct device *dev)
+{
+ struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
+ struct pcie_port *pp = dra7xx-pp;
+ u32 val;
+
+ /* Set MSE */
+ val = dra7xx_pcie_readl_rc(pp, PCI_COMMAND);
+ val |= PCI_COMMAND_MEMORY;
+ dra7xx_pcie_writel_rc(pp, PCI_COMMAND, val);
+
+ return 0;
+}
+
static int dra7xx_pcie_suspend_noirq(struct device *dev)
{
struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/2] pci: am57xx-evm: Fix PCIe card enumeration issue
This series fixes PCIe card enumeration issue in am57xx-evm. In the case of am57xx-evm, the PERST# line is connected to a gpio line and this has to be driven low in order to perform a fundamental reset of the card. If the gpio line is driven high, there is no way the card can come out of reset. Add support in the pcie-dra7xx driver to make gpio drive PERST# line. The PERST# line can be used to perform reset not during the power on sequence too (warm reset) but we are not adding support for this as the PCIe express base sepcification doesn't explain how to perform warm reset In some cases, it may be possible for the Fundamental Reset mechanism to be triggered by hardware without the removal and re-application of power to the component. This is called a warm reset. This document does not specify a means for generating a warm reset. Kishon Vijay Abraham I (2): pci: host: pci-dra7xx: Add support to make gpio drive PERST# line ARM: dts: am57xx-evm: Add 'gpios' property with gpio2_8 Documentation/devicetree/bindings/pci/ti-pci.txt |3 +++ arch/arm/boot/dts/am57xx-beagle-x15.dts |5 + arch/arm/boot/dts/dra7.dtsi |2 +- drivers/pci/host/pci-dra7xx.c| 24 -- 4 files changed, 31 insertions(+), 3 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 1/3] PCI: host: pci-dra7xx: Disable pm_runtime on get_sync failure
Fix the error handling code in case pm_runtime_get_sync fails. Now
when pm_runtime_get_sync fails pm_runtime_disable is invoked so that
there is no unbalanced pm_runtime_enable calls.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/pci/host/pci-dra7xx.c |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
index 80db09e..d8b6d66 100644
--- a/drivers/pci/host/pci-dra7xx.c
+++ b/drivers/pci/host/pci-dra7xx.c
@@ -384,7 +384,7 @@ static int __init dra7xx_pcie_probe(struct platform_device
*pdev)
ret = pm_runtime_get_sync(dev);
if (IS_ERR_VALUE(ret)) {
dev_err(dev, pm_runtime_get_sync failed\n);
- goto err_phy;
+ goto err_get_sync;
}
reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
@@ -401,6 +401,8 @@ static int __init dra7xx_pcie_probe(struct platform_device
*pdev)
err_add_port:
pm_runtime_put(dev);
+
+err_get_sync:
pm_runtime_disable(dev);
err_phy:
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 2/3] PCI: host: pci-dra7xx: add pm support to pci dra7xx
Add PM support to pci-dra7xx so that PCI clocks can be disabled
during suspend and enabled back during resume without affecting
PCI functionality.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/pci/host/pci-dra7xx.c | 51 +
1 file changed, 51 insertions(+)
diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
index d8b6d66..08b999a 100644
--- a/drivers/pci/host/pci-dra7xx.c
+++ b/drivers/pci/host/pci-dra7xx.c
@@ -433,6 +433,56 @@ static int __exit dra7xx_pcie_remove(struct
platform_device *pdev)
return 0;
}
+#ifdef CONFIG_PM_SLEEP
+static int dra7xx_pcie_suspend_noirq(struct device *dev)
+{
+ struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
+ int count = dra7xx-phy_count;
+
+ while (count--) {
+ phy_power_off(dra7xx-phy[count]);
+ phy_exit(dra7xx-phy[count]);
+ }
+
+ return 0;
+}
+
+static int dra7xx_pcie_resume_noirq(struct device *dev)
+{
+ struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
+ int phy_count = dra7xx-phy_count;
+ int ret;
+ int i;
+
+ for (i = 0; i phy_count; i++) {
+ ret = phy_init(dra7xx-phy[i]);
+ if (ret 0)
+ goto err_phy;
+
+ ret = phy_power_on(dra7xx-phy[i]);
+ if (ret 0) {
+ phy_exit(dra7xx-phy[i]);
+ goto err_phy;
+ }
+ }
+
+ return 0;
+
+err_phy:
+ while (--i = 0) {
+ phy_power_off(dra7xx-phy[i]);
+ phy_exit(dra7xx-phy[i]);
+ }
+
+ return ret;
+}
+#endif
+
+static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq,
+ dra7xx_pcie_resume_noirq)
+};
+
static const struct of_device_id of_dra7xx_pcie_match[] = {
{ .compatible = ti,dra7-pcie, },
{},
@@ -444,6 +494,7 @@ static struct platform_driver dra7xx_pcie_driver = {
.driver = {
.name = dra7-pcie,
.of_match_table = of_dra7xx_pcie_match,
+ .pm = dra7xx_pcie_pm_ops,
},
};
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] pci: host: pci-dra7xx: Add support to make gpio drive PERST# line
The PERST# line in am57x-evm is connected to a gpio line and PERST#
should be driven high to indicate the clocks are stable (As per
Figure 2-10: Power Up of the PCIe CEM spec 3.0).
Add support in pci-dra7xx driver to make gpio drive PERST#
line here.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/pci/ti-pci.txt |3 +++
drivers/pci/host/pci-dra7xx.c| 24 --
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt
b/Documentation/devicetree/bindings/pci/ti-pci.txt
index 3d21791..60e2516 100644
--- a/Documentation/devicetree/bindings/pci/ti-pci.txt
+++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
@@ -23,6 +23,9 @@ PCIe Designware Controller
interrupt-map-mask,
interrupt-map : as specified in ../designware-pcie.txt
+Optional Property:
+ - gpios : Should be added if a gpio line is required to drive PERST# line
+
Example:
axi {
compatible = simple-bus;
diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
index 7acc833..d3d0faf 100644
--- a/drivers/pci/host/pci-dra7xx.c
+++ b/drivers/pci/host/pci-dra7xx.c
@@ -17,6 +17,7 @@
#include linux/irqdomain.h
#include linux/kernel.h
#include linux/module.h
+#include linux/of_gpio.h
#include linux/pci.h
#include linux/phy/phy.h
#include linux/platform_device.h
@@ -336,6 +337,9 @@ static int __init dra7xx_pcie_probe(struct platform_device
*pdev)
struct device *dev = pdev-dev;
struct device_node *np = dev-of_node;
char name[10];
+ int gpio_sel;
+ enum of_gpio_flags flags;
+ unsigned long gpio_flags;
dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
if (!dra7xx)
@@ -398,6 +402,22 @@ static int __init dra7xx_pcie_probe(struct platform_device
*pdev)
goto err_get_sync;
}
+ gpio_sel = of_get_gpio_flags(dev-of_node, 0, flags);
+ if (gpio_is_valid(gpio_sel)) {
+ gpio_flags = (flags OF_GPIO_ACTIVE_LOW) ?
+ GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH;
+ ret = devm_gpio_request_one(dev, gpio_sel, gpio_flags,
+ pcie_reset);
+ if (ret) {
+ dev_err(pdev-dev, gpio%d request failed, ret %d\n,
+ gpio_sel, ret);
+ goto err_gpio;
+ }
+ } else if (gpio_sel == -EPROBE_DEFER) {
+ ret = -EPROBE_DEFER;
+ goto err_gpio;
+ }
+
reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
reg = ~LTSSM_EN;
dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
@@ -406,11 +426,11 @@ static int __init dra7xx_pcie_probe(struct
platform_device *pdev)
ret = dra7xx_add_pcie_port(dra7xx, pdev);
if (ret 0)
- goto err_add_port;
+ goto err_gpio;
return 0;
-err_add_port:
+err_gpio:
pm_runtime_put(dev);
err_get_sync:
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 3/3] PCI: host: pci-dra7xx: Idle the module by disabling MSE bit
DRA7xx require MSE bit to be cleared to set the master in
standby mode. (In DRA7xx TRM_vE, section 24.9.4.5.2.2.1 PCIe
Controller Master Standby Behavior advises to use the clearing
of the local MSE bit to set the master in standby. Without this
some of the clocks do not idle).
Cleared the MSE bit on suspend and enabled it back on resume.
Clearing MSE bit is required to get clocks to be idled after
suspend.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Signed-off-by: Sekhar Nori nsek...@ti.com
---
drivers/pci/host/pci-dra7xx.c | 40
1 file changed, 40 insertions(+)
diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
index 08b999a..3772aff 100644
--- a/drivers/pci/host/pci-dra7xx.c
+++ b/drivers/pci/host/pci-dra7xx.c
@@ -83,6 +83,17 @@ static inline void dra7xx_pcie_writel(struct dra7xx_pcie
*pcie, u32 offset,
writel(value, pcie-base + offset);
}
+static inline u32 dra7xx_pcie_readl_rc(struct pcie_port *pp, u32 offset)
+{
+ return readl(pp-dbi_base + offset);
+}
+
+static inline void dra7xx_pcie_writel_rc(struct pcie_port *pp, u32 offset,
+u32 value)
+{
+ writel(value, pp-dbi_base + offset);
+}
+
static int dra7xx_pcie_link_up(struct pcie_port *pp)
{
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
@@ -434,6 +445,34 @@ static int __exit dra7xx_pcie_remove(struct
platform_device *pdev)
}
#ifdef CONFIG_PM_SLEEP
+static int dra7xx_pcie_suspend(struct device *dev)
+{
+ struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
+ struct pcie_port *pp = dra7xx-pp;
+ u32 val;
+
+ /* clear MSE */
+ val = dra7xx_pcie_readl_rc(pp, PCI_COMMAND);
+ val = ~PCI_COMMAND_MEMORY;
+ dra7xx_pcie_writel_rc(pp, PCI_COMMAND, val);
+
+ return 0;
+}
+
+static int dra7xx_pcie_resume(struct device *dev)
+{
+ struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
+ struct pcie_port *pp = dra7xx-pp;
+ u32 val;
+
+ /* set MSE */
+ val = dra7xx_pcie_readl_rc(pp, PCI_COMMAND);
+ val |= PCI_COMMAND_MEMORY;
+ dra7xx_pcie_writel_rc(pp, PCI_COMMAND, val);
+
+ return 0;
+}
+
static int dra7xx_pcie_suspend_noirq(struct device *dev)
{
struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
@@ -479,6 +518,7 @@ err_phy:
#endif
static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume)
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq,
dra7xx_pcie_resume_noirq)
};
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 1/3] PCI: host: pci-dra7xx: Disable pm_runtime on get_sync failure
Fix the error handling code in case pm_runtime_get_sync fails. Now
when pm_runtime_get_sync fails pm_runtime_disable is invoked so that
there is no unbalanced pm_runtime_enable calls.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/pci/host/pci-dra7xx.c |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
index 80db09e..d8b6d66 100644
--- a/drivers/pci/host/pci-dra7xx.c
+++ b/drivers/pci/host/pci-dra7xx.c
@@ -384,7 +384,7 @@ static int __init dra7xx_pcie_probe(struct platform_device
*pdev)
ret = pm_runtime_get_sync(dev);
if (IS_ERR_VALUE(ret)) {
dev_err(dev, pm_runtime_get_sync failed\n);
- goto err_phy;
+ goto err_get_sync;
}
reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
@@ -401,6 +401,8 @@ static int __init dra7xx_pcie_probe(struct platform_device
*pdev)
err_add_port:
pm_runtime_put(dev);
+
+err_get_sync:
pm_runtime_disable(dev);
err_phy:
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 2/3] PCI: host: pci-dra7xx: add pm support to pci dra7xx
Add PM support to pci-dra7xx so that PCI clocks can be disabled
during suspend and enabled back during resume without affecting
PCI functionality.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/pci/host/pci-dra7xx.c | 51 +
1 file changed, 51 insertions(+)
diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
index d8b6d66..08b999a 100644
--- a/drivers/pci/host/pci-dra7xx.c
+++ b/drivers/pci/host/pci-dra7xx.c
@@ -433,6 +433,56 @@ static int __exit dra7xx_pcie_remove(struct
platform_device *pdev)
return 0;
}
+#ifdef CONFIG_PM_SLEEP
+static int dra7xx_pcie_suspend_noirq(struct device *dev)
+{
+ struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
+ int count = dra7xx-phy_count;
+
+ while (count--) {
+ phy_power_off(dra7xx-phy[count]);
+ phy_exit(dra7xx-phy[count]);
+ }
+
+ return 0;
+}
+
+static int dra7xx_pcie_resume_noirq(struct device *dev)
+{
+ struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
+ int phy_count = dra7xx-phy_count;
+ int ret;
+ int i;
+
+ for (i = 0; i phy_count; i++) {
+ ret = phy_init(dra7xx-phy[i]);
+ if (ret 0)
+ goto err_phy;
+
+ ret = phy_power_on(dra7xx-phy[i]);
+ if (ret 0) {
+ phy_exit(dra7xx-phy[i]);
+ goto err_phy;
+ }
+ }
+
+ return 0;
+
+err_phy:
+ while (--i = 0) {
+ phy_power_off(dra7xx-phy[i]);
+ phy_exit(dra7xx-phy[i]);
+ }
+
+ return ret;
+}
+#endif
+
+static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq,
+ dra7xx_pcie_resume_noirq)
+};
+
static const struct of_device_id of_dra7xx_pcie_match[] = {
{ .compatible = ti,dra7-pcie, },
{},
@@ -444,6 +494,7 @@ static struct platform_driver dra7xx_pcie_driver = {
.driver = {
.name = dra7-pcie,
.of_match_table = of_dra7xx_pcie_match,
+ .pm = dra7xx_pcie_pm_ops,
},
};
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5 0/3] dra7xx: Add PM support to PCIe
This series adds PM support to pci-dra7xx so that PCI clocks can be disabled during suspend and enabled back during resume without affecting PCI functionality. Changes from v4: *) Fixed a bug caused by sending incomplete patch. Changes from v3: *) Fix compilation errors when individual patches are applied Changes from v2: *) Used SET_SYSTEM_SLEEP_PM_OPS and SET_NOIRQ_SYSTEM_SLEEP_PM_OPS for populating PM ops. Changes from v1: *) Moved resetting and setting of MSE bit to pci-dra7xx. The comment to reset and set ISE is not done now since I don't have a card with IO space. Once I get to test that, I'll post a separate patch for handling that. Kishon Vijay Abraham I (3): PCI: host: pci-dra7xx: Disable pm_runtime on get_sync failure PCI: host: pci-dra7xx: add pm support to pci dra7xx PCI: host: pci-dra7xx: Idle the module by disabling MSE bit drivers/pci/host/pci-dra7xx.c | 95 - 1 file changed, 94 insertions(+), 1 deletion(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] usb: musb: omap2430: use *syscon* framework API to write to mailbox register
Deprecate using phy-omap-control driver to write to the mailbox register
and start using *syscon* framework to do the same.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/usb/omap-usb.txt |7 +-
drivers/usb/musb/omap2430.c| 115
2 files changed, 99 insertions(+), 23 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt
b/Documentation/devicetree/bindings/usb/omap-usb.txt
index 38d9bb8..c001306 100644
--- a/Documentation/devicetree/bindings/usb/omap-usb.txt
+++ b/Documentation/devicetree/bindings/usb/omap-usb.txt
@@ -20,10 +20,15 @@ OMAP MUSB GLUE
- phy-names : the names of the PHY corresponding to the PHYs present in the
*phy* phandle.
-Optional properties:
+Optional Properties:
+Deprecated properties:
- ctrl-module : phandle of the control module this glue uses to write to
mailbox
+Recommended properies:
+ - syscon-otghs : phandle/offset pair. Phandle to the system control module
and the
+ register offset of the mailbox.
+
SOC specific device node entry
usb_otg_hs: usb_otg_hs@4a0ab000 {
compatible = ti,omap4-musb;
diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
index 70f2b8a..a03cf1e 100644
--- a/drivers/usb/musb/omap2430.c
+++ b/drivers/usb/musb/omap2430.c
@@ -39,16 +39,27 @@
#include linux/usb/musb-omap.h
#include linux/phy/omap_control_phy.h
#include linux/of_platform.h
+#include linux/regmap.h
+#include linux/mfd/syscon.h
#include musb_core.h
#include omap2430.h
+#define OMAP2430_MUSB_MODE_MASK0x1f
+#define OMAP2430_MUSB_AVALID BIT(0)
+#define OMAP2430_MUSB_BVALID BIT(1)
+#define OMAP2430_MUSB_VBUSVALIDBIT(2)
+#define OMAP2430_MUSB_SESSEND BIT(3)
+#define OMAP2430_MUSB_IDDIGBIT(4)
+
struct omap2430_glue {
struct device *dev;
struct platform_device *musb;
enum omap_musb_vbus_id_status status;
struct work_struct omap_musb_mailbox_work;
struct device *control_otghs;
+ struct regmap *syscon_otghs; /* ctrl. reg. acces */
+ unsigned intotghs_reg; /* otghs reg. index within syscon */
};
#define glue_to_musb(g)platform_get_drvdata(g-musb)
@@ -253,6 +264,44 @@ void omap_musb_mailbox(enum omap_musb_vbus_id_status
status)
}
EXPORT_SYMBOL_GPL(omap_musb_mailbox);
+static void omap2430_musb_set_usbmode(struct omap2430_glue *glue,
+ enum omap_control_usb_mode mode)
+{
+ u32 val;
+ int ret;
+
+ if (glue-syscon_otghs) {
+ switch (mode) {
+ case USB_MODE_HOST:
+ val = OMAP2430_MUSB_AVALID | OMAP2430_MUSB_VBUSVALID;
+ break;
+ case USB_MODE_DEVICE:
+ val = OMAP2430_MUSB_IDDIG | OMAP2430_MUSB_AVALID |
+ OMAP2430_MUSB_VBUSVALID;
+ break;
+ case USB_MODE_DISCONNECT:
+ val = OMAP2430_MUSB_IDDIG | OMAP2430_MUSB_SESSEND;
+ break;
+ default:
+ dev_dbg(glue-dev, Invalid mode\n);
+ goto err_regmap_update;
+ }
+
+ ret = regmap_update_bits(glue-syscon_otghs,
+glue-otghs_reg,
+OMAP2430_MUSB_MODE_MASK, val);
+ if (ret 0)
+ goto err_regmap_update;
+ } else {
+ omap_control_usb_set_mode(glue-control_otghs, mode);
+ }
+
+ return;
+
+err_regmap_update:
+ dev_err(glue-dev, Failed to set mode to %d\n, mode);
+}
+
static void omap_musb_set_mailbox(struct omap2430_glue *glue)
{
struct musb *musb = glue_to_musb(glue);
@@ -270,8 +319,7 @@ static void omap_musb_set_mailbox(struct omap2430_glue
*glue)
musb-xceiv-last_event = USB_EVENT_ID;
if (musb-gadget_driver) {
pm_runtime_get_sync(dev);
- omap_control_usb_set_mode(glue-control_otghs,
- USB_MODE_HOST);
+ omap2430_musb_set_usbmode(glue, USB_MODE_HOST);
omap2430_musb_set_vbus(musb, 1);
}
break;
@@ -284,7 +332,7 @@ static void omap_musb_set_mailbox(struct omap2430_glue
*glue)
musb-xceiv-last_event = USB_EVENT_VBUS;
if (musb-gadget_driver)
pm_runtime_get_sync(dev);
- omap_control_usb_set_mode(glue-control_otghs, USB_MODE_DEVICE);
+ omap2430_musb_set_usbmode(glue, USB_MODE_DEVICE);
break;
case OMAP_MUSB_ID_FLOAT:
@@ -301,8 +349,7 @@ static void omap_musb_set_mailbox(struct omap2430_glue
*glue)
if (data-interface_type == MUSB_INTERFACE_UTMI
[PATCH 1/7] phy: ti-pipe3: cleanup ti_pipe3_probe()
No functional change. Add separate functions for pll,
clocks and syscon to make ti_pipe3_probe clean.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/phy/phy-ti-pipe3.c | 165
1 file changed, 104 insertions(+), 61 deletions(-)
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index 08020dc..072d308 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -308,51 +308,45 @@ static struct phy_ops ops = {
static const struct of_device_id ti_pipe3_id_table[];
-static int ti_pipe3_probe(struct platform_device *pdev)
+static int ti_pipe3_get_pll_base(struct ti_pipe3 *phy)
{
- struct ti_pipe3 *phy;
- struct phy *generic_phy;
- struct phy_provider *phy_provider;
struct resource *res;
- struct device_node *node = pdev-dev.of_node;
- struct device_node *control_node;
- struct platform_device *control_pdev;
const struct of_device_id *match;
- struct clk *clk;
+ struct device *dev = phy-dev;
+ struct device_node *node = dev-of_node;
+ struct platform_device *pdev = to_platform_device(dev);
- phy = devm_kzalloc(pdev-dev, sizeof(*phy), GFP_KERNEL);
- if (!phy)
- return -ENOMEM;
+ if (of_device_is_compatible(node, ti,phy-pipe3-pcie))
+ return 0;
- phy-dev= pdev-dev;
+ match = of_match_device(ti_pipe3_id_table, dev);
+ if (!match)
+ return -EINVAL;
- if (!of_device_is_compatible(node, ti,phy-pipe3-pcie)) {
- match = of_match_device(ti_pipe3_id_table, pdev-dev);
- if (!match)
- return -EINVAL;
+ phy-dpll_map = (struct pipe3_dpll_map *)match-data;
+ if (!phy-dpll_map) {
+ dev_err(dev, no DPLL data\n);
+ return -EINVAL;
+ }
- phy-dpll_map = (struct pipe3_dpll_map *)match-data;
- if (!phy-dpll_map) {
- dev_err(pdev-dev, no DPLL data\n);
- return -EINVAL;
- }
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ pll_ctrl);
+ phy-pll_ctrl_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(phy-pll_ctrl_base))
+ return PTR_ERR(phy-pll_ctrl_base);
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- pll_ctrl);
- phy-pll_ctrl_base = devm_ioremap_resource(pdev-dev, res);
- if (IS_ERR(phy-pll_ctrl_base))
- return PTR_ERR(phy-pll_ctrl_base);
+ return 0;
+}
- phy-sys_clk = devm_clk_get(phy-dev, sysclk);
- if (IS_ERR(phy-sys_clk)) {
- dev_err(pdev-dev, unable to get sysclk\n);
- return -EINVAL;
- }
- }
+static int ti_pipe3_get_clk(struct ti_pipe3 *phy)
+{
+ struct clk *clk;
+ struct device *dev = phy-dev;
+ struct device_node *node = dev-of_node;
- phy-refclk = devm_clk_get(phy-dev, refclk);
+ phy-refclk = devm_clk_get(dev, refclk);
if (IS_ERR(phy-refclk)) {
- dev_err(pdev-dev, unable to get refclk\n);
+ dev_err(dev, unable to get refclk\n);
/* older DTBs have missing refclk in SATA PHY
* so don't bail out in case of SATA PHY.
*/
@@ -361,76 +355,125 @@ static int ti_pipe3_probe(struct platform_device *pdev)
}
if (!of_device_is_compatible(node, ti,phy-pipe3-sata)) {
- phy-wkupclk = devm_clk_get(phy-dev, wkupclk);
+ phy-wkupclk = devm_clk_get(dev, wkupclk);
if (IS_ERR(phy-wkupclk)) {
- dev_err(pdev-dev, unable to get wkupclk\n);
+ dev_err(dev, unable to get wkupclk\n);
return PTR_ERR(phy-wkupclk);
}
} else {
phy-wkupclk = ERR_PTR(-ENODEV);
- phy-dpll_reset_syscon = syscon_regmap_lookup_by_phandle(node,
- syscon-pllreset);
- if (IS_ERR(phy-dpll_reset_syscon)) {
- dev_info(pdev-dev,
-can't get syscon-pllreset, sata dpll won't
idle\n);
- phy-dpll_reset_syscon = NULL;
- } else {
- if (of_property_read_u32_index(node,
- syscon-pllreset, 1,
- phy-dpll_reset_reg)) {
- dev_err(pdev-dev,
- couldn't get pllreset reg. offset\n);
- return -EINVAL
[PATCH 5/7] phy: omap-usb2: use omap_usb_power_off to power off the PHY during probe
No functional change. Previously omap_control_phy_power() was used to power off the PHY during probe. But once phy-omap-usb2 driver is adapted to use syscon, omap_control_phy_power() cannot be used. Hence used omap_usb_power_off to power off the PHY. Signed-off-by: Kishon Vijay Abraham I kis...@ti.com Acked-by: Roger Quadros rog...@ti.com --- drivers/phy/phy-omap-usb2.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c index c1a4686..b5c266a 100644 --- a/drivers/phy/phy-omap-usb2.c +++ b/drivers/phy/phy-omap-usb2.c @@ -241,7 +241,6 @@ static int omap_usb2_probe(struct platform_device *pdev) } phy-control_dev = control_pdev-dev; - omap_control_phy_power(phy-control_dev, 0); otg-set_host = omap_usb_set_host; otg-set_peripheral = omap_usb_set_peripheral; @@ -261,6 +260,7 @@ static int omap_usb2_probe(struct platform_device *pdev) } phy_set_drvdata(generic_phy, phy); + omap_usb_power_off(generic_phy); phy_provider = devm_of_phy_provider_register(phy-dev, of_phy_simple_xlate); -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/7] phy: use syscon framework APIs to set ctrl mod reg
This series is split from [1] to include only the PHY patches. This series is basically to deprecate using phy-omap-control and use syscon APIs to program the control module registers. Changes from [1] in PHY patches include *) cleanup ti_pipe3_probe *) have mask, power_on and power_off values in usb_phy_data for omap-usb2 phy Did basic enumeration testing in the below platforms. *) Tested PCIe, SATA and USB in dra7 *) Tested SATA and USB in omap5 *) Tested USB(dwc3) in am43xx_evm *) Tested USB(musb) in omap4 panda after including [2] All the testing was done both before applying the dt patches and after applying the dt patches (dt patches will be posted shortly). [1] - https://lkml.org/lkml/2015/6/23/189 [2] - http://permalink.gmane.org/gmane.linux.kernel/2012427 Kishon Vijay Abraham I (7): phy: ti-pipe3: cleanup ti_pipe3_probe() phy: ti-pipe3: use ti_pipe3_power_off to power off the PHY during probe phy: ti-pipe3: use *syscon* framework API to power on/off the PHY phy: ti-pipe3: use *syscon* framework API to set PCS value of the PHY phy: omap-usb2: use omap_usb_power_off to power off the PHY during probe phy: omap-usb2: Add a new compatible string for USB2 PHY2 phy: omap-usb2: use *syscon* framework API to power on/off the PHY Documentation/devicetree/bindings/phy/ti-phy.txt | 20 +- drivers/phy/phy-omap-usb2.c | 96 ++-- drivers/phy/phy-ti-pipe3.c | 283 -- include/linux/phy/omap_usb.h | 23 ++ 4 files changed, 329 insertions(+), 93 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 4/7] phy: ti-pipe3: use *syscon* framework API to set PCS value of the PHY
Deprecate using phy-omap-control driver to set PCS value of the PHY
and start using *syscon* API to do the same.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Acked-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt |2 ++
drivers/phy/phy-ti-pipe3.c | 34 +-
2 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index e06f980..49e5b0c 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -83,6 +83,8 @@ Optional properties:
- syscon-pllreset: Handle to system control region that contains the
CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0
register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy.
+ - syscon-pcs : phandle/offset pair. Phandle to the system control module and
the
+ register offset to write the PCS delay value.
Deprecated properties:
- ctrl-module : phandle of the control module used by PHY driver to power on
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index a7c20e8..8dc606d 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -65,6 +65,9 @@
#define PIPE3_PHY_TX_RX_POWERON0x3
#define PIPE3_PHY_TX_RX_POWEROFF 0x0
+#define PCIE_PCS_MASK 0xFF
+#define PCIE_PCS_DELAY_COUNT_SHIFT 0x10
+
/*
* This is an Empirical value that works, need to confirm the actual
* value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
@@ -96,9 +99,11 @@ struct ti_pipe3 {
struct clk *div_clk;
struct pipe3_dpll_map *dpll_map;
struct regmap *phy_power_syscon; /* ctrl. reg. acces */
+ struct regmap *pcs_syscon; /* ctrl. reg. acces */
struct regmap *dpll_reset_syscon; /* ctrl. reg. acces */
unsigned intdpll_reset_reg; /* reg. index within syscon */
unsigned intpower_reg; /* power reg. index within syscon */
+ unsigned intpcie_pcs_reg; /* pcs reg. index in syscon */
boolsata_refclk_enabled;
};
@@ -275,7 +280,16 @@ static int ti_pipe3_init(struct phy *x)
* 18-1804.
*/
if (of_device_is_compatible(phy-dev-of_node, ti,phy-pipe3-pcie)) {
- omap_control_pcie_pcs(phy-control_dev, 0x96);
+ if (phy-pcs_syscon) {
+ val = 0x96 OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT;
+ ret = regmap_update_bits(phy-pcs_syscon,
+phy-pcie_pcs_reg,
+PCIE_PCS_MASK, val);
+ if (ret 0)
+ return ret;
+ } else {
+ omap_control_pcie_pcs(phy-control_dev, 0x96);
+ }
return 0;
}
@@ -491,6 +505,24 @@ static int ti_pipe3_get_sysctrl(struct ti_pipe3 *phy)
phy-control_dev = control_pdev-dev;
}
+ if (of_device_is_compatible(node, ti,phy-pipe3-pcie)) {
+ phy-pcs_syscon = syscon_regmap_lookup_by_phandle(node,
+ syscon-pcs);
+ if (IS_ERR(phy-pcs_syscon)) {
+ dev_dbg(dev,
+ can't get syscon-pcs, using omap control\n);
+ phy-pcs_syscon = NULL;
+ } else {
+ if (of_property_read_u32_index(node,
+ syscon-pcs, 1,
+ phy-pcie_pcs_reg)) {
+ dev_err(dev,
+ couldn't get pcie pcs reg. offset\n);
+ return -EINVAL;
+ }
+ }
+ }
+
if (of_device_is_compatible(node, ti,phy-pipe3-sata)) {
phy-dpll_reset_syscon = syscon_regmap_lookup_by_phandle(node,
syscon-pllreset);
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 6/7] phy: omap-usb2: Add a new compatible string for USB2 PHY2
The USB2 PHY2 has a different register map compared to USB2 PHY1
to power on/off the PHY. In order to handle it, add a new
compatible string.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt |2 ++
drivers/phy/phy-omap-usb2.c |9 +
2 files changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 49e5b0c..a061077 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -31,6 +31,8 @@ OMAP USB2 PHY
Required properties:
- compatible: Should be ti,omap-usb2
+ Should be ti,dra7x-usb2-phy2 for the 2nd instance of USB2 PHY
+ in DRA7x
- reg : Address and length of the register set for the device.
- #phy-cells: determine the number of cells that should be given in the
phandle while referencing this phy.
diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
index b5c266a..2f7220f 100644
--- a/drivers/phy/phy-omap-usb2.c
+++ b/drivers/phy/phy-omap-usb2.c
@@ -159,6 +159,11 @@ static const struct usb_phy_data dra7x_usb2_data = {
.flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
};
+static const struct usb_phy_data dra7x_usb2_phy2_data = {
+ .label = dra7x_usb2_phy2,
+ .flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
+};
+
static const struct usb_phy_data am437x_usb2_data = {
.label = am437x_usb2,
.flags = 0,
@@ -178,6 +183,10 @@ static const struct of_device_id omap_usb2_id_table[] = {
.data = dra7x_usb2_data,
},
{
+ .compatible = ti,dra7x-usb2-phy2,
+ .data = dra7x_usb2_phy2_data,
+ },
+ {
.compatible = ti,am437x-usb2,
.data = am437x_usb2_data,
},
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/7] phy: ti-pipe3: use *syscon* framework API to power on/off the PHY
Deprecate using phy-omap-control driver to power on/off the PHY and
use *syscon* framework to do the same.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 10 ++-
drivers/phy/phy-ti-pipe3.c | 90 ++
2 files changed, 85 insertions(+), 15 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 9cf9446..e06f980 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -77,8 +77,6 @@ Required properties:
* div-clk - apll clock
Optional properties:
- - ctrl-module : phandle of the control module used by PHY driver to power on
- the PHY.
- id: If there are multiple instance of the same type, in order to
differentiate between each instance id can be used (e.g., multi-lane PCIe
PHY). If id is not provided, it is set to default value of '1'.
@@ -86,6 +84,14 @@ Optional properties:
CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0
register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy.
+Deprecated properties:
+ - ctrl-module : phandle of the control module used by PHY driver to power on
+ the PHY.
+
+Recommended properies:
+ - syscon-phy-power : phandle/offset pair. Phandle to the system control
+ module and the register offset to power on/off the PHY.
+
This is usually a subnode of ocp2scp to which it is connected.
usb3phy@4a084400 {
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index 9782c16..a7c20e8 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -56,6 +56,15 @@
#define SATA_PLL_SOFT_RESETBIT(18)
+#define PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
+#define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 14
+
+#define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC0
+#define PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT22
+
+#define PIPE3_PHY_TX_RX_POWERON0x3
+#define PIPE3_PHY_TX_RX_POWEROFF 0x0
+
/*
* This is an Empirical value that works, need to confirm the actual
* value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
@@ -86,8 +95,10 @@ struct ti_pipe3 {
struct clk *refclk;
struct clk *div_clk;
struct pipe3_dpll_map *dpll_map;
+ struct regmap *phy_power_syscon; /* ctrl. reg. acces */
struct regmap *dpll_reset_syscon; /* ctrl. reg. acces */
unsigned intdpll_reset_reg; /* reg. index within syscon */
+ unsigned intpower_reg; /* power reg. index within syscon */
boolsata_refclk_enabled;
};
@@ -144,18 +155,53 @@ static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy);
static int ti_pipe3_power_off(struct phy *x)
{
+ u32 val;
+ int ret;
struct ti_pipe3 *phy = phy_get_drvdata(x);
- omap_control_phy_power(phy-control_dev, 0);
+ if (phy-phy_power_syscon) {
+ val = PIPE3_PHY_TX_RX_POWEROFF
+ PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
+
+ ret = regmap_update_bits(phy-phy_power_syscon, phy-power_reg,
+PIPE3_PHY_PWRCTL_CLK_CMD_MASK, val);
+ if (ret 0)
+ return ret;
+ } else {
+ omap_control_phy_power(phy-control_dev, 0);
+ }
return 0;
}
static int ti_pipe3_power_on(struct phy *x)
{
+ u32 val;
+ u32 mask;
+ int ret;
+ unsigned long rate;
struct ti_pipe3 *phy = phy_get_drvdata(x);
- omap_control_phy_power(phy-control_dev, 1);
+ if (phy-phy_power_syscon) {
+ rate = clk_get_rate(phy-sys_clk);
+ if (!rate) {
+ dev_err(phy-dev, Invalid clock rate\n);
+ return -EINVAL;
+ }
+ rate = rate / 100;
+ mask = OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
+ OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK;
+ val = PIPE3_PHY_TX_RX_POWERON
+ PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
+ val |= rate OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
+
+ ret = regmap_update_bits(phy-phy_power_syscon, phy-power_reg,
+mask, val);
+ if (ret 0)
+ return ret;
+ } else {
+ omap_control_phy_power(phy-control_dev, 1);
+ }
return 0;
}
@@ -364,7 +410,8 @@ static int ti_pipe3_get_clk(struct ti_pipe3 *phy)
phy-wkupclk = ERR_PTR(-ENODEV);
}
- if (!of_device_is_compatible(node, ti,phy-pipe3-pcie)) {
+ if (!of_device_is_compatible(node, ti,phy-pipe3-pcie) ||
+ phy-phy_power_syscon) {
phy-sys_clk = devm_clk_get(dev, sysclk
[PATCH 2/7] phy: ti-pipe3: use ti_pipe3_power_off to power off the PHY during probe
No functional change. Previously omap_control_phy_power() was used to power off the PHY during probe. But once PIPE3 driver is adapted to use syscon, omap_control_phy_power() cannot be used. Hence used ti_pipe3_power_off to power off the PHY. Signed-off-by: Kishon Vijay Abraham I kis...@ti.com Acked-by: Roger Quadros rog...@ti.com --- drivers/phy/phy-ti-pipe3.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c index 072d308..9782c16 100644 --- a/drivers/phy/phy-ti-pipe3.c +++ b/drivers/phy/phy-ti-pipe3.c @@ -474,8 +474,6 @@ static int ti_pipe3_probe(struct platform_device *pdev) if (ret) return ret; - omap_control_phy_power(phy-control_dev, 0); - platform_set_drvdata(pdev, phy); pm_runtime_enable(phy-dev); @@ -494,6 +492,8 @@ static int ti_pipe3_probe(struct platform_device *pdev) return PTR_ERR(generic_phy); phy_set_drvdata(generic_phy, phy); + ti_pipe3_power_off(generic_phy); + phy_provider = devm_of_phy_provider_register(phy-dev, of_phy_simple_xlate); if (IS_ERR(phy_provider)) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 7/7] phy: omap-usb2: use *syscon* framework API to power on/off the PHY
Deprecate using phy-omap-control driver to power on/off the PHY,
and use *syscon* framework to do the same. This handles
powering on/off the PHY for the USB2 PHYs used in various TI SoCs.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt |6 +-
drivers/phy/phy-omap-usb2.c | 85 +-
include/linux/phy/omap_usb.h | 23 ++
3 files changed, 96 insertions(+), 18 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index a061077..a3b3945 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -42,10 +42,14 @@ Required properties:
* wkupclk - wakeup clock.
* refclk - reference clock (optional).
-Optional properties:
+Deprecated properties:
- ctrl-module : phandle of the control module used by PHY driver to power on
the PHY.
+Recommended properies:
+- syscon-phy-power : phandle/offset pair. Phandle to the system control
+ module and the register offset to power on/off the PHY.
+
This is usually a subnode of ocp2scp to which it is connected.
usb2phy@4a0ad080 {
diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
index 2f7220f..531fe04 100644
--- a/drivers/phy/phy-omap-usb2.c
+++ b/drivers/phy/phy-omap-usb2.c
@@ -29,6 +29,8 @@
#include linux/delay.h
#include linux/phy/omap_control_phy.h
#include linux/phy/phy.h
+#include linux/mfd/syscon.h
+#include linux/regmap.h
#include linux/of_platform.h
#define USB2PHY_DISCON_BYP_LATCH (1 31)
@@ -97,22 +99,40 @@ static int omap_usb_set_peripheral(struct usb_otg *otg,
return 0;
}
-static int omap_usb_power_off(struct phy *x)
+static int omap_usb_phy_power(struct omap_usb *phy, int on)
{
- struct omap_usb *phy = phy_get_drvdata(x);
+ u32 val = 0;
+ int ret;
- omap_control_phy_power(phy-control_dev, 0);
+ if (phy-syscon_phy_power) {
+ if (on)
+ val = phy-power_on;
+ else
+ val = phy-power_off;
+
+ ret = regmap_update_bits(phy-syscon_phy_power, phy-power_reg,
+phy-mask, val);
+ if (ret 0)
+ return ret;
+ } else {
+ omap_control_phy_power(phy-control_dev, on);
+ }
return 0;
}
-static int omap_usb_power_on(struct phy *x)
+static int omap_usb_power_off(struct phy *x)
{
struct omap_usb *phy = phy_get_drvdata(x);
- omap_control_phy_power(phy-control_dev, 1);
+ return omap_usb_phy_power(phy, false);
+}
- return 0;
+static int omap_usb_power_on(struct phy *x)
+{
+ struct omap_usb *phy = phy_get_drvdata(x);
+
+ return omap_usb_phy_power(phy, true);
}
static int omap_usb_init(struct phy *x)
@@ -147,26 +167,38 @@ static struct phy_ops ops = {
static const struct usb_phy_data omap_usb2_data = {
.label = omap_usb2,
.flags = OMAP_USB2_HAS_START_SRP | OMAP_USB2_HAS_SET_VBUS,
+ .mask = OMAP_DEV_PHY_PD,
+ .power_off = OMAP_DEV_PHY_PD,
};
static const struct usb_phy_data omap5_usb2_data = {
.label = omap5_usb2,
.flags = 0,
+ .mask = OMAP_DEV_PHY_PD,
+ .power_off = OMAP_DEV_PHY_PD,
};
static const struct usb_phy_data dra7x_usb2_data = {
.label = dra7x_usb2,
.flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
+ .mask = OMAP_DEV_PHY_PD,
+ .power_off = OMAP_DEV_PHY_PD,
};
static const struct usb_phy_data dra7x_usb2_phy2_data = {
.label = dra7x_usb2_phy2,
.flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
+ .mask = OMAP_USB2_PHY_PD,
+ .power_off = OMAP_USB2_PHY_PD,
};
static const struct usb_phy_data am437x_usb2_data = {
.label = am437x_usb2,
.flags = 0,
+ .mask = AM437X_USB2_PHY_PD | AM437X_USB2_OTG_PD |
+ AM437X_USB2_OTGVDET_EN | AM437X_USB2_OTGSESSEND_EN,
+ .power_on = AM437X_USB2_OTGVDET_EN | AM437X_USB2_OTGSESSEND_EN,
+ .power_off = AM437X_USB2_PHY_PD | AM437X_USB2_OTG_PD,
};
static const struct of_device_id omap_usb2_id_table[] = {
@@ -228,6 +260,9 @@ static int omap_usb2_probe(struct platform_device *pdev)
phy-phy.label = phy_data-label;
phy-phy.otg= otg;
phy-phy.type = USB_PHY_TYPE_USB2;
+ phy-mask = phy_data-mask;
+ phy-power_on = phy_data-power_on;
+ phy-power_off = phy_data-power_off;
if (phy_data-flags OMAP_USB2_CALIBRATE_FALSE_DISCONNECT) {
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -237,20 +272,36 @@ static int omap_usb2_probe(struct platform_device *pdev)
phy-flags |= OMAP_USB2_CALIBRATE_FALSE_DISCONNECT;
}
- control_node = of_parse_phandle
[PATCH 04/10] ARM: dts: dra7: Use ti,dra7x-usb2-phy2 compatible string for USB2 PHY2
The USB2 PHY2 has a different register map compared to USB2 PHY1
to power on/off the PHY. In order to handle it, use the new compatible
string ti,dra7x-usb2-phy2 for the second instance of USB2 PHY.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 0ebb808..dfefd17 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1234,7 +1234,7 @@
};
usb2_phy2: phy@4a085000 {
- compatible = ti,omap-usb2;
+ compatible = ti,dra7x-usb2-phy2,
ti,omap-usb2;
reg = 0x4a085000 0x400;
ctrl-module = omap_control_usb2phy2;
clocks = usb_phy2_always_on_clk32k,
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 05/10] ARM: dts: dra7: Use syscon-phy-power instead of ctrl-module in USB PHY node
Add syscon-phy-power property and remove the deprecated ctrl-module
property from USB PHY devicetree nodes.
Since omap_control_usb2phy1, omap_control_usb3phy1 and
omap_control_usb2phy2 devicetree nodes are no longer used, remove it.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 24 +++-
1 file changed, 3 insertions(+), 21 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index dfefd17..191ffae 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1195,24 +1195,6 @@
clocks = sys_32k_ck;
};
- omap_control_usb2phy1: control-phy@4a002300 {
- compatible = ti,control-phy-usb2;
- reg = 0x4a002300 0x4;
- reg-names = power;
- };
-
- omap_control_usb3phy1: control-phy@4a002370 {
- compatible = ti,control-phy-pipe3;
- reg = 0x4a002370 0x4;
- reg-names = power;
- };
-
- omap_control_usb2phy2: control-phy@0x4a002e74 {
- compatible = ti,control-phy-usb2-dra7;
- reg = 0x4a002e74 0x4;
- reg-names = power;
- };
-
/* OCP2SCP1 */
ocp2scp@4a08 {
compatible = ti,omap-ocp2scp;
@@ -1225,7 +1207,7 @@
usb2_phy1: phy@4a084000 {
compatible = ti,omap-usb2;
reg = 0x4a084000 0x400;
- ctrl-module = omap_control_usb2phy1;
+ syscon-phy-power = scm_conf 0x300;
clocks = usb_phy1_always_on_clk32k,
usb_otg_ss1_refclk960m;
clock-names = wkupclk,
@@ -1236,7 +1218,7 @@
usb2_phy2: phy@4a085000 {
compatible = ti,dra7x-usb2-phy2,
ti,omap-usb2;
reg = 0x4a085000 0x400;
- ctrl-module = omap_control_usb2phy2;
+ syscon-phy-power = scm_conf 0xe74;
clocks = usb_phy2_always_on_clk32k,
usb_otg_ss2_refclk960m;
clock-names = wkupclk,
@@ -1250,7 +1232,7 @@
0x4a084800 0x64,
0x4a084c00 0x40;
reg-names = phy_rx, phy_tx, pll_ctrl;
- ctrl-module = omap_control_usb3phy1;
+ syscon-phy-power = scm_conf 0x370;
clocks = usb_phy3_always_on_clk32k,
sys_clkin1,
usb_otg_ss1_refclk960m;
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 03/10] ARM: dts: dra7: Use syscon-phy-power and syscon-pcs in PCIe PHY node
Add syscon-phy-power property and syscon-pcs property which can
be used to perform the control module initializations and remove
the deprecated ctrl-module property from PCIe PHY dt nodes.
Phandle to sysclk clock node is also added to the PCIe PHY node
since some of the syscon initializations is based on system clock
frequency.
Since omap_control_pcie1phy and omap_control_pcie2phy devicetree
nodes are no longer used, remove it.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 28 +++-
1 file changed, 7 insertions(+), 21 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 6854385..0ebb808 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1140,16 +1140,18 @@
reg = 0x4a094000 0x80, /* phy_rx */
0x4a094400 0x64; /* phy_tx */
reg-names = phy_rx, phy_tx;
- ctrl-module = omap_control_pcie1phy;
+ syscon-phy-power = scm_conf2 0x1c;
+ syscon-pcs = scm_conf2 0x10;
clocks = dpll_pcie_ref_ck,
dpll_pcie_ref_m2ldo_ck,
optfclk_pciephy1_32khz,
optfclk_pciephy1_clk,
optfclk_pciephy1_div_clk,
-optfclk_pciephy_div;
+optfclk_pciephy_div,
+sys_clkin1;
clock-names = dpll_ref, dpll_ref_m2,
wkupclk, refclk,
- div-clk, phy-div;
+ div-clk, phy-div, sysclk;
#phy-cells = 0;
};
@@ -1158,7 +1160,8 @@
reg = 0x4a095000 0x80, /* phy_rx */
0x4a095400 0x64; /* phy_tx */
reg-names = phy_rx, phy_tx;
- ctrl-module = omap_control_pcie2phy;
+ syscon-phy-power = scm_conf2 0x20;
+ syscon-pcs = scm_conf2 0x10;
clocks = dpll_pcie_ref_ck,
dpll_pcie_ref_m2ldo_ck,
optfclk_pciephy2_32khz,
@@ -1183,23 +1186,6 @@
ti,hwmods = sata;
};
- omap_control_pcie1phy: control-phy@0x4a003c40 {
- compatible = ti,control-phy-pcie;
- reg = 0x4a003c40 0x4, 0x4a003c14 0x4, 0x4a003c34
0x4;
- reg-names = power, control_sma, pcie_pcs;
- clocks = sys_clkin1;
- clock-names = sysclk;
- };
-
- omap_control_pcie2phy: control-pcie@0x4a003c44 {
- compatible = ti,control-phy-pcie;
- reg = 0x4a003c44 0x4, 0x4a003c14 0x4, 0x4a003c34
0x4;
- reg-names = power, control_sma, pcie_pcs;
- clocks = sys_clkin1;
- clock-names = sysclk;
- status = disabled;
- };
-
rtc: rtc@48838000 {
compatible = ti,am3352-rtc;
reg = 0x48838000 0x100;
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 01/10] ARM: dts: dra7: Add dt node for PCIe registers in sysctrl space
Add new device tree node for the control module register space where
PCIe registers are present.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index aa6abfc..33c5655 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -154,6 +154,11 @@
compatible = syscon;
reg = 0x1c04 0x0020;
};
+
+ scm_conf2: scm_conf@1c24 {
+ compatible = syscon;
+ reg = 0x1c24 0x0024;
+ };
};
cm_core_aon: cm_core_aon@5000 {
--
1.7.9.5
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
