[PATCH] arm64: dts: renesas: r8a779{7|8}0: add TMU support
Describe TMUs in the R8A779{7|8}0 device trees.
Based on the original (and large) patches by Vladimir Barinov.
Signed-off-by: Vladimir Barinov
Signed-off-by: Sergei Shtylyov
---
This patch is against the 'renesas-devel-20180906-v4.19-rc2' branch of
Simon Horman's 'renesas.git' repo plus the R8A779{7|8}0 DT patch adding
the CMT support).
The R8A779{7|8}0 TMU DT binding update have been just posted...
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 66 ++
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 66 ++
2 files changed, 132 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
===
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -316,6 +316,72 @@
resets = < 407>;
};
+ tmu0: timer@e61e {
+ compatible = "renesas,tmu-r8a77970", "renesas,tmu";
+ reg = <0 0xe61e 0 0x30>;
+ interrupts = ,
+,
+;
+ clocks = < CPG_MOD 125>;
+ clock-names = "fck";
+ power-domains = < R8A77970_PD_ALWAYS_ON>;
+ resets = < 125>;
+ status = "disabled";
+ };
+
+ tmu1: timer@e6fc {
+ compatible = "renesas,tmu-r8a77970", "renesas,tmu";
+ reg = <0 0xe6fc 0 0x30>;
+ interrupts = ,
+,
+;
+ clocks = < CPG_MOD 124>;
+ clock-names = "fck";
+ power-domains = < R8A77970_PD_ALWAYS_ON>;
+ resets = < 124>;
+ status = "disabled";
+ };
+
+ tmu2: timer@e6fd {
+ compatible = "renesas,tmu-r8a77970", "renesas,tmu";
+ reg = <0 0xe6fd 0 0x30>;
+ interrupts = ,
+,
+;
+ clocks = < CPG_MOD 123>;
+ clock-names = "fck";
+ power-domains = < R8A77970_PD_ALWAYS_ON>;
+ resets = < 123>;
+ status = "disabled";
+ };
+
+ tmu3: timer@e6fe {
+ compatible = "renesas,tmu-r8a7797", "renesas,tmu";
+ reg = <0 0xe6fe 0 0x30>;
+ interrupts = ,
+,
+;
+ clocks = < CPG_MOD 122>;
+ clock-names = "fck";
+ power-domains = < R8A77970_PD_ALWAYS_ON>;
+ resets = < 122>;
+ status = "disabled";
+ };
+
+ tmu4: timer@ffc0 {
+ compatible = "renesas,tmu-r8a7797", "renesas,tmu";
+ reg = <0 0xffc0 0 0x30>;
+ interrupts = ,
+,
+,
+;
+ clocks = < CPG_MOD 121>;
+ clock-names = "fck";
+ power-domains = < R8A77970_PD_ALWAYS_ON>;
+ resets = < 121>;
+ status = "disabled";
+ };
+
i2c0: i2c@e650 {
compatible = "renesas,i2c-r8a77970",
"renesas,rcar-gen3-i2c";
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -346,6 +346,72 @@
resets = < 407>;
};
+ tmu0: timer@e61e {
+ compatible = "renesas,tmu-r8a77980", "renesas,tmu";
+ reg = <0 0xe61e 0 0x30>;
+ interrupts = ,
+,
+;
+ clocks = < CPG_MOD 125>;
+ clock-names = "fck";
+ power-domains = < R8A77980_PD_ALWAYS_ON>;
+ resets = < 125>;
+ status = "disabled";
+ };
+
+ tmu1: timer@e6fc {
+ compatible = "renesas,tmu-r8a77980", "renesas,tmu";
+ reg = <0 0xe6fc 0 0x30>;
+ interrupts = ,
+
[PATCH] dt-bindings: timer: renesas: tmu: document R8A779{7|8}0 bindings
Document the R-Car V3{M|H} (R8A779{7|8}0) SoC in the Renesas TMU bindings;
the TMU hardware in those is the Renesas standard 3-channel timer unit.
Signed-off-by: Sergei Shtylyov
---
The patch is against the 'tip.git' repo's 'timers/core' branch.
Documentation/devicetree/bindings/timer/renesas,tmu.txt |2 ++
1 file changed, 2 insertions(+)
Index: tip/Documentation/devicetree/bindings/timer/renesas,tmu.txt
===
--- tip.orig/Documentation/devicetree/bindings/timer/renesas,tmu.txt
+++ tip/Documentation/devicetree/bindings/timer/renesas,tmu.txt
@@ -12,6 +12,8 @@ Required Properties:
- "renesas,tmu-r8a7740" for the r8a7740 TMU
- "renesas,tmu-r8a7778" for the r8a7778 TMU
- "renesas,tmu-r8a7779" for the r8a7779 TMU
+- "renesas,tmu-r8a77970" for the r8a77970 TMU
+- "renesas,tmu-r8a77980" for the r8a77980 TMU
- "renesas,tmu" for any TMU.
This is a fallback for the above renesas,tmu-* entries
Re: [PATCH] watchdog: rza_wdt: convert to SPDX identifiers
On Fri, Sep 07, 2018 at 02:11:17AM +, Kuninori Morimoto wrote: > > From: Kuninori Morimoto > > This patch updates license to use SPDX-License-Identifier > instead of verbose license text. > > Signed-off-by: Kuninori Morimoto Reviewed-by: Guenter Roeck > --- > drivers/watchdog/rza_wdt.c | 5 + > 1 file changed, 1 insertion(+), 4 deletions(-) > > diff --git a/drivers/watchdog/rza_wdt.c b/drivers/watchdog/rza_wdt.c > index e618218..c63ef03 100644 > --- a/drivers/watchdog/rza_wdt.c > +++ b/drivers/watchdog/rza_wdt.c > @@ -1,12 +1,9 @@ > +// SPDX-License-Identifier: GPL-2.0 > /* > * Renesas RZ/A Series WDT Driver > * > * Copyright (C) 2017 Renesas Electronics America, Inc. > * Copyright (C) 2017 Chris Brandt > - * > - * This file is subject to the terms and conditions of the GNU General Public > - * License. See the file "COPYING" in the main directory of this archive > - * for more details. > */ > > #include > -- > 2.7.4 >
Re: [PATCH] watchdog: renesas_wdt: convert to SPDX identifiers
On Fri, Sep 07, 2018 at 02:10:58AM +, Kuninori Morimoto wrote: > > From: Kuninori Morimoto > > This patch updates license to use SPDX-License-Identifier > instead of verbose license text. > > Signed-off-by: Kuninori Morimoto Reviewed-by: Guenter Roeck > --- > drivers/watchdog/renesas_wdt.c | 5 + > 1 file changed, 1 insertion(+), 4 deletions(-) > > diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c > index 88d81fe..84bb9d3 100644 > --- a/drivers/watchdog/renesas_wdt.c > +++ b/drivers/watchdog/renesas_wdt.c > @@ -1,12 +1,9 @@ > +// SPDX-License-Identifier: GPL-2.0 > /* > * Watchdog driver for Renesas WDT watchdog > * > * Copyright (C) 2015-17 Wolfram Sang, Sang Engineering > > * Copyright (C) 2015-17 Renesas Electronics Corporation > - * > - * This program is free software; you can redistribute it and/or modify it > - * under the terms of the GNU General Public License version 2 as published > by > - * the Free Software Foundation. > */ > #include > #include > -- > 2.7.4 >
[PATCH v2] arm64: dts: renesas: r8a779{7|8}0: add CMT support
Describe CMTs in the R8A779{7|8}0 device trees.
Based on the original (and large) patches by Vladimir Barinov.
Signed-off-by: Vladimir Barinov
Signed-off-by: Sergei Shtylyov
---
This patch is against the 'renesas-devel-20180906-v4.19-rc2' branch of
Simon Horman's 'renesas.git' repo.
The R8A779{7|8}0 CMT DT binding updates have been posted the other day...
Changes in version 2:
- added the "resets" prop to all CMT nodes;
- credited Vladimir Barinov as the formal author of the original patches.
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 70 ++
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 70 ++
2 files changed, 140 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
===
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -209,6 +209,76 @@
reg = <0 0xe606 0 0x504>;
};
+ cmt0: timer@e60f {
+ compatible = "renesas,r8a77970-cmt0",
+"renesas,rcar-gen3-cmt0";
+ reg = <0 0xe60f 0 0x1004>;
+ interrupts = ,
+;
+ clocks = < CPG_MOD 303>;
+ clock-names = "fck";
+ power-domains = < R8A77970_PD_ALWAYS_ON>;
+ resets = < 303>;
+ status = "disabled";
+ };
+
+ cmt1: timer@e613 {
+ compatible = "renesas,r8a77970-cmt1",
+"renesas,rcar-gen3-cmt1";
+ reg = <0 0xe613 0 0x1004>;
+ interrupts = ,
+,
+,
+,
+,
+,
+,
+;
+ clocks = < CPG_MOD 302>;
+ clock-names = "fck";
+ power-domains = < R8A77970_PD_ALWAYS_ON>;
+ resets = < 302>;
+ status = "disabled";
+ };
+
+ cmt2: timer@e614 {
+ compatible = "renesas,r8a77970-cmt1",
+"renesas,rcar-gen3-cmt1";
+ reg = <0 0xe614 0 0x1004>;
+ interrupts = ,
+,
+,
+,
+,
+,
+,
+;
+ clocks = < CPG_MOD 301>;
+ clock-names = "fck";
+ power-domains = < R8A77970_PD_ALWAYS_ON>;
+ resets = < 301>;
+ status = "disabled";
+ };
+
+ cmt3: timer@e6148000 {
+ compatible = "renesas,r8a77970-cmt1",
+"renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6148000 0 0x1004>;
+ interrupts = ,
+,
+,
+,
+,
+,
+,
+;
+ clocks = < CPG_MOD 300>;
+ clock-names = "fck";
+ power-domains = < R8A77970_PD_ALWAYS_ON>;
+ resets = < 300>;
+ status = "disabled";
+ };
+
cpg: clock-controller@e615 {
compatible = "renesas,r8a77970-cpg-mssr";
reg = <0 0xe615 0 0x1000>;
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -239,6 +239,76 @@
reg = <0 0xe606 0 0x50c>;
};
+ cmt0: timer@e60f {
+ compatible = "renesas,r8a77980-cmt0",
+"renesas,rcar-gen3-cmt0";
+ reg = <0 0xe60f 0 0x1004>;
+ interrupts = ,
+;
+ clocks = < CPG_MOD 303>;
+ clock-names = "fck";
+ power-domains = < R8A77980_PD_ALWAYS_ON>;
+ resets = < 303>;
[PATCH v4] clk: renesas: cpg-mssr: Add R7S9210 support
Add support for the R7S9210 (RZ/A2) Clock Pulse Generator and Module
Standby.
The Module Standby HW in the RZ/A series is very close to R-Car HW, except
for how the registers are laid out.
The MSTP registers are only 8-bits wide, there is no status registers
(MSTPSR), and the register offsets are a little different. Since the RZ/A
hardware manuals refer to these registers as the Standby Control Registers,
we'll use that name to distinguish the RZ/A type from the R-Car type.
Signed-off-by: Chris Brandt
---
v4:
* Preserved sort order of SoC listings
* Removed R7S9210_CLK_PLL from dt-binding since it's an internal clock
* ratio_tab is now a struct making it look a little nicer
* Removed CLK_I,...CLK_P0 because they are already defined in dt-bindings
* Sorted mod_clks by ascending MSTP number
* Removed cast from clk_get_rate(parent)
* Corrected register index of stbcr[1]
* Don't use MOD_CLK_PACK_10 for non priv->stbyctrl devices (bug fix)
v3:
* Use actual register bit names and numbers from manual for both DT and
tables ("36" instead of "306")
* Do not register reset controller for stbyctrl (RZ/A) SoCs
* Changed SPDX from "GPL-2.0+" to "GPL-2.0"
v2:
* num_hw_mod_clks was wrong
* added ethernet clocks
---
.../devicetree/bindings/clock/renesas,cpg-mssr.txt | 5 +-
drivers/clk/renesas/Kconfig| 5 +
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r7s9210-cpg-mssr.c | 189 +
drivers/clk/renesas/renesas-cpg-mssr.c | 81 +++--
drivers/clk/renesas/renesas-cpg-mssr.h | 13 ++
include/dt-bindings/clock/r7s9210-cpg-mssr.h | 20 +++
7 files changed, 300 insertions(+), 14 deletions(-)
create mode 100644 drivers/clk/renesas/r7s9210-cpg-mssr.c
create mode 100644 include/dt-bindings/clock/r7s9210-cpg-mssr.h
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
index 42d0f83d812b..5e46e6be789b 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
@@ -13,6 +13,7 @@ They provide the following functionalities:
Required Properties:
- compatible: Must be one of:
+ - "renesas,r7s9210-cpg-mssr" for the r7s9210 SoC (RZ/A2)
- "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
- "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
- "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)
@@ -36,8 +37,8 @@ Required Properties:
- clocks: References to external parent clocks, one entry for each entry in
clock-names
- clock-names: List of external parent clock names. Valid names are:
- - "extal" (r8a7743, r8a7745, r8a77470, r8a774a1, r8a7790, r8a7791,
-r8a7792, r8a7793, r8a7794, r8a7795, r8a7796, r8a77965,
+ - "extal" (r7s9210, r8a7743, r8a7745, r8a77470, r8a774a1, r8a7790,
+r8a7791, r8a7792, r8a7793, r8a7794, r8a7795, r8a7796, r8a77965,
r8a77970, r8a77980, r8a77990, r8a77995)
- "extalr" (r8a774a1, r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
- "usb_extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7793,
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index f998a7333acb..2edcb1bdb487 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -3,6 +3,7 @@ config CLK_RENESAS
default y if ARCH_RENESAS
select CLK_EMEV2 if ARCH_EMEV2
select CLK_RZA1 if ARCH_R7S72100
+ select CLK_R7S9210 if ARCH_R7S9210
select CLK_R8A73A4 if ARCH_R8A73A4
select CLK_R8A7740 if ARCH_R8A7740
select CLK_R8A7743 if ARCH_R8A7743
@@ -46,6 +47,10 @@ config CLK_RZA1
bool "RZ/A1H clock support" if COMPILE_TEST
select CLK_RENESAS_CPG_MSTP
+config CLK_R7S9210
+ bool "RZ/A2 clock support" if COMPILE_TEST
+ select CLK_RENESAS_CPG_MSSR
+
config CLK_R8A73A4
bool "R-Mobile APE6 clock support" if COMPILE_TEST
select CLK_RENESAS_CPG_MSTP
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 71d4cafe15c0..dbbfd0b0742b 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -2,6 +2,7 @@
# SoC
obj-$(CONFIG_CLK_EMEV2)+= clk-emev2.o
obj-$(CONFIG_CLK_RZA1) += clk-rz.o
+obj-$(CONFIG_CLK_R7S9210) += r7s9210-cpg-mssr.o
obj-$(CONFIG_CLK_R8A73A4) += clk-r8a73a4.o
obj-$(CONFIG_CLK_R8A7740) += clk-r8a7740.o
obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c
b/drivers/clk/renesas/r7s9210-cpg-mssr.c
new file mode 100644
index ..bd1dd4ff2051
--- /dev/null
+++ b/drivers/clk/renesas/r7s9210-cpg-mssr.c
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * R7S9210 Clock Pulse Generator / Module
RE: [PATCH 1/2] clocksource/drivers/ostm: Delay driver registration
On Thursday, August 30, 2018, Daniel Lezcano wrote: > > AFAIK no attempt was done to support EPROBE_DEFER with *_OF_DECLARE. > > IMHO it would be pointless, as it would be much easier to just switch to > real > > platform drivers. > > May be, may be not. > > From your point of view, the change is simple because it touches only a > single driver. > > From my point of view, the change implies a split in the approach while > I'm trying to unify the drivers little by little and there are hundred > of them. > > It is not the first time we face this situation and Bartosz Golaszewski > has a similar problem [1]. > > We have all the frameworks we need to solve this properly but I would > like something we can propagate to all drivers (OF and !OF) so we end up > with unified code. > > It is time we clearly state the dependency issues and we find a proper > way to solve it. On Thursday, August 30, 2018, Bartosz Golaszewski wrote: > This was my latest proposal for early platform drivers: > > https://lkml.org/lkml/2018/5/11/488 > > I still intend on continuing this work, I just don't have the time right > now. Daniel, So what is your final thought on this? The current OSTM driver uses TIMER_OF_DECLARE and that basically means it will never work with my new SoC. For now, can I change the driver to register a standard platform driver in subsys_initcall like the other Renesas timer drivers? Or do I have to live without a timer in my system for the unseeable future? If there every becomes a fix for this resource dependence, I'll be happy to modify the OSTM driver to comply. But at the moment, I'm stuck with nothing. Thanks, Chris
Applied "ASoC: rsnd: Add device tree binding for r8a77990" to the asoc tree
The patch ASoC: rsnd: Add device tree binding for r8a77990 has been applied to the asoc tree at https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark >From e058a4033240d30192124d6bf32b78e9a1f8975c Mon Sep 17 00:00:00 2001 From: Hiroyuki Yokoyama Date: Thu, 6 Sep 2018 22:28:33 +0900 Subject: [PATCH] ASoC: rsnd: Add device tree binding for r8a77990 This patch adds the device tree binding of the r8a77990 SoC. Signed-off-by: Hiroyuki Yokoyama Signed-off-by: Yoshihiro Kaneko Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/renesas,rsnd.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt index 8083f0d8f263..f4688c508be6 100644 --- a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt +++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt @@ -354,6 +354,7 @@ Required properties: - "renesas,rcar_sound-r8a7795" (R-Car H3) - "renesas,rcar_sound-r8a7796" (R-Car M3-W) - "renesas,rcar_sound-r8a77965" (R-Car M3-N) + - "renesas,rcar_sound-r8a77990" (R-Car E3) - reg : Should contain the register physical address. required register is SRU/ADG/SSI if generation1 -- 2.19.0.rc1
Re: [PATCH 4/4] clk: renesas: r8a77995: Add ZA2 clock
Hi Hoan,
On Fri, Sep 7, 2018 at 10:26 AM Nguyen An Hoan wrote:
> From: Hoan Nguyen An
>
> Add ZA2 clock support for the R8A77995 SoC
>
> Signed-off-by: Hoan Nguyen An
Thanks for your patch!
> --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
> @@ -80,6 +80,7 @@ static const struct cpg_core_clk r8a77995_core_clks[]
> __initconst = {
>
> /* Core Clock Outputs */
> DEF_FIXED("z2",R8A77995_CLK_Z2,CLK_PLL0D3, 1, 1),
> + DEF_FIXED("za2", R8A77995_CLK_ZA2, CLK_PLL0D3,10, 2),
(Why /10 * 2 instead of /5?)
ZA2 is not a fixed divider clock, but controlled through the ZA2 Clock
Control Register.
> DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
> DEF_FIXED("zt",R8A77995_CLK_ZT,CLK_PLL1, 4, 1),
> DEF_FIXED("zx",R8A77995_CLK_ZX,CLK_PLL1, 3, 1),
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: arm64: dts: salvator-common: Add PWM-2 channel
Dear Geert-san, Thank you very much for your comments!
CC: Simon-san
> Hi Hoan,
>
> On Wed, Aug 29, 2018 at 11:33 AM Nguyen An Hoan wrote:
> > From: Hoan Nguyen An
> >
> > Add PWM-2 channel(CN28 - pin30) support for Salvator-X
>
> Thanks for your patch!
>
> Please explain why this is useful. Usually we do not enable random
> functionality
> on expansion connectors.
> In this case, this even has an (undocumented) impact on on-board devices,
> as the signal is also connected to the BD9571MWV PMIC.
> (Perhaps that was the actual intention of this patch? ;-) If yes,
> please explain)
> Thanks!
> Gr{oetje,eeting}s,
> Geert
>
On this issue, with H3/M3 SoC there are 7 PWM channels but only 2 channels are
supported: PWM1, PWM2.
While PWM1 is connected to CN19 for LVDS service. So only remaining PWM2,
I think simple, if you want to generate a signal with variable frequency and
pulse width using M3/H3 (I used for testting Addition Tasks)
then forced to use PWM2. Although I'm not sure the H3/M3 boards are not
purposeful to use the PWM functions.
Thanks you!
Hoan
Re: [PATCH] clk: renesas: convert to SPDX identifiers
Hi Morimoto-san,
On Fri, Sep 7, 2018 at 3:57 AM Kuninori Morimoto
wrote:
> From: Kuninori Morimoto
>
> This patch updates license to use SPDX-License-Identifier
> instead of verbose license text.
>
> Signed-off-by: Kuninori Morimoto
Thanks for your patch!
> ---
> drivers/clk/renesas/Kconfig | 2 ++
> drivers/clk/renesas/clk-div6.c| 5 +
> drivers/clk/renesas/clk-emev2.c | 14 +-
> drivers/clk/renesas/clk-mstp.c| 5 +
> drivers/clk/renesas/clk-r8a73a4.c | 5 +
> drivers/clk/renesas/clk-r8a7740.c | 5 +
> drivers/clk/renesas/clk-r8a7778.c | 5 +
> drivers/clk/renesas/clk-r8a7779.c | 5 +
> drivers/clk/renesas/clk-rcar-gen2.c | 5 +
> drivers/clk/renesas/clk-rz.c | 5 +
> drivers/clk/renesas/clk-sh73a0.c | 5 +
> drivers/clk/renesas/r8a7743-cpg-mssr.c| 5 +
> drivers/clk/renesas/r8a7745-cpg-mssr.c| 5 +
> drivers/clk/renesas/r8a7790-cpg-mssr.c| 5 +
> drivers/clk/renesas/r8a7791-cpg-mssr.c| 5 +
> drivers/clk/renesas/r8a7792-cpg-mssr.c| 5 +
> drivers/clk/renesas/r8a7794-cpg-mssr.c| 5 +
> drivers/clk/renesas/r8a7795-cpg-mssr.c| 5 +
> drivers/clk/renesas/r8a7796-cpg-mssr.c| 5 +
> drivers/clk/renesas/r8a77970-cpg-mssr.c | 5 +
> drivers/clk/renesas/r8a77995-cpg-mssr.c | 5 +
> drivers/clk/renesas/rcar-gen2-cpg.c | 5 +
> drivers/clk/renesas/rcar-gen2-cpg.h | 7 ++-
> drivers/clk/renesas/rcar-gen3-cpg.c | 5 +
> drivers/clk/renesas/rcar-gen3-cpg.h | 7 ++-
> drivers/clk/renesas/rcar-usb2-clock-sel.c | 5 +
> drivers/clk/renesas/renesas-cpg-mssr.c| 5 +
> drivers/clk/renesas/renesas-cpg-mssr.h| 7 ++-
> include/linux/clk/renesas.h | 8 ++--
> 29 files changed, 34 insertions(+), 126 deletions(-)
This duplicates some of the work by Wolfram, which was already applied:
commit e848c2ea117f222b62715d5c4e1714ec4e0aa647
Author: Wolfram Sang
Date: Wed Aug 22 00:02:14 2018 +0200
clk: renesas: use SPDX identifier for Renesas drivers
Signed-off-by: Wolfram Sang
Reviewed-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Stephen Boyd
drivers/clk/renesas/clk-div6.c| 5 +
drivers/clk/renesas/r8a7795-cpg-mssr.c| 5 +
drivers/clk/renesas/r8a7796-cpg-mssr.c| 5 +
drivers/clk/renesas/r8a77995-cpg-mssr.c | 5 +
drivers/clk/renesas/rcar-gen3-cpg.c | 5 +
drivers/clk/renesas/rcar-usb2-clock-sel.c | 5 +
drivers/clk/renesas/renesas-cpg-mssr.c| 5 +
drivers/clk/renesas/renesas-cpg-mssr.h| 5 +
8 files changed, 8 insertions(+), 32 deletions(-)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: arm64: dts: salvator-common: Add PWM-2 channel
Dear Geert-san, Thank you very much for your comments!
CC: Simon-san
> Hi Hoan,
>
> On Wed, Aug 29, 2018 at 11:33 AM Nguyen An Hoan wrote:
> > From: Hoan Nguyen An
> >
> > Add PWM-2 channel(CN28 - pin30) support for Salvator-X
>
> Thanks for your patch!
>
> Please explain why this is useful. Usually we do not enable random
> functionality
> on expansion connectors.
> In this case, this even has an (undocumented) impact on on-board devices,
> as the signal is also connected to the BD9571MWV PMIC.
> (Perhaps that was the actual intention of this patch? ;-) If yes,
> please explain)
> Thanks!
> Gr{oetje,eeting}s,
> Geert
>
On this issue, with H3/M3 SoC there are 7 PWM channels but only 2 channels are
supported: PWM1, PWM2. While PWM1 is connected to CN19 for LVDS service. So
only remaining PWM2, I think simple, if you want to generate a signal with
variable frequency and pulse width using M3/H3 (I used for testting Addition
Tasks) then forced to use PWM2. Although I'm not sure the H3/M3 boards are not
purposeful to use the PWM functions.
Thanks you!
Hoan
Re: [PATCH 3/4] arm64: dts: r8a77995-draak: Enable Audio
Hi Nguyen
> From: Hoan Nguyen An
>
> This patch enables Audio support for the D3 Draak board on the R8A77995
>
> Signed-off-by: Hoan Nguyen An
> ---
(snip)
> + rsnd_ak4613: sound {
> + compatible = "simple-scu-audio-card";
I don't think you need to use "*-scu-*" sound card here.
"simple-audio-card" is enough
Re: [PATCH 2/4] arm64: dts: r8a77995: Add Audio device nodes
Hi Nguyen Thank you for your patch > From: Hoan Nguyen An > > This patch adds Audio device nodes for the R8A77995 > > Signed-off-by: Hoan Nguyen An > --- (snip) > + clock-names = "ssi-all", > + "ssi.9", "ssi.8", "ssi.7", "ssi.6", > + "ssi.5", "ssi.4", "ssi.3", "ssi.2", > + "ssi.1", "ssi.0", (snip) > + reset-names = "ssi-all", > + "ssi.9", "ssi.8", "ssi.7", "ssi.6", > + "ssi.5", "ssi.4", "ssi.3", "ssi.2", > + "ssi.1", "ssi.0"; These are strange. 77995 has SSI3/4 only,right ?
[PATCH 4/4] clk: renesas: r8a77995: Add ZA2 clock
From: Hoan Nguyen An
Add ZA2 clock support for the R8A77995 SoC
Signed-off-by: Hoan Nguyen An
---
drivers/clk/renesas/r8a77995-cpg-mssr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c
b/drivers/clk/renesas/r8a77995-cpg-mssr.c
index 49e6a0d..bc15daa 100644
--- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
@@ -80,6 +80,7 @@ static const struct cpg_core_clk r8a77995_core_clks[]
__initconst = {
/* Core Clock Outputs */
DEF_FIXED("z2",R8A77995_CLK_Z2,CLK_PLL0D3, 1, 1),
+ DEF_FIXED("za2", R8A77995_CLK_ZA2, CLK_PLL0D3,10, 2),
DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
DEF_FIXED("zt",R8A77995_CLK_ZT,CLK_PLL1, 4, 1),
DEF_FIXED("zx",R8A77995_CLK_ZX,CLK_PLL1, 3, 1),
--
2.7.4
[PATCH 3/4] arm64: dts: r8a77995-draak: Enable Audio
From: Hoan Nguyen An
This patch enables Audio support for the D3 Draak board on the R8A77995
Signed-off-by: Hoan Nguyen An
---
arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 123 +
1 file changed, 123 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
index a8e8f26..0f17335 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
@@ -83,6 +83,12 @@
reg = <0x0 0x4800 0x0 0x1800>;
};
+ x19_clk: x19_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ };
+
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
@@ -101,6 +107,36 @@
regulator-always-on;
};
+ audio_clkout: audio-clkout {
+ /*
+* This is same as <_sound 0>
+* but needed to avoid cs2000/rcar_sound probe dead-lock
+*/
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <11289600>;
+ };
+
+ rsnd_ak4613: sound {
+ compatible = "simple-scu-audio-card";
+
+ simple-audio-card,name = "rsnd-ak4613";
+ simple-audio-card,format = "left_j";
+ simple-audio-card,bitclock-master = <>;
+ simple-audio-card,frame-master = <>;
+
+ simple-audio-card,prefix = "ak4613";
+ simple-audio-card,routing = "ak4613 Playback", "DAI0 Playback",
+ "DAI0 Capture", "ak4613 Capture";
+ sndcpu: simple-audio-card,cpu {
+ sound-dai = <_sound>;
+ };
+
+ sndcodec: simple-audio-card,codec {
+sound-dai = <>;
+ };
+ };
+
x12_clk: x12 {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -162,6 +198,16 @@
power-source = <1800>;
};
+ sound_pins: sound {
+ groups = "ssi3_data", "ssi34_ctrl", "ssi4_data_a";
+ function = "ssi";
+ };
+
+ sound_clk_pins: sound_clk {
+ groups = "audio_clk_a", "audio_clk_b", "audio_clkout",
"audio_clkout1";
+ function = "audio_clk";
+ };
+
usb0_pins: usb0 {
groups = "usb0";
function = "usb0";
@@ -184,6 +230,33 @@
pagesize = <8>;
};
+ ak4613: codec@10 {
+ compatible = "asahi-kasei,ak4613";
+ #sound-dai-cells = <0>;
+ reg = <0x10>;
+ clocks = <_sound 3>;
+
+ asahi-kasei,in1-single-end;
+ asahi-kasei,in2-single-end;
+ asahi-kasei,out1-single-end;
+ asahi-kasei,out2-single-end;
+ asahi-kasei,out3-single-end;
+ asahi-kasei,out4-single-end;
+ asahi-kasei,out5-single-end;
+ asahi-kasei,out6-single-end;
+ };
+
+ cs2000: clk-multiplier@4f {
+ #clock-cells = <0>;
+ compatible = "cirrus,cs2000-cp";
+ reg = <0x4f>;
+ clocks = <_clkout>, <_clk>;
+ clock-names = "clk_in", "ref_clk";
+
+ assigned-clocks = <>;
+ assigned-clock-rates = <24576000>; /* 1/1 divide */
+ };
+
composite-in@20 {
compatible = "adi,adv7180cp";
reg = <0x20>;
@@ -352,6 +425,56 @@
status = "okay";
};
+_sound {
+ pinctrl-0 = <_pins _clk_pins>;
+ pinctrl-names = "default";
+
+ /* Single DAI */
+ #sound-dai-cells = <0>;
+
+ /* audio_clkout0/1/2/3 */
+ #clock-cells = <1>;
+ clock-frequency = <12288000 11289600>;
+ clkout-lr-synchronous;
+
+ status = "okay";
+
+ /* update to */
+ clocks = < CPG_MOD 1005>,
+< CPG_MOD 1005>, < CPG_MOD 1005>,
+< CPG_MOD 1005>, < CPG_MOD 1005>,
+< CPG_MOD 1005>, < CPG_MOD 1011>,
+< CPG_MOD 1012>, < CPG_MOD 1005>,
+< CPG_MOD 1005>, < CPG_MOD 1005>,
+< CPG_MOD 1017>, < CPG_MOD 1017>,
+< CPG_MOD 1017>, < CPG_MOD 1025>,
+< CPG_MOD 1026>, < CPG_MOD 1017>,
+< CPG_MOD 1017>, < CPG_MOD 1017>,
+< CPG_MOD 1017>, < CPG_MOD 1017>,
+< CPG_MOD 1020>, < CPG_MOD 1021>,
+< CPG_MOD 1020>, < CPG_MOD 1021>,
+< CPG_MOD 1019>, < CPG_MOD 1018>,
+<>, <_clk_b>,
+< CPG_CORE R8A77995_CLK_ZA2>;
+
+ rcar_sound,dai {
+
+ dai0 {
+ playback = < >;
+ capture = < >;
+
[PATCH 2/4] arm64: dts: r8a77995: Add Audio device nodes
From: Hoan Nguyen An
This patch adds Audio device nodes for the R8A77995
Signed-off-by: Hoan Nguyen An
---
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 183 ++
1 file changed, 183 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index 42d8dff..b96fc30 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -50,6 +50,23 @@
clock-frequency = <0>;
};
+ /*
+* The external audio clocks are configured as 0 Hz fixed frequency
+* clocks by default.
+* Boards that provide audio clocks should override them.
+*/
+ audio_clk_a: audio_clk_a {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_b: audio_clk_b {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts-extended = < GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
@@ -487,6 +504,172 @@
dma-channels = <16>;
};
+ rcar_sound: sound@ec50 {
+ /*
+* #sound-dai-cells is required
+*
+* Single DAI : #sound-dai-cells = <0>; <_sound>;
+* Multi DAI : #sound-dai-cells = <1>; <_sound N>;
+*/
+ /*
+* #clock-cells is required for audio_clkout0/1/2/3
+*
+* clkout : #clock-cells = <0>; <_sound>;
+* clkout0/1/2/3: #clock-cells = <1>; <_sound N>;
+*/
+ compatible = "renesas,rcar_sound-r8a77995",
"renesas,rcar_sound-gen3";
+ reg = <0 0xec50 0 0x1000>, /* SCU */
+ <0 0xec5a 0 0x100>, /* ADG */
+ <0 0xec54 0 0x1000>, /* SSIU */
+ <0 0xec541000 0 0x280>, /* SSI */
+ <0 0xec74 0 0x200>; /* Audio DMAC peri
peri*/
+ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+ clocks = < CPG_MOD 1005>,
+< CPG_MOD 1005>, < CPG_MOD 1005>,
+< CPG_MOD 1005>, < CPG_MOD 1005>,
+< CPG_MOD 1005>, < CPG_MOD 1011>,
+< CPG_MOD 1012>, < CPG_MOD 1005>,
+< CPG_MOD 1005>, < CPG_MOD 1005>,
+< CPG_MOD 1017>, < CPG_MOD 1017>,
+< CPG_MOD 1017>, < CPG_MOD 1025>,
+< CPG_MOD 1026>, < CPG_MOD 1017>,
+< CPG_MOD 1017>, < CPG_MOD 1017>,
+< CPG_MOD 1017>, < CPG_MOD 1017>,
+< CPG_MOD 1020>, < CPG_MOD 1021>,
+< CPG_MOD 1020>, < CPG_MOD 1021>,
+< CPG_MOD 1019>, < CPG_MOD 1018>,
+<_clk_a>, <_clk_b>,
+< CPG_CORE R8A77995_CLK_ZA2>;
+
+ clock-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0",
+ "src.9", "src.8", "src.7", "src.6",
+ "src.5", "src.4", "src.3", "src.2",
+ "src.1", "src.0",
+ "mix.1", "mix.0",
+ "ctu.1", "ctu.0",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b", "clk_i";
+ power-domains = < R8A77995_PD_ALWAYS_ON>;
+ resets = < 1005>,
+< 1006>, < 1007>,
+< 1008>, < 1009>,
+< 1010>, < 1011>,
+< 1012>, < 1013>,
+< 1014>, < 1015>;
+ reset-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0";
+ status = "disabled";
+
+ rcar_sound,dvc {
+ dvc0: dvc-0 {
+ dmas = < 0xbc>;
+
[PATCH 1/4] arm64: dts: r8a77995: Add Audio DMAC node
From: Hoan Nguyen An
This patch adds Audio-DMAC{0} node for the R8A77995
Signed-off-by: Hoan Nguyen An
---
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 34 +++
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index 625ba2b..42d8dff 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -453,6 +453,40 @@
<_ds1 22>, <_ds1 23>;
};
+ audma0: dma-controller@ec70 {
+ compatible = "renesas,dmac-r8a77995",
+"renesas,rcar-dmac";
+ reg = <0 0xec70 0 0x1>;
+ interrupts = ;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = < CPG_MOD 502>;
+ clock-names = "fck";
+ power-domains = < R8A77995_PD_ALWAYS_ON>;
+ resets = < 502>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ };
+
ipmmu_ds0: mmu@e674 {
compatible = "renesas,ipmmu-r8a77995";
reg = <0 0xe674 0 0x1000>;
--
2.7.4
[PATCH 0/4] Enable Audio support for the Draak D3 board on r8a77995.
From: Hoan Nguyen An These patches enable Audio support for the Draak D3 board on the r8a77995 SoC. Since Sound has a clock source for ADG from ZA2, add ZA2 clock. Thanks you for reading! Hoan Nguyen An (4): arm64: dts: r8a77995: Add Audio DMAC node arm64: dts: r8a77995: Add Audio device nodes arm64: dts: r8a77995-draak: Enable Audio clk: renesas: r8a77995: Add ZA2 clock arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 123 ++ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 217 + drivers/clk/renesas/r8a77995-cpg-mssr.c| 1 + 3 files changed, 341 insertions(+) -- 2.7.4
