RE: [PATCH 2/2] dt-bindings: pinctrl: Add RZ/A2 pinctrl and GPIO
On Tuesday, October 16, 2018, Rob Herring wrote: > > +Optional properties: > > + - gpio-controller > > +Include this in order to enable GPIO functionality. When included, > both > > +gpio_cells and gpio_ranges are then required. > > + - #gpio-cells > > +Must be 2 > > + - gpio-ranges > > +Expresses the total number GPIO ports/pins in this SoC > > Are these really optional? I guess in theory a board could use no GPIOs, > but that seems unlikely. They are 'optional' in the sense that if you don't include them in the DT, the driver still loads (just without any GPIO, but pinctrl still works). So, I was just documenting that fact. If you think I should just move these to required, let me know an I'm fine with that. (as in, DT documents HW, not software) > > +Sub-nodes > > +- > > + > > +The child nodes of the pin controller node describe a pin multiplexing > > +function or a GPIO controller alternatively. > > But the parent is already a GPIO controller. This needs to be fully > defined. Now that I read this, I think my wording was off (I was borrowing text for other files). How about this: The child nodes of the pin controller designate pins to be used for specific peripheral functions or as GPIO. Chris
Re: [PATCH 2/2] dt-bindings: pinctrl: Add RZ/A2 pinctrl and GPIO
On Fri, Oct 05, 2018 at 10:09:51AM -0500, Chris Brandt wrote:
> Add device tree binding documentation and header file for Renesas R7S9210
> (RZ/A2) SoCs.
>
> Signed-off-by: Chris Brandt
> ---
> .../bindings/pinctrl/renesas,rza2-pinctrl.txt | 76
> ++
> include/dt-bindings/pinctrl/r7s9210-pinctrl.h | 47 +
> 2 files changed, 123 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt
> create mode 100644 include/dt-bindings/pinctrl/r7s9210-pinctrl.h
>
> diff --git
> a/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt
> b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt
> new file mode 100644
> index ..5f338054f493
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt
> @@ -0,0 +1,76 @@
> +Renesas RZ/A2 combined Pin and GPIO controller
> +
> +The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO
> controller.
> +Pin multiplexing and GPIO configuration is performed on a per-pin basis.
> +Each port features up to 8 pins, each of them configurable for GPIO
> +function (port mode) or in alternate function mode.
> +Up to 8 different alternate function modes exist for each single pin.
> +
> +Pin controller node
> +---
> +
> +Required properties:
> + - compatible: should be:
> +- "renesas,r7s9210-pinctrl": for RZ/A2M
> +
> + - reg
> +address base and length of the memory area where the pin controller
> +hardware is mapped to.
> +
> +Optional properties:
> + - gpio-controller
> +Include this in order to enable GPIO functionality. When included, both
> +gpio_cells and gpio_ranges are then required.
> + - #gpio-cells
> +Must be 2
> + - gpio-ranges
> +Expresses the total number GPIO ports/pins in this SoC
Are these really optional? I guess in theory a board could use no GPIOs,
but that seems unlikely.
> +
> +
> +Example: Pin controller node for RZ/A2M SoC (r7s9210)
> +
> + pinctrl: pin-controller@fcffe000 {
> + compatible = "renesas,r7s9210-pinctrl";
> + reg = <0xfcffe000 0x9D1>;
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = < 0 0 176>;
> + };
> +
> +Sub-nodes
> +-
> +
> +The child nodes of the pin controller node describe a pin multiplexing
> +function or a GPIO controller alternatively.
But the parent is already a GPIO controller. This needs to be fully
defined.
> +
> +- Pin multiplexing sub-nodes:
> + A pin multiplexing sub-node describes how to configure a set of
> + (or a single) pin in some desired alternate function mode.
> + The values for the pinmux properties are a combination of port name, pin
> + number and the desired function index. Use the RZA2_PINMUX macro located
> + in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily define these.
> + For assigning GPIO pins, use the macro RZA2_PIN_ID also in
> r7s9210-pinctrl.h
> + to express the desired port pin.
> +
> + Example: Board specific pins configuration
> +
> + {
> + /* Serial Console */
> + scif4_pins: serial4 {
> + pinmux = , /* TxD4 */
> + ; /* RxD4 */
> + };
> + };
> +
> + Example: Assigning a GPIO:
> +
> + leds {
> + status = "okay";
> + compatible = "gpio-leds";
> +
> + led0 {
> + /* P6_0 */
> + gpios = < RZA2_PIN_ID(P6, 0) GPIO_ACTIVE_HIGH>;
> + };
> + };
[PATCH] arm64: dts: renesas: r8a779{7|8}0: add MSIOF support
Describe MSIOF in the R8A779{7|8}0 device trees.
The DMA props are deliberately omitted as the MSIOF DMA doesn't work on
R8A77970 (due to IPMMU issue) and the RT-DMAC isn't supported on R8A77980.
Signed-off-by: Sergei Shtylyov
---
This patch is against the 'renesas-devel-20181015-v4.19-rc8' branch of
Simon Horman's 'renesas.git' repo.
The MSIOF bindings patch has just been posted...
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 56 ++
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 56 ++
2 files changed, 112 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
===
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -22,6 +22,10 @@
i2c2 =
i2c3 =
i2c4 =
+ spi1 =
+ spi2 =
+ spi3 =
+ spi4 =
};
/* External CAN clock - to be overridden by boards that provide it */
@@ -688,6 +692,58 @@
status = "disabled";
};
+ msiof0: spi@e6e9 {
+ compatible = "renesas,msiof-r8a77970",
+"renesas,rcar-gen3-msiof";
+ reg = <0 0xe6e9 0 0x64>;
+ interrupts = ;
+ clocks = < CPG_MOD 211>;
+ power-domains = < R8A77970_PD_ALWAYS_ON>;
+ resets = < 211>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof1: spi@e6ea {
+ compatible = "renesas,msiof-r8a77970",
+"renesas,rcar-gen3-msiof";
+ reg = <0 0xe6ea 0 0x0064>;
+ interrupts = ;
+ clocks = < CPG_MOD 210>;
+ power-domains = < R8A77970_PD_ALWAYS_ON>;
+ resets = < 210>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof2: spi@e6c0 {
+ compatible = "renesas,msiof-r8a77970",
+"renesas,rcar-gen3-msiof";
+ reg = <0 0xe6c0 0 0x0064>;
+ interrupts = ;
+ clocks = < CPG_MOD 209>;
+ power-domains = < R8A77970_PD_ALWAYS_ON>;
+ resets = < 209>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof3: spi@e6c1 {
+ compatible = "renesas,msiof-r8a77970",
+"renesas,rcar-gen3-msiof";
+ reg = <0 0xe6c1 0 0x0064>;
+ interrupts = ;
+ clocks = < CPG_MOD 208>;
+ power-domains = < R8A77970_PD_ALWAYS_ON>;
+ resets = < 208>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
vin0: video@e6ef {
compatible = "renesas,vin-r8a77970";
reg = <0 0xe6ef 0 0x1000>;
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -23,6 +23,10 @@
i2c3 =
i2c4 =
i2c5 =
+ spi1 =
+ spi2 =
+ spi3 =
+ spi4 =
};
/* External CAN clock - to be overridden by boards that provide it */
@@ -740,6 +744,58 @@
status = "disabled";
};
+ msiof0: spi@e6e9 {
+ compatible = "renesas,msiof-r8a77980",
+"renesas,rcar-gen3-msiof";
+ reg = <0 0xe6e9 0 0x64>;
+ interrupts = ;
+ clocks = < CPG_MOD 211>;
+ power-domains = < R8A77980_PD_ALWAYS_ON>;
+ resets = < 211>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof1: spi@e6ea {
+ compatible = "renesas,msiof-r8a77980",
+"renesas,rcar-gen3-msiof";
+ reg
[PATCH] dt-bindings: spi: sh-msiof: document R8A779{7|8}0 bindings
Document the R-Car V3{M|H} (R8A779{7|8}0) SoCs in the Renesas MSIOF
bindings.
Signed-off-by: Sergei Shtylyov
---
The patch is against the 'for-next' branch of Mark Brown's 'spi.git' repo.
Documentation/devicetree/bindings/spi/sh-msiof.txt |2 ++
1 file changed, 2 insertions(+)
Index: spi/Documentation/devicetree/bindings/spi/sh-msiof.txt
===
--- spi.orig/Documentation/devicetree/bindings/spi/sh-msiof.txt
+++ spi/Documentation/devicetree/bindings/spi/sh-msiof.txt
@@ -13,6 +13,8 @@ Required properties:
"renesas,msiof-r8a7795" (R-Car H3)
"renesas,msiof-r8a7796" (R-Car M3-W)
"renesas,msiof-r8a77965" (R-Car M3-N)
+"renesas,msiof-r8a77970" (R-Car V3M)
+"renesas,msiof-r8a77980" (R-Car V3H)
"renesas,msiof-r8a77990" (R-Car E3)
"renesas,msiof-r8a77995" (R-Car D3)
"renesas,msiof-sh73a0" (SH-Mobile AG5)
Re: [PATCH] MAINTAINERS: Add Renesas RZ/A and RZ/N files to Renesas pinctrl section
Hi Geert, On Tue, Oct 16, 2018 at 01:56:53PM +0200, Geert Uytterhoeven wrote: > Add paths for the Renesas RZ/A and RZ/N series pin controller drivers, > as they are not under sh-pfc/, but still maintained with the other > Renesas pin controller drivers. > > Signed-off-by: Geert Uytterhoeven Acked-by: Jacopo Mondi Thank you j > --- > To be queued in sh-pfc-for-v4.21. > > MAINTAINERS | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 809600de0b7293c8..77ff83bc09464c1f 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -11672,6 +11672,7 @@ M:Geert Uytterhoeven > L: linux-renesas-soc@vger.kernel.org > T: git > git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git sh-pfc > S: Maintained > +F: drivers/pinctrl/pinctrl-rz* > F: drivers/pinctrl/sh-pfc/ > > PIN CONTROLLER - SAMSUNG > -- > 2.17.1 > signature.asc Description: PGP signature
Re: [PATCH] MAINTAINERS: Add Renesas RZ/A and RZ/N files to Renesas pinctrl section
On Tue, Oct 16, 2018 at 01:56:53PM +0200, Geert Uytterhoeven wrote: > Add paths for the Renesas RZ/A and RZ/N series pin controller drivers, > as they are not under sh-pfc/, but still maintained with the other > Renesas pin controller drivers. > > Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman > --- > To be queued in sh-pfc-for-v4.21. > > MAINTAINERS | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 809600de0b7293c8..77ff83bc09464c1f 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -11672,6 +11672,7 @@ M:Geert Uytterhoeven > L: linux-renesas-soc@vger.kernel.org > T: git > git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git sh-pfc > S: Maintained > +F: drivers/pinctrl/pinctrl-rz* > F: drivers/pinctrl/sh-pfc/ > > PIN CONTROLLER - SAMSUNG > -- > 2.17.1 >
[PATCH] MAINTAINERS: Add Renesas RZ/A and RZ/N files to Renesas pinctrl section
Add paths for the Renesas RZ/A and RZ/N series pin controller drivers, as they are not under sh-pfc/, but still maintained with the other Renesas pin controller drivers. Signed-off-by: Geert Uytterhoeven --- To be queued in sh-pfc-for-v4.21. MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 809600de0b7293c8..77ff83bc09464c1f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11672,6 +11672,7 @@ M: Geert Uytterhoeven L: linux-renesas-soc@vger.kernel.org T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git sh-pfc S: Maintained +F: drivers/pinctrl/pinctrl-rz* F: drivers/pinctrl/sh-pfc/ PIN CONTROLLER - SAMSUNG -- 2.17.1
[PATCH/RFC v2] serial: sh-sci: Fix fallback to PIO on DMA failure
When submitting a DMA request fails, the driver is supposed to fall back
to PIO. However, this never really worked due to various reasons
(sh-sci driver issues and dmaengine framework limitations).
There are three places where DMA submission can fail, and the driver
should fall back to PIO:
1. sci_dma_rx_complete(),
2. sci_submit_rx(),
3. work_fn_tx().
This RFC fixes fallback to PIO in the receive path (cases 1 and 2).
Fallback to PIO in the transmit path (case 3) already works fine.
Case 1: sci_dma_rx_complete()
A. PIO cannot take over on SCIF if any DMA transactions are pending,
hence they must be terminated first.
B. The active cookies must be invalidated, else rx_timer_fn() may
trigger a NULL pointer dereference.
C. Restarting the port is not needed, as it is already running, but
serial port interrupts must be directed back from the DMA engine to
the CPU.
Case 2: sci_submit_rx()
D. Some callers of sci_submit_rx() hold the port spinlock, others
don't. During fallback to PIO, the driver needs to obtain the port
spinlock. If the lock was already held, spinlock recursion is
detected, causing a deadlock: BUG: spinlock recursion on CPU#0.
Fix this by adding a flag parameter to sci_submit_rx() for the
caller to indicate the port spinlock is already held, so spinlock
recursion can be avoided.
Move the spin_lock_irqsave() up, so all DMA disable steps are
protected, which is safe as the recently introduced
dmaengine_terminate_async() can be called in atomic context.
E. When falling back to PIO, active_rx must be set to a different
value than cookie_rx[i], else sci_dma_rx_find_active() will
incorrectly find a match, leading to a NULL pointer dereference in
rx_timer_fn() later.
F. On (H)SCIF, sci_submit_rx() is called in the receive interrupt
handler. Hence if DMA submission fails, the interrupt handler
should handle reception using PIO.
Signed-off-by: Geert Uytterhoeven
---
Against tty/next + "serial: sh-sci: Fix receive on SCIFA/SCIFB variants
with DMA".
All testing was done on r8a7791/koelsch using SCIF1 on debug serial 1,
and SCIFA3 on EXIO-B, by introducing random failures in DMA submission
code.
Thanks for your comments!
v2:
- Fix fallback in sci_dma_rx_complete(),
- Fallback in the transmit path already works fine,
- Widen audience, but keep RFC.
---
drivers/tty/serial/sh-sci.c | 34 +-
1 file changed, 25 insertions(+), 9 deletions(-)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 3aad48e64b9b71ff..30b2728c20d6e982 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -1272,6 +1272,7 @@ static void sci_dma_rx_complete(void *arg)
struct dma_async_tx_descriptor *desc;
unsigned long flags;
int active, count = 0;
+ unsigned int i;
dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
s->active_rx);
@@ -1309,12 +1310,22 @@ static void sci_dma_rx_complete(void *arg)
return;
fail:
+ dmaengine_terminate_async(chan);
spin_unlock_irqrestore(>lock, flags);
dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
/* Switch to PIO */
spin_lock_irqsave(>lock, flags);
+ for (i = 0; i < 2; i++)
+ s->cookie_rx[i] = -EINVAL;
+ s->active_rx = 0;
s->chan_rx = NULL;
- sci_start_rx(port);
+ /* Direct new serial port interrupts back to CPU */
+ scr = serial_port_in(port, SCSCR);
+ if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
+ scr &= ~SCSCR_RDRQE;
+ enable_irq(s->irqs[SCIx_RXI_IRQ]);
+ }
+ serial_port_out(port, SCSCR, scr | SCSCR_RIE);
spin_unlock_irqrestore(>lock, flags);
}
@@ -1331,7 +1342,7 @@ static void sci_tx_dma_release(struct sci_port *s)
dma_release_channel(chan);
}
-static void sci_submit_rx(struct sci_port *s)
+static int sci_submit_rx(struct sci_port *s, bool port_lock_held)
{
struct dma_chan *chan = s->chan_rx;
struct uart_port *port = >port;
@@ -1359,19 +1370,22 @@ static void sci_submit_rx(struct sci_port *s)
s->active_rx = s->cookie_rx[0];
dma_async_issue_pending(chan);
- return;
+ return 0;
fail:
+ if (!port_lock_held)
+ spin_lock_irqsave(>lock, flags);
if (i)
dmaengine_terminate_async(chan);
for (i = 0; i < 2; i++)
s->cookie_rx[i] = -EINVAL;
- s->active_rx = -EINVAL;
+ s->active_rx = 0;
/* Switch to PIO */
- spin_lock_irqsave(>lock, flags);
s->chan_rx = NULL;
sci_start_rx(port);
- spin_unlock_irqrestore(>lock, flags);
+ if (!port_lock_held)
+ spin_unlock_irqrestore(>lock, flags);
+ return -1;
}
static void work_fn_tx(struct work_struct *work)
[PATCH] pinctrl: sh-pfc: Reduce kernel size for narrow VIN channels
Some VIN channels support less than 24 lanes. As union vin_data always
consumes space for 24 lanes, this wastes memory.
Hence introduce new smaller unions vin_data12 and vin_data16, to
accommodate VIN channels with only 12 or 16 lanes.
This reduces the static pin controller driver size by 320 bytes for
R-Car V2H, and by 96 bytes for R-Car E2.
Signed-off-by: Geert Uytterhoeven
---
To be queued in sh-pfc-for-v4.21.
drivers/pinctrl/sh-pfc/pfc-r8a7792.c | 16
drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 4 ++--
drivers/pinctrl/sh-pfc/sh_pfc.h | 17 +++--
3 files changed, 25 insertions(+), 12 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c
b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c
index bf0681b381819a4b..e977121b433b773c 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c
@@ -1474,7 +1474,7 @@ static const unsigned int vin1_clk_mux[] = {
VI1_CLK_MARK,
};
/* - VIN2 ---
*/
-static const union vin_data vin2_data_pins = {
+static const union vin_data16 vin2_data_pins = {
.data16 = {
RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
@@ -1486,7 +1486,7 @@ static const union vin_data vin2_data_pins = {
RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
},
};
-static const union vin_data vin2_data_mux = {
+static const union vin_data16 vin2_data_mux = {
.data16 = {
VI2_D0_C0_MARK, VI2_D1_C1_MARK,
VI2_D2_C2_MARK, VI2_D3_C3_MARK,
@@ -1524,7 +1524,7 @@ static const unsigned int vin2_clk_mux[] = {
VI2_CLK_MARK,
};
/* - VIN3 ---
*/
-static const union vin_data vin3_data_pins = {
+static const union vin_data16 vin3_data_pins = {
.data16 = {
RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
@@ -1536,7 +1536,7 @@ static const union vin_data vin3_data_pins = {
RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16),
},
};
-static const union vin_data vin3_data_mux = {
+static const union vin_data16 vin3_data_mux = {
.data16 = {
VI3_D0_C0_MARK, VI3_D1_C1_MARK,
VI3_D2_C2_MARK, VI3_D3_C3_MARK,
@@ -1574,7 +1574,7 @@ static const unsigned int vin3_clk_mux[] = {
VI3_CLK_MARK,
};
/* - VIN4 ---
*/
-static const union vin_data vin4_data_pins = {
+static const union vin_data12 vin4_data_pins = {
.data12 = {
RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
@@ -1584,7 +1584,7 @@ static const union vin_data vin4_data_pins = {
RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15),
},
};
-static const union vin_data vin4_data_mux = {
+static const union vin_data12 vin4_data_mux = {
.data12 = {
VI4_D0_C0_MARK, VI4_D1_C1_MARK,
VI4_D2_C2_MARK, VI4_D3_C3_MARK,
@@ -1620,7 +1620,7 @@ static const unsigned int vin4_clk_mux[] = {
VI4_CLK_MARK,
};
/* - VIN5 ---
*/
-static const union vin_data vin5_data_pins = {
+static const union vin_data12 vin5_data_pins = {
.data12 = {
RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
@@ -1630,7 +1630,7 @@ static const union vin_data vin5_data_pins = {
RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15),
},
};
-static const union vin_data vin5_data_mux = {
+static const union vin_data12 vin5_data_mux = {
.data12 = {
VI5_D0_C0_MARK, VI5_D1_C1_MARK,
VI5_D2_C2_MARK, VI5_D3_C3_MARK,
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
index 6d1e5fdc03f84554..b96a3cc79084ddcc 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
@@ -3704,7 +3704,7 @@ static const unsigned int vin0_clk_mux[] = {
VI0_CLK_MARK,
};
/* - VIN1 ---
*/
-static const union vin_data vin1_data_pins = {
+static const union vin_data12 vin1_data_pins = {
.data12 = {
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
@@ -3714,7 +3714,7 @@ static const union vin_data vin1_data_pins = {
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
},
};
-static const union vin_data vin1_data_mux = {
+static const union vin_data12 vin1_data_mux = {
.data12 = {
VI1_DATA0_MARK, VI1_DATA1_MARK,
VI1_DATA2_MARK, VI1_DATA3_MARK,
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 458ae0a6b5404631..1fc13366869abd4c 100644
---
Re: [PATCH] MAINTAINERS: Remove Laurent Pinchart as Renesas pinctrl maintainer
CC pinctrl
On Tue, Oct 16, 2018 at 12:33 PM Laurent Pinchart
wrote:
> Geert Uytterhoeven has long taken over and I'm not involved anymore with
> the Renesas pinctrl driver. Remove myself from the maintainers list.
>
> Signed-off-by: Laurent Pinchart
Thank you, will queue in sh-pfc-for-v4.21.
> ---
> MAINTAINERS | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 69373eb328d4..f9d00cc05202 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -11515,7 +11515,6 @@ F:
> Documentation/devicetree/bindings/pinctrl/qcom,*.txt
> F: drivers/pinctrl/qcom/
>
> PIN CONTROLLER - RENESAS
> -M: Laurent Pinchart
> M: Geert Uytterhoeven
> L: linux-renesas-soc@vger.kernel.org
> T: git
> git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git sh-pfc
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH] dt-bindings: pwm: renesas: pwm-rcar: document R8A779{7|8}0 bindings
On Mon, Oct 15, 2018 at 01:57:13PM -0500, Rob Herring wrote:
> On Fri, Oct 12, 2018 at 01:21:14PM +0200, Thierry Reding wrote:
> > On Mon, Oct 01, 2018 at 10:57:39PM +0300, Sergei Shtylyov wrote:
> > > Document the R-Car V3{M|H} (R8A779{7|8}0) SoC in the Renesas R-Car PWM
> > > bindings. R8A77970's hardware is a generic R-Car gen3 PWM, while R8A77980
> > > has an extra error injection register...
> > >
> > > Signed-off-by: Sergei Shtylyov
> > >
> > > ---
> > > This patch is against the 'for-next' branch of Thierry Reding's
> > > 'linux-pwm.git'
> > > repo.
> > >
> > > Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt |2 ++
> > > 1 file changed, 2 insertions(+)
> >
> > Applied, thanks.
>
> Some reason your tree isn't updated for linux-next?
No particular reason, I just had not pushed it out yet because the build
tests were taking longer than expected and I had to clean up a couple of
minor things.
It's pushed out now.
Thierry
signature.asc
Description: PGP signature
[PATCH] MAINTAINERS: Remove Laurent Pinchart as Renesas pinctrl maintainer
Geert Uytterhoeven has long taken over and I'm not involved anymore with the Renesas pinctrl driver. Remove myself from the maintainers list. Signed-off-by: Laurent Pinchart --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 69373eb328d4..f9d00cc05202 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11515,7 +11515,6 @@ F: Documentation/devicetree/bindings/pinctrl/qcom,*.txt F: drivers/pinctrl/qcom/ PIN CONTROLLER - RENESAS -M: Laurent Pinchart M: Geert Uytterhoeven L: linux-renesas-soc@vger.kernel.org T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git sh-pfc -- Regards, Laurent Pinchart
[PATCH v4 2/6] pinctrl: sh-pfc: r8a77470: Add SDHI support
Add SH_PFC_PIN_CFG_IO_VOLTAGE definition for the SDHI pins
capable of switching voltage, also add pin groups and functions
for SDHI0 and SDHI1. Please note that with the RZ/G1C only 1
bit of the POC Control Register is used to control each interface.
Signed-off-by: Fabrizio Castro
Reviewed-by: Biju Das
Reviewed-by: Geert Uytterhoeven
---
v3->v4:
* Fixed voltage control of GP0_11 and GP0_12
v2->v3:
* No change
v1->v2:
* Reworked implementation of r8a77470_pin_to_pocctrl as per Wolfram's
and Geert's comments
* Added SDHI0 and SDHI1 pins and IO voltage control
* Added SDHI0 and SDHI1 pin groups and functions
* Reworked changelog and title
* Please note that there is some overlapping between mmc pin groups
and sdhi1 pin groups
---
drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 162 +-
1 file changed, 160 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
index 5e29b95..4359aeb 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
@@ -10,14 +10,45 @@
#include "sh_pfc.h"
#define CPU_ALL_PORT(fn, sfx) \
- PORT_GP_23(0, fn, sfx), \
+ PORT_GP_4(0, fn, sfx), \
+ PORT_GP_1(0, 4, fn, sfx), \
+ PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_1(0, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_1(0, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_1(0, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_1(0, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_1(0, 11, fn, sfx), \
+ PORT_GP_1(0, 12, fn, sfx), \
+ PORT_GP_CFG_1(0, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_1(0, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_1(0, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_1(0, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_1(0, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_1(0, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_1(0, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_1(0, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_1(0, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_1(0, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_23(1, fn, sfx), \
PORT_GP_32(2, fn, sfx), \
PORT_GP_17(3, fn, sfx), \
PORT_GP_1(3, 27, fn, sfx), \
PORT_GP_1(3, 28, fn, sfx), \
PORT_GP_1(3, 29, fn, sfx), \
- PORT_GP_26(4, fn, sfx), \
+ PORT_GP_14(4, fn, sfx), \
+ PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_1(4, 20, fn, sfx), \
+ PORT_GP_1(4, 21, fn, sfx), \
+ PORT_GP_1(4, 22, fn, sfx), \
+ PORT_GP_1(4, 23, fn, sfx), \
+ PORT_GP_1(4, 24, fn, sfx), \
+ PORT_GP_1(4, 25, fn, sfx), \
PORT_GP_32(5, fn, sfx)
enum {
@@ -1865,6 +1896,81 @@ static const unsigned int scif_clk_b_pins[] = {
static const unsigned int scif_clk_b_mux[] = {
SCIF_CLK_B_MARK,
};
+/* - SDHI0 --
*/
+static const unsigned int sdhi0_data1_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(0, 7),
+};
+static const unsigned int sdhi0_data1_mux[] = {
+ SD0_DAT0_MARK,
+};
+static const unsigned int sdhi0_data4_pins[] = {
+ /* D[0:3] */
+ RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
+ RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
+};
+static const unsigned int sdhi0_data4_mux[] = {
+ SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
+};
+static const unsigned
RE: USB2.0 blocks on RZ/G1C
Hi Shimoda-San, Thanks for the feedback. > > Subject: RE: USB2.0 blocks on RZ/G1C > > > > Hello Shimoda-San and all, > > > > RZ/G1C USB2.0 host/function controller has the below features > > compared to R-Car Gen2/Gen3 USB2.0 block > > > > 1) It has a shared pll reset register for hsusb0/hsusb1 and this register > reside in hsusb0 block. > > 2) This implies, in order to enable USB1 host/peripheral, we need to enable > hsusb0 block as well. > > 3) USB2.0 Host controller block is similar to R-Car Gen3 USB2.0 host > controller but with > >few register sets. There is no PLL reset on the host side(USBCTR). > > I also checked the RZ/G1C datasheet and I understood them. > - Each USB host needs to deassert the pll reset only if RZ/G1C. > (In other words, other RZ/G1 and R-Car Gen2/3 don't need to deassert the > pll reset of hsusb block for host side.) > > > To address 1 and 3, I have modified the phy-rcar-gen2 with rz/g1c specific > phy_ops . > > Also added optional usb2.0 host reg property for initializing > > interrupt enable, OVC detection timer and Suspend/resume timer register > . > If so, you also have to add optional usb2.0 host clock and enable the clock on > the phy-rcar-gen2 driver. OK. Will add this in phy-rcar-gen2 driver. > > I will send the patch based on the below discussion. > > > > To address 2, I am seeing 2 solutions > > > > solution 1) On the SoC dtsi->define USB1 clocks(ehci1/ohci1/hsusb1) and > > On the board dts-> enable hsusb0 + usb1 host/peripheral. > > > > solution 2) On the SoC dtsi->define USB1 clocks(ehci1/ohci1/hsusb1) > followed by hsusb0 clock and > > On the board dts-> enable only usb1 host/peripheral. > > This will allow us to do pll reset without enabling > > hsusb0 on the > board dts. > > I'm afraid but I don't understand these 2 solutions. Where are the USB1 > clocks defined? - ehci0/ohci0/hsusb0 nodes have phys property with usbphy0. - ehci1/ohci1/hsusb1 nodes have phys property with usbphy1 To achieve2, I have added usbphy0 clock + usb1 (ehci1/ohc1/hsusb1) clocks to ehci1/ohc1/hsusb1 node. > > Do you have any preferences one way or the other? Or a third option? > > I'm thinking which nodes we will have on RZ/G1C dtsi: > - We will have ehci[01]/ohci[01]/hsusb[01]/usbphy[01] nodes. > - ehci0/ohci0/hsusb0 nodes have phys property with usbphy0. > - ehci1/ohci1/hsusb1 nodes have phys property with both usbphy0 and > usbphy1 to achieve the 2) you mentioned above. > - usbphy[01] has reg/clocks as both own hsusb and usb host blocks. Looks this solution is better. I will submit the patches based on this. > About the phy driver: > - Add the 1) and 3) you mentioned above. Regards, Biju Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
Re: [PATCH v2] pinctrl: rzn1: Fix check for used MDIO bus
Hi Phil,
On Tue, Oct 16, 2018 at 08:04:53AM +, Phil Edworthy wrote:
> Hi Jacopo,
>
> On 15 October 2018 16:12 jacopo mondi wrote:
> > On Mon, Oct 15, 2018 at 04:01:47PM +0100, Phil Edworthy wrote:
> > > This fixes the check for unused mdio bus setting and the following
> > > static checker warning:
> > > drivers/pinctrl/pinctrl-rzn1.c:198 rzn1_pinctrl_mdio_select()
> > > warn: always true condition '(ipctl->mdio_func[mdio] >= 0) => (0-u32max
> > >= 0)'
> > >
> > > It also fixes the return var when calling of_get_child_count()
> > >
> >
> > Not really, since you skip the assignement if return value is <= 0:
> >
> > nfuncs = of_get_child_count(np);
> > if (nfuncs <= 0)
> > return 0;
> >
> > ipctl->nfunctions = nfuncs;
> >
> > This seems more likely to be here to make 'rzn1_pmx_get_funcs_count()'
> > happy, as it returns a signed integer, but since nfunctions is only
> > assigned if
> > 'nfuncs' > 0, then the cast is safe there.
> >
> > I would keep this unsigned, and rather return an error if
> > 'of_get_child_count()' returns an error of any sort in 'probe_dt()',
> > otherwise
> > assign 'ipctl->nfunctions = nfuncs;' unconditionally and return immediately
> > if
> > nfuncs == 0. This makes sure nfunctions is initialized even if there are no
> > functions registered.
> Ok, I get what you're saying, though nfunctions will always be initialised due
> to allocation with devm_kzalloc.
>
Right, sorry for missing that.
> > Anyway, small issues, this just doesn't belong to this patch, but it's
> > likely not
> > to cause any harm I guess.
> True... should I leave this patch as is or respin again?
I think you should handle the case where of_get_child_count() returns
an error, but in a follow up patch. You can leave this one as it is,
even if that change is imho not necessary.
Thanks
j
>
> Thanks
> Phil
>
> > > Reported-by: Dan Carpenter
> > > Signed-off-by: Phil Edworthy
> > > ---
> > > v2:
> > > - Don't use implicit type conversion.
> > > - Fix type of return var when calling of_get_child_count().
> > > ---
> > > drivers/pinctrl/pinctrl-rzn1.c | 10 +-
> > > 1 file changed, 5 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/pinctrl/pinctrl-rzn1.c
> > > b/drivers/pinctrl/pinctrl-rzn1.c index ce05e3a00be2..4998463c54a0
> > > 100644
> > > --- a/drivers/pinctrl/pinctrl-rzn1.c
> > > +++ b/drivers/pinctrl/pinctrl-rzn1.c
> > > @@ -112,13 +112,13 @@ struct rzn1_pinctrl {
> > > struct rzn1_pinctrl_regs __iomem *lev2;
> > > u32 lev1_protect_phys;
> > > u32 lev2_protect_phys;
> > > - u32 mdio_func[2];
> > > + int mdio_func[2];
> > >
> > > struct rzn1_pin_group *groups;
> > > unsigned int ngroups;
> > >
> > > struct rzn1_pmx_func *functions;
> > > - unsigned int nfunctions;
> > > + int nfunctions;
> > > };
> > >
> > > #define RZN1_PINS_PROP "pinmux"
> > > @@ -195,9 +195,9 @@ static void rzn1_hw_set_lock(struct rzn1_pinctrl
> > > *ipctl, u8 lock, u8 value) static void rzn1_pinctrl_mdio_select(struct
> > rzn1_pinctrl *ipctl, int mdio,
> > >u32 func)
> > > {
> > > - if (ipctl->mdio_func[mdio] >= 0 && ipctl->mdio_func[mdio] != func)
> > > + if (ipctl->mdio_func[mdio] >= 0 && ipctl->mdio_func[mdio] !=
> > > +(int)func)
> > > dev_warn(ipctl->dev, "conflicting setting for mdio%d!\n",
> > mdio);
> > > - ipctl->mdio_func[mdio] = func;
> > > + ipctl->mdio_func[mdio] = (int)func;
> > >
> > > dev_dbg(ipctl->dev, "setting mdio%d to %u\n", mdio, func);
> > >
> > > @@ -810,8 +810,8 @@ static int rzn1_pinctrl_probe_dt(struct
> > platform_device *pdev,
> > > struct device_node *np = pdev->dev.of_node;
> > > struct device_node *child;
> > > unsigned int maxgroups = 0;
> > > - unsigned int nfuncs = 0;
> > > unsigned int i = 0;
> > > + int nfuncs = 0;
> > > int ret;
> > >
> > > nfuncs = of_get_child_count(np);
> > > --
> > > 2.17.1
> > >
signature.asc
Description: PGP signature
RE: [PATCH v2] pinctrl: rzn1: Fix check for used MDIO bus
Hi Jacopo,
On 15 October 2018 16:12 jacopo mondi wrote:
> On Mon, Oct 15, 2018 at 04:01:47PM +0100, Phil Edworthy wrote:
> > This fixes the check for unused mdio bus setting and the following
> > static checker warning:
> > drivers/pinctrl/pinctrl-rzn1.c:198 rzn1_pinctrl_mdio_select()
> > warn: always true condition '(ipctl->mdio_func[mdio] >= 0) => (0-u32max
> >= 0)'
> >
> > It also fixes the return var when calling of_get_child_count()
> >
>
> Not really, since you skip the assignement if return value is <= 0:
>
> nfuncs = of_get_child_count(np);
> if (nfuncs <= 0)
> return 0;
>
> ipctl->nfunctions = nfuncs;
>
> This seems more likely to be here to make 'rzn1_pmx_get_funcs_count()'
> happy, as it returns a signed integer, but since nfunctions is only assigned
> if
> 'nfuncs' > 0, then the cast is safe there.
>
> I would keep this unsigned, and rather return an error if
> 'of_get_child_count()' returns an error of any sort in 'probe_dt()', otherwise
> assign 'ipctl->nfunctions = nfuncs;' unconditionally and return immediately if
> nfuncs == 0. This makes sure nfunctions is initialized even if there are no
> functions registered.
Ok, I get what you're saying, though nfunctions will always be initialised due
to allocation with devm_kzalloc.
> Anyway, small issues, this just doesn't belong to this patch, but it's likely
> not
> to cause any harm I guess.
True... should I leave this patch as is or respin again?
Thanks
Phil
> > Reported-by: Dan Carpenter
> > Signed-off-by: Phil Edworthy
> > ---
> > v2:
> > - Don't use implicit type conversion.
> > - Fix type of return var when calling of_get_child_count().
> > ---
> > drivers/pinctrl/pinctrl-rzn1.c | 10 +-
> > 1 file changed, 5 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/pinctrl/pinctrl-rzn1.c
> > b/drivers/pinctrl/pinctrl-rzn1.c index ce05e3a00be2..4998463c54a0
> > 100644
> > --- a/drivers/pinctrl/pinctrl-rzn1.c
> > +++ b/drivers/pinctrl/pinctrl-rzn1.c
> > @@ -112,13 +112,13 @@ struct rzn1_pinctrl {
> > struct rzn1_pinctrl_regs __iomem *lev2;
> > u32 lev1_protect_phys;
> > u32 lev2_protect_phys;
> > - u32 mdio_func[2];
> > + int mdio_func[2];
> >
> > struct rzn1_pin_group *groups;
> > unsigned int ngroups;
> >
> > struct rzn1_pmx_func *functions;
> > - unsigned int nfunctions;
> > + int nfunctions;
> > };
> >
> > #define RZN1_PINS_PROP "pinmux"
> > @@ -195,9 +195,9 @@ static void rzn1_hw_set_lock(struct rzn1_pinctrl
> > *ipctl, u8 lock, u8 value) static void rzn1_pinctrl_mdio_select(struct
> rzn1_pinctrl *ipctl, int mdio,
> > u32 func)
> > {
> > - if (ipctl->mdio_func[mdio] >= 0 && ipctl->mdio_func[mdio] != func)
> > + if (ipctl->mdio_func[mdio] >= 0 && ipctl->mdio_func[mdio] !=
> > +(int)func)
> > dev_warn(ipctl->dev, "conflicting setting for mdio%d!\n",
> mdio);
> > - ipctl->mdio_func[mdio] = func;
> > + ipctl->mdio_func[mdio] = (int)func;
> >
> > dev_dbg(ipctl->dev, "setting mdio%d to %u\n", mdio, func);
> >
> > @@ -810,8 +810,8 @@ static int rzn1_pinctrl_probe_dt(struct
> platform_device *pdev,
> > struct device_node *np = pdev->dev.of_node;
> > struct device_node *child;
> > unsigned int maxgroups = 0;
> > - unsigned int nfuncs = 0;
> > unsigned int i = 0;
> > + int nfuncs = 0;
> > int ret;
> >
> > nfuncs = of_get_child_count(np);
> > --
> > 2.17.1
> >
Re: [PATCH v2 0/3] mmc: tmio: Fix reset operation
Hi Niklas,
On Tue, Oct 16, 2018 at 3:39 AM Niklas Söderlund
wrote:
> From: Niklas Söderlund
> While looking at the Renesas BSP kernel I found patches which improves
> the state of the hardware at probe and after runtime resume.
>
> Patch 1/3 make sure the module clock is enabled after resuming before
> register are accessed. Patch 2/3 is the real change in this series and
> brings in reset of the vendor specific callback when resetting (SCC in
> the Renesas case). While 3/3 simply make sure that the IRQ mask for
> Renesas boards (Gen2 and later) are in a good shape after probe (and
> reset).
>
> In addition to addressing the state after resuming it helped unbreak a
> SD card I have which are very problematic on Koelsch. Without this
> series inserting the card results in:
>
> sh_mobile_sdhi ee10.sd: timeout waiting for hardware interrupt (CMD19)
> sh_mobile_sdhi ee10.sd: timeout waiting for hardware interrupt (CMD19)
> sh_mobile_sdhi ee10.sd: timeout waiting for hardware interrupt (CMD19)
> sh_mobile_sdhi ee10.sd: timeout waiting for hardware interrupt (CMD19)
> sh_mobile_sdhi ee10.sd: timeout waiting for hardware interrupt (CMD19)
> sh_mobile_sdhi ee10.sd: timeout waiting for hardware interrupt (CMD19)
> sh_mobile_sdhi ee10.sd: timeout waiting for hardware interrupt (CMD19)
> sh_mobile_sdhi ee10.sd: timeout waiting for hardware interrupt (CMD19)
> sh_mobile_sdhi ee10.sd: timeout waiting for hardware interrupt (CMD19)
> sh_mobile_sdhi ee10.sd: timeout waiting for hardware interrupt (CMD19)
> sh_mobile_sdhi ee10.sd: Tuning procedure failed
> mmc0: tuning execution failed: -5
> mmc0: error -5 whilst initialising SD card
> sh_mobile_sdhi ee10.sd: timeout waiting for hardware interrupt (CMD19)
>
> While with this series applied (patch 2/3):
>
> sh_mobile_sdhi ee10.sd: timeout waiting for hardware interrupt (CMD19)
> mmc0: new ultra high speed SDR50 SDHC card at address
> mmcblk0: mmc0: SU04G 3.69 GiB
> mmcblk0: p1 p2
Nice!
Can you please check if this fixes the similar issue on Magnus' ALT?
My (old, latest is v4.15) logs show the same timeout, but with errors
84 (EILSEQ)
or 110 (ETIMEDOUT) instead of 5 (EIO).
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
[PATCH v2] arm64: dts: renesas: add/enable USB2.0 peripheral for R-Car [DE]3
This patch adds/enables USB2.0 peripheral for R-Car [DE]3 boards.
So, the default mode on each board is:
- R-Car D3 Draak board (has a type-A connector) = host.
- R-Car E3 Ebisu board (has a type-B micro connector) = peripheral.
Signed-off-by: Yoshihiro Shimoda
---
Changed from v1:
- Revise the reg size for each hsusb node.
arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 8 +
arch/arm64/boot/dts/renesas/r8a77990.dtsi | 45 ++
arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 8 +
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 45 ++
4 files changed, 106 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
index f342dd8..f85655d 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
@@ -188,6 +188,7 @@
};
{
+ dr_mode = "peripheral";
status = "okay";
};
@@ -195,6 +196,11 @@
clock-frequency = <4800>;
};
+ {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
{
status = "okay";
@@ -295,6 +301,7 @@
};
{
+ dr_mode = "peripheral";
status = "okay";
};
@@ -359,6 +366,7 @@
pinctrl-0 = <_pins>;
pinctrl-names = "default";
+ renesas,no-otg-pins;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 6d5efeb..4bafc38 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -357,6 +357,51 @@
resets = < 407>;
};
+ hsusb: usb@e659 {
+ compatible = "renesas,usbhs-r8a77990",
+"renesas,rcar-gen3-usbhs";
+ reg = <0 0xe659 0 0x200>;
+ interrupts = ;
+ clocks = < CPG_MOD 704>, < CPG_MOD 703>;
+ dmas = <_dmac0 0>, <_dmac0 1>,
+ <_dmac1 0>, <_dmac1 1>;
+ dma-names = "ch0", "ch1", "ch2", "ch3";
+ renesas,buswait = <11>;
+ phys = <_phy0>;
+ phy-names = "usb";
+ power-domains = < R8A77990_PD_ALWAYS_ON>;
+ resets = < 704>, < 703>;
+ status = "disabled";
+ };
+
+ usb_dmac0: dma-controller@e65a {
+ compatible = "renesas,r8a77990-usb-dmac",
+"renesas,usb-dmac";
+ reg = <0 0xe65a 0 0x100>;
+ interrupts = ;
+ interrupt-names = "ch0", "ch1";
+ clocks = < CPG_MOD 330>;
+ power-domains = < R8A77990_PD_ALWAYS_ON>;
+ resets = < 330>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
+ usb_dmac1: dma-controller@e65b {
+ compatible = "renesas,r8a77990-usb-dmac",
+"renesas,usb-dmac";
+ reg = <0 0xe65b 0 0x100>;
+ interrupts = ;
+ interrupt-names = "ch0", "ch1";
+ clocks = < CPG_MOD 331>;
+ power-domains = < R8A77990_PD_ALWAYS_ON>;
+ resets = < 331>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
dmac0: dma-controller@e670 {
compatible = "renesas,dmac-r8a77990",
"renesas,rcar-dmac";
diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
index 2405eaa..48bb1d7 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
@@ -179,6 +179,7 @@
};
{
+ dr_mode = "host";
status = "okay";
};
@@ -186,6 +187,11 @@
clock-frequency = <4800>;
};
+ {
+ dr_mode = "host";
+ status = "okay";
+};
+
{
pinctrl-0 = <_pins>;
pinctrl-names = "default";
@@ -337,6 +343,7 @@
};
{
+ dr_mode = "host";
status = "okay";
};
@@ -445,6 +452,7 @@
pinctrl-0 = <_pins>;
pinctrl-names = "default";
+ renesas,no-otg-pins;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index 214f495..8530d9f 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -344,6 +344,51 @@
status = "disabled";
};
+ hsusb: usb@e659 {
+ compatible =
[PATCH] arm64: dts: renesas: revise hsusb's reg size
This patch revises the reg size of each hsusb device node for
r8a7795, r8a7796 and r8a77965.
Reported-by: Biju Das
Fixes: d2422e108812 ("arm64: dts: r8a7795: Add HSUSB device node")
Fixes: 4725f2b88057 ("arm64: dts: renesas: r8a7795: add hsusb ch3 device node")
Fixes: b9535853777f ("arm64: dts: r8a7796: Add HSUSB device node")
Fixes: 9e1b00a2ef43 ("arm64: dts: renesas: r8a77965: Add "reg" properties")
Signed-off-by: Yoshihiro Shimoda
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 4 ++--
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 2 +-
arch/arm64/boot/dts/renesas/r8a77965.dtsi | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 5f6020e..0b54c53 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -695,7 +695,7 @@
hsusb: usb@e659 {
compatible = "renesas,usbhs-r8a7795",
"renesas,rcar-gen3-usbhs";
- reg = <0 0xe659 0 0x100>;
+ reg = <0 0xe659 0 0x200>;
interrupts = ;
clocks = < CPG_MOD 704>, < CPG_MOD 703>;
dmas = <_dmac0 0>, <_dmac0 1>,
@@ -712,7 +712,7 @@
hsusb3: usb@e659c000 {
compatible = "renesas,usbhs-r8a7795",
"renesas,rcar-gen3-usbhs";
- reg = <0 0xe659c000 0 0x100>;
+ reg = <0 0xe659c000 0 0x200>;
interrupts = ;
clocks = < CPG_MOD 705>, < CPG_MOD 700>;
dmas = <_dmac2 0>, <_dmac2 1>,
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 1ec6aaa..3baee26 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -674,7 +674,7 @@
hsusb: usb@e659 {
compatible = "renesas,usbhs-r8a7796",
"renesas,rcar-gen3-usbhs";
- reg = <0 0xe659 0 0x100>;
+ reg = <0 0xe659 0 0x200>;
interrupts = ;
clocks = < CPG_MOD 704>, < CPG_MOD 703>;
dmas = <_dmac0 0>, <_dmac0 1>,
diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 83946ca..f12be5b 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -590,7 +590,7 @@
hsusb: usb@e659 {
compatible = "renesas,usbhs-r8a77965",
"renesas,rcar-gen3-usbhs";
- reg = <0 0xe659 0 0x100>;
+ reg = <0 0xe659 0 0x200>;
interrupts = ;
clocks = < CPG_MOD 704>, < CPG_MOD 703>;
dmas = <_dmac0 0>, <_dmac0 1>,
--
1.9.1
