Re: [PATCH] thermal: rcar_gen3_thermal: Add supports the hwmon thermal sysfs
Dear Geert-san, Wolfram-san
I'm sorry for the delay at the comments of this patch.
And I think it's not hurry!
+ /* Enable hwmon thermal sysfs */
+ tsc->zone->tzp->no_hwmon = false;
+ ret = thermal_add_hwmon_sysfs(tsc->zone);
+ if (ret)
+ dev_err(dev, "Can't register hwmon sysfs\n");
+
dev_info(dev, "TSC%d: Loaded %d trip points\n", i, ret);
}
You forgot to call thermal_remove_hwmon_sysfs() in the .remove()
callback?
I got it, Thanks!
On 2018/11/13 20:57, Wolfram Sang wrote:
Hi Hoan,
+ /* Enable hwmon thermal sysfs */
+ tsc->zone->tzp->no_hwmon = false;
A driver diving so deep into core structures always looks suspicious.
Questions I have:
1)
We have that code also in rcar_thermal.c, but the commit introducing
it[1] has a reason which does not apply for this driver, or?
This is not the reason to apply this patch.
I would say here are the general Linux systems, or as if the systems
that thermal was registered by "thermal_zone_device_register()".
The Linux community has developed tools that use this, such as
"lm-sensors",
my Ubuntu and rcar-Gen2 are still compatible with lm-sensors but Gen3
does not.
Although I do not want to say paradoxical that the kernel drivers must
be compatible
with the user-space applications.
2)
of_parse_thermal_zones() intentionally sets this flag with this
comment:
/* No hwmon because there might be hwmon drivers registering */
Why does it not apply for us?
I think so it should be registered separately.
3)
If it turns out, we really need it, there should be some thermal core
helper or flag for it, I'd think...
Yes, It up to you!
Regards,
Wolfram
[1] 64a411e8042e ("thermal: rcar-thermal: enable hwmon when
thermal_zone_of_sensor_register is used")
Thank you very much for your comments :-)!
Hoan.
[PATCH] thermal: rcar_gen3_thermal: Add supports the hwmon thermal sysfs
From: Hoan Nguyen An Gen3 thermal registered by devm_thermal_zone_of_sensor_register() and this function does not enable hwmon sysfs extensions. This patch enables it to keep compatibility to common systems Signed-off-by: Hoan Nguyen An --- drivers/thermal/rcar_gen3_thermal.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/thermal/rcar_gen3_thermal.c b/drivers/thermal/rcar_gen3_thermal.c index 75786cc..ae172db 100644 --- a/drivers/thermal/rcar_gen3_thermal.c +++ b/drivers/thermal/rcar_gen3_thermal.c @@ -19,6 +19,7 @@ #include #include "thermal_core.h" +#include "thermal_hwmon.h" /* Register offsets */ #define REG_GEN3_IRQSTR0x04 @@ -429,6 +430,12 @@ static int rcar_gen3_thermal_probe(struct platform_device *pdev) if (ret < 0) goto error_unregister; + /* Enable hwmon thermal sysfs */ + tsc->zone->tzp->no_hwmon = false; + ret = thermal_add_hwmon_sysfs(tsc->zone); + if (ret) + dev_err(dev, "Can't register hwmon sysfs\n"); + dev_info(dev, "TSC%d: Loaded %d trip points\n", i, ret); } -- 2.7.4
[v2 PATCH] thermal: rcar_gen3_thermal: Add Standby/Reset Mode support
From: Hoan Nguyen An
According to the hardware manual, Gen3 supports Standby/Reset mode.
Add this function, and we should use this function while suspend
to reduce the energy consumption.
Signed-off-by: Hoan Nguyen An
---
drivers/thermal/rcar_gen3_thermal.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/thermal/rcar_gen3_thermal.c
b/drivers/thermal/rcar_gen3_thermal.c
index 7aed533..e654519 100644
--- a/drivers/thermal/rcar_gen3_thermal.c
+++ b/drivers/thermal/rcar_gen3_thermal.c
@@ -447,11 +447,32 @@ static int rcar_gen3_thermal_probe(struct platform_device
*pdev)
return ret;
}
+static int rcar_gen3_thermal_reset(struct rcar_gen3_thermal_priv* priv)
+{
+ unsigned int i;
+ u32 reg_val;
+
+ for (i = 0; i < priv->num_tscs; i++) {
+ struct rcar_gen3_thermal_tsc *tsc = priv->tscs[i];
+
+ rcar_gen3_thermal_write(tsc, REG_GEN3_IRQEN, 0);
+ rcar_gen3_thermal_write(tsc, REG_GEN3_IRQMSK, 0);
+
+ reg_val = rcar_gen3_thermal_read(tsc, REG_GEN3_THCTR);
+ rcar_gen3_thermal_write(tsc, REG_GEN3_THCTR, reg_val &
~THCTR_THSST);
+ }
+
+ usleep_range(1000, 2000);
+
+ return 0;
+}
+
static int __maybe_unused rcar_gen3_thermal_suspend(struct device *dev)
{
struct rcar_gen3_thermal_priv *priv = dev_get_drvdata(dev);
- rcar_thermal_irq_set(priv, false);
+ /* Reset to enter standby mode */
+ rcar_gen3_thermal_reset(priv);
return 0;
}
--
2.7.4
Re: [v2 PATCH] thermal: rcar_gen3_thermal: Fix init value of IRQCTL register
Thank you for your review ! Hoan
Re: [PATCH] thermal: rcar_gen3_thermal: Fix does not have interrupts counting
Dear Niklas-san
On 2018/11/02 18:31, Niklas Söderlund wrote:
Hi Hoan-san,
Thanks for your patch.
On 2018-10-30 18:10:01 +0900, Nguyen An Hoan wrote:
From: Hoan Nguyen An
This patch fixes thermal interrupts that did not happen when temprature changed.
Add the function rcar_gen3_thermal_update_threshold(), this function is used to
calculate the value written to the threshold registers REG_GEN3_IRQTEMP1 and
REG_GEN3_IRQTEMP2.
Is it really a error if the IRQ don't happen and the thermal framework
use the .set_trip() callback to move the window due to the polling
instead of a IRQ due to a rapid thermal increase? I think not. I do not
like this patch but I'm not expert on thermal subsystem so I'm open to
be proven wrong :-)
I'm investigating more about this issue!
This patch is based on renesas-bsp/rcar-3.5.4.rc2 !
Signed-off-by: Hoan Nguyen An
---
drivers/thermal/rcar_gen3_thermal.c | 45 +
1 file changed, 26 insertions(+), 19 deletions(-)
diff --git a/drivers/thermal/rcar_gen3_thermal.c
b/drivers/thermal/rcar_gen3_thermal.c
index 7aed533..009c0db 100644
--- a/drivers/thermal/rcar_gen3_thermal.c
+++ b/drivers/thermal/rcar_gen3_thermal.c
@@ -185,37 +185,39 @@ static int rcar_gen3_thermal_get_temp(void *devdata, int
*temp)
static int rcar_gen3_thermal_mcelsius_to_temp(struct rcar_gen3_thermal_tsc
*tsc,
int mcelsius)
{
- int celsius, val1, val2;
+ int val1, val2;
- celsius = DIV_ROUND_CLOSEST(mcelsius, 1000);
- val1 = celsius * tsc->coef.a1 + tsc->coef.b1;
- val2 = celsius * tsc->coef.a2 + tsc->coef.b2;
+ val1 = (mcelsius * tsc->coef.a1)/1000 + tsc->coef.b1;
+ val2 = (mcelsius * tsc->coef.a2)/1000 + tsc->coef.b2;
This won't work I'm afraid as it can overflow. As the thcodes and ptat
values can be read from hardware there theoretical max size is 0xfff
according to the documentation. Those values are then used to calculate
a1, b1, a2 and b2 constants. If you can prove that no overflow can
happen I'm happy for this change as it increases accuracy. If so this
should be posted as a separate patch.
With this patch, when rcar_gen3_thermal_mcelsius_to_temp () is called,
since the mcelsius value was passed is calculated from the previous formula:
rcar_gen3_thermal_get_temp():
int mcelsius, val1, val2;
u32 reg;
/* Read register and convert to mili Celsius */
reg = rcar_gen3_thermal_read(tsc, REG_GEN3_TEMP) & CTEMP_MASK;
val1 = FIXPT_DIV(FIXPT_INT(reg) - tsc->coef.b1, tsc->coef.a1);
val2 = FIXPT_DIV(FIXPT_INT(reg) - tsc->coef.b2, tsc->coef.a2);
mcelsius = FIXPT_TO_MCELSIUS((val1 + val2) / 2);
/* Make sure we are inside specifications */
if ((mcelsius < MCELSIUS(-40)) || (mcelsius > MCELSIUS(125)))
return -EIO;
From int mcelsius values, val1, val2;
The reverse calculation I do not think will happen the overflow!
With the current situation, I am not clear about the high, low values
But with (a1, b1), (a2, b2)
tsc1->coef.a1 965 tsc1->coef.a2 953 tsc1->coef.b1 323853 tsc1->coef.b2
324268
tsc2->coef.a1 965 tsc2->coef.a2 954 tsc2->coef.b1 323213 tsc2->coef.b2
323640
tsc3->coef.a1 947 tsc3->coef.a2 932 tsc3->coef.b1 325163 tsc3->coef.b2
325680
with all tscX, aX <=1000.
If the temperature is 1000celsius = 100 mcelsius.
val1 <100 * 1000 + 323853 = 1 000 323 853 <2 147 483 647 (max int value)
(In fact the temperature of the board could not get to 1000 celsius
degrees )
Here the current constant values are used.
But at future THCODE and PLAT values are read from registers
to calculate aX, bX, I do not know whether there really will be overflow
or not.
If you use this patches without this part.
I have received incorrect interrupts with H3ES1.1.
So I need to integrate this part to ensure correctly in testing.
return INT_FIXPT((val1 + val2) / 2);
}
-static int rcar_gen3_thermal_set_trips(void *devdata, int low, int high)
+static int rcar_gen3_thermal_update_threshold(struct rcar_gen3_thermal_tsc
*tsc)
{
- struct rcar_gen3_thermal_tsc *tsc = devdata;
-
- low = clamp_val(low, -4, 12);
- high = clamp_val(high, -4, 12);
-
- rcar_gen3_thermal_write(tsc, REG_GEN3_IRQTEMP1,
- rcar_gen3_thermal_mcelsius_to_temp(tsc, low));
+ u32 ctemp;
+ int temp_code;
+ int mcelsius, val1, val2;
- rcar_gen3_thermal_write(tsc, REG_GEN3_IRQTEMP2,
- rcar_gen3_thermal_mcelsius_to_temp(tsc, high));
+ ctemp = rcar_gen3_thermal_read(tsc, REG_GEN3_TEMP) & CTEMP_MASK;
+ val1 = FIXPT_DIV(FIXPT_INT(ctemp) - tsc->coef.b1, tsc->coef.a1);
+ val2 = FIXPT_DIV(FIXPT_INT(ctemp) - tsc->coef.b2, tsc->coef.a2);
+ mcelsius = FIXPT_TO_MCELSIUS((val1 + val2) / 2);
- tsc->low
Re: [PATCH] thermal: rcar_gen3_thermal: Add Standby-Mode function support
Dear Niklas-san
Thank you for your comments!
On 2018/11/02 18:50, Niklas Söderlund wrote:
Hi Hoan,
Thanks for your work.
On 2018-11-02 16:06:10 +0900, Nguyen An Hoan wrote:
From: Hoan Nguyen An
According to the hardware manual, Gen3 supports Standby-mode.
Add this function, and we should use this function while
suspend to reduce the energy consumption.
Out of curiosity is the power saved measurable?
I apologize for not investigating yet this issue. It is considered
to reduce energy consumption that Equal to the power of the
"A/D converter for the thermal sensor".
Signed-off-by: Hoan Nguyen An
---
drivers/thermal/rcar_gen3_thermal.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/thermal/rcar_gen3_thermal.c
b/drivers/thermal/rcar_gen3_thermal.c
index 7aed533..85fc4b2 100644
--- a/drivers/thermal/rcar_gen3_thermal.c
+++ b/drivers/thermal/rcar_gen3_thermal.c
@@ -447,11 +447,32 @@ static int rcar_gen3_thermal_probe(struct platform_device
*pdev)
return ret;
}
+static int rcar_gen3_thermal_standby(struct rcar_gen3_thermal_priv* priv)
I don't want to bikeshed about the name but the datasheet confuses me as
it documents the standby and reset procedures to be exactly the same, or
am I missing something? If they are indeed one and the same I would
prefers this function to be called rcar_gen3_thermal_reset() and in
rcar_gen3_thermal_suspend() add a comment "Reset to enter standby mode"
or something similar. But it's up to you.
I also find it strange that the procedures of Stand-by and Reset
are exactly the same. Since we should not doubt the accuracy of
the document. I will update v2 according to your comments.
+{
+ unsigned int i;
+ u32 reg_val;
+
+ for (i = 0; i < TSC_MAX_NUM; i++) {
+ struct rcar_gen3_thermal_tsc *tsc = priv->tscs[i];
+
+ rcar_gen3_thermal_write(tsc, REG_GEN3_IRQEN, 0);
+ rcar_gen3_thermal_write(tsc, REG_GEN3_IRQMSK, 0);
+
+ reg_val = rcar_gen3_thermal_read(tsc, REG_GEN3_THCTR);
+ rcar_gen3_thermal_write(tsc, REG_GEN3_THCTR, reg_val &
~THCTR_THSST);
Too many new lines.
Thank, in addition this point, perhaps using 'priv->num_tscs' instead of
TSC_MAX_NUM would be more accurate!
+
+
+ usleep_range(1000, 2000);
Can't the sleep be moved outside the loop? We can reset all TSC and then
wait the required 1 ms only once while they all are reset or are they
somehow dependent on being reset in sequence?
Thank you, that's right, exactly 1ms only once,
I will put usleep () outside at v2 of this patch.
Thank you very much for the review!
Hoan.
+ }
+
+ return 0;
+}
+
static int __maybe_unused rcar_gen3_thermal_suspend(struct device *dev)
{
struct rcar_gen3_thermal_priv *priv = dev_get_drvdata(dev);
- rcar_thermal_irq_set(priv, false);
+ rcar_gen3_thermal_standby(priv);
return 0;
}
--
2.7.4
[PATCH] thermal: rcar_gen3_thermal: Add Standby-Mode function support
From: Hoan Nguyen An
According to the hardware manual, Gen3 supports Standby-mode.
Add this function, and we should use this function while
suspend to reduce the energy consumption.
Signed-off-by: Hoan Nguyen An
---
drivers/thermal/rcar_gen3_thermal.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/thermal/rcar_gen3_thermal.c
b/drivers/thermal/rcar_gen3_thermal.c
index 7aed533..85fc4b2 100644
--- a/drivers/thermal/rcar_gen3_thermal.c
+++ b/drivers/thermal/rcar_gen3_thermal.c
@@ -447,11 +447,32 @@ static int rcar_gen3_thermal_probe(struct platform_device
*pdev)
return ret;
}
+static int rcar_gen3_thermal_standby(struct rcar_gen3_thermal_priv* priv)
+{
+ unsigned int i;
+ u32 reg_val;
+
+ for (i = 0; i < TSC_MAX_NUM; i++) {
+ struct rcar_gen3_thermal_tsc *tsc = priv->tscs[i];
+
+ rcar_gen3_thermal_write(tsc, REG_GEN3_IRQEN, 0);
+ rcar_gen3_thermal_write(tsc, REG_GEN3_IRQMSK, 0);
+
+ reg_val = rcar_gen3_thermal_read(tsc, REG_GEN3_THCTR);
+ rcar_gen3_thermal_write(tsc, REG_GEN3_THCTR, reg_val &
~THCTR_THSST);
+
+
+ usleep_range(1000, 2000);
+ }
+
+ return 0;
+}
+
static int __maybe_unused rcar_gen3_thermal_suspend(struct device *dev)
{
struct rcar_gen3_thermal_priv *priv = dev_get_drvdata(dev);
- rcar_thermal_irq_set(priv, false);
+ rcar_gen3_thermal_standby(priv);
return 0;
}
--
2.7.4
[PATCH] thermal: rcar_gen3_thermal: Add Standby-mode function support
From: Hoan Nguyen An
According to the hardware manual, Gen3 supports Standby-mode,
Add this function, and we should use this function while
suspend to reduce the energy consumption.
Signed-off-by: Hoan Nguyen An
---
drivers/thermal/rcar_gen3_thermal.c | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/thermal/rcar_gen3_thermal.c
b/drivers/thermal/rcar_gen3_thermal.c
index 7aed533..7f3bd7f 100644
--- a/drivers/thermal/rcar_gen3_thermal.c
+++ b/drivers/thermal/rcar_gen3_thermal.c
@@ -447,11 +447,30 @@ static int rcar_gen3_thermal_probe(struct platform_device
*pdev)
return ret;
}
+static int rcar_gen3_thermal_standby(struct rcar_gen3_thermal_priv* priv)
+{
+ unsigned int i;
+ u32 reg_val;
+
+ for (i = 0; i < TSC_MAX_NUM; i++) {
+ struct rcar_gen3_thermal_tsc *tsc = priv->tscs[i];
+
+ rcar_gen3_thermal_write(tsc, REG_GEN3_IRQEN, 0);
+ rcar_gen3_thermal_write(tsc, REG_GEN3_IRQMSK, 0);
+
+ reg_val = rcar_gen3_thermal_read(tsc, REG_GEN3_THCTR);
+ rcar_gen3_thermal_write(tsc, REG_GEN3_THCTR, reg_val &
~THCTR_THSST);
+
+
+ usleep_range(1000, 2000);
+ }
+}
+
static int __maybe_unused rcar_gen3_thermal_suspend(struct device *dev)
{
struct rcar_gen3_thermal_priv *priv = dev_get_drvdata(dev);
- rcar_thermal_irq_set(priv, false);
+ rcar_gen3_thermal_standby(priv);
return 0;
}
--
2.7.4
[PATCH] thermal: rcar_gen3_thermal: Fix does not have interrupts counting
From: Hoan Nguyen An
This patch fixes thermal interrupts that did not happen when temprature changed.
Add the function rcar_gen3_thermal_update_threshold(), this function is used to
calculate the value written to the threshold registers REG_GEN3_IRQTEMP1 and
REG_GEN3_IRQTEMP2.
This patch is based on renesas-bsp/rcar-3.5.4.rc2 !
Signed-off-by: Hoan Nguyen An
---
drivers/thermal/rcar_gen3_thermal.c | 45 +
1 file changed, 26 insertions(+), 19 deletions(-)
diff --git a/drivers/thermal/rcar_gen3_thermal.c
b/drivers/thermal/rcar_gen3_thermal.c
index 7aed533..009c0db 100644
--- a/drivers/thermal/rcar_gen3_thermal.c
+++ b/drivers/thermal/rcar_gen3_thermal.c
@@ -185,37 +185,39 @@ static int rcar_gen3_thermal_get_temp(void *devdata, int
*temp)
static int rcar_gen3_thermal_mcelsius_to_temp(struct rcar_gen3_thermal_tsc
*tsc,
int mcelsius)
{
- int celsius, val1, val2;
+ int val1, val2;
- celsius = DIV_ROUND_CLOSEST(mcelsius, 1000);
- val1 = celsius * tsc->coef.a1 + tsc->coef.b1;
- val2 = celsius * tsc->coef.a2 + tsc->coef.b2;
+ val1 = (mcelsius * tsc->coef.a1)/1000 + tsc->coef.b1;
+ val2 = (mcelsius * tsc->coef.a2)/1000 + tsc->coef.b2;
return INT_FIXPT((val1 + val2) / 2);
}
-static int rcar_gen3_thermal_set_trips(void *devdata, int low, int high)
+static int rcar_gen3_thermal_update_threshold(struct rcar_gen3_thermal_tsc
*tsc)
{
- struct rcar_gen3_thermal_tsc *tsc = devdata;
-
- low = clamp_val(low, -4, 12);
- high = clamp_val(high, -4, 12);
-
- rcar_gen3_thermal_write(tsc, REG_GEN3_IRQTEMP1,
- rcar_gen3_thermal_mcelsius_to_temp(tsc, low));
+ u32 ctemp;
+ int temp_code;
+ int mcelsius, val1, val2;
- rcar_gen3_thermal_write(tsc, REG_GEN3_IRQTEMP2,
- rcar_gen3_thermal_mcelsius_to_temp(tsc, high));
+ ctemp = rcar_gen3_thermal_read(tsc, REG_GEN3_TEMP) & CTEMP_MASK;
+ val1 = FIXPT_DIV(FIXPT_INT(ctemp) - tsc->coef.b1, tsc->coef.a1);
+ val2 = FIXPT_DIV(FIXPT_INT(ctemp) - tsc->coef.b2, tsc->coef.a2);
+ mcelsius = FIXPT_TO_MCELSIUS((val1 + val2) / 2);
- tsc->low = low;
- tsc->high = high;
+ /* set the interrupts to exceed the temperature */
+ temp_code = rcar_gen3_thermal_mcelsius_to_temp(tsc,
+ mcelsius + MCELSIUS(1));
+ rcar_gen3_thermal_write(tsc, REG_GEN3_IRQTEMP1, temp_code);
+ /* set the interrupts to fall below the temperature */
+ temp_code = rcar_gen3_thermal_mcelsius_to_temp(tsc,
+ mcelsius - MCELSIUS(1));
+ rcar_gen3_thermal_write(tsc, REG_GEN3_IRQTEMP2, temp_code);
return 0;
}
static const struct thermal_zone_of_device_ops rcar_gen3_tz_of_ops = {
.get_temp = rcar_gen3_thermal_get_temp,
- .set_trips = rcar_gen3_thermal_set_trips,
};
static void rcar_thermal_irq_set(struct rcar_gen3_thermal_priv *priv, bool on)
@@ -256,8 +258,11 @@ static irqreturn_t rcar_gen3_thermal_irq_thread(int irq,
void *data)
int i;
for (i = 0; i < priv->num_tscs; i++)
+ {
+ rcar_gen3_thermal_update_threshold(priv->tscs[i]);
thermal_zone_device_update(priv->tscs[i]->zone,
THERMAL_EVENT_UNSPECIFIED);
+ }
spin_lock_irqsave(>lock, flags);
rcar_thermal_irq_set(priv, true);
@@ -306,7 +311,7 @@ static void rcar_gen3_thermal_init(struct
rcar_gen3_thermal_tsc *tsc)
usleep_range(1000, 2000);
- rcar_gen3_thermal_write(tsc, REG_GEN3_IRQCTL, 0x3F);
+ rcar_gen3_thermal_write(tsc, REG_GEN3_IRQCTL, 0);
rcar_gen3_thermal_write(tsc, REG_GEN3_IRQMSK, 0);
rcar_gen3_thermal_write(tsc, REG_GEN3_IRQEN, IRQ_TEMPD1 | IRQ_TEMP2);
@@ -414,6 +419,8 @@ static int rcar_gen3_thermal_probe(struct platform_device
*pdev)
priv->thermal_init(tsc);
rcar_gen3_thermal_calc_coefs(>coef, ptat, thcode[i]);
+ rcar_gen3_thermal_update_threshold(tsc);
+
zone = devm_thermal_zone_of_sensor_register(dev, i, tsc,
_gen3_tz_of_ops);
if (IS_ERR(zone)) {
@@ -465,7 +472,7 @@ static int __maybe_unused rcar_gen3_thermal_resume(struct
device *dev)
struct rcar_gen3_thermal_tsc *tsc = priv->tscs[i];
priv->thermal_init(tsc);
- rcar_gen3_thermal_set_trips(tsc, tsc->low, tsc->high);
+ rcar_gen3_thermal_update_threshold(tsc);
}
rcar_thermal_irq_set(priv, true);
--
2.7.4
Re: [v2 PATCH] thermal: rcar_gen3_thermal: Fix init value of IRQCTL register
Dear Geert-san, Wolfram-san I am very sorry for not being re-test for this patch v1 with H3ES1.*. Although I tested with M3-N, M3W H3ES2.0 and did not test with H3ES1.1. I discarded v1 and updated v2. Thank you! Hoan. On 2018/10/25 11:13, Nguyen An Hoan wrote: From: Hoan Nguyen An Fix setting value for IRQCTL register. We are setting the last 6 bits of (IRQCTL) to be 1 (0x3f), this is only suitable for H3ES1.*, according to new Hardware manual values 1 are "setting prohibited" for Gen3! Signed-off-by: Hoan Nguyen An --- drivers/thermal/rcar_gen3_thermal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/thermal/rcar_gen3_thermal.c b/drivers/thermal/rcar_gen3_thermal.c index 7aed533..fde3fd8 100644 --- a/drivers/thermal/rcar_gen3_thermal.c +++ b/drivers/thermal/rcar_gen3_thermal.c @@ -306,7 +306,7 @@ static void rcar_gen3_thermal_init(struct rcar_gen3_thermal_tsc *tsc) usleep_range(1000, 2000); - rcar_gen3_thermal_write(tsc, REG_GEN3_IRQCTL, 0x3F); + rcar_gen3_thermal_write(tsc, REG_GEN3_IRQCTL, 0); rcar_gen3_thermal_write(tsc, REG_GEN3_IRQMSK, 0); rcar_gen3_thermal_write(tsc, REG_GEN3_IRQEN, IRQ_TEMPD1 | IRQ_TEMP2);
[v2 PATCH] thermal: rcar_gen3_thermal: Fix init value of IRQCTL register
From: Hoan Nguyen An Fix setting value for IRQCTL register. We are setting the last 6 bits of (IRQCTL) to be 1 (0x3f), this is only suitable for H3ES1.*, according to new Hardware manual values 1 are "setting prohibited" for Gen3! Signed-off-by: Hoan Nguyen An --- drivers/thermal/rcar_gen3_thermal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/thermal/rcar_gen3_thermal.c b/drivers/thermal/rcar_gen3_thermal.c index 7aed533..fde3fd8 100644 --- a/drivers/thermal/rcar_gen3_thermal.c +++ b/drivers/thermal/rcar_gen3_thermal.c @@ -306,7 +306,7 @@ static void rcar_gen3_thermal_init(struct rcar_gen3_thermal_tsc *tsc) usleep_range(1000, 2000); - rcar_gen3_thermal_write(tsc, REG_GEN3_IRQCTL, 0x3F); + rcar_gen3_thermal_write(tsc, REG_GEN3_IRQCTL, 0); rcar_gen3_thermal_write(tsc, REG_GEN3_IRQMSK, 0); rcar_gen3_thermal_write(tsc, REG_GEN3_IRQEN, IRQ_TEMPD1 | IRQ_TEMP2); -- 2.7.4
[PATCH] thermal: rcar_gen3_thermal: Fix init value of IRQCTL register
From: Hoan Nguyen An Fix setting value for IRQCTL register. We are setting the last 6 bits of (IRQCTL) to be 1 (0x3f). But according to Hardware manual, values 1 are "setting prohibited". Signed-off-by: Hoan Nguyen An --- drivers/thermal/rcar_gen3_thermal.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/rcar_gen3_thermal.c b/drivers/thermal/rcar_gen3_thermal.c index 7aed533..2b8fb1e 100644 --- a/drivers/thermal/rcar_gen3_thermal.c +++ b/drivers/thermal/rcar_gen3_thermal.c @@ -280,7 +280,7 @@ static void rcar_gen3_thermal_init_r8a7795es1(struct rcar_gen3_thermal_tsc *tsc) rcar_gen3_thermal_write(tsc, REG_GEN3_CTSR, CTSR_PONM); - rcar_gen3_thermal_write(tsc, REG_GEN3_IRQCTL, 0x3F); + rcar_gen3_thermal_write(tsc, REG_GEN3_IRQCTL, 0); rcar_gen3_thermal_write(tsc, REG_GEN3_IRQMSK, 0); rcar_gen3_thermal_write(tsc, REG_GEN3_IRQEN, IRQ_TEMPD1 | IRQ_TEMP2); @@ -306,7 +306,7 @@ static void rcar_gen3_thermal_init(struct rcar_gen3_thermal_tsc *tsc) usleep_range(1000, 2000); - rcar_gen3_thermal_write(tsc, REG_GEN3_IRQCTL, 0x3F); + rcar_gen3_thermal_write(tsc, REG_GEN3_IRQCTL, 0); rcar_gen3_thermal_write(tsc, REG_GEN3_IRQMSK, 0); rcar_gen3_thermal_write(tsc, REG_GEN3_IRQEN, IRQ_TEMPD1 | IRQ_TEMP2); -- 2.7.4
Re: [PATCH] drm: rcar-du: Re-update the DSYSR register value for start/stop
Dear Laurent-san Thank you for your reply and comments! On 2018/10/22 20:23, Laurent Pinchart wrote: Hello Hoan, Thank you for the patch. On Monday, 22 October 2018 09:30:54 EEST Nguyen An Hoan wrote: From: Hoan Nguyen An From previous commit 0521ccb "drm: rcar-du: Cache DSYSR value to ensure known initial value" What exact commit are you referring to ? The mainline commit that has this subject is 9144adc5e5a99577bce0d4ee2ca3615f53b9d296. Seems I have cited the wrong Commit-ID、it is 9144adc5e5a99577bce0d4ee2ca3615f53b9d296 drm: rcar-du: Cache DSYSR value to ensure known initial value We only need to update DSYSR0, DSYSR2 for start/stop. So using rgrp-> mmio_offset is enough, the change back from rcar_du_crtc -> rcar_du_group -> rcar_du_crtc leading to mmio addresses for DSYSR may be different. Is this fixing an actual problem ? If you look at the code, the line struct rcar_du_crtc *rcrtc = >dev->crtcs[rgrp->index * 2]; makes sure that we select DU0 or DU2 only, so the register write rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_DRES | DSYSR_DEN, start ? DSYSR_DEN : DSYSR_DRES); should only access DSYSR0 and DSYSR2. This seems I think to fix the rcar-du problem with M3N-r8a77965, With M3N-R8a77965 we have DU0, DU1, DU3 So, when Laurent-san divide objetcs into rcar_du_group, rcar_du_crtc. DU0, DU1 -> du_group[0] rgrp-> mmio_offset = DU0_REG_OFFSET DU3->du_group[1] and rgrp-> mmio_offset = DU2_REG_OFFSET, but rcrtc->mmio_offset=DU3_REG_OFFSET (with M3N) M3N-R8a77965 not have DU2, So after the command: struct rcar_du_crtc *rcrtc = >dev->crtcs[rgrp->index * 2]; So in fact, with M3N we are updating DSYSR3 (In this my TC, this reference to start/stop DU3-RGB) This will not affect H3, since the H3 lines always have enough DU0, DU1,DU2,DU3. Thank you very much ! Hoan.
Re: [PATCH] drm: rcar-du: Re-update the DSYSR register value for start/stop
Dear Sergei Shtylyov-san
On 2018/10/22 17:21, Sergei Shtylyov wrote:
Hello!
On 22.10.2018 9:30, Nguyen An Hoan wrote:
From: Hoan Nguyen An
From previous commit 0521ccb "drm: rcar-du: Cache DSYSR value to
ensure known initial value"
When you cite an commit, at least 12 digits of SHA1 are needed, and
the summary needs to enclosed in (""), no just "".
We only need to update DSYSR0, DSYSR2 for start/stop. So using rgrp->
mmio_offset is enough,
the change back from rcar_du_crtc -> rcar_du_group -> rcar_du_crtc
leading to
mmio addresses for DSYSR may be different.
Signed-off-by: Hoan Nguyen An
---
drivers/gpu/drm/rcar-du/rcar_du_group.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c
b/drivers/gpu/drm/rcar-du/rcar_du_group.c
index d85f0a1..a5f7eed 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_group.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c
@@ -202,10 +202,9 @@ void rcar_du_group_put(struct rcar_du_group *rgrp)
static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp,
bool start)
{
- struct rcar_du_crtc *rcrtc = >dev->crtcs[rgrp->index * 2];
-
- rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_DRES | DSYSR_DEN,
- start ? DSYSR_DEN : DSYSR_DRES);
The continuation line indentation style used above is different
from yours below.
would be preferable to keep the existing style...
Thank you for the comments, and the notes to me about code rules.
I note and improve for the next time, thank you!
Hoan.
+ rcar_du_group_write(rgrp, DSYSR,
+ (rcar_du_group_read(rgrp, DSYSR) & ~(DSYSR_DRES |
DSYSR_DEN)) |
+ (start ? DSYSR_DEN : DSYSR_DRES));
}
void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
MBR, Sergei
[PATCH] drm: rcar-du: Re-update the DSYSR register value for start/stop
From: Hoan Nguyen An
>From previous commit 0521ccb "drm: rcar-du: Cache DSYSR value to ensure known
>initial value"
We only need to update DSYSR0, DSYSR2 for start/stop. So using rgrp->
mmio_offset is enough,
the change back from rcar_du_crtc -> rcar_du_group -> rcar_du_crtc leading to
mmio addresses for DSYSR may be different.
Signed-off-by: Hoan Nguyen An
---
drivers/gpu/drm/rcar-du/rcar_du_group.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c
b/drivers/gpu/drm/rcar-du/rcar_du_group.c
index d85f0a1..a5f7eed 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_group.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c
@@ -202,10 +202,9 @@ void rcar_du_group_put(struct rcar_du_group *rgrp)
static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
{
- struct rcar_du_crtc *rcrtc = >dev->crtcs[rgrp->index * 2];
-
- rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_DRES | DSYSR_DEN,
- start ? DSYSR_DEN : DSYSR_DRES);
+ rcar_du_group_write(rgrp, DSYSR,
+ (rcar_du_group_read(rgrp, DSYSR) & ~(DSYSR_DRES |
DSYSR_DEN)) |
+ (start ? DSYSR_DEN : DSYSR_DRES));
}
void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
--
2.7.4
[PATCH] drm: rcar-du: fix probe error when DRM_RCAR_DW_HDMI disabled
From: Hoan Nguyen An
Skip return EPROBE_DEFER when DRM_RCAR_DW_HDMI is disabled in case HDMI
initialize.
At this time, the rcar-du driver not be able to successfully initialize
if disable DRM_RCAR_DW_HDMI (rcar_du_probe return error),
so can not use other features such as RGB Analog, this patch to fix.
Signed-off-by: Hoan Nguyen An
---
drivers/gpu/drm/rcar-du/rcar_du_encoder.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
index f9c933d..4dbc508 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
@@ -66,8 +66,15 @@ int rcar_du_encoder_init(struct rcar_du_device *rcdu,
/* Locate the DRM bridge from the encoder DT node. */
bridge = of_drm_find_bridge(enc_node);
if (!bridge) {
+#if IS_ENABLED(CONFIG_DRM_RCAR_DW_HDMI)
ret = -EPROBE_DEFER;
goto done;
+#else
+ if (output == RCAR_DU_OUTPUT_HDMI0 ||
+ output == RCAR_DU_OUTPUT_HDMI1)
+ ret = 0;
+ goto done;
+#endif
}
ret = drm_encoder_init(rcdu->ddev, encoder, _funcs,
--
2.7.4
[PATCH] drm: rcar-du: fix probe error when DRM_RCAR_DW_HDMI disabled
From: Hoan Nguyen An Skip return EPROBE_DEFER when DRM_RCAR_DW_HDMI is disabled in case HDMI initialize. At this time, the rcar-du driver not be able to successfully initialize if disable DRM_RCAR_DW_HDMI (rcar_du_probe return error), so can not use other features such as RGB Analog, this patch to fix. Hoan Nguyen An (1): drm: rcar-du: fix probe error when DRM_RCAR_DW_HDMI disabled drivers/gpu/drm/rcar-du/rcar_du_encoder.c | 7 +++ 1 file changed, 7 insertions(+) -- 2.7.4
Re: arm64: dts: salvator-common: Add PWM-2 channel
Dear Geert-san, Thank you very much for your comments!
CC: Simon-san
> Hi Hoan,
>
> On Wed, Aug 29, 2018 at 11:33 AM Nguyen An Hoan wrote:
> > From: Hoan Nguyen An
> >
> > Add PWM-2 channel(CN28 - pin30) support for Salvator-X
>
> Thanks for your patch!
>
> Please explain why this is useful. Usually we do not enable random
> functionality
> on expansion connectors.
> In this case, this even has an (undocumented) impact on on-board devices,
> as the signal is also connected to the BD9571MWV PMIC.
> (Perhaps that was the actual intention of this patch? ;-) If yes,
> please explain)
> Thanks!
> Gr{oetje,eeting}s,
> Geert
>
On this issue, with H3/M3 SoC there are 7 PWM channels but only 2 channels are
supported: PWM1, PWM2.
While PWM1 is connected to CN19 for LVDS service. So only remaining PWM2,
I think simple, if you want to generate a signal with variable frequency and
pulse width using M3/H3 (I used for testting Addition Tasks)
then forced to use PWM2. Although I'm not sure the H3/M3 boards are not
purposeful to use the PWM functions.
Thanks you!
Hoan
Re: arm64: dts: salvator-common: Add PWM-2 channel
Dear Geert-san, Thank you very much for your comments!
CC: Simon-san
> Hi Hoan,
>
> On Wed, Aug 29, 2018 at 11:33 AM Nguyen An Hoan wrote:
> > From: Hoan Nguyen An
> >
> > Add PWM-2 channel(CN28 - pin30) support for Salvator-X
>
> Thanks for your patch!
>
> Please explain why this is useful. Usually we do not enable random
> functionality
> on expansion connectors.
> In this case, this even has an (undocumented) impact on on-board devices,
> as the signal is also connected to the BD9571MWV PMIC.
> (Perhaps that was the actual intention of this patch? ;-) If yes,
> please explain)
> Thanks!
> Gr{oetje,eeting}s,
> Geert
>
On this issue, with H3/M3 SoC there are 7 PWM channels but only 2 channels are
supported: PWM1, PWM2. While PWM1 is connected to CN19 for LVDS service. So
only remaining PWM2, I think simple, if you want to generate a signal with
variable frequency and pulse width using M3/H3 (I used for testting Addition
Tasks) then forced to use PWM2. Although I'm not sure the H3/M3 boards are not
purposeful to use the PWM functions.
Thanks you!
Hoan
[PATCH 4/4] clk: renesas: r8a77995: Add ZA2 clock
From: Hoan Nguyen An
Add ZA2 clock support for the R8A77995 SoC
Signed-off-by: Hoan Nguyen An
---
drivers/clk/renesas/r8a77995-cpg-mssr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c
b/drivers/clk/renesas/r8a77995-cpg-mssr.c
index 49e6a0d..bc15daa 100644
--- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
@@ -80,6 +80,7 @@ static const struct cpg_core_clk r8a77995_core_clks[]
__initconst = {
/* Core Clock Outputs */
DEF_FIXED("z2",R8A77995_CLK_Z2,CLK_PLL0D3, 1, 1),
+ DEF_FIXED("za2", R8A77995_CLK_ZA2, CLK_PLL0D3,10, 2),
DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
DEF_FIXED("zt",R8A77995_CLK_ZT,CLK_PLL1, 4, 1),
DEF_FIXED("zx",R8A77995_CLK_ZX,CLK_PLL1, 3, 1),
--
2.7.4
[PATCH 3/4] arm64: dts: r8a77995-draak: Enable Audio
From: Hoan Nguyen An
This patch enables Audio support for the D3 Draak board on the R8A77995
Signed-off-by: Hoan Nguyen An
---
arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 123 +
1 file changed, 123 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
index a8e8f26..0f17335 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
@@ -83,6 +83,12 @@
reg = <0x0 0x4800 0x0 0x1800>;
};
+ x19_clk: x19_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ };
+
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
@@ -101,6 +107,36 @@
regulator-always-on;
};
+ audio_clkout: audio-clkout {
+ /*
+* This is same as <_sound 0>
+* but needed to avoid cs2000/rcar_sound probe dead-lock
+*/
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <11289600>;
+ };
+
+ rsnd_ak4613: sound {
+ compatible = "simple-scu-audio-card";
+
+ simple-audio-card,name = "rsnd-ak4613";
+ simple-audio-card,format = "left_j";
+ simple-audio-card,bitclock-master = <>;
+ simple-audio-card,frame-master = <>;
+
+ simple-audio-card,prefix = "ak4613";
+ simple-audio-card,routing = "ak4613 Playback", "DAI0 Playback",
+ "DAI0 Capture", "ak4613 Capture";
+ sndcpu: simple-audio-card,cpu {
+ sound-dai = <_sound>;
+ };
+
+ sndcodec: simple-audio-card,codec {
+sound-dai = <>;
+ };
+ };
+
x12_clk: x12 {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -162,6 +198,16 @@
power-source = <1800>;
};
+ sound_pins: sound {
+ groups = "ssi3_data", "ssi34_ctrl", "ssi4_data_a";
+ function = "ssi";
+ };
+
+ sound_clk_pins: sound_clk {
+ groups = "audio_clk_a", "audio_clk_b", "audio_clkout",
"audio_clkout1";
+ function = "audio_clk";
+ };
+
usb0_pins: usb0 {
groups = "usb0";
function = "usb0";
@@ -184,6 +230,33 @@
pagesize = <8>;
};
+ ak4613: codec@10 {
+ compatible = "asahi-kasei,ak4613";
+ #sound-dai-cells = <0>;
+ reg = <0x10>;
+ clocks = <_sound 3>;
+
+ asahi-kasei,in1-single-end;
+ asahi-kasei,in2-single-end;
+ asahi-kasei,out1-single-end;
+ asahi-kasei,out2-single-end;
+ asahi-kasei,out3-single-end;
+ asahi-kasei,out4-single-end;
+ asahi-kasei,out5-single-end;
+ asahi-kasei,out6-single-end;
+ };
+
+ cs2000: clk-multiplier@4f {
+ #clock-cells = <0>;
+ compatible = "cirrus,cs2000-cp";
+ reg = <0x4f>;
+ clocks = <_clkout>, <_clk>;
+ clock-names = "clk_in", "ref_clk";
+
+ assigned-clocks = <>;
+ assigned-clock-rates = <24576000>; /* 1/1 divide */
+ };
+
composite-in@20 {
compatible = "adi,adv7180cp";
reg = <0x20>;
@@ -352,6 +425,56 @@
status = "okay";
};
+_sound {
+ pinctrl-0 = <_pins _clk_pins>;
+ pinctrl-names = "default";
+
+ /* Single DAI */
+ #sound-dai-cells = <0>;
+
+ /* audio_clkout0/1/2/3 */
+ #clock-cells = <1>;
+ clock-frequency = <12288000 11289600>;
+ clkout-lr-synchronous;
+
+ status = "okay";
+
+ /* update to */
+ clocks = < CPG_MOD 1005>,
+< CPG_MOD 1005>, < CPG_MOD 1005>,
+< CPG_MOD 1005>, < CPG_MOD 1005>,
+< CPG_MOD 1005>, < CPG_MOD 1011>,
+< CPG_MOD 1012>, < CPG_MOD 1005>,
+< CPG_MOD 1005>, < CPG_MOD 1005>,
+< CPG_MOD 1017>, < CPG_MOD 1
[PATCH 2/4] arm64: dts: r8a77995: Add Audio device nodes
From: Hoan Nguyen An
This patch adds Audio device nodes for the R8A77995
Signed-off-by: Hoan Nguyen An
---
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 183 ++
1 file changed, 183 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index 42d8dff..b96fc30 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -50,6 +50,23 @@
clock-frequency = <0>;
};
+ /*
+* The external audio clocks are configured as 0 Hz fixed frequency
+* clocks by default.
+* Boards that provide audio clocks should override them.
+*/
+ audio_clk_a: audio_clk_a {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_b: audio_clk_b {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts-extended = < GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
@@ -487,6 +504,172 @@
dma-channels = <16>;
};
+ rcar_sound: sound@ec50 {
+ /*
+* #sound-dai-cells is required
+*
+* Single DAI : #sound-dai-cells = <0>; <_sound>;
+* Multi DAI : #sound-dai-cells = <1>; <_sound N>;
+*/
+ /*
+* #clock-cells is required for audio_clkout0/1/2/3
+*
+* clkout : #clock-cells = <0>; <_sound>;
+* clkout0/1/2/3: #clock-cells = <1>; <_sound N>;
+*/
+ compatible = "renesas,rcar_sound-r8a77995",
"renesas,rcar_sound-gen3";
+ reg = <0 0xec50 0 0x1000>, /* SCU */
+ <0 0xec5a 0 0x100>, /* ADG */
+ <0 0xec54 0 0x1000>, /* SSIU */
+ <0 0xec541000 0 0x280>, /* SSI */
+ <0 0xec74 0 0x200>; /* Audio DMAC peri
peri*/
+ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+ clocks = < CPG_MOD 1005>,
+< CPG_MOD 1005>, < CPG_MOD 1005>,
+< CPG_MOD 1005>, < CPG_MOD 1005>,
+< CPG_MOD 1005>, < CPG_MOD 1011>,
+< CPG_MOD 1012>, < CPG_MOD 1005>,
+< CPG_MOD 1005>, < CPG_MOD 1005>,
+< CPG_MOD 1017>, < CPG_MOD 1017>,
+< CPG_MOD 1017>, < CPG_MOD 1025>,
+< CPG_MOD 1026>, < CPG_MOD 1017>,
+< CPG_MOD 1017>, < CPG_MOD 1017>,
+< CPG_MOD 1017>, < CPG_MOD 1017>,
+< CPG_MOD 1020>, < CPG_MOD 1021>,
+< CPG_MOD 1020>, < CPG_MOD 1021>,
+< CPG_MOD 1019>, < CPG_MOD 1018>,
+<_clk_a>, <_clk_b>,
+< CPG_CORE R8A77995_CLK_ZA2>;
+
+ clock-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0",
+ "src.9", "src.8", "src.7", "src.6",
+ "src.5", "src.4", "src.3", "src.2",
+ "src.1", "src.0",
+ "mix.1", "mix.0",
+ "ctu.1", "ctu.0",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b", "clk_i";
+ power-domains = < R8A77995_PD_ALWAYS_ON>;
+ res
[PATCH 1/4] arm64: dts: r8a77995: Add Audio DMAC node
From: Hoan Nguyen An
This patch adds Audio-DMAC{0} node for the R8A77995
Signed-off-by: Hoan Nguyen An
---
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 34 +++
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index 625ba2b..42d8dff 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -453,6 +453,40 @@
<_ds1 22>, <_ds1 23>;
};
+ audma0: dma-controller@ec70 {
+ compatible = "renesas,dmac-r8a77995",
+"renesas,rcar-dmac";
+ reg = <0 0xec70 0 0x1>;
+ interrupts = ;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = < CPG_MOD 502>;
+ clock-names = "fck";
+ power-domains = < R8A77995_PD_ALWAYS_ON>;
+ resets = < 502>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ };
+
ipmmu_ds0: mmu@e674 {
compatible = "renesas,ipmmu-r8a77995";
reg = <0 0xe674 0 0x1000>;
--
2.7.4
[PATCH 0/4] Enable Audio support for the Draak D3 board on r8a77995.
From: Hoan Nguyen An These patches enable Audio support for the Draak D3 board on the r8a77995 SoC. Since Sound has a clock source for ADG from ZA2, add ZA2 clock. Thanks you for reading! Hoan Nguyen An (4): arm64: dts: r8a77995: Add Audio DMAC node arm64: dts: r8a77995: Add Audio device nodes arm64: dts: r8a77995-draak: Enable Audio clk: renesas: r8a77995: Add ZA2 clock arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 123 ++ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 217 + drivers/clk/renesas/r8a77995-cpg-mssr.c| 1 + 3 files changed, 341 insertions(+) -- 2.7.4
Re: [1/2] pinctrl: sh-pfc: r8a77965: add Audio clock pin support
Geert-san, > Thanks for the update! > > Reviewed-by: Geert Uytterhoeven > i.e. will queue in sh-pfc-for-v4.20. Thank you very much for your helps!
Re: [1/2] arm64: dts: r8a77965: add FDP1 device nodes
Laurent-san, Simon-san > You're missing a commit message. I agree that for simple patches like this > one > the subject line often contains enough information, but adding a commit > message is still a good practice that we try to enforce through the kernel. ... > Yes, can do. I understand! Thank you very much for your reviews and comments!
[PATCH] thermal: rcar: reduce inaccuracy in calculate rounding
From: Hoan Nguyen An
About the formula for temperature calculation
[reg] = [temp] * a + b <=> [temp] = ([reg] - b) / a
Using "(mcelsius * tsc-> coef.aX) / 1000" instead of
"DIV_ROUND_CLOSEST(mcelsius, 1000) * tsc-> coef.aX"
to avoid and reduce inaccuracy due to rounding the integer division.
Signed-off-by: Hoan Nguyen An
---
drivers/thermal/rcar_gen3_thermal.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/thermal/rcar_gen3_thermal.c
b/drivers/thermal/rcar_gen3_thermal.c
index 7aed533..dbb31b8 100644
--- a/drivers/thermal/rcar_gen3_thermal.c
+++ b/drivers/thermal/rcar_gen3_thermal.c
@@ -185,11 +185,10 @@ static int rcar_gen3_thermal_get_temp(void *devdata, int
*temp)
static int rcar_gen3_thermal_mcelsius_to_temp(struct rcar_gen3_thermal_tsc
*tsc,
int mcelsius)
{
- int celsius, val1, val2;
+ int val1, val2;
- celsius = DIV_ROUND_CLOSEST(mcelsius, 1000);
- val1 = celsius * tsc->coef.a1 + tsc->coef.b1;
- val2 = celsius * tsc->coef.a2 + tsc->coef.b2;
+ val1 = (mcelsius * tsc->coef.a1)/1000 + tsc->coef.b1;
+ val2 = (mcelsius * tsc->coef.a2)/1000 + tsc->coef.b2;
return INT_FIXPT((val1 + val2) / 2);
}
--
2.7.4
[PATCH] thermal: rcar: reduce inaccuracy in the calculate rounding for temperature conversion
From: Hoan Nguyen An This patch to avoid and reduce the inaccuracy in the calculation when DIV_ROUND() and then calculates the conversion, I think, should change the order: calculate the conversion and then DIV_ROUND(). Although I'm not sure there will be an error, but I have encountered problems when troubleshooting interrupts not counting up. Hoan Nguyen An (1): thermal: rcar: reduce inaccuracy in calculate rounding drivers/thermal/rcar_gen3_thermal.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) -- 2.7.4
[PATCH] arm64: dts: salvator-common: Add PWM-2 channel
From: Hoan Nguyen An
Add PWM-2 channel(CN28 - pin30) support for Salvator-X
Signed-off-by: Hoan Nguyen An
---
arch/arm64/boot/dts/renesas/salvator-common.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
index 7d3d866..1234f91 100644
--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
@@ -572,6 +572,11 @@
function = "pwm1";
};
+ pwm2_pins: pwm2 {
+ groups = "pwm2_a";
+ function = "pwm2";
+ };
+
scif1_pins: scif1 {
groups = "scif1_data_a", "scif1_ctrl";
function = "scif1";
@@ -669,6 +674,12 @@
status = "okay";
};
+ {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
_sound {
pinctrl-0 = <_pins _clk_pins>;
pinctrl-names = "default";
--
2.7.4
[PATCH] Add PWM-2 channel support for Salvator-X
From: Hoan Nguyen An Since the Salvator-X boards have 2 PWM channels, this patch adds the PWM-2 channel, I tested by measuring the output signal at CN28-pin30. Hoan Nguyen An (1): arm64: dts: salvator-common: Add PWM-2 channel arch/arm64/boot/dts/renesas/salvator-common.dtsi | 11 +++ 1 file changed, 11 insertions(+) -- 2.7.4
[PATCH 2/2] pinctrl: sh-pfc: r8a77965: add Audio SSI pin support
From: Hoan Nguyen An
Add Audio SSI pin support for r8a77965
Signed-off-by: Hoan Nguyen An
---
drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 232 ++
1 file changed, 232 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
index 46241c0..dfdd982 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
@@ -3517,6 +3517,184 @@ static const unsigned int sdhi3_ds_mux[] = {
SD3_DS_MARK,
};
+/* - SSI
*/
+static const unsigned int ssi0_data_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(6, 2),
+};
+static const unsigned int ssi0_data_mux[] = {
+ SSI_SDATA0_MARK,
+};
+static const unsigned int ssi01239_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
+};
+static const unsigned int ssi01239_ctrl_mux[] = {
+ SSI_SCK01239_MARK, SSI_WS01239_MARK,
+};
+static const unsigned int ssi1_data_a_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(6, 3),
+};
+static const unsigned int ssi1_data_a_mux[] = {
+ SSI_SDATA1_A_MARK,
+};
+static const unsigned int ssi1_data_b_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(5, 12),
+};
+static const unsigned int ssi1_data_b_mux[] = {
+ SSI_SDATA1_B_MARK,
+};
+static const unsigned int ssi1_ctrl_a_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
+};
+static const unsigned int ssi1_ctrl_a_mux[] = {
+ SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
+};
+static const unsigned int ssi1_ctrl_b_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
+};
+static const unsigned int ssi1_ctrl_b_mux[] = {
+ SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
+};
+static const unsigned int ssi2_data_a_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(6, 4),
+};
+static const unsigned int ssi2_data_a_mux[] = {
+ SSI_SDATA2_A_MARK,
+};
+static const unsigned int ssi2_data_b_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(5, 13),
+};
+static const unsigned int ssi2_data_b_mux[] = {
+ SSI_SDATA2_B_MARK,
+};
+static const unsigned int ssi2_ctrl_a_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
+};
+static const unsigned int ssi2_ctrl_a_mux[] = {
+ SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
+};
+static const unsigned int ssi2_ctrl_b_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
+};
+static const unsigned int ssi2_ctrl_b_mux[] = {
+ SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
+};
+static const unsigned int ssi3_data_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(6, 7),
+};
+static const unsigned int ssi3_data_mux[] = {
+ SSI_SDATA3_MARK,
+};
+static const unsigned int ssi349_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
+};
+static const unsigned int ssi349_ctrl_mux[] = {
+ SSI_SCK349_MARK, SSI_WS349_MARK,
+};
+static const unsigned int ssi4_data_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(6, 10),
+};
+static const unsigned int ssi4_data_mux[] = {
+ SSI_SDATA4_MARK,
+};
+static const unsigned int ssi4_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
+};
+static const unsigned int ssi4_ctrl_mux[] = {
+ SSI_SCK4_MARK, SSI_WS4_MARK,
+};
+static const unsigned int ssi5_data_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(6, 13),
+};
+static const unsigned int ssi5_data_mux[] = {
+ SSI_SDATA5_MARK,
+};
+static const unsigned int ssi5_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
+};
+static const unsigned int ssi5_ctrl_mux[] = {
+ SSI_SCK5_MARK, SSI_WS5_MARK,
+};
+static const unsigned int ssi6_data_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(6, 16),
+};
+static const unsigned int ssi6_data_mux[] = {
+ SSI_SDATA6_MARK,
+};
+static const unsigned int ssi6_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
+};
+static const unsigned int ssi6_ctrl_mux[] = {
+ SSI_SCK6_MARK, SSI_WS6_MARK,
+};
+static const unsigned int ssi7_data_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(6, 19),
+};
+static const unsigned int ssi7_data_mux[] = {
+ SSI_SDATA7_MARK,
+};
+static const unsigned int ssi78_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
+};
+static const unsigned int ssi78_ctrl_mux[] = {
+ SSI_SCK78_MARK, SSI_WS78_MARK,
+};
+static const unsigned int ssi8_data_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(6, 20),
+};
+static const unsigned int ssi8_data_mux[] = {
+ SSI_SDATA8_MARK,
+};
+static const unsigned int ssi9_data_a_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(6, 21),
+};
+static const unsigned int ssi9_data_a_mux[] = {
+ SSI_SDATA9_A_MARK,
+};
+static const unsigned int ssi9_data_b_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(5, 14
[RESEND PATCH 0/2] Add support Audio's pins for r8a77965.
From: Hoan Nguyen An Morimoto-san, Geert-san: Thank you for your comments. These are the patches that I added Signed-off-by. These patches based on the file drivers/pinctrl/sh-pfc/pfc-r8a7796.c. Although the current renesas-drives tree r8a77965.dtsi has not yet configured for the Sound-driver, but I have manually configured and tested for this. Patches were be tested. Hoan Nguyen An (2): pinctrl: sh-pfc: r8a77965: add Audio clock pin support pinctrl: sh-pfc: r8a77965: add Audio SSI pin support drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 392 ++ 1 file changed, 392 insertions(+) -- 2.7.4
[PATCH 1/2] pinctrl: sh-pfc: r8a77965: add Audio clock pin support
From: Hoan Nguyen An
Add Audio clock pin support for r8a77965
Signed-off-by: Hoan Nguyen An
---
drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 160 ++
1 file changed, 160 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
index 72ccd1a..46241c0 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
@@ -1575,6 +1575,128 @@ static const struct sh_pfc_pin pinmux_pins[] = {
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
};
+/* - AUDIO CLOCK
*/
+static const unsigned int audio_clk_a_a_pins[] = {
+ /* CLK A */
+ RCAR_GP_PIN(6, 22),
+};
+static const unsigned int audio_clk_a_a_mux[] = {
+ AUDIO_CLKA_A_MARK,
+};
+static const unsigned int audio_clk_a_b_pins[] = {
+ /* CLK A */
+ RCAR_GP_PIN(5, 4),
+};
+static const unsigned int audio_clk_a_b_mux[] = {
+ AUDIO_CLKA_B_MARK,
+};
+static const unsigned int audio_clk_a_c_pins[] = {
+ /* CLK A */
+ RCAR_GP_PIN(5, 19),
+};
+static const unsigned int audio_clk_a_c_mux[] = {
+ AUDIO_CLKA_C_MARK,
+};
+static const unsigned int audio_clk_b_a_pins[] = {
+ /* CLK B */
+ RCAR_GP_PIN(5, 12),
+};
+static const unsigned int audio_clk_b_a_mux[] = {
+ AUDIO_CLKB_A_MARK,
+};
+static const unsigned int audio_clk_b_b_pins[] = {
+ /* CLK B */
+ RCAR_GP_PIN(6, 23),
+};
+static const unsigned int audio_clk_b_b_mux[] = {
+ AUDIO_CLKB_B_MARK,
+};
+static const unsigned int audio_clk_c_a_pins[] = {
+ /* CLK C */
+ RCAR_GP_PIN(5, 21),
+};
+static const unsigned int audio_clk_c_a_mux[] = {
+ AUDIO_CLKC_A_MARK,
+};
+static const unsigned int audio_clk_c_b_pins[] = {
+ /* CLK C */
+ RCAR_GP_PIN(5, 0),
+};
+static const unsigned int audio_clk_c_b_mux[] = {
+ AUDIO_CLKC_B_MARK,
+};
+static const unsigned int audio_clkout_a_pins[] = {
+ /* CLKOUT */
+ RCAR_GP_PIN(5, 18),
+};
+static const unsigned int audio_clkout_a_mux[] = {
+ AUDIO_CLKOUT_A_MARK,
+};
+static const unsigned int audio_clkout_b_pins[] = {
+ /* CLKOUT */
+ RCAR_GP_PIN(6, 28),
+};
+static const unsigned int audio_clkout_b_mux[] = {
+ AUDIO_CLKOUT_B_MARK,
+};
+static const unsigned int audio_clkout_c_pins[] = {
+ /* CLKOUT */
+ RCAR_GP_PIN(5, 3),
+};
+static const unsigned int audio_clkout_c_mux[] = {
+ AUDIO_CLKOUT_C_MARK,
+};
+static const unsigned int audio_clkout_d_pins[] = {
+ /* CLKOUT */
+ RCAR_GP_PIN(5, 21),
+};
+static const unsigned int audio_clkout_d_mux[] = {
+ AUDIO_CLKOUT_D_MARK,
+};
+static const unsigned int audio_clkout1_a_pins[] = {
+ /* CLKOUT1 */
+ RCAR_GP_PIN(5, 15),
+};
+static const unsigned int audio_clkout1_a_mux[] = {
+ AUDIO_CLKOUT1_A_MARK,
+};
+static const unsigned int audio_clkout1_b_pins[] = {
+ /* CLKOUT1 */
+ RCAR_GP_PIN(6, 29),
+};
+static const unsigned int audio_clkout1_b_mux[] = {
+ AUDIO_CLKOUT1_B_MARK,
+};
+static const unsigned int audio_clkout2_a_pins[] = {
+ /* CLKOUT2 */
+ RCAR_GP_PIN(5, 16),
+};
+static const unsigned int audio_clkout2_a_mux[] = {
+ AUDIO_CLKOUT2_A_MARK,
+};
+static const unsigned int audio_clkout2_b_pins[] = {
+ /* CLKOUT2 */
+ RCAR_GP_PIN(6, 30),
+};
+static const unsigned int audio_clkout2_b_mux[] = {
+ AUDIO_CLKOUT2_B_MARK,
+};
+
+static const unsigned int audio_clkout3_a_pins[] = {
+ /* CLKOUT3 */
+ RCAR_GP_PIN(5, 19),
+};
+static const unsigned int audio_clkout3_a_mux[] = {
+ AUDIO_CLKOUT3_A_MARK,
+};
+static const unsigned int audio_clkout3_b_pins[] = {
+ /* CLKOUT3 */
+ RCAR_GP_PIN(6, 31),
+};
+static const unsigned int audio_clkout3_b_mux[] = {
+ AUDIO_CLKOUT3_B_MARK,
+};
+
/* - EtherAVB ---
*/
static const unsigned int avb_link_pins[] = {
/* AVB_LINK */
@@ -3426,6 +3548,23 @@ static const unsigned int usb30_mux[] = {
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(audio_clk_a_a),
+ SH_PFC_PIN_GROUP(audio_clk_a_b),
+ SH_PFC_PIN_GROUP(audio_clk_a_c),
+ SH_PFC_PIN_GROUP(audio_clk_b_a),
+ SH_PFC_PIN_GROUP(audio_clk_b_b),
+ SH_PFC_PIN_GROUP(audio_clk_c_a),
+ SH_PFC_PIN_GROUP(audio_clk_c_b),
+ SH_PFC_PIN_GROUP(audio_clkout_a),
+ SH_PFC_PIN_GROUP(audio_clkout_b),
+ SH_PFC_PIN_GROUP(audio_clkout_c),
+ SH_PFC_PIN_GROUP(audio_clkout_d),
+ SH_PFC_PIN_GROUP(audio_clkout1_a),
+ SH_PFC_PIN_GROUP(audio_clkout1_b),
+ SH_PFC_PIN_GROUP(audio_clkout2_a),
+ SH_PFC_PIN_GROUP(audio_clkout2_b),
+ SH_PFC_PIN_GROUP(audio_clkout3_a),
+ SH_PFC_PIN_GROUP(audio_clkout3_b),
SH_PFC_PIN_GROUP(avb_link),
SH_PFC_PIN_GROUP(avb_magic),
SH_PFC_PIN_GROUP
[PATCH 1/2] arm64: dts: r8a77965: add FDP1 device nodes
From: Hoan Nguyen An
Signed-off-by: Hoan Nguyen An
---
arch/arm64/boot/dts/renesas/r8a77965.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 9c4f405..bef519f 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -1578,6 +1578,16 @@
status = "disabled";
};
+ fdp1@fe94 {
+ compatible = "renesas,fdp1";
+ reg = <0 0xfe94 0 0x2400>;
+ interrupts = ;
+ clocks = < CPG_MOD 119>;
+ power-domains = < R8A77965_PD_A3VP>;
+ resets = < 119>;
+ renesas,fcp = <>;
+ };
+
fcpf0: fcp@fe95 {
compatible = "renesas,fcpf";
reg = <0 0xfe95 0 0x200>;
--
2.7.4
[PATCH 0/2] Add support fdp1 device for Salvator-XS M3-N
From: Hoan Nguyen An These patches add fdp1 device support for M3-N r8a77965 board. Please review for me, thank you! Hoan Nguyen An (2): arm64: dts: r8a77965: add FDP1 device nodes clk: renesas: r8a77965: Add FDP clock arch/arm64/boot/dts/renesas/r8a77965.dtsi | 10 ++ drivers/clk/renesas/r8a77965-cpg-mssr.c | 1 + 2 files changed, 11 insertions(+) -- 2.7.4
[PATCH 2/2] clk: renesas: r8a77965: Add FDP clock
From: Hoan Nguyen An
Signed-off-by: Hoan Nguyen An
---
drivers/clk/renesas/r8a77965-cpg-mssr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c
b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index 312f9fe..d0847dc 100644
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -112,6 +112,7 @@ static const struct cpg_core_clk r8a77965_core_clks[]
__initconst = {
};
static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
+ DEF_MOD("fdp0", 119,R8A77965_CLK_S0D1),
DEF_MOD("scif5",202,R8A77965_CLK_S3D4),
DEF_MOD("scif4",203,R8A77965_CLK_S3D4),
DEF_MOD("scif3",204,R8A77965_CLK_S3D4),
--
2.7.4
[PATCH 0/2] Add support Audio's pins for r8a77965.
From: Hoan Nguyen An These patches based on the file drivers/pinctrl/sh-pfc/pfc-r8a7796.c. Although the current renesas-drives tree r8a77965.dtsi has not yet configured for the Sound-driver, but I have manually configured and tested for this. Patches were be tested. Hoan Nguyen An (2): pinctrl: sh-pfc: r8a77965: add Audio clock pin support pinctrl: sh-pfc: r8a77965: add Audio SSI pin support drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 392 ++ 1 file changed, 392 insertions(+) -- 2.7.4
[PATCH 1/2] pinctrl: sh-pfc: r8a77965: add Audio clock pin support
From: Hoan Nguyen An
---
drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 160 ++
1 file changed, 160 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
index 72ccd1a..46241c0 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
@@ -1575,6 +1575,128 @@ static const struct sh_pfc_pin pinmux_pins[] = {
SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
};
+/* - AUDIO CLOCK
*/
+static const unsigned int audio_clk_a_a_pins[] = {
+ /* CLK A */
+ RCAR_GP_PIN(6, 22),
+};
+static const unsigned int audio_clk_a_a_mux[] = {
+ AUDIO_CLKA_A_MARK,
+};
+static const unsigned int audio_clk_a_b_pins[] = {
+ /* CLK A */
+ RCAR_GP_PIN(5, 4),
+};
+static const unsigned int audio_clk_a_b_mux[] = {
+ AUDIO_CLKA_B_MARK,
+};
+static const unsigned int audio_clk_a_c_pins[] = {
+ /* CLK A */
+ RCAR_GP_PIN(5, 19),
+};
+static const unsigned int audio_clk_a_c_mux[] = {
+ AUDIO_CLKA_C_MARK,
+};
+static const unsigned int audio_clk_b_a_pins[] = {
+ /* CLK B */
+ RCAR_GP_PIN(5, 12),
+};
+static const unsigned int audio_clk_b_a_mux[] = {
+ AUDIO_CLKB_A_MARK,
+};
+static const unsigned int audio_clk_b_b_pins[] = {
+ /* CLK B */
+ RCAR_GP_PIN(6, 23),
+};
+static const unsigned int audio_clk_b_b_mux[] = {
+ AUDIO_CLKB_B_MARK,
+};
+static const unsigned int audio_clk_c_a_pins[] = {
+ /* CLK C */
+ RCAR_GP_PIN(5, 21),
+};
+static const unsigned int audio_clk_c_a_mux[] = {
+ AUDIO_CLKC_A_MARK,
+};
+static const unsigned int audio_clk_c_b_pins[] = {
+ /* CLK C */
+ RCAR_GP_PIN(5, 0),
+};
+static const unsigned int audio_clk_c_b_mux[] = {
+ AUDIO_CLKC_B_MARK,
+};
+static const unsigned int audio_clkout_a_pins[] = {
+ /* CLKOUT */
+ RCAR_GP_PIN(5, 18),
+};
+static const unsigned int audio_clkout_a_mux[] = {
+ AUDIO_CLKOUT_A_MARK,
+};
+static const unsigned int audio_clkout_b_pins[] = {
+ /* CLKOUT */
+ RCAR_GP_PIN(6, 28),
+};
+static const unsigned int audio_clkout_b_mux[] = {
+ AUDIO_CLKOUT_B_MARK,
+};
+static const unsigned int audio_clkout_c_pins[] = {
+ /* CLKOUT */
+ RCAR_GP_PIN(5, 3),
+};
+static const unsigned int audio_clkout_c_mux[] = {
+ AUDIO_CLKOUT_C_MARK,
+};
+static const unsigned int audio_clkout_d_pins[] = {
+ /* CLKOUT */
+ RCAR_GP_PIN(5, 21),
+};
+static const unsigned int audio_clkout_d_mux[] = {
+ AUDIO_CLKOUT_D_MARK,
+};
+static const unsigned int audio_clkout1_a_pins[] = {
+ /* CLKOUT1 */
+ RCAR_GP_PIN(5, 15),
+};
+static const unsigned int audio_clkout1_a_mux[] = {
+ AUDIO_CLKOUT1_A_MARK,
+};
+static const unsigned int audio_clkout1_b_pins[] = {
+ /* CLKOUT1 */
+ RCAR_GP_PIN(6, 29),
+};
+static const unsigned int audio_clkout1_b_mux[] = {
+ AUDIO_CLKOUT1_B_MARK,
+};
+static const unsigned int audio_clkout2_a_pins[] = {
+ /* CLKOUT2 */
+ RCAR_GP_PIN(5, 16),
+};
+static const unsigned int audio_clkout2_a_mux[] = {
+ AUDIO_CLKOUT2_A_MARK,
+};
+static const unsigned int audio_clkout2_b_pins[] = {
+ /* CLKOUT2 */
+ RCAR_GP_PIN(6, 30),
+};
+static const unsigned int audio_clkout2_b_mux[] = {
+ AUDIO_CLKOUT2_B_MARK,
+};
+
+static const unsigned int audio_clkout3_a_pins[] = {
+ /* CLKOUT3 */
+ RCAR_GP_PIN(5, 19),
+};
+static const unsigned int audio_clkout3_a_mux[] = {
+ AUDIO_CLKOUT3_A_MARK,
+};
+static const unsigned int audio_clkout3_b_pins[] = {
+ /* CLKOUT3 */
+ RCAR_GP_PIN(6, 31),
+};
+static const unsigned int audio_clkout3_b_mux[] = {
+ AUDIO_CLKOUT3_B_MARK,
+};
+
/* - EtherAVB ---
*/
static const unsigned int avb_link_pins[] = {
/* AVB_LINK */
@@ -3426,6 +3548,23 @@ static const unsigned int usb30_mux[] = {
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(audio_clk_a_a),
+ SH_PFC_PIN_GROUP(audio_clk_a_b),
+ SH_PFC_PIN_GROUP(audio_clk_a_c),
+ SH_PFC_PIN_GROUP(audio_clk_b_a),
+ SH_PFC_PIN_GROUP(audio_clk_b_b),
+ SH_PFC_PIN_GROUP(audio_clk_c_a),
+ SH_PFC_PIN_GROUP(audio_clk_c_b),
+ SH_PFC_PIN_GROUP(audio_clkout_a),
+ SH_PFC_PIN_GROUP(audio_clkout_b),
+ SH_PFC_PIN_GROUP(audio_clkout_c),
+ SH_PFC_PIN_GROUP(audio_clkout_d),
+ SH_PFC_PIN_GROUP(audio_clkout1_a),
+ SH_PFC_PIN_GROUP(audio_clkout1_b),
+ SH_PFC_PIN_GROUP(audio_clkout2_a),
+ SH_PFC_PIN_GROUP(audio_clkout2_b),
+ SH_PFC_PIN_GROUP(audio_clkout3_a),
+ SH_PFC_PIN_GROUP(audio_clkout3_b),
SH_PFC_PIN_GROUP(avb_link),
SH_PFC_PIN_GROUP(avb_magic),
SH_PFC_PIN_GROUP(avb_phy_int),
@@ -3660,6 +3799,26 @@ static const struct sh_pfc_pin_group
[PATCH 2/2] pinctrl: sh-pfc: r8a77965: add Audio SSI pin support
From: Hoan Nguyen An
---
drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 232 ++
1 file changed, 232 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
index 46241c0..dfdd982 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
@@ -3517,6 +3517,184 @@ static const unsigned int sdhi3_ds_mux[] = {
SD3_DS_MARK,
};
+/* - SSI
*/
+static const unsigned int ssi0_data_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(6, 2),
+};
+static const unsigned int ssi0_data_mux[] = {
+ SSI_SDATA0_MARK,
+};
+static const unsigned int ssi01239_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
+};
+static const unsigned int ssi01239_ctrl_mux[] = {
+ SSI_SCK01239_MARK, SSI_WS01239_MARK,
+};
+static const unsigned int ssi1_data_a_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(6, 3),
+};
+static const unsigned int ssi1_data_a_mux[] = {
+ SSI_SDATA1_A_MARK,
+};
+static const unsigned int ssi1_data_b_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(5, 12),
+};
+static const unsigned int ssi1_data_b_mux[] = {
+ SSI_SDATA1_B_MARK,
+};
+static const unsigned int ssi1_ctrl_a_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
+};
+static const unsigned int ssi1_ctrl_a_mux[] = {
+ SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
+};
+static const unsigned int ssi1_ctrl_b_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
+};
+static const unsigned int ssi1_ctrl_b_mux[] = {
+ SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
+};
+static const unsigned int ssi2_data_a_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(6, 4),
+};
+static const unsigned int ssi2_data_a_mux[] = {
+ SSI_SDATA2_A_MARK,
+};
+static const unsigned int ssi2_data_b_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(5, 13),
+};
+static const unsigned int ssi2_data_b_mux[] = {
+ SSI_SDATA2_B_MARK,
+};
+static const unsigned int ssi2_ctrl_a_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
+};
+static const unsigned int ssi2_ctrl_a_mux[] = {
+ SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
+};
+static const unsigned int ssi2_ctrl_b_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
+};
+static const unsigned int ssi2_ctrl_b_mux[] = {
+ SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
+};
+static const unsigned int ssi3_data_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(6, 7),
+};
+static const unsigned int ssi3_data_mux[] = {
+ SSI_SDATA3_MARK,
+};
+static const unsigned int ssi349_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
+};
+static const unsigned int ssi349_ctrl_mux[] = {
+ SSI_SCK349_MARK, SSI_WS349_MARK,
+};
+static const unsigned int ssi4_data_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(6, 10),
+};
+static const unsigned int ssi4_data_mux[] = {
+ SSI_SDATA4_MARK,
+};
+static const unsigned int ssi4_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
+};
+static const unsigned int ssi4_ctrl_mux[] = {
+ SSI_SCK4_MARK, SSI_WS4_MARK,
+};
+static const unsigned int ssi5_data_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(6, 13),
+};
+static const unsigned int ssi5_data_mux[] = {
+ SSI_SDATA5_MARK,
+};
+static const unsigned int ssi5_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
+};
+static const unsigned int ssi5_ctrl_mux[] = {
+ SSI_SCK5_MARK, SSI_WS5_MARK,
+};
+static const unsigned int ssi6_data_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(6, 16),
+};
+static const unsigned int ssi6_data_mux[] = {
+ SSI_SDATA6_MARK,
+};
+static const unsigned int ssi6_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
+};
+static const unsigned int ssi6_ctrl_mux[] = {
+ SSI_SCK6_MARK, SSI_WS6_MARK,
+};
+static const unsigned int ssi7_data_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(6, 19),
+};
+static const unsigned int ssi7_data_mux[] = {
+ SSI_SDATA7_MARK,
+};
+static const unsigned int ssi78_ctrl_pins[] = {
+ /* SCK, WS */
+ RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
+};
+static const unsigned int ssi78_ctrl_mux[] = {
+ SSI_SCK78_MARK, SSI_WS78_MARK,
+};
+static const unsigned int ssi8_data_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(6, 20),
+};
+static const unsigned int ssi8_data_mux[] = {
+ SSI_SDATA8_MARK,
+};
+static const unsigned int ssi9_data_a_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(6, 21),
+};
+static const unsigned int ssi9_data_a_mux[] = {
+ SSI_SDATA9_A_MARK,
+};
+static const unsigned int ssi9_data_b_pins[] = {
+ /* SDATA */
+ RCAR_GP_PIN(5, 14),
+};
+static const unsigned int ssi9_data_b_mux
Re: [PATCH v6] gpio: dwapb: Add support for 1 interrupt per port A GPIO
Hi Lee, On 5/16/18, 11:25 PM, "Lee Jones" <lee.jo...@linaro.org> wrote: On Wed, 16 May 2018, Hoan Tran wrote: > Hi Phil, > > On 5/11/18, 1:31 AM, "Phil Edworthy" <phil.edwor...@renesas.com> wrote: > > The DesignWare GPIO IP can be configured for either 1 interrupt or 1 > per GPIO in port A, but the driver currently only supports 1 interrupt. > See the DesignWare DW_apb_gpio Databook description of the > 'GPIO_INTR_IO' parameter. > > This change allows the driver to work with up to 32 interrupts, it will > get as many interrupts as specified in the DT 'interrupts' property. > It doesn't do anything clever with the different interrupts, it just calls > the same handler used for single interrupt hardware. > > Signed-off-by: Phil Edworthy <phil.edwor...@renesas.com> > Reviewed-by: Rob Herring <r...@kernel.org> > Acked-by: Lee Jones <lee.jo...@linaro.org> > --- > One point to mention is that I have made it possible for users to have > unconnected interrupts by specifying holes in the list of interrupts. This is > done by supporting the interrupts-extended DT prop. > However, I have no use for this and had to hack some test case for this. > Perhaps the driver should support 1 interrupt or all GPIOa as interrupts? > > v6: > - Treat DT and ACPI the same as much as possible. Note that we can't use >platform_get_irq() to get the DT interrupts as they are in the port > sub-node and hence do not have an associated platform device. > v5: > - Rolled ACPI companion code provided by Hoan Tran into this patch. > v4: > - Use of_irq_get() instead of of_irq_parse_one()+irq_create_of_mapping() > v3: > - Rolled mfd: intel_quark_i2c_gpio fix into this patch to avoid bisect problems > v2: > - Replaced interrupt-mask DT prop with support for the interrupts-extended >prop. This means replacing the call to irq_of_parse_and_map() with calls >to of_irq_parse_one() and irq_create_of_mapping(). > --- > .../devicetree/bindings/gpio/snps-dwapb-gpio.txt | 9 +++- > drivers/gpio/gpio-dwapb.c | 49 +++--- > drivers/mfd/intel_quark_i2c_gpio.c | 3 +- > include/linux/platform_data/gpio-dwapb.h | 3 +- > 4 files changed, 45 insertions(+), 19 deletions(-) > > diff --git a/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt b/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt > index 4a75da7..3c1118b 100644 > --- a/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt > +++ b/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt > @@ -26,8 +26,13 @@ controller. >the second encodes the triger flags encoded as described in > Documentation/devicetree/bindings/interrupt-controller/interrupts.txt > - interrupt-parent : The parent interrupt controller. > -- interrupts : The interrupt to the parent controller raised when GPIOs > - generate the interrupts. > +- interrupts : The interrupts to the parent controller raised when GPIOs > + generate the interrupts. If the controller provides one combined interrupt > + for all GPIOs, specify a single interrupt. If the controller provides one > + interrupt for each GPIO, provide a list of interrupts that correspond to each > + of the GPIO pins. When specifying multiple interrupts, if any are unconnected, > + use the interrupts-extended property to specify the interrupts and set the > + interrupt controller handle for unused interrupts to 0. > - snps,nr-gpios : The number of pins in the port, a single cell. > - resets : Reset line for the controller. > > Acked-by: Hoan Tran <hoan.t...@amperecomputing.com> Well that's new. I've never seen a mailer reply like that before. Which mailer are you using? Might be worth sorting that out. Yes, it looks like my new email from outlook does not have the correct format. With my old one, it works correctly. Thanks Hoan -- Lee Jones [李琼斯] Linaro Services Technical Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog
Re: [PATCH v6] gpio: dwapb: Add support for 1 interrupt per port A GPIO
Hi Phil,
On 5/11/18, 1:31 AM, "Phil Edworthy" <phil.edwor...@renesas.com> wrote:
The DesignWare GPIO IP can be configured for either 1 interrupt or 1
per GPIO in port A, but the driver currently only supports 1 interrupt.
See the DesignWare DW_apb_gpio Databook description of the
'GPIO_INTR_IO' parameter.
This change allows the driver to work with up to 32 interrupts, it will
get as many interrupts as specified in the DT 'interrupts' property.
It doesn't do anything clever with the different interrupts, it just calls
the same handler used for single interrupt hardware.
Signed-off-by: Phil Edworthy <phil.edwor...@renesas.com>
Reviewed-by: Rob Herring <r...@kernel.org>
Acked-by: Lee Jones <lee.jo...@linaro.org>
---
One point to mention is that I have made it possible for users to have
unconnected interrupts by specifying holes in the list of interrupts. This
is
done by supporting the interrupts-extended DT prop.
However, I have no use for this and had to hack some test case for this.
Perhaps the driver should support 1 interrupt or all GPIOa as interrupts?
v6:
- Treat DT and ACPI the same as much as possible. Note that we can't use
platform_get_irq() to get the DT interrupts as they are in the port
sub-node and hence do not have an associated platform device.
v5:
- Rolled ACPI companion code provided by Hoan Tran into this patch.
v4:
- Use of_irq_get() instead of of_irq_parse_one()+irq_create_of_mapping()
v3:
- Rolled mfd: intel_quark_i2c_gpio fix into this patch to avoid bisect
problems
v2:
- Replaced interrupt-mask DT prop with support for the interrupts-extended
prop. This means replacing the call to irq_of_parse_and_map() with calls
to of_irq_parse_one() and irq_create_of_mapping().
---
.../devicetree/bindings/gpio/snps-dwapb-gpio.txt | 9 +++-
drivers/gpio/gpio-dwapb.c | 49
+++---
drivers/mfd/intel_quark_i2c_gpio.c | 3 +-
include/linux/platform_data/gpio-dwapb.h | 3 +-
4 files changed, 45 insertions(+), 19 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
b/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
index 4a75da7..3c1118b 100644
--- a/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
@@ -26,8 +26,13 @@ controller.
the second encodes the triger flags encoded as described in
Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
- interrupt-parent : The parent interrupt controller.
-- interrupts : The interrupt to the parent controller raised when GPIOs
- generate the interrupts.
+- interrupts : The interrupts to the parent controller raised when GPIOs
+ generate the interrupts. If the controller provides one combined
interrupt
+ for all GPIOs, specify a single interrupt. If the controller provides one
+ interrupt for each GPIO, provide a list of interrupts that correspond to
each
+ of the GPIO pins. When specifying multiple interrupts, if any are
unconnected,
+ use the interrupts-extended property to specify the interrupts and set
the
+ interrupt controller handle for unused interrupts to 0.
- snps,nr-gpios : The number of pins in the port, a single cell.
- resets : Reset line for the controller.
diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio-dwapb.c
index 226977f..15b4154 100644
--- a/drivers/gpio/gpio-dwapb.c
+++ b/drivers/gpio/gpio-dwapb.c
@@ -441,14 +441,19 @@ static void dwapb_configure_irqs(struct dwapb_gpio
*gpio,
irq_gc->chip_types[1].handler = handle_edge_irq;
if (!pp->irq_shared) {
- irq_set_chained_handler_and_data(pp->irq, dwapb_irq_handler,
-gpio);
+ int i;
+
+ for (i = 0; i < pp->ngpio; i++) {
+ if (pp->irq[i] >= 0)
+ irq_set_chained_handler_and_data(pp->irq[i],
+ dwapb_irq_handler, gpio);
+ }
} else {
/*
* Request a shared IRQ since where MFD would have devices
* using the same irq pin
*/
- err = devm_request_irq(gpio->dev, pp->irq,
+ err = devm_request_irq(gpio->dev, pp->irq[0],
dwapb_irq_handler_mfd,
IRQF_SHARED, "gpio-dwapb-mfd", gpio);
if (err) {
@@ -524,7 +529,7 @@ static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
if (pp->idx == 0)
Re: [PATCH v5] gpio: dwapb: Add support for 1 interrupt per port A GPIO
Hi,
On Thu, Apr 26, 2018 at 9:19 AM, Phil Edworthy
<phil.edwor...@renesas.com> wrote:
> The DesignWare GPIO IP can be configured for either 1 interrupt or 1
> per GPIO in port A, but the driver currently only supports 1 interrupt.
> See the DesignWare DW_apb_gpio Databook description of the
> 'GPIO_INTR_IO' parameter.
>
> This change allows the driver to work with up to 32 interrupts, it will
> get as many interrupts as specified in the DT 'interrupts' property.
> It doesn't do anything clever with the different interrupts, it just calls
> the same handler used for single interrupt hardware.
>
> ACPI companion code provided by Hoan Tran <hot...@apm.com>. This was tested
> on X-Gene by Hoan.
>
> Signed-off-by: Phil Edworthy <phil.edwor...@renesas.com>
> Reviewed-by: Rob Herring <r...@kernel.org>
> Acked-by: Lee Jones <lee.jo...@linaro.org>
> ---
> One point to mention is that I have made it possible for users to have
> unconncted interrupts by specifying holes in the list of interrupts. This is
> done by supporting the interrupts-extended DT prop.
> However, I have no use for this and had to hack some test case for this.
> Perhaps the driver should support 1 interrupt or all GPIOa as interrupts?
>
> v5:
> - Rolled ACPI companion code provided by Hoan Tran into this patch.
> v4:
> - Use of_irq_get() instead of of_irq_parse_one()+irq_create_of_mapping()
> v3:
> - Rolled mfd: intel_quark_i2c_gpio fix into this patch to avoid bisect
> problems
> v2:
> - Replaced interrupt-mask DT prop with support for the interrupts-extended
>prop. This means replacing the call to irq_of_parse_and_map() with calls
>to of_irq_parse_one() and irq_create_of_mapping().
>
> Note: There are a few *code* lines over 80 chars, but this is just guidance,
>right? Especially as there are already some lines over 80 chars.
> ---
> .../devicetree/bindings/gpio/snps-dwapb-gpio.txt | 9 -
> drivers/gpio/gpio-dwapb.c | 46
> +-
> drivers/mfd/intel_quark_i2c_gpio.c | 3 +-
> include/linux/platform_data/gpio-dwapb.h | 3 +-
> 4 files changed, 48 insertions(+), 13 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
> b/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
> index 4a75da7..3c1118b 100644
> --- a/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
> +++ b/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
> @@ -26,8 +26,13 @@ controller.
>the second encodes the triger flags encoded as described in
>Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
> - interrupt-parent : The parent interrupt controller.
> -- interrupts : The interrupt to the parent controller raised when GPIOs
> - generate the interrupts.
> +- interrupts : The interrupts to the parent controller raised when GPIOs
> + generate the interrupts. If the controller provides one combined interrupt
> + for all GPIOs, specify a single interrupt. If the controller provides one
> + interrupt for each GPIO, provide a list of interrupts that correspond to
> each
> + of the GPIO pins. When specifying multiple interrupts, if any are
> unconnected,
> + use the interrupts-extended property to specify the interrupts and set the
> + interrupt controller handle for unused interrupts to 0.
> - snps,nr-gpios : The number of pins in the port, a single cell.
> - resets : Reset line for the controller.
>
> diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio-dwapb.c
> index 226977f..7dcd06b 100644
> --- a/drivers/gpio/gpio-dwapb.c
> +++ b/drivers/gpio/gpio-dwapb.c
> @@ -441,14 +441,19 @@ static void dwapb_configure_irqs(struct dwapb_gpio
> *gpio,
> irq_gc->chip_types[1].handler = handle_edge_irq;
>
> if (!pp->irq_shared) {
> - irq_set_chained_handler_and_data(pp->irq, dwapb_irq_handler,
> -gpio);
> + int i;
> +
> + for (i = 0; i < pp->ngpio; i++) {
> + if (pp->irq[i])
> + irq_set_chained_handler_and_data(pp->irq[i],
> + dwapb_irq_handler, gpio);
> + }
> } else {
> /*
> * Request a shared IRQ since where MFD would have devices
> * using the same irq pin
> */
> - err = devm_request_irq(gpio->dev, pp->irq,
> + err = devm_request_irq(gpio->dev, pp->irq[0],
>dwapb_irq_handler_mfd,
>
Re: [PATCH v3] gpio: dwapb: Add support for 1 interrupt per port A GPIO
Hi Phil,
On Thu, Apr 19, 2018 at 3:03 AM, Phil Edworthy
<phil.edwor...@renesas.com> wrote:
> Hi Hoan
>
> On 18 April 2018 08:03 Hoan Tran wrote:
>> On Fri, Apr 13, 2018 at 9:47 AM, Phil Edworthy wrote:
>> > On 13 April 2018 17:37 Hoan Tran wrote:
>> >> On Fri, Apr 13, 2018 at 1:51 AM, Phil Edworthy wrote:
>> >> > The DesignWare GPIO IP can be configured for either 1 interrupt or
>> >> > 1 per GPIO in port A, but the driver currently only supports 1
>> >> > interrupt.
>> >> > See the DesignWare DW_apb_gpio Databook description of the
>> >> > 'GPIO_INTR_IO' parameter.
>> >> >
>> >> > This change allows the driver to work with up to 32 interrupts, it
>> >> > will get as many interrupts as specified in the DT 'interrupts'
>> >> > property.
>> >> > It doesn't do anything clever with the different interrupts, it
>> >> > just calls the same handler used for single interrupt hardware.
>> >> >
>> >> > Signed-off-by: Phil Edworthy <phil.edwor...@renesas.com>
>> >> > ---
>> >> > One point to mention is that I have made it possible for users to
>> >> > have unconncted interrupts by specifying holes in the list of
>> >> > interrupts.
>> >> > This is done by supporting the interrupts-extended DT prop.
>> >> > However, I have no use for this and had to hack some test case for this.
>> >> > Perhaps the driver should support 1 interrupt or all GPIOa as
>> >> > interrupts?
>> >> >
>> >> > v3:
>> >> > - Rolled mfd: intel_quark_i2c_gpio fix into this patch to avoid
>> >> > bisect problems
>> >> > v2:
>> >> > - Replaced interrupt-mask DT prop with support for the interrupts-
>> >> extended
>> >> >prop. This means replacing the call to irq_of_parse_and_map() with
>> calls
>> >> >to of_irq_parse_one() and irq_create_of_mapping().
>> >> >
>> >> > Note: There are a few *code* lines over 80 chars, but this is just
>> guidance,
>> >> >right? Especially as there are already some lines over 80 chars.
>> >> > ---
>> > [snip]
>> >
>> >> > - if (has_acpi_companion(dev) && pp->idx == 0)
>> >> > - pp->irq =
>> >> > platform_get_irq(to_platform_device(dev), 0);
>> >> > + if (has_acpi_companion(dev) && pp->idx == 0) {
>> >> > + pp->irq[0] =
>> >> > platform_get_irq(to_platform_device(dev),
>> 0);
>> >> > + if (pp->irq[0])
>> >> > + pp->has_irq = true;
>> >> > + }
>> >>
>> >> It doesn't work for ACPI. Could you do the same logic for ACPI?
>> > I don’t have access to any device that was baked (i.e. fabbed) with
>> > multiple output interrupts from the Synopsys GPIO blocks and use ACPI.
>> > I don't know if any such device exists.
>>
>> Below code is tested on X-Gene system which supports 1 interrupt per GPIO
>> on Port A. You can update it into your patch.
>>
>> - if (has_acpi_companion(dev) && pp->idx == 0)
>> - pp->irq = platform_get_irq(to_platform_device(dev),
>> 0);
>> + if (has_acpi_companion(dev) && pp->idx == 0) {
>> + unsigned int j;
>> + for (j = 0; j < pp->ngpio; j++) {
>> + pp->irq[j] =
>> platform_get_irq(to_platform_device(dev), j);
>> + if (pp->irq[j])
>> + pp->has_irq = true;
>> + }
>> + }
> Since I've already got some reviewed-by and acks for v4, I'll leave it to
> Linus
> to decide if he wants me to roll your changes into this patch or for you to
> submit a separate patch.
>
I prefer this patch works for both DTB and ACPI. Btw let Linus decide.
Thanks
Hoan
> Thanks
> Phil
>
>
>> >> > pp->irq_shared = false;
>> >> > pp->gpio_base = -1;
>> >> > diff --git a/drivers/mfd/intel_quark_i2c_gpio.c
>> >> > b/drivers/mfd/intel_quark_i2c_gpio.c
>> >> > index 90e35de..5bddb84 1006
Re: [PATCH v3] gpio: dwapb: Add support for 1 interrupt per port A GPIO
Hi Phil,
On Fri, Apr 13, 2018 at 9:47 AM, Phil Edworthy
<phil.edwor...@renesas.com> wrote:
> Hi Hoan,
>
> On 13 April 2018 17:37 Hoan Tran wrote:
>> On Fri, Apr 13, 2018 at 1:51 AM, Phil Edworthy wrote:
>> > The DesignWare GPIO IP can be configured for either 1 interrupt or 1
>> > per GPIO in port A, but the driver currently only supports 1 interrupt.
>> > See the DesignWare DW_apb_gpio Databook description of the
>> > 'GPIO_INTR_IO' parameter.
>> >
>> > This change allows the driver to work with up to 32 interrupts, it
>> > will get as many interrupts as specified in the DT 'interrupts' property.
>> > It doesn't do anything clever with the different interrupts, it just
>> > calls the same handler used for single interrupt hardware.
>> >
>> > Signed-off-by: Phil Edworthy <phil.edwor...@renesas.com>
>> > ---
>> > One point to mention is that I have made it possible for users to have
>> > unconncted interrupts by specifying holes in the list of interrupts.
>> > This is done by supporting the interrupts-extended DT prop.
>> > However, I have no use for this and had to hack some test case for this.
>> > Perhaps the driver should support 1 interrupt or all GPIOa as interrupts?
>> >
>> > v3:
>> > - Rolled mfd: intel_quark_i2c_gpio fix into this patch to avoid
>> > bisect problems
>> > v2:
>> > - Replaced interrupt-mask DT prop with support for the interrupts-
>> extended
>> >prop. This means replacing the call to irq_of_parse_and_map() with calls
>> >to of_irq_parse_one() and irq_create_of_mapping().
>> >
>> > Note: There are a few *code* lines over 80 chars, but this is just
>> > guidance,
>> >right? Especially as there are already some lines over 80 chars.
>> > ---
> [snip]
>
>> > - if (has_acpi_companion(dev) && pp->idx == 0)
>> > - pp->irq =
>> > platform_get_irq(to_platform_device(dev), 0);
>> > + if (has_acpi_companion(dev) && pp->idx == 0) {
>> > + pp->irq[0] =
>> > platform_get_irq(to_platform_device(dev), 0);
>> > + if (pp->irq[0])
>> > + pp->has_irq = true;
>> > + }
>>
>> It doesn't work for ACPI. Could you do the same logic for ACPI?
> I don’t have access to any device that was baked (i.e. fabbed) with multiple
> output interrupts from the Synopsys GPIO blocks and use ACPI. I don't
> know if any such device exists.
Below code is tested on X-Gene system which supports 1 interrupt per
GPIO on Port A. You can update it into your patch.
- if (has_acpi_companion(dev) && pp->idx == 0)
- pp->irq = platform_get_irq(to_platform_device(dev), 0);
+ if (has_acpi_companion(dev) && pp->idx == 0) {
+ unsigned int j;
+ for (j = 0; j < pp->ngpio; j++) {
+ pp->irq[j] =
platform_get_irq(to_platform_device(dev), j);
+ if (pp->irq[j])
+ pp->has_irq = true;
+ }
+ }
Thanks
Hoan
>
> I would prefer not writing code that can be tested easily. I cannot even
> test the current, albeit small, changes to the Intel Quark MFD.
>
> Regards
> Phil
>
>> Thanks
>> Hoan
>>
>> >
>> > pp->irq_shared = false;
>> > pp->gpio_base = -1;
>> > diff --git a/drivers/mfd/intel_quark_i2c_gpio.c
>> > b/drivers/mfd/intel_quark_i2c_gpio.c
>> > index 90e35de..5bddb84 100644
>> > --- a/drivers/mfd/intel_quark_i2c_gpio.c
>> > +++ b/drivers/mfd/intel_quark_i2c_gpio.c
>> > @@ -233,7 +233,8 @@ static int intel_quark_gpio_setup(struct pci_dev
>> *pdev, struct mfd_cell *cell)
>> > pdata->properties->idx = 0;
>> > pdata->properties->ngpio= INTEL_QUARK_MFD_NGPIO;
>> > pdata->properties->gpio_base= INTEL_QUARK_MFD_GPIO_BASE;
>> > - pdata->properties->irq = pdev->irq;
>> > + pdata->properties->irq[0] = pdev->irq;
>> > + pdata->properties->has_irq = true;
>> > pdata->properties->irq_shared = true;
>> >
>> > cell->platform_data = pdata;
>> > diff --git a/include/linux/platform_data/gpio-dwapb.h
>> > b/include/linux/platform_data/gpio-dwapb.h
>> > index 2dc7f4a..5a52d69 100644
>> > --- a/include/linux/platform_data/gpio-dwapb.h
>> > +++ b/include/linux/platform_data/gpio-dwapb.h
>> > @@ -19,7 +19,8 @@ struct dwapb_port_property {
>> > unsigned intidx;
>> > unsigned intngpio;
>> > unsigned intgpio_base;
>> > - unsigned intirq;
>> > + unsigned intirq[32];
>> > + boolhas_irq;
>> > boolirq_shared;
>> > };
>> >
>> > --
>> > 2.7.4
>> >
Re: [PATCH v3] gpio: dwapb: Add support for 1 interrupt per port A GPIO
irqs(gpio, port, pp);
>
> err = gpiochip_add_data(>gc, port);
> @@ -535,7 +540,7 @@ static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
> port->is_registered = true;
>
> /* Add GPIO-signaled ACPI event support */
> - if (pp->irq)
> + if (pp->has_irq)
> acpi_gpiochip_request_interrupts(>gc);
>
> return err;
> @@ -601,13 +606,33 @@ dwapb_gpio_get_pdata(struct device *dev)
> if (dev->of_node && pp->idx == 0 &&
> fwnode_property_read_bool(fwnode,
> "interrupt-controller")) {
> - pp->irq = irq_of_parse_and_map(to_of_node(fwnode), 0);
> - if (!pp->irq)
> + struct device_node *np = to_of_node(fwnode);
> + struct of_phandle_args oirq;
> + unsigned int j;
> +
> + /*
> +* The IP has configuration options to allow a single
> +* combined interrupt or one per gpio. If one per
> gpio,
> +* some might not be used.
> +*/
> + for (j = 0; j < pp->ngpio; j++) {
> + if (of_irq_parse_one(np, j, ))
> + continue;
> +
> + pp->irq[j] = irq_create_of_mapping();
> + if (pp->irq[j])
> + pp->has_irq = true;
> + }
> +
> + if (!pp->has_irq)
> dev_warn(dev, "no irq for port%d\n", pp->idx);
> }
>
> - if (has_acpi_companion(dev) && pp->idx == 0)
> - pp->irq = platform_get_irq(to_platform_device(dev),
> 0);
> + if (has_acpi_companion(dev) && pp->idx == 0) {
> + pp->irq[0] =
> platform_get_irq(to_platform_device(dev), 0);
> + if (pp->irq[0])
> + pp->has_irq = true;
> + }
It doesn't work for ACPI. Could you do the same logic for ACPI?
Thanks
Hoan
>
> pp->irq_shared = false;
> pp->gpio_base = -1;
> diff --git a/drivers/mfd/intel_quark_i2c_gpio.c
> b/drivers/mfd/intel_quark_i2c_gpio.c
> index 90e35de..5bddb84 100644
> --- a/drivers/mfd/intel_quark_i2c_gpio.c
> +++ b/drivers/mfd/intel_quark_i2c_gpio.c
> @@ -233,7 +233,8 @@ static int intel_quark_gpio_setup(struct pci_dev *pdev,
> struct mfd_cell *cell)
> pdata->properties->idx = 0;
> pdata->properties->ngpio= INTEL_QUARK_MFD_NGPIO;
> pdata->properties->gpio_base= INTEL_QUARK_MFD_GPIO_BASE;
> - pdata->properties->irq = pdev->irq;
> + pdata->properties->irq[0] = pdev->irq;
> + pdata->properties->has_irq = true;
> pdata->properties->irq_shared = true;
>
> cell->platform_data = pdata;
> diff --git a/include/linux/platform_data/gpio-dwapb.h
> b/include/linux/platform_data/gpio-dwapb.h
> index 2dc7f4a..5a52d69 100644
> --- a/include/linux/platform_data/gpio-dwapb.h
> +++ b/include/linux/platform_data/gpio-dwapb.h
> @@ -19,7 +19,8 @@ struct dwapb_port_property {
> unsigned intidx;
> unsigned intngpio;
> unsigned intgpio_base;
> - unsigned intirq;
> + unsigned intirq[32];
> + boolhas_irq;
> boolirq_shared;
> };
>
> --
> 2.7.4
>
Re: The failure summary report of GEN3 for linux upstream v4.10-rc2
Hi all, We have tested the linux v4.10-rc2 for Gen3 Salvator. So we would like to report the summary of the failure. Best Regards, Jinso/Linux Team Hoan GEN3(H3)_The failure summary report for linux upstream v4.10-rc2.xls Description: MS-Excel spreadsheet
Re: The failure summary report of GEN3 for linux stable v4.9
Dear Geert Uytterhoeven, I have retested PM, recheck the PM test procedures. I am using board H3 ES1.1, procedures involving i2cset is right. With the same test procedures and setting for this version and previous version(v4.9-rc2), but the results are different. (Only U-boot versions are different for two version) I am using U-boot version(U-Boot 2015.04 (Sep 13 2016 - 11:32:36)). I attach the test log file of PM. Please have a look at the log. On 27/12/16 22:02, Geert Uytterhoeven wrote: Hi Hoan, On Tue, Dec 27, 2016 at 11:35 AM, Hoan Nguyen An <na-h...@jinso.co.jp> wrote: My name is Hoan from Jinzai Solution. We have tested the linux stable v4.9 for Gen3 Salvator-X (H3) So we would like to report the summary of the failure. 1 PM: It is not working, can't return to the system. NG New issue root@linaro-nano:~# echo mem > /sys/power/state [ 221.280712] PM: Syncing filesystems ... done. [ 221.286474] Freezing user space processes ... (elapsed 0.001 seconds) done. [ 221.295013] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done. [ 221.303691] Suspending console(s) (use no_console_suspend to debug) Are you using R-Car H3 ES1.0? AFAIK, tbe newer firmware supports system suspend/resume on H3 ES1.1 only, and only when following the right procedure involving i2cset. I only set the following command for test. root@linaro-nano:~# echo enabled > /sys/devices/platform/soc/e6e68000.serial/tty/ttySC1/power/wakeup root@linaro-nano:~# echo enabled > /sys/devices/platform/soc/e6e88000.serial/tty/ttySC0/power/wakeup root@linaro-nano:~# echo mem > /sys/power/state Could you please tell me more details for using i2cset?. Thanks, Jinzai Solution/Linux Team, Hoan. NOTICE: BL2: R-Car Gen3 Initial Program Loader(CA57) Rev.1.0.9 NOTICE: BL2: PRR is R-Car H3 ES1.1 NOTICE: BL2: Boot device is HyperFlash(80MHz) NOTICE: BL2: LCM state is CM NOTICE: BL2: AVS setting succeeded. DVFS_SetVID=0x52 NOTICE: BL2: DDR1600(rev.0.15) NOTICE: BL2: DRAM Split is 4ch NOTICE: BL2: QoS is default setting(rev.0.32) NOTICE: BL2: v1.1(release):3ad02ac NOTICE: BL2: Built : 11:32:54, Sep 13 2016 NOTICE: BL2: Normal boot NOTICE: BL2: dst=0xe631a208 src=0x818 len=512(0x200) NOTICE: BL2: dst=0x43f0 src=0x8180400 len=6144(0x1800) NOTICE: BL2: dst=0x4400 src=0x81c len=65536(0x1) NOTICE: BL2: dst=0x4410 src=0x820 len=524288(0x8) NOTICE: BL2: dst=0x4900 src=0x864 len=1048576(0x10) U-Boot 2015.04 (Sep 13 2016 - 11:32:36) CPU: Renesas Electronics R8A7795 rev 1.1 Board: Salvator-X I2C: ready DRAM: 3.9 GiB MMC: sh-sdhi: 0, sh-sdhi: 1, sh-sdhi: 2 In:serial Out: serial Err: serial Net: ravb Hit any key to stop autoboot: 0 ravb Waiting for PHY auto negotiation to complete.. done ravb: 100Base/Full Using ravb device TFTP from server 192.168.1.8; our IP address is 192.168.1.18 Filename 'Salvator-X/Image'. Load address: 0x5000 Loading: # # # # # # # # # # # # # # # 1 MiB/s done Bytes transferred = 14182912 (d86a00 hex) ravb:0 is connected to ravb. Reconnecting to ravb ravb Waiting for PHY auto negotiation to complete.. done ravb: 100Base/Full Using ravb device TFTP from server 192.168.1.8; our IP address is 192.168.1.18 Filename 'Salvator-X/r8a7795-salvator-x.dtb'. Load address: 0x48f0 Loading: ### 6.8 KiB/s done Bytes transferred = 35648 (8b40 hex) ## Flattened Device Tree blob at 48f0 Booting using the fdt blob at 0x48f0 Using Device Tree in place at 48f0, end 48f0bb3f Starting kernel ... [0.00] Booting Linux on physical CPU 0x0 [0.00] Linux version 4.9.0-1-g4a5b13a-dirty (hoan@HoanNa) (gcc version 4.9.2 20140904 (prerelease) (crosstool-NG l6 [0.00] Boot CPU: AArch64 Processor [411fd073] [0.00] debug: ignoring loglevel setting. [0.00] efi: Getting EFI p
Re: The failure summary report of GEN3 for linux stable v4.9
Dear Geert Uytterhoeven, (I resend my mail because of making mistake at previous mail) I have retested PM, recheck the PM test procedures. Are you using R-Car H3 ES1.0? I am using board H3 ES1.1. With the same test procedures and setting for this version and previous version(v4.9-rc2), but the results are different. (Only U-boot versions are different for two version) I am using U-boot version(U-Boot 2015.04 (Sep 13 2016 - 11:32:36)). I attach the test log file of PM. Please have a look at the log. AFAIK, tbe newer firmware supports system suspend/resume on H3 ES1.1 only, and only when following the right procedure involving i2cset. I only set the following command for test. root@linaro-nano:~# echo enabled > /sys/devices/platform/soc/e6e68000.serial/tty/ttySC1/power/wakeup root@linaro-nano:~# echo enabled > /sys/devices/platform/soc/e6e88000.serial/tty/ttySC0/power/wakeup root@linaro-nano:~# echo mem > /sys/power/state Could you please tell me more details for using i2cset?. Thanks, Jinzai Solution/Linux Team, Hoan. NOTICE: BL2: R-Car Gen3 Initial Program Loader(CA57) Rev.1.0.9 NOTICE: BL2: PRR is R-Car H3 ES1.1 NOTICE: BL2: Boot device is HyperFlash(80MHz) NOTICE: BL2: LCM state is CM NOTICE: BL2: AVS setting succeeded. DVFS_SetVID=0x52 NOTICE: BL2: DDR1600(rev.0.15) NOTICE: BL2: DRAM Split is 4ch NOTICE: BL2: QoS is default setting(rev.0.32) NOTICE: BL2: v1.1(release):3ad02ac NOTICE: BL2: Built : 11:32:54, Sep 13 2016 NOTICE: BL2: Normal boot NOTICE: BL2: dst=0xe631a208 src=0x818 len=512(0x200) NOTICE: BL2: dst=0x43f0 src=0x8180400 len=6144(0x1800) NOTICE: BL2: dst=0x4400 src=0x81c len=65536(0x1) NOTICE: BL2: dst=0x4410 src=0x820 len=524288(0x8) NOTICE: BL2: dst=0x4900 src=0x864 len=1048576(0x10) U-Boot 2015.04 (Sep 13 2016 - 11:32:36) CPU: Renesas Electronics R8A7795 rev 1.1 Board: Salvator-X I2C: ready DRAM: 3.9 GiB MMC: sh-sdhi: 0, sh-sdhi: 1, sh-sdhi: 2 In:serial Out: serial Err: serial Net: ravb Hit any key to stop autoboot: 0 ravb Waiting for PHY auto negotiation to complete.. done ravb: 100Base/Full Using ravb device TFTP from server 192.168.1.8; our IP address is 192.168.1.18 Filename 'Salvator-X/Image'. Load address: 0x5000 Loading: # # # # # # # # # # # # # # # 1 MiB/s done Bytes transferred = 14182912 (d86a00 hex) ravb:0 is connected to ravb. Reconnecting to ravb ravb Waiting for PHY auto negotiation to complete.. done ravb: 100Base/Full Using ravb device TFTP from server 192.168.1.8; our IP address is 192.168.1.18 Filename 'Salvator-X/r8a7795-salvator-x.dtb'. Load address: 0x48f0 Loading: ### 6.8 KiB/s done Bytes transferred = 35648 (8b40 hex) ## Flattened Device Tree blob at 48f0 Booting using the fdt blob at 0x48f0 Using Device Tree in place at 48f0, end 48f0bb3f Starting kernel ... [0.00] Booting Linux on physical CPU 0x0 [0.00] Linux version 4.9.0-1-g4a5b13a-dirty (hoan@HoanNa) (gcc version 4.9.2 20140904 (prerelease) (crosstool-NG l6 [0.00] Boot CPU: AArch64 Processor [411fd073] [0.00] debug: ignoring loglevel setting. [0.00] efi: Getting EFI parameters from FDT: [0.00] efi: UEFI not found. [0.00] cma: Reserved 16 MiB at 0x7f00 [0.00] On node 0 totalpages: 1015808 [0.00] DMA zone: 3584 pages used for memmap [0.00] DMA zone: 0 pages reserved [0.00] DMA zone: 229376 pages, LIFO batch:31 [0.00] Normal zone: 12288 pages used for memmap [0.00] Normal zone: 786432 pages, LIFO batch:31 [0.00] psci: probing for conduit method from DT. [0.00] psci: PSCIv1.0 detected in firmware. [0.00] psci: Using standard PSCI v0.2 function IDs [0.00] psci: Trusted OS migration not required [0.00] percpu: Embedded 21
The failure summary report of GEN3 for linux stable v4.9
Hi all, My name is Hoan from Jinzai Solution. We have tested the linux stable v4.9 for Gen3 Salvator-X (H3) So we would like to report the summary of the failure. Best Regards, Jinso/Linux Team HOAN GEN3(H3)_The failure summary report for linux stable v4.9.xlsx Description: MS-Excel 2007 spreadsheet
