[PATCH v3 2/2] dt-bindings: can: rcar_canfd: add r8a77995 (R-Car D3) compatibility strings

[Ulrich Hecht]

From: Ulrich Hecht 

Adds compatible strings for the R-Car CAN FD controller in the D3 SoC.

Signed-off-by: Ulrich Hecht 
Acked-by: Rob Herring 
Reviewed-by: Geert Uytterhoeven 
Reviewed-by: Simon Horman 
---
 Documentation/devicetree/bindings/net/can/rcar_canfd.txt | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt 
b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
index ac71daa..ae2a2b7 100644
--- a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
+++ b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt
@@ -8,6 +8,7 @@ Required properties:
   - "renesas,r8a7796-canfd" for R8A7796 (R-Car M3-W) compatible controller.
   - "renesas,r8a77970-canfd" for R8A77970 (R-Car V3M) compatible controller.
   - "renesas,r8a77980-canfd" for R8A77980 (R-Car V3H) compatible controller.
+  - "renesas,r8a77995-canfd" for R8A77995 (R-Car D3) compatible controller.
 
   When compatible with the generic version, nodes must list the
   SoC-specific version corresponding to the platform first, followed by the
@@ -26,10 +27,9 @@ The name of the child nodes are "channel0" and "channel1" 
respectively. Each
 child node supports the "status" property only, which is used to
 enable/disable the respective channel.
 
-Required properties for "renesas,r8a7795-canfd" and "renesas,r8a7796-canfd"
-compatible:
-In R8A7795 and R8A7796 SoCs, canfd clock is a div6 clock and can be used by 
both
-CAN and CAN FD controller at the same time. It needs to be scaled to maximum
+Required properties for R8A7795, R8A7796 and R8A77995:
+In the denoted SoCs, canfd clock is a div6 clock and can be used by both CAN
+and CAN FD controller at the same time. It needs to be scaled to maximum
 frequency if any of these controllers use it. This is done using the below
 properties:
 
-- 
2.7.4

[PATCH v3 1/2] dt-bindings: can: rcar_can: add r8a77995 (R-Car D3) compatibility strings

[Ulrich Hecht]

From: Ulrich Hecht 

Adds compatible strings for the R-Car CAN controller in the D3 SoC.

Signed-off-by: Ulrich Hecht 
Acked-by: Rob Herring 
Reviewed-by: Geert Uytterhoeven 
Reviewed-by: Simon Horman 
---
 Documentation/devicetree/bindings/net/can/rcar_can.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/net/can/rcar_can.txt 
b/Documentation/devicetree/bindings/net/can/rcar_can.txt
index 9936b9e..a72ced1 100644
--- a/Documentation/devicetree/bindings/net/can/rcar_can.txt
+++ b/Documentation/devicetree/bindings/net/can/rcar_can.txt
@@ -16,6 +16,7 @@ Required properties:
  "renesas,can-r8a7795" if CAN controller is a part of R8A7795 SoC.
  "renesas,can-r8a7796" if CAN controller is a part of R8A7796 SoC.
  "renesas,can-r8a77965" if CAN controller is a part of R8A77965 
SoC.
+ "renesas,can-r8a77995" if CAN controller is a part of R8A77995 
SoC.
  "renesas,rcar-gen1-can" for a generic R-Car Gen1 compatible 
device.
  "renesas,rcar-gen2-can" for a generic R-Car Gen2 or RZ/G1
  compatible device.
@@ -37,7 +38,7 @@ Required properties:
 - pinctrl-0: pin control group to be used for this controller.
 - pinctrl-names: must be "default".
 
-Required properties for R8A7795, R8A7796 and R8A77965:
+Required properties for R8A7795, R8A7796, R8A77965 and R8A77995:
 For the denoted SoCs, "clkp2" can be CANFD clock. This is a div6 clock and can
 be used by both CAN and CAN FD controller at the same time. It needs to be
 scaled to maximum frequency if any of these controllers use it. This is done
-- 
2.7.4

[PATCH v3 0/2] dt-bindings: can: rcar_can*: add R-Car D3

[Ulrich Hecht]

Hi!

These are the bindings for CAN and CAN FD controllers on R-Car D3
(R8A77995).

Changes since v2:
- rebased
- made wording less redundant in rcar_canfd.txt
- added dt-bindings prefix to subjects

CU
Uli


Ulrich Hecht (2):
  dt-bindings: can: rcar_can: add r8a77995 (R-Car D3) compatibility
strings
  dt-bindings: can: rcar_canfd: add r8a77995 (R-Car D3) compatibility
strings

 Documentation/devicetree/bindings/net/can/rcar_can.txt   | 3 ++-
 Documentation/devicetree/bindings/net/can/rcar_canfd.txt | 8 
 2 files changed, 6 insertions(+), 5 deletions(-)

-- 
2.7.4

Re: [PATCH v2 1/4] pinctrl: sh-pfc: Add physical pin multiplexing helper macros

[Ulrich Hecht]

> On November 16, 2018 at 9:42 AM Geert Uytterhoeven  
> wrote:
> 
> 
> Hi Uli,
> 
> On Fri, Nov 16, 2018 at 8:21 AM Ulrich Hecht  wrote:
> > Used by I2C controllers 0, 3 and 5 in R8A7795 and R8A7796 SoCs.
> >
> > Signed-off-by: Ulrich Hecht 
> 
> Thanks for your patch!
> 
> Reviewed-by: Geert Uytterhoeven 
> 
> Some bikeshedding below, which I believe would increase readability.
> 
> > --- a/drivers/pinctrl/sh-pfc/sh_pfc.h
> > +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
> > @@ -386,6 +386,28 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
> > PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
> >
> >  /*
> > + * Describe a pinmux configuration similar to PINMUX_IPSR_MSEL, but with
> > + * an additional select register that controls physical multiplexing
> > + * with another pin.
> > + *   - ipsr: IPSR field
> > + *   - fn: Function name, also referring to the IPSR field
> > + *   - msel1: Physical multiplexing selector
> 
> psel?
> 
> > + *   - msel2: Module selector
> 
> msel?
> 
> > + */
> > +#define PINMUX_IPSR_MSEL2(ipsr, fn, msel1, msel2) \
> 
> PINMUX_IPSR_PHYS_MSEL?
> 
> > +   PINMUX_DATA(fn##_MARK, FN_##msel1, FN_##msel2, FN_##fn, FN_##ipsr)
> > +
> > +/*
> > + * Describe a pinmux configuration in which a pin is physically multiplexed
> > + * with other pins.
> > + *   - ipsr: IPSR field
> > + *   - fn: Function name, also referring to the IPSR field
> > + *   - msel: Phyiscal multiplexing selector
> 
> psel?
> Physical
> 
> > + */
> > +#define PINMUX_IPSR_PHYS(ipsr, fn, msel) \
> > +   PINMUX_DATA(fn##_MARK, FN_##msel)
> > +
> > +/*
> >   * Describe a pinmux configuration for a single-function pin with GPIO
> >   * capability.
> >   *   - fn: Function name
> 
> If you agree, I can fix up all of the above while applying.

That would be fine with me, thank you.

CU
Uli

[PATCH v2 2/4] pinctrl: sh-pfc: r8a7795: Add I2C{0,3,5} pins, groups and functions

[Ulrich Hecht]

From: Takeshi Kihara 

This patch adds I2C{0,3,5} pins, groups and functions to the R8A7795 SoC.

These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Ulrich Hecht 
---
 drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 95 
 1 file changed, 74 insertions(+), 21 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 0af737d..6f3a969 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -550,6 +550,9 @@ MOD_SEL0_4_3MOD_SEL1_4 \
FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) 
FM(EXTALR)
 
+#define PINMUX_PHYS \
+   FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
+
 enum {
PINMUX_RESERVED = 0,
 
@@ -575,6 +578,7 @@ enum {
PINMUX_IPSR
PINMUX_MOD_SELS
PINMUX_STATIC
+   PINMUX_PHYS
PINMUX_MARK_END,
 #undef F_
 #undef FM
@@ -588,9 +592,6 @@ static const u16 pinmux_data[] = {
PINMUX_SINGLE(CLKOUT),
PINMUX_SINGLE(HDMI0_CEC),
PINMUX_SINGLE(HDMI1_CEC),
-   PINMUX_SINGLE(I2C_SEL_0_1),
-   PINMUX_SINGLE(I2C_SEL_3_1),
-   PINMUX_SINGLE(I2C_SEL_5_1),
PINMUX_SINGLE(MSIOF0_RXD),
PINMUX_SINGLE(MSIOF0_SCK),
PINMUX_SINGLE(MSIOF0_TXD),
@@ -614,14 +615,16 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C,   SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_15_12, TX4_A,  SEL_SCIF4_0),
 
-   PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A,   SEL_ETHERAVB_0),
-   PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C,   SEL_MSIOF2_2),
-   PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A,   SEL_SCIF4_0),
-   PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
+   PINMUX_IPSR_MSEL2(IP0_19_16,AVB_AVTP_MATCH_A,   I2C_SEL_5_0, 
SEL_ETHERAVB_0),
+   PINMUX_IPSR_MSEL2(IP0_19_16,MSIOF2_RXD_C,   I2C_SEL_5_0, 
SEL_MSIOF2_2),
+   PINMUX_IPSR_MSEL2(IP0_19_16,CTS4_N_A,   I2C_SEL_5_0, 
SEL_SCIF4_0),
+   PINMUX_IPSR_MSEL(IP0_19_16, FSCLKST2_N_A,   I2C_SEL_5_0),
+   PINMUX_IPSR_PHYS(IP0_19_16, SCL5,   I2C_SEL_5_1),
 
-   PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
-   PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C,   SEL_MSIOF2_2),
-   PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A,   SEL_SCIF4_0),
+   PINMUX_IPSR_MSEL2(IP0_23_20,AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, 
SEL_ETHERAVB_0),
+   PINMUX_IPSR_MSEL2(IP0_23_20,MSIOF2_TXD_C,   I2C_SEL_5_0, 
SEL_MSIOF2_2),
+   PINMUX_IPSR_MSEL2(IP0_23_20,RTS4_N_A,   I2C_SEL_5_0, 
SEL_SCIF4_0),
+   PINMUX_IPSR_PHYS(IP0_23_20, SDA5,   I2C_SEL_5_1),
 
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
@@ -674,14 +677,16 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B,SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B,SEL_IEBUS_1),
 
-   PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
-   PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
-   PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B,SEL_VIN4_1),
-   PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
+   PINMUX_IPSR_MSEL2(IP1_23_20,PWM1_A, I2C_SEL_3_0, 
SEL_PWM1_0),
+   PINMUX_IPSR_MSEL2(IP1_23_20,HRX3_D, I2C_SEL_3_0, 
SEL_HSCIF3_3),
+   PINMUX_IPSR_MSEL2(IP1_23_20,VI4_DATA7_B,I2C_SEL_3_0, 
SEL_VIN4_1),
+   PINMUX_IPSR_MSEL2(IP1_23_20,IERX_B, I2C_SEL_3_0, 
SEL_IEBUS_1),
+   PINMUX_IPSR_PHYS(IP0_23_20, SCL3,   I2C_SEL_3_1),
 
-   PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
-   PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
-   PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
+   PINMUX_IPSR_MSEL2(IP1_27_24,PWM2_A, I2C_SEL_3_0, 
SEL_PWM2_0),
+   PINMUX_IPSR_MSEL2(IP1_27_24,HTX3_D, I2C_SEL_3_0, 
SEL_HSCIF3_3),
+   PINMUX_IPSR_MSEL2(IP1_27_24,IETX_B, I2C_SEL_3_0, 
SEL_IEBUS_1),
+   PINMUX_IPSR_PHYS(IP1_27_24, SDA3,   I2C_SEL_3_1),
 
PINMUX_IPSR_GPSR(IP1_31_28, A0),
PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
@@ -1113,11 +1118,13 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP11_15_12,SD0_WP),
PINMUX_IPSR_MSEL(IP11_15_12,SDA2_B, SEL_I2C2_1

[PATCH v2 3/4] pinctrl: sh-pfc: r8a7795-es1: Add I2C{0,3,5} pins, groups and functions

[Ulrich Hecht]

From: Takeshi Kihara 

This patch adds I2C{0,3,5} pins, groups and functions to
the R8A7795 ES1.x SoC.

These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Ulrich Hecht 
---
 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 97 
 1 file changed, 75 insertions(+), 22 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
index 8c7de44..59cb0d7 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
@@ -537,6 +537,9 @@ MOD_SEL0_2_1MOD_SEL1_2 \
FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) 
FM(EXTALR)
 
+#define PINMUX_PHYS \
+   FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
+
 enum {
PINMUX_RESERVED = 0,
 
@@ -562,6 +565,7 @@ enum {
PINMUX_IPSR
PINMUX_MOD_SELS
PINMUX_STATIC
+   PINMUX_PHYS
PINMUX_MARK_END,
 #undef F_
 #undef FM
@@ -574,9 +578,6 @@ static const u16 pinmux_data[] = {
PINMUX_SINGLE(AVS2),
PINMUX_SINGLE(HDMI0_CEC),
PINMUX_SINGLE(HDMI1_CEC),
-   PINMUX_SINGLE(I2C_SEL_0_1),
-   PINMUX_SINGLE(I2C_SEL_3_1),
-   PINMUX_SINGLE(I2C_SEL_5_1),
PINMUX_SINGLE(MSIOF0_RXD),
PINMUX_SINGLE(MSIOF0_SCK),
PINMUX_SINGLE(MSIOF0_TXD),
@@ -608,13 +609,15 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C,   SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_15_12, TX4_A,  SEL_SCIF4_0),
 
-   PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A,   SEL_ETHERAVB_0),
-   PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C,   SEL_MSIOF2_2),
-   PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A,   SEL_SCIF4_0),
+   PINMUX_IPSR_MSEL2(IP0_19_16,AVB_AVTP_MATCH_A,   I2C_SEL_5_0, 
SEL_ETHERAVB_0),
+   PINMUX_IPSR_MSEL2(IP0_19_16,MSIOF2_RXD_C,   I2C_SEL_5_0, 
SEL_MSIOF2_2),
+   PINMUX_IPSR_MSEL2(IP0_19_16,CTS4_N_A,   I2C_SEL_5_0, 
SEL_SCIF4_0),
+   PINMUX_IPSR_PHYS(IP0_19_16, SCL5,   I2C_SEL_5_1),
 
-   PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
-   PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C,   SEL_MSIOF2_2),
-   PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A,  SEL_SCIF4_0),
+   PINMUX_IPSR_MSEL2(IP0_23_20,AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, 
SEL_ETHERAVB_0),
+   PINMUX_IPSR_MSEL2(IP0_23_20,MSIOF2_TXD_C,   I2C_SEL_5_0, 
SEL_MSIOF2_2),
+   PINMUX_IPSR_MSEL2(IP0_23_20,RTS4_N_TANS_A,  I2C_SEL_5_0, 
SEL_SCIF4_0),
+   PINMUX_IPSR_PHYS(IP0_23_20, SDA5,   I2C_SEL_5_1),
 
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
@@ -664,16 +667,18 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B,SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B,SEL_IEBUS_1),
 
-   PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
-   PINMUX_IPSR_GPSR(IP1_23_20, A21),
-   PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
-   PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B,SEL_VIN4_1),
-   PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
+   PINMUX_IPSR_MSEL2(IP1_23_20,PWM1_A, I2C_SEL_3_0,
SEL_PWM1_0),
+   PINMUX_IPSR_MSEL(IP1_23_20, A21,I2C_SEL_3_0),
+   PINMUX_IPSR_MSEL2(IP1_23_20,HRX3_D, I2C_SEL_3_0,
SEL_HSCIF3_3),
+   PINMUX_IPSR_MSEL2(IP1_23_20,VI4_DATA7_B,I2C_SEL_3_0,
SEL_VIN4_1),
+   PINMUX_IPSR_MSEL2(IP1_23_20,IERX_B, I2C_SEL_3_0,
SEL_IEBUS_1),
+   PINMUX_IPSR_PHYS(IP0_23_20, SCL3,   I2C_SEL_3_1),
 
-   PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
-   PINMUX_IPSR_GPSR(IP1_27_24, A20),
-   PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
-   PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
+   PINMUX_IPSR_MSEL2(IP1_27_24,PWM2_A, I2C_SEL_3_0,
SEL_PWM2_0),
+   PINMUX_IPSR_MSEL(IP1_27_24, A20,I2C_SEL_3_0),
+   PINMUX_IPSR_MSEL2(IP1_27_24,HTX3_D, I2C_SEL_3_0,
SEL_HSCIF3_3),
+   PINMUX_IPSR_MSEL2(IP1_27_24,IETX_B, I2C_SEL_3_0,
SEL_IEBUS_1),
+   PINMUX_IPSR_PHYS(IP1_27_24, SDA3,   I2C_SEL_3_1),
 
PINMUX_IPSR_GPSR(IP1_31_28, A0),
PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
@@ -1067,11 +1072,13 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP10_15_12,SD0_WP

[PATCH v2 4/4] pinctrl: sh-pfc: r8a7796: Add I2C{0,3,5} pins, groups and functions

[Ulrich Hecht]

From: Takeshi Kihara 

This patch adds I2C{0,3,5} pins, groups and functions to the R8A7796 SoC.

These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Ulrich Hecht 
---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 98 
 1 file changed, 77 insertions(+), 21 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 3a6d21d..b1f45d8 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -556,6 +556,9 @@ MOD_SEL0_4_3MOD_SEL1_4 \
FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) 
FM(EXTALR)
 
+#define PINMUX_PHYS \
+   FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
+
 enum {
PINMUX_RESERVED = 0,
 
@@ -581,6 +584,7 @@ enum {
PINMUX_IPSR
PINMUX_MOD_SELS
PINMUX_STATIC
+   PINMUX_PHYS
PINMUX_MARK_END,
 #undef F_
 #undef FM
@@ -617,13 +621,15 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C,   SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_15_12, TX4_A,  SEL_SCIF4_0),
 
-   PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A,   SEL_ETHERAVB_0),
-   PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C,   SEL_MSIOF2_2),
-   PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A,   SEL_SCIF4_0),
+   PINMUX_IPSR_MSEL2(IP0_19_16,AVB_AVTP_MATCH_A,   I2C_SEL_5_0, 
SEL_ETHERAVB_0),
+   PINMUX_IPSR_MSEL2(IP0_19_16,MSIOF2_RXD_C,   I2C_SEL_5_0, 
SEL_MSIOF2_2),
+   PINMUX_IPSR_MSEL2(IP0_19_16,CTS4_N_A,   I2C_SEL_5_0, 
SEL_SCIF4_0),
+   PINMUX_IPSR_PHYS(IP0_19_16, SCL5,   I2C_SEL_5_1),
 
-   PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
-   PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C,   SEL_MSIOF2_2),
-   PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A,   SEL_SCIF4_0),
+   PINMUX_IPSR_MSEL2(IP0_23_20,AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, 
SEL_ETHERAVB_0),
+   PINMUX_IPSR_MSEL2(IP0_23_20,MSIOF2_TXD_C,   I2C_SEL_5_0, 
SEL_MSIOF2_2),
+   PINMUX_IPSR_MSEL2(IP0_23_20,RTS4_N_A,   I2C_SEL_5_0, 
SEL_SCIF4_0),
+   PINMUX_IPSR_PHYS(IP0_23_20, SDA5,   I2C_SEL_5_1),
 
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
@@ -675,14 +681,16 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B,SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B,SEL_IEBUS_1),
 
-   PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
-   PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
-   PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B,SEL_VIN4_1),
-   PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
+   PINMUX_IPSR_MSEL2(IP1_23_20,PWM1_A, I2C_SEL_3_0,
SEL_PWM1_0),
+   PINMUX_IPSR_MSEL2(IP1_23_20,HRX3_D, I2C_SEL_3_0,
SEL_HSCIF3_3),
+   PINMUX_IPSR_MSEL2(IP1_23_20,VI4_DATA7_B,I2C_SEL_3_0,
SEL_VIN4_1),
+   PINMUX_IPSR_MSEL2(IP1_23_20,IERX_B, I2C_SEL_3_0,
SEL_IEBUS_1),
+   PINMUX_IPSR_PHYS(IP0_23_20, SCL3,   I2C_SEL_3_1),
 
-   PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
-   PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
-   PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
+   PINMUX_IPSR_MSEL2(IP1_27_24,PWM2_A, I2C_SEL_3_0,
SEL_PWM2_0),
+   PINMUX_IPSR_MSEL2(IP1_27_24,HTX3_D, I2C_SEL_3_0,
SEL_HSCIF3_3),
+   PINMUX_IPSR_MSEL2(IP1_27_24,IETX_B, I2C_SEL_3_0,
SEL_IEBUS_1),
+   PINMUX_IPSR_PHYS(IP1_27_24, SDA3,   I2C_SEL_3_1),
 
PINMUX_IPSR_GPSR(IP1_31_28, A0),
PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
@@ -1115,13 +1123,15 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP11_15_12,NFDATA15_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_15_12,SDA2_B, SEL_I2C2_1),
 
-   PINMUX_IPSR_GPSR(IP11_19_16,SD1_CD),
-   PINMUX_IPSR_MSEL(IP11_19_16,NFRB_N_A,   SEL_NDFC_0),
-   PINMUX_IPSR_MSEL(IP11_19_16,SIM0_CLK_B, SEL_SIMCARD_1),
+   PINMUX_IPSR_MSEL(IP11_19_16,SD1_CD, I2C_SEL_0_0),
+   PINMUX_IPSR_MSEL2(IP11_19_16,   NFRB_N_A,   I2C_SEL_0_0, 
SEL_NDFC_0),
+   PINMUX_IPSR_MSEL2(IP11_19_16,   SIM0_CLK_B, I2C_SEL_0_0, 
SEL_SIMCARD_1),
+   PINMUX_IPSR_PHYS(IP11_19_16,SCL0,   I2C_SEL_0_1

[PATCH v2 1/4] pinctrl: sh-pfc: Add physical pin multiplexing helper macros

[Ulrich Hecht]

Used by I2C controllers 0, 3 and 5 in R8A7795 and R8A7796 SoCs.

Signed-off-by: Ulrich Hecht 
---
 drivers/pinctrl/sh-pfc/sh_pfc.h | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 1fc1336..6bb9c6b 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -386,6 +386,28 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
 
 /*
+ * Describe a pinmux configuration similar to PINMUX_IPSR_MSEL, but with
+ * an additional select register that controls physical multiplexing
+ * with another pin.
+ *   - ipsr: IPSR field
+ *   - fn: Function name, also referring to the IPSR field
+ *   - msel1: Physical multiplexing selector
+ *   - msel2: Module selector
+ */
+#define PINMUX_IPSR_MSEL2(ipsr, fn, msel1, msel2) \
+   PINMUX_DATA(fn##_MARK, FN_##msel1, FN_##msel2, FN_##fn, FN_##ipsr)
+
+/*
+ * Describe a pinmux configuration in which a pin is physically multiplexed
+ * with other pins.
+ *   - ipsr: IPSR field
+ *   - fn: Function name, also referring to the IPSR field
+ *   - msel: Phyiscal multiplexing selector
+ */
+#define PINMUX_IPSR_PHYS(ipsr, fn, msel) \
+   PINMUX_DATA(fn##_MARK, FN_##msel)
+
+/*
  * Describe a pinmux configuration for a single-function pin with GPIO
  * capability.
  *   - fn: Function name
-- 
2.7.4

[PATCH v2 0/4] I2C0/3/5 pin control for H3 and M3-W

[Ulrich Hecht]

This is an up-port from the BSP. Unfortunately I could not test these
because none of those pins seem to be accessible on Salvator boards (not on
ULCB either, AFAICT), so the best thing I can say is that they don't seem to
break anything.

This revision incorporates the suggestions made by Geert; see below for
details.

CU
Uli


Changes since v1:
- factor out identical macros to sh_pfc.h, comment them
- sort pin groups
- adjust for common/automotive split in r8a7796


Takeshi Kihara (3):
  pinctrl: sh-pfc: r8a7795: Add I2C{0,3,5} pins, groups and functions
  pinctrl: sh-pfc: r8a7795-es1: Add I2C{0,3,5} pins, groups and
functions
  pinctrl: sh-pfc: r8a7796: Add I2C{0,3,5} pins, groups and functions

Ulrich Hecht (1):
  pinctrl: sh-pfc: Add physical pin multiplexing helper macros

 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 97 ---
 drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 95 ---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 98 +---
 drivers/pinctrl/sh-pfc/sh_pfc.h  | 22 +++
 4 files changed, 248 insertions(+), 64 deletions(-)

-- 
2.7.4

Re: [PATCH/RFC] dmaengine: sh: Remove R-Mobile APE6 support

[Ulrich Hecht]

4bdd..
> --- a/drivers/dma/sh/shdma-r8a73a4.c
> +++ /dev/null
> @@ -1,74 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0
> -/*
> - * Renesas SuperH DMA Engine support for r8a73a4 (APE6) SoCs
> - *
> - * Copyright (C) 2013 Renesas Electronics, Inc.
> - */
> -#include 
> -
> -#include "shdma-arm.h"
> -
> -static const unsigned int dma_ts_shift[] = SH_DMAE_TS_SHIFT;
> -
> -static const struct sh_dmae_slave_config dma_slaves[] = {
> - {
> - .chcr   = CHCR_TX(XMIT_SZ_32BIT),
> - .mid_rid= 0xd1, /* MMC0 Tx */
> - }, {
> - .chcr   = CHCR_RX(XMIT_SZ_32BIT),
> - .mid_rid= 0xd2, /* MMC0 Rx */
> - }, {
> - .chcr   = CHCR_TX(XMIT_SZ_32BIT),
> - .mid_rid= 0xe1, /* MMC1 Tx */
> - }, {
> - .chcr   = CHCR_RX(XMIT_SZ_32BIT),
> - .mid_rid= 0xe2, /* MMC1 Rx */
> - },
> -};
> -
> -#define DMAE_CHANNEL(a, b)   \
> - {   \
> - .offset = (a) - 0x20,   \
> - .dmars  = (a) - 0x20 + 0x40,\
> - .chclr_bit  = (b),  \
> - .chclr_offset   = 0x80 - 0x20,  \
> - }
> -
> -static const struct sh_dmae_channel dma_channels[] = {
> - DMAE_CHANNEL(0x8000, 0),
> - DMAE_CHANNEL(0x8080, 1),
> - DMAE_CHANNEL(0x8100, 2),
> - DMAE_CHANNEL(0x8180, 3),
> - DMAE_CHANNEL(0x8200, 4),
> - DMAE_CHANNEL(0x8280, 5),
> - DMAE_CHANNEL(0x8300, 6),
> - DMAE_CHANNEL(0x8380, 7),
> - DMAE_CHANNEL(0x8400, 8),
> - DMAE_CHANNEL(0x8480, 9),
> - DMAE_CHANNEL(0x8500, 10),
> - DMAE_CHANNEL(0x8580, 11),
> - DMAE_CHANNEL(0x8600, 12),
> - DMAE_CHANNEL(0x8680, 13),
> - DMAE_CHANNEL(0x8700, 14),
> - DMAE_CHANNEL(0x8780, 15),
> - DMAE_CHANNEL(0x8800, 16),
> - DMAE_CHANNEL(0x8880, 17),
> - DMAE_CHANNEL(0x8900, 18),
> - DMAE_CHANNEL(0x8980, 19),
> -};
> -
> -const struct sh_dmae_pdata r8a73a4_dma_pdata = {
> - .slave  = dma_slaves,
> - .slave_num  = ARRAY_SIZE(dma_slaves),
> - .channel= dma_channels,
> - .channel_num= ARRAY_SIZE(dma_channels),
> - .ts_low_shift   = TS_LOW_SHIFT,
> - .ts_low_mask= TS_LOW_BIT << TS_LOW_SHIFT,
> - .ts_high_shift  = TS_HI_SHIFT,
> - .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
> - .ts_shift   = dma_ts_shift,
> - .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
> - .dmaor_init = DMAOR_DME,
> - .chclr_present  = 1,
> - .chclr_bitwise  = 1,
> -};
> diff --git a/drivers/dma/sh/shdma.h b/drivers/dma/sh/shdma.h
> index bfb69909bd192759..9c121a4b33ad829c 100644
> --- a/drivers/dma/sh/shdma.h
> +++ b/drivers/dma/sh/shdma.h
> @@ -58,11 +58,4 @@ struct sh_dmae_desc {
>  #define to_sh_dev(chan) container_of(chan->shdma_chan.dma_chan.device,\
>struct sh_dmae_device, shdma_dev.dma_dev)
>  
> -#ifdef CONFIG_SH_DMAE_R8A73A4
> -extern const struct sh_dmae_pdata r8a73a4_dma_pdata;
> -#define r8a73a4_shdma_devid (_dma_pdata)
> -#else
> -#define r8a73a4_shdma_devid NULL
> -#endif
> -
>  #endif   /* __DMA_SHDMA_H */
> diff --git a/drivers/dma/sh/shdmac.c b/drivers/dma/sh/shdmac.c
> index 7971ea2753877486..5aafe548ca5f3082 100644
> --- a/drivers/dma/sh/shdmac.c
> +++ b/drivers/dma/sh/shdmac.c
> @@ -665,12 +665,6 @@ static const struct shdma_ops sh_dmae_shdma_ops = {
>   .get_partial = sh_dmae_get_partial,
>  };
>  
> -static const struct of_device_id sh_dmae_of_match[] = {
> - {.compatible = "renesas,shdma-r8a73a4", .data = r8a73a4_shdma_devid,},
> - {}
> -};
> -MODULE_DEVICE_TABLE(of, sh_dmae_of_match);
> -
>  static int sh_dmae_probe(struct platform_device *pdev)
>  {
>   const enum dma_slave_buswidth widths =
> @@ -915,7 +909,6 @@ static struct platform_driver sh_dmae_driver = {
>   .driver = {
>   .pm = _dmae_pm,
>   .name   = SH_DMAE_DRV_NAME,
> - .of_match_table = sh_dmae_of_match,
>   },
>   .remove = sh_dmae_remove,
>  };
> -- 
> 2.17.1
>

Reviewed-by: Ulrich Hecht 

CU
Uli

Re: [PATCH] serial: sh-sci: Improve type-safety calling sci_receive_chars()

[Ulrich Hecht]

Thanks for your patch!

> On November 7, 2018 at 2:37 PM Geert Uytterhoeven  
> wrote:
> 
> 
> While ptr and port both point to the uart_port structure, the former is
> the untyped pointer cookie passed to interrupt handlers.
> Use the correctly typed port variable instead, to improve type-safety.
> 
> Signed-off-by: Geert Uytterhoeven 
> ---
>  drivers/tty/serial/sh-sci.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
> index 8863689a6eebcc72..f1ee992532717a34 100644
> --- a/drivers/tty/serial/sh-sci.c
> +++ b/drivers/tty/serial/sh-sci.c
> @@ -1710,7 +1710,7 @@ static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
>* of whether the I_IXOFF is set, otherwise, how is the interrupt
>* to be disabled?
>*/
> - sci_receive_chars(ptr);
> + sci_receive_chars(port);
>  
>   return IRQ_HANDLED;
>  }
> @@ -1766,7 +1766,7 @@ static irqreturn_t sci_er_interrupt(int irq, void *ptr)
>   } else {
>   sci_handle_fifo_overrun(port);
>   if (!s->chan_rx)
> - sci_receive_chars(ptr);
> + sci_receive_chars(port);
>   }
>  
>   sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
> -- 
> 2.17.1
>

Reviewed-by: Ulrich Hecht 

CU
Uli

Re: [PATCH] serial: sh-sci: Fix could not remove dev_attr_rx_fifo_timeout

[Ulrich Hecht]

Thanks for your patch!

> On October 30, 2018 at 7:13 AM Yoshihiro Shimoda 
>  wrote:
> 
> 
> This patch fixes an issue that the sci_remove() could not remove
> dev_attr_rx_fifo_timeout because uart_remove_one_port() set
> the port->port.type to PORT_UNKNOWN.
> 
> Reported-by: Hiromitsu Yamasaki 
> Fixes: 5d23188a473d ("serial: sh-sci: make RX FIFO parameters tunable via 
> sysfs")
> Cc:  # v4.11+
> Signed-off-by: Yoshihiro Shimoda 
> ---
>  drivers/tty/serial/sh-sci.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
> index ab3f6e91..3649b83 100644
> --- a/drivers/tty/serial/sh-sci.c
> +++ b/drivers/tty/serial/sh-sci.c
> @@ -3102,6 +3102,7 @@ static inline int sci_probe_earlyprintk(struct 
> platform_device *pdev)
>  static int sci_remove(struct platform_device *dev)
>  {
>   struct sci_port *port = platform_get_drvdata(dev);
> + unsigned int type = port->port.type;/* uart_remove_... clears it */
>  
>   sci_ports_in_use &= ~BIT(port->port.line);
>   uart_remove_one_port(_uart_driver, >port);
> @@ -3112,8 +3113,7 @@ static int sci_remove(struct platform_device *dev)
>   sysfs_remove_file(>dev.kobj,
> _attr_rx_fifo_trigger.attr);
>   }
> - if (port->port.type == PORT_SCIFA || port->port.type == PORT_SCIFB ||
> - port->port.type == PORT_HSCIF) {
> + if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) {
>   sysfs_remove_file(>dev.kobj,
> _attr_rx_fifo_timeout.attr);
>   }
> -- 
> 1.9.1
>

Reviewed-by: Ulrich Hecht 

CU
Uli

[PATCH] serial: sh-sci: do not warn if DMA transfers are not supported

[Ulrich Hecht]

Not all (H)SCIF devices support DMA, and failure to set it up is not
normally a cause for concern. This patch demotes the associated warning to
debug output.

Inspired by BSP patch "sci: sh-sci: Fix transfer sequence of unsupport DMA
transfer" (6beb1f98d3bd30) by Hiromitsu Yamasaki.

Signed-off-by: Ulrich Hecht 
---
 drivers/tty/serial/sh-sci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 426241d..ff6ba6d 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -1516,7 +1516,7 @@ static struct dma_chan *sci_request_dma_chan(struct 
uart_port *port,
chan = dma_request_slave_channel(port->dev,
 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
if (!chan) {
-   dev_warn(port->dev, "dma_request_slave_channel failed\n");
+   dev_dbg(port->dev, "dma_request_slave_channel failed\n");
return NULL;
}
 
-- 
2.7.4

Re: [PATCH 0/2] serial: sh-sci: Use pm_runtime_get_sync()/put()

[Ulrich Hecht]

Sorry for the delay...

> On April 13, 2018 at 7:27 PM Geert Uytterhoeven  wrote:
> 
> On Fri, Apr 13, 2018 at 7:00 PM, Ulrich Hecht
>  wrote:
> > These patches make sure that the device is up while the suspend/resume code
> > is executed. Up-port from the BSP, tested not to break stuff.
> >
> > Hien Dang (2):
> >   serial: sh-sci: Use pm_runtime_get_sync()/put() on suspend
> >   serial: sh-sci: Use pm_runtime_get_sync()/put() on resume
> 
> I don't think it makes much sense to split this in two parts...
> 
> Furthermore, shouldn't this be handled by the serial core, calling
> uart_change_pm()?
> 
> It looks like uart_resume_port() already changes the port's state to
> enabled, while  uart_suspend_port() assumes the port is already enabled,
> and disables it.
> 
> Perhaps handling is not correct for some code paths?

The way I understand it, the problem this intends to fix is not the state the 
device ends up in, but that it needs to be powered while registers are read or 
written.

It seems to me that that the current "resume" code should work in that respect, 
because it changes the PM state to "on" in uart_resume_port() before any access 
to hardware registers takes place, so there is nothing that needs to be fixed.

That may be different for the "suspend" part, though, because it assumes that 
the PM state is "on", and I think that is what the patch asserts to not be a 
valid assumption anymore. It's hard to tell if that is true, though, because I 
cannot reproduce the issue here; it just works either way...

CU
Uli

Re: [RESEND PATCH] spi: sh-msiof: Document R-Car D3 support

[Ulrich Hecht]

> On September 4, 2018 at 9:20 AM Wolfram Sang  wrote:
> 
> 
> On Mon, Sep 03, 2018 at 12:02:19PM +0100, Mark Brown wrote:
> > On Mon, Sep 03, 2018 at 11:28:19AM +0200, Wolfram Sang wrote:
> > > On Fri, Aug 24, 2018 at 11:12:31AM +0200, Ulrich Hecht wrote:
> > 
> > > > This patch fell by the wayside, probably because I forgot to cc 
> > > > devicetree.
> > 
> > > Yeah, this is good practice. Yet, I'd think this goes upstream via the
> > > SPI tree? Ccing Mark, he prefers to be Cced explicitly.
> > 
> > Yes, if I don't get sent a copy of patches I'm not going to see them:
> > 
> > As documented in SubmittingPatches please send patches to the 
> > maintainers for the code you would like to change.  The normal kernel
> > workflow is that people apply patches from their inboxes, if they aren't
> > copied they are likely to not see the patch at all and it is much more
> > difficult to apply patches.
> 
> Uli, can you resend?

Geert has already done so, together with the corresponding change for E3.

CU
Uli

[RESEND PATCH] spi: sh-msiof: Document R-Car D3 support

[Ulrich Hecht]

Document support for the MSIOF module in the Renesas D3 (r8a77995) SoC.

No driver update is needed.

Signed-off-by: Ulrich Hecht 
Reviewed-by: Simon Horman 
Reviewed-by: Geert Uytterhoeven 
---
This patch fell by the wayside, probably because I forgot to cc devicetree.

CU
Uli


 Documentation/devicetree/bindings/spi/sh-msiof.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt 
b/Documentation/devicetree/bindings/spi/sh-msiof.txt
index bfbc203..fd15715 100644
--- a/Documentation/devicetree/bindings/spi/sh-msiof.txt
+++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt
@@ -11,6 +11,7 @@ Required properties:
 "renesas,msiof-r8a7795" (R-Car H3)
 "renesas,msiof-r8a7796" (R-Car M3-W)
 "renesas,msiof-r8a77965" (R-Car M3-N)
+"renesas,msiof-r8a77995" (R-Car D3)
 "renesas,msiof-sh73a0" (SH-Mobile AG5)
 "renesas,sh-mobile-msiof" (generic SH-Mobile 
compatibile device)
 "renesas,rcar-gen2-msiof" (generic R-Car Gen2 and 
RZ/G1 compatible device)
-- 
2.7.4

[PATCH 0/5] H3/M3-W cpuidle support

[Ulrich Hecht]

Hi!

This series adds CPU idle support for H3 and M3-W. It's a straight
up-port from the BSP.

The part that disables cpuidle for the CA53 cores on M3ULCB is a bit
dodgy. Is it a valid assumption that all M3ULCB boards have an ES1.0
SoC?

CU
Uli


Dien Pham (2):
  arm64: dts: r8a7795: Add cpuidle support for CA53 cores
  arm64: dts: r8a7796: Add cpuidle support for CA53 cores

Khiem Nguyen (2):
  arm64: dts: r8a7795: Add cpuidle support for CA57 cores
  arm64: dts: r8a7796: Add cpuidle support for CA57 cores

Takeshi Kihara (1):
  arm64: dts: r8a7796-m3ulcb: Disable cpuidle support for CA53 cores

 arch/arm64/boot/dts/renesas/r8a7795.dtsi   | 32 ++
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 22 ++
 arch/arm64/boot/dts/renesas/r8a7796.dtsi   | 30 
 3 files changed, 84 insertions(+)

-- 
2.7.4

[PATCH 3/5] arm64: dts: r8a7796: Add cpuidle support for CA57 cores

[Ulrich Hecht]

From: Khiem Nguyen 

Enable cpuidle (core shutdown) support for R-Car M3-W CA57 cores.

Parameters were found after evaluation by gaku.inami...@bp.renesas.com; they
help to keep the performance and reduce the power consumption.

Signed-off-by: Khiem Nguyen 
Signed-off-by: Takeshi Kihara 
[dien.pham.ry: Apply new cpuidle parameters]
Signed-off-by: Dien Pham 
Signed-off-by: Ulrich Hecht 
---
 arch/arm64/boot/dts/renesas/r8a7796.dtsi | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi 
b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 258a327..3d30b05 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -134,6 +134,7 @@
power-domains = < R8A7796_PD_CA57_CPU0>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
clocks =< CPG_CORE R8A7796_CLK_Z>;
operating-points-v2 = <_opp>;
#cooling-cells = <2>;
@@ -146,6 +147,7 @@
power-domains = < R8A7796_PD_CA57_CPU1>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
clocks =< CPG_CORE R8A7796_CLK_Z>;
operating-points-v2 = <_opp>;
#cooling-cells = <2>;
@@ -208,6 +210,20 @@
cache-unified;
cache-level = <2>;
};
+
+   idle-states {
+   entry-method = "psci";
+
+   CPU_SLEEP_0: cpu-sleep-0 {
+   compatible = "arm,idle-state";
+   arm,psci-suspend-param = <0x001>;
+   local-timer-stop;
+   entry-latency-us = <400>;
+   exit-latency-us = <500>;
+   min-residency-us = <4000>;
+   status = "okay";
+   };
+   };
};
 
extal_clk: extal {
-- 
2.7.4

[PATCH 1/5] arm64: dts: r8a7795: Add cpuidle support for CA57 cores

[Ulrich Hecht]

From: Khiem Nguyen 

Enable cpuidle (core shutdown) support for R-Car H3 CA57 cores.

Parameters were found after evaluation by gaku.inami...@bp.renesas.com; they
help to keep the performance and reduce the power consumption.

Signed-off-by: Khiem Nguyen 
[dien.pham.ry: Apply new cpuidle parameters]
Signed-off-by: Dien Pham 
Signed-off-by: Takeshi Kihara 
Signed-off-by: Ulrich Hecht 
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi 
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index efc2477..64ab88a 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -123,6 +123,7 @@
power-domains = < R8A7795_PD_CA57_CPU0>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
clocks =< CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
#cooling-cells = <2>;
@@ -135,6 +136,7 @@
power-domains = < R8A7795_PD_CA57_CPU1>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
clocks =< CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
#cooling-cells = <2>;
@@ -147,6 +149,7 @@
power-domains = < R8A7795_PD_CA57_CPU2>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
clocks =< CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
#cooling-cells = <2>;
@@ -159,6 +162,7 @@
power-domains = < R8A7795_PD_CA57_CPU3>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
clocks =< CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
#cooling-cells = <2>;
@@ -221,6 +225,20 @@
cache-unified;
cache-level = <2>;
};
+
+   idle-states {
+   entry-method = "psci";
+
+   CPU_SLEEP_0: cpu-sleep-0 {
+   compatible = "arm,idle-state";
+   arm,psci-suspend-param = <0x001>;
+   local-timer-stop;
+   entry-latency-us = <400>;
+   exit-latency-us = <500>;
+   min-residency-us = <4000>;
+   status = "okay";
+   };
+   };
};
 
extal_clk: extal {
-- 
2.7.4

[PATCH 4/5] arm64: dts: r8a7796: Add cpuidle support for CA53 cores

[Ulrich Hecht]

From: Dien Pham 

Enable cpuidle (core shutdown) support for R-Car M3-W CA53 cores.

Signed-off-by: Dien Pham 
Signed-off-by: Takeshi Kihara 
Signed-off-by: Ulrich Hecht 
---
 arch/arm64/boot/dts/renesas/r8a7796.dtsi | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi 
b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 3d30b05..0c0877e 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -160,6 +160,7 @@
power-domains = < R8A7796_PD_CA53_CPU0>;
next-level-cache = <_CA53>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_1>;
clocks =< CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <_opp>;
};
@@ -171,6 +172,7 @@
power-domains = < R8A7796_PD_CA53_CPU1>;
next-level-cache = <_CA53>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_1>;
clocks =< CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <_opp>;
};
@@ -182,6 +184,7 @@
power-domains = < R8A7796_PD_CA53_CPU2>;
next-level-cache = <_CA53>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_1>;
clocks =< CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <_opp>;
};
@@ -193,6 +196,7 @@
power-domains = < R8A7796_PD_CA53_CPU3>;
next-level-cache = <_CA53>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_1>;
clocks =< CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <_opp>;
};
@@ -223,6 +227,16 @@
min-residency-us = <4000>;
status = "okay";
};
+
+   CPU_SLEEP_1: cpu-sleep-1 {
+   compatible = "arm,idle-state";
+   arm,psci-suspend-param = <0x001>;
+   local-timer-stop;
+   entry-latency-us = <700>;
+   exit-latency-us = <700>;
+   min-residency-us = <5000>;
+   status = "okay";
+   };
};
};
 
-- 
2.7.4

[PATCH 5/5] arm64: dts: r8a7796-m3ulcb: Disable cpuidle support for CA53 cores

[Ulrich Hecht]

From: Takeshi Kihara 

The revision of the R8A7796 SoC on the M3ULCB board is ES1.0. This revision
can not use cpuidle for CA53 cores.

Therefore, this patch disables cpuidle support for CA53 cores.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Ulrich Hecht 
---
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts 
b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
index 9e4594c..cf96675 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -14,6 +14,12 @@
model = "Renesas M3ULCB board based on r8a7796";
compatible = "renesas,m3ulcb", "renesas,r8a7796";
 
+   cpus {
+   idle-states {
+   /delete-node/ cpu-sleep-1;
+   };
+   };
+
memory@4800 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
@@ -26,6 +32,22 @@
};
 };
 
+_0 {
+   /delete-property/ cpu-idle-states;
+};
+
+_1 {
+   /delete-property/ cpu-idle-states;
+};
+
+_2 {
+   /delete-property/ cpu-idle-states;
+};
+
+_3 {
+   /delete-property/ cpu-idle-states;
+};
+
  {
clocks = < CPG_MOD 724>,
 < CPG_MOD 723>,
-- 
2.7.4

[PATCH 2/5] arm64: dts: r8a7795: Add cpuidle support for CA53 cores

[Ulrich Hecht]

From: Dien Pham 

Enables cpuidle (core shutdown) support for R-Car H3 CA53 cores.

Signed-off-by: Dien Pham 
Signed-off-by: Takeshi Kihara 
Signed-off-by: Ulrich Hecht 
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi 
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 64ab88a..23f10d3 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -175,6 +175,7 @@
power-domains = < R8A7795_PD_CA53_CPU0>;
next-level-cache = <_CA53>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_1>;
clocks =< CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
};
@@ -186,6 +187,7 @@
power-domains = < R8A7795_PD_CA53_CPU1>;
next-level-cache = <_CA53>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_1>;
clocks =< CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
};
@@ -197,6 +199,7 @@
power-domains = < R8A7795_PD_CA53_CPU2>;
next-level-cache = <_CA53>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_1>;
clocks =< CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
};
@@ -208,6 +211,7 @@
power-domains = < R8A7795_PD_CA53_CPU3>;
next-level-cache = <_CA53>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_1>;
clocks =< CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
};
@@ -238,6 +242,16 @@
min-residency-us = <4000>;
status = "okay";
};
+
+   CPU_SLEEP_1: cpu-sleep-1 {
+   compatible = "arm,idle-state";
+   arm,psci-suspend-param = <0x001>;
+   local-timer-stop;
+   entry-latency-us = <700>;
+   exit-latency-us = <700>;
+   min-residency-us = <5000>;
+   status = "okay";
+   };
};
};
 
-- 
2.7.4

[PATCH 3/3] pinctrl: sh-pfc: r8a7796: Add I2C{0,3,5} pins, groups and functions

[Ulrich Hecht]

From: Takeshi Kihara 

This patch adds I2C{0,3,5} pins, groups and functions to the R8A7796 SoC.

These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Ulrich Hecht 
---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 100 ---
 1 file changed, 81 insertions(+), 19 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 3ea133c..d2ba65e 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -559,6 +559,9 @@ MOD_SEL0_4_3MOD_SEL1_4 \
FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) 
FM(EXTALR)
 
+#define PINMUX_PHYS \
+   FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
+
 enum {
PINMUX_RESERVED = 0,
 
@@ -584,11 +587,18 @@ enum {
PINMUX_IPSR
PINMUX_MOD_SELS
PINMUX_STATIC
+   PINMUX_PHYS
PINMUX_MARK_END,
 #undef F_
 #undef FM
 };
 
+#define PINMUX_IPSR_MSEL2(ipsr, fn, msel1, msel2) \
+   PINMUX_DATA(fn##_MARK, FN_##msel1, FN_##msel2, FN_##fn, FN_##ipsr)
+
+#define PINMUX_IPSR_PHYS(ipsr, fn, msel) \
+   PINMUX_DATA(fn##_MARK, FN_##msel)
+
 static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(),
 
@@ -620,13 +630,15 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C,   SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_15_12, TX4_A,  SEL_SCIF4_0),
 
-   PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A,   SEL_ETHERAVB_0),
-   PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C,   SEL_MSIOF2_2),
-   PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A,   SEL_SCIF4_0),
+   PINMUX_IPSR_MSEL2(IP0_19_16,AVB_AVTP_MATCH_A,   I2C_SEL_5_0, 
SEL_ETHERAVB_0),
+   PINMUX_IPSR_MSEL2(IP0_19_16,MSIOF2_RXD_C,   I2C_SEL_5_0, 
SEL_MSIOF2_2),
+   PINMUX_IPSR_MSEL2(IP0_19_16,CTS4_N_A,   I2C_SEL_5_0, 
SEL_SCIF4_0),
+   PINMUX_IPSR_PHYS(IP0_19_16, SCL5,   I2C_SEL_5_1),
 
-   PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
-   PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C,   SEL_MSIOF2_2),
-   PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A,   SEL_SCIF4_0),
+   PINMUX_IPSR_MSEL2(IP0_23_20,AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, 
SEL_ETHERAVB_0),
+   PINMUX_IPSR_MSEL2(IP0_23_20,MSIOF2_TXD_C,   I2C_SEL_5_0, 
SEL_MSIOF2_2),
+   PINMUX_IPSR_MSEL2(IP0_23_20,RTS4_N_A,   I2C_SEL_5_0, 
SEL_SCIF4_0),
+   PINMUX_IPSR_PHYS(IP0_23_20, SDA5,   I2C_SEL_5_1),
 
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
@@ -678,14 +690,16 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B,SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B,SEL_IEBUS_1),
 
-   PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
-   PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
-   PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B,SEL_VIN4_1),
-   PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
+   PINMUX_IPSR_MSEL2(IP1_23_20,PWM1_A, I2C_SEL_3_0,
SEL_PWM1_0),
+   PINMUX_IPSR_MSEL2(IP1_23_20,HRX3_D, I2C_SEL_3_0,
SEL_HSCIF3_3),
+   PINMUX_IPSR_MSEL2(IP1_23_20,VI4_DATA7_B,I2C_SEL_3_0,
SEL_VIN4_1),
+   PINMUX_IPSR_MSEL2(IP1_23_20,IERX_B, I2C_SEL_3_0,
SEL_IEBUS_1),
+   PINMUX_IPSR_PHYS(IP0_23_20, SCL3,   I2C_SEL_3_1),
 
-   PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
-   PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
-   PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
+   PINMUX_IPSR_MSEL2(IP1_27_24,PWM2_A, I2C_SEL_3_0,
SEL_PWM2_0),
+   PINMUX_IPSR_MSEL2(IP1_27_24,HTX3_D, I2C_SEL_3_0,
SEL_HSCIF3_3),
+   PINMUX_IPSR_MSEL2(IP1_27_24,IETX_B, I2C_SEL_3_0,
SEL_IEBUS_1),
+   PINMUX_IPSR_PHYS(IP1_27_24, SDA3,   I2C_SEL_3_1),
 
PINMUX_IPSR_GPSR(IP1_31_28, A0),
PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
@@ -1118,13 +1132,15 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP11_15_12,NFDATA15_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_15_12,SDA2_B, SEL_I2C2_1),
 
-   PINMUX_IPSR_GPSR(IP11_19_16,SD1_CD),
-   PINMUX_IPSR_MSEL(IP11_19_16,NFRB_N_A,   SEL_NDFC_0),
-   PINMUX_IPSR_MSEL(IP11_19_16,SIM0_CLK_B, SEL_SIMCARD_1),
+   PINMUX_IPSR_MSEL(IP11_19_16,SD1_CD

[PATCH 1/3] pinctrl: sh-pfc: r8a7795: Add I2C{0,3,5} pins, groups and functions

[Ulrich Hecht]

From: Takeshi Kihara 

This patch adds I2C{0,3,5} pins, groups and functions to the R8A7795 SoC.

These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Ulrich Hecht 
---
 drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 101 +++
 1 file changed, 80 insertions(+), 21 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 4f55b15..285cb97 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -553,6 +553,9 @@ MOD_SEL0_4_3MOD_SEL1_4 \
FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) 
FM(EXTALR)
 
+#define PINMUX_PHYS \
+   FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
+
 enum {
PINMUX_RESERVED = 0,
 
@@ -578,11 +581,18 @@ enum {
PINMUX_IPSR
PINMUX_MOD_SELS
PINMUX_STATIC
+   PINMUX_PHYS
PINMUX_MARK_END,
 #undef F_
 #undef FM
 };
 
+#define PINMUX_IPSR_MSEL2(ipsr, fn, msel1, msel2) \
+   PINMUX_DATA(fn##_MARK, FN_##msel1, FN_##msel2, FN_##fn, FN_##ipsr)
+
+#define PINMUX_IPSR_PHYS(ipsr, fn, msel) \
+   PINMUX_DATA(fn##_MARK, FN_##msel)
+
 static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(),
 
@@ -591,9 +601,6 @@ static const u16 pinmux_data[] = {
PINMUX_SINGLE(CLKOUT),
PINMUX_SINGLE(HDMI0_CEC),
PINMUX_SINGLE(HDMI1_CEC),
-   PINMUX_SINGLE(I2C_SEL_0_1),
-   PINMUX_SINGLE(I2C_SEL_3_1),
-   PINMUX_SINGLE(I2C_SEL_5_1),
PINMUX_SINGLE(MSIOF0_RXD),
PINMUX_SINGLE(MSIOF0_SCK),
PINMUX_SINGLE(MSIOF0_TXD),
@@ -617,14 +624,16 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C,   SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_15_12, TX4_A,  SEL_SCIF4_0),
 
-   PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A,   SEL_ETHERAVB_0),
-   PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C,   SEL_MSIOF2_2),
-   PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A,   SEL_SCIF4_0),
-   PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
+   PINMUX_IPSR_MSEL2(IP0_19_16,AVB_AVTP_MATCH_A,   I2C_SEL_5_0, 
SEL_ETHERAVB_0),
+   PINMUX_IPSR_MSEL2(IP0_19_16,MSIOF2_RXD_C,   I2C_SEL_5_0, 
SEL_MSIOF2_2),
+   PINMUX_IPSR_MSEL2(IP0_19_16,CTS4_N_A,   I2C_SEL_5_0, 
SEL_SCIF4_0),
+   PINMUX_IPSR_MSEL(IP0_19_16, FSCLKST2_N_A,   I2C_SEL_5_0),
+   PINMUX_IPSR_PHYS(IP0_19_16, SCL5,   I2C_SEL_5_1),
 
-   PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
-   PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C,   SEL_MSIOF2_2),
-   PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A,   SEL_SCIF4_0),
+   PINMUX_IPSR_MSEL2(IP0_23_20,AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, 
SEL_ETHERAVB_0),
+   PINMUX_IPSR_MSEL2(IP0_23_20,MSIOF2_TXD_C,   I2C_SEL_5_0, 
SEL_MSIOF2_2),
+   PINMUX_IPSR_MSEL2(IP0_23_20,RTS4_N_A,   I2C_SEL_5_0, 
SEL_SCIF4_0),
+   PINMUX_IPSR_PHYS(IP0_23_20, SDA5,   I2C_SEL_5_1),
 
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
@@ -677,14 +686,16 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B,SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B,SEL_IEBUS_1),
 
-   PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
-   PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
-   PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B,SEL_VIN4_1),
-   PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
+   PINMUX_IPSR_MSEL2(IP1_23_20,PWM1_A, I2C_SEL_3_0, 
SEL_PWM1_0),
+   PINMUX_IPSR_MSEL2(IP1_23_20,HRX3_D, I2C_SEL_3_0, 
SEL_HSCIF3_3),
+   PINMUX_IPSR_MSEL2(IP1_23_20,VI4_DATA7_B,I2C_SEL_3_0, 
SEL_VIN4_1),
+   PINMUX_IPSR_MSEL2(IP1_23_20,IERX_B, I2C_SEL_3_0, 
SEL_IEBUS_1),
+   PINMUX_IPSR_PHYS(IP0_23_20, SCL3,   I2C_SEL_3_1),
 
-   PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
-   PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
-   PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
+   PINMUX_IPSR_MSEL2(IP1_27_24,PWM2_A, I2C_SEL_3_0, 
SEL_PWM2_0),
+   PINMUX_IPSR_MSEL2(IP1_27_24,HTX3_D, I2C_SEL_3_0, 
SEL_HSCIF3_3),
+   PINMUX_IPSR_MSEL2(IP1_27_24,IETX_B, I2C_SEL_3_0, 
SEL_IEBUS_1),
+   PINMUX_IPSR_PHYS(IP1_27_24, SDA3,   I2C_SEL_3_1

[PATCH 2/3] pinctrl: sh-pfc: r8a7795-es1: Add I2C{0,3,5} pins, groups and functions

[Ulrich Hecht]

From: Takeshi Kihara 

This patch adds I2C{0,3,5} pins, groups and functions to
the R8A7795 ES1.x SoC.

These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Ulrich Hecht 
---
 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 103 ---
 1 file changed, 81 insertions(+), 22 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
index a6c5d50..b3aee4c 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
@@ -540,6 +540,9 @@ MOD_SEL0_2_1MOD_SEL1_2 \
FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) 
FM(EXTALR)
 
+#define PINMUX_PHYS \
+   FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
+
 enum {
PINMUX_RESERVED = 0,
 
@@ -565,11 +568,18 @@ enum {
PINMUX_IPSR
PINMUX_MOD_SELS
PINMUX_STATIC
+   PINMUX_PHYS
PINMUX_MARK_END,
 #undef F_
 #undef FM
 };
 
+#define PINMUX_IPSR_MSEL2(ipsr, fn, msel1, msel2) \
+   PINMUX_DATA(fn##_MARK, FN_##msel1, FN_##msel2, FN_##fn, FN_##ipsr)
+
+#define PINMUX_IPSR_PHYS(ipsr, fn, msel) \
+   PINMUX_DATA(fn##_MARK, FN_##msel)
+
 static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(),
 
@@ -577,9 +587,6 @@ static const u16 pinmux_data[] = {
PINMUX_SINGLE(AVS2),
PINMUX_SINGLE(HDMI0_CEC),
PINMUX_SINGLE(HDMI1_CEC),
-   PINMUX_SINGLE(I2C_SEL_0_1),
-   PINMUX_SINGLE(I2C_SEL_3_1),
-   PINMUX_SINGLE(I2C_SEL_5_1),
PINMUX_SINGLE(MSIOF0_RXD),
PINMUX_SINGLE(MSIOF0_SCK),
PINMUX_SINGLE(MSIOF0_TXD),
@@ -611,13 +618,15 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C,   SEL_MSIOF2_2),
PINMUX_IPSR_MSEL(IP0_15_12, TX4_A,  SEL_SCIF4_0),
 
-   PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A,   SEL_ETHERAVB_0),
-   PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C,   SEL_MSIOF2_2),
-   PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A,   SEL_SCIF4_0),
+   PINMUX_IPSR_MSEL2(IP0_19_16,AVB_AVTP_MATCH_A,   I2C_SEL_5_0, 
SEL_ETHERAVB_0),
+   PINMUX_IPSR_MSEL2(IP0_19_16,MSIOF2_RXD_C,   I2C_SEL_5_0, 
SEL_MSIOF2_2),
+   PINMUX_IPSR_MSEL2(IP0_19_16,CTS4_N_A,   I2C_SEL_5_0, 
SEL_SCIF4_0),
+   PINMUX_IPSR_PHYS(IP0_19_16, SCL5,   I2C_SEL_5_1),
 
-   PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
-   PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C,   SEL_MSIOF2_2),
-   PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A,  SEL_SCIF4_0),
+   PINMUX_IPSR_MSEL2(IP0_23_20,AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, 
SEL_ETHERAVB_0),
+   PINMUX_IPSR_MSEL2(IP0_23_20,MSIOF2_TXD_C,   I2C_SEL_5_0, 
SEL_MSIOF2_2),
+   PINMUX_IPSR_MSEL2(IP0_23_20,RTS4_N_TANS_A,  I2C_SEL_5_0, 
SEL_SCIF4_0),
+   PINMUX_IPSR_PHYS(IP0_23_20, SDA5,   I2C_SEL_5_1),
 
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
@@ -667,16 +676,18 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B,SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B,SEL_IEBUS_1),
 
-   PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
-   PINMUX_IPSR_GPSR(IP1_23_20, A21),
-   PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
-   PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B,SEL_VIN4_1),
-   PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
+   PINMUX_IPSR_MSEL2(IP1_23_20,PWM1_A, I2C_SEL_3_0,
SEL_PWM1_0),
+   PINMUX_IPSR_MSEL(IP1_23_20, A21,I2C_SEL_3_0),
+   PINMUX_IPSR_MSEL2(IP1_23_20,HRX3_D, I2C_SEL_3_0,
SEL_HSCIF3_3),
+   PINMUX_IPSR_MSEL2(IP1_23_20,VI4_DATA7_B,I2C_SEL_3_0,
SEL_VIN4_1),
+   PINMUX_IPSR_MSEL2(IP1_23_20,IERX_B, I2C_SEL_3_0,
SEL_IEBUS_1),
+   PINMUX_IPSR_PHYS(IP0_23_20, SCL3,   I2C_SEL_3_1),
 
-   PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
-   PINMUX_IPSR_GPSR(IP1_27_24, A20),
-   PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
-   PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
+   PINMUX_IPSR_MSEL2(IP1_27_24,PWM2_A, I2C_SEL_3_0,
SEL_PWM2_0),
+   PINMUX_IPSR_MSEL(IP1_27_24, A20,I2C_SEL_3_0),
+   PINMUX_IPSR_MSEL2(IP1_27_24,HTX3_D, I2C_SEL_3_0,
SEL_HSCIF3_3),
+   PINMUX_IPSR_MSEL2(IP1_27_24,IETX_B, I2C_SEL_3_0,
SEL_IEBUS_1

[PATCH 0/3] I2C0/3/5 pin control for H3 and M3-W

[Ulrich Hecht]

Hi!

This is an up-port from the BSP. Unfortunately I could not test these
because none of those pins seem to be accessible on Salvator boards (not on
ULCB either, AFAICT), so the best thing I can say is that they don't seem to
break anything.

CU
Uli


Takeshi Kihara (3):
  pinctrl: sh-pfc: r8a7795: Add I2C{0,3,5} pins, groups and functions
  pinctrl: sh-pfc: r8a7795-es1: Add I2C{0,3,5} pins, groups and
functions
  pinctrl: sh-pfc: r8a7796: Add I2C{0,3,5} pins, groups and functions

 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 103 ---
 drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 101 +++---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 100 --
 3 files changed, 242 insertions(+), 62 deletions(-)

-- 
2.7.4

Re: [PATCH 2/2] i2c: rcar: implement STOP and REP_START according to docs

[Ulrich Hecht]

Thank you for your patch.

> On August 8, 2018 at 9:59 AM Wolfram Sang  
> wrote:
> 
> 
> When doing a REP_START after a read message, the driver used to trigger
> a STOP first which would then be overwritten by REP_START. This was the
> only stable method found when doing the last refactoring. However, this
> was not in accordance with the documentation.
> 
> After research from our BSP team and myself, we now can implement a
> version which works and is according to the documentation. The new
> approach ensures the ICMCR register is only changed when really needed.
> 
> Tested on a R-Car Gen2 (H2) and Gen3 with DMA (M3N).
> 
> Signed-off-by: Hiromitsu Yamasaki 
> Signed-off-by: Wolfram Sang 
> ---
>  drivers/i2c/busses/i2c-rcar.c | 34 --
>  1 file changed, 20 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
> index a9f1880e2eae..43ad933df0f0 100644
> --- a/drivers/i2c/busses/i2c-rcar.c
> +++ b/drivers/i2c/busses/i2c-rcar.c
> @@ -113,9 +113,10 @@
>  #define ID_ARBLOST   (1 << 3)
>  #define ID_NACK  (1 << 4)
>  /* persistent flags */
> +#define ID_P_REP_AFTER_RDBIT(29)
>  #define ID_P_NO_RXDMABIT(30) /* HW forbids RXDMA sometimes */
>  #define ID_P_PM_BLOCKED  BIT(31)
> -#define ID_P_MASKGENMASK(31, 30)
> +#define ID_P_MASKGENMASK(31, 29)
>  
>  enum rcar_i2c_type {
>   I2C_RCAR_GEN1,
> @@ -345,7 +346,10 @@ static void rcar_i2c_prepare_msg(struct rcar_i2c_priv 
> *priv)
>   rcar_i2c_write(priv, ICMSR, 0);
>   rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
>   } else {
> - rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
> + if (priv->flags & ID_P_REP_AFTER_RD)
> + priv->flags &= ~ID_P_REP_AFTER_RD;
> + else
> + rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
>   rcar_i2c_write(priv, ICMSR, 0);
>   }
>   rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
> @@ -550,15 +554,15 @@ static void rcar_i2c_irq_recv(struct rcar_i2c_priv 
> *priv, u32 msr)
>   priv->pos++;
>   }
>  
> - /*
> -  * If next received data is the _LAST_, go to STOP phase. Might be
> -  * overwritten by REP START when setting up a new msg. Not elegant
> -  * but the only stable sequence for REP START I have found so far.
> -  * If you want to change this code, make sure sending one transfer with
> -  * four messages (WR-RD-WR-RD) works!
> -  */
> - if (priv->pos + 1 >= msg->len)
> - rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
> + /* If next received data is the _LAST_, go to new phase. */
> + if (priv->pos + 1 == msg->len) {
> + if (priv->flags & ID_LAST_MSG) {
> + rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
> + } else {
> + rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
> + priv->flags |= ID_P_REP_AFTER_RD;
> + }
> + }

So "priv->pos + 1 <= msg->len" is an invariant? (The current code seems to 
imply that it isn't.)

If it is,
Reviewed-by: Ulrich Hecht 

CU
Uli

Re: [PATCH 1/2] i2c: rcar: refactor private flags

[Ulrich Hecht]

> On August 8, 2018 at 9:59 AM Wolfram Sang  
> wrote:
> 
> 
> Use BIT macro to avoid shift-31-problem, indent a little more and use
> GENMASK to make it easier to add new flags.
> 
> Signed-off-by: Wolfram Sang 
> ---
>  drivers/i2c/busses/i2c-rcar.c | 7 ---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
> index 791a4aa34fdd..a9f1880e2eae 100644
> --- a/drivers/i2c/busses/i2c-rcar.c
> +++ b/drivers/i2c/busses/i2c-rcar.c
> @@ -19,6 +19,7 @@
>   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>   * GNU General Public License for more details.
>   */
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -112,9 +113,9 @@
>  #define ID_ARBLOST   (1 << 3)
>  #define ID_NACK  (1 << 4)
>  /* persistent flags */
> -#define ID_P_NO_RXDMA(1 << 30) /* HW forbids RXDMA sometimes */
> -#define ID_P_PM_BLOCKED  (1 << 31)
> -#define ID_P_MASK(ID_P_PM_BLOCKED | ID_P_NO_RXDMA)
> +#define ID_P_NO_RXDMABIT(30) /* HW forbids RXDMA sometimes */
> +#define ID_P_PM_BLOCKED  BIT(31)
> +#define ID_P_MASKGENMASK(31, 30)
>  
>  enum rcar_i2c_type {
>   I2C_RCAR_GEN1,
> -- 
> 2.11.0
>

Reviewed-by: Ulrich Hecht 

CU
Uli

Re: [PATCH] i2c: recovery: make pin init look like STOP

[Ulrich Hecht]

On Thu, Jul 12, 2018 at 7:49 PM, Wolfram Sang
 wrote:
> When we we initialize the pins, make sure it looks like STOP by dividing
> the delay into halves. It shouldn't matter because SDA is expected to be
> held low by a device,

Yeah, what could possibly go wrong? :)

>
> Signed-off-by: Wolfram Sang 
> ---
>  drivers/i2c/i2c-core-base.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c
> index 51cbb0c158f2..e57231ccb32a 100644
> --- a/drivers/i2c/i2c-core-base.c
> +++ b/drivers/i2c/i2c-core-base.c
> @@ -191,9 +191,10 @@ int i2c_generic_scl_recovery(struct i2c_adapter *adap)
> bri->prepare_recovery(adap);
>
> bri->set_scl(adap, scl);
> +   ndelay(RECOVERY_NDELAY / 2);
> if (bri->set_sda)
> -   bri->set_sda(adap, 1);
> -   ndelay(RECOVERY_NDELAY);
> +   bri->set_sda(adap, scl);
> +   ndelay(RECOVERY_NDELAY / 2);
>
> /*
>  * By this time SCL is high, as we need to give 9 falling-rising edges
> --
> 2.11.0
>

Reviewed-by: Ulrich Hecht 

CU
Uli

Re: [PATCH v3 2/2] arm64: dts: renesas: condor/v3hsk: add DU/LVDS/HDMI support

[Ulrich Hecht]

On Mon, Jul 16, 2018 at 9:53 AM, Simon Horman  wrote:
> On Thu, Jun 14, 2018 at 09:24:27AM +0200, Simon Horman wrote:
>> On Wed, Jun 13, 2018 at 11:12:40PM +0300, Sergei Shtylyov wrote:
>> > Define the Condor/V3HSK board dependent parts of the DU and  LVDS device
>> > nodes. Also add the device nodes for Thine THC63LVD1024 LVDS decoder and
>> > Analog Devices ADV7511W HDMI transmitter...
>> >
>> > Based on the original (and large) patch by Vladimir Barinov.
>> >
>> > Signed-off-by: Vladimir Barinov 
>> > Signed-off-by: Sergei Shtylyov 
>> >
>> > ---
>> > Changes in version 2:
>> > - added the V3HSK DT update, reworded the description, renamed the patch;
>> > - added a space between the HDMI node name and a brace.
>> >
>> >  arch/arm64/boot/dts/renesas/r8a77980-condor.dts |  106 
>> > +
>> >  arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts  |  120 
>> > 
>>
>> Laurent, could you review this?
>
> Ping

For the Condor part:

Reviewed-by: Ulrich Hecht 

Unfortunately, I do not have documentation for the other board.

CU
Uli

[PATCH v2 2/2] spi: sh-msiof: Document R-Car D3 support

[Ulrich Hecht]

Document support for the MSIOF module in the Renesas D3 (r8a77995) SoC.

No driver update is needed.

Signed-off-by: Ulrich Hecht 
Reviewed-by: Simon Horman 
Reviewed-by: Geert Uytterhoeven 
---
Added Reviewed-bys.

CU
Uli


 Documentation/devicetree/bindings/spi/sh-msiof.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt 
b/Documentation/devicetree/bindings/spi/sh-msiof.txt
index 3980632..914036d 100644
--- a/Documentation/devicetree/bindings/spi/sh-msiof.txt
+++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt
@@ -11,6 +11,7 @@ Required properties:
 "renesas,msiof-r8a7795" (R-Car H3)
 "renesas,msiof-r8a7796" (R-Car M3-W)
 "renesas,msiof-r8a77965" (R-Car M3-N)
+"renesas,msiof-r8a77995" (R-Car D3)
 "renesas,msiof-sh73a0" (SH-Mobile AG5)
 "renesas,sh-mobile-msiof" (generic SH-Mobile 
compatibile device)
 "renesas,rcar-gen2-msiof" (generic R-Car Gen2 and 
RZ/G1 compatible device)
-- 
2.7.4

[PATCH resend] dmaengine: rcar-dmac: Document R8A77990 bindings

[Ulrich Hecht]

From: Hiroyuki Yokoyama 

Renesas R-Car E3 (R8A77990) SoC also has the R-Car gen2/3 compatible DMA
controllers, so document the SoC specific binding.

Signed-off-by: Hiroyuki Yokoyama 
Signed-off-by: Ulrich Hecht 
Reviewed-by: Simon Horman 
Acked-by: Rob Herring 
Reviewed-by: Geert Uytterhoeven 
---
This didn't apply for Vinod before, but now it seems to. If it still does
not, please tell me what tree to base this on.

CU
Uli


 Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt 
b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
index b1ba6395..946229c 100644
--- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
+++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
@@ -29,6 +29,7 @@ Required Properties:
- "renesas,dmac-r8a77965" (R-Car M3-N)
- "renesas,dmac-r8a77970" (R-Car V3M)
- "renesas,dmac-r8a77980" (R-Car V3H)
+   - "renesas,dmac-r8a77990" (R-Car E3)
- "renesas,dmac-r8a77995" (R-Car D3)
 
 - reg: base address and length of the registers block for the DMAC
-- 
2.7.4

[PATCH v2 1/2] arm64: dts: r8a77995: Add MSIOF device nodes

[Ulrich Hecht]

From: Hiromitsu Yamasaki 

This patch adds MSIOF device nodes for the R8A77995 SoC.

Signed-off-by: Hiromitsu Yamasaki 
Signed-off-by: Takeshi Kihara 
[uli: remove unimplemented ref clock, clock-names]
Signed-off-by: Ulrich Hecht 
---
Removed clock-names and fixed the number formatting. Thanks to Geert
and Simon for the review.

CU
Uli


 arch/arm64/boot/dts/renesas/r8a77995.dtsi | 62 +++
 1 file changed, 62 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index eb23c85..a5c8d4a 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -798,6 +798,68 @@
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
};
+
+   msiof0: spi@e6e9 {
+   compatible = "renesas,msiof-r8a77995",
+"renesas,rcar-gen3-msiof";
+   reg = <0 0xe6e9 0 0x64>;
+   interrupts = ;
+   clocks = < CPG_MOD 211>;
+   dmas = < 0x41>, < 0x40>,
+  < 0x41>, < 0x40>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < R8A77995_PD_ALWAYS_ON>;
+   resets = < 211>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   msiof1: spi@e6ea {
+   compatible = "renesas,msiof-r8a77995",
+"renesas,rcar-gen3-msiof";
+   reg = <0 0xe6ea 0 0x64>;
+   interrupts = ;
+   clocks = < CPG_MOD 210>;
+   dmas = < 0x43>, < 0x42>,
+  < 0x43>, < 0x42>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < R8A77995_PD_ALWAYS_ON>;
+   resets = < 210>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   msiof2: spi@e6c0 {
+   compatible = "renesas,msiof-r8a77995",
+"renesas,rcar-gen3-msiof";
+   reg = <0 0xe6c0 0 0x64>;
+   interrupts = ;
+   clocks = < CPG_MOD 209>;
+   dmas = < 0x45>, < 0x44>;
+   dma-names = "tx", "rx";
+   power-domains = < R8A77995_PD_ALWAYS_ON>;
+   resets = < 209>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   msiof3: spi@e6c1 {
+   compatible = "renesas,msiof-r8a77995",
+"renesas,rcar-gen3-msiof";
+   reg = <0 0xe6c1 0 0x64>;
+   interrupts = ;
+   clocks = < CPG_MOD 208>;
+   dmas = < 0x47>, < 0x46>;
+   dma-names = "tx", "rx";
+   power-domains = < R8A77995_PD_ALWAYS_ON>;
+   resets = < 208>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
};
 
thermal-zones {
-- 
2.7.4

Re: [PATCH 1/2] arm64: dts: r8a77995: Add MSIOF device nodes

[Ulrich Hecht]

On Thu, May 17, 2018 at 9:56 AM, Wolfram Sang <w...@the-dreams.de> wrote:
> On Wed, May 16, 2018 at 03:05:15PM +0200, Ulrich Hecht wrote:
>> From: Hiromitsu Yamasaki <hiromitsu.yamasaki...@renesas.com>
>>
>> This patch adds MSIOF device nodes for the R8A77995 SoC.
>>
>> Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki...@renesas.com>
>> Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
>> [uli: remove unimplemented ref clock]
>> Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
>
> Thanks, Uli!
>
> For the record: can you describe shortly which of these got tested with
> what setup? I don't know the Draak, so I don't know what is exposed.

MSIOF2 is conveniently hooked up to a 1x4 pin header (CN41), no
weird-ass Samtec connectors required. My testing covered sending some
data using spidev_test and watching the output on an oscilloscope
attached to MSIOF2_TXD (pin 3). Looks plausible.

CU
Uli

Re: [PATCH/RFT v3 0/3] thermal: add support for r8a77995

[Ulrich Hecht]

On Wed, Apr 11, 2018 at 11:01 AM, jacopo mondi <jac...@jmondi.org> wrote:
> Hello Kaneko-san,
>
> On Tue, Apr 03, 2018 at 09:43:02PM +0900, Yoshihiro Kaneko wrote:
>> This series adds thermal support for r8a77995.
>> R-Car D3 (r8a77995) have a thermal sensor module which is similar to Gen2.
>> Therefore this series adds r8a77995 support to rcar_thermal driver not
>> rcar_gen3_thermal driver.
>
> I tested this on D3 Draak.
>
> I generated load expecting the detected temperature to rise.
>
> It took a while, and I only see a slight increase of the temperature
> reported by the 'temp' attribute.

Pointing a heat gun at the SoC, I managed to get the temperature up to
8, and it went back to 40000 when I removed it. I'd say this
works.

Tested-By: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>

CU
Uli

Re: [PATCH 2/5] drm: rcar-du: lvds: Add R8A77995 support

[Ulrich Hecht]

On Wed, May 16, 2018 at 10:59 AM, Sergei Shtylyov
<sergei.shtyl...@cogentembedded.com> wrote:
> Hello!
>
> On 5/16/2018 10:54 AM, Simon Horman wrote:
>
>>> Add support for the R-Car D3 (R8A77995) SoC to the LVDS encoder driver.
>>>
>>> Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
>>> ---
>>>   drivers/gpu/drm/rcar-du/rcar_lvds.c | 6 ++
>>>   1 file changed, 6 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c
>>> b/drivers/gpu/drm/rcar-du/rcar_lvds.c
>>> index 3d2d3bb..58fb9f8 100644
>>> --- a/drivers/gpu/drm/rcar-du/rcar_lvds.c
>>> +++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c
>>> @@ -511,6 +511,11 @@ static const struct rcar_lvds_device_info
>>> rcar_lvds_r8a77970_info = {
>>> .quirks = RCAR_LVDS_QUIRK_GEN2_PLLCR | RCAR_LVDS_QUIRK_GEN3_LVEN,
>>>   };
>>>   +static const struct rcar_lvds_device_info rcar_lvds_r8a77995_info = {
>>> +   .gen = 3,
>>> +   .quirks = RCAR_LVDS_QUIRK_GEN3_LVEN,
>>> +};
>>
>>
>> This new structure seems to be identical to rcar_lvds_r8a77970_info.
>
>> Could we consolidate somehow?
>
>In my book, that one has 2 quirk flags. What tree are you looking at?

IIRC the other one was for the PLL, which is not supported yet.

CU
Uli

[PATCH 1/2] dmaengine: usb-dmac: Document R8A7799{0,5} bindings

[Ulrich Hecht]

From: Hiroyuki Yokoyama <hiroyuki.yokoyama...@renesas.com>

Renesas R-Car D3 (R8A77995) and E3 (R8A77990) SoCs also have the R-Car
gen2/3 compatible DMA controllers, so document the SoC specific binding.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama...@renesas.com>
[uli: squashed]
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt 
b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt
index 9dc935e..482e543 100644
--- a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt
+++ b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt
@@ -12,6 +12,8 @@ Required Properties:
  - "renesas,r8a7795-usb-dmac" (R-Car H3)
  - "renesas,r8a7796-usb-dmac" (R-Car M3-W)
  - "renesas,r8a77965-usb-dmac" (R-Car M3-N)
+ - "renesas,r8a77990-usb-dmac" (R-Car E3)
+ - "renesas,r8a77995-usb-dmac" (R-Car D3)
 - reg: base address and length of the registers block for the DMAC
 - interrupts: interrupt specifiers for the DMAC, one for each entry in
   interrupt-names.
-- 
2.7.4

[PATCH 2/2] dmaengine: rcar-dmac: Document R8A77990 bindings

[Ulrich Hecht]

From: Hiroyuki Yokoyama <hiroyuki.yokoyama...@renesas.com>

Renesas R-Car E3 (R8A77990) SoC also has the R-Car gen2/3 compatible DMA
controllers, so document the SoC specific binding.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama...@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt 
b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
index b1ba6395..946229c 100644
--- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
+++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
@@ -29,6 +29,7 @@ Required Properties:
- "renesas,dmac-r8a77965" (R-Car M3-N)
- "renesas,dmac-r8a77970" (R-Car V3M)
- "renesas,dmac-r8a77980" (R-Car V3H)
+   - "renesas,dmac-r8a77990" (R-Car E3)
- "renesas,dmac-r8a77995" (R-Car D3)
 
 - reg: base address and length of the registers block for the DMAC
-- 
2.7.4

[PATCH] arm64: dts: r8a77995: Add SCIF-{0,1,3,4,5} device nodes

[Ulrich Hecht]

From: Takeshi Kihara <takeshi.kihara...@renesas.com>

This patch adds the device nodes for SCIF-{0,1,3,4,5} serial ports,
incl. clocks and power domain.

Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 arch/arm64/boot/dts/renesas/r8a77995.dtsi | 70 +++
 1 file changed, 70 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index 4b05dc2..73d6589 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -628,6 +628,34 @@
status = "disabled";
};
 
+   scif0: serial@e6e6 {
+   compatible = "renesas,scif-r8a77995",
+"renesas,rcar-gen3-scif", "renesas,scif";
+   reg = <0 0xe6e6 0 64>;
+   interrupts = ;
+   clocks = < CPG_MOD 207>,
+< CPG_CORE R8A77995_CLK_S3D1>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   power-domains = < R8A77995_PD_ALWAYS_ON>;
+   resets = < 207>;
+   status = "disabled";
+   };
+
+   scif1: serial@e6e68000 {
+   compatible = "renesas,scif-r8a77995",
+"renesas,rcar-gen3-scif", "renesas,scif";
+   reg = <0 0xe6e68000 0 64>;
+   interrupts = ;
+   clocks = < CPG_MOD 206>,
+< CPG_CORE R8A77995_CLK_S3D1>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   power-domains = < R8A77995_PD_ALWAYS_ON>;
+   resets = < 206>;
+   status = "disabled";
+   };
+
scif2: serial@e6e88000 {
compatible = "renesas,scif-r8a77995",
 "renesas,rcar-gen3-scif", "renesas,scif";
@@ -645,6 +673,48 @@
status = "disabled";
};
 
+   scif3: serial@e6c5 {
+   compatible = "renesas,scif-r8a77995",
+"renesas,rcar-gen3-scif", "renesas,scif";
+   reg = <0 0xe6c5 0 64>;
+   interrupts = ;
+   clocks = < CPG_MOD 204>,
+< CPG_CORE R8A77995_CLK_S3D1>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   power-domains = < R8A77995_PD_ALWAYS_ON>;
+   resets = < 204>;
+   status = "disabled";
+   };
+
+   scif4: serial@e6c4 {
+   compatible = "renesas,scif-r8a77995",
+"renesas,rcar-gen3-scif", "renesas,scif";
+   reg = <0 0xe6c4 0 64>;
+   interrupts = ;
+   clocks = < CPG_MOD 203>,
+< CPG_CORE R8A77995_CLK_S3D1>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   power-domains = < R8A77995_PD_ALWAYS_ON>;
+   resets = < 203>;
+   status = "disabled";
+   };
+
+   scif5: serial@e6f3 {
+   compatible = "renesas,scif-r8a77995",
+"renesas,rcar-gen3-scif", "renesas,scif";
+   reg = <0 0xe6f3 0 64>;
+   interrupts = ;
+   clocks = < CPG_MOD 202>,
+< CPG_CORE R8A77995_CLK_S3D1>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   power-domains = < R8A77995_PD_ALWAYS_ON>;
+   resets = < 202>;
+   status = "disabled";
+   };
+
vin4: video@e6ef4000 {
compatible = "renesas,vin-r8a77995";
reg = <0 0xe6ef4000 0 0x1000>;
-- 
2.7.4

[PATCH 1/2] arm64: dts: r8a77995: Add MSIOF device nodes

[Ulrich Hecht]

From: Hiromitsu Yamasaki <hiromitsu.yamasaki...@renesas.com>

This patch adds MSIOF device nodes for the R8A77995 SoC.

Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki...@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
[uli: remove unimplemented ref clock]
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 arch/arm64/boot/dts/renesas/r8a77995.dtsi | 66 +++
 1 file changed, 66 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index 2506f46..2f712ac 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -783,6 +783,72 @@
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
};
+
+   msiof0: spi@e6e9 {
+   compatible = "renesas,msiof-r8a77995",
+"renesas,rcar-gen3-msiof";
+   reg = <0 0xe6e9 0 0x0064>;
+   interrupts = ;
+   clocks = < CPG_MOD 211>;
+   clock-names = "msiof_clk";
+   dmas = < 0x41>, < 0x40>,
+  < 0x41>, < 0x40>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < R8A77995_PD_ALWAYS_ON>;
+   resets = < 211>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   msiof1: spi@e6ea {
+   compatible = "renesas,msiof-r8a77995",
+"renesas,rcar-gen3-msiof";
+   reg = <0 0xe6ea 0 0x0064>;
+   interrupts = ;
+   clocks = < CPG_MOD 210>;
+   clock-names = "msiof_clk";
+   dmas = < 0x43>, < 0x42>,
+  < 0x43>, < 0x42>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < R8A77995_PD_ALWAYS_ON>;
+   resets = < 210>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   msiof2: spi@e6c0 {
+   compatible = "renesas,msiof-r8a77995",
+"renesas,rcar-gen3-msiof";
+   reg = <0 0xe6c0 0 0x0064>;
+   interrupts = ;
+   clocks = < CPG_MOD 209>;
+   clock-names = "msiof_clk";
+   dmas = < 0x45>, < 0x44>;
+   dma-names = "tx", "rx";
+   power-domains = < R8A77995_PD_ALWAYS_ON>;
+   resets = < 209>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   msiof3: spi@e6c1 {
+   compatible = "renesas,msiof-r8a77995",
+"renesas,rcar-gen3-msiof";
+   reg = <0 0xe6c1 0 0x0064>;
+   interrupts = ;
+   clocks = < CPG_MOD 208>;
+   clock-names = "msiof_clk";
+   dmas = < 0x47>, < 0x46>;
+   dma-names = "tx", "rx";
+   power-domains = < R8A77995_PD_ALWAYS_ON>;
+   resets = < 208>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
};
 
timer {
-- 
2.7.4

[PATCH 2/2] spi: sh-msiof: Document R-Car D3 support

[Ulrich Hecht]

Document support for the MSIOF module in the Renesas D3 (r8a77995) SoC.

No driver update is needed.

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 Documentation/devicetree/bindings/spi/sh-msiof.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt 
b/Documentation/devicetree/bindings/spi/sh-msiof.txt
index 3980632..914036d 100644
--- a/Documentation/devicetree/bindings/spi/sh-msiof.txt
+++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt
@@ -11,6 +11,7 @@ Required properties:
 "renesas,msiof-r8a7795" (R-Car H3)
 "renesas,msiof-r8a7796" (R-Car M3-W)
 "renesas,msiof-r8a77965" (R-Car M3-N)
+"renesas,msiof-r8a77995" (R-Car D3)
 "renesas,msiof-sh73a0" (SH-Mobile AG5)
 "renesas,sh-mobile-msiof" (generic SH-Mobile 
compatibile device)
 "renesas,rcar-gen2-msiof" (generic R-Car Gen2 and 
RZ/G1 compatible device)
-- 
2.7.4

[PATCH 4/5] arm64: dts: renesas: r8a77995-draak: add HDMI output

[Ulrich Hecht]

Adds LVDS decoder, HDMI encoder and connector for Draak boards.

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 80 ++
 1 file changed, 80 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts 
b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
index 9d73de8..b059e32 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
@@ -27,6 +27,41 @@
stdout-path = "serial0:115200n8";
};
 
+   lvds-decoder {
+   compatible = "thine,thc63lvd1024";
+   vcc-supply = <_3p3v>;
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+   thc63lvd1024_in: endpoint {
+   remote-endpoint = <_out>;
+   };
+   };
+
+   port@2 {
+   reg = <2>;
+   thc63lvd1024_out: endpoint {
+   remote-endpoint = <_in>;
+   };
+   };
+   };
+   };
+
+   hdmi-out {
+   compatible = "hdmi-connector";
+   type = "a";
+
+   port {
+   hdmi_con_out: endpoint {
+   remote-endpoint = <_out>;
+   };
+   };
+   };
+
vga {
compatible = "vga-connector";
 
@@ -154,6 +189,39 @@
reg = <0x50>;
pagesize = <8>;
};
+
+   hdmi@39 {
+   compatible = "adi,adv7511w";
+   reg = <0x39>, <0x3f>, <0x38>, <0x3c>;
+   reg-names = "main", "edid", "packet", "cec";
+   interrupt-parent = <>;
+   interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
+
+   adi,input-depth = <8>;
+   adi,input-colorspace = "rgb";
+   adi,input-clock = "1x";
+   adi,input-style = <1>;
+   adi,input-justification = "evenly";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+   adv7511_in: endpoint {
+   remote-endpoint = <_out>;
+   };
+   };
+
+   port@1 {
+   reg = <1>;
+   adv7511_out: endpoint {
+   remote-endpoint = <_con_out>;
+   };
+   };
+   };
+   };
 };
 
  {
@@ -176,6 +244,18 @@
};
 };
 
+ {
+   status = "okay";
+
+   ports {
+   port@1 {
+   lvds0_out: endpoint {
+   remote-endpoint = <_in>;
+   };
+   };
+   };
+};
+
  {
status = "okay";
 };
-- 
2.7.4

[PATCH 2/5] drm: rcar-du: lvds: Add R8A77995 support

[Ulrich Hecht]

Add support for the R-Car D3 (R8A77995) SoC to the LVDS encoder driver.

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 drivers/gpu/drm/rcar-du/rcar_lvds.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c 
b/drivers/gpu/drm/rcar-du/rcar_lvds.c
index 3d2d3bb..58fb9f8 100644
--- a/drivers/gpu/drm/rcar-du/rcar_lvds.c
+++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c
@@ -511,6 +511,11 @@ static const struct rcar_lvds_device_info 
rcar_lvds_r8a77970_info = {
.quirks = RCAR_LVDS_QUIRK_GEN2_PLLCR | RCAR_LVDS_QUIRK_GEN3_LVEN,
 };
 
+static const struct rcar_lvds_device_info rcar_lvds_r8a77995_info = {
+   .gen = 3,
+   .quirks = RCAR_LVDS_QUIRK_GEN3_LVEN,
+};
+
 static const struct of_device_id rcar_lvds_of_table[] = {
{ .compatible = "renesas,r8a7743-lvds", .data = _lvds_gen2_info },
{ .compatible = "renesas,r8a7790-lvds", .data = _lvds_r8a7790_info 
},
@@ -519,6 +524,7 @@ static const struct of_device_id rcar_lvds_of_table[] = {
{ .compatible = "renesas,r8a7795-lvds", .data = _lvds_gen3_info },
{ .compatible = "renesas,r8a7796-lvds", .data = _lvds_gen3_info },
{ .compatible = "renesas,r8a77970-lvds", .data = 
_lvds_r8a77970_info },
+   { .compatible = "renesas,r8a77995-lvds", .data = 
_lvds_r8a77995_info },
{ }
 };
 
-- 
2.7.4

[PATCH 3/5] arm64: dts: renesas: r8a77995: Add LVDS support

[Ulrich Hecht]

From: Kieran Bingham <kieran.bingham+rene...@ideasonboard.com>

The r8a77995 D3 platform has 2 LVDS channels connected to the DU.

Signed-off-by: Kieran Bingham <kieran.bingham+rene...@ideasonboard.com>
[uli: moved lvds* into the soc node, added PM domains, resets]
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 arch/arm64/boot/dts/renesas/r8a77995.dtsi | 56 +++
 1 file changed, 56 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index ba98865..8e78110d 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -757,12 +757,68 @@
port@1 {
reg = <1>;
du_out_lvds0: endpoint {
+   remote-endpoint = <_in>;
};
};
 
port@2 {
reg = <2>;
du_out_lvds1: endpoint {
+   remote-endpoint = <_in>;
+   };
+   };
+   };
+   };
+
+   lvds0: lvds-encoder@feb9 {
+   compatible = "renesas,r8a77995-lvds";
+   reg = <0 0xfeb9 0 0x20>;
+   clocks = < CPG_MOD 727>;
+   power-domains = < R8A77995_PD_ALWAYS_ON>;
+   resets = < 727>;
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+   lvds0_in: endpoint {
+   remote-endpoint = 
<_out_lvds0>;
+   };
+   };
+
+   port@1 {
+   reg = <1>;
+   lvds0_out: endpoint {
+   };
+   };
+   };
+   };
+
+   lvds1: lvds-encoder@feb90100 {
+   compatible = "renesas,r8a77995-lvds";
+   reg = <0 0xfeb90100 0 0x20>;
+   clocks = < CPG_MOD 727>;
+   power-domains = < R8A77995_PD_ALWAYS_ON>;
+   resets = < 727>;
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+   lvds1_in: endpoint {
+   remote-endpoint = 
<_out_lvds1>;
+   };
+   };
+
+   port@1 {
+   reg = <1>;
+   lvds1_out: endpoint {
};
};
};
-- 
2.7.4

[PATCH 5/5] arm64: dts: renesas: r8a77995-draak: add X12 input dot clock

[Ulrich Hecht]

74.25 Mhz oscillator X12 is connected to DU_DOTCLKIN0.

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts 
b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
index b059e32..04d2018 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
@@ -117,6 +117,12 @@
regulator-boot-on;
regulator-always-on;
};
+
+   x12_clk: x12 {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <7425>;
+   };
 };
 
 _clk {
@@ -235,6 +241,11 @@
pinctrl-names = "default";
status = "okay";
 
+   clocks = < CPG_MOD 724>,
+< CPG_MOD 723>,
+<_clk>;
+   clock-names = "du.0", "du.1", "dclkin.0";
+
ports {
port@0 {
endpoint {
-- 
2.7.4

[PATCH 1/5] drm: rcar-du: Add r8a77995 device support

[Ulrich Hecht]

From: Koji Matsuoka <koji.matsuoka...@renesas.com>

Add support for the R-Car D3 (R8A77995) SoC to the R-Car DU driver.

Signed-off-by: Koji Matsuoka <koji.matsuoka...@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 drivers/gpu/drm/rcar-du/rcar_du_drv.c | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c 
b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
index 05745e8..ba82842 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
@@ -266,6 +266,31 @@ static const struct rcar_du_device_info 
rcar_du_r8a77970_info = {
.num_lvds = 1,
 };
 
+static const struct rcar_du_device_info rcar_du_r8a77995_info = {
+   .gen = 3,
+   .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
+ | RCAR_DU_FEATURE_EXT_CTRL_REGS
+ | RCAR_DU_FEATURE_VSP1_SOURCE,
+   .num_crtcs = 2,
+   .routes = {
+   /* R8A77995 has two LVDS output and one RGB output.
+*/
+   [RCAR_DU_OUTPUT_DPAD0] = {
+   .possible_crtcs = BIT(0) | BIT(1),
+   .port = 0,
+   },
+   [RCAR_DU_OUTPUT_LVDS0] = {
+   .possible_crtcs = BIT(0),
+   .port = 1,
+   },
+   [RCAR_DU_OUTPUT_LVDS1] = {
+   .possible_crtcs = BIT(1),
+   .port = 2,
+   },
+   },
+   .num_lvds = 2,
+};
+
 static const struct of_device_id rcar_du_of_table[] = {
{ .compatible = "renesas,du-r8a7743", .data = _du_r8a7743_info },
{ .compatible = "renesas,du-r8a7745", .data = _du_r8a7745_info },
@@ -278,6 +303,7 @@ static const struct of_device_id rcar_du_of_table[] = {
{ .compatible = "renesas,du-r8a7795", .data = _du_r8a7795_info },
{ .compatible = "renesas,du-r8a7796", .data = _du_r8a7796_info },
{ .compatible = "renesas,du-r8a77970", .data = _du_r8a77970_info },
+   { .compatible = "renesas,du-r8a77995", .data = _du_r8a77995_info },
{ }
 };
 
-- 
2.7.4

[PATCH 0/5] R-Car D3 LVDS/HDMI support

[Ulrich Hecht]

Hi!

This adds D3 support to the DU and LVDS drivers, not including LVDS PLL
support.

It also adds LVDS encoders to the D3 device tree, and LVDS decoder, HDMI
encoder and HDMI output connector to the Draak device tree.

In theory that should be good enough to provide HDMI output on the Draak
board, but in practice the lack of LVDS PLL support prevents generation of
close-enough dot clock frequencies.

This series is based on renesas-drivers-2018-05-02-v4.17-rc3 and requires
Jacopo's "drm: bridge: Add thc63lvd1024 LVDS decoder driver" patch.

CU
Uli


Kieran Bingham (1):
  arm64: dts: renesas: r8a77995: Add LVDS support

Koji Matsuoka (1):
  drm: rcar-du: Add r8a77995 device support

Ulrich Hecht (3):
  drm: rcar-du: lvds: Add R8A77995 support
  arm64: dts: renesas: r8a77995-draak: add HDMI output
  arm64: dts: renesas: r8a77995-draak: add X12 input dot clock

 arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 91 ++
 arch/arm64/boot/dts/renesas/r8a77995.dtsi  | 56 
 drivers/gpu/drm/rcar-du/rcar_du_drv.c  | 26 
 drivers/gpu/drm/rcar-du/rcar_lvds.c|  6 ++
 4 files changed, 179 insertions(+)

-- 
2.7.4

Re: [PATCH igt 0/8] Non-Intel test suite fixes

[Ulrich Hecht]

On Fri, Apr 27, 2018 at 6:03 PM, Laurent Pinchart
<laurent.pinch...@ideasonboard.com> wrote:
> Hi Ulrich,
>
> On Thursday, 15 March 2018 16:45:36 EEST Ulrich Hecht wrote:
>> Hi!
>>
>> I have run the tests on a Renesas R-Car M3-W's DU device, and have found a
>> number of false negatives that mostly stem from use of Intel-specifics
>> without checking if that makes sense first. So here's a bunch of fixes for
>> those, hope they are generic enough for upstreaming.
>
> I'm looking for instructions on how to compile and use igt on elinux.org but
> can't find them. Could you please point me to the relevant page ?

Here's a wikified version of what I have sent to our QA people:

https://elinux.org/R-Car/Tests:igt

CU
Uli

[PATCH] spi: sh-msiof: Add spi_master_suspend/spi_master_resume

[Ulrich Hecht]

From: Gaku Inami <gaku.inami...@bp.renesas.com>

Add spi_master_suspend(), spi_master_resume() in PM callback since it needs
to start/stop the queue during suspend/resume.

Signed-off-by: Gaku Inami <gaku.inami...@bp.renesas.com>
Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki...@renesas.com>
[uli: simplified code, added pm field to platform driver]
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
Slightly brushed up port from the BSP; tested to execute on suspend/resume
without breaking anything.

CU
Uli

 drivers/spi/spi-sh-msiof.c | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
index ae086aa..db30aad 100644
--- a/drivers/spi/spi-sh-msiof.c
+++ b/drivers/spi/spi-sh-msiof.c
@@ -1415,12 +1415,35 @@ static const struct platform_device_id spi_driver_ids[] 
= {
 };
 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
 
+#ifdef CONFIG_PM_SLEEP
+static int sh_msiof_spi_suspend(struct device *dev)
+{
+   struct platform_device *pdev = to_platform_device(dev);
+   struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
+
+   return spi_master_suspend(p->master);
+}
+
+static int sh_msiof_spi_resume(struct device *dev)
+{
+   struct platform_device *pdev = to_platform_device(dev);
+   struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
+
+   return spi_master_resume(p->master);
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(sh_msiof_spi_pm_ops,
+sh_msiof_spi_suspend,
+sh_msiof_spi_resume);
+
 static struct platform_driver sh_msiof_spi_drv = {
.probe  = sh_msiof_spi_probe,
.remove = sh_msiof_spi_remove,
.id_table   = spi_driver_ids,
.driver = {
.name   = "spi_sh_msiof",
+   .pm = _msiof_spi_pm_ops,
.of_match_table = of_match_ptr(sh_msiof_match),
},
 };
-- 
2.7.4

[PATCH 2/2] serial: sh-sci: Use pm_runtime_get_sync()/put() on resume

[Ulrich Hecht]

From: Hien Dang <hien.dang...@renesas.com>

Since commit '39dd0f234fc37d ("PM / Domains: Allow runtime PM during system
PM phases")', runtime PM may be in suspended state during the system
suspend phase. It is therefore necessary to call pm_runtime_get_sync()/
pm_runtime_put() when accessing the hardware.

This modification is the counterpart for the resume case. It ensures
stability of the system, should the kernel allow the devices's runtime
suspend state to change during the system resume phase as well.

Signed-off-by: Hien Dang <hien.dang...@renesas.com>
Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki...@renesas.com>
[uli: edited description for clarity]
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 drivers/tty/serial/sh-sci.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 22d7a78..d5a1acb 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -3259,8 +3259,11 @@ static __maybe_unused int sci_resume(struct device *dev)
 {
struct sci_port *sport = dev_get_drvdata(dev);
 
-   if (sport)
+   if (sport) {
+   pm_runtime_get_sync(sport->port.dev);
uart_resume_port(_uart_driver, >port);
+   pm_runtime_put(sport->port.dev);
+   }
 
return 0;
 }
-- 
2.7.4

[PATCH 0/2] serial: sh-sci: Use pm_runtime_get_sync()/put()

[Ulrich Hecht]

Hi!

These patches make sure that the device is up while the suspend/resume code
is executed. Up-port from the BSP, tested not to break stuff.

CU
Uli


Hien Dang (2):
  serial: sh-sci: Use pm_runtime_get_sync()/put() on suspend
  serial: sh-sci: Use pm_runtime_get_sync()/put() on resume

 drivers/tty/serial/sh-sci.c | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

-- 
2.7.4

[PATCH 1/2] serial: sh-sci: Use pm_runtime_get_sync()/put() on suspend

[Ulrich Hecht]

From: Hien Dang <hien.dang...@renesas.com>

Since commit '39dd0f234fc37d ("PM / Domains: Allow runtime PM during system
PM phases")', runtime PM may be in suspended state when the module
registers are backed up. It is therefore necessary to ensure the device is
on during suspend by using pm_runtime_get_sync()/pm_runtime_put().

Signed-off-by: Hien Dang <hien.dang...@renesas.com>
Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki...@renesas.com>
[uli: edited description for clarity]
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 drivers/tty/serial/sh-sci.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index fdbbff5..22d7a78 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -3246,8 +3246,11 @@ static __maybe_unused int sci_suspend(struct device *dev)
 {
struct sci_port *sport = dev_get_drvdata(dev);
 
-   if (sport)
+   if (sport) {
+   pm_runtime_get_sync(sport->port.dev);
uart_suspend_port(_uart_driver, >port);
+   pm_runtime_put(sport->port.dev);
+   }
 
return 0;
 }
-- 
2.7.4

[PATCH v2] serial: sh-sci: Support for HSCIF RX sampling point adjustment

[Ulrich Hecht]

HSCIF has facilities that allow moving the RX sampling point by between
-8 and 7 sampling cycles (one sampling cycles equals 1/15 of a bit
by default) to improve the error margin in case of slightly mismatched
bit rates between sender and receiver.

This patch tries to determine if shifting the sampling point can improve
the error margin and will enable it if so.

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
This revision dumps the sysfs interface and works out the optimal shift
on its own. It also moves setting of the HSSRR register back to its
original location.

CU
Uli


 drivers/tty/serial/sh-sci.c | 65 +
 drivers/tty/serial/sh-sci.h |  4 +++
 2 files changed, 46 insertions(+), 23 deletions(-)

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index fdbbff5..5d61654 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -2390,6 +2390,27 @@ static void sci_set_termios(struct uart_port *port, 
struct ktermios *termios,
 
uart_update_timeout(port, termios->c_cflag, baud);
 
+   /* byte size and parity */
+   switch (termios->c_cflag & CSIZE) {
+   case CS5:
+   bits = 7;
+   break;
+   case CS6:
+   bits = 8;
+   break;
+   case CS7:
+   bits = 9;
+   break;
+   default:
+   bits = 10;
+   break;
+   }
+
+   if (termios->c_cflag & CSTOPB)
+   bits++;
+   if (termios->c_cflag & PARENB)
+   bits++;
+
if (best_clk >= 0) {
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
switch (srr + 1) {
@@ -2406,8 +2427,27 @@ static void sci_set_termios(struct uart_port *port, 
struct ktermios *termios,
serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
serial_port_out(port, SCSMR, smr_val);
serial_port_out(port, SCBRR, brr);
-   if (sci_getreg(port, HSSRR)->size)
-   serial_port_out(port, HSSRR, srr | HSCIF_SRE);
+   if (sci_getreg(port, HSSRR)->size) {
+   unsigned int hssrr = srr | HSCIF_SRE;
+   /* Calculate deviation from intended rate at the
+* center of the last stop bit in sampling clocks.
+*/
+   int last_stop = bits * 2 - 1;
+   int deviation = min_err * srr * last_stop / 2 / baud;
+
+   if (abs(deviation) >= 2) {
+   /* At least two sampling clocks off at the
+* last stop bit; we can increase the error
+* margin by shifting the sampling point.
+*/
+   int shift = min(-8, max(7, deviation / 2));
+
+   hssrr |= (shift << HSCIF_SRHP_SHIFT) &
+HSCIF_SRHP_MASK;
+   hssrr |= HSCIF_SRDE;
+   }
+   serial_port_out(port, HSSRR, hssrr);
+   }
 
/* Wait one bit interval */
udelay((100 + (baud - 1)) / baud);
@@ -2474,27 +2514,6 @@ static void sci_set_termios(struct uart_port *port, 
struct ktermios *termios,
 * value obtained by this formula is too small. Therefore, if the value
 * is smaller than 20ms, use 20ms as the timeout value for DMA.
 */
-   /* byte size and parity */
-   switch (termios->c_cflag & CSIZE) {
-   case CS5:
-   bits = 7;
-   break;
-   case CS6:
-   bits = 8;
-   break;
-   case CS7:
-   bits = 9;
-   break;
-   default:
-   bits = 10;
-   break;
-   }
-
-   if (termios->c_cflag & CSTOPB)
-   bits++;
-   if (termios->c_cflag & PARENB)
-   bits++;
-
s->rx_frame = (1 * bits) / (baud / 100);
 #ifdef CONFIG_SERIAL_SH_SCI_DMA
s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
diff --git a/drivers/tty/serial/sh-sci.h b/drivers/tty/serial/sh-sci.h
index a5f792f..0b9e804 100644
--- a/drivers/tty/serial/sh-sci.h
+++ b/drivers/tty/serial/sh-sci.h
@@ -130,6 +130,10 @@ enum {
 
 /* HSSRR HSCIF */
 #define HSCIF_SRE  BIT(15) /* Sampling Rate Register Enable */
+#define HSCIF_SRDE BIT(14) /* Sampling Point Register Enable */
+
+#define HSCIF_SRHP_SHIFT   8
+#define HSCIF_SRHP_MASK0x0f00
 
 /* SCPCR (Serial Port Control Register), SCIFA/SCIFB only */
 #define SCPCR_RTSC BIT(4)  /* Serial Port RTS# Pin / Output Pin */
-- 
2.7.4

Re: [Intel-gfx] [PATCH igt 0/8] Non-Intel test suite fixes

[Ulrich Hecht]

On Fri, Mar 16, 2018 at 9:55 AM, Daniel Vetter <dan...@ffwll.ch> wrote:
> On Thu, Mar 15, 2018 at 03:45:36PM +0100, Ulrich Hecht wrote:
>> Hi!
>>
>> I have run the tests on a Renesas R-Car M3-W's DU device, and have found a
>> number of false negatives that mostly stem from use of Intel-specifics
>> without checking if that makes sense first. So here's a bunch of fixes for
>> those, hope they are generic enough for upstreaming.
>
> Nice, other people using this! Do you plan to maintain this actively going
> forward, or is this more a one-off effort?

For now, this is just an attempt at evaluating if this works for us.
It has caught a few things that look like legitimate bugs to me,
though...

CU
Uli

[PATCH 2/3] pinctrl: sh-pfc: r8a7796: deduplicate VIN4 pin definitions

[Ulrich Hecht]

Use union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancies
in pin definitions.

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 308 ---
 1 file changed, 72 insertions(+), 236 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 7a26392..96ddcf7 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -3897,130 +3897,6 @@ static const unsigned int usb30_mux[] = {
 };
 
 /* - VIN4 --- 
*/
-static const unsigned int vin4_data8_a_pins[] = {
-   RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
-   RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-   RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-   RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-};
-static const unsigned int vin4_data8_a_mux[] = {
-   VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
-   VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
-   VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
-   VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
-};
-static const unsigned int vin4_data8_b_pins[] = {
-   RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
-   RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
-   RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
-   RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-};
-static const unsigned int vin4_data8_b_mux[] = {
-   VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
-   VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
-   VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
-   VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
-};
-static const unsigned int vin4_data10_a_pins[] = {
-   RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
-   RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-   RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-   RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-   RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
-};
-static const unsigned int vin4_data10_a_mux[] = {
-   VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
-   VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
-   VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
-   VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
-   VI4_DATA8_MARK,  VI4_DATA9_MARK,
-};
-static const unsigned int vin4_data10_b_pins[] = {
-   RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
-   RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
-   RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
-   RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-   RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
-};
-static const unsigned int vin4_data10_b_mux[] = {
-   VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
-   VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
-   VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
-   VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
-   VI4_DATA8_MARK,  VI4_DATA9_MARK,
-};
-static const unsigned int vin4_data12_a_pins[] = {
-   RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
-   RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-   RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-   RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-   RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
-   RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
-};
-static const unsigned int vin4_data12_a_mux[] = {
-   VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
-   VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
-   VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
-   VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
-   VI4_DATA8_MARK,  VI4_DATA9_MARK,
-   VI4_DATA10_MARK, VI4_DATA11_MARK,
-};
-static const unsigned int vin4_data12_b_pins[] = {
-   RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
-   RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
-   RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
-   RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-   RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
-   RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
-};
-static const unsigned int vin4_data12_b_mux[] = {
-   VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
-   VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
-   VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
-   VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
-   VI4_DATA8_MARK,  VI4_DATA9_MARK,
-   VI4_DATA10_MARK, VI4_DATA11_MARK,
-};
-static const unsigned int vin4_data16_a_pins[] = {
-   RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
-   RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-   RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-   RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-   RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
-   RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
-   RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-   RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-};
-static const unsigned int vin4_data16_a_mux[] = {
-   VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
-   VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
-   VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
-   VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
-   VI4_DATA8_MARK,  VI4_DATA9_MARK,
-   VI4_DATA10_MARK, VI4_DATA11_MARK,
-   VI4_DATA12_MARK, VI4_DATA13_MARK,
-   VI4_DATA14_MARK, VI4_DATA15_MARK,
-};
-static const unsigned int vin4_data16_b_pins[] = {
-   RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
-   RCAR_GP_PIN(2, 2), RCAR_GP_PI

[PATCH 3/3] pinctrl: sh-pfc: r8a77995: deduplicate VIN4 pin definitions

[Ulrich Hecht]

Use union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancies
in pin definitions.

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 154 --
 1 file changed, 36 insertions(+), 118 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
index 62bab9f..70def2af 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
@@ -1627,68 +1627,6 @@ static const unsigned int usb0_mux[] = {
 };
 
 /* - VIN4 --- 
*/
-static const unsigned int vin4_data8_pins[] = {
-   RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
-   RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
-   RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
-   RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
-};
-static const unsigned int vin4_data8_mux[] = {
-   VI4_DATA0_MARK, VI4_DATA1_MARK,
-   VI4_DATA2_MARK, VI4_DATA3_MARK,
-   VI4_DATA4_MARK, VI4_DATA5_MARK,
-   VI4_DATA6_MARK, VI4_DATA7_MARK,
-};
-static const unsigned int vin4_data10_pins[] = {
-   RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
-   RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
-   RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
-   RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
-   RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
-};
-static const unsigned int vin4_data10_mux[] = {
-   VI4_DATA0_MARK, VI4_DATA1_MARK,
-   VI4_DATA2_MARK, VI4_DATA3_MARK,
-   VI4_DATA4_MARK, VI4_DATA5_MARK,
-   VI4_DATA6_MARK, VI4_DATA7_MARK,
-   VI4_DATA8_MARK,  VI4_DATA9_MARK,
-};
-static const unsigned int vin4_data12_pins[] = {
-   RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
-   RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
-   RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
-   RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
-   RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
-   RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
-};
-static const unsigned int vin4_data12_mux[] = {
-   VI4_DATA0_MARK, VI4_DATA1_MARK,
-   VI4_DATA2_MARK, VI4_DATA3_MARK,
-   VI4_DATA4_MARK, VI4_DATA5_MARK,
-   VI4_DATA6_MARK, VI4_DATA7_MARK,
-   VI4_DATA8_MARK,  VI4_DATA9_MARK,
-   VI4_DATA10_MARK, VI4_DATA11_MARK,
-};
-static const unsigned int vin4_data16_pins[] = {
-   RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
-   RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
-   RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
-   RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
-   RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
-   RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
-   RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
-   RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
-};
-static const unsigned int vin4_data16_mux[] = {
-   VI4_DATA0_MARK, VI4_DATA1_MARK,
-   VI4_DATA2_MARK, VI4_DATA3_MARK,
-   VI4_DATA4_MARK, VI4_DATA5_MARK,
-   VI4_DATA6_MARK, VI4_DATA7_MARK,
-   VI4_DATA8_MARK,  VI4_DATA9_MARK,
-   VI4_DATA10_MARK, VI4_DATA11_MARK,
-   VI4_DATA12_MARK, VI4_DATA13_MARK,
-   VI4_DATA14_MARK, VI4_DATA15_MARK,
-};
 static const unsigned int vin4_data18_pins[] = {
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
@@ -1711,57 +1649,37 @@ static const unsigned int vin4_data18_mux[] = {
VI4_DATA20_MARK, VI4_DATA21_MARK,
VI4_DATA22_MARK, VI4_DATA23_MARK,
 };
-static const unsigned int vin4_data20_pins[] = {
-   RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
-   RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
-   RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
-   RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
-   RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
-   RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
-   RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
-   RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
-   RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
-   RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
-};
-static const unsigned int vin4_data20_mux[] = {
-   VI4_DATA0_MARK, VI4_DATA1_MARK,
-   VI4_DATA2_MARK, VI4_DATA3_MARK,
-   VI4_DATA4_MARK, VI4_DATA5_MARK,
-   VI4_DATA6_MARK, VI4_DATA7_MARK,
-   VI4_DATA8_MARK,  VI4_DATA9_MARK,
-   VI4_DATA10_MARK, VI4_DATA11_MARK,
-   VI4_DATA12_MARK, VI4_DATA13_MARK,
-   VI4_DATA14_MARK, VI4_DATA15_MARK,
-   VI4_DATA16_MARK, VI4_DATA17_MARK,
-   VI4_DATA18_MARK, VI4_DATA19_MARK,
-};
-static const unsigned int vin4_data24_pins[] = {
-   RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
-   RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
-   RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
-   RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
-   RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
-   RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
-   RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
-   RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
-   RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
-   RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
-   RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
-   RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
+static

[PATCH 0/3] pinctrl: sh-pfc: R-Car Gen3 VIN4 18-bit pin control fixups

[Ulrich Hecht]

Hi!

This fixes the incorrect RGB666 pin assignments reported by Geert in H3,
M3-W and D3 SoCs. Thank you!

CU
Uli


Ulrich Hecht (3):
  pinctrl: sh-pfc: r8a7795: correct VIN4 18-bit pins
  pinctrl: sh-pfc: r8a7796: correct VIN4 18-bit pins
  pinctrl: sh-pfc: r8a77995: correct VIN4 18-bit pins

 drivers/pinctrl/sh-pfc/pfc-r8a7795.c  | 24 
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c  | 24 
 drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 12 ++--
 3 files changed, 30 insertions(+), 30 deletions(-)

-- 
2.7.4

[PATCH 1/3] pinctrl: sh-pfc: r8a7795: correct VIN4 18-bit pins

[Ulrich Hecht]

RGB666 has a pin assignment that differs from the other formats.

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 24 
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 706ffe15..a9fd534 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -4053,48 +4053,48 @@ static const unsigned int vin4_data16_b_mux[] = {
VI4_DATA14_MARK, VI4_DATA15_MARK,
 };
 static const unsigned int vin4_data18_a_pins[] = {
-   RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-   RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-   RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+   RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+   RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+   RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
 };
 static const unsigned int vin4_data18_a_mux[] = {
-   VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
-   VI4_DATA8_MARK,  VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
-   VI4_DATA16_MARK, VI4_DATA17_MARK,
+   VI4_DATA18_MARK, VI4_DATA19_MARK,
+   VI4_DATA20_MARK, VI4_DATA21_MARK,
+   VI4_DATA22_MARK, VI4_DATA23_MARK,
 };
 static const unsigned int vin4_data18_b_pins[] = {
-   RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-   RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-   RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+   RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+   RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+   RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
 };
 static const unsigned int vin4_data18_b_mux[] = {
-   VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
-   VI4_DATA8_MARK,  VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
-   VI4_DATA16_MARK, VI4_DATA17_MARK,
+   VI4_DATA18_MARK, VI4_DATA19_MARK,
+   VI4_DATA20_MARK, VI4_DATA21_MARK,
+   VI4_DATA22_MARK, VI4_DATA23_MARK,
 };
 static const unsigned int vin4_data20_a_pins[] = {
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
-- 
2.7.4

[PATCH 0/3] pinctrl: sh-pfc: R-Car Gen 3 VIN4 deduplication

[Ulrich Hecht]

Hi!

This uses union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancy
in the VIN4 pin data on H3, M3-W and D3 SoCs.

CU
Uli


Ulrich Hecht (3):
  pinctrl: sh-pfc: r8a7795: deduplicate VIN4 pin definitions
  pinctrl: sh-pfc: r8a7796: deduplicate VIN4 pin definitions
  pinctrl: sh-pfc: r8a77995: deduplicate VIN4 pin definitions

 drivers/pinctrl/sh-pfc/pfc-r8a7795.c  | 308 --
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c  | 308 --
 drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 154 -
 3 files changed, 180 insertions(+), 590 deletions(-)

-- 
2.7.4

[PATCH 1/3] pinctrl: sh-pfc: r8a7795: deduplicate VIN4 pin definitions

[Ulrich Hecht]

Use union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancies
in pin definitions.

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 308 ---
 1 file changed, 72 insertions(+), 236 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index a9fd534..722cf6c 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -3928,130 +3928,6 @@ static const unsigned int usb30_mux[] = {
 };
 
 /* - VIN4 --- 
*/
-static const unsigned int vin4_data8_a_pins[] = {
-   RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
-   RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-   RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-   RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-};
-static const unsigned int vin4_data8_a_mux[] = {
-   VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
-   VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
-   VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
-   VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
-};
-static const unsigned int vin4_data8_b_pins[] = {
-   RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
-   RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
-   RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
-   RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-};
-static const unsigned int vin4_data8_b_mux[] = {
-   VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
-   VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
-   VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
-   VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
-};
-static const unsigned int vin4_data10_a_pins[] = {
-   RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
-   RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-   RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-   RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-   RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
-};
-static const unsigned int vin4_data10_a_mux[] = {
-   VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
-   VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
-   VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
-   VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
-   VI4_DATA8_MARK,  VI4_DATA9_MARK,
-};
-static const unsigned int vin4_data10_b_pins[] = {
-   RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
-   RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
-   RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
-   RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-   RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
-};
-static const unsigned int vin4_data10_b_mux[] = {
-   VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
-   VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
-   VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
-   VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
-   VI4_DATA8_MARK,  VI4_DATA9_MARK,
-};
-static const unsigned int vin4_data12_a_pins[] = {
-   RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
-   RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-   RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-   RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-   RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
-   RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
-};
-static const unsigned int vin4_data12_a_mux[] = {
-   VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
-   VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
-   VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
-   VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
-   VI4_DATA8_MARK,  VI4_DATA9_MARK,
-   VI4_DATA10_MARK, VI4_DATA11_MARK,
-};
-static const unsigned int vin4_data12_b_pins[] = {
-   RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
-   RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
-   RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
-   RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-   RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
-   RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
-};
-static const unsigned int vin4_data12_b_mux[] = {
-   VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
-   VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
-   VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
-   VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
-   VI4_DATA8_MARK,  VI4_DATA9_MARK,
-   VI4_DATA10_MARK, VI4_DATA11_MARK,
-};
-static const unsigned int vin4_data16_a_pins[] = {
-   RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
-   RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
-   RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
-   RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-   RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
-   RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
-   RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
-   RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-};
-static const unsigned int vin4_data16_a_mux[] = {
-   VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
-   VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
-   VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
-   VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
-   VI4_DATA8_MARK,  VI4_DATA9_MARK,
-   VI4_DATA10_MARK, VI4_DATA11_MARK,
-   VI4_DATA12_MARK, VI4_DATA13_MARK,
-   VI4_DATA14_MARK, VI4_DATA15_MARK,
-};
-static const unsigned int vin4_data16_b_pins[] = {
-   RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
-   RCAR_GP_PIN(2, 2), RCAR_GP_PI

[PATCH 3/3] pinctrl: sh-pfc: r8a77995: correct VIN4 18-bit pins

[Ulrich Hecht]

RGB666 has a pin assignment that differs from the other formats.

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
index 27b9417..62bab9f 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
@@ -1690,26 +1690,26 @@ static const unsigned int vin4_data16_mux[] = {
VI4_DATA14_MARK, VI4_DATA15_MARK,
 };
 static const unsigned int vin4_data18_pins[] = {
-   RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
-   RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
-   RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
+   RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
+   RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
+   RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
 };
 static const unsigned int vin4_data18_mux[] = {
-   VI4_DATA0_MARK, VI4_DATA1_MARK,
VI4_DATA2_MARK, VI4_DATA3_MARK,
VI4_DATA4_MARK, VI4_DATA5_MARK,
VI4_DATA6_MARK, VI4_DATA7_MARK,
-   VI4_DATA8_MARK,  VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
-   VI4_DATA16_MARK, VI4_DATA17_MARK,
+   VI4_DATA18_MARK, VI4_DATA19_MARK,
+   VI4_DATA20_MARK, VI4_DATA21_MARK,
+   VI4_DATA22_MARK, VI4_DATA23_MARK,
 };
 static const unsigned int vin4_data20_pins[] = {
RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
-- 
2.7.4

[PATCH 2/3] pinctrl: sh-pfc: r8a7796: correct VIN4 18-bit pins

[Ulrich Hecht]

RGB666 has a pin assignment that differs from the other formats.

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 24 
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index e6fff55..7a26392 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -4022,48 +4022,48 @@ static const unsigned int vin4_data16_b_mux[] = {
VI4_DATA14_MARK, VI4_DATA15_MARK,
 };
 static const unsigned int vin4_data18_a_pins[] = {
-   RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
-   RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-   RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+   RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+   RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+   RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
 };
 static const unsigned int vin4_data18_a_mux[] = {
-   VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
-   VI4_DATA8_MARK,  VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
-   VI4_DATA16_MARK, VI4_DATA17_MARK,
+   VI4_DATA18_MARK, VI4_DATA19_MARK,
+   VI4_DATA20_MARK, VI4_DATA21_MARK,
+   VI4_DATA22_MARK, VI4_DATA23_MARK,
 };
 static const unsigned int vin4_data18_b_pins[] = {
-   RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
-   RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
-   RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
+   RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+   RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+   RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
 };
 static const unsigned int vin4_data18_b_mux[] = {
-   VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
-   VI4_DATA8_MARK,  VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
-   VI4_DATA16_MARK, VI4_DATA17_MARK,
+   VI4_DATA18_MARK, VI4_DATA19_MARK,
+   VI4_DATA20_MARK, VI4_DATA21_MARK,
+   VI4_DATA22_MARK, VI4_DATA23_MARK,
 };
 static const unsigned int vin4_data20_a_pins[] = {
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
-- 
2.7.4

[PATCH igt 7/8] tests/kms_addfb_basic: size_tests(): reduce test buffer size

[Ulrich Hecht]

Fixes fails on low-memory devices.

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 tests/kms_addfb_basic.c | 26 +-
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/tests/kms_addfb_basic.c b/tests/kms_addfb_basic.c
index cf9ba37..d1da718 100644
--- a/tests/kms_addfb_basic.c
+++ b/tests/kms_addfb_basic.c
@@ -238,26 +238,26 @@ static void size_tests(int fd)
struct drm_mode_fb_cmd2 f_16 = {};
struct drm_mode_fb_cmd2 f_8 = {};
 
-   f.width = 1024;
-   f.height = 1024;
+   f.width = 512;
+   f.height = 512;
f.pixel_format = DRM_FORMAT_XRGB;
-   f.pitches[0] = 1024*4;
+   f.pitches[0] = 512*4;
 
-   f_16.width = 1024;
-   f_16.height = 1024*2;
+   f_16.width = 512;
+   f_16.height = 512*2;
f_16.pixel_format = DRM_FORMAT_RGB565;
-   f_16.pitches[0] = 1024*2;
+   f_16.pitches[0] = 512*2;
 
-   f_8.width = 1024*2;
-   f_8.height = 1024*2;
+   f_8.width = 512*2;
+   f_8.height = 512*2;
f_8.pixel_format = DRM_FORMAT_C8;
-   f_8.pitches[0] = 1024*2;
+   f_8.pitches[0] = 512*2;
 
igt_fixture {
-   gem_bo = igt_create_bo_with_dimensions(fd, 1024, 1024,
+   gem_bo = igt_create_bo_with_dimensions(fd, 512, 512,
DRM_FORMAT_XRGB, 0, 0, NULL, NULL, NULL);
igt_assert(gem_bo);
-   gem_bo_small = igt_create_bo_with_dimensions(fd, 1024, 1023,
+   gem_bo_small = igt_create_bo_with_dimensions(fd, 512, 511,
DRM_FORMAT_XRGB, 0, 0, NULL, NULL, NULL);
igt_assert(gem_bo_small);
}
@@ -311,7 +311,7 @@ static void size_tests(int fd)
}
 
/* Just to check that the parameters would work. */
-   f.height = 1020;
+   f.height = 510;
igt_subtest("small-bo") {
igt_assert(drmIoctl(fd, DRM_IOCTL_MODE_ADDFB2, ) == 0);
igt_assert(drmIoctl(fd, DRM_IOCTL_MODE_RMFB, _id) == 0);
@@ -320,7 +320,7 @@ static void size_tests(int fd)
 
igt_subtest("bo-too-small-due-to-tiling") {
igt_require(is_i915_device(fd));
-   gem_set_tiling(fd, gem_bo_small, I915_TILING_X, 1024*4);
+   gem_set_tiling(fd, gem_bo_small, I915_TILING_X, 512*4);
igt_assert(drmIoctl(fd, DRM_IOCTL_MODE_ADDFB2, ) == -1 &&
   errno == EINVAL);
}
-- 
2.7.4

[PATCH igt 1/8] tests/kms_addfb_basic: skip i915-specific tests on other platforms

[Ulrich Hecht]

Add is_i915_device() requirement to tests using Intel-specific APIs.

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 tests/kms_addfb_basic.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/tests/kms_addfb_basic.c b/tests/kms_addfb_basic.c
index 7d8852f..cf9ba37 100644
--- a/tests/kms_addfb_basic.c
+++ b/tests/kms_addfb_basic.c
@@ -104,6 +104,7 @@ static void invalid_tests(int fd)
}
 
igt_subtest("clobberred-modifier") {
+   igt_require(is_i915_device(fd));
f.flags = 0;
f.modifier[0] = 0;
gem_set_tiling(fd, gem_bo, I915_TILING_X, 512*4);
@@ -318,6 +319,7 @@ static void size_tests(int fd)
}
 
igt_subtest("bo-too-small-due-to-tiling") {
+   igt_require(is_i915_device(fd));
gem_set_tiling(fd, gem_bo_small, I915_TILING_X, 1024*4);
igt_assert(drmIoctl(fd, DRM_IOCTL_MODE_ADDFB2, ) == -1 &&
   errno == EINVAL);
@@ -369,6 +371,7 @@ static void addfb25_tests(int fd)
 
igt_subtest_group {
igt_fixture {
+   igt_require(is_i915_device(fd));
gem_set_tiling(fd, gem_bo, I915_TILING_X, 1024*4);
igt_require_fb_modifiers(fd);
}
-- 
2.7.4

[PATCH igt 4/8] lib/igt_gt: check for presence of GPU reset before using it

[Ulrich Hecht]

Fixes failed assertion on non-i915 devices.

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 lib/igt_gt.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index 9cb07c2..825ea52 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -166,14 +166,15 @@ igt_hang_t igt_allow_hang(int fd, unsigned ctx, unsigned 
flags)
struct drm_i915_gem_context_param param;
unsigned ban;
 
+   if (!igt_check_boolean_env_var("IGT_HANG_WITHOUT_RESET", false))
+   igt_require(has_gpu_reset(fd));
+
igt_assert(igt_sysfs_set_parameter
   (fd, "reset", "%d", INT_MAX /* any reset method */));
 
if (!igt_check_boolean_env_var("IGT_HANG", true))
igt_skip("hang injection disabled by user");
gem_context_require_bannable(fd);
-   if (!igt_check_boolean_env_var("IGT_HANG_WITHOUT_RESET", false))
-   igt_require(has_gpu_reset(fd));
 
param.ctx_id = ctx;
param.size = 0;
-- 
2.7.4

[PATCH igt 8/8] test/kms_addfb_basic: tolerate absence of 8-bit format

[Ulrich Hecht]

Ignores failure to add DRM_FORMAT_C8 frame buffer; some devices do not
support any 8-bit format.

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 tests/kms_addfb_basic.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tests/kms_addfb_basic.c b/tests/kms_addfb_basic.c
index d1da718..db79827 100644
--- a/tests/kms_addfb_basic.c
+++ b/tests/kms_addfb_basic.c
@@ -273,8 +273,8 @@ static void size_tests(int fd)
igt_assert(drmIoctl(fd, DRM_IOCTL_MODE_ADDFB2, _16) == 0);
igt_assert(drmIoctl(fd, DRM_IOCTL_MODE_RMFB, _16.fb_id) == 0);
f.fb_id = 0;
-   igt_assert(drmIoctl(fd, DRM_IOCTL_MODE_ADDFB2, _8) == 0);
-   igt_assert(drmIoctl(fd, DRM_IOCTL_MODE_RMFB, _8.fb_id) == 0);
+   if (drmIoctl(fd, DRM_IOCTL_MODE_ADDFB2, _8) == 0)
+   igt_assert(drmIoctl(fd, DRM_IOCTL_MODE_RMFB, 
_8.fb_id) == 0);
f.fb_id = 0;
}
 
-- 
2.7.4

[PATCH igt 2/8] tests/kms_panel_fitting: check for i915 before checking version

[Ulrich Hecht]

Fixes false negatives on non-i915 platforms.

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 tests/kms_panel_fitting.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tests/kms_panel_fitting.c b/tests/kms_panel_fitting.c
index b3cee22..6d0be50 100644
--- a/tests/kms_panel_fitting.c
+++ b/tests/kms_panel_fitting.c
@@ -243,6 +243,7 @@ static void test_atomic_fastset(igt_display_t *display)
igt_set_module_param_int("fastboot", 1);
 
igt_require(display->is_atomic);
+   igt_require(is_i915_device(display->drm_fd));
igt_require(intel_gen(intel_get_drm_devid(display->drm_fd)) >= 5);
 
for_each_pipe_with_valid_output(display, pipe, output) {
-- 
2.7.4

[PATCH igt 6/8] lib/igt_pm: turn absence of autosuspend_delay_ms from fail to skip

[Ulrich Hecht]

Fixes false negatives on everything that doesn't happen to be at a
specific hard-coded sysfs path...

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 lib/igt_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/igt_pm.c b/lib/igt_pm.c
index 5bf5b2e..641157b 100644
--- a/lib/igt_pm.c
+++ b/lib/igt_pm.c
@@ -262,7 +262,7 @@ bool igt_setup_runtime_pm(void)
 * suite goes faster and we have a higher probability of triggering race
 * conditions. */
fd = open(POWER_DIR "/autosuspend_delay_ms", O_WRONLY);
-   igt_assert_f(fd >= 0,
+   igt_require_f(fd >= 0,
 "Can't open " POWER_DIR "/autosuspend_delay_ms\n");
 
/* If we fail to write to the file, it means this system doesn't support
-- 
2.7.4

[PATCH igt 0/8] Non-Intel test suite fixes

[Ulrich Hecht]

Hi!

I have run the tests on a Renesas R-Car M3-W's DU device, and have found a
number of false negatives that mostly stem from use of Intel-specifics
without checking if that makes sense first. So here's a bunch of fixes for
those, hope they are generic enough for upstreaming.

CU
Uli


Ulrich Hecht (8):
  tests/kms_addfb_basic: skip i915-specific tests on other platforms
  tests/kms_panel_fitting: check for i915 before checking version
  lib/igt_gt: has_gpu_reset(): fix failed assertion on non-i915
platforms
  lib/igt_gt: check for presence of GPU reset before using it
  tests/kms_plane_lowres: skip i915-specific tests on other platforms
  lib/igt_pm: turn absence of autosuspend_delay_ms from fail to skip
  tests/kms_addfb_basic: size_tests(): reduce test buffer size
  test/kms_addfb_basic: tolerate absence of 8-bit format

 lib/igt_gt.c  | 24 ++--
 lib/igt_pm.c  |  2 +-
 tests/kms_addfb_basic.c   | 33 ++---
 tests/kms_panel_fitting.c |  1 +
 tests/kms_plane_lowres.c  |  1 +
 5 files changed, 35 insertions(+), 26 deletions(-)

-- 
2.7.4

[PATCH igt 5/8] tests/kms_plane_lowres: skip i915-specific tests on other platforms

[Ulrich Hecht]

Add is_i915_device() requirement to tests using Intel-specific APIs.

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 tests/kms_plane_lowres.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tests/kms_plane_lowres.c b/tests/kms_plane_lowres.c
index d1e4b3c..8fc7654 100644
--- a/tests/kms_plane_lowres.c
+++ b/tests/kms_plane_lowres.c
@@ -270,6 +270,7 @@ run_tests_for_pipe(data_t *data, enum pipe pipe)
igt_skip_on(pipe >= data->display.n_pipes);
 
igt_display_require_output_on_pipe(>display, pipe);
+   igt_require(is_i915_device(data->drm_fd));
}
 
igt_subtest_f("pipe-%s-tiling-none",
-- 
2.7.4

[PATCH igt 3/8] lib/igt_gt: has_gpu_reset(): fix failed assertion on non-i915 platforms

[Ulrich Hecht]

Checks if we have an i915 device before using intel_get_drm_devid().

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 lib/igt_gt.c | 19 +++
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index e630550..9cb07c2 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -59,14 +59,17 @@ static bool has_gpu_reset(int fd)
struct drm_i915_getparam gp;
int val = 0;
 
-   memset(, 0, sizeof(gp));
-   gp.param = 35; /* HAS_GPU_RESET */
-   gp.value = 
-
-   if (ioctl(fd, DRM_IOCTL_I915_GETPARAM, ))
-   once = intel_gen(intel_get_drm_devid(fd)) >= 5;
-   else
-   once = val > 0;
+   if (is_i915_device(fd)) {
+   memset(, 0, sizeof(gp));
+   gp.param = 35; /* HAS_GPU_RESET */
+   gp.value = 
+
+   if (ioctl(fd, DRM_IOCTL_I915_GETPARAM, ))
+   once = intel_gen(intel_get_drm_devid(fd)) >= 5;
+   else
+   once = val > 0;
+   } else
+   once = 0;
}
return once;
 }
-- 
2.7.4

Re: [PATCH 1/4] pinctrl: sh-pfc: r8a7796: Add VIN4, VIN5 pins, groups and functions

[Ulrich Hecht]

On Tue, Feb 20, 2018 at 2:58 PM, Geert Uytterhoeven
 wrote:
> Would there be a use case for vin4_data4 and vin5_data4, or is that
> mode only supported on R-Car H2?

The docs don't mention it, so I would assume it's not supported.

CU
Uli

Re: [PATCH] serial: sh-sci: prevent lockup on full TTY buffers

[Ulrich Hecht]

On Thu, Feb 15, 2018 at 2:12 PM, Wolfram Sang  wrote:
>
>> This can be prevented by doing a dummy read of the RX data register.
>
> Just so I understand the issue correctly: We are reading the register to
> throw the content away to prevent it being used in the TTY buffers?

Not quite. The problem was that if the buffers are full,
sci_receive_chars() returned immediately without reading anything from
the data register, and that led to a lockup. I am not fully sure why
that is so (I arrived at the fix by examining how the different code
paths look from the serial controller's perspective), but dropping
data here fixes it. At this point buffers are full, so any data
received will have to be discarded anyway.

CU
Uli

[PATCH 1/3] pinctrl: sh-pfc: r8a7795: Add TMU pins, groups and functions

[Ulrich Hecht]

From: Takeshi Kihara <takeshi.kihara...@renesas.com>

This patch adds TMU TCLK{1,2} pins, groups and functions to
the R8A7795 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 42 
 1 file changed, 42 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 18aeee5..100eda4 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -3840,6 +3840,36 @@ static const unsigned int ssi9_ctrl_b_mux[] = {
SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
 };
 
+/* - TMU  
*/
+static const unsigned int tmu_tclk1_a_pins[] = {
+   /* TCLK */
+   RCAR_GP_PIN(6, 23),
+};
+static const unsigned int tmu_tclk1_a_mux[] = {
+   TCLK1_A_MARK,
+};
+static const unsigned int tmu_tclk1_b_pins[] = {
+   /* TCLK */
+   RCAR_GP_PIN(5, 19),
+};
+static const unsigned int tmu_tclk1_b_mux[] = {
+   TCLK1_B_MARK,
+};
+static const unsigned int tmu_tclk2_a_pins[] = {
+   /* TCLK */
+   RCAR_GP_PIN(6, 19),
+};
+static const unsigned int tmu_tclk2_a_mux[] = {
+   TCLK2_A_MARK,
+};
+static const unsigned int tmu_tclk2_b_pins[] = {
+   /* TCLK */
+   RCAR_GP_PIN(6, 28),
+};
+static const unsigned int tmu_tclk2_b_mux[] = {
+   TCLK2_B_MARK,
+};
+
 /* - USB0 --- 
*/
 static const unsigned int usb0_pins[] = {
/* PWEN, OVC */
@@ -4190,6 +4220,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(ssi9_data_b),
SH_PFC_PIN_GROUP(ssi9_ctrl_a),
SH_PFC_PIN_GROUP(ssi9_ctrl_b),
+   SH_PFC_PIN_GROUP(tmu_tclk1_a),
+   SH_PFC_PIN_GROUP(tmu_tclk1_b),
+   SH_PFC_PIN_GROUP(tmu_tclk2_a),
+   SH_PFC_PIN_GROUP(tmu_tclk2_b),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb2),
@@ -4639,6 +4673,13 @@ static const char * const ssi_groups[] = {
"ssi9_ctrl_b",
 };
 
+static const char * const tmu_groups[] = {
+   "tmu_tclk1_a",
+   "tmu_tclk1_b",
+   "tmu_tclk2_a",
+   "tmu_tclk2_b",
+};
+
 static const char * const usb0_groups[] = {
"usb0",
 };
@@ -4705,6 +4746,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(sdhi2),
SH_PFC_FUNCTION(sdhi3),
SH_PFC_FUNCTION(ssi),
+   SH_PFC_FUNCTION(tmu),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(usb2),
-- 
2.7.4

[PATCH 0/3] pinctrl: sh-pfc: add TMU pins

[Ulrich Hecht]

Hi!

Straight from the BSP, TMU pins for r8a7795{,-es1} and r8a7796. Magic
numbers verified according to "pinfunction" document revisions 0.54 (M3-W)
and 0.553 (H3).

CU
Uli


Takeshi Kihara (3):
  pinctrl: sh-pfc: r8a7795: Add TMU pins, groups and functions
  pinctrl: sh-pfc: r8a7795-es1: Add TMU pins, groups and functions
  pinctrl: sh-pfc: r8a7796: Add TMU pins, groups and functions

 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 42 
 drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 42 
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 42 
 3 files changed, 126 insertions(+)

-- 
2.7.4

[PATCH 3/3] pinctrl: sh-pfc: r8a7796: Add TMU pins, groups and functions

[Ulrich Hecht]

From: Takeshi Kihara <takeshi.kihara...@renesas.com>

This patch adds TMU TCLK{1,2} pins, groups and functions to
the R8A7796 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 42 
 1 file changed, 42 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index e5807d1..f32483c 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -3827,6 +3827,36 @@ static const unsigned int ssi9_ctrl_b_mux[] = {
SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
 };
 
+/* - TMU  
*/
+static const unsigned int tmu_tclk1_a_pins[] = {
+   /* TCLK */
+   RCAR_GP_PIN(6, 23),
+};
+static const unsigned int tmu_tclk1_a_mux[] = {
+   TCLK1_A_MARK,
+};
+static const unsigned int tmu_tclk1_b_pins[] = {
+   /* TCLK */
+   RCAR_GP_PIN(5, 19),
+};
+static const unsigned int tmu_tclk1_b_mux[] = {
+   TCLK1_B_MARK,
+};
+static const unsigned int tmu_tclk2_a_pins[] = {
+   /* TCLK */
+   RCAR_GP_PIN(6, 19),
+};
+static const unsigned int tmu_tclk2_a_mux[] = {
+   TCLK2_A_MARK,
+};
+static const unsigned int tmu_tclk2_b_pins[] = {
+   /* TCLK */
+   RCAR_GP_PIN(6, 28),
+};
+static const unsigned int tmu_tclk2_b_mux[] = {
+   TCLK2_B_MARK,
+};
+
 /* - USB0 --- 
*/
 static const unsigned int usb0_pins[] = {
/* PWEN, OVC */
@@ -4159,6 +4189,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(ssi9_data_b),
SH_PFC_PIN_GROUP(ssi9_ctrl_a),
SH_PFC_PIN_GROUP(ssi9_ctrl_b),
+   SH_PFC_PIN_GROUP(tmu_tclk1_a),
+   SH_PFC_PIN_GROUP(tmu_tclk1_b),
+   SH_PFC_PIN_GROUP(tmu_tclk2_a),
+   SH_PFC_PIN_GROUP(tmu_tclk2_b),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb30),
@@ -4601,6 +4635,13 @@ static const char * const ssi_groups[] = {
"ssi9_ctrl_b",
 };
 
+static const char * const tmu_groups[] = {
+   "tmu_tclk1_a",
+   "tmu_tclk1_b",
+   "tmu_tclk2_a",
+   "tmu_tclk2_b",
+};
+
 static const char * const usb0_groups[] = {
"usb0",
 };
@@ -4658,6 +4699,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(sdhi2),
SH_PFC_FUNCTION(sdhi3),
SH_PFC_FUNCTION(ssi),
+   SH_PFC_FUNCTION(tmu),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(usb30),
-- 
2.7.4

[PATCH 2/3] pinctrl: sh-pfc: r8a7795-es1: Add TMU pins, groups and functions

[Ulrich Hecht]

From: Takeshi Kihara <takeshi.kihara...@renesas.com>

This patch adds TMU TCLK{1,2} pins, groups and functions to
the R8A7795 ES1.x SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 42 
 1 file changed, 42 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
index 292e35d..0f81802 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
@@ -3750,6 +3750,36 @@ static const unsigned int ssi9_ctrl_b_mux[] = {
SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
 };
 
+/* - TMU  
*/
+static const unsigned int tmu_tclk1_a_pins[] = {
+   /* TCLK */
+   RCAR_GP_PIN(6, 23),
+};
+static const unsigned int tmu_tclk1_a_mux[] = {
+   TCLK1_A_MARK,
+};
+static const unsigned int tmu_tclk1_b_pins[] = {
+   /* TCLK */
+   RCAR_GP_PIN(5, 19),
+};
+static const unsigned int tmu_tclk1_b_mux[] = {
+   TCLK1_B_MARK,
+};
+static const unsigned int tmu_tclk2_a_pins[] = {
+   /* TCLK */
+   RCAR_GP_PIN(6, 19),
+};
+static const unsigned int tmu_tclk2_a_mux[] = {
+   TCLK2_A_MARK,
+};
+static const unsigned int tmu_tclk2_b_pins[] = {
+   /* TCLK */
+   RCAR_GP_PIN(6, 28),
+};
+static const unsigned int tmu_tclk2_b_mux[] = {
+   TCLK2_B_MARK,
+};
+
 /* - USB0 --- 
*/
 static const unsigned int usb0_pins[] = {
/* PWEN, OVC */
@@ -4095,6 +4125,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(ssi9_data_b),
SH_PFC_PIN_GROUP(ssi9_ctrl_a),
SH_PFC_PIN_GROUP(ssi9_ctrl_b),
+   SH_PFC_PIN_GROUP(tmu_tclk1_a),
+   SH_PFC_PIN_GROUP(tmu_tclk1_b),
+   SH_PFC_PIN_GROUP(tmu_tclk2_a),
+   SH_PFC_PIN_GROUP(tmu_tclk2_b),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb2),
@@ -4545,6 +4579,13 @@ static const char * const ssi_groups[] = {
"ssi9_ctrl_b",
 };
 
+static const char * const tmu_groups[] = {
+   "tmu_tclk1_a",
+   "tmu_tclk1_b",
+   "tmu_tclk2_a",
+   "tmu_tclk2_b",
+};
+
 static const char * const usb0_groups[] = {
"usb0",
 };
@@ -4613,6 +4654,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(sdhi2),
SH_PFC_FUNCTION(sdhi3),
SH_PFC_FUNCTION(ssi),
+   SH_PFC_FUNCTION(tmu),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(usb2),
-- 
2.7.4

[PATCH 0/3] pinctrl: sh-pfc: add HDMI pins

[Ulrich Hecht]

Hi!

Straight from the BSP, HDMI pins for r8a7795{,-es1} and r8a7796. Magic
numbers verified according to "pinfunction" document revisions 0.54 (M3-W)
and 0.553 (H3).

CU
Uli


Takeshi Kihara (3):
  pinctrl: sh-pfc: r8a7795: Add HDMI pins, groups and functions
  pinctrl: sh-pfc: r8a7795-es1: Add HDMI pins, groups and functions
  pinctrl: sh-pfc: r8a7796: Add HDMI pins, groups and functions

 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 30 +-
 drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 28 
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 15 +++
 3 files changed, 72 insertions(+), 1 deletion(-)

-- 
2.7.4

[PATCH 3/3] pinctrl: sh-pfc: r8a7796: Add HDMI pins, groups and functions

[Ulrich Hecht]

From: Takeshi Kihara <takeshi.kihara...@renesas.com>

This patch adds HDMI0 CEC pin, group and function to the R8A7796 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index e5807d1..b15326d 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -2129,6 +2129,15 @@ static const unsigned int du_disp_mux[] = {
DU_DISP_MARK,
 };
 
+/* - HDMI --- 
*/
+static const unsigned int hdmi0_cec_pins[] = {
+   /* HDMI0_CEC */
+   RCAR_GP_PIN(7, 2),
+};
+static const unsigned int hdmi0_cec_mux[] = {
+   HDMI0_CEC_MARK,
+};
+
 /* - HSCIF0 - 
*/
 static const unsigned int hscif0_data_pins[] = {
/* RX, TX */
@@ -3926,6 +3935,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(du_oddf),
SH_PFC_PIN_GROUP(du_cde),
SH_PFC_PIN_GROUP(du_disp),
+   SH_PFC_PIN_GROUP(hdmi0_cec),
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(hscif0_ctrl),
@@ -4272,6 +4282,10 @@ static const char * const du_groups[] = {
"du_disp",
 };
 
+static const char * const hdmi0_groups[] = {
+   "hdmi0_cec",
+};
+
 static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_clk",
@@ -4626,6 +4640,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
SH_PFC_FUNCTION(du),
+   SH_PFC_FUNCTION(hdmi0),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hscif2),
-- 
2.7.4

[PATCH 1/3] pinctrl: sh-pfc: r8a7795: Add HDMI pins, groups and functions

[Ulrich Hecht]

From: Takeshi Kihara <takeshi.kihara...@renesas.com>

This patch adds HDMI0 CEC pin, group and function to the R8A7795 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
[uli: fixed typo in comment]
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 28 
 1 file changed, 28 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 18aeee5..7e7bf86 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -2128,6 +2128,22 @@ static const unsigned int du_disp_mux[] = {
DU_DISP_MARK,
 };
 
+/* - HDMI --- 
*/
+static const unsigned int hdmi0_cec_pins[] = {
+   /* HDMI0_CEC */
+   RCAR_GP_PIN(7, 2),
+};
+static const unsigned int hdmi0_cec_mux[] = {
+   HDMI0_CEC_MARK,
+};
+static const unsigned int hdmi1_cec_pins[] = {
+   /* HDMI1_CEC */
+   RCAR_GP_PIN(7, 3),
+};
+static const unsigned int hdmi1_cec_mux[] = {
+   HDMI1_CEC_MARK,
+};
+
 /* - HSCIF0 - 
*/
 static const unsigned int hscif0_data_pins[] = {
/* RX, TX */
@@ -3955,6 +3971,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(du_oddf),
SH_PFC_PIN_GROUP(du_cde),
SH_PFC_PIN_GROUP(du_disp),
+   SH_PFC_PIN_GROUP(hdmi0_cec),
+   SH_PFC_PIN_GROUP(hdmi1_cec),
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(hscif0_ctrl),
@@ -4305,6 +4323,14 @@ static const char * const du_groups[] = {
"du_disp",
 };
 
+static const char * const hdmi0_groups[] = {
+   "hdmi0_cec",
+};
+
+static const char * const hdmi1_groups[] = {
+   "hdmi1_cec",
+};
+
 static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_clk",
@@ -4672,6 +4698,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
SH_PFC_FUNCTION(du),
+   SH_PFC_FUNCTION(hdmi0),
+   SH_PFC_FUNCTION(hdmi1),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hscif2),
-- 
2.7.4

[PATCH 2/3] pinctrl: sh-pfc: r8a7796: Fix MOD_SEL register pin assignment for SSI pins group

[Ulrich Hecht]

From: Takeshi Kihara <takeshi.kihara...@renesas.com>

This patch fixes MOD_SEL1 bit20 and MOD_SEL2 bit20, bit21 pin assignment
for SSI pins group.

This is a correction to the incorrect implementation of MOD_SEL register
pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.51E or later.

Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 40 ++--
 1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index e5807d1..74ee483 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -1,7 +1,7 @@
 /*
  * R8A7796 processor support - PFC hardware block.
  *
- * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2016-2017 Renesas Electronics Corp.
  *
  * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
  *
@@ -477,7 +477,7 @@ FM(IP16_31_28)  IP16_31_28  FM(IP17_31_28)  
IP17_31_28
 #define MOD_SEL1_26FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0)FM(SEL_SSP1_1_1)
FM(SEL_SSP1_1_2)FM(SEL_SSP1_1_3)
 #define MOD_SEL1_23_22_21  FM(SEL_SSP1_0_0)FM(SEL_SSP1_0_1)
FM(SEL_SSP1_0_2)FM(SEL_SSP1_0_3)FM(SEL_SSP1_0_4)F_(0, 
0)F_(0, 0)F_(0, 0)
-#define MOD_SEL1_20FM(SEL_SSI_0)   FM(SEL_SSI_1)
+#define MOD_SEL1_20FM(SEL_SSI1_0)  FM(SEL_SSI1_1)
 #define MOD_SEL1_19FM(SEL_SPEED_PULSE_0)   FM(SEL_SPEED_PULSE_1)
 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0)   FM(SEL_SIMCARD_1)   
FM(SEL_SIMCARD_2)   FM(SEL_SIMCARD_3)
 #define MOD_SEL1_16FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
@@ -1218,7 +1218,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D,   SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A,   SEL_ADG_B_0),
-   PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B,   SEL_SSI_1),
+   PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B,   SEL_SSI1_1),
PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D,  SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D,  SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
@@ -1226,14 +1226,14 @@ static const u16 pinmux_data[] = {
 
PINMUX_IPSR_GPSR(IP13_15_12,HRX0),
PINMUX_IPSR_MSEL(IP13_15_12,MSIOF1_RXD_D,   SEL_MSIOF1_3),
-   PINMUX_IPSR_MSEL(IP13_15_12,SSI_SDATA2_B,   SEL_SSI_1),
+   PINMUX_IPSR_MSEL(IP13_15_12,SSI_SDATA2_B,   SEL_SSI2_1),
PINMUX_IPSR_MSEL(IP13_15_12,TS_SDEN0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_15_12,STP_ISEN_0_D,   SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_15_12,RIF0_D0_C,  SEL_DRIF0_2),
 
PINMUX_IPSR_GPSR(IP13_19_16,HTX0),
PINMUX_IPSR_MSEL(IP13_19_16,MSIOF1_TXD_D,   SEL_MSIOF1_3),
-   PINMUX_IPSR_MSEL(IP13_19_16,SSI_SDATA9_B,   SEL_SSI_1),
+   PINMUX_IPSR_MSEL(IP13_19_16,SSI_SDATA9_B,   SEL_SSI9_1),
PINMUX_IPSR_MSEL(IP13_19_16,TS_SDAT0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_19_16,STP_ISD_0_D,SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_19_16,RIF0_D1_C,  SEL_DRIF0_2),
@@ -1241,7 +1241,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP13_23_20,HCTS0_N),
PINMUX_IPSR_MSEL(IP13_23_20,RX2_B,  SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP13_23_20,MSIOF1_SYNC_D,  SEL_MSIOF1_3),
-   PINMUX_IPSR_MSEL(IP13_23_20,SSI_SCK9_A, SEL_SSI_0),
+   PINMUX_IPSR_MSEL(IP13_23_20,SSI_SCK9_A, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP13_23_20,TS_SPSYNC0_D,   SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_23_20,STP_ISSYNC_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_23_20,RIF0_SYNC_C,SEL_DRIF0_2),
@@ -1250,7 +1250,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP13_27_24,HRTS0_N),
PINMUX_IPSR_MSEL(IP13_27_24,TX2_B,  SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP13_27_24,MSIOF1_SS1_D,   SEL_MSIOF1_3),
-   PINMUX_IPSR_MSEL(IP13_27_24,SSI_WS9_A,  SEL_SSI_0),
+   PINMUX_IPSR_MSEL(IP13_27_24,SSI_WS9_A,  SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP13_27_24,STP_IVCXO27_0_D,SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_27_24,BPFC

[PATCH 1/3] pinctrl: sh-pfc: r8a7795: Fix MOD_SEL register pin assignment for SSI pins group

[Ulrich Hecht]

From: Takeshi Kihara <takeshi.kihara...@renesas.com>

This patch fixes MOD_SEL1 bit20 and MOD_SEL2 bit20, bit21 pin assignment
for SSI pins group.

This is a correction because MOD_SEL register specification for R8A7795
ES2.0 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E.

Fixes: b205914c8f82 ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0")
Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 40 ++--
 1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 18aeee5..edbf136 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -1,7 +1,7 @@
 /*
  * R8A7795 ES2.0+ processor support - PFC hardware block.
  *
- * Copyright (C) 2015-2016 Renesas Electronics Corporation
+ * Copyright (C) 2015-2017 Renesas Electronics Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -472,7 +472,7 @@ FM(IP16_31_28)  IP16_31_28  FM(IP17_31_28)  
IP17_31_28
 #define MOD_SEL1_26FM(SEL_TIMER_TMU1_0)FM(SEL_TIMER_TMU1_1)
 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0)FM(SEL_SSP1_1_1)
FM(SEL_SSP1_1_2)FM(SEL_SSP1_1_3)
 #define MOD_SEL1_23_22_21  FM(SEL_SSP1_0_0)FM(SEL_SSP1_0_1)
FM(SEL_SSP1_0_2)FM(SEL_SSP1_0_3)FM(SEL_SSP1_0_4)F_(0, 
0)F_(0, 0)F_(0, 0)
-#define MOD_SEL1_20FM(SEL_SSI_0)   FM(SEL_SSI_1)
+#define MOD_SEL1_20FM(SEL_SSI1_0)  FM(SEL_SSI1_1)
 #define MOD_SEL1_19FM(SEL_SPEED_PULSE_0)   FM(SEL_SPEED_PULSE_1)
 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0)   FM(SEL_SIMCARD_1)   
FM(SEL_SIMCARD_2)   FM(SEL_SIMCARD_3)
 #define MOD_SEL1_16FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
@@ -1218,7 +1218,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D,   SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A,   SEL_ADG_B_0),
-   PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B,   SEL_SSI_1),
+   PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B,   SEL_SSI1_1),
PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D,  SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D,  SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
@@ -1226,14 +1226,14 @@ static const u16 pinmux_data[] = {
 
PINMUX_IPSR_GPSR(IP13_15_12,HRX0),
PINMUX_IPSR_MSEL(IP13_15_12,MSIOF1_RXD_D,   SEL_MSIOF1_3),
-   PINMUX_IPSR_MSEL(IP13_15_12,SSI_SDATA2_B,   SEL_SSI_1),
+   PINMUX_IPSR_MSEL(IP13_15_12,SSI_SDATA2_B,   SEL_SSI2_1),
PINMUX_IPSR_MSEL(IP13_15_12,TS_SDEN0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_15_12,STP_ISEN_0_D,   SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_15_12,RIF0_D0_C,  SEL_DRIF0_2),
 
PINMUX_IPSR_GPSR(IP13_19_16,HTX0),
PINMUX_IPSR_MSEL(IP13_19_16,MSIOF1_TXD_D,   SEL_MSIOF1_3),
-   PINMUX_IPSR_MSEL(IP13_19_16,SSI_SDATA9_B,   SEL_SSI_1),
+   PINMUX_IPSR_MSEL(IP13_19_16,SSI_SDATA9_B,   SEL_SSI9_1),
PINMUX_IPSR_MSEL(IP13_19_16,TS_SDAT0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_19_16,STP_ISD_0_D,SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_19_16,RIF0_D1_C,  SEL_DRIF0_2),
@@ -1241,7 +1241,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP13_23_20,HCTS0_N),
PINMUX_IPSR_MSEL(IP13_23_20,RX2_B,  SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP13_23_20,MSIOF1_SYNC_D,  SEL_MSIOF1_3),
-   PINMUX_IPSR_MSEL(IP13_23_20,SSI_SCK9_A, SEL_SSI_0),
+   PINMUX_IPSR_MSEL(IP13_23_20,SSI_SCK9_A, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP13_23_20,TS_SPSYNC0_D,   SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_23_20,STP_ISSYNC_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_23_20,RIF0_SYNC_C,SEL_DRIF0_2),
@@ -1250,7 +1250,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP13_27_24,HRTS0_N),
PINMUX_IPSR_MSEL(IP13_27_24,TX2_B,  SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP13_27_24,MSIOF1_SS1_D,   SEL_MSIOF1_3),
-   PINMUX_IPSR_MSEL(IP13_27_24,SSI_WS9_A,  SEL_SSI_0),
+   PINMUX_IPSR_MSEL(IP13_27_24,SSI_WS9_A,  SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP13_27_24,STP_IVCX

[PATCH 2/3] pinctrl: sh-pfc: r8a7795-es1: Add HDMI pins, groups and functions

[Ulrich Hecht]

From: Takeshi Kihara <takeshi.kihara...@renesas.com>

This patch adds HDMI0 CEC pin, group and function to
the R8A7795 ES1.x SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
[uli: fixed typo in comment]
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 30 +-
 1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
index 292e35d..81bfcaf 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
@@ -1,7 +1,7 @@
 /*
  * R8A7795 ES1.x processor support - PFC hardware block.
  *
- * Copyright (C) 2015  Renesas Electronics Corporation
+ * Copyright (C) 2015-2017  Renesas Electronics Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -2067,6 +2067,22 @@ static const unsigned int du_disp_pins[] = {
 static const unsigned int du_disp_mux[] = {
DU_DISP_MARK,
 };
+/* - HDMI --- 
*/
+static const unsigned int hdmi0_cec_pins[] = {
+   /* HDMI0_CEC */
+   RCAR_GP_PIN(7, 2),
+};
+static const unsigned int hdmi0_cec_mux[] = {
+   HDMI0_CEC_MARK,
+};
+static const unsigned int hdmi1_cec_pins[] = {
+   /* HDMI1_CEC */
+   RCAR_GP_PIN(7, 3),
+};
+static const unsigned int hdmi1_cec_mux[] = {
+   HDMI1_CEC_MARK,
+};
+
 /* - HSCIF0 - 
*/
 static const unsigned int hscif0_data_pins[] = {
/* RX, TX */
@@ -3865,6 +3881,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(du_oddf),
SH_PFC_PIN_GROUP(du_cde),
SH_PFC_PIN_GROUP(du_disp),
+   SH_PFC_PIN_GROUP(hdmi0_cec),
+   SH_PFC_PIN_GROUP(hdmi1_cec),
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(hscif0_ctrl),
@@ -4210,6 +4228,14 @@ static const char * const du_groups[] = {
"du_disp",
 };
 
+static const char * const hdmi0_groups[] = {
+   "hdmi0_cec",
+};
+
+static const char * const hdmi1_groups[] = {
+   "hdmi1_cec",
+};
+
 static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_clk",
@@ -4578,6 +4604,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
SH_PFC_FUNCTION(du),
+   SH_PFC_FUNCTION(hdmi0),
+   SH_PFC_FUNCTION(hdmi1),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hscif2),
-- 
2.7.4

[PATCH 0/3] pinctrl: sh-pfc: r8a7795,6: Fix pin assignment definitions

[Ulrich Hecht]

Hi!

This series contains fixes to the PFC register definitions for r8a7795 and
r8a7796 from the BSP that are not upstream yet.
As far as I could tell, these changes check out with the Gen3 datasheet
revision 0.80.

CU
Uli


Takeshi Kihara (3):
  pinctrl: sh-pfc: r8a7795: Fix MOD_SEL register pin assignment for SSI
pins group
  pinctrl: sh-pfc: r8a7796: Fix MOD_SEL register pin assignment for SSI
pins group
  pinctrl: sh-pfc: r8a7796: Fix IPSR and MOD_SEL register pin assignment
for NDFC pins group

 drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 40 -
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 58 +++-
 2 files changed, 51 insertions(+), 47 deletions(-)

-- 
2.7.4

[PATCH 3/3] pinctrl: sh-pfc: r8a7796: Fix IPSR and MOD_SEL register pin assignment for NDFC pins group

[Ulrich Hecht]

From: Takeshi Kihara <takeshi.kihara...@renesas.com>

This patch fixes to set IPSR and MOD_SEL when using NFDATA{14,15}_A and
NF{RB,WP}_N_A pin function is selected. And renamess MOD_SEL2 bit22 value
definition name to SEL_NDFC.

This is a correction to the incorrect implementation of MOD_SEL register
pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.53E.

Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 18 +++---
 1 file changed, 11 insertions(+), 7 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 74ee483..48f371e 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -502,7 +502,7 @@ FM(IP16_31_28)  IP16_31_28  FM(IP17_31_28)  
IP17_31_28
 #define MOD_SEL2_28_27 FM(SEL_FM_0)FM(SEL_FM_1)
FM(SEL_FM_2)FM(SEL_FM_3)
 #define MOD_SEL2_26FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
 #define MOD_SEL2_25_24_23  FM(SEL_I2C6_0)  FM(SEL_I2C6_1)  
FM(SEL_I2C6_2)  F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)
-#define MOD_SEL2_22FM(SEL_NDF_0)   FM(SEL_NDF_1)
+#define MOD_SEL2_22FM(SEL_NDFC_0)  FM(SEL_NDFC_1)
 #define MOD_SEL2_21FM(SEL_SSI2_0)  FM(SEL_SSI2_1)
 #define MOD_SEL2_20FM(SEL_SSI9_0)  FM(SEL_SSI9_1)
 #define MOD_SEL2_19FM(SEL_TIMER_TMU2_0)FM(SEL_TIMER_TMU2_1)
@@ -1016,35 +1016,35 @@ static const u16 pinmux_data[] = {
 
PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G,  SEL_MSIOF1_6),
-   PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B,   SEL_NDF_1),
+   PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B,   SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A,   SEL_SIMCARD_0),
PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B,SEL_SSP1_1_1),
 
PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G,   SEL_MSIOF1_6),
-   PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B,   SEL_NDF_1),
+   PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B,   SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B,  SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B,  SEL_SSP1_1_1),
 
PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G,   SEL_MSIOF1_6),
-   PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
+   PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B,   SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
 
PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G,   SEL_MSIOF1_6),
-   PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
+   PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B,SEL_SSP1_1_1),
 
PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G,   SEL_MSIOF1_6),
-   PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B,   SEL_NDF_1),
+   PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B,   SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B,   SEL_SSP1_1_1),
 
@@ -1110,16 +1110,20 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP11_7_4,  NFCLE),
 
PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
+   PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
 
PINMUX_IPSR_GPSR(IP11_15_12,SD0_WP),
+   PINMUX_IPSR_MSEL(IP11_15_12,NFDATA15_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_15_12,SDA2_B, SEL_I2C2_1),
 
PINMUX_IPSR_GPSR(IP11_19_16,SD1_CD),
+   PINMUX_IPSR_MSEL(IP11_19_16,NFRB_N_A,   SEL_NDFC_0),
   

[PATCH] serial: sh-sci: use hrtimer for receive timeout

[Ulrich Hecht]

High latencies of classic timers cause performance issues for high-
speed serial transmissions. This patch transforms rx_timer into an
hrtimer to reduce the minimum latency.

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 drivers/tty/serial/sh-sci.c | 47 +
 1 file changed, 30 insertions(+), 17 deletions(-)

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index d9f399c..553f30c 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -33,6 +33,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -143,8 +144,8 @@ struct sci_port {
void*rx_buf[2];
size_t  buf_len_rx;
struct work_struct  work_tx;
-   struct timer_list   rx_timer;
-   unsigned intrx_timeout;
+   struct hrtimer  rx_timer;
+   unsigned intrx_timeout; /* microseconds */
 #endif
unsigned intrx_frame;
int rx_trigger;
@@ -1229,6 +1230,15 @@ static void sci_rx_dma_release(struct sci_port *s, bool 
enable_pio)
}
 }
 
+static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
+{
+   long sec = usec / 100;
+   long nsec = (usec % 100) * 1000;
+   ktime_t t = ktime_set(sec, nsec);
+
+   hrtimer_start(hrt, t, HRTIMER_MODE_REL);
+}
+
 static void sci_dma_rx_complete(void *arg)
 {
struct sci_port *s = arg;
@@ -1247,7 +1257,7 @@ static void sci_dma_rx_complete(void *arg)
if (active >= 0)
count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
 
-   mod_timer(>rx_timer, jiffies + s->rx_timeout);
+   start_hrtimer_us(>rx_timer, s->rx_timeout);
 
if (count)
tty_flip_buffer_push(>state->port);
@@ -1391,9 +1401,9 @@ static void work_fn_tx(struct work_struct *work)
dma_async_issue_pending(chan);
 }
 
-static void rx_timer_fn(struct timer_list *t)
+static enum hrtimer_restart rx_timer_fn(struct hrtimer *t)
 {
-   struct sci_port *s = from_timer(s, t, rx_timer);
+   struct sci_port *s = container_of(t, struct sci_port, rx_timer);
struct dma_chan *chan = s->chan_rx;
struct uart_port *port = >port;
struct dma_tx_state state;
@@ -1410,7 +1420,7 @@ static void rx_timer_fn(struct timer_list *t)
active = sci_dma_rx_find_active(s);
if (active < 0) {
spin_unlock_irqrestore(>lock, flags);
-   return;
+   return HRTIMER_NORESTART;
}
 
status = dmaengine_tx_status(s->chan_rx, s->active_rx, );
@@ -1420,7 +1430,7 @@ static void rx_timer_fn(struct timer_list *t)
s->active_rx, active);
 
/* Let packet complete handler take care of the packet */
-   return;
+   return HRTIMER_NORESTART;
}
 
dmaengine_pause(chan);
@@ -1435,7 +1445,7 @@ static void rx_timer_fn(struct timer_list *t)
if (status == DMA_COMPLETE) {
spin_unlock_irqrestore(>lock, flags);
dev_dbg(port->dev, "Transaction complete after DMA engine was 
stopped");
-   return;
+   return HRTIMER_NORESTART;
}
 
/* Handle incomplete DMA receive */
@@ -1460,6 +1470,8 @@ static void rx_timer_fn(struct timer_list *t)
serial_port_out(port, SCSCR, scr | SCSCR_RIE);
 
spin_unlock_irqrestore(>lock, flags);
+
+   return HRTIMER_NORESTART;
 }
 
 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
@@ -1571,7 +1583,8 @@ static void sci_request_dma(struct uart_port *port)
dma += s->buf_len_rx;
}
 
-   timer_setup(>rx_timer, rx_timer_fn, 0);
+   hrtimer_init(>rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+   s->rx_timer.function = rx_timer_fn;
 
if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
sci_submit_rx(s);
@@ -1630,9 +1643,9 @@ static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
/* Clear current interrupt */
serial_port_out(port, SCxSR,
ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
-   dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
+   dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
jiffies, s->rx_timeout);
-   mod_timer(>rx_timer, jiffies + s->rx_timeout);
+   start_hrtimer_us(>rx_timer, s->rx_timeout);
 
return IRQ_HANDLED;
}
@@ -1643,7 +1656,7 @@ static irqreturn_t sci_rx_interrupt(int irq, v

[PATCH] serial: sh-sci: prevent lockup on full TTY buffers

[Ulrich Hecht]

When the TTY buffers fill up to the configured maximum, a system lockup
occurs:

[  598.820128] INFO: rcu_preempt detected stalls on CPUs/tasks:
[  598.825796]  0-...!: (1 GPs behind) idle=5a6/2/0 softirq=1974/1974 fqs=1
[  598.832577]  (detected by 3, t=62517 jiffies, g=296, c=295, q=126)
[  598.838755] Task dump for CPU 0:
[  598.841977] swapper/0   R  running task0 0  0 0x0022
[  598.849023] Call trace:
[  598.851476]  __switch_to+0x98/0xb0
[  598.854870](null)

This can be prevented by doing a dummy read of the RX data register.

This issue affects both HSCIF and SCIF ports. Reported for R-Car H3 ES2.0;
reproduced and fixed on H3 ES1.1. Probably affects other R-Car platforms
as well.

Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda...@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 drivers/tty/serial/sh-sci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index d9f399c..db2ebec 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -885,6 +885,8 @@ static void sci_receive_chars(struct uart_port *port)
/* Tell the rest of the system the news. New characters! */
tty_flip_buffer_push(tport);
} else {
+   /* TTY buffers full; read from RX reg to prevent lockup */
+   serial_port_in(port, SCxRDR);
serial_port_in(port, SCxSR); /* dummy read */
sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
}
-- 
2.7.4

[PATCH 0/4] r8a779{5,6,95} VIN and DU pin control tables

[Ulrich Hecht]

Hi!

This series adds pin control tables for VIN4 (H3, M3-W, D3), VIN5 (H3, M3-W)
and DU (D3).

The patches for M3-W and H3 are identical, so there is no need to review
both of them in detail.

[The last patch overlaps with a concurrently developed PFC patch for DU on
D3 ("[PATCH 1/8] pinctrl: sh-pfc: r8a77995: Add DU support") posted earlier
today by kbingham in his "[PATCH 0/8] r8a77995 D3 DU and LVDS support"
series.]

CU
Uli


Ulrich Hecht (4):
  pinctrl: sh-pfc: r8a7796: Add VIN4, VIN5 pins, groups and functions
  pinctrl: sh-pfc: r8a7795: Add VIN4, VIN5 pins, groups and functions
  pinctrl: sh-pfc: r8a77995: Add VIN4 pins, groups and function
  pinctrl: sh-pfc: r8a77995: Add DU pins, groups and function

 drivers/pinctrl/sh-pfc/pfc-r8a7795.c  | 454 ++
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c  | 454 ++
 drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 293 ++
 3 files changed, 1201 insertions(+)

-- 
2.7.4

[PATCH 2/4] pinctrl: sh-pfc: r8a7795: Add VIN4, VIN5 pins, groups and functions

[Ulrich Hecht]

This patch adds VIN4 and VIN5 pins, groups and functions for the
R8A7795 SoC.

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 454 +++
 1 file changed, 454 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 18aeee5..8bd29ec 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -3882,6 +3882,400 @@ static const unsigned int usb30_mux[] = {
USB30_PWEN_MARK, USB30_OVC_MARK,
 };
 
+/* - VIN4 --- 
*/
+static const unsigned int vin4_data8_a_pins[] = {
+   RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+   RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+   RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+   RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+};
+static const unsigned int vin4_data8_a_mux[] = {
+   VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+   VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+   VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+   VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+};
+static const unsigned int vin4_data8_b_pins[] = {
+   RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+   RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+   RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+   RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+};
+static const unsigned int vin4_data8_b_mux[] = {
+   VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
+   VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+   VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+   VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+};
+static const unsigned int vin4_data10_a_pins[] = {
+   RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+   RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+   RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+   RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+   RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+};
+static const unsigned int vin4_data10_a_mux[] = {
+   VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+   VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+   VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+   VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+   VI4_DATA8_MARK,  VI4_DATA9_MARK,
+};
+static const unsigned int vin4_data10_b_pins[] = {
+   RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+   RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+   RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+   RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+   RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+};
+static const unsigned int vin4_data10_b_mux[] = {
+   VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
+   VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+   VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+   VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+   VI4_DATA8_MARK,  VI4_DATA9_MARK,
+};
+static const unsigned int vin4_data12_a_pins[] = {
+   RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+   RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+   RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+   RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+   RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+   RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+};
+static const unsigned int vin4_data12_a_mux[] = {
+   VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+   VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+   VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+   VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+   VI4_DATA8_MARK,  VI4_DATA9_MARK,
+   VI4_DATA10_MARK, VI4_DATA11_MARK,
+};
+static const unsigned int vin4_data12_b_pins[] = {
+   RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+   RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+   RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+   RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+   RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+   RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+};
+static const unsigned int vin4_data12_b_mux[] = {
+   VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
+   VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+   VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+   VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+   VI4_DATA8_MARK,  VI4_DATA9_MARK,
+   VI4_DATA10_MARK, VI4_DATA11_MARK,
+};
+static const unsigned int vin4_data16_a_pins[] = {
+   RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+   RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+   RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+   RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+   RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+   RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+   RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+   RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+};
+static const unsigned int vin4_data16_a_mux[] = {
+   VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+   VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+   VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+   VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+   VI4_DATA8_MARK,  VI4_DATA9_MARK,
+   VI4_DATA10_MARK, VI4_DATA11_MARK,
+   VI4_DATA12_MARK, VI4_DATA13_MARK,
+   VI4_DATA14_MARK, VI4_DATA15_MARK,
+};
+static const unsigned int vin4_data16_b_pins[] = {
+   RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+   RCAR_GP_PIN(2, 2), RCAR_GP_PI

[PATCH 1/4] pinctrl: sh-pfc: r8a7796: Add VIN4, VIN5 pins, groups and functions

[Ulrich Hecht]

This patch adds VIN4 and VIN5 pins, groups and functions for the
R8A7796 SoC.

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 454 +++
 1 file changed, 454 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index e5807d1..0ad8750 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -3853,6 +3853,400 @@ static const unsigned int usb30_mux[] = {
USB30_PWEN_MARK, USB30_OVC_MARK,
 };
 
+/* - VIN4 --- 
*/
+static const unsigned int vin4_data8_a_pins[] = {
+   RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+   RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+   RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+   RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+};
+static const unsigned int vin4_data8_a_mux[] = {
+   VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+   VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+   VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+   VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+};
+static const unsigned int vin4_data8_b_pins[] = {
+   RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+   RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+   RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+   RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+};
+static const unsigned int vin4_data8_b_mux[] = {
+   VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
+   VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+   VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+   VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+};
+static const unsigned int vin4_data10_a_pins[] = {
+   RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+   RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+   RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+   RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+   RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+};
+static const unsigned int vin4_data10_a_mux[] = {
+   VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+   VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+   VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+   VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+   VI4_DATA8_MARK,  VI4_DATA9_MARK,
+};
+static const unsigned int vin4_data10_b_pins[] = {
+   RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+   RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+   RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+   RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+   RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+};
+static const unsigned int vin4_data10_b_mux[] = {
+   VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
+   VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+   VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+   VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+   VI4_DATA8_MARK,  VI4_DATA9_MARK,
+};
+static const unsigned int vin4_data12_a_pins[] = {
+   RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+   RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+   RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+   RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+   RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+   RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+};
+static const unsigned int vin4_data12_a_mux[] = {
+   VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+   VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+   VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+   VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+   VI4_DATA8_MARK,  VI4_DATA9_MARK,
+   VI4_DATA10_MARK, VI4_DATA11_MARK,
+};
+static const unsigned int vin4_data12_b_pins[] = {
+   RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+   RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+   RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+   RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+   RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+   RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+};
+static const unsigned int vin4_data12_b_mux[] = {
+   VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
+   VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
+   VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
+   VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
+   VI4_DATA8_MARK,  VI4_DATA9_MARK,
+   VI4_DATA10_MARK, VI4_DATA11_MARK,
+};
+static const unsigned int vin4_data16_a_pins[] = {
+   RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+   RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+   RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+   RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+   RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+   RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+   RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+   RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+};
+static const unsigned int vin4_data16_a_mux[] = {
+   VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
+   VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
+   VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
+   VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
+   VI4_DATA8_MARK,  VI4_DATA9_MARK,
+   VI4_DATA10_MARK, VI4_DATA11_MARK,
+   VI4_DATA12_MARK, VI4_DATA13_MARK,
+   VI4_DATA14_MARK, VI4_DATA15_MARK,
+};
+static const unsigned int vin4_data16_b_pins[] = {
+   RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+   RCAR_GP_PIN(2, 2), RCAR_GP_PI

[PATCH 3/4] pinctrl: sh-pfc: r8a77995: Add VIN4 pins, groups and function

[Ulrich Hecht]

This patch adds VIN4 pins, groups and function for the
R8A77995 (D3) SoC.

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 192 ++
 1 file changed, 192 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
index a4927b7..f11edf1 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
@@ -1545,6 +1545,172 @@ static const unsigned int usb0_mux[] = {
USB0_PWEN_MARK, USB0_OVC_MARK,
 };
 
+/* - VIN4 --- 
*/
+static const unsigned int vin4_data8_pins[] = {
+   RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+   RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
+   RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
+   RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+};
+static const unsigned int vin4_data8_mux[] = {
+   VI4_DATA0_MARK, VI4_DATA1_MARK,
+   VI4_DATA2_MARK, VI4_DATA3_MARK,
+   VI4_DATA4_MARK, VI4_DATA5_MARK,
+   VI4_DATA6_MARK, VI4_DATA7_MARK,
+};
+static const unsigned int vin4_data10_pins[] = {
+   RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+   RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
+   RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
+   RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+   RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
+};
+static const unsigned int vin4_data10_mux[] = {
+   VI4_DATA0_MARK, VI4_DATA1_MARK,
+   VI4_DATA2_MARK, VI4_DATA3_MARK,
+   VI4_DATA4_MARK, VI4_DATA5_MARK,
+   VI4_DATA6_MARK, VI4_DATA7_MARK,
+   VI4_DATA8_MARK,  VI4_DATA9_MARK,
+};
+static const unsigned int vin4_data12_pins[] = {
+   RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+   RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
+   RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
+   RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+   RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
+   RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
+};
+static const unsigned int vin4_data12_mux[] = {
+   VI4_DATA0_MARK, VI4_DATA1_MARK,
+   VI4_DATA2_MARK, VI4_DATA3_MARK,
+   VI4_DATA4_MARK, VI4_DATA5_MARK,
+   VI4_DATA6_MARK, VI4_DATA7_MARK,
+   VI4_DATA8_MARK,  VI4_DATA9_MARK,
+   VI4_DATA10_MARK, VI4_DATA11_MARK,
+};
+static const unsigned int vin4_data16_pins[] = {
+   RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+   RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
+   RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
+   RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+   RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
+   RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
+   RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
+   RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
+};
+static const unsigned int vin4_data16_mux[] = {
+   VI4_DATA0_MARK, VI4_DATA1_MARK,
+   VI4_DATA2_MARK, VI4_DATA3_MARK,
+   VI4_DATA4_MARK, VI4_DATA5_MARK,
+   VI4_DATA6_MARK, VI4_DATA7_MARK,
+   VI4_DATA8_MARK,  VI4_DATA9_MARK,
+   VI4_DATA10_MARK, VI4_DATA11_MARK,
+   VI4_DATA12_MARK, VI4_DATA13_MARK,
+   VI4_DATA14_MARK, VI4_DATA15_MARK,
+};
+static const unsigned int vin4_data18_pins[] = {
+   RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+   RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
+   RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
+   RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+   RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
+   RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
+   RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
+   RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
+   RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
+};
+static const unsigned int vin4_data18_mux[] = {
+   VI4_DATA0_MARK, VI4_DATA1_MARK,
+   VI4_DATA2_MARK, VI4_DATA3_MARK,
+   VI4_DATA4_MARK, VI4_DATA5_MARK,
+   VI4_DATA6_MARK, VI4_DATA7_MARK,
+   VI4_DATA8_MARK,  VI4_DATA9_MARK,
+   VI4_DATA10_MARK, VI4_DATA11_MARK,
+   VI4_DATA12_MARK, VI4_DATA13_MARK,
+   VI4_DATA14_MARK, VI4_DATA15_MARK,
+   VI4_DATA16_MARK, VI4_DATA17_MARK,
+};
+static const unsigned int vin4_data20_pins[] = {
+   RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
+   RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
+   RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
+   RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+   RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
+   RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
+   RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
+   RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
+   RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
+   RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
+};
+static const unsigned int vin4_data20_mux[] = {
+   VI4_DATA0_MARK, VI4_DATA1_MARK,
+   VI4_DATA2_MARK, VI4_DATA3_MARK,
+   VI4_DATA4_MARK, VI4_DATA5_MARK,
+   VI4_DATA6_MARK, VI4_DATA7_MARK,
+   VI4_DATA8_MARK,  VI4_DATA9_MARK,
+   VI4_DATA10_MARK, VI4_DATA11_MARK,
+   VI4_DATA12_MARK, VI4_DATA13_MARK,
+   VI4_DATA14_MARK, VI4_DATA15_MARK,
+   VI4_DATA16_MARK, VI4_DATA17_MARK,
+   VI4_DATA18_MARK, VI4_DATA19_MARK,
+};
+static const un

[PATCH 4/4] pinctrl: sh-pfc: r8a77995: Add DU pins, groups and function

[Ulrich Hecht]

This patch adds DU pins, groups and function for the R8A77995 (D3) SoC.

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 101 ++
 1 file changed, 101 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
index f11edf1..27b9417 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
@@ -1114,6 +1114,87 @@ static const unsigned int canfd1_data_mux[] = {
CANFD1_TX_MARK, CANFD1_RX_MARK,
 };
 
+/* - DU - 
*/
+static const unsigned int du_rgb666_pins[] = {
+   /* R[7:2], G[7:2], B[7:2] */
+   RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
+   RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
+   RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
+   RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
+   RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
+   RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
+};
+static const unsigned int du_rgb666_mux[] = {
+   DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
+   DU_DR3_MARK, DU_DR2_MARK,
+   DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
+   DU_DG3_MARK, DU_DG2_MARK,
+   DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
+   DU_DB3_MARK, DU_DB2_MARK,
+};
+static const unsigned int du_rgb888_pins[] = {
+   /* R[7:0], G[7:0], B[7:0] */
+   RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
+   RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
+   RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
+   RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
+   RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
+   RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 8),
+   RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
+   RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
+   RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
+};
+static const unsigned int du_rgb888_mux[] = {
+   DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
+   DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
+   DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
+   DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
+   DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
+   DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
+};
+static const unsigned int du_clk_in_1_pins[] = {
+   /* CLKIN */
+   RCAR_GP_PIN(1, 28),
+};
+static const unsigned int du_clk_in_1_mux[] = {
+   DU_DOTCLKIN1_MARK
+};
+static const unsigned int du_clk_out_0_pins[] = {
+   /* CLKOUT */
+   RCAR_GP_PIN(1, 24),
+};
+static const unsigned int du_clk_out_0_mux[] = {
+   DU_DOTCLKOUT0_MARK
+};
+static const unsigned int du_sync_pins[] = {
+   /* VSYNC, HSYNC */
+   RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
+};
+static const unsigned int du_sync_mux[] = {
+   DU_VSYNC_MARK, DU_HSYNC_MARK
+};
+static const unsigned int du_disp_cde_pins[] = {
+   /* DISP_CDE */
+   RCAR_GP_PIN(1, 28),
+};
+static const unsigned int du_disp_cde_mux[] = {
+   DU_DISP_CDE_MARK,
+};
+static const unsigned int du_cde_pins[] = {
+   /* CDE */
+   RCAR_GP_PIN(1, 29),
+};
+static const unsigned int du_cde_mux[] = {
+   DU_CDE_MARK,
+};
+static const unsigned int du_disp_pins[] = {
+   /* DISP */
+   RCAR_GP_PIN(1, 27),
+};
+static const unsigned int du_disp_mux[] = {
+   DU_DISP_MARK,
+};
+
 /* - I2C  
*/
 static const unsigned int i2c0_pins[] = {
/* SCL, SDA */
@@ -1734,6 +1815,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(can_clk),
SH_PFC_PIN_GROUP(canfd0_data),
SH_PFC_PIN_GROUP(canfd1_data),
+   SH_PFC_PIN_GROUP(du_rgb666),
+   SH_PFC_PIN_GROUP(du_rgb888),
+   SH_PFC_PIN_GROUP(du_clk_in_1),
+   SH_PFC_PIN_GROUP(du_clk_out_0),
+   SH_PFC_PIN_GROUP(du_sync),
+   SH_PFC_PIN_GROUP(du_disp_cde),
+   SH_PFC_PIN_GROUP(du_cde),
+   SH_PFC_PIN_GROUP(du_disp),
SH_PFC_PIN_GROUP(i2c0),
SH_PFC_PIN_GROUP(i2c1),
SH_PFC_PIN_GROUP(i2c2_a),
@@ -1841,6 +1930,17 @@ static const char * const canfd1_groups[] = {
"canfd1_data",
 };
 
+static const char * const du_groups[] = {
+   "du_rgb666",
+   "du_rgb888",
+   "du_clk_in_1",
+   "du_clk_out_0",
+   "du_sync",
+   "du_disp_cde",
+   "du_cde",
+   "du_disp",
+};
+
 static const char * const i2c0_groups[] = {
"i2c0",
 };
@@ -1970,6 +2070,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(can_clk),
SH_PFC_FU

[PATCH v2 1/5] arm64: renesas: r8a77995: add I2C support

[Ulrich Hecht]

Defines R-Car D3 I2C controllers 0-3.

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
 arch/arm64/boot/dts/renesas/r8a77995.dtsi | 67 +++
 1 file changed, 67 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index 23f763b..22e633c 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -536,6 +536,73 @@
status = "disabled";
};
 
+   i2c0: i2c@e650 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "renesas,i2c-r8a77995",
+"renesas,rcar-gen3-i2c";
+   reg = <0 0xe650 0 0x40>;
+   interrupts = ;
+   clocks = < CPG_MOD 931>;
+   power-domains = < R8A77995_PD_ALWAYS_ON>;
+   resets = < 931>;
+   dmas = < 0x91>, < 0x90>,
+  < 0x91>, < 0x90>;
+   dma-names = "tx", "rx", "tx", "rx";
+   i2c-scl-internal-delay-ns = <6>;
+   status = "disabled";
+   };
+
+   i2c1: i2c@e6508000 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "renesas,i2c-r8a77995",
+"renesas,rcar-gen3-i2c";
+   reg = <0 0xe6508000 0 0x40>;
+   interrupts = ;
+   clocks = < CPG_MOD 930>;
+   power-domains = < R8A77995_PD_ALWAYS_ON>;
+   resets = < 930>;
+   dmas = < 0x93>, < 0x92>,
+  < 0x93>, < 0x92>;
+   dma-names = "tx", "rx", "tx", "rx";
+   i2c-scl-internal-delay-ns = <6>;
+   status = "disabled";
+   };
+
+   i2c2: i2c@e651 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "renesas,i2c-r8a77995",
+"renesas,rcar-gen3-i2c";
+   reg = <0 0xe651 0 0x40>;
+   interrupts = ;
+   clocks = < CPG_MOD 929>;
+   power-domains = < R8A77995_PD_ALWAYS_ON>;
+   resets = < 929>;
+   dmas = < 0x95>, < 0x94>,
+  < 0x95>, < 0x94>;
+   dma-names = "tx", "rx", "tx", "rx";
+   i2c-scl-internal-delay-ns = <6>;
+   status = "disabled";
+   };
+
+   i2c3: i2c@e66d {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "renesas,i2c-r8a77995",
+"renesas,rcar-gen3-i2c";
+   reg = <0 0xe66d 0 0x40>;
+   interrupts = ;
+   clocks = < CPG_MOD 928>;
+   power-domains = < R8A77995_PD_ALWAYS_ON>;
+   resets = < 928>;
+   dmas = < 0x97>, < 0x96>;
+   dma-names = "tx", "rx";
+   i2c-scl-internal-delay-ns = <6>;
+   status = "disabled";
+   };
+
pwm0: pwm@e6e3 {
compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
reg = <0 0xe6e3 0 0x8>;
-- 
2.7.4

Re: [PATCH 5/6] arm64: renesas: draak: enable I2C controller 1

[Ulrich Hecht]

On Thu, Nov 16, 2017 at 10:31 AM, Geert Uytterhoeven
 wrote:
> If no devices are connected, perhaps it's wise to defer the status update
> to e.g. an overlay that describes what's connected to CN23?
>
> Or do you want it enabled to allow adding devices manually using
> /sys/bus/i2c/devices/i2c-1/new_device?

Indeed. It's an unpopulated bus on a development board with an
external connector, so I think it's valid to assume that it is
intended to be used for experimentation.

CU
Uli

[PATCH v2 3/5] arm64: renesas: draak: enable I2C controller 1

[Ulrich Hecht]

No devices to add, I2C1 has an external connector only.

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
 arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts 
b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
index 6ff9d3e..af07da2 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
@@ -51,6 +51,11 @@
function = "i2c0";
};
 
+   i2c1_pins: i2c1 {
+   groups = "i2c1";
+   function = "i2c1";
+   };
+
pwm0_pins: pwm0 {
groups = "pwm0_c";
function = "pwm0";
@@ -84,6 +89,12 @@
};
 };
 
+ {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+   status = "okay";
+};
+
  {
status = "okay";
 };
-- 
2.7.4

[PATCH v2 4/5] i2c: rcar: document R8A77995 bindings

[Ulrich Hecht]

R-Car D3 (R8A77995) SoC has a R-Car Gen3-compatible I2C controller.

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
 Documentation/devicetree/bindings/i2c/i2c-rcar.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt 
b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
index a777477..e91dbaf 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
@@ -14,6 +14,7 @@ Required properties:
"renesas,i2c-r8a7795" if the device is a part of a R8A7795 SoC.
"renesas,i2c-r8a7796" if the device is a part of a R8A7796 SoC.
"renesas,i2c-r8a77970" if the device is a part of a R8A77970 SoC.
+   "renesas,i2c-r8a77995" if the device is a part of a R8A77995 SoC.
"renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device.
"renesas,rcar-gen2-i2c" for a generic R-Car Gen2 or RZ/G1 compatible
device.
-- 
2.7.4

[PATCH v2 2/5] arm64: renesas: draak: enable I2C controller 0 and EEPROM

[Ulrich Hecht]

Enables EEPROM on I2C0 on the Draak board.

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
 arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 17 +
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts 
b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
index 09de73b..6ff9d3e 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
@@ -46,6 +46,11 @@
};
};
 
+   i2c0_pins: i2c0 {
+   groups = "i2c0";
+   function = "i2c0";
+   };
+
pwm0_pins: pwm0 {
groups = "pwm0_c";
function = "pwm0";
@@ -67,6 +72,18 @@
};
 };
 
+ {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+   status = "okay";
+
+   eeprom@50 {
+   compatible = "rohm,br24t01", "atmel,24c01";
+   reg = <0x50>;
+   pagesize = <8>;
+   };
+};
+
  {
status = "okay";
 };
-- 
2.7.4

[PATCH v2 5/5] dt-bindings: at24: add bindings for Rohm BR24T01

[Ulrich Hecht]

Both manufacturer and name variant.

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
 Documentation/devicetree/bindings/eeprom/at24.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/eeprom/at24.txt 
b/Documentation/devicetree/bindings/eeprom/at24.txt
index 1812c84..dd29937 100644
--- a/Documentation/devicetree/bindings/eeprom/at24.txt
+++ b/Documentation/devicetree/bindings/eeprom/at24.txt
@@ -40,6 +40,7 @@ Required properties:
 "microchip",
 "ramtron",
 "renesas",
+"rohm",
 "nxp",
 "st",
 
@@ -47,6 +48,7 @@ Required properties:
 variants of the above. Known such exceptions are listed below:
 
 "renesas,r1ex24002" - the fallback is "atmel,24c02"
+"rohm,br24t01" - the fallback is "atmel,24c01"
 
   - reg: The I2C address of the EEPROM.
 
-- 
2.7.4

[PATCH v2 0/5] R-Car D3 (r8a77995) I2C integration

[Ulrich Hecht]

Hi!

This adds I2C controllers to the D3 device tree and enables I2C busses 0
and 1 on the Draak board. (I2C2 is not connected on that board.)

This revision addresses Geert's review comments and adds Reviewed-Bys.
See below for details.

CU
Uli


Changes since v1:
- pinctrl: patch dropped, has been picked up
- i2c-rcar: patch dropped, redundant
- dtsi: added dmac2 for i2c0-2
- dtsi: fixed internal SCL delays
- dts: fixed EEPROM compatible string
- bindings: added Rohm EEPROM
- bindings: fixed typo in i2c-rcar bindings


Ulrich Hecht (5):
  arm64: renesas: r8a77995: add I2C support
  arm64: renesas: draak: enable I2C controller 0 and EEPROM
  arm64: renesas: draak: enable I2C controller 1
  i2c: rcar: document R8A77995 bindings
  dt-bindings: at24: add bindings for Rohm BR24T01

 Documentation/devicetree/bindings/eeprom/at24.txt  |  2 +
 Documentation/devicetree/bindings/i2c/i2c-rcar.txt |  1 +
 arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 28 +
 arch/arm64/boot/dts/renesas/r8a77995.dtsi  | 67 ++
 4 files changed, 98 insertions(+)

-- 
2.7.4

[PATCH v2] serdev: add method to set parity

[Ulrich Hecht]

Adds serdev_device_set_parity() and an implementation for ttyport.
The interface uses an enum with the values SERIAL_PARITY_NONE,
SERIAL_PARITY_EVEN and SERIAL_PARITY_ODD.

Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
Reviewed-by: Sebastian Reichel <sebastian.reic...@collabora.co.uk>
---

Hi!

This revision addresses Johan's comments (see below for details) and adds
Sebastian's Reviewed-by tag. Thank you for your reviews!

CU
Uli


Changes since v1:
- added Reviewed-by tag
- expanded commit message
- shuffled stuff around to keep line-setting bits together
- clear CMSPAR
- (hopefully) detect errors correctly by checking tty->termios after call
  to tty_set_termios().


 drivers/tty/serdev/core.c   | 12 
 drivers/tty/serdev/serdev-ttyport.c | 24 
 include/linux/serdev.h  | 10 ++
 3 files changed, 46 insertions(+)

diff --git a/drivers/tty/serdev/core.c b/drivers/tty/serdev/core.c
index 5dc88f6..ceee0ca 100644
--- a/drivers/tty/serdev/core.c
+++ b/drivers/tty/serdev/core.c
@@ -257,6 +257,18 @@ void serdev_device_set_flow_control(struct serdev_device 
*serdev, bool enable)
 }
 EXPORT_SYMBOL_GPL(serdev_device_set_flow_control);
 
+int serdev_device_set_parity(struct serdev_device *serdev,
+enum serdev_parity parity)
+{
+   struct serdev_controller *ctrl = serdev->ctrl;
+
+   if (!ctrl || !ctrl->ops->set_parity)
+   return -ENOTSUPP;
+
+   return ctrl->ops->set_parity(ctrl, parity);
+}
+EXPORT_SYMBOL_GPL(serdev_device_set_parity);
+
 void serdev_device_wait_until_sent(struct serdev_device *serdev, long timeout)
 {
struct serdev_controller *ctrl = serdev->ctrl;
diff --git a/drivers/tty/serdev/serdev-ttyport.c 
b/drivers/tty/serdev/serdev-ttyport.c
index a5abb05..fa16729 100644
--- a/drivers/tty/serdev/serdev-ttyport.c
+++ b/drivers/tty/serdev/serdev-ttyport.c
@@ -194,6 +194,29 @@ static void ttyport_set_flow_control(struct 
serdev_controller *ctrl, bool enable
tty_set_termios(tty, );
 }
 
+static int ttyport_set_parity(struct serdev_controller *ctrl,
+ enum serdev_parity parity)
+{
+   struct serport *serport = serdev_controller_get_drvdata(ctrl);
+   struct tty_struct *tty = serport->tty;
+   struct ktermios ktermios = tty->termios;
+
+   ktermios.c_cflag &= ~(PARENB | PARODD | CMSPAR);
+   if (parity != SERDEV_PARITY_NONE) {
+   ktermios.c_cflag |= PARENB;
+   if (parity == SERDEV_PARITY_ODD)
+   ktermios.c_cflag |= PARODD;
+   }
+
+   tty_set_termios(tty, );
+
+   if ((tty->termios.c_cflag & (PARENB | PARODD | CMSPAR)) !=
+   (ktermios.c_cflag & (PARENB | PARODD | CMSPAR)))
+   return -EINVAL;
+
+   return 0;
+}
+
 static void ttyport_wait_until_sent(struct serdev_controller *ctrl, long 
timeout)
 {
struct serport *serport = serdev_controller_get_drvdata(ctrl);
@@ -231,6 +254,7 @@ static const struct serdev_controller_ops ctrl_ops = {
.open = ttyport_open,
.close = ttyport_close,
.set_flow_control = ttyport_set_flow_control,
+   .set_parity = ttyport_set_parity,
.set_baudrate = ttyport_set_baudrate,
.wait_until_sent = ttyport_wait_until_sent,
.get_tiocm = ttyport_get_tiocm,
diff --git a/include/linux/serdev.h b/include/linux/serdev.h
index 48d8ce2..f153b2c 100644
--- a/include/linux/serdev.h
+++ b/include/linux/serdev.h
@@ -78,6 +78,12 @@ static inline struct serdev_device_driver 
*to_serdev_device_driver(struct device
return container_of(d, struct serdev_device_driver, driver);
 }
 
+enum serdev_parity {
+   SERDEV_PARITY_NONE,
+   SERDEV_PARITY_EVEN,
+   SERDEV_PARITY_ODD,
+};
+
 /*
  * serdev controller structures
  */
@@ -88,6 +94,7 @@ struct serdev_controller_ops {
int (*open)(struct serdev_controller *);
void (*close)(struct serdev_controller *);
void (*set_flow_control)(struct serdev_controller *, bool);
+   int (*set_parity)(struct serdev_controller *, enum serdev_parity);
unsigned int (*set_baudrate)(struct serdev_controller *, unsigned int);
void (*wait_until_sent)(struct serdev_controller *, long);
int (*get_tiocm)(struct serdev_controller *);
@@ -301,6 +308,9 @@ static inline int serdev_device_set_rts(struct 
serdev_device *serdev, bool enabl
return serdev_device_set_tiocm(serdev, 0, TIOCM_RTS);
 }
 
+int serdev_device_set_parity(struct serdev_device *serdev,
+enum serdev_parity parity);
+
 /*
  * serdev hooks into TTY core
  */
-- 
2.7.4