Re: [PATCH] arm64: dts: renesas: r8a77980: add SMP support

[Simon Horman]

On Tue, May 22, 2018 at 11:49:36AM +0200, Geert Uytterhoeven wrote:
> On Tue, May 22, 2018 at 10:54 AM, Simon Horman <ho...@verge.net.au> wrote:
> > On Sat, May 19, 2018 at 08:38:13PM +0300, Sergei Shtylyov wrote:
> >> On 05/17/2018 11:23 PM, Geert Uytterhoeven wrote:
> >>
> >> >> Add the device nodes for 3 more Cortex-A53 CPU cores; adjust the 
> >> >> interrupt
> >> >> delivery masks for the ARM GIC and Architectured Timer.
> >> >>
> >> >> Based on the original (and large) patch by Vladimir Barinov.
> >> >>
> >> >> Signed-off-by: Vladimir Barinov <vladimir.bari...@cogentembedded.com>
> >> >> Signed-off-by: Sergei Shtylyov <sergei.shtyl...@cogentembedded.com>
> >> >
> >> > Thanks for your patch!
> >> >
> >> >> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> >> >> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> >> >> @@ -30,6 +30,36 @@
> >> >> enable-method = "psci";
> >> >> };
> >> >>
> >> >> +   a53_1: cpu@1 {
> >> >> +   device_type = "cpu";
> >> >> +   compatible = "arm,cortex-a53","arm,armv8";
> >> >
> >> > Please stop copying spaceless lists ;-)
> >>
> >>Oops! Simon, do I need to re-post?
> >
> > No, but Geert, are you otherwise ok with this patch?
> 
> Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>

Thanks, I have applied the following:

From: Sergei Shtylyov <sergei.shtyl...@cogentembedded.com>
Subject: [PATCH] arm64: dts: renesas: r8a77980: add SMP support

Add the device nodes for 3 more Cortex-A53 CPU cores; adjust the interrupt
delivery masks for the ARM GIC and Architectured Timer.

Based on the original (and large) patch by Vladimir Barinov.

Signed-off-by: Vladimir Barinov <vladimir.bari...@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtyl...@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
[simon: corrected whitespace]
Signed-off-by: Simon Horman <horms+rene...@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a77980.dtsi | 40 +++
 1 file changed, 35 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
index 4c40f9f0ebc9..6d2b61d83caf 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -30,6 +30,36 @@
enable-method = "psci";
};
 
+   a53_1: cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53", "arm,armv8";
+   reg = <1>;
+   clocks = < CPG_CORE R8A77980_CLK_Z2>;
+   power-domains = < R8A77980_PD_CA53_CPU1>;
+   next-level-cache = <_CA53>;
+   enable-method = "psci";
+   };
+
+   a53_2: cpu@2 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53", "arm,armv8";
+   reg = <2>;
+   clocks = < CPG_CORE R8A77980_CLK_Z2>;
+   power-domains = < R8A77980_PD_CA53_CPU2>;
+   next-level-cache = <_CA53>;
+   enable-method = "psci";
+   };
+
+   a53_3: cpu@3 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53", "arm,armv8";
+   reg = <3>;
+   clocks = < CPG_CORE R8A77980_CLK_Z2>;
+   power-domains = < R8A77980_PD_CA53_CPU3>;
+   next-level-cache = <_CA53>;
+   enable-method = "psci";
+   };
+
L2_CA53: cache-controller {
compatible = "cache";
power-domains = < R8A77980_PD_CA53_SCU>;
@@ -408,7 +438,7 @@
  <0x0 0xf102 0 0x2>,
  <0x0 0xf104 0 0x2>,
  <0x0 0xf106 0 0x2>;
-   interrupts = ;
clocks = < CPG_MOD 408>;
clock-names = "clk";
@@ -4

Re: [PATCH] arm64: dts: renesas: r8a77980: add SMP support

[Simon Horman]

On Thu, May 17, 2018 at 11:19:44PM +0300, Sergei Shtylyov wrote:
> Add the device nodes for 3 more Cortex-A53 CPU cores; adjust the interrupt
> delivery masks for the ARM GIC and Architectured Timer.
> 
> Based on the original (and large) patch by Vladimir Barinov.
> 
> Signed-off-by: Vladimir Barinov 
> Signed-off-by: Sergei Shtylyov 
> 
> ---
> The patch is against the 'renesas-devel-20180516v2-v4.17-rc5' tag of Simon
> Horman's 'renesas.git' repo. Tested successfully on the V3M Starter Kit board
> (except offlining CPU0 hangs the kernel).

This looks fine but I will wait to see if there are other reviews completed
before applying.

Reviewed-by: Simon Horman 

Re: [PATCH] arm64: dts: renesas: r8a77980: add SMP support

[Simon Horman]

On Sat, May 19, 2018 at 08:38:13PM +0300, Sergei Shtylyov wrote:
> On 05/17/2018 11:23 PM, Geert Uytterhoeven wrote:
> 
> >> Add the device nodes for 3 more Cortex-A53 CPU cores; adjust the interrupt
> >> delivery masks for the ARM GIC and Architectured Timer.
> >>
> >> Based on the original (and large) patch by Vladimir Barinov.
> >>
> >> Signed-off-by: Vladimir Barinov 
> >> Signed-off-by: Sergei Shtylyov 
> > 
> > Thanks for your patch!
> > 
> >> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> >> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> >> @@ -30,6 +30,36 @@
> >> enable-method = "psci";
> >> };
> >>
> >> +   a53_1: cpu@1 {
> >> +   device_type = "cpu";
> >> +   compatible = "arm,cortex-a53","arm,armv8";
> > 
> > Please stop copying spaceless lists ;-)
> 
>Oops! Simon, do I need to re-post?

No, but Geert, are you otherwise ok with this patch?

Re: [PATCH] arm64: dts: renesas: r8a77980: add SMP support

[Sergei Shtylyov]

On 05/17/2018 11:23 PM, Geert Uytterhoeven wrote:

>> Add the device nodes for 3 more Cortex-A53 CPU cores; adjust the interrupt
>> delivery masks for the ARM GIC and Architectured Timer.
>>
>> Based on the original (and large) patch by Vladimir Barinov.
>>
>> Signed-off-by: Vladimir Barinov 
>> Signed-off-by: Sergei Shtylyov 
> 
> Thanks for your patch!
> 
>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> @@ -30,6 +30,36 @@
>> enable-method = "psci";
>> };
>>
>> +   a53_1: cpu@1 {
>> +   device_type = "cpu";
>> +   compatible = "arm,cortex-a53","arm,armv8";
> 
> Please stop copying spaceless lists ;-)

   Oops! Simon, do I need to re-post?

> Gr{oetje,eeting}s,
> 
> Geert

MBR, Sergei

Re: [PATCH] arm64: dts: renesas: r8a77980: add SMP support

[Geert Uytterhoeven]

Hi Sergei,

On Thu, May 17, 2018 at 10:19 PM, Sergei Shtylyov
 wrote:
> Add the device nodes for 3 more Cortex-A53 CPU cores; adjust the interrupt
> delivery masks for the ARM GIC and Architectured Timer.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov 
> Signed-off-by: Sergei Shtylyov 

Thanks for your patch!

> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> @@ -30,6 +30,36 @@
> enable-method = "psci";
> };
>
> +   a53_1: cpu@1 {
> +   device_type = "cpu";
> +   compatible = "arm,cortex-a53","arm,armv8";

Please stop copying spaceless lists ;-)

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH] arm64: dts: renesas: r8a77980: add SMP support

[Sergei Shtylyov]

Add the device nodes for 3 more Cortex-A53 CPU cores; adjust the interrupt
delivery masks for the ARM GIC and Architectured Timer.

Based on the original (and large) patch by Vladimir Barinov.

Signed-off-by: Vladimir Barinov 
Signed-off-by: Sergei Shtylyov 

---
The patch is against the 'renesas-devel-20180516v2-v4.17-rc5' tag of Simon
Horman's 'renesas.git' repo. Tested successfully on the V3M Starter Kit board
(except offlining CPU0 hangs the kernel).

 arch/arm64/boot/dts/renesas/r8a77980.dtsi |   40 ++
 1 file changed, 35 insertions(+), 5 deletions(-)

Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -30,6 +30,36 @@
enable-method = "psci";
};
 
+   a53_1: cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53","arm,armv8";
+   reg = <1>;
+   clocks = < CPG_CORE R8A77980_CLK_Z2>;
+   power-domains = < R8A77980_PD_CA53_CPU1>;
+   next-level-cache = <_CA53>;
+   enable-method = "psci";
+   };
+
+   a53_2: cpu@2 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53","arm,armv8";
+   reg = <2>;
+   clocks = < CPG_CORE R8A77980_CLK_Z2>;
+   power-domains = < R8A77980_PD_CA53_CPU2>;
+   next-level-cache = <_CA53>;
+   enable-method = "psci";
+   };
+
+   a53_3: cpu@3 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53","arm,armv8";
+   reg = <3>;
+   clocks = < CPG_CORE R8A77980_CLK_Z2>;
+   power-domains = < R8A77980_PD_CA53_CPU3>;
+   next-level-cache = <_CA53>;
+   enable-method = "psci";
+   };
+
L2_CA53: cache-controller {
compatible = "cache";
power-domains = < R8A77980_PD_CA53_SCU>;
@@ -408,7 +438,7 @@
  <0x0 0xf102 0 0x2>,
  <0x0 0xf104 0 0x2>,
  <0x0 0xf106 0 0x2>;
-   interrupts = ;
clocks = < CPG_MOD 408>;
clock-names = "clk";
@@ -424,13 +454,13 @@
 
timer {
compatible = "arm,armv8-timer";
-   interrupts-extended = < GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
+   interrupts-extended = < GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
   IRQ_TYPE_LEVEL_LOW)>,
- < GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
+ < GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
   IRQ_TYPE_LEVEL_LOW)>,
- < GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
+ < GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
   IRQ_TYPE_LEVEL_LOW)>,
- < GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
+ < GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
   IRQ_TYPE_LEVEL_LOW)>;
};
 };