From: Takeshi Kihara
This patch adds PCI express channel 0 device node to the R8A77990 SoC
and enables PCIEC0 PCI express controller on the Ebisu board.
Signed-off-by: Takeshi Kihara
Signed-off-by: Marek Vasut
Cc: Geert Uytterhoeven
Cc: Simon Horman
Cc: Wolfram Sang
Cc: Yoshihiro Shimoda
Cc: linux-renesas-soc@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
To: devicet...@vger.kernel.org
---
.../arm64/boot/dts/renesas/r8a77990-ebisu.dts | 8 +
arch/arm64/boot/dts/renesas/r8a77990.dtsi | 34 +++
2 files changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
index 447e9831104a..2ef9067616ee 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
@@ -444,6 +444,14 @@
status = "okay";
};
+_bus_clk {
+ clock-frequency = <1>;
+};
+
+ {
+ status = "okay";
+};
+
{
avb_pins: avb {
mux {
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index a2524fc138a2..46868dacbeef 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -85,6 +85,13 @@
clock-frequency = <0>;
};
+ /* External PCIe clock - can be overridden by the board */
+ pcie_bus_clk: pcie_bus {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts-extended = < GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
@@ -1610,6 +1617,33 @@
};
};
+ pciec0: pcie@fe00 {
+ compatible = "renesas,pcie-r8a77990",
+"renesas,pcie-rcar-gen3";
+ reg = <0 0xfe00 0 0x8>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x0100 0 0x 0 0xfe10 0
0x0010
+ 0x0200 0 0xfe20 0 0xfe20 0
0x0020
+ 0x0200 0 0x3000 0 0x3000 0
0x0800
+ 0x4200 0 0x3800 0 0x3800 0
0x0800>;
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x4200 0 0x4000 0 0x4000 0
0x4000>;
+ interrupts = ,
+ ,
+ ;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 GIC_SPI 116
IRQ_TYPE_LEVEL_HIGH>;
+ clocks = < CPG_MOD 319>, <_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = < R8A77990_PD_ALWAYS_ON>;
+ resets = < 319>;
+ status = "disabled";
+ };
+
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
--
2.18.0
