Re: [PATCH 04/14] pinctrl: sh-pfc: r8a7796: Fix MOD_SEL register pin assignment for SSI pins group
Hi Kaneko-san, Kihara-san, On Sun, Jul 23, 2017 at 6:32 PM, Yoshihiro Kaneko wrote: > I'm very sorry that for the long delay in my reply. No problem. Likewise, I've been on holidays. > 2017-07-13 18:12 GMT+09:00 Geert Uytterhoeven : >> On Wed, Jul 12, 2017 at 6:55 PM, Yoshihiro Kaneko >> wrote: >>> From: Takeshi Kihara >>> >>> This patch fixes MOD_SEL1 bit20 and MOD_SEL2 bit20, bit21 pin assignment >>> for SSI pins group. >>> >>> This is a correction to the incorrect implementation of MOD_SEL register >>> pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware >>> User's Manual Rev.0.51E or later. >>> >>> Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support") >>> Signed-off-by: Takeshi Kihara >>> Signed-off-by: Yoshihiro Kaneko >>> --- >>> drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 38 >>> ++-- >>> 1 file changed, 19 insertions(+), 19 deletions(-) >>> >>> diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c >>> b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c >>> index 4d070c2..18c9c61 100644 >>> --- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c >>> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c >> >>> @@ -1277,7 +1277,7 @@ enum { >>> PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, >>> SEL_SCIF5_0), >>> PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0), >>> PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, >>> SEL_ADG_A_2), >>> - PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0), >>> + PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), >> >> The SSI_SCK2_A part seems to have been removed in Rev.052E and later? >> However, I can't find that in the errata for Rev.051E. It's the same in Rev. 0.55 (page 6-39, second row at the top), where the cell that used to contain SSI_SCK2_A is blank. Kihara-san, is the datasheet correct w.r.t. this? > Indeed, SSI_SCK2_A seems to have been removed from configuration of > SEL_SSI2 in Rev.0.52E, but the definition of IP14[3:0] does not > change. Correct. > Should I remove the entry of SSI_SCK2_A from pinmux_data[]? Please wait for that until we have confirmation about the correctness of the datasheet. Thanks! Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Re: [PATCH 04/14] pinctrl: sh-pfc: r8a7796: Fix MOD_SEL register pin assignment for SSI pins group
Hi Geert-san, I'm very sorry that for the long delay in my reply. 2017-07-13 18:12 GMT+09:00 Geert Uytterhoeven : > Hi Kaneko-san, Kihara-san, > > On Wed, Jul 12, 2017 at 6:55 PM, Yoshihiro Kaneko > wrote: >> From: Takeshi Kihara >> >> This patch fixes MOD_SEL1 bit20 and MOD_SEL2 bit20, bit21 pin assignment >> for SSI pins group. >> >> This is a correction to the incorrect implementation of MOD_SEL register >> pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware >> User's Manual Rev.0.51E or later. >> >> Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support") >> Signed-off-by: Takeshi Kihara >> Signed-off-by: Yoshihiro Kaneko >> --- >> drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 38 >> ++-- >> 1 file changed, 19 insertions(+), 19 deletions(-) >> >> diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c >> b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c >> index 4d070c2..18c9c61 100644 >> --- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c >> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c > >> @@ -1277,7 +1277,7 @@ enum { >> PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), >> PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0), >> PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2), >> - PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0), >> + PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), > > The SSI_SCK2_A part seems to have been removed in Rev.052E and later? > However, I can't find that in the errata for Rev.051E. Indeed, SSI_SCK2_A seems to have been removed from configuration of SEL_SSI2 in Rev.0.52E, but the definition of IP14[3:0] does not change. Should I remove the entry of SSI_SCK2_A from pinmux_data[]? Thanks, Kaneko > >> PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, >> SEL_SSP1_0_2), >> PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), >> PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, >> SEL_TIMER_TMU_1), > > The rest looks good to me. > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- > ge...@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like > that. > -- Linus Torvalds
Re: [PATCH 04/14] pinctrl: sh-pfc: r8a7796: Fix MOD_SEL register pin assignment for SSI pins group
Hi Kaneko-san, Kihara-san, On Wed, Jul 12, 2017 at 6:55 PM, Yoshihiro Kaneko wrote: > From: Takeshi Kihara > > This patch fixes MOD_SEL1 bit20 and MOD_SEL2 bit20, bit21 pin assignment > for SSI pins group. > > This is a correction to the incorrect implementation of MOD_SEL register > pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware > User's Manual Rev.0.51E or later. > > Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support") > Signed-off-by: Takeshi Kihara > Signed-off-by: Yoshihiro Kaneko > --- > drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 38 > ++-- > 1 file changed, 19 insertions(+), 19 deletions(-) > > diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c > b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c > index 4d070c2..18c9c61 100644 > --- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c > +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c > @@ -1277,7 +1277,7 @@ enum { > PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), > PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0), > PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2), > - PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0), > + PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), The SSI_SCK2_A part seems to have been removed in Rev.052E and later? However, I can't find that in the errata for Rev.051E. > PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C,SEL_SSP1_0_2), > PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), > PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, > SEL_TIMER_TMU_1), The rest looks good to me. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
[PATCH 04/14] pinctrl: sh-pfc: r8a7796: Fix MOD_SEL register pin assignment for SSI pins group
From: Takeshi Kihara This patch fixes MOD_SEL1 bit20 and MOD_SEL2 bit20, bit21 pin assignment for SSI pins group. This is a correction to the incorrect implementation of MOD_SEL register pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.51E or later. Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: Takeshi Kihara Signed-off-by: Yoshihiro Kaneko --- drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 38 ++-- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c index 4d070c2..18c9c61 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c @@ -480,7 +480,7 @@ #define MOD_SEL1_26FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1) #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0)FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2)FM(SEL_SSP1_1_3) #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0)FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2)FM(SEL_SSP1_0_3)FM(SEL_SSP1_0_4)F_(0, 0)F_(0, 0)F_(0, 0) -#define MOD_SEL1_20FM(SEL_SSI_0) FM(SEL_SSI_1) +#define MOD_SEL1_20FM(SEL_SSI1_0) FM(SEL_SSI1_1) #define MOD_SEL1_19FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1) #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3) #define MOD_SEL1_16FM(SEL_SDHI2_0) FM(SEL_SDHI2_1) @@ -1230,7 +1230,7 @@ enum { PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0), - PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1), PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2), @@ -1238,14 +1238,14 @@ enum { PINMUX_IPSR_GPSR(IP13_15_12,HRX0), PINMUX_IPSR_MSEL(IP13_15_12,MSIOF1_RXD_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP13_15_12,SSI_SDATA2_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP13_15_12,SSI_SDATA2_B, SEL_SSI2_1), PINMUX_IPSR_MSEL(IP13_15_12,TS_SDEN0_D, SEL_TSIF0_3), PINMUX_IPSR_MSEL(IP13_15_12,STP_ISEN_0_D, SEL_SSP1_0_3), PINMUX_IPSR_MSEL(IP13_15_12,RIF0_D0_C, SEL_DRIF0_2), PINMUX_IPSR_GPSR(IP13_19_16,HTX0), PINMUX_IPSR_MSEL(IP13_19_16,MSIOF1_TXD_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP13_19_16,SSI_SDATA9_B, SEL_SSI_1), + PINMUX_IPSR_MSEL(IP13_19_16,SSI_SDATA9_B, SEL_SSI9_1), PINMUX_IPSR_MSEL(IP13_19_16,TS_SDAT0_D, SEL_TSIF0_3), PINMUX_IPSR_MSEL(IP13_19_16,STP_ISD_0_D,SEL_SSP1_0_3), PINMUX_IPSR_MSEL(IP13_19_16,RIF0_D1_C, SEL_DRIF0_2), @@ -1253,7 +1253,7 @@ enum { PINMUX_IPSR_GPSR(IP13_23_20,HCTS0_N), PINMUX_IPSR_MSEL(IP13_23_20,RX2_B, SEL_SCIF2_1), PINMUX_IPSR_MSEL(IP13_23_20,MSIOF1_SYNC_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP13_23_20,SSI_SCK9_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP13_23_20,SSI_SCK9_A, SEL_SSI9_0), PINMUX_IPSR_MSEL(IP13_23_20,TS_SPSYNC0_D, SEL_TSIF0_3), PINMUX_IPSR_MSEL(IP13_23_20,STP_ISSYNC_0_D, SEL_SSP1_0_3), PINMUX_IPSR_MSEL(IP13_23_20,RIF0_SYNC_C,SEL_DRIF0_2), @@ -1262,7 +1262,7 @@ enum { PINMUX_IPSR_GPSR(IP13_27_24,HRTS0_N), PINMUX_IPSR_MSEL(IP13_27_24,TX2_B, SEL_SCIF2_1), PINMUX_IPSR_MSEL(IP13_27_24,MSIOF1_SS1_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP13_27_24,SSI_WS9_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP13_27_24,SSI_WS9_A, SEL_SSI9_0), PINMUX_IPSR_MSEL(IP13_27_24,STP_IVCXO27_0_D,SEL_SSP1_0_3), PINMUX_IPSR_MSEL(IP13_27_24,BPFCLK_A, SEL_FM_0), PINMUX_IPSR_GPSR(IP13_27_24,AUDIO_CLKOUT2_A), @@ -1277,7 +1277,7 @@ enum { PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0), PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2), - PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0), + PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C,