Re: [PATCH 05/11] clk: renesas: r8a77980: Add OSC predivider configuration and clock
Hi Simon,
On Thu, Jul 12, 2018 at 3:56 PM Simon Horman wrote:
> On Wed, Jul 11, 2018 at 04:20:54PM +0200, Geert Uytterhoeven wrote:
> > R-Car Gen3 Hardware Manual Rev.0.54 documents the relation between the
> > MD13 and MD14 mode pins, and the OSC EXTAL predivider, as used by the
> > OSC clock. Hence augment the configuration structure with all
> > documented predivider values.
> >
> > Add the OSC clock using the configured predivider.
> >
> > Signed-off-by: Geert Uytterhoeven
> > --- a/drivers/clk/renesas/r8a77980-cpg-mssr.c
> > +++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c
> > @@ -171,23 +173,23 @@ static const unsigned int r8a77980_crit_mod_clks[]
> > __initconst = {
> > */
> >
> > /*
> > - * MD EXTAL PLL2PLL1PLL3
> > + * MD EXTAL PLL2PLL1PLL3OSC
> > * 14 13 (MHz)
> > - * --
> > - * 0 0 16.66 x 1 x240x192x192
> > - * 0 1 20x 1 x200x160x160
> > - * 1 0 27x 1 x148x118x118
> > - * 1 1 33.33 / 2 x240x192x192
> > + *
> > + * 0 0 16.66 x 1 x240x192x192/16
> > + * 0 1 20x 1 x200x160x160/19
> > + * 1 0 27x 1 x148x118x118/24
>
> Not related to this patch, but in the Users' Manual 1.0
> EXTAL is listed as 27MHz in table 8.4e but 25MHz (below) table 8.2e.
Nice catch:
- Divider 24 is correct for 25 MHz, but not for 27 Mhz.
- Multipliers 148 and 118 are correct for 27 MHz, but not for 25 MHz.
Needs clarification...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 05/11] clk: renesas: r8a77980: Add OSC predivider configuration and clock
On Wed, Jul 11, 2018 at 04:20:54PM +0200, Geert Uytterhoeven wrote:
> R-Car Gen3 Hardware Manual Rev.0.54 documents the relation between the
> MD13 and MD14 mode pins, and the OSC EXTAL predivider, as used by the
> OSC clock. Hence augment the configuration structure with all
> documented predivider values.
>
> Add the OSC clock using the configured predivider.
>
> Signed-off-by: Geert Uytterhoeven
> ---
> drivers/clk/renesas/r8a77980-cpg-mssr.c | 24 +---
> 1 file changed, 13 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c
> b/drivers/clk/renesas/r8a77980-cpg-mssr.c
> index d7ebd9ec00594fc8..093677b8927800fa 100644
> --- a/drivers/clk/renesas/r8a77980-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c
> @@ -96,6 +96,8 @@ static const struct cpg_core_clk r8a77980_core_clks[]
> __initconst = {
> DEF_DIV6P1("canfd", R8A77980_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
> DEF_DIV6P1("csi0", R8A77980_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
> DEF_DIV6P1("mso", R8A77980_CLK_MSO, CLK_PLL1_DIV4, 0x014),
> +
> + DEF_GEN3_OSC("osc", R8A77980_CLK_OSC, CLK_EXTAL, 8),
> };
>
> static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
> @@ -171,23 +173,23 @@ static const unsigned int r8a77980_crit_mod_clks[]
> __initconst = {
> */
>
> /*
> - * MD EXTAL PLL2PLL1PLL3
> + * MD EXTAL PLL2PLL1PLL3OSC
> * 14 13 (MHz)
> - * --
> - * 0 0 16.66 x 1 x240x192x192
> - * 0 1 20x 1 x200x160x160
> - * 1 0 27x 1 x148x118x118
> - * 1 1 33.33 / 2 x240x192x192
> + *
> + * 0 0 16.66 x 1 x240x192x192/16
> + * 0 1 20x 1 x200x160x160/19
> + * 1 0 27x 1 x148x118x118/24
Not related to this patch, but in the Users' Manual 1.0
EXTAL is listed as 27MHz in table 8.4e but 25MHz (below) table 8.2e.
> + * 1 1 33.33 / 2 x240x192x192/32
> */
> #define CPG_PLL_CONFIG_INDEX(md) md) & BIT(14)) >> 13) | \
>(((md) & BIT(13)) >> 13))
>
> static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] __initconst
> = {
> - /* EXTAL divPLL1 mult/div PLL3 mult/div */
> - { 1,192,1, 192,1, },
> - { 1,160,1, 160,1, },
> - { 1,118,1, 118,1, },
> - { 2,192,1, 192,1, },
> + /* EXTAL divPLL1 mult/div PLL3 mult/div OSC prediv */
> + { 1,192,1, 192,1, 16, },
> + { 1,160,1, 160,1, 19, },
> + { 1,118,1, 118,1, 24, },
> + { 2,192,1, 192,1, 32, },
> };
>
> static int __init r8a77980_cpg_mssr_init(struct device *dev)
> --
> 2.17.1
>
[PATCH 05/11] clk: renesas: r8a77980: Add OSC predivider configuration and clock
R-Car Gen3 Hardware Manual Rev.0.54 documents the relation between the
MD13 and MD14 mode pins, and the OSC EXTAL predivider, as used by the
OSC clock. Hence augment the configuration structure with all
documented predivider values.
Add the OSC clock using the configured predivider.
Signed-off-by: Geert Uytterhoeven
---
drivers/clk/renesas/r8a77980-cpg-mssr.c | 24 +---
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c
b/drivers/clk/renesas/r8a77980-cpg-mssr.c
index d7ebd9ec00594fc8..093677b8927800fa 100644
--- a/drivers/clk/renesas/r8a77980-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c
@@ -96,6 +96,8 @@ static const struct cpg_core_clk r8a77980_core_clks[]
__initconst = {
DEF_DIV6P1("canfd", R8A77980_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
DEF_DIV6P1("csi0", R8A77980_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
DEF_DIV6P1("mso", R8A77980_CLK_MSO, CLK_PLL1_DIV4, 0x014),
+
+ DEF_GEN3_OSC("osc", R8A77980_CLK_OSC, CLK_EXTAL, 8),
};
static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
@@ -171,23 +173,23 @@ static const unsigned int r8a77980_crit_mod_clks[]
__initconst = {
*/
/*
- * MDEXTAL PLL2PLL1PLL3
+ * MDEXTAL PLL2PLL1PLL3OSC
* 14 13 (MHz)
- * --
- * 0 016.66 x 1 x240x192x192
- * 0 120x 1 x200x160x160
- * 1 027x 1 x148x118x118
- * 1 133.33 / 2 x240x192x192
+ *
+ * 0 016.66 x 1 x240x192x192/16
+ * 0 120x 1 x200x160x160/19
+ * 1 027x 1 x148x118x118/24
+ * 1 133.33 / 2 x240x192x192/32
*/
#define CPG_PLL_CONFIG_INDEX(md) md) & BIT(14)) >> 13) | \
(((md) & BIT(13)) >> 13))
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] __initconst = {
- /* EXTAL divPLL1 mult/div PLL3 mult/div */
- { 1,192,1, 192,1, },
- { 1,160,1, 160,1, },
- { 1,118,1, 118,1, },
- { 2,192,1, 192,1, },
+ /* EXTAL divPLL1 mult/div PLL3 mult/div OSC prediv */
+ { 1,192,1, 192,1, 16, },
+ { 1,160,1, 160,1, 19, },
+ { 1,118,1, 118,1, 24, },
+ { 2,192,1, 192,1, 32, },
};
static int __init r8a77980_cpg_mssr_init(struct device *dev)
--
2.17.1
