RE: [PATCH v3] Samsung: sdhci-s3c: add support for new card detection methods
Hello, On Monday, July 26, 2010 10:57 PM Andrew Morton wrote: On Thu, 22 Jul 2010 10:25:44 +0200 Marek Szyprowski m.szyprow...@samsung.com wrote: On Thursday, July 22, 2010 1:12 AM On Fri, 16 Jul 2010 08:24:26 +0200 Marek Szyprowski m.szyprow...@samsung.com wrote: arch/arm/mach-s3c64xx/setup-sdhci-gpio.c | 14 +--- arch/arm/mach-s5pc100/setup-sdhci-gpio.c | 21 ++ - arch/arm/mach-s5pv210/setup-sdhci-gpio.c | 22 +++--- -- arch/arm/plat-samsung/dev-hsmmc.c |5 arch/arm/plat-samsung/dev-hsmmc1.c |5 arch/arm/plat-samsung/dev-hsmmc2.c |5 arch/arm/plat-samsung/dev-hsmmc3.c |5 arch/arm/plat-samsung/include/plat/sdhci.h | 29 8 files changed, 90 insertions(+), 16 deletions(-) This is quite confusing. You've already sent a patch called sdhci-s3c: add support for new card detection methods. It had the same changelog as this patch and the same title, but the two patches are utterly different! The real patch has been split into two for easier merging: 1. the driver part and 2. samsung platform related part. The part which patch belongs to is indicated in the last line of the change log. I'm really confused how to submit properly a patch that requires changes to both the driver (which is merged by the proper driver maintainer's sub-tree) and the platform (which should go through platform maintainer's tree). Make the relationship very very clear in the changelog. Send both patches to both maintainers. Ask that one of them merge both patches and that the other ack both patches. Ok. Thanks for the hint. Anyway, I've forgotten what's happening here. I appear to be sitting on sdhci-s3c-add-support-for-the-non-standard-minimal-clock-value.patch This one is independent from the card-detection patches and can be applied directly onto linux-next kernel tree. and sdhci-s3c-add-support-for-new-card-detection-methods.patch the latter of which is below. Am I missing something? Is sdhci-s3c-add-support-for-new-card-detection-methods.patch up to date? Ok, I will repost these 2 patches under new names to avoid further confusion. Currently there exists two sdhci-s3c-add-support-for-new-card-detection-methods.patch, both of them are required. So the second(?) patch [PATCH v4] Samsung: add new card detection methods in s3c-sdhci driver (platform part) has already been applied to linux-next by Kukjin Kim, along with modifications which we have not been shown. But the first patch (sdhci-s3c-add-support-for-the-non-standard-minimal-clock-value.patch) has not been applied to linux-next by anoyne and the third patch [PATCH v4] sdhci-s3c: add support for new card detection methods (driver part) has not been applied either. This is a complete mess. What happens if I apply and merge sdhci-s3c-add-support-for-the-non-standard-minimal-clock-value.patch and sdhci-s3c-add-support-for-new-card-detection-methods-driver-part.patch? I have no idea. [PATCH v4] Samsung: add new card detection methods in s3c-sdhci driver (platform part) perform some important changes in platform setup code. It does not influence the driver itself (the driver can be still compiled as before and works without changes). The only changes added by Kukjin Kim were compilation fixes (looks I've forgot one include on the platform that has not been tested). This patch is also a prerequisite for [PATCH v4] sdhci-s3c: add support for new card detection methods (driver part). I think I'll just drop all of it. Please sort all of this out then let me know what you want me to do. I would to ask not for dropping. As all required platform changes has been already merged by Kukjin, s dhci-s3c-add-support-for-the-non-standard-minimal-clock-value.patch and sdhci-s3c-add-support-for-new-card-detection-methods-driver-part.patch can be merged without causing compilation break in the 'next' kernel tree. Best regards -- Marek Szyprowski Samsung Poland RD Center -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v2 3/8] ARM: S5PV310: Add Clock and PLL support
MyungJoo Ham wrote:
Hello,
Hello,
On Fri, Jul 16, 2010 at 5:58 PM, Kukjin Kim kgene@samsung.com wrote:
From: Changhwan Youn chaos.y...@samsung.com
This patch adds clock and pll support for S5PV310.
Signed-off-by: Changhwan Youn chaos.y...@samsung.com
Signed-off-by: Kukjin Kim kgene@samsung.com
---
arch/arm/mach-s5pv310/clock.c | 544
+++
arch/arm/mach-s5pv310/include/mach/regs-clock.h | 60 +++
arch/arm/plat-s5p/include/plat/pll.h| 41 ++
3 files changed, 645 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-s5pv310/clock.c
create mode 100644 arch/arm/mach-s5pv310/include/mach/regs-clock.h
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
new file mode 100644
index 000..bb671d5
--- /dev/null
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -0,0 +1,544 @@
+/* linux/arch/arm/mach-s5pv310/clock.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * S5PV310 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include linux/kernel.h
+#include linux/err.h
+#include linux/io.h
+
+#include plat/cpu-freq.h
+#include plat/clock.h
+#include plat/cpu.h
+#include plat/pll.h
+#include plat/s5p-clock.h
+#include plat/clock-clksrc.h
+
+#include mach/map.h
+#include mach/regs-clock.h
+
+static struct clk clk_sclk_hdmi27m = {
+ .name = sclk_hdmi27m,
+ .id = -1,
+ .rate = 2700,
+};
+
+/* Core list of CMU_CPU side */
+
+static struct clksrc_clk clk_mout_apll = {
+ .clk= {
+ .name = mout_apll,
+ .id = -1,
+ },
+ .sources= clk_src_apll,
+ .reg_src= { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
+ .reg_div= { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
+};
+
+static struct clksrc_clk clk_mout_epll = {
+ .clk= {
+ .name = mout_epll,
+ .id = -1,
+ },
+ .sources= clk_src_epll,
+ .reg_src= { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
+};
+
+static struct clksrc_clk clk_mout_mpll = {
+ .clk = {
+ .name = mout_mpll,
+ .id = -1,
+ },
+ .sources= clk_src_mpll,
+ .reg_src= { .reg = S5P_CLKSRC_CPU, .shift = 4, .size = 1 },
+};
S5P_CLKSRC_CPU[4] is not described in the user manual (it's
Reserved). Is it undocumented, typographical error in manual, or
typographical error in the source code? If the user manual is
correct, it appears to have the shift value of 8.
Yeah, you're righttypo...will fix it.
+
+static struct clk *clkset_moutcore_list[] = {
+ [0] = clk_mout_apll.clk,
+ [1] = clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources clkset_moutcore = {
+ .sources= clkset_moutcore_list,
+ .nr_sources = ARRAY_SIZE(clkset_moutcore_list),
+};
+
+static struct clksrc_clk clk_moutcore = {
+ .clk= {
+ .name = moutcore,
+ .id = -1,
+ },
+ .sources= clkset_moutcore,
+ .reg_src= { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk clk_coreclk = {
+ .clk= {
+ .name = core_clk,
+ .id = -1,
+ .parent = clk_moutcore.clk,
+ },
+ .reg_div= { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk clk_armclk = {
+ .clk= {
+ .name = armclk,
+ .id = -1,
+ .parent = clk_coreclk.clk,
+ },
+};
+
+static struct clksrc_clk clk_aclk_corem0 = {
+ .clk= {
+ .name = aclk_corem0,
+ .id = -1,
+ .parent = clk_coreclk.clk,
+ },
+ .reg_div= { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk clk_aclk_cores = {
+ .clk= {
+ .name = aclk_cores,
+ .id = -1,
+ .parent = clk_coreclk.clk,
+ },
+ .reg_div= { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
+};
We have two clock definitions that are identical, aclk_corem0 and
aclk_cores. Is there any reason to define the same clock source
twice? Although this is not going to make
[PATCH v4 3/8] ARM: S5PV310: Add Clock and PLL support
From: Changhwan Youn chaos.y...@samsung.com
This patch adds clock and pll support for S5PV310.
Signed-off-by: Changhwan Youn chaos.y...@samsung.com
Signed-off-by: Jongpill Lee boyko@samsung.com
Signed-off-by: Kukjin Kim kgene@samsung.com
---
NOTE: skipped v3 to avoid confusing...
Changes since v2:
-Fixed on following...
The shift bit of 'S5P_CLKSRC_CPU' register for clksrc_clk 'clk_mout_mpll'
The 'S5P_CLKSRC_CORE' register for clksrc_clk 'clk_mout_corebus'
The 'S5P_CLKSRC_TOP1' register for clksrc_clk 'clk_vpllsrc'
Added S5P_CLKSRC_CORE definition.
- Modified some wrong clock names.
- CodingStyle fixes...
arch/arm/mach-s5pv310/clock.c | 544 +++
arch/arm/mach-s5pv310/include/mach/regs-clock.h | 62 +++
arch/arm/plat-s5p/include/plat/pll.h| 41 ++
3 files changed, 647 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-s5pv310/clock.c
create mode 100644 arch/arm/mach-s5pv310/include/mach/regs-clock.h
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
new file mode 100644
index 000..59eeb46
--- /dev/null
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -0,0 +1,544 @@
+/* linux/arch/arm/mach-s5pv310/clock.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * S5PV310 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include linux/kernel.h
+#include linux/err.h
+#include linux/io.h
+
+#include plat/cpu-freq.h
+#include plat/clock.h
+#include plat/cpu.h
+#include plat/pll.h
+#include plat/s5p-clock.h
+#include plat/clock-clksrc.h
+
+#include mach/map.h
+#include mach/regs-clock.h
+
+static struct clk clk_sclk_hdmi27m = {
+ .name = sclk_hdmi27m,
+ .id = -1,
+ .rate = 2700,
+};
+
+/* Core list of CMU_CPU side */
+
+static struct clksrc_clk clk_mout_apll = {
+ .clk= {
+ .name = mout_apll,
+ .id = -1,
+ },
+ .sources= clk_src_apll,
+ .reg_src= { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
+ .reg_div= { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
+};
+
+static struct clksrc_clk clk_mout_epll = {
+ .clk= {
+ .name = mout_epll,
+ .id = -1,
+ },
+ .sources= clk_src_epll,
+ .reg_src= { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
+};
+
+static struct clksrc_clk clk_mout_mpll = {
+ .clk = {
+ .name = mout_mpll,
+ .id = -1,
+ },
+ .sources= clk_src_mpll,
+ .reg_src= { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
+};
+
+static struct clk *clkset_moutcore_list[] = {
+ [0] = clk_mout_apll.clk,
+ [1] = clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources clkset_moutcore = {
+ .sources= clkset_moutcore_list,
+ .nr_sources = ARRAY_SIZE(clkset_moutcore_list),
+};
+
+static struct clksrc_clk clk_moutcore = {
+ .clk= {
+ .name = moutcore,
+ .id = -1,
+ },
+ .sources= clkset_moutcore,
+ .reg_src= { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk clk_coreclk = {
+ .clk= {
+ .name = core_clk,
+ .id = -1,
+ .parent = clk_moutcore.clk,
+ },
+ .reg_div= { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk clk_armclk = {
+ .clk= {
+ .name = armclk,
+ .id = -1,
+ .parent = clk_coreclk.clk,
+ },
+};
+
+static struct clksrc_clk clk_aclk_corem0 = {
+ .clk= {
+ .name = aclk_corem0,
+ .id = -1,
+ .parent = clk_coreclk.clk,
+ },
+ .reg_div= { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk clk_aclk_cores = {
+ .clk= {
+ .name = aclk_cores,
+ .id = -1,
+ .parent = clk_coreclk.clk,
+ },
+ .reg_div= { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk clk_aclk_corem1 = {
+ .clk= {
+ .name = aclk_corem1,
+ .id = -1,
+ .parent = clk_coreclk.clk,
+ },
+ .reg_div= { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
+};
+
+static struct clksrc_clk clk_periphclk = {
+ .clk= {
+ .name = periphclk,
+
Re: [PATCH v2 3/8] ARM: S5PV310: Add Clock and PLL support
Hi, again.
On Tue, Jul 27, 2010 at 6:06 PM, Kukjin Kim kgene@samsung.com wrote:
MyungJoo Ham wrote:
Hello,
Hello,
On Fri, Jul 16, 2010 at 5:58 PM, Kukjin Kim kgene@samsung.com wrote:
From: Changhwan Youn chaos.y...@samsung.com
This patch adds clock and pll support for S5PV310.
Signed-off-by: Changhwan Youn chaos.y...@samsung.com
Signed-off-by: Kukjin Kim kgene@samsung.com
---
arch/arm/mach-s5pv310/clock.c | 544
+++
arch/arm/mach-s5pv310/include/mach/regs-clock.h | 60 +++
arch/arm/plat-s5p/include/plat/pll.h | 41 ++
3 files changed, 645 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-s5pv310/clock.c
create mode 100644 arch/arm/mach-s5pv310/include/mach/regs-clock.h
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
new file mode 100644
index 000..bb671d5
--- /dev/null
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -0,0 +1,544 @@
+/* linux/arch/arm/mach-s5pv310/clock.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * S5PV310 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include linux/kernel.h
+#include linux/err.h
+#include linux/io.h
+
+#include plat/cpu-freq.h
+#include plat/clock.h
+#include plat/cpu.h
+#include plat/pll.h
+#include plat/s5p-clock.h
+#include plat/clock-clksrc.h
+
+#include mach/map.h
+#include mach/regs-clock.h
+
+static struct clk clk_sclk_hdmi27m = {
+ .name = sclk_hdmi27m,
+ .id = -1,
+ .rate = 2700,
+};
+
+/* Core list of CMU_CPU side */
+
+static struct clksrc_clk clk_mout_apll = {
+ .clk = {
+ .name = mout_apll,
+ .id = -1,
+ },
+ .sources = clk_src_apll,
+ .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
+ .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3
},
+};
+
+static struct clksrc_clk clk_mout_epll = {
+ .clk = {
+ .name = mout_epll,
+ .id = -1,
+ },
+ .sources = clk_src_epll,
+ .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1
},
+};
+
+static struct clksrc_clk clk_mout_mpll = {
+ .clk = {
+ .name = mout_mpll,
+ .id = -1,
+ },
+ .sources = clk_src_mpll,
+ .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 4, .size = 1 },
+};
S5P_CLKSRC_CPU[4] is not described in the user manual (it's
Reserved). Is it undocumented, typographical error in manual, or
typographical error in the source code? If the user manual is
correct, it appears to have the shift value of 8.
Yeah, you're righttypo...will fix it.
+
+static struct clk *clkset_moutcore_list[] = {
+ [0] = clk_mout_apll.clk,
+ [1] = clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources clkset_moutcore = {
+ .sources = clkset_moutcore_list,
+ .nr_sources = ARRAY_SIZE(clkset_moutcore_list),
+};
+
+static struct clksrc_clk clk_moutcore = {
+ .clk = {
+ .name = moutcore,
+ .id = -1,
+ },
+ .sources = clkset_moutcore,
+ .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1
},
+};
+
+static struct clksrc_clk clk_coreclk = {
+ .clk = {
+ .name = core_clk,
+ .id = -1,
+ .parent = clk_moutcore.clk,
+ },
+ .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk clk_armclk = {
+ .clk = {
+ .name = armclk,
+ .id = -1,
+ .parent = clk_coreclk.clk,
+ },
+};
+
+static struct clksrc_clk clk_aclk_corem0 = {
+ .clk = {
+ .name = aclk_corem0,
+ .id = -1,
+ .parent = clk_coreclk.clk,
+ },
+ .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk clk_aclk_cores = {
+ .clk = {
+ .name = aclk_cores,
+ .id = -1,
+ .parent = clk_coreclk.clk,
+ },
+ .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
+};
We have two clock definitions that are identical, aclk_corem0 and
aclk_cores. Is
RE: [PATCH v3] Samsung: sdhci-s3c: add support for new card detection methods
Andrew Morton wrote: On Thu, 22 Jul 2010 10:25:44 +0200 Marek Szyprowski m.szyprow...@samsung.com wrote: Hello, On Thursday, July 22, 2010 1:12 AM On Fri, 16 Jul 2010 08:24:26 +0200 Marek Szyprowski m.szyprow...@samsung.com wrote: arch/arm/mach-s3c64xx/setup-sdhci-gpio.c | 14 +--- arch/arm/mach-s5pc100/setup-sdhci-gpio.c | 21 ++ - arch/arm/mach-s5pv210/setup-sdhci-gpio.c | 22 +++--- -- arch/arm/plat-samsung/dev-hsmmc.c |5 arch/arm/plat-samsung/dev-hsmmc1.c |5 arch/arm/plat-samsung/dev-hsmmc2.c |5 arch/arm/plat-samsung/dev-hsmmc3.c |5 arch/arm/plat-samsung/include/plat/sdhci.h | 29 8 files changed, 90 insertions(+), 16 deletions(-) This is quite confusing. You've already sent a patch called sdhci-s3c: add support for new card detection methods. It had the same changelog as this patch and the same title, but the two patches are utterly different! The real patch has been split into two for easier merging: 1. the driver part and 2. samsung platform related part. The part which patch belongs to is indicated in the last line of the change log. I'm really confused how to submit properly a patch that requires changes to both the driver (which is merged by the proper driver maintainer's sub-tree) and the platform (which should go through platform maintainer's tree). Make the relationship very very clear in the changelog. Send both patches to both maintainers. Ask that one of them merge both patches and that the other ack both patches. Ok. Thanks for the hint. Anyway, I've forgotten what's happening here. I appear to be sitting on sdhci-s3c-add-support-for-the-non-standard-minimal-clock-value.patch This one is independent from the card-detection patches and can be applied directly onto linux-next kernel tree. and sdhci-s3c-add-support-for-new-card-detection-methods.patch the latter of which is below. Am I missing something? Is sdhci-s3c-add-support-for-new-card-detection-methods.patch up to date? Ok, I will repost these 2 patches under new names to avoid further confusion. Currently there exists two sdhci-s3c-add-support-for-new-card-detection-methods.patch, both of them are required. So the second(?) patch [PATCH v4] Samsung: add new card detection methods in s3c-sdhci driver (platform part) has already been applied to linux-next by Kukjin Kim, along with modifications which we have not been shown. Yeah, I applied it in my tree which can be merged linux-next. But the first patch (sdhci-s3c-add-support-for-the-non-standard-minimal-clock-value.patch) has not been applied to linux-next by anoyne and the third patch [PATCH v4] sdhci-s3c: add support for new card detection methods (driver part) has not been applied either. This is a complete mess. What happens if I apply and merge sdhci-s3c-add-support-for-the-non-standard-minimal-clock-value.patch and sdhci-s3c-add-support-for-new-card-detection-methods-driver-part.patch? I have no idea. Hmm... I think I'll just drop all of it. Please sort all of this out then let me know what you want me to do. If any updates, please let me know. Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v3 3/3] sdhci-s3c: Add SDHCI_QUIRK_NO_WP_BIT quirk for Samsung SoC
Kyungmin Park wrote:
On Fri, Jul 23, 2010 at 8:56 PM, Kukjin Kim kgene@samsung.com wrote:
From: Hyuk Lee hyuk1@samsung.com
If host controller doesn't have WP pin which should be connnected with
SDMMC
card WP pin, can implement get_ro function with using the allocated
gpio.
In order to use this quirk wp_gpio in the platform data must be set.
Signed-off-by: Hyuk Lee hyuk1@samsung.com
Signed-off-by: Kukjin Kim kgene@samsung.com
---
drivers/mmc/host/sdhci-s3c.c | 43
++
drivers/mmc/host/sdhci.c | 3 ++
drivers/mmc/host/sdhci.h | 3 ++
3 files changed, 49 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index 0d25285..0b75e57 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -22,6 +22,7 @@
#include linux/mmc/host.h
+#include plat/gpio-cfg.h
#include plat/sdhci.h
#include plat/regs-sdhci.h
@@ -213,6 +214,36 @@ static void sdhci_s3c_set_clock(struct sdhci_host
*host,
unsigned int clock)
}
/**
+ * sdhci_s3c_get_ro - callback for get_ro
+ * @host: The SDHCI host being changed
+ *
+ * If the WP pin is connected with GPIO, can get the value which
indicates
+ * the card is locked or not.
+*/
+static int sdhci_s3c_get_ro(struct mmc_host *mmc)
+{
+ struct sdhci_s3c *sc;
+ struct sdhci_host *host;
+
+ host = mmc_priv(mmc);
+ sc = sdhci_priv(host);
+
+ return gpio_get_value(sc-pdata-wp_gpio);
+}
+
+/**
+ * sdhci_s3c_cfg_wp - configure GPIO for WP pin
+ * @gpio_num: GPIO number which connected with WP line from SD/MMC slot
+ *
+ * Configure GPIO for using WP line
+*/
+static void sdhci_s3c_cfg_wp(unsigned int gpio_num)
+{
+ s3c_gpio_cfgpin(gpio_num, S3C_GPIO_INPUT);
+ s3c_gpio_setpull(gpio_num, S3C_GPIO_PULL_UP);
+}
+
+/**
* sdhci_s3c_get_min_clock - callback to get minimal supported clock
value
* @host: The SDHCI host being queried
*
@@ -375,6 +406,9 @@ static int __devinit sdhci_s3c_probe(struct
platform_device *pdev)
if (pdata-cfg_gpio)
pdata-cfg_gpio(pdev, pdata-max_width);
+ if (gpio_is_valid(pdata-wp_gpio))
+ sdhci_s3c_ops.get_ro = sdhci_s3c_get_ro;
+
host-hw_name = samsung-hsmmc;
host-ops = sdhci_s3c_ops;
host-quirks = 0;
@@ -408,6 +442,15 @@ static int __devinit sdhci_s3c_probe(struct
platform_device *pdev)
host-quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
SDHCI_QUIRK_32BIT_DMA_SIZE);
+ /* Controller's WP pin donsn't connected with SD card and there
is an
+ * allocated GPIO for getting WP data form SD card, use this
quirk and
+ * send the GPIO number in pdata-wp_gpio. */
+ host-quirks |= SDHCI_QUIRK_NO_WP_BIT;
+
+ /* to configure gpio pin as a card write protection signal */
+ if (gpio_is_valid(pdata-wp_gpio))
+ sdhci_s3c_cfg_wp(pdata-wp_gpio);
+
Put it just one place like this.
if (gpio_is_valid(pdata-wp_gpio)) {
sdhci_s3c_cfg_wp(pdata-wp_gpio);
sdhci_s3c_ops.get_ro = sdhci_s3c_get_ro;
host-quirks |= SDHCI_QUIRK_NO_WP_BIT;
}
It reduce the below quirks check by one. If you add the quriks as your
patch, host-quirks are always true whether WP use or not.
Ok..thanks for your suggestion.
Will re-submit as per your comments.
Thank you,
Kyungmin Park
ret = sdhci_add_host(host);
if (ret) {
dev_err(dev, sdhci_add_host() failed\n);
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index f9ca4c6..7fba401 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1198,6 +1198,9 @@ static int sdhci_get_ro(struct mmc_host *mmc)
host = mmc_priv(mmc);
+ if ((host-quirks SDHCI_QUIRK_NO_WP_BIT) host-ops-get_ro)
+ return host-ops-get_ro(mmc);
+
spin_lock_irqsave(host-lock, flags);
if (host-flags SDHCI_DEVICE_DEAD)
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 0de8b38..dd9a233 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -247,6 +247,8 @@ struct sdhci_host {
#define SDHCI_QUIRK_MISSING_CAPS (128)
/* Controller has nonstandard clock management */
#define SDHCI_QUIRK_NONSTANDARD_MINCLOCK (129)
+/* Controller has no write-protect pin connected with SD card */
+#define SDHCI_QUIRK_NO_WP_BIT (130)
int irq; /* Device IRQ */
void __iomem * ioaddr; /* Mapped address */
@@ -321,6 +323,7 @@ struct sdhci_ops {
unsigned int (*get_max_clock)(struct sdhci_host *host);
unsigned int (*get_min_clock)(struct sdhci_host *host);
unsigned int
RE: [PATCH v3 3/3] sdhci-s3c: Add SDHCI_QUIRK_NO_WP_BIT quirk for Samsung SoC
Marek Szyprowski wrote:
Hello,
On Friday, July 23, 2010 1:57 PM Kukjin Kim wrote:
From: Hyuk Lee hyuk1@samsung.com
If host controller doesn't have WP pin which should be connnected with
SDMMC
card WP pin, can implement get_ro function with using the allocated
gpio.
In order to use this quirk wp_gpio in the platform data must be set.
Signed-off-by: Hyuk Lee hyuk1@samsung.com
Signed-off-by: Kukjin Kim kgene@samsung.com
---
drivers/mmc/host/sdhci-s3c.c | 43
++
drivers/mmc/host/sdhci.c |3 ++
drivers/mmc/host/sdhci.h |3 ++
3 files changed, 49 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index 0d25285..0b75e57 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -22,6 +22,7 @@
#include linux/mmc/host.h
+#include plat/gpio-cfg.h
#include plat/sdhci.h
#include plat/regs-sdhci.h
@@ -213,6 +214,36 @@ static void sdhci_s3c_set_clock(struct sdhci_host
*host, unsigned int clock)
}
/**
+ * sdhci_s3c_get_ro - callback for get_ro
+ * @host: The SDHCI host being changed
+ *
+ * If the WP pin is connected with GPIO, can get the value which
indicates
+ * the card is locked or not.
+*/
+static int sdhci_s3c_get_ro(struct mmc_host *mmc)
+{
+ struct sdhci_s3c *sc;
+ struct sdhci_host *host;
+
+ host = mmc_priv(mmc);
+ sc = sdhci_priv(host);
+
+ return gpio_get_value(sc-pdata-wp_gpio);
+}
+
+/**
+ * sdhci_s3c_cfg_wp - configure GPIO for WP pin
+ * @gpio_num: GPIO number which connected with WP line from SD/MMC slot
+ *
+ * Configure GPIO for using WP line
+*/
+static void sdhci_s3c_cfg_wp(unsigned int gpio_num)
+{
+ s3c_gpio_cfgpin(gpio_num, S3C_GPIO_INPUT);
+ s3c_gpio_setpull(gpio_num, S3C_GPIO_PULL_UP);
+}
+
+/**
* sdhci_s3c_get_min_clock - callback to get minimal supported clock
value
* @host: The SDHCI host being queried
*
@@ -375,6 +406,9 @@ static int __devinit sdhci_s3c_probe(struct
platform_device *pdev)
if (pdata-cfg_gpio)
pdata-cfg_gpio(pdev, pdata-max_width);
+ if (gpio_is_valid(pdata-wp_gpio))
+ sdhci_s3c_ops.get_ro = sdhci_s3c_get_ro;
+
There is still a problem here, but the opposite to the issue from V1 of
this
patch.
If one apply the current version, he would need to set pdata-wp_gpio to
-1 on
all
existing platforms to get old behavior of the driver. Leaving it as zero
means
that
the driver will try to use GPA(0) for write protection.
Adding one more field to pdata (like bool has_gpio_wp) seems to be
unavoidable
in this case imho.
Ok..thanks for your review.
Will fix it like your card detection method soon.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim kgene@samsung.com, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
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[PATCH v4 0/3] Add support WP on SMDKV210 and SDHCI_QUIRK_NO_WP_BIT quirk
This patch adds support SDMMC write protection pin on SMDKV210. Changes since v3: Addressed comments from Kyungmin Park and Marek Szyprowski - Added pdata 'bool has_gpio_wp' as per Marek - Moved new WP quirk checking as per Kyungmin Changes since v2: Addressed comments from Marek Szyprowski - modified wp_gpio checking method for support gpio number 0. - removed unnecessary checking in dev-hsmmc.c Changes since v1: Addressed comments from Ben Dooks, Maurus Cuelenaere and Kyungmin Park - just pass gpio numbers for support WP as Ben's suggestion - use the gpio layer for specific machine - use s3c_sdhcix_set_platdata() in machine_init() - removed unnecessary EXPORT_SYMBOL Note: Depends on following patch set [PATCH v2 1/2] ARM: SAMSUNG: Add device definition for HSMMC3 [PATCH v2 2/2] ARM: S5PV210: Add support HSMMC on SMDKV210 [PATCH v4] Samsung: add new card detection methods in s3c-sdhci driver (platform part) from Marek Szyprowski [PATCH v4] sdhci-s3c: add support for new card detection methods (driver part) from Marek Szyprowski And this patch set includes the following patches: -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 1/3] ARM: SAMSUNG: Add the member of platdata to implement SDMMC Write Protection
From: Hyuk Lee hyuk1@samsung.com
This patch adds the members of platdata which is wp_gpio.
The wp_gpio is a gpio_number which is connected with WP pin of SD Slot.
Signed-off-by: Hyuk Lee hyuk1@samsung.com
Signed-off-by: Kukjin Kim kgene@samsung.com
---
arch/arm/plat-samsung/dev-hsmmc.c |2 ++
arch/arm/plat-samsung/dev-hsmmc1.c |2 ++
arch/arm/plat-samsung/dev-hsmmc2.c |2 ++
arch/arm/plat-samsung/dev-hsmmc3.c |2 ++
arch/arm/plat-samsung/include/plat/sdhci.h |4
5 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-samsung/dev-hsmmc.c
b/arch/arm/plat-samsung/dev-hsmmc.c
index b0f93f1..ce06aa6 100644
--- a/arch/arm/plat-samsung/dev-hsmmc.c
+++ b/arch/arm/plat-samsung/dev-hsmmc.c
@@ -65,6 +65,8 @@ void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
set-ext_cd_cleanup = pd-ext_cd_cleanup;
set-ext_cd_gpio = pd-ext_cd_gpio;
set-ext_cd_gpio_invert = pd-ext_cd_gpio_invert;
+ set-wp_gpio = pd-wp_gpio;
+ set-has_wp_gpio = pd-has_wp_gpio;
if (pd-cfg_gpio)
set-cfg_gpio = pd-cfg_gpio;
diff --git a/arch/arm/plat-samsung/dev-hsmmc1.c
b/arch/arm/plat-samsung/dev-hsmmc1.c
index 1504fd8..d2d9f72 100644
--- a/arch/arm/plat-samsung/dev-hsmmc1.c
+++ b/arch/arm/plat-samsung/dev-hsmmc1.c
@@ -65,6 +65,8 @@ void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
set-ext_cd_cleanup = pd-ext_cd_cleanup;
set-ext_cd_gpio = pd-ext_cd_gpio;
set-ext_cd_gpio_invert = pd-ext_cd_gpio_invert;
+ set-wp_gpio = pd-wp_gpio;
+ set-has_wp_gpio = pd-has_wp_gpio;
if (pd-cfg_gpio)
set-cfg_gpio = pd-cfg_gpio;
diff --git a/arch/arm/plat-samsung/dev-hsmmc2.c
b/arch/arm/plat-samsung/dev-hsmmc2.c
index b28ef17..34b1ccd 100644
--- a/arch/arm/plat-samsung/dev-hsmmc2.c
+++ b/arch/arm/plat-samsung/dev-hsmmc2.c
@@ -66,6 +66,8 @@ void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
set-ext_cd_cleanup = pd-ext_cd_cleanup;
set-ext_cd_gpio = pd-ext_cd_gpio;
set-ext_cd_gpio_invert = pd-ext_cd_gpio_invert;
+ set-wp_gpio = pd-wp_gpio;
+ set-has_wp_gpio = pd-has_wp_gpio;
if (pd-cfg_gpio)
set-cfg_gpio = pd-cfg_gpio;
diff --git a/arch/arm/plat-samsung/dev-hsmmc3.c
b/arch/arm/plat-samsung/dev-hsmmc3.c
index 85aaf0f..9b88c99 100644
--- a/arch/arm/plat-samsung/dev-hsmmc3.c
+++ b/arch/arm/plat-samsung/dev-hsmmc3.c
@@ -69,6 +69,8 @@ void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd)
set-ext_cd_cleanup = pd-ext_cd_cleanup;
set-ext_cd_gpio = pd-ext_cd_gpio;
set-ext_cd_gpio_invert = pd-ext_cd_gpio_invert;
+ set-wp_gpio = pd-wp_gpio;
+ set-has_wp_gpio = pd-has_wp_gpio;
if (pd-cfg_gpio)
set-cfg_gpio = pd-cfg_gpio;
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h
b/arch/arm/plat-samsung/include/plat/sdhci.h
index 7c21a7c..cbf05c6 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -33,6 +33,8 @@ enum cd_types {
* @max_width: The maximum number of data bits supported.
* @host_caps: Standard MMC host capabilities bit field.
* @cd_type: Type of Card Detection method (see cd_types enum above)
+ * @wp_gpio: The gpio number using for WP.
+ * @has_wp_gpio: Check using wp_gpio or not.
* @ext_cd_init: Initialize external card detect subsystem. Called on
* sdhci-s3c driver probe when cd_type == S3C_SDHCI_CD_EXTERNAL.
* notify_func argument is a callback to the sdhci-s3c driver
@@ -62,8 +64,10 @@ struct s3c_sdhci_platdata {
char**clocks; /* set of clock sources */
+ int wp_gpio;
int ext_cd_gpio;
boolext_cd_gpio_invert;
+ boolhas_wp_gpio;
int (*ext_cd_init)(void (*notify_func)(struct platform_device *,
int state));
int (*ext_cd_cleanup)(void (*notify_func)(struct platform_device *,
--
1.6.2.5
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[PATCH v4 3/3] sdhci-s3c: Add SDHCI_QUIRK_NO_WP_BIT quirk for Samsung SoC
From: Hyuk Lee hyuk1@samsung.com
If host controller doesn't have WP pin which should be connnected with SDMMC
card WP pin, can implement get_ro function with using the allocated gpio.
In order to use this quirk wp_gpio in the platform data must be set.
Signed-off-by: Hyuk Lee hyuk1@samsung.com
Signed-off-by: Kukjin Kim kgene@samsung.com
---
drivers/mmc/host/sdhci-s3c.c | 36
drivers/mmc/host/sdhci.c |3 +++
drivers/mmc/host/sdhci.h |3 +++
3 files changed, 42 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index 0d25285..98a8ec8 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -22,6 +22,7 @@
#include linux/mmc/host.h
+#include plat/gpio-cfg.h
#include plat/sdhci.h
#include plat/regs-sdhci.h
@@ -213,6 +214,32 @@ static void sdhci_s3c_set_clock(struct sdhci_host *host,
unsigned int clock)
}
/**
+ * sdhci_s3c_get_ro - callback for get_ro
+ * @host: The SDHCI host being changed
+ *
+ * If the WP pin is connected with GPIO, can get the value which indicates
+ * the card is locked or not.
+*/
+static int sdhci_s3c_get_ro(struct mmc_host *mmc)
+{
+ struct sdhci_s3c *ourhost = to_s3c(mmc_priv(mmc));
+
+ return gpio_get_value(ourhost-pdata-wp_gpio);
+}
+
+/**
+ * sdhci_s3c_cfg_wp - configure GPIO for WP pin
+ * @gpio_num: GPIO number which connected with WP line from SD/MMC slot
+ *
+ * Configure GPIO for using WP line
+*/
+static void sdhci_s3c_cfg_wp(unsigned int gpio_num)
+{
+ s3c_gpio_cfgpin(gpio_num, S3C_GPIO_INPUT);
+ s3c_gpio_setpull(gpio_num, S3C_GPIO_PULL_UP);
+}
+
+/**
* sdhci_s3c_get_min_clock - callback to get minimal supported clock value
* @host: The SDHCI host being queried
*
@@ -408,6 +435,15 @@ static int __devinit sdhci_s3c_probe(struct
platform_device *pdev)
host-quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
SDHCI_QUIRK_32BIT_DMA_SIZE);
+ /* Controller's WP pin doesn't connected with SD card and there is an
+* allocated GPIO for getting WP data form SD card, use this quirk and
+* send the GPIO number in pdata-wp_gpio. */
+ if (gpio_is_valid(pdata-wp_gpio) pdata-has_wp_gpio) {
+ sdhci_s3c_ops.get_ro = sdhci_s3c_get_ro;
+ host-quirks |= SDHCI_QUIRK_NO_WP_BIT;
+ sdhci_s3c_cfg_wp(pdata-wp_gpio);
+ }
+
ret = sdhci_add_host(host);
if (ret) {
dev_err(dev, sdhci_add_host() failed\n);
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index f9ca4c6..7fba401 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1198,6 +1198,9 @@ static int sdhci_get_ro(struct mmc_host *mmc)
host = mmc_priv(mmc);
+ if ((host-quirks SDHCI_QUIRK_NO_WP_BIT) host-ops-get_ro)
+ return host-ops-get_ro(mmc);
+
spin_lock_irqsave(host-lock, flags);
if (host-flags SDHCI_DEVICE_DEAD)
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 0de8b38..dd9a233 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -247,6 +247,8 @@ struct sdhci_host {
#define SDHCI_QUIRK_MISSING_CAPS (128)
/* Controller has nonstandard clock management */
#define SDHCI_QUIRK_NONSTANDARD_MINCLOCK (129)
+/* Controller has no write-protect pin connected with SD card */
+#define SDHCI_QUIRK_NO_WP_BIT (130)
int irq;/* Device IRQ */
void __iomem * ioaddr; /* Mapped address */
@@ -321,6 +323,7 @@ struct sdhci_ops {
unsigned int(*get_max_clock)(struct sdhci_host *host);
unsigned int(*get_min_clock)(struct sdhci_host *host);
unsigned int(*get_timeout_clock)(struct sdhci_host *host);
+ int (*get_ro)(struct mmc_host *mmc);
};
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
--
1.6.2.5
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[PATCH v4 2/3] ARM: S5PV210: Add support SDMMC WP through EXT_INT on SMDKV210
From: Hyuk Lee hyuk1@samsung.com
S5PV210 HSMMC host controller doesn't have the Write Protection pin which
should be connnected with SDMMC card WP pin. So send the allocated GPIO number
which is connected with WP pin of SD slot in order to implement get_ro function
in sdhci-s3c.
Signed-off-by: Hyuk Lee hyuk1@samsung.com
Signed-off-by: Kukjin Kim kgene@samsung.com
---
arch/arm/mach-s5pv210/mach-smdkv210.c | 26 ++
1 files changed, 26 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c
b/arch/arm/mach-s5pv210/mach-smdkv210.c
index d20adf7..5b58278 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -12,6 +12,7 @@
#include linux/types.h
#include linux/init.h
#include linux/serial_core.h
+#include linux/gpio.h
#include asm/mach/arch.h
#include asm/mach/map.h
@@ -29,6 +30,7 @@
#include plat/ts.h
#include plat/ata.h
#include plat/keypad.h
+#include plat/sdhci.h
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL |\
@@ -118,6 +120,26 @@ static struct s3c2410_ts_mach_info s3c_ts_platform
__initdata = {
.oversampling_shift = 2,
};
+static struct s3c_sdhci_platdata smdkv210_hsmmc0_pdata __initdata = {
+ .wp_gpio= S5PV210_GPH0(7),
+ .has_wp_gpio= true,
+};
+
+static struct s3c_sdhci_platdata smdkv210_hsmmc1_pdata __initdata = {
+ .wp_gpio= S5PV210_GPH0(7),
+ .has_wp_gpio= true,
+};
+
+static struct s3c_sdhci_platdata smdkv210_hsmmc2_pdata __initdata = {
+ .wp_gpio= S5PV210_GPH3(1),
+ .has_wp_gpio= true,
+};
+
+static struct s3c_sdhci_platdata smdkv210_hsmmc3_pdata __initdata = {
+ .wp_gpio= S5PV210_GPH1(0),
+ .has_wp_gpio= true,
+};
+
static void __init smdkv210_map_io(void)
{
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -129,6 +151,10 @@ static void __init smdkv210_machine_init(void)
{
samsung_keypad_set_platdata(smdkv210_keypad_data);
s3c24xx_ts_set_platdata(s3c_ts_platform);
+ s3c_sdhci0_set_platdata(smdkv210_hsmmc0_pdata);
+ s3c_sdhci1_set_platdata(smdkv210_hsmmc1_pdata);
+ s3c_sdhci2_set_platdata(smdkv210_hsmmc2_pdata);
+ s3c_sdhci3_set_platdata(smdkv210_hsmmc3_pdata);
s3c_ide_set_platdata(smdkv210_ide_pdata);
platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices));
--
1.6.2.5
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RE: [rtc-linux] [PATCH 3/3] rtc: rtc-s3c: Add BCD register initialization codes
Wan ZongShun wrote: 2010/7/23 Kukjin Kim kgene@samsung.com: Wan ZongShun wrote: 2010/7/21 Kukjin Kim kgene@samsung.com: From: Taekgyun Ko taeggyun...@samsung.com RTC needs to be initialized when BCD registers have invalid value. Do you mean that the hardware register does not have default value? Any results if no initialized value here? Hi, Yes..I mean that it has no default value. As you know, it has to be keep the previous time value after reset..and the reset value is not defined. So, reset is no use to this RTC BCD registers, it still keep previous time value. So added check that functionality, because if it has no valid BCD value, RTC time does not move on. Of course, if we set time at that time, RTC works well...I mean just need initialize that. Okay,good patch.:) Thanks ;-) In addtion,For making sure to get valid value, it is much better to use also 'rtc_valid_tm(tm)' to check returning time value in your s3c_rtc_gettime() and s3c_rtc_getalarm(() functions. Ok..will do it later as per your suggestion. Signed-off-by: Taekgyun Ko taeggyun...@samsung.com Signed-off-by: Kukjin Kim kgene@samsung.com --- drivers/rtc/rtc-s3c.c | 14 -- 1 files changed, 12 insertions(+), 2 deletions(-) (snip) Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH v4 3/3] sdhci-s3c: Add SDHCI_QUIRK_NO_WP_BIT quirk for Samsung SoC
Hello,
On Tuesday, July 27, 2010 2:44 PM Kukjin Kim wrote:
From: Hyuk Lee hyuk1@samsung.com
If host controller doesn't have WP pin which should be connnected with
SDMMC
card WP pin, can implement get_ro function with using the allocated gpio.
In order to use this quirk wp_gpio in the platform data must be set.
Signed-off-by: Hyuk Lee hyuk1@samsung.com
Signed-off-by: Kukjin Kim kgene@samsung.com
---
drivers/mmc/host/sdhci-s3c.c | 36
drivers/mmc/host/sdhci.c |3 +++
drivers/mmc/host/sdhci.h |3 +++
3 files changed, 42 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index 0d25285..98a8ec8 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -22,6 +22,7 @@
#include linux/mmc/host.h
+#include plat/gpio-cfg.h
#include plat/sdhci.h
#include plat/regs-sdhci.h
@@ -213,6 +214,32 @@ static void sdhci_s3c_set_clock(struct sdhci_host
*host, unsigned int clock)
}
/**
+ * sdhci_s3c_get_ro - callback for get_ro
+ * @host: The SDHCI host being changed
+ *
+ * If the WP pin is connected with GPIO, can get the value which indicates
+ * the card is locked or not.
+*/
+static int sdhci_s3c_get_ro(struct mmc_host *mmc)
+{
+ struct sdhci_s3c *ourhost = to_s3c(mmc_priv(mmc));
+
+ return gpio_get_value(ourhost-pdata-wp_gpio);
+}
+
+/**
+ * sdhci_s3c_cfg_wp - configure GPIO for WP pin
+ * @gpio_num: GPIO number which connected with WP line from SD/MMC slot
+ *
+ * Configure GPIO for using WP line
+*/
+static void sdhci_s3c_cfg_wp(unsigned int gpio_num)
+{
+ s3c_gpio_cfgpin(gpio_num, S3C_GPIO_INPUT);
+ s3c_gpio_setpull(gpio_num, S3C_GPIO_PULL_UP);
+}
+
+/**
* sdhci_s3c_get_min_clock - callback to get minimal supported clock value
* @host: The SDHCI host being queried
*
@@ -408,6 +435,15 @@ static int __devinit sdhci_s3c_probe(struct
platform_device *pdev)
host-quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
SDHCI_QUIRK_32BIT_DMA_SIZE);
+ /* Controller's WP pin doesn't connected with SD card and there is an
+ * allocated GPIO for getting WP data form SD card, use this quirk
and
+ * send the GPIO number in pdata-wp_gpio. */
+ if (gpio_is_valid(pdata-wp_gpio) pdata-has_wp_gpio) {
IMHO the opposite order would make much more sense:
if (pdata-has_wp_gpio gpio_is_valid(pdata-wp_gpio))
+ sdhci_s3c_ops.get_ro = sdhci_s3c_get_ro;
+ host-quirks |= SDHCI_QUIRK_NO_WP_BIT;
+ sdhci_s3c_cfg_wp(pdata-wp_gpio);
+ }
+
ret = sdhci_add_host(host);
if (ret) {
dev_err(dev, sdhci_add_host() failed\n);
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index f9ca4c6..7fba401 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1198,6 +1198,9 @@ static int sdhci_get_ro(struct mmc_host *mmc)
host = mmc_priv(mmc);
+ if ((host-quirks SDHCI_QUIRK_NO_WP_BIT) host-ops-get_ro)
+ return host-ops-get_ro(mmc);
+
spin_lock_irqsave(host-lock, flags);
if (host-flags SDHCI_DEVICE_DEAD)
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 0de8b38..dd9a233 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -247,6 +247,8 @@ struct sdhci_host {
#define SDHCI_QUIRK_MISSING_CAPS (128)
/* Controller has nonstandard clock management */
#define SDHCI_QUIRK_NONSTANDARD_MINCLOCK (129)
+/* Controller has no write-protect pin connected with SD card */
+#define SDHCI_QUIRK_NO_WP_BIT(130)
int irq;/* Device IRQ */
void __iomem * ioaddr; /* Mapped address */
@@ -321,6 +323,7 @@ struct sdhci_ops {
unsigned int(*get_max_clock)(struct sdhci_host *host);
unsigned int(*get_min_clock)(struct sdhci_host *host);
unsigned int(*get_timeout_clock)(struct sdhci_host *host);
+ int (*get_ro)(struct mmc_host *mmc);
};
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
Otherwise looks fine.
Best regards
--
Marek Szyprowski
Samsung Poland RD Center
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Re: [PATCH v3 3/3] sdhci-s3c: Add SDHCI_QUIRK_NO_WP_BIT quirk for Samsung SoC
Op 27-07-10 13:58, Kukjin Kim schreef:
Maurus Cuelenaere wrote:
Op 23-07-10 13:56, Kukjin Kim schreef:
From: Hyuk Lee hyuk1@samsung.com
If host controller doesn't have WP pin which should be connnected with SDMMC
card WP pin, can implement get_ro function with using the allocated gpio.
In order to use this quirk wp_gpio in the platform data must be set.
Signed-off-by: Hyuk Lee hyuk1@samsung.com
Signed-off-by: Kukjin Kim kgene@samsung.com
---
drivers/mmc/host/sdhci-s3c.c | 43
++
drivers/mmc/host/sdhci.c |3 ++
drivers/mmc/host/sdhci.h |3 ++
3 files changed, 49 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index 0d25285..0b75e57 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -22,6 +22,7 @@
#include linux/mmc/host.h
+#include plat/gpio-cfg.h
#include plat/sdhci.h
#include plat/regs-sdhci.h
@@ -213,6 +214,36 @@ static void sdhci_s3c_set_clock(struct sdhci_host
*host,
unsigned int clock)
}
/**
+ * sdhci_s3c_get_ro - callback for get_ro
+ * @host: The SDHCI host being changed
+ *
+ * If the WP pin is connected with GPIO, can get the value which indicates
+ * the card is locked or not.
+*/
+static int sdhci_s3c_get_ro(struct mmc_host *mmc)
+{
+ struct sdhci_s3c *sc;
+ struct sdhci_host *host;
+
+ host = mmc_priv(mmc);
+ sc = sdhci_priv(host);
This can be done as static initializer if you reverse the order above.
Could you please kindly explain about this?
Sorry, I cannot get the exactly meaning...
+static int sdhci_s3c_get_ro(struct mmc_host *mmc)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ struct sdhci_s3c *sc = sdhci_priv(host);
--
Maurus Cuelenaere
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Re: [rtc-linux] [PATCH v2 3/3] rtc: rtc-s3c: Add BCD register initialization codes
On Tue, 27 Jul 2010 21:59:13 +0900 Kukjin Kim kgene@samsung.com wrote: From: Taekgyun Ko taeggyun...@samsung.com RTC needs to be initialized when BCD registers have invalid value. Signed-off-by: Taekgyun Ko taeggyun...@samsung.com Signed-off-by: Kukjin Kim kgene@samsung.com Acked-by: Alessandro Zummo a.zu...@towertech.it -- Best regards, Alessandro Zummo, Tower Technologies - Torino, Italy http://www.towertech.it -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [rtc-linux] [PATCH 2/2] rtc: rtc-s3c: Updates RTC driver for clock enabling support
2010/7/22 Atul Dahiya atuldahiy...@gmail.com:
On Thu, Jul 22, 2010 at 11:39 AM, Wan ZongShun mcuos@gmail.com wrote:
2010/7/21 Kukjin Kim kgene@samsung.com:
From: Atul Dahiya atul.dah...@samsung.com
This Patch updates existing Samsung RTC driver for clock enabling support.
Signed-off-by: Atul Dahiya atul.dah...@samsung.com
Signed-off-by: Kukjin Kim kgene@samsung.com
---
drivers/rtc/rtc-s3c.c | 22 ++
1 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/drivers/rtc/rtc-s3c.c b/drivers/rtc/rtc-s3c.c
index 70b68d3..c032a15 100644
--- a/drivers/rtc/rtc-s3c.c
+++ b/drivers/rtc/rtc-s3c.c
@@ -1,5 +1,8 @@
/* drivers/rtc/rtc-s3c.c
*
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
* Copyright (c) 2004,2006 Simtec Electronics
* Ben Dooks, b...@simtec.co.uk
* http://armlinux.simtec.co.uk/
@@ -39,6 +42,7 @@ enum s3c_cpu_type {
static struct resource *s3c_rtc_mem;
+static struct clk *rtc_clk;
static void __iomem *s3c_rtc_base;
static int s3c_rtc_alarmno = NO_IRQ;
static int s3c_rtc_tickno = NO_IRQ;
@@ -431,6 +435,10 @@ static int __devexit s3c_rtc_remove(struct
platform_device *dev)
s3c_rtc_setpie(dev-dev, 0);
s3c_rtc_setaie(0);
+ clk_disable(rtc_clk);
+ clk_put(rtc_clk);
+ rtc_clk = NULL;
+
iounmap(s3c_rtc_base);
release_resource(s3c_rtc_mem);
kfree(s3c_rtc_mem);
@@ -488,6 +496,16 @@ static int __devinit s3c_rtc_probe(struct
platform_device *pdev)
goto err_nomap;
}
+ rtc_clk = clk_get(pdev-dev, rtc);
Do you really need the second argument? I think the bus clock for
a device should be findable with NULL for s3c platform..
No, actually clk_get() function for s3c platform searches on the
basis of second parameter passed
so need to pass the second argument here.
Okay, good patch!
Acked-by: Wan ZongShun mcuos@gmail.com
+ if (IS_ERR(rtc_clk)) {
+ dev_err(pdev-dev, failed to find rtc clock source\n);
+ ret = PTR_ERR(rtc_clk);
+ rtc_clk = NULL;
+ goto err_clk;
+ }
+
+ clk_enable(rtc_clk);
+
/* check to see if everything is setup correctly */
s3c_rtc_enable(pdev, 1);
@@ -523,6 +541,10 @@ static int __devinit s3c_rtc_probe(struct
platform_device *pdev)
err_nortc:
s3c_rtc_enable(pdev, 0);
+ clk_disable(rtc_clk);
+ clk_put(rtc_clk);
+
+ err_clk:
iounmap(s3c_rtc_base);
err_nomap:
--
1.6.2.5
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[PATCH 1/2] ARM: S5PV210: Add audio support to Aquila
This patch the I2C board information for the WM8994 used in the Aquila
as audio codec and adds the I2C/I2S platform drivers. Additionlly, to
control power consumption have registerd the voltage consumer of WM8994
to the regulator framework. I initialize gpio settting relevant to
operation of audio codec. I explain following comment concering gpio
setting:
- CODEC_XTAL_EN : This gpio enables that the main clock is provided
to operate audio codec.
- MICBIAS_EN : This gpio enable the microphone to input analog
- ADC_EN : This gpio enable the ADC device which is used to detect
the kind of jack. (SND_JACK_HEADPHONE/HEADSET/MECHANICAL/AVOUT)
According to the kind of jack, an electric current is changed.
Signed-off-by : Chanwoo Choi cw00.c...@samsung.com
Signed-off-by : Joonyoung Shim jy0922.s...@samsung.com
Signed-off-by : Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-s5pv210/mach-aquila.c | 177 +++
1 files changed, 177 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c
b/arch/arm/mach-s5pv210/mach-aquila.c
index f0f960f..d027f9d 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -17,9 +17,11 @@
#include linux/i2c-gpio.h
#include linux/i2c/mcs.h
#include linux/mfd/max8998.h
+#include linux/mfd/wm8994/pdata.h
#include linux/gpio_keys.h
#include linux/input.h
#include linux/gpio.h
+#include linux/regulator/fixed.h
#include asm/mach/arch.h
#include asm/mach/map.h
@@ -397,6 +399,120 @@ static struct max8998_platform_data aquila_max8998_pdata
= {
};
#endif
+static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
+ {
+ .dev_name = 5-001a,
+ .supply = DBVDD,
+ }, {
+ .dev_name = 5-001a,
+ .supply = AVDD2,
+ }, {
+ .dev_name = 5-001a,
+ .supply = CPVDD,
+ },
+
+};
+
+static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
+ {
+ .dev_name = 5-001a,
+ .supply = SPKVDD1,
+ }, {
+ .dev_name = 5-001a,
+ .supply = SPKVDD2,
+ },
+};
+
+static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
+ .constraints = {
+ .always_on = 1,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage0_supplies),
+ .consumer_supplies = wm8994_fixed_voltage0_supplies,
+};
+
+static struct regulator_init_data wm8994_fixed_voltage1_init_data = {
+ .constraints = {
+ .always_on = 1,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(wm8994_fixed_voltage1_supplies),
+ .consumer_supplies = wm8994_fixed_voltage1_supplies,
+};
+
+static struct fixed_voltage_config wm8994_fixed_voltage0_config = {
+ .supply_name= VCC_1.8V_PDA,
+ .microvolts = 180,
+ .gpio = -EINVAL,
+ .init_data = wm8994_fixed_voltage0_init_data,
+};
+
+static struct fixed_voltage_config wm8994_fixed_voltage1_config = {
+ .supply_name= V_BAT,
+ .microvolts = 370,
+ .gpio = -EINVAL,
+ .init_data = wm8994_fixed_voltage1_init_data,
+};
+
+static struct platform_device wm8994_fixed_voltage0 = {
+ .name = reg-fixed-voltage,
+ .id = 0,
+ .dev= {
+ .platform_data = wm8994_fixed_voltage0_config,
+ },
+};
+
+static struct platform_device wm8994_fixed_voltage1 = {
+ .name = reg-fixed-voltage,
+ .id = 1,
+ .dev= {
+ .platform_data = wm8994_fixed_voltage1_config,
+ },
+};
+
+static struct regulator_consumer_supply wm8994_avdd1_supply = {
+ .dev_name = 5-001a,
+ .supply = AVDD1,
+};
+
+static struct regulator_consumer_supply wm8994_dcvdd_supply = {
+ .dev_name = 5-001a,
+ .supply = DCVDD,
+};
+
+static struct regulator_init_data wm8994_ldo1_data = {
+ .constraints= {
+ .name = AVDD1_3.0V,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = wm8994_avdd1_supply,
+};
+
+static struct regulator_init_data wm8994_ldo2_data = {
+ .constraints= {
+ .name = DCVDD_1.0V,
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = wm8994_dcvdd_supply,
+};
+
+static struct wm8994_pdata wm8994_platform_data = {
+ /* configure gpio1 function: 0x0001(Logic level input/output) */
+ .gpio_defaults[0] = 0x0001,
+ /* configure gpio3/4/5/7 function for AIF2 voice */
+ .gpio_defaults[2] = 0x8100,
+ .gpio_defaults[3] = 0x8100,
+ .gpio_defaults[4] = 0x8100,
+ .gpio_defaults[6] =
[PATCH 2/2] ARM: S5PV210: Add the GPIO lib
This patch add the definition of GPIO to support WM8994 audio codec on
I2C bus.
Signed-off-by : Chanwoo Choi cw00.c...@samsung.com
Signed-off-by : Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-s5pv210/include/mach/gpio.h | 10 --
1 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-s5pv210/include/mach/gpio.h
b/arch/arm/mach-s5pv210/include/mach/gpio.h
index d6461ba..33a9867 100644
--- a/arch/arm/mach-s5pv210/include/mach/gpio.h
+++ b/arch/arm/mach-s5pv210/include/mach/gpio.h
@@ -52,6 +52,8 @@
#define S5PV210_GPIO_MP01_NR (8)
#define S5PV210_GPIO_MP02_NR (4)
#define S5PV210_GPIO_MP03_NR (8)
+#define S5PV210_GPIO_MP04_NR (8)
+#define S5PV210_GPIO_MP05_NR (8)
/* GPIO bank numbers */
@@ -94,6 +96,8 @@ enum s5p_gpio_number {
S5PV210_GPIO_MP01_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J4),
S5PV210_GPIO_MP02_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP01),
S5PV210_GPIO_MP03_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP02),
+ S5PV210_GPIO_MP04_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP03),
+ S5PV210_GPIO_MP05_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP04),
};
/* S5PV210 GPIO number definitions */
@@ -127,13 +131,15 @@ enum s5p_gpio_number {
#define S5PV210_MP01(_nr) (S5PV210_GPIO_MP01_START + (_nr))
#define S5PV210_MP02(_nr) (S5PV210_GPIO_MP02_START + (_nr))
#define S5PV210_MP03(_nr) (S5PV210_GPIO_MP03_START + (_nr))
+#define S5PV210_MP04(_nr) (S5PV210_GPIO_MP04_START + (_nr))
+#define S5PV210_MP05(_nr) (S5PV210_GPIO_MP05_START + (_nr))
/* the end of the S5PV210 specific gpios */
-#define S5PV210_GPIO_END (S5PV210_MP03(S5PV210_GPIO_MP03_NR) + 1)
+#define S5PV210_GPIO_END (S5PV210_MP05(S5PV210_GPIO_MP05_NR) + 1)
#define S3C_GPIO_END S5PV210_GPIO_END
/* define the number of gpios we need to the one after the MP03() range */
-#define ARCH_NR_GPIOS (S5PV210_MP03(S5PV210_GPIO_MP03_NR) + \
+#define ARCH_NR_GPIOS (S5PV210_MP05(S5PV210_GPIO_MP05_NR) + \
CONFIG_SAMSUNG_GPIO_EXTRA + 1)
#include asm-generic/gpio.h
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[PATCH] ARM: Samsung SoC: clksrc-clk: wait for the stable SRC/DIV status.
Many MUX and clock dividers have a status bit so that users can wait
until the status is stable. When corresponding registers are accessed
while a clock is not stable, we may suffer from unexpected errors.
Therefore, we introduce a mechanism to let the operations related with
updating SRC/DIV registers of clksrc-clk wait for the stabilization:
clk_set_parent, clk_set_rate.
In order to use this feature, the definition of clksrc_clk should
include reg_src_stable or reg_div_stable. With effective rec_src_stable
values, clk_set_parent returns with a stabilized SRC register and
with effective rec_div_stable values, clk_set_rate returns with a
stabilized DIV register. If .reg field is null, its (either SRC or DIV)
register's status is not checked and returned without waiting; i.e.,
some MUX/DIV may not need this feature.
When setting reg_*_stable, .size is used to tell the value of stable.
If .size = 0, the stable status is 0 and if .size = 1, the stable status
is 1.
Signed-off-by: MyungJoo Ham myungjoo@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/plat-samsung/clock-clksrc.c | 13 +
arch/arm/plat-samsung/include/plat/clock-clksrc.h | 10 ++
2 files changed, 23 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-samsung/clock-clksrc.c
b/arch/arm/plat-samsung/clock-clksrc.c
index 46d204a..5ff17ad 100644
--- a/arch/arm/plat-samsung/clock-clksrc.c
+++ b/arch/arm/plat-samsung/clock-clksrc.c
@@ -68,6 +68,12 @@ static int s3c_setrate_clksrc(struct clk *clk, unsigned long
rate)
val |= (div - 1) sclk-reg_div.shift;
__raw_writel(val, reg);
+ if (sclk-reg_div_stable.reg) {
+ do { } while (((__raw_readl(sclk-reg_div_stable.reg)
+ sclk-reg_div_stable.shift) 1)
+ != sclk-reg_div_stable.size);
+ }
+
return 0;
}
@@ -93,6 +99,13 @@ static int s3c_setparent_clksrc(struct clk *clk, struct clk
*parent)
clksrc |= src_nr sclk-reg_src.shift;
__raw_writel(clksrc, sclk-reg_src.reg);
+
+ if (sclk-reg_src_stable.reg) {
+ do { } while (((__raw_readl(sclk-reg_src_stable.reg)
+ sclk-reg_src_stable.shift) 1)
+ != sclk-reg_src_stable.size);
+ }
+
return 0;
}
diff --git a/arch/arm/plat-samsung/include/plat/clock-clksrc.h
b/arch/arm/plat-samsung/include/plat/clock-clksrc.h
index 50a8ca7..282821d 100644
--- a/arch/arm/plat-samsung/include/plat/clock-clksrc.h
+++ b/arch/arm/plat-samsung/include/plat/clock-clksrc.h
@@ -45,6 +45,13 @@ struct clksrc_reg {
* @sources: the sources for this clock
* @reg_src: the register definition for selecting the clock's source
* @reg_div: the register definition for the clock's output divisor
+ * @reg_src_stable: the register definition to probe if reg_src is
+ *stabilized after the update of reg_src. It is stabilized if
+ *reg[shift] == size. If reg == NULL, this stable reg is not looked
+ *up. Thus, in S5PV210, size is usually 0.
+ * @reg_div_stable: the register definition to probe if reg_div is
+ *stabilized after the update of reg_div. Same mechanism with
+ *reg_src_stable.
*
* This clock implements the features required by the newer SoCs where
* the standard clock block provides an input mux and a post-mux divisor
@@ -61,6 +68,9 @@ struct clksrc_clk {
struct clksrc_reg reg_src;
struct clksrc_reg reg_div;
+
+ struct clksrc_reg reg_src_stable;
+ struct clksrc_reg reg_div_stable;
};
/**
--
1.6.3.3
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[PATCH] ARM: S5PV210: clksrc-clk: wait for the stable SRC/DIV fields added.
With this patch, clk_set_rate and clk_set_parent returns with stabilized
clocks for non-glitch muxs and divs.
This patch requires the following two patches.
1. ARM: Samsung SoC: clksrc-clk: wait for the stable SRC/DIV status.,
which has stable SRC/DIV support for Samsung SoC.
2. ARM: S5PV210: macros for clock registers at regs-clock.h included
in CPUFREQ patch, which has definitions for S5P_CLK_MUX_STAT0,
S5P_CLK_MUX_STAT1, S5P_CLK_DIV_STAT0, and S5P_CLK_DIV_STAT1.
Signed-off-by: MyungJoo Ham myungjoo@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-s5pv210/clock.c | 79 +
1 files changed, 79 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 04a0ef9..8b79b6c 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -38,6 +38,7 @@ static struct clksrc_clk clk_mout_apll = {
},
.sources= clk_src_apll,
.reg_src= { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
+ .reg_src_stable = { .reg = S5P_CLK_MUX_STAT0, .shift = 2, .size = 0 },
};
static struct clksrc_clk clk_mout_epll = {
@@ -47,6 +48,7 @@ static struct clksrc_clk clk_mout_epll = {
},
.sources= clk_src_epll,
.reg_src= { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
+ .reg_src_stable = { .reg = S5P_CLK_MUX_STAT0, .shift = 10, .size = 0 },
};
static struct clksrc_clk clk_mout_mpll = {
@@ -56,6 +58,7 @@ static struct clksrc_clk clk_mout_mpll = {
},
.sources= clk_src_mpll,
.reg_src= { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
+ .reg_src_stable = { .reg = S5P_CLK_MUX_STAT0, .shift = 6, .size = 0 },
};
static struct clk *clkset_armclk_list[] = {
@@ -75,7 +78,9 @@ static struct clksrc_clk clk_armclk = {
},
.sources= clkset_armclk,
.reg_src= { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
+ .reg_src_stable = { .reg = S5P_CLK_MUX_STAT0, .shift = 18, .size = 0 },
.reg_div= { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
+ .reg_div_stable = { .reg = S5P_CLK_DIV_STAT0, .shift = 0, .size = 0 },
};
static struct clksrc_clk clk_hclk_msys = {
@@ -85,6 +90,7 @@ static struct clksrc_clk clk_hclk_msys = {
.parent = clk_armclk.clk,
},
.reg_div= { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
+ .reg_div_stable = { .reg = S5P_CLK_DIV_STAT0, .shift = 2, .size = 0 },
};
static struct clksrc_clk clk_pclk_msys = {
@@ -94,6 +100,7 @@ static struct clksrc_clk clk_pclk_msys = {
.parent = clk_hclk_msys.clk,
},
.reg_div= { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
+ .reg_div_stable = { .reg = S5P_CLK_DIV_STAT0, .shift = 3, .size = 0 },
};
static struct clksrc_clk clk_sclk_a2m = {
@@ -103,6 +110,7 @@ static struct clksrc_clk clk_sclk_a2m = {
.parent = clk_mout_apll.clk,
},
.reg_div= { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
+ .reg_div_stable = { .reg = S5P_CLK_DIV_STAT0, .shift = 1, .size = 0 },
};
static struct clk *clkset_hclk_sys_list[] = {
@@ -122,7 +130,9 @@ static struct clksrc_clk clk_hclk_dsys = {
},
.sources= clkset_hclk_sys,
.reg_src= { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
+ .reg_src_stable = { .reg = S5P_CLK_MUX_STAT0, .shift = 22, .size = 0 },
.reg_div= { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
+ .reg_div_stable = { .reg = S5P_CLK_DIV_STAT0, .shift = 4, .size = 0 },
};
static struct clksrc_clk clk_pclk_dsys = {
@@ -132,6 +142,7 @@ static struct clksrc_clk clk_pclk_dsys = {
.parent = clk_hclk_dsys.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
+ .reg_div_stable = { .reg = S5P_CLK_DIV_STAT0, .shift = 5, .size = 0 },
};
static struct clksrc_clk clk_hclk_psys = {
@@ -141,7 +152,9 @@ static struct clksrc_clk clk_hclk_psys = {
},
.sources= clkset_hclk_sys,
.reg_src= { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
+ .reg_src_stable = { .reg = S5P_CLK_MUX_STAT0, .shift = 26, .size = 0 },
.reg_div= { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
+ .reg_div_stable = { .reg = S5P_CLK_DIV_STAT0, .shift = 6, .size = 0 },
};
static struct clksrc_clk clk_pclk_psys = {
@@ -151,6 +164,7 @@ static struct clksrc_clk clk_pclk_psys = {
.parent = clk_hclk_psys.clk,
},
.reg_div= { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
+ .reg_div_stable = { .reg = S5P_CLK_DIV_STAT0, .shift = 7, .size = 0 },
};
static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
@@ -262,6 +276,7 @@ static struct clksrc_clk clk_sclk_vpll = {
},
.sources
RE: [rtc-linux] [PATCH v2 3/3] rtc: rtc-s3c: Add BCD register initialization codes
Alessandro Zummo wrote: On Tue, 27 Jul 2010 21:59:13 +0900 Kukjin Kim kgene@samsung.com wrote: From: Taekgyun Ko taeggyun...@samsung.com RTC needs to be initialized when BCD registers have invalid value. Signed-off-by: Taekgyun Ko taeggyun...@samsung.com Signed-off-by: Kukjin Kim kgene@samsung.com Acked-by: Alessandro Zummo a.zu...@towertech.it Thanks for your ack. So...which subsystem tree is appropriate for this? Thanks. Best regards, Kgene. -- Kukjin Kim kgene@samsung.com, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [rtc-linux] [PATCH 2/2] rtc: rtc-s3c: Updates RTC driver for clock enabling support
Wan ZongShun wrote:
2010/7/22 Atul Dahiya atuldahiy...@gmail.com:
On Thu, Jul 22, 2010 at 11:39 AM, Wan ZongShun mcuos@gmail.com
wrote:
2010/7/21 Kukjin Kim kgene@samsung.com:
From: Atul Dahiya atul.dah...@samsung.com
This Patch updates existing Samsung RTC driver for clock enabling
support.
Signed-off-by: Atul Dahiya atul.dah...@samsung.com
Signed-off-by: Kukjin Kim kgene@samsung.com
---
drivers/rtc/rtc-s3c.c | 22 ++
1 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/drivers/rtc/rtc-s3c.c b/drivers/rtc/rtc-s3c.c
index 70b68d3..c032a15 100644
--- a/drivers/rtc/rtc-s3c.c
+++ b/drivers/rtc/rtc-s3c.c
@@ -1,5 +1,8 @@
/* drivers/rtc/rtc-s3c.c
*
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
* Copyright (c) 2004,2006 Simtec Electronics
* Ben Dooks, b...@simtec.co.uk
* http://armlinux.simtec.co.uk/
@@ -39,6 +42,7 @@ enum s3c_cpu_type {
static struct resource *s3c_rtc_mem;
+static struct clk *rtc_clk;
static void __iomem *s3c_rtc_base;
static int s3c_rtc_alarmno = NO_IRQ;
static int s3c_rtc_tickno = NO_IRQ;
@@ -431,6 +435,10 @@ static int __devexit s3c_rtc_remove(struct
platform_device *dev)
s3c_rtc_setpie(dev-dev, 0);
s3c_rtc_setaie(0);
+ clk_disable(rtc_clk);
+ clk_put(rtc_clk);
+ rtc_clk = NULL;
+
iounmap(s3c_rtc_base);
release_resource(s3c_rtc_mem);
kfree(s3c_rtc_mem);
@@ -488,6 +496,16 @@ static int __devinit s3c_rtc_probe(struct
platform_device *pdev)
goto err_nomap;
}
+ rtc_clk = clk_get(pdev-dev, rtc);
Do you really need the second argument? I think the bus clock for
a device should be findable with NULL for s3c platform..
No, actually clk_get() function for s3c platform searches on the
basis of second parameter passed
so need to pass the second argument here.
Okay, good patch!
Acked-by: Wan ZongShun mcuos@gmail.com
Thanks for your review and ack.
As I asked to Alessandro, does this goes through what subsystem go to upstream?
(snip)
Thanks.
Best regards,
Kgene.
--
Kukjin Kim kgene@samsung.com, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
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Re: [rtc-linux] [PATCH 2/2] rtc: rtc-s3c: Updates RTC driver for clock enabling support
2010/7/28 Kukjin Kim kgene@samsung.com:
Wan ZongShun wrote:
2010/7/22 Atul Dahiya atuldahiy...@gmail.com:
On Thu, Jul 22, 2010 at 11:39 AM, Wan ZongShun mcuos@gmail.com
wrote:
2010/7/21 Kukjin Kim kgene@samsung.com:
From: Atul Dahiya atul.dah...@samsung.com
This Patch updates existing Samsung RTC driver for clock enabling
support.
Signed-off-by: Atul Dahiya atul.dah...@samsung.com
Signed-off-by: Kukjin Kim kgene@samsung.com
---
drivers/rtc/rtc-s3c.c | 22 ++
1 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/drivers/rtc/rtc-s3c.c b/drivers/rtc/rtc-s3c.c
index 70b68d3..c032a15 100644
--- a/drivers/rtc/rtc-s3c.c
+++ b/drivers/rtc/rtc-s3c.c
@@ -1,5 +1,8 @@
/* drivers/rtc/rtc-s3c.c
*
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
* Copyright (c) 2004,2006 Simtec Electronics
* Ben Dooks, b...@simtec.co.uk
* http://armlinux.simtec.co.uk/
@@ -39,6 +42,7 @@ enum s3c_cpu_type {
static struct resource *s3c_rtc_mem;
+static struct clk *rtc_clk;
static void __iomem *s3c_rtc_base;
static int s3c_rtc_alarmno = NO_IRQ;
static int s3c_rtc_tickno = NO_IRQ;
@@ -431,6 +435,10 @@ static int __devexit s3c_rtc_remove(struct
platform_device *dev)
s3c_rtc_setpie(dev-dev, 0);
s3c_rtc_setaie(0);
+ clk_disable(rtc_clk);
+ clk_put(rtc_clk);
+ rtc_clk = NULL;
+
iounmap(s3c_rtc_base);
release_resource(s3c_rtc_mem);
kfree(s3c_rtc_mem);
@@ -488,6 +496,16 @@ static int __devinit s3c_rtc_probe(struct
platform_device *pdev)
goto err_nomap;
}
+ rtc_clk = clk_get(pdev-dev, rtc);
Do you really need the second argument? I think the bus clock for
a device should be findable with NULL for s3c platform..
No, actually clk_get() function for s3c platform searches on the
basis of second parameter passed
so need to pass the second argument here.
Okay, good patch!
Acked-by: Wan ZongShun mcuos@gmail.com
Thanks for your review and ack.
As I asked to Alessandro, does this goes through what subsystem go to
upstream?
After you get ack, Samsung git tree or Andrew's mm git tree can do it.
Thanks!
(snip)
Thanks.
Best regards,
Kgene.
--
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SW Solution Development Team, Samsung Electronics Co., Ltd.
--
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Please read http://groups.google.com/group/rtc-linux/web/checklist
before submitting a driver.
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RE: [PATCH v3 3/3] sdhci-s3c: Add SDHCI_QUIRK_NO_WP_BIT quirk for Samsung SoC
Maurus Cuelenaere wrote:
Op 27-07-10 13:58, Kukjin Kim schreef:
Maurus Cuelenaere wrote:
Op 23-07-10 13:56, Kukjin Kim schreef:
From: Hyuk Lee hyuk1@samsung.com
If host controller doesn't have WP pin which should be connnected with
SDMMC
card WP pin, can implement get_ro function with using the allocated gpio.
In order to use this quirk wp_gpio in the platform data must be set.
Signed-off-by: Hyuk Lee hyuk1@samsung.com
Signed-off-by: Kukjin Kim kgene@samsung.com
---
drivers/mmc/host/sdhci-s3c.c | 43
++
drivers/mmc/host/sdhci.c |3 ++
drivers/mmc/host/sdhci.h |3 ++
3 files changed, 49 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index 0d25285..0b75e57 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -22,6 +22,7 @@
#include linux/mmc/host.h
+#include plat/gpio-cfg.h
#include plat/sdhci.h
#include plat/regs-sdhci.h
@@ -213,6 +214,36 @@ static void sdhci_s3c_set_clock(struct sdhci_host
*host,
unsigned int clock)
}
/**
+ * sdhci_s3c_get_ro - callback for get_ro
+ * @host: The SDHCI host being changed
+ *
+ * If the WP pin is connected with GPIO, can get the value which
indicates
+ * the card is locked or not.
+*/
+static int sdhci_s3c_get_ro(struct mmc_host *mmc)
+{
+ struct sdhci_s3c *sc;
+ struct sdhci_host *host;
+
+ host = mmc_priv(mmc);
+ sc = sdhci_priv(host);
This can be done as static initializer if you reverse the order above.
Could you please kindly explain about this?
Sorry, I cannot get the exactly meaning...
+static int sdhci_s3c_get_ro(struct mmc_host *mmc)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ struct sdhci_s3c *sc = sdhci_priv(host);
Hahaha, no need more words ;-)
Thanks for your kindly explanation.
I think, v4 patch seems to satisfy your suggestion...even though need v5 patch
right now.
Thanks.
Best regards,
Kgene.
--
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SW Solution Development Team, Samsung Electronics Co., Ltd.
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RE: [rtc-linux] [PATCH 2/2] rtc: rtc-s3c: Updates RTC driver for clock enabling support
-Original Message-
From: linux-arm-kernel-boun...@lists.infradead.org [mailto:linux-arm-kernel-
boun...@lists.infradead.org] On Behalf Of Wan ZongShun
Sent: Wednesday, July 28, 2010 1:42 PM
To: rtc-li...@googlegroups.com
Cc: a.zu...@towertech.it; linux-samsung-soc@vger.kernel.org; Atul Dahiya;
p_gortma...@yahoo.com; Atul Dahiya; ben-li...@fluff.org; linux-arm-
ker...@lists.infradead.org
Subject: Re: [rtc-linux] [PATCH 2/2] rtc: rtc-s3c: Updates RTC driver for
clock
enabling support
2010/7/28 Kukjin Kim kgene@samsung.com:
Wan ZongShun wrote:
2010/7/22 Atul Dahiya atuldahiy...@gmail.com:
On Thu, Jul 22, 2010 at 11:39 AM, Wan ZongShun mcuos@gmail.com
wrote:
2010/7/21 Kukjin Kim kgene@samsung.com:
From: Atul Dahiya atul.dah...@samsung.com
This Patch updates existing Samsung RTC driver for clock enabling
support.
Signed-off-by: Atul Dahiya atul.dah...@samsung.com
Signed-off-by: Kukjin Kim kgene@samsung.com
---
drivers/rtc/rtc-s3c.c | 22 ++
1 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/drivers/rtc/rtc-s3c.c b/drivers/rtc/rtc-s3c.c
index 70b68d3..c032a15 100644
--- a/drivers/rtc/rtc-s3c.c
+++ b/drivers/rtc/rtc-s3c.c
@@ -1,5 +1,8 @@
/* drivers/rtc/rtc-s3c.c
*
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
* Copyright (c) 2004,2006 Simtec Electronics
* Ben Dooks, b...@simtec.co.uk
* http://armlinux.simtec.co.uk/
@@ -39,6 +42,7 @@ enum s3c_cpu_type {
static struct resource *s3c_rtc_mem;
+static struct clk *rtc_clk;
static void __iomem *s3c_rtc_base;
static int s3c_rtc_alarmno = NO_IRQ;
static int s3c_rtc_tickno = NO_IRQ;
@@ -431,6 +435,10 @@ static int __devexit s3c_rtc_remove(struct
platform_device *dev)
s3c_rtc_setpie(dev-dev, 0);
s3c_rtc_setaie(0);
+ clk_disable(rtc_clk);
+ clk_put(rtc_clk);
+ rtc_clk = NULL;
+
iounmap(s3c_rtc_base);
release_resource(s3c_rtc_mem);
kfree(s3c_rtc_mem);
@@ -488,6 +496,16 @@ static int __devinit s3c_rtc_probe(struct
platform_device *pdev)
goto err_nomap;
}
+ rtc_clk = clk_get(pdev-dev, rtc);
Do you really need the second argument? I think the bus clock for
a device should be findable with NULL for s3c platform..
No, actually clk_get() function for s3c platform searches on the
basis of second parameter passed
so need to pass the second argument here.
Okay, good patch!
Acked-by: Wan ZongShun mcuos@gmail.com
Thanks for your review and ack.
As I asked to Alessandro, does this goes through what subsystem go to
upstream?
After you get ack, Samsung git tree or Andrew's mm git tree can do it.
Thanks!
Ok...will apply this for next merge window with your ack.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim kgene@samsung.com, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
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RE: [PATCH v4 3/3] sdhci-s3c: Add SDHCI_QUIRK_NO_WP_BIT quirk for Samsung SoC
Marek Szyprowski wrote:
Hello,
Hi :-)
On Tuesday, July 27, 2010 2:44 PM Kukjin Kim wrote:
From: Hyuk Lee hyuk1@samsung.com
If host controller doesn't have WP pin which should be connnected with
SDMMC
card WP pin, can implement get_ro function with using the allocated
gpio.
In order to use this quirk wp_gpio in the platform data must be set.
Signed-off-by: Hyuk Lee hyuk1@samsung.com
Signed-off-by: Kukjin Kim kgene@samsung.com
---
drivers/mmc/host/sdhci-s3c.c | 36
drivers/mmc/host/sdhci.c |3 +++
drivers/mmc/host/sdhci.h |3 +++
3 files changed, 42 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index 0d25285..98a8ec8 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -22,6 +22,7 @@
#include linux/mmc/host.h
+#include plat/gpio-cfg.h
#include plat/sdhci.h
#include plat/regs-sdhci.h
@@ -213,6 +214,32 @@ static void sdhci_s3c_set_clock(struct sdhci_host
*host, unsigned int clock)
}
/**
+ * sdhci_s3c_get_ro - callback for get_ro
+ * @host: The SDHCI host being changed
+ *
+ * If the WP pin is connected with GPIO, can get the value which
indicates
+ * the card is locked or not.
+*/
+static int sdhci_s3c_get_ro(struct mmc_host *mmc)
+{
+ struct sdhci_s3c *ourhost = to_s3c(mmc_priv(mmc));
+
+ return gpio_get_value(ourhost-pdata-wp_gpio);
+}
+
+/**
+ * sdhci_s3c_cfg_wp - configure GPIO for WP pin
+ * @gpio_num: GPIO number which connected with WP line from SD/MMC slot
+ *
+ * Configure GPIO for using WP line
+*/
+static void sdhci_s3c_cfg_wp(unsigned int gpio_num)
+{
+ s3c_gpio_cfgpin(gpio_num, S3C_GPIO_INPUT);
+ s3c_gpio_setpull(gpio_num, S3C_GPIO_PULL_UP);
+}
+
+/**
* sdhci_s3c_get_min_clock - callback to get minimal supported clock
value
* @host: The SDHCI host being queried
*
@@ -408,6 +435,15 @@ static int __devinit sdhci_s3c_probe(struct
platform_device *pdev)
host-quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
SDHCI_QUIRK_32BIT_DMA_SIZE);
+ /* Controller's WP pin doesn't connected with SD card and there is
an
+* allocated GPIO for getting WP data form SD card, use this quirk
and
+* send the GPIO number in pdata-wp_gpio. */
+ if (gpio_is_valid(pdata-wp_gpio) pdata-has_wp_gpio) {
IMHO the opposite order would make much more sense:
if (pdata-has_wp_gpio gpio_is_valid(pdata-wp_gpio))
Ok..will modify.
+ sdhci_s3c_ops.get_ro = sdhci_s3c_get_ro;
+ host-quirks |= SDHCI_QUIRK_NO_WP_BIT;
+ sdhci_s3c_cfg_wp(pdata-wp_gpio);
+ }
+
ret = sdhci_add_host(host);
if (ret) {
dev_err(dev, sdhci_add_host() failed\n);
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index f9ca4c6..7fba401 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1198,6 +1198,9 @@ static int sdhci_get_ro(struct mmc_host *mmc)
host = mmc_priv(mmc);
+ if ((host-quirks SDHCI_QUIRK_NO_WP_BIT) host-ops-get_ro)
+ return host-ops-get_ro(mmc);
+
spin_lock_irqsave(host-lock, flags);
if (host-flags SDHCI_DEVICE_DEAD)
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 0de8b38..dd9a233 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -247,6 +247,8 @@ struct sdhci_host {
#define SDHCI_QUIRK_MISSING_CAPS (128)
/* Controller has nonstandard clock management */
#define SDHCI_QUIRK_NONSTANDARD_MINCLOCK (129)
+/* Controller has no write-protect pin connected with SD card */
+#define SDHCI_QUIRK_NO_WP_BIT (130)
int irq;/* Device IRQ */
void __iomem * ioaddr; /* Mapped address */
@@ -321,6 +323,7 @@ struct sdhci_ops {
unsigned int(*get_max_clock)(struct sdhci_host *host);
unsigned int(*get_min_clock)(struct sdhci_host *host);
unsigned int(*get_timeout_clock)(struct sdhci_host *host);
+ int (*get_ro)(struct mmc_host *mmc);
};
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
Otherwise looks fine.
Thanks for your comment.
Best regards,
Kgene.
--
Kukjin Kim kgene@samsung.com, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
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[PATCH v5 3/3] sdhci-s3c: Add SDHCI_QUIRK_NO_WP_BIT quirk for Samsung SoC
From: Hyuk Lee hyuk1@samsung.com
If host controller doesn't have WP pin which should be connnected with SDMMC
card WP pin, can implement get_ro function with using the allocated gpio.
In order to use this quirk wp_gpio in the platform data must be set.
Signed-off-by: Hyuk Lee hyuk1@samsung.com
Signed-off-by: Kukjin Kim kgene@samsung.com
Cc: Ben Dooks ben-li...@fluff.org
---
Changes since v4:
- Address comments from Marek.
Hi Andrew,
If there are no problems, could you please apply this patch?
drivers/mmc/host/sdhci-s3c.c | 36
drivers/mmc/host/sdhci.c |3 +++
drivers/mmc/host/sdhci.h |3 +++
3 files changed, 42 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index 0d25285..98a8ec8 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -22,6 +22,7 @@
#include linux/mmc/host.h
+#include plat/gpio-cfg.h
#include plat/sdhci.h
#include plat/regs-sdhci.h
@@ -213,6 +214,32 @@ static void sdhci_s3c_set_clock(struct sdhci_host *host,
unsigned int clock)
}
/**
+ * sdhci_s3c_get_ro - callback for get_ro
+ * @host: The SDHCI host being changed
+ *
+ * If the WP pin is connected with GPIO, can get the value which indicates
+ * the card is locked or not.
+*/
+static int sdhci_s3c_get_ro(struct mmc_host *mmc)
+{
+ struct sdhci_s3c *ourhost = to_s3c(mmc_priv(mmc));
+
+ return gpio_get_value(ourhost-pdata-wp_gpio);
+}
+
+/**
+ * sdhci_s3c_cfg_wp - configure GPIO for WP pin
+ * @gpio_num: GPIO number which connected with WP line from SD/MMC slot
+ *
+ * Configure GPIO for using WP line
+*/
+static void sdhci_s3c_cfg_wp(unsigned int gpio_num)
+{
+ s3c_gpio_cfgpin(gpio_num, S3C_GPIO_INPUT);
+ s3c_gpio_setpull(gpio_num, S3C_GPIO_PULL_UP);
+}
+
+/**
* sdhci_s3c_get_min_clock - callback to get minimal supported clock value
* @host: The SDHCI host being queried
*
@@ -408,6 +435,15 @@ static int __devinit sdhci_s3c_probe(struct
platform_device *pdev)
host-quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
SDHCI_QUIRK_32BIT_DMA_SIZE);
+ /* Controller's WP pin doesn't connected with SD card and there is an
+* allocated GPIO for getting WP data form SD card, use this quirk and
+* send the GPIO number in pdata-wp_gpio. */
+ if (pdata-has_wp_gpio gpio_is_valid(pdata-wp_gpio)) {
+ sdhci_s3c_ops.get_ro = sdhci_s3c_get_ro;
+ host-quirks |= SDHCI_QUIRK_NO_WP_BIT;
+ sdhci_s3c_cfg_wp(pdata-wp_gpio);
+ }
+
ret = sdhci_add_host(host);
if (ret) {
dev_err(dev, sdhci_add_host() failed\n);
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index f9ca4c6..7fba401 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1198,6 +1198,9 @@ static int sdhci_get_ro(struct mmc_host *mmc)
host = mmc_priv(mmc);
+ if ((host-quirks SDHCI_QUIRK_NO_WP_BIT) host-ops-get_ro)
+ return host-ops-get_ro(mmc);
+
spin_lock_irqsave(host-lock, flags);
if (host-flags SDHCI_DEVICE_DEAD)
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 0de8b38..dd9a233 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -247,6 +247,8 @@ struct sdhci_host {
#define SDHCI_QUIRK_MISSING_CAPS (128)
/* Controller has nonstandard clock management */
#define SDHCI_QUIRK_NONSTANDARD_MINCLOCK (129)
+/* Controller has no write-protect pin connected with SD card */
+#define SDHCI_QUIRK_NO_WP_BIT (130)
int irq;/* Device IRQ */
void __iomem * ioaddr; /* Mapped address */
@@ -321,6 +323,7 @@ struct sdhci_ops {
unsigned int(*get_max_clock)(struct sdhci_host *host);
unsigned int(*get_min_clock)(struct sdhci_host *host);
unsigned int(*get_timeout_clock)(struct sdhci_host *host);
+ int (*get_ro)(struct mmc_host *mmc);
};
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
--
1.6.2.5
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