[PATCH] cpufreq: exynos5440: Protect opp search calls with rcu lock

[Amit Daniel Kachhap]

As per the OPP library documentation(Documentation/power/opp.txt) all
opp find/get calls should be protected by rcu locks.

Signed-off-by: Amit Daniel Kachhap amit.dan...@samsung.com
---

This patch is created against linux-next tree and is suggested by
Nishanth Menon. (https://lkml.org/lkml/2013/4/12/119)

 drivers/cpufreq/exynos5440-cpufreq.c |3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/drivers/cpufreq/exynos5440-cpufreq.c 
b/drivers/cpufreq/exynos5440-cpufreq.c
index ead7ed4..0c74018 100644
--- a/drivers/cpufreq/exynos5440-cpufreq.c
+++ b/drivers/cpufreq/exynos5440-cpufreq.c
@@ -120,11 +120,13 @@ static int init_div_table(void)
int i = 0;
struct opp *opp;
 
+   rcu_read_lock();
for (i = 0; freq_tbl[i].frequency != CPUFREQ_TABLE_END; i++) {
 
opp = opp_find_freq_exact(dvfs_info-dev,
freq_tbl[i].frequency * 1000, true);
if (IS_ERR(opp)) {
+   rcu_read_unlock();
dev_err(dvfs_info-dev,
failed to find valid OPP for %u KHZ\n,
freq_tbl[i].frequency);
@@ -159,6 +161,7 @@ static int init_div_table(void)
__raw_writel(tmp, dvfs_info-base + XMU_PMU_P0_7 + 4 * i);
}
 
+   rcu_read_unlock();
return 0;
 }
 
-- 
1.7.1

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Re: [PATCH 3/7] ARM: exynos: add missing properties for combiner IRQs

[Thomas Abraham]

On 12 April 2013 19:33, Arnd Bergmann a...@arndb.de wrote:
 The exynos combiner irqchip needs to find the parent interrupts
 and needs to know their number, so add the missing properties
 for exynos4 as they were already present for exynos5.

 Signed-off-by: Arnd Bergmann a...@arndb.de
 ---
  arch/arm/boot/dts/exynos4210.dtsi | 1 +
  arch/arm/boot/dts/exynos4212.dtsi | 9 +
  arch/arm/boot/dts/exynos4412.dtsi | 9 +
  3 files changed, 19 insertions(+)

 diff --git a/arch/arm/boot/dts/exynos4210.dtsi 
 b/arch/arm/boot/dts/exynos4210.dtsi
 index 15143bd..c102869 100644
 --- a/arch/arm/boot/dts/exynos4210.dtsi
 +++ b/arch/arm/boot/dts/exynos4210.dtsi
 @@ -41,6 +41,7 @@
 };

 combiner:interrupt-controller@1044 {
 +   combiner-nr = 16;

The default value of the combiner-nr is case it is not specified is
16. The default value is documented in the bindings documentation.

 interrupts = 0 0 0, 0 1 0, 0 2 0, 0 3 0,
  0 4 0, 0 5 0, 0 6 0, 0 7 0,
  0 8 0, 0 9 0, 0 10 0, 0 11 0,
 diff --git a/arch/arm/boot/dts/exynos4212.dtsi 
 b/arch/arm/boot/dts/exynos4212.dtsi
 index 36d4299..f83c3c1 100644
 --- a/arch/arm/boot/dts/exynos4212.dtsi
 +++ b/arch/arm/boot/dts/exynos4212.dtsi
 @@ -26,6 +26,15 @@
 cpu-offset = 0x8000;
 };

 +   interrupt-controller@1044 {
 +combiner-nr = 18;
 +   interrupts = 0 0 0, 0 1 0, 0 2 0, 0 3 0,
 +0 4 0, 0 5 0, 0 6 0, 0 7 0,
 +0 8 0, 0 9 0, 0 10 0, 0 11 0,
 +0 12 0, 0 13 0, 0 14 0, 0 15 0,
 +0 107 0, 0 108 0;
 +   };
 +
 mct@1005 {
 compatible = samsung,exynos4412-mct;
 reg = 0x1005 0x800;
 diff --git a/arch/arm/boot/dts/exynos4412.dtsi 
 b/arch/arm/boot/dts/exynos4412.dtsi
 index d75c047..4cb657e 100644
 --- a/arch/arm/boot/dts/exynos4412.dtsi
 +++ b/arch/arm/boot/dts/exynos4412.dtsi
 @@ -26,6 +26,15 @@
 cpu-offset = 0x4000;
 };

 +   interrupt-controller@1044 {
 +   combiner-nr = 20;
 +   interrupts = 0 0 0, 0 1 0, 0 2 0, 0 3 0,
 +0 4 0, 0 5 0, 0 6 0, 0 7 0,
 +0 8 0, 0 9 0, 0 10 0, 0 11 0,
 +0 12 0, 0 13 0, 0 14 0, 0 15 0,
 +0 107 0, 0 108 0, 0 48 0, 0 42 0;

Extra '' for 0 108 0 can be removed.

Reviewed-by: Thomas Abraham thomas.abra...@linaro.org?

 +   };
 +
 mct@1005 {
 compatible = samsung,exynos4412-mct;
 reg = 0x1005 0x800;
 --
 1.8.1.2

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Re: [PATCH 1/7] clk: exynos: prepare for multiplatform

[Thomas Abraham]

On 12 April 2013 19:33, Arnd Bergmann a...@arndb.de wrote:
 The new common clock drivers for exynos are using compile
 time constants and soc_is_exynos* macros to provide backwards
 compatibility for pre-DT systems, which is not possible with
 multiplatform kernels. This moves all the necessary
 information back into platform code and removes the mach/*
 header inclusions.


Since kgene has submitted a patch to remove pre-dt Exynos support
which looks like it will be accepted, we could just remove the use of
soc_is_xyz() instead of continuing to support non-dt Exynos.

Thanks,
Thomas.
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Re: [PATCH 3/7] ARM: exynos: add missing properties for combiner IRQs

[Sachin Kamat]

On 12 April 2013 19:33, Arnd Bergmann a...@arndb.de wrote:
 The exynos combiner irqchip needs to find the parent interrupts
 and needs to know their number, so add the missing properties
 for exynos4 as they were already present for exynos5.

 Signed-off-by: Arnd Bergmann a...@arndb.de
 ---
  arch/arm/boot/dts/exynos4210.dtsi | 1 +
  arch/arm/boot/dts/exynos4212.dtsi | 9 +
  arch/arm/boot/dts/exynos4412.dtsi | 9 +
  3 files changed, 19 insertions(+)

 diff --git a/arch/arm/boot/dts/exynos4210.dtsi 
 b/arch/arm/boot/dts/exynos4210.dtsi
 index 15143bd..c102869 100644
 --- a/arch/arm/boot/dts/exynos4210.dtsi
 +++ b/arch/arm/boot/dts/exynos4210.dtsi
 @@ -41,6 +41,7 @@
 };

 combiner:interrupt-controller@1044 {
 +   combiner-nr = 16;

I think this should be samsung,combiner-nr
Without this i see the following message in boot log:
combiner_of_init: number of combiners not specified

 interrupts = 0 0 0, 0 1 0, 0 2 0, 0 3 0,
  0 4 0, 0 5 0, 0 6 0, 0 7 0,
  0 8 0, 0 9 0, 0 10 0, 0 11 0,
 diff --git a/arch/arm/boot/dts/exynos4212.dtsi 
 b/arch/arm/boot/dts/exynos4212.dtsi
 index 36d4299..f83c3c1 100644
 --- a/arch/arm/boot/dts/exynos4212.dtsi
 +++ b/arch/arm/boot/dts/exynos4212.dtsi
 @@ -26,6 +26,15 @@
 cpu-offset = 0x8000;
 };

 +   interrupt-controller@1044 {

Don't we need a node name here (combiner:interrupt-controller@1044)?

 +combiner-nr = 18;
^^^
nit: tabs instead of space would look better.

 +   interrupts = 0 0 0, 0 1 0, 0 2 0, 0 3 0,
 +0 4 0, 0 5 0, 0 6 0, 0 7 0,
 +0 8 0, 0 9 0, 0 10 0, 0 11 0,
 +0 12 0, 0 13 0, 0 14 0, 0 15 0,
 +0 107 0, 0 108 0;
 +   };
 +
 mct@1005 {
 compatible = samsung,exynos4412-mct;
 reg = 0x1005 0x800;
 diff --git a/arch/arm/boot/dts/exynos4412.dtsi 
 b/arch/arm/boot/dts/exynos4412.dtsi
 index d75c047..4cb657e 100644
 --- a/arch/arm/boot/dts/exynos4412.dtsi
 +++ b/arch/arm/boot/dts/exynos4412.dtsi
 @@ -26,6 +26,15 @@
 cpu-offset = 0x4000;
 };

 +   interrupt-controller@1044 {
 +   combiner-nr = 20;
Same as above (for exynos4212.dtsi).

 +   interrupts = 0 0 0, 0 1 0, 0 2 0, 0 3 0,
 +0 4 0, 0 5 0, 0 6 0, 0 7 0,
 +0 8 0, 0 9 0, 0 10 0, 0 11 0,
 +0 12 0, 0 13 0, 0 14 0, 0 15 0,
 +0 107 0, 0 108 0, 0 48 0, 0 42 0;
  ^^^
Syntax error.

We have a combiner node defined in exynos4x12.dtsi. With the bindings
now defined separately in 4212 and 4412 dtsi files, probably the one
in 4x12 could be dropped?


-- 
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Sachin
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Re: [PATCH 1/7] clk: exynos: prepare for multiplatform

[Arnd Bergmann]

On Monday 15 April 2013, Thomas Abraham wrote:
 On 12 April 2013 19:33, Arnd Bergmann a...@arndb.de wrote:
  The new common clock drivers for exynos are using compile
  time constants and soc_is_exynos* macros to provide backwards
  compatibility for pre-DT systems, which is not possible with
  multiplatform kernels. This moves all the necessary
  information back into platform code and removes the mach/*
  header inclusions.
 
 
 Since kgene has submitted a patch to remove pre-dt Exynos support
 which looks like it will be accepted, we could just remove the use of
 soc_is_xyz() instead of continuing to support non-dt Exynos.

I think based on the most recent discussion, we are not actually doing
that for 3.10, since there are still people that require ATAGS support.

Arnd
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Re: [PATCH 3/7] ARM: exynos: add missing properties for combiner IRQs

[Arnd Bergmann]

On Monday 15 April 2013, Thomas Abraham wrote:
 On 12 April 2013 19:33, Arnd Bergmann a...@arndb.de wrote:
  The exynos combiner irqchip needs to find the parent interrupts
  and needs to know their number, so add the missing properties
  for exynos4 as they were already present for exynos5.
 
  Signed-off-by: Arnd Bergmann a...@arndb.de
  ---
   arch/arm/boot/dts/exynos4210.dtsi | 1 +
   arch/arm/boot/dts/exynos4212.dtsi | 9 +
   arch/arm/boot/dts/exynos4412.dtsi | 9 +
   3 files changed, 19 insertions(+)
 
  diff --git a/arch/arm/boot/dts/exynos4210.dtsi 
  b/arch/arm/boot/dts/exynos4210.dtsi
  index 15143bd..c102869 100644
  --- a/arch/arm/boot/dts/exynos4210.dtsi
  +++ b/arch/arm/boot/dts/exynos4210.dtsi
  @@ -41,6 +41,7 @@
  };
 
  combiner:interrupt-controller@1044 {
  +   combiner-nr = 16;
 
 The default value of the combiner-nr is case it is not specified is
 16. The default value is documented in the bindings documentation.

Unfortunately, the driver now warns about a missing attribute, which
seems right. I also made the default 20 instead of 16 to cover the
other exynos4 chips. I'd say it's best to keep this one explicitly listed
even if it's optional.

  +   interrupt-controller@1044 {
  +   combiner-nr = 20;
  +   interrupts = 0 0 0, 0 1 0, 0 2 0, 0 3 0,
  +0 4 0, 0 5 0, 0 6 0, 0 7 0,
  +0 8 0, 0 9 0, 0 10 0, 0 11 0,
  +0 12 0, 0 13 0, 0 14 0, 0 15 0,
  +0 107 0, 0 108 0, 0 48 0, 0 42 0;
 
 Extra '' for 0 108 0 can be removed.
 
 Reviewed-by: Thomas Abraham thomas.abra...@linaro.org?

Thanks!
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Re: [PATCH v2 02/13] ARM: convert arm/arm64 arch timer to use CLKSRC_OF init

[Catalin Marinas]

On Mon, Apr 01, 2013 at 11:21:12PM +0100, Rob Herring wrote:
 From: Rob Herring rob.herr...@calxeda.com
 
 This converts arm and arm64 to use CLKSRC_OF DT based initialization for
 the arch timer. A new function arch_timer_arch_init is added to allow for
 arch specific setup.
 
 This has a side effect of enabling sched_clock on omap5 and exynos5. There
 should not be any reason not to use the arch timers for sched_clock.
 
 Signed-off-by: Rob Herring rob.herr...@calxeda.com
 Cc: Russell King li...@arm.linux.org.uk
 Cc: Kukjin Kim kgene@samsung.com
 Cc: Tony Lindgren t...@atomide.com
 Cc: Simon Horman ho...@verge.net.au
 Cc: Magnus Damm magnus.d...@gmail.com
 Cc: Catalin Marinas catalin.mari...@arm.com
 Cc: Will Deacon will.dea...@arm.com
 Cc: John Stultz john.stu...@linaro.org
 Cc: Thomas Gleixner t...@linutronix.de
 Cc: linux-samsung-soc@vger.kernel.org
 Cc: linux-o...@vger.kernel.org
 Cc: linux...@vger.kernel.org

Unless you pushed the patches already (I've been away for two weeks),
for arm64:

Acked-by: Catalin Marinas catalin.mari...@arm.com
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Re: [PATCH 3/7] ARM: exynos: add missing properties for combiner IRQs

[Sachin Kamat]

  diff --git a/arch/arm/boot/dts/exynos4212.dtsi 
  b/arch/arm/boot/dts/exynos4212.dtsi
  index 36d4299..f83c3c1 100644
  --- a/arch/arm/boot/dts/exynos4212.dtsi
  +++ b/arch/arm/boot/dts/exynos4212.dtsi
  @@ -26,6 +26,15 @@
  cpu-offset = 0x8000;
  };
 
  +   interrupt-controller@1044 {

 Don't we need a node name here (combiner:interrupt-controller@1044)?

 Why?

Since it is being referenced as combiner by other bindings, i
thought that was required.

The combiner: part is just a label. Actually I think the preferred
 syntax is

 combiner {
 samsung,combiner-nr = 18;
 };

 which is much shorter to write, but I did not want to change the style used
 in the rest of the file.

  +combiner-nr = 18;
 ^^^
 nit: tabs instead of space would look better.

 I fixed that up locally, but I think I sent out the wrong version.

OK.


  diff --git a/arch/arm/boot/dts/exynos4412.dtsi 
  b/arch/arm/boot/dts/exynos4412.dtsi
  index d75c047..4cb657e 100644
  --- a/arch/arm/boot/dts/exynos4412.dtsi
  +++ b/arch/arm/boot/dts/exynos4412.dtsi
  @@ -26,6 +26,15 @@
  cpu-offset = 0x4000;
  };
 
  +   interrupt-controller@1044 {
  +   combiner-nr = 20;
 Same as above (for exynos4212.dtsi).

  +   interrupts = 0 0 0, 0 1 0, 0 2 0, 0 3 0,
  +0 4 0, 0 5 0, 0 6 0, 0 7 0,
  +0 8 0, 0 9 0, 0 10 0, 0 11 0,
  +0 12 0, 0 13 0, 0 14 0, 0 15 0,
  +0 107 0, 0 108 0, 0 48 0, 0 42 0;
   ^^^
 Syntax error.

 We have a combiner node defined in exynos4x12.dtsi. With the bindings
 now defined separately in 4212 and 4412 dtsi files, probably the one
 in 4x12 could be dropped?

 I did not see that one, but it seems to have the wrong numbers in the last
 four interrupt specifiers. I think it would be better to just fix that one
 and keep using it.

OK. Do you want me to fix it and send as a patch or would you like to do it?


-- 
With warm regards,
Sachin
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Re: [PATCH v6 1/3] of/pci: Unify pci_process_bridge_OF_ranges from Microblaze and PowerPC

[Thomas Petazzoni]

Michal, Ben,

Would you have some time to look at this patch and give your comments
and/or ACK ? Since it touches the PowerPC and Microblaze core code, we
need your agreement to merge this code, and quite a bit of code pending
for 3.10 depends on this patch.

Rob, alternatively, could we imagine doing a different version of the
'of/pci: Provide support for parsing PCI DT ranges property' that
introduces the new API only, leaving the PowerPC and Microblaze rework
as follow-up efforts, so that all the PCIe drivers that depend on this
patch can get in for 3.10 ? I'd find it pretty sad if the Marvell PCIe
driver that has been worked on since 4+ months does not get into 3.10
just because this patch cannot be merged.

Thanks!

Thomas

On Thu, 11 Apr 2013 16:26:07 +0100, Andrew Murray wrote:
 The pci_process_bridge_OF_ranges function, used to parse the ranges
 property of a PCI host device, is found in both Microblaze and PowerPC
 architectures. These implementations are nearly identical. This patch
 moves this common code to a common place.
 
 Signed-off-by: Andrew Murray andrew.mur...@arm.com
 Signed-off-by: Liviu Dudau liviu.du...@arm.com
 Reviewed-by: Rob Herring rob.herr...@calxeda.com
 Tested-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
 ---
  arch/microblaze/include/asm/pci-bridge.h |5 +-
  arch/microblaze/pci/pci-common.c |  192 
  arch/powerpc/include/asm/pci-bridge.h|5 +-
  arch/powerpc/kernel/pci-common.c |  192 
  drivers/of/of_pci.c  |  200 
 ++
  include/linux/of_pci.h   |4 +
  6 files changed, 206 insertions(+), 392 deletions(-)
 
 diff --git a/arch/microblaze/include/asm/pci-bridge.h 
 b/arch/microblaze/include/asm/pci-bridge.h
 index cb5d397..5783cd6 100644
 --- a/arch/microblaze/include/asm/pci-bridge.h
 +++ b/arch/microblaze/include/asm/pci-bridge.h
 @@ -10,6 +10,7 @@
  #include linux/pci.h
  #include linux/list.h
  #include linux/ioport.h
 +#include linux/of_pci.h
  
  struct device_node;
  
 @@ -132,10 +133,6 @@ extern void setup_indirect_pci(struct pci_controller 
 *hose,
  extern struct pci_controller *pci_find_hose_for_OF_device(
   struct device_node *node);
  
 -/* Fill up host controller resources from the OF node */
 -extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
 - struct device_node *dev, int primary);
 -
  /* Allocate  free a PCI host bridge structure */
  extern struct pci_controller *pcibios_alloc_controller(struct device_node 
 *dev);
  extern void pcibios_free_controller(struct pci_controller *phb);
 diff --git a/arch/microblaze/pci/pci-common.c 
 b/arch/microblaze/pci/pci-common.c
 index 9ea521e..2735ad9 100644
 --- a/arch/microblaze/pci/pci-common.c
 +++ b/arch/microblaze/pci/pci-common.c
 @@ -622,198 +622,6 @@ void pci_resource_to_user(const struct pci_dev *dev, 
 int bar,
   *end = rsrc-end - offset;
  }
  
 -/**
 - * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
 - * @hose: newly allocated pci_controller to be setup
 - * @dev: device node of the host bridge
 - * @primary: set if primary bus (32 bits only, soon to be deprecated)
 - *
 - * This function will parse the ranges property of a PCI host bridge device
 - * node and setup the resource mapping of a pci controller based on its
 - * content.
 - *
 - * Life would be boring if it wasn't for a few issues that we have to deal
 - * with here:
 - *
 - *   - We can only cope with one IO space range and up to 3 Memory space
 - * ranges. However, some machines (thanks Apple !) tend to split their
 - * space into lots of small contiguous ranges. So we have to coalesce.
 - *
 - *   - We can only cope with all memory ranges having the same offset
 - * between CPU addresses and PCI addresses. Unfortunately, some bridges
 - * are setup for a large 1:1 mapping along with a small window which
 - * maps PCI address 0 to some arbitrary high address of the CPU space in
 - * order to give access to the ISA memory hole.
 - * The way out of here that I've chosen for now is to always set the
 - * offset based on the first resource found, then override it if we
 - * have a different offset and the previous was set by an ISA hole.
 - *
 - *   - Some busses have IO space not starting at 0, which causes trouble with
 - * the way we do our IO resource renumbering. The code somewhat deals 
 with
 - * it for 64 bits but I would expect problems on 32 bits.
 - *
 - *   - Some 32 bits platforms such as 4xx can have physical space larger than
 - * 32 bits so we need to use 64 bits values for the parsing
 - */
 -void pci_process_bridge_OF_ranges(struct pci_controller *hose,
 -   struct device_node *dev, int primary)
 -{
 - const u32 *ranges;
 - int rlen;
 - int pna = of_n_addr_cells(dev);
 - int np = pna + 

Re: [PATCH] cpufreq: exynos5440: Protect opp search calls with rcu lock

[Nishanth Menon]

Daniel,
On Mon, Apr 15, 2013 at 1:24 AM, Amit Daniel Kachhap
amit.dan...@samsung.com wrote:
 As per the OPP library documentation(Documentation/power/opp.txt) all
 opp find/get calls should be protected by rcu locks.

 Signed-off-by: Amit Daniel Kachhap amit.dan...@samsung.com
 ---

 This patch is created against linux-next tree and is suggested by
 Nishanth Menon. (https://lkml.org/lkml/2013/4/12/119)

  drivers/cpufreq/exynos5440-cpufreq.c |3 +++
  1 files changed, 3 insertions(+), 0 deletions(-)

 diff --git a/drivers/cpufreq/exynos5440-cpufreq.c 
 b/drivers/cpufreq/exynos5440-cpufreq.c
 index ead7ed4..0c74018 100644
 --- a/drivers/cpufreq/exynos5440-cpufreq.c
 +++ b/drivers/cpufreq/exynos5440-cpufreq.c
 @@ -120,11 +120,13 @@ static int init_div_table(void)
 int i = 0;
 struct opp *opp;

 +   rcu_read_lock();
 for (i = 0; freq_tbl[i].frequency != CPUFREQ_TABLE_END; i++) {

 opp = opp_find_freq_exact(dvfs_info-dev,
 freq_tbl[i].frequency * 1000, true);
 if (IS_ERR(opp)) {
 +   rcu_read_unlock();
 dev_err(dvfs_info-dev,
 failed to find valid OPP for %u KHZ\n,
 freq_tbl[i].frequency);
 @@ -159,6 +161,7 @@ static int init_div_table(void)
 __raw_writel(tmp, dvfs_info-base + XMU_PMU_P0_7 + 4 * i);
 }

 +   rcu_read_unlock();

Is it not possible to reduce the amount of code protected by RCU lock?
something like this:
+   rcu_read_lock();
opp = opp_find_freq_exact(dvfs_info-dev,
freq_tbl[i].frequency * 1000, true);
if (IS_ERR(opp)) {
+   rcu_read_unlock();
dev_err(dvfs_info-dev,
failed to find valid OPP for %u KHZ\n,
freq_tbl[i].frequency);
return PTR_ERR(opp);
}
+   volt_id = opp_get_voltage(opp);
+   rcu_unlock();
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[PATCH v2 0/3] ARM: EXYNOS: DT-enabled support for Universal C210

[Tomasz Figa]

This series intends to add support for Universal C210 board using Device
Tree. Main difference from other boards based on Exynos 4210 is that
hardware revision of the SoC used on Universal C210 does not support MCT
timers and legacy PWM timers must be used instead.

First patch adds device tree node for PWM block available on Exynos4 SoCs,
second patch adds support for Exynos4210 rev0 SoC in exynos_init_time()
and third patch introduces initial device tree for Universal C210 board.

Depends on my series for PWM timers rework:
[PATCH v5 00/14] ARM: samsung-time: Prepare for multiplatform support
(http://thread.gmane.org/gmane.linux.kernel.samsung-soc/17864)

On Universal C210 board:

Tested-by: Tomasz Figa t.f...@samsung.com

Tomasz Figa (3):
  ARM: dts: exynos4: Add node for PWM device
  ARM: EXYNOS: Fix support of Exynos4210 rev0 SoC
  ARM: dts: exynos4210: Add basic dts file for universal_c210 board

 arch/arm/boot/dts/Makefile  |   1 +
 arch/arm/boot/dts/exynos4.dtsi  |   8 +
 arch/arm/boot/dts/exynos4210-universal_c210.dts | 352 
 arch/arm/mach-exynos/common.c   |   6 +-
 arch/arm/mach-exynos/mach-universal_c210.c  |   2 +-
 5 files changed, 367 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/boot/dts/exynos4210-universal_c210.dts

-- 
1.8.1.5

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[PATCH v2 1/3] ARM: dts: exynos4: Add node for PWM device

[Tomasz Figa]

This patch adds device tree node for PWM block present on Exynos 4 SoCs.

Signed-off-by: Tomasz Figa t.f...@samsung.com
---
 arch/arm/boot/dts/exynos4.dtsi | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index d73eaa1..d7058c1 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -333,6 +333,14 @@
status = disabled;
};
 
+   pwm@139D {
+   compatible = samsung,exynos4210-pwm;
+   reg = 0x139D 0x1000;
+   interrupts = 0 37 0, 0 38 0, 0 39 0, 0 40 0, 0 41 0;
+   #pwm-cells = 2;
+   status = disabled;
+   };
+
amba {
#address-cells = 1;
#size-cells = 1;
-- 
1.8.1.5

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[PATCH v2 2/3] ARM: EXYNOS: Fix support of Exynos4210 rev0 SoC

[Tomasz Figa]

This patch extends exynos_init_time() function to handle Exynos4210 rev0
SoC, which differs in availability of system timers and needs different
clocksource initialization.

This makes it possible to use exynos_init_time() function as init_time
callback for all Exynos-based boards, including Universal_C210, which
originally had to use samsung_timer_init().

Signed-off-by: Tomasz Figa t.f...@samsung.com
---
 arch/arm/mach-exynos/common.c  | 6 +-
 arch/arm/mach-exynos/mach-universal_c210.c | 2 +-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index b65229d..ec596fc 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -51,6 +51,7 @@
 #include plat/fimc-core.h
 #include plat/iic-core.h
 #include plat/tv-core.h
+#include plat/samsung-time.h
 #include plat/spi-core.h
 #include plat/regs-serial.h
 
@@ -457,7 +458,10 @@ void __init exynos_init_time(void)
exynos4_clk_init(NULL);
exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
 #endif
-   mct_init();
+   if (soc_is_exynos4210()  samsung_rev() == EXYNOS4210_REV_0)
+   samsung_timer_init();
+   else
+   mct_init();
}
 }
 
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c 
b/arch/arm/mach-exynos/mach-universal_c210.c
index 020e1f4..a728812 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -1177,7 +1177,7 @@ MACHINE_START(UNIVERSAL_C210, UNIVERSAL_C210)
.map_io = universal_map_io,
.init_machine   = universal_machine_init,
.init_late  = exynos_init_late,
-   .init_time  = samsung_timer_init,
+   .init_time  = exynos_init_time,
.reserve= universal_reserve,
.restart= exynos4_restart,
 MACHINE_END
-- 
1.8.1.5

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[PATCH v2 3/3] ARM: dts: exynos4210: Add basic dts file for universal_c210 board

[Tomasz Figa]

This patch adds basic device tree sources for Universal C210 board.

Currently support includes:
- eMMC
- serial
- max8952 and max8998 voltage regulators.
- gpio-keys

More support will be added in further patches.

Signed-off-by: Tomasz Figa t.f...@samsung.com
---
 arch/arm/boot/dts/Makefile  |   1 +
 arch/arm/boot/dts/exynos4210-universal_c210.dts | 352 
 2 files changed, 353 insertions(+)
 create mode 100644 arch/arm/boot/dts/exynos4210-universal_c210.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 11fef62..95b7311 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
 dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos4210-smdkv310.dtb \
exynos4210-trats.dtb \
+   exynos4210-universal_c210.dtb \
exynos4412-odroidx.dtb \
exynos4412-smdk4412.dtb \
exynos4412-origen.dtb \
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts 
b/arch/arm/boot/dts/exynos4210-universal_c210.dts
new file mode 100644
index 000..8174a7a
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -0,0 +1,352 @@
+/*
+ * Samsung's Exynos4210 based Universal C210 board device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Device tree source file for Samsung's Universal C210 board which is based on
+ * Samsung's Exynos4210 EVT0 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ exynos4210.dtsi
+
+/ {
+   model = Samsung Universal C210 based on Exynos4210 EVT0;
+   compatible = samsung,universal_c210, samsung,exynos4210;
+
+   memory {
+   reg =  0x4000 0x1000
+   0x5000 0x1000;
+   };
+
+   chosen {
+   bootargs = console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw 
rootwait earlyprintk panic=5 maxcpus=1;
+   };
+
+   mct@1005 {
+   compatible = none;
+   };
+
+   fixed-rate-clocks {
+   xxti {
+   compatible = samsung,clock-xxti;
+   clock-frequency = 0;
+   };
+
+   xusbxti {
+   compatible = samsung,clock-xusbxti;
+   clock-frequency = 2400;
+   };
+   };
+
+   vemmc_reg: voltage-regulator {
+   compatible = regulator-fixed;
+   regulator-name = VMEM_VDD_2_8V;
+   regulator-min-microvolt = 280;
+   regulator-max-microvolt = 280;
+   gpio = gpe1 3 0;
+   enable-active-high;
+   };
+
+   sdhci_emmc: sdhci@1251 {
+   bus-width = 8;
+   non-removable;
+   pinctrl-0 = sd0_clk sd0_cmd sd0_bus8;
+   pinctrl-names = default;
+   vmmc-supply = vemmc_reg;
+   status = okay;
+   };
+
+   serial@1380 {
+   status = okay;
+   };
+
+   serial@1381 {
+   status = okay;
+   };
+
+   serial@1382 {
+   status = okay;
+   };
+
+   serial@1383 {
+   status = okay;
+   };
+
+   gpio-keys {
+   compatible = gpio-keys;
+
+   vol-up-key {
+   gpios = gpx2 0 1;
+   linux,code = 115;
+   label = volume up;
+   debounce-interval = 1;
+   };
+
+   vol-down-key {
+   gpios = gpx2 1 1;
+   linux,code = 114;
+   label = volume down;
+   debounce-interval = 1;
+   };
+
+   config-key {
+   gpios = gpx2 2 1;
+   linux,code = 171;
+   label = config;
+   debounce-interval = 1;
+   gpio-key,wakeup;
+   };
+
+   camera-key {
+   gpios = gpx2 3 1;
+   linux,code = 212;
+   label = camera;
+   debounce-interval = 1;
+   };
+
+   power-key {
+   gpios = gpx2 7 1;
+   linux,code = 116;
+   label = power;
+   debounce-interval = 1;
+   gpio-key,wakeup;
+   };
+
+   ok-key {
+   gpios = gpx3 5 1;
+   linux,code = 352;
+   label = ok;
+   debounce-interval = 1;
+   };
+   };
+
+   tsp_reg: voltage-regulator {
+   

Re: [PATCH v6 1/3] of/pci: Unify pci_process_bridge_OF_ranges from Microblaze and PowerPC

[Benjamin Herrenschmidt]

On Mon, 2013-04-15 at 14:57 +0200, Thomas Petazzoni wrote:
 Michal, Ben,
 
 Would you have some time to look at this patch and give your comments
 and/or ACK ? Since it touches the PowerPC and Microblaze core code, we
 need your agreement to merge this code, and quite a bit of code pending
 for 3.10 depends on this patch.

I'm currently still on vacation. I will be able to look at this after
I'm back in about a week.

 Rob, alternatively, could we imagine doing a different version of the
 'of/pci: Provide support for parsing PCI DT ranges property' that
 introduces the new API only, leaving the PowerPC and Microblaze rework
 as follow-up efforts, so that all the PCIe drivers that depend on this
 patch can get in for 3.10 ? I'd find it pretty sad if the Marvell PCIe
 driver that has been worked on since 4+ months does not get into 3.10
 just because this patch cannot be merged.

Cheers,
Ben.

 Thanks!
 
 Thomas
 
 On Thu, 11 Apr 2013 16:26:07 +0100, Andrew Murray wrote:
  The pci_process_bridge_OF_ranges function, used to parse the ranges
  property of a PCI host device, is found in both Microblaze and PowerPC
  architectures. These implementations are nearly identical. This patch
  moves this common code to a common place.
  
  Signed-off-by: Andrew Murray andrew.mur...@arm.com
  Signed-off-by: Liviu Dudau liviu.du...@arm.com
  Reviewed-by: Rob Herring rob.herr...@calxeda.com
  Tested-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
  ---
   arch/microblaze/include/asm/pci-bridge.h |5 +-
   arch/microblaze/pci/pci-common.c |  192 
  
   arch/powerpc/include/asm/pci-bridge.h|5 +-
   arch/powerpc/kernel/pci-common.c |  192 
  
   drivers/of/of_pci.c  |  200 
  ++
   include/linux/of_pci.h   |4 +
   6 files changed, 206 insertions(+), 392 deletions(-)
  
  diff --git a/arch/microblaze/include/asm/pci-bridge.h 
  b/arch/microblaze/include/asm/pci-bridge.h
  index cb5d397..5783cd6 100644
  --- a/arch/microblaze/include/asm/pci-bridge.h
  +++ b/arch/microblaze/include/asm/pci-bridge.h
  @@ -10,6 +10,7 @@
   #include linux/pci.h
   #include linux/list.h
   #include linux/ioport.h
  +#include linux/of_pci.h
   
   struct device_node;
   
  @@ -132,10 +133,6 @@ extern void setup_indirect_pci(struct pci_controller 
  *hose,
   extern struct pci_controller *pci_find_hose_for_OF_device(
  struct device_node *node);
   
  -/* Fill up host controller resources from the OF node */
  -extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
  -   struct device_node *dev, int primary);
  -
   /* Allocate  free a PCI host bridge structure */
   extern struct pci_controller *pcibios_alloc_controller(struct device_node 
  *dev);
   extern void pcibios_free_controller(struct pci_controller *phb);
  diff --git a/arch/microblaze/pci/pci-common.c 
  b/arch/microblaze/pci/pci-common.c
  index 9ea521e..2735ad9 100644
  --- a/arch/microblaze/pci/pci-common.c
  +++ b/arch/microblaze/pci/pci-common.c
  @@ -622,198 +622,6 @@ void pci_resource_to_user(const struct pci_dev *dev, 
  int bar,
  *end = rsrc-end - offset;
   }
   
  -/**
  - * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device 
  tree
  - * @hose: newly allocated pci_controller to be setup
  - * @dev: device node of the host bridge
  - * @primary: set if primary bus (32 bits only, soon to be deprecated)
  - *
  - * This function will parse the ranges property of a PCI host bridge 
  device
  - * node and setup the resource mapping of a pci controller based on its
  - * content.
  - *
  - * Life would be boring if it wasn't for a few issues that we have to deal
  - * with here:
  - *
  - *   - We can only cope with one IO space range and up to 3 Memory space
  - * ranges. However, some machines (thanks Apple !) tend to split their
  - * space into lots of small contiguous ranges. So we have to coalesce.
  - *
  - *   - We can only cope with all memory ranges having the same offset
  - * between CPU addresses and PCI addresses. Unfortunately, some bridges
  - * are setup for a large 1:1 mapping along with a small window which
  - * maps PCI address 0 to some arbitrary high address of the CPU space 
  in
  - * order to give access to the ISA memory hole.
  - * The way out of here that I've chosen for now is to always set the
  - * offset based on the first resource found, then override it if we
  - * have a different offset and the previous was set by an ISA hole.
  - *
  - *   - Some busses have IO space not starting at 0, which causes trouble 
  with
  - * the way we do our IO resource renumbering. The code somewhat deals 
  with
  - * it for 64 bits but I would expect problems on 32 bits.
  - *
  - *   - Some 32 bits platforms such as 4xx can have physical space larger 
  than
  - * 32 bits so we 

Re: [PATCH] iio: adc: exynos_adc: Handle timeout issues

[Doug Anderson]

Naveen,

On Fri, Apr 12, 2013 at 9:36 PM, Naveen Krishna Ch
naveenkrishna...@gmail.com wrote:
 Can some one review this and get this fix into the tree.

I think the ball is in your court.  Lars responded to your RFC patch
here and requested that you do a reset of the bus in the case of being
interrupted.

https://lkml.org/lkml/2013/4/5/91

I made a comment about perhaps just using non-interruptable and then
shortening the timeout and Lars thought that would be OK.  ...but I've
since thought about it and I think Lars' suggestion is best.

The reason I no longer like my suggestion of just using a 1ms
non-interruptable tiemout is that I'm slightly worried about running
into some case where the interrupt gets blocked for a while and then
we get timeouts for no reasons.  Perhaps I'm worrying over nothing,
but Lars' suggestion doesn't have this issue.

-Doug
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Re: [PATCH] i2c: s3c2410: Add SMBus emulation for block read

[Wolfram Sang]

 I don't know if that can happen, but if the block has length 0 (that is,
 only consists of a single byte that is read as 0) the is_msglast() test
 returns 0 which might be wrong. Maybe even if it cannot regularily
 happen handle it in a sane way?

Length of 0 is illegal according to the specs, but a check won't hurt.

 Also I wonder if error checking for byte  I2C_SMBUS_BLOCK_MAX would be
 needed to prevent a buffer overrun?

Yes. Although I have seen devices able to send more than that, yet
adding support for that is a seperate issue.

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Re: [PATCH v6 1/3] of/pci: Unify pci_process_bridge_OF_ranges from Microblaze and PowerPC

[Michal Simek]

Hi Thomas and Andrew,

First of all I would recommend you to add your tree to 0-day testing
system where you can easily catch up compilation failures for
microblaze and others.

Getting this compilation failure:
drivers/of/of_pci.c: In function 'pci_process_bridge_OF_ranges':
drivers/of/of_pci.c:88:22: error: storage size of 'range' isn't known
drivers/of/of_pci.c:89:29: error: storage size of 'parser' isn't known
drivers/of/of_pci.c:96:2: error: implicit declaration of function 
'of_pci_range_parser' [-Werror=implicit-function-declaration]
drivers/of/of_pci.c:100:2: error: implicit declaration of function 
'for_each_of_pci_range' [-Werror=implicit-function-declaration]
drivers/of/of_pci.c:100:41: error: expected ';' before '{' token
drivers/of/of_pci.c:90:6: warning: unused variable 'res_type' 
[-Wunused-variable]
drivers/of/of_pci.c:89:29: warning: unused variable 'parser' [-Wunused-variable]
drivers/of/of_pci.c:88:22: warning: unused variable 'range' [-Wunused-variable]
drivers/of/of_pci.c:87:19: warning: unused variable 'res' [-Wunused-variable]
drivers/of/of_pci.c:86:21: warning: unused variable 'isa_mb' [-Wunused-variable]
drivers/of/of_pci.c:85:17: warning: unused variable 'isa_hole' 
[-Wunused-variable]
drivers/of/of_pci.c:85:6: warning: unused variable 'memno' [-Wunused-variable]

which is caused missing linux/of_addresss.h in of_pci.c.
PowerPC probably won't have this problem because you have this header in 
asm/prom.h
but based on the same comment it is better to add it directly to the files.

That's why please add this header to this patch.

diff --git a/drivers/of/of_pci.c b/drivers/of/of_pci.c
index 3e428a1..f30887e 100644
--- a/drivers/of/of_pci.c
+++ b/drivers/of/of_pci.c
@@ -1,6 +1,7 @@
 #include linux/kernel.h
 #include linux/export.h
 #include linux/of.h
+#include linux/of_address.h
 #include linux/of_pci.h
 #include asm/prom.h


When you fix it:
Acked-by: Michal Simek mon...@monstr.eu

Thanks,
Michal



On 04/15/2013 02:57 PM, Thomas Petazzoni wrote:
 Michal, Ben,
 
 Would you have some time to look at this patch and give your comments
 and/or ACK ? Since it touches the PowerPC and Microblaze core code, we
 need your agreement to merge this code, and quite a bit of code pending
 for 3.10 depends on this patch.
 
 Rob, alternatively, could we imagine doing a different version of the
 'of/pci: Provide support for parsing PCI DT ranges property' that
 introduces the new API only, leaving the PowerPC and Microblaze rework
 as follow-up efforts, so that all the PCIe drivers that depend on this
 patch can get in for 3.10 ? I'd find it pretty sad if the Marvell PCIe
 driver that has been worked on since 4+ months does not get into 3.10
 just because this patch cannot be merged.
 
 Thanks!
 
 Thomas
 
 On Thu, 11 Apr 2013 16:26:07 +0100, Andrew Murray wrote:
 The pci_process_bridge_OF_ranges function, used to parse the ranges
 property of a PCI host device, is found in both Microblaze and PowerPC
 architectures. These implementations are nearly identical. This patch
 moves this common code to a common place.

 Signed-off-by: Andrew Murray andrew.mur...@arm.com
 Signed-off-by: Liviu Dudau liviu.du...@arm.com
 Reviewed-by: Rob Herring rob.herr...@calxeda.com
 Tested-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
 ---
  arch/microblaze/include/asm/pci-bridge.h |5 +-
  arch/microblaze/pci/pci-common.c |  192 
  arch/powerpc/include/asm/pci-bridge.h|5 +-
  arch/powerpc/kernel/pci-common.c |  192 
  drivers/of/of_pci.c  |  200 
 ++
  include/linux/of_pci.h   |4 +
  6 files changed, 206 insertions(+), 392 deletions(-)

 diff --git a/arch/microblaze/include/asm/pci-bridge.h 
 b/arch/microblaze/include/asm/pci-bridge.h
 index cb5d397..5783cd6 100644
 --- a/arch/microblaze/include/asm/pci-bridge.h
 +++ b/arch/microblaze/include/asm/pci-bridge.h
 @@ -10,6 +10,7 @@
  #include linux/pci.h
  #include linux/list.h
  #include linux/ioport.h
 +#include linux/of_pci.h
  
  struct device_node;
  
 @@ -132,10 +133,6 @@ extern void setup_indirect_pci(struct pci_controller 
 *hose,
  extern struct pci_controller *pci_find_hose_for_OF_device(
  struct device_node *node);
  
 -/* Fill up host controller resources from the OF node */
 -extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
 -struct device_node *dev, int primary);
 -
  /* Allocate  free a PCI host bridge structure */
  extern struct pci_controller *pcibios_alloc_controller(struct device_node 
 *dev);
  extern void pcibios_free_controller(struct pci_controller *phb);
 diff --git a/arch/microblaze/pci/pci-common.c 
 b/arch/microblaze/pci/pci-common.c
 index 9ea521e..2735ad9 100644
 --- a/arch/microblaze/pci/pci-common.c
 +++ b/arch/microblaze/pci/pci-common.c
 @@ -622,198 +622,6 @@ void pci_resource_to_user(const struct pci_dev *dev, 
 int 

Re: [PATCH 1/7] clk: exynos: prepare for multiplatform

[Sylwester Nawrocki]

On 04/15/2013 10:35 AM, Arnd Bergmann wrote:
 On Monday 15 April 2013, Thomas Abraham wrote:
 On 12 April 2013 19:33, Arnd Bergmann a...@arndb.de wrote:
 The new common clock drivers for exynos are using compile
 time constants and soc_is_exynos* macros to provide backwards
 compatibility for pre-DT systems, which is not possible with
 multiplatform kernels. This moves all the necessary
 information back into platform code and removes the mach/*
 header inclusions.


 Since kgene has submitted a patch to remove pre-dt Exynos support
 which looks like it will be accepted, we could just remove the use of
 soc_is_xyz() instead of continuing to support non-dt Exynos.
 
 I think based on the most recent discussion, we are not actually doing
 that for 3.10, since there are still people that require ATAGS support.

It seems patches from Tomasz [1] will likely make it to 3.10, thus
it is fine to apply Kukjin's patch as far as we are concerned.

Besides, it seems some drivers are already broken with ATAGS booting
(e.g. Exynos DRM, SDHCI) due to introduction of the common clock
framework driver. It doesn't seem worthwhile to spend time fixing
this, I would rather focus on improving the DT support.

Sorry for any confusion.

[1] http://www.spinics.net/lists/arm-kernel/msg238387.html

Sylwester
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Re: [PATCH] spi: s3c64xx: let device core setup the default pin configuration

[Doug Anderson]

Mark,

On Mon, Mar 11, 2013 at 10:36 AM, Doug Anderson diand...@chromium.org wrote:
 Thomas,

 On Wed, Mar 6, 2013 at 3:42 AM, Thomas Abraham
 thomas.abra...@linaro.org wrote:
 With device core now able to setup the default pin configuration,
 the pin configuration code based on the deprecated Samsung specific
 gpio bindings is removed.

 Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
 ---
  .../devicetree/bindings/spi/spi-samsung.txt|8 +--
  drivers/spi/spi-s3c64xx.c  |   66 
 +--
  2 files changed, 6 insertions(+), 68 deletions(-)

Is this something you would pick up?  It looks like you weren't copied
on the original email thread, unfortunately.

Without this (or some equivalent) patch we can't use the SPI driver on
any SoCs that have switched over to the proper pinmux support.

Thanks!

-Doug
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Re: [PATCH] spi: s3c64xx: let device core setup the default pin configuration

[Linus Walleij]

On Mon, Apr 15, 2013 at 7:23 PM, Doug Anderson diand...@chromium.org wrote:

 Mark,
(...)
 Is this something you would pick up?  It looks like you weren't copied
 on the original email thread, unfortunately.

Resend the patch with collected ACKs and Mark+Grant explitly on the
To: line and I think it'll be picked up.

Yours,
Linus Walleij
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[PATCH v5 0/6] Initial Device Tree support for S3C64xx

[Tomasz Figa]

This series adds Device Tree support for Samsung S3C64xx SoC series.

It fixes several problems preventing from booting an S3C64xx-based system
using Device Tree, adds all the infrastructure for Device Tree-based board
support, including mach-s3c64xx-dt and dts include files for S3C64xx SoCs,
and basic device tree source for FriendlyARM Mini6410 board.

Current support is very limited and allows only basic bootup with UART and
SDHCI, but should be fine as a start and will be extended in future,
hopefully with help of S3C64xx board maintainers.

This series depends on my other series reworking samsung-time for
multiplatform:
[PATCH v5 00/14] ARM: samsung-time: Prepare for multiplatform support
http://thread.gmane.org/gmane.linux.kernel.samsung-soc/17864

Changes since v4:
 - Rebased onto current for-next branch of Kgene's tree
 - Added support for pinctrl (driver merged through pinctrl tree)
 - Added labels to all nodes that can be overridden from board dts
 - Modified board dts to use the label syntax to reference device nodes

Changes since v3:
 - Rebased onto current for-next branch of Kgene's tree
 - Updated timer node for next version of samsung-time patches
 - Replaced local s3c64xx_dt_init_irq with irqchip_init

Changes since v2:
 - Updated timer node for next version of samsung-time patches

Changes since v1:
 - Dropped two VIC-related patches that are no longer necessary
 - Added Device Tree-based instantation of system timers
 - Corrected VIC interrupt specifiers
 - Adjusted CPU compatible values and dropped @id

Tomasz Figa (6):
  ARM: common: vic: Parse interrupt and resume masks from device tree
  ARM: s3c64xx: Skip legacy EINT setup if pinctrl-s3c64xx driver is
present
  gpio: samsung: Skip legacy GPIO registration if pinctrl-s3c64xx is
present
  ARM: s3c64xx: Add board file for boot using Device Tree
  ARM: dts: Add basic dts include files for Samsung S3C64xx SoCs
  ARM: dts: Add dts file for S3C6410-based Mini6410 board

 Documentation/devicetree/bindings/arm/vic.txt |   6 +
 arch/arm/boot/dts/Makefile|   1 +
 arch/arm/boot/dts/s3c6400.dtsi|  33 ++
 arch/arm/boot/dts/s3c6410-mini6410.dts| 168 +++
 arch/arm/boot/dts/s3c6410.dtsi|  33 ++
 arch/arm/boot/dts/s3c64xx-pinctrl.dtsi| 683 ++
 arch/arm/boot/dts/s3c64xx.dtsi| 136 +
 arch/arm/mach-s3c64xx/Kconfig |  16 +
 arch/arm/mach-s3c64xx/Makefile|   1 +
 arch/arm/mach-s3c64xx/common.c|  20 +-
 arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c   |  83 
 drivers/gpio/gpio-samsung.c   |   4 +-
 drivers/irqchip/irq-vic.c |   7 +-
 13 files changed, 1188 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/boot/dts/s3c6400.dtsi
 create mode 100644 arch/arm/boot/dts/s3c6410-mini6410.dts
 create mode 100644 arch/arm/boot/dts/s3c6410.dtsi
 create mode 100644 arch/arm/boot/dts/s3c64xx-pinctrl.dtsi
 create mode 100644 arch/arm/boot/dts/s3c64xx.dtsi
 create mode 100644 arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c

-- 
1.8.1.5

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[PATCH v5 1/6] ARM: common: vic: Parse interrupt and resume masks from device tree

[Tomasz Figa]

This patch extends vic_of_init to parse valid interrupt sources
and resume sources masks from device tree.

If mask values are not specified in device tree, all sources
are assumed to be valid, as before this patch.

Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
 Documentation/devicetree/bindings/arm/vic.txt | 6 ++
 drivers/irqchip/irq-vic.c | 7 ++-
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/vic.txt 
b/Documentation/devicetree/bindings/arm/vic.txt
index 266716b..bb7137c 100644
--- a/Documentation/devicetree/bindings/arm/vic.txt
+++ b/Documentation/devicetree/bindings/arm/vic.txt
@@ -18,6 +18,9 @@ Required properties:
 Optional properties:
 
 - interrupts : Interrupt source for parent controllers if the VIC is nested.
+- interrupt-mask : Bit mask of valid interrupt sources (defaults to all valid)
+- wakeup-mask : Bit mask of interrupt sources that can wake up the system
+  (defaults to all allowed)
 
 Example:
 
@@ -26,4 +29,7 @@ Example:
interrupt-controller;
#interrupt-cells = 1;
reg = 0x6 0x1000;
+
+   interrupt-mask = 0xff7f;
+   wakeup-mask = 0xff7f;
};
diff --git a/drivers/irqchip/irq-vic.c b/drivers/irqchip/irq-vic.c
index 3cf97aa..61602df 100644
--- a/drivers/irqchip/irq-vic.c
+++ b/drivers/irqchip/irq-vic.c
@@ -468,6 +468,8 @@ void __init vic_init(void __iomem *base, unsigned int 
irq_start,
 int __init vic_of_init(struct device_node *node, struct device_node *parent)
 {
void __iomem *regs;
+   u32 interrupt_mask = ~0;
+   u32 wakeup_mask = ~0;
 
if (WARN(parent, non-root VICs are not supported))
return -EINVAL;
@@ -476,10 +478,13 @@ int __init vic_of_init(struct device_node *node, struct 
device_node *parent)
if (WARN_ON(!regs))
return -EIO;
 
+   of_property_read_u32(node, interrupt-mask, interrupt_mask);
+   of_property_read_u32(node, wakeup-mask, wakeup_mask);
+
/*
 * Passing 0 as first IRQ makes the simple domain allocate descriptors
 */
-   __vic_init(regs, 0, ~0, ~0, node);
+   __vic_init(regs, 0, interrupt_mask, wakeup_mask, node);
 
return 0;
 }
-- 
1.8.1.5

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[PATCH v5 2/6] ARM: s3c64xx: Skip legacy EINT setup if pinctrl-s3c64xx driver is present

[Tomasz Figa]

The new pinctrl-s3c64xx is responsible for EINT handling on DT-enabled
platforms.

Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
 arch/arm/mach-s3c64xx/common.c | 20 +++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index e79ca92..866be9e 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -365,7 +365,25 @@ static void s3c_irq_demux_eint20_27(unsigned int irq, 
struct irq_desc *desc)
 static int __init s3c64xx_init_irq_eint(void)
 {
int irq;
-
+#if defined(CONFIG_PINCTRL_S3C64XX)
+   /*
+   * This gpio driver includes support for device tree support and there
+   * are platforms using it. In order to maintain compatibility with those
+   * platforms, and to allow non-dt Exynos4210 platforms to use this
+   * gpiolib support, a check is added to find out if there is a active
+   * pin-controller driver support available. If it is available, this
+   * gpiolib support is ignored and the gpiolib support available in
+   * pin-controller driver is used. This is a temporary check and will go
+   * away when all of the Exynos4210 platforms have switched to using
+   * device tree and the pin-ctrl driver.
+   */
+   struct device_node *pctrl_np;
+
+   pctrl_np = of_find_compatible_node(NULL, NULL,
+   samsung,s3c64xx-pinctrl);
+   if (pctrl_np  of_device_is_available(pctrl_np))
+   return -ENODEV;
+#endif
for (irq = IRQ_EINT(0); irq = IRQ_EINT(27); irq++) {
irq_set_chip_and_handler(irq, s3c_irq_eint, handle_level_irq);
irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
-- 
1.8.1.5

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[PATCH v5 3/6] gpio: samsung: Skip legacy GPIO registration if pinctrl-s3c64xx is present

[Tomasz Figa]

The new driver handles GPIO on DT-enabled platforms.

Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
 drivers/gpio/gpio-samsung.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index 99e0fa4..dc06a6f 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -3012,7 +3012,7 @@ static __init int samsung_gpiolib_init(void)
int i, nr_chips;
int group = 0;
 
-#if defined(CONFIG_PINCTRL_EXYNOS) || defined(CONFIG_PINCTRL_EXYNOS5440)
+#if defined(CONFIG_PINCTRL_SAMSUNG) || defined(CONFIG_PINCTRL_EXYNOS5440)
/*
* This gpio driver includes support for device tree support and there
* are platforms using it. In order to maintain compatibility with those
@@ -3026,10 +3026,12 @@ static __init int samsung_gpiolib_init(void)
*/
struct device_node *pctrl_np;
static const struct of_device_id exynos_pinctrl_ids[] = {
+   { .compatible = samsung,s3c64xx-pinctrl, },
{ .compatible = samsung,exynos4210-pinctrl, },
{ .compatible = samsung,exynos4x12-pinctrl, },
{ .compatible = samsung,exynos5250-pinctrl, },
{ .compatible = samsung,exynos5440-pinctrl, },
+   { },
};
for_each_matching_node(pctrl_np, exynos_pinctrl_ids)
if (pctrl_np  of_device_is_available(pctrl_np))
-- 
1.8.1.5

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[PATCH v5 4/6] ARM: s3c64xx: Add board file for boot using Device Tree

[Tomasz Figa]

This patch adds board file that will be used to boot S3C64xx-based boards
using Device Tree.

Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
 arch/arm/mach-s3c64xx/Kconfig   | 16 +++
 arch/arm/mach-s3c64xx/Makefile  |  1 +
 arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c | 83 +
 3 files changed, 100 insertions(+)
 create mode 100644 arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c

diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 283cb77..184d53c 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -311,3 +311,19 @@ config MACH_WLF_CRAGG_6410
select SAMSUNG_GPIO_EXTRA128
help
  Machine support for the Wolfson Cragganmore S3C6410 variant.
+
+config MACH_S3C64XX_DT
+   bool Samsung S3C6400/S3C6410 machine using Device Tree
+   select CLKSRC_OF
+   select CPU_S3C6400
+   select CPU_S3C6410
+   select PINCTRL
+   select PINCTRL_S3C64XX
+   select USE_OF
+   help
+ Machine support for Samsung S3C6400/S3C6410 machines with Device Tree
+ enabled.
+ Select this if a fdt blob is available for your S3C64XX SoC based
+ board.
+ Note: This is under development and not all peripherals can be
+ supported with this machine file.
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index 31d0c91..5e5eb4b 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -57,3 +57,4 @@ obj-$(CONFIG_MACH_SMARTQ7)+= mach-smartq7.o
 obj-$(CONFIG_MACH_SMDK6400)+= mach-smdk6400.o
 obj-$(CONFIG_MACH_SMDK6410)+= mach-smdk6410.o
 obj-$(CONFIG_MACH_WLF_CRAGG_6410)  += mach-crag6410.o 
mach-crag6410-module.o
+obj-$(CONFIG_MACH_S3C64XX_DT)  += mach-s3c64xx-dt.o
diff --git a/arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c 
b/arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c
new file mode 100644
index 000..10b76cc
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c
@@ -0,0 +1,83 @@
+/*
+ * Samsung's S3C64XX flattened device tree enabled machine
+ *
+ * Copyright (c) 2013 Tomasz Figa tomasz.f...@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include linux/clocksource.h
+#include linux/irqchip.h
+#include linux/of_irq.h
+#include linux/of_platform.h
+#include linux/serial_core.h
+
+#include asm/mach/arch.h
+#include mach/map.h
+
+#include plat/cpu.h
+#include plat/regs-serial.h
+
+#include common.h
+
+/*
+ * The following lookup table is used to override device names when devices
+ * are registered from device tree. This is temporarily added to enable
+ * device tree support addition for the S3C64xx architecture.
+ *
+ * For drivers that require platform data to be provided from the machine
+ * file, a platform data pointer can also be supplied along with the
+ * devices names. Usually, the platform data elements that cannot be parsed
+ * from the device tree by the drivers (example: function pointers) are
+ * supplied. But it should be noted that this is a temporary mechanism and
+ * at some point, the drivers should be capable of parsing all the platform
+ * data from the device tree.
+ */
+static const struct of_dev_auxdata s3c64xx_auxdata_lookup[] __initconst = {
+   OF_DEV_AUXDATA(samsung,s3c6400-uart, 0x7f005000,
+   s3c6400-uart.0, NULL),
+   OF_DEV_AUXDATA(samsung,s3c6400-uart, 0x7f005400,
+   s3c6400-uart.1, NULL),
+   OF_DEV_AUXDATA(samsung,s3c6400-uart, 0x7f005800,
+   s3c6400-uart.2, NULL),
+   OF_DEV_AUXDATA(samsung,s3c6400-uart, 0x7f005c00,
+   s3c6400-uart.3, NULL),
+   OF_DEV_AUXDATA(samsung,s3c6410-sdhci, 0x7c20,
+   s3c-sdhci.0, NULL),
+   OF_DEV_AUXDATA(samsung,s3c6410-sdhci, 0x7c30,
+   s3c-sdhci.1, NULL),
+   OF_DEV_AUXDATA(samsung,s3c6410-sdhci, 0x7c40,
+   s3c-sdhci.2, NULL),
+   {},
+};
+
+static void __init s3c64xx_dt_map_io(void)
+{
+   s3c64xx_init_io(NULL, 0);
+   s3c24xx_init_clocks(1200);
+}
+
+static void __init s3c64xx_dt_machine_init(void)
+{
+   of_platform_populate(NULL, of_default_bus_match_table,
+   s3c64xx_auxdata_lookup, NULL);
+}
+
+static char const *s3c64xx_dt_compat[] __initdata = {
+   samsung,s3c6400,
+   samsung,s3c6410,
+   NULL
+};
+
+DT_MACHINE_START(S3C6400_DT, Samsung S3C64xx (Flattened Device Tree))
+   /* Maintainer: Tomasz Figa tomasz.f...@gmail.com */
+   .init_irq   = irqchip_init,
+   .map_io = s3c64xx_dt_map_io,
+   .init_machine   = s3c64xx_dt_machine_init,
+   .init_late  = 

[PATCH v5 5/6] ARM: dts: Add basic dts include files for Samsung S3C64xx SoCs

[Tomasz Figa]

This patch adds basic device tree definitions for Samsung S3C64xx SoCs.

Since all the SoCs in the series are very similar, the files are created
hierarchically - one file for the whole series and then separate files
for particular SoCs including the common one.

Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
 arch/arm/boot/dts/s3c6400.dtsi |  33 ++
 arch/arm/boot/dts/s3c6410.dtsi |  33 ++
 arch/arm/boot/dts/s3c64xx-pinctrl.dtsi | 683 +
 arch/arm/boot/dts/s3c64xx.dtsi | 136 +++
 4 files changed, 885 insertions(+)
 create mode 100644 arch/arm/boot/dts/s3c6400.dtsi
 create mode 100644 arch/arm/boot/dts/s3c6410.dtsi
 create mode 100644 arch/arm/boot/dts/s3c64xx-pinctrl.dtsi
 create mode 100644 arch/arm/boot/dts/s3c64xx.dtsi

diff --git a/arch/arm/boot/dts/s3c6400.dtsi b/arch/arm/boot/dts/s3c6400.dtsi
new file mode 100644
index 000..76106b8
--- /dev/null
+++ b/arch/arm/boot/dts/s3c6400.dtsi
@@ -0,0 +1,33 @@
+/*
+ * Samsung's S3C6400 SoC device tree source
+ *
+ * Copyright (c) 2013 Tomasz Figa tomasz.f...@gmail.com
+ *
+ * Samsung's S3C6400 SoC device nodes are listed in this file. S3C6400
+ * based board files can include this file and provide values for board specfic
+ * bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * S3C6400 SoC. As device tree coverage for S3C6400 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/include/ s3c64xx.dtsi
+
+/ {
+   compatible = samsung,s3c6400;
+
+   vic0: interrupt-controller@7120 {
+   interrupt-mask = 0xfe1f;
+   wakeup-mask = 0x0024;
+   };
+
+   vic1: interrupt-controller@7130 {
+   interrupt-mask = 0x;
+   wakeup-mask = 0x5302;
+   };
+};
diff --git a/arch/arm/boot/dts/s3c6410.dtsi b/arch/arm/boot/dts/s3c6410.dtsi
new file mode 100644
index 000..4a74df9
--- /dev/null
+++ b/arch/arm/boot/dts/s3c6410.dtsi
@@ -0,0 +1,33 @@
+/*
+ * Samsung's S3C6410 SoC device tree source
+ *
+ * Copyright (c) 2013 Tomasz Figa tomasz.f...@gmail.com
+ *
+ * Samsung's S3C6410 SoC device nodes are listed in this file. S3C6410
+ * based board files can include this file and provide values for board specfic
+ * bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * S3C6410 SoC. As device tree coverage for S3C6410 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/include/ s3c64xx.dtsi
+
+/ {
+   compatible = samsung,s3c6410;
+
+   vic0: interrupt-controller@7120 {
+   interrupt-mask = 0xff7f;
+   wakeup-mask = 0x0024;
+   };
+
+   vic1: interrupt-controller@7130 {
+   interrupt-mask = 0x;
+   wakeup-mask = 0x5302;
+   };
+};
diff --git a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi 
b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi
new file mode 100644
index 000..738017f
--- /dev/null
+++ b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi
@@ -0,0 +1,683 @@
+/*
+ * Samsung's S3C64xx SoC series common device tree source
+ * - pin control-related definitions
+ *
+ * Copyright (c) 2013 Tomasz Figa tomasz.f...@gmail.com
+ *
+ * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are
+ * listed as device tree nodes in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+pinctrl0 {
+   /*
+* Pin banks
+*/
+
+   gpa: gpa {
+   gpio-controller;
+   #gpio-cells = 2;
+   interrupt-controller;
+   #interrupt-cells = 2;
+   };
+
+   gpb: gpb {
+   gpio-controller;
+   #gpio-cells = 2;
+   interrupt-controller;
+   #interrupt-cells = 2;
+   };
+
+   gpc: gpc {
+   gpio-controller;
+   #gpio-cells = 2;
+   interrupt-controller;
+   #interrupt-cells = 2;
+   };
+
+   gpd: gpd {
+   gpio-controller;
+   #gpio-cells = 2;
+   interrupt-controller;
+   #interrupt-cells = 2;
+   };
+
+   gpe: gpe {
+   gpio-controller;
+   #gpio-cells = 2;
+   };
+
+   gpf: gpf {
+   gpio-controller;
+   #gpio-cells = 2;
+   interrupt-controller;
+   #interrupt-cells = 2;
+   };
+
+   gpg: gpg 

[PATCH v5 6/6] ARM: dts: Add dts file for S3C6410-based Mini6410 board

[Tomasz Figa]

This patch adds basic device tree sources for FriendlyARM Mini6410 board
based on Samsung S3C6410 SoC.

Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
 arch/arm/boot/dts/Makefile |   1 +
 arch/arm/boot/dts/s3c6410-mini6410.dts | 168 +
 2 files changed, 169 insertions(+)
 create mode 100644 arch/arm/boot/dts/s3c6410-mini6410.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 11fef62..5885c37 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -138,6 +138,7 @@ dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
hrefprev60.dtb \
hrefv60plus.dtb \
ccu9540.dtb
+dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb
 dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
r8a7740-armadillo800eva.dtb \
sh73a0-kzm9g.dtb \
diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts 
b/arch/arm/boot/dts/s3c6410-mini6410.dts
new file mode 100644
index 000..679b1bb
--- /dev/null
+++ b/arch/arm/boot/dts/s3c6410-mini6410.dts
@@ -0,0 +1,168 @@
+/*
+ * Samsung's S3C6410 based Mini6410 board device tree source
+ *
+ * Copyright (c) 2013 Tomasz Figa tomasz.f...@gmail.com
+ *
+ * Device tree source file for FriendlyARM Mini6410 board which is based on
+ * Samsung's S3C6410 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ s3c6410.dtsi
+
+/ {
+   model = FriendlyARM Mini6410 board based on S3C6410;
+   compatible = friendlyarm,mini6410, samsung,s3c6410;
+
+   memory {
+   reg = 0x5000 0x1000;
+   };
+
+   chosen {
+   bootargs = console=ttySAC0,115200n8 earlyprintk rootwait 
root=/dev/mmcblk0p1;
+   };
+
+   gpio-keys {
+   compatible = gpio-keys;
+   pinctrl-names = default;
+   pinctrl-0 = gpio_keys;
+   autorepeat;
+
+   button-k1 {
+   label = K1;
+   gpios = gpn 0 1;
+   linux,code = 2;
+   debounce-interval = 20;
+   };
+
+   button-k2 {
+   label = K2;
+   gpios = gpn 1 1;
+   linux,code = 3;
+   debounce-interval = 20;
+   };
+
+   button-k3 {
+   label = K3;
+   gpios = gpn 2 1;
+   linux,code = 4;
+   debounce-interval = 20;
+   };
+
+   button-k4 {
+   label = K4;
+   gpios = gpn 3 1;
+   linux,code = 5;
+   debounce-interval = 20;
+   };
+
+   button-k5 {
+   label = K5;
+   gpios = gpn 4 1;
+   linux,code = 6;
+   debounce-interval = 20;
+   };
+
+   button-k6 {
+   label = K6;
+   gpios = gpn 5 1;
+   linux,code = 7;
+   debounce-interval = 20;
+   };
+
+   button-k7 {
+   label = K7;
+   gpios = gpl 11 1;
+   linux,code = 8;
+   debounce-interval = 20;
+   };
+
+   button-k8 {
+   label = K8;
+   gpios = gpl 12 1;
+   linux,code = 9;
+   debounce-interval = 20;
+   };
+   };
+
+   leds {
+   compatible = gpio-leds;
+   pinctrl-names = default;
+   pinctrl-0 = gpio_leds;
+
+   led-1 {
+   label = LED1;
+   gpios = gpk 4 1;
+   linux,default-trigger = heartbeat;
+   };
+
+   led-2 {
+   label = LED2;
+   gpios = gpk 5 1;
+   linux,default-trigger = mmc0;
+   };
+
+   led-3 {
+   label = LED3;
+   gpios = gpk 6 1;
+   };
+
+   led-4 {
+   label = LED4;
+   gpios = gpk 7 1;
+   };
+   };
+};
+
+pinctrl0 {
+   gpio_leds: gpio-leds {
+   samsung,pins = gpk-4, gpk-5, gpk-6, gpk-7;
+   samsung,pin-function = 1;
+   samsung,pin-pud = 0;
+   };
+
+   gpio_keys: gpio-keys {
+   samsung,pins = gpn-0, gpn-1, gpn-2, gpn-3,
+   gpn-4, gpn-5, gpl-11, gpl-12;
+   samsung,pin-pud = 0;
+   };
+};
+
+pwm {
+   status = okay;
+};
+
+uart0 {
+   pinctrl-names = default;
+  

Re: [PATCH v6 0/3] of/pci: Provide common support for PCI DT parsing

[Jason Cooper]

Andrew Murray, Thomas,

On Thu, Apr 11, 2013 at 04:26:06PM +0100, Andrew Murray wrote:
 This patchset factors out duplicated code associated with parsing PCI
 DT ranges properties across the architectures and introduces a
 ranges parser. This parser of_pci_range_parser can be used directly
 by ARM host bridge drivers enabling them to obtain ranges from device
 trees.
 
 I've included the Reviewed-by and Tested-by's received from v5 in this
 patchset, earlier versions of this patchset (v3) have been tested-by:
 
 Thierry Reding thierry.red...@avionic-design.de
 Jingoo Han jg1@samsung.com
 
 I believe a version of this patchset has also been tested through its
 inclusion in Thomas Petazzoni's Armada 370 and Armada XP SoCs PCIe support by:
 
 Linus Walleij linus.wall...@linaro.org
 
 I've tested that this patchset builds and runs on ARM and that it builds on
 PowerPC.
 
 Compared to the v5 sent by Andrew Murray, the following changes have
 been made:
 
  * Use of CONFIG_64BIT instead of CONFIG_[a32bitarch] as suggested by
Rob Herring in drivers/of/of_pci.c
 
  * Added forward declaration of struct pci_controller in linux/of_pci.h
to prevent compiler warning as suggested by Thomas Petazzoni
 
  * Improved error checking (!range check), removal of unnecessary be32_to_cpup
call, improved formatting of struct of_pci_range_parser layout and
replacement of macro with a static inline. All suggested by Rob Herring.
 
 Compared to the v4 (incorrectly labelled v3) sent by Andrew Murray,
 the following changes have been made:
 
  * Split the patch as suggested by Rob Herring
 
 Compared to the v3 sent by Andrew Murray, the following changes have
 been made:
 
  * Unify and move duplicate pci_process_bridge_OF_ranges functions to
drivers/of/of_pci.c as suggested by Rob Herring
 
  * Fix potential build errors with Microblaze/MIPS
 
 Compared to [PATCH v5 01/17] of/pci: Provide support for parsing PCI DT
 ranges property, the following changes have been made:
 
  * Correct use of IORESOURCE_* as suggested by Russell King
 
  * Improved interface and naming as suggested by Thierry Reding
 
 Compared to the v2 sent by Andrew Murray, Thomas Petazzoni did:
 
  * Add a memset() on the struct of_pci_range_iter when starting the
for loop in for_each_pci_range(). Otherwise, with an uninitialized
of_pci_range_iter, of_pci_process_ranges() may crash.
 
  * Add parenthesis around 'res', 'np' and 'iter' in the
for_each_of_pci_range macro definitions. Otherwise, passing
something like foobar as 'res' didn't work.
 
  * Rebased on top of 3.9-rc2, which required fixing a few conflicts in
the Microblaze code.
 
 v2:
   This follows on from suggestions made by Grant Likely
   (marc.info/?l=linux-kernelm=136079602806328)
 
 Andrew Murray (3):
   of/pci: Unify pci_process_bridge_OF_ranges from Microblaze and
 PowerPC
   of/pci: Provide support for parsing PCI DT ranges property
   of/pci: mips: convert to common of_pci_range_parser
 
  arch/microblaze/include/asm/pci-bridge.h |5 +-
  arch/microblaze/pci/pci-common.c |  192 
 --
  arch/mips/pci/pci.c  |   50 +++--
  arch/powerpc/include/asm/pci-bridge.h|5 +-
  arch/powerpc/kernel/pci-common.c |  192 
 --
  drivers/of/address.c |   66 ++
  drivers/of/of_pci.c  |  168 ++
  include/linux/of_address.h   |   46 +++
  include/linux/of_pci.h   |4 +
  9 files changed, 302 insertions(+), 426 deletions(-)

As agreed with Rob Herring, series applied to mvebu/drivers to support
mvebu pcie driver.

thx,

Jason.
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[REPOST PATCH] spi: s3c64xx: let device core setup the default pin configuration

[Doug Anderson]

From: Thomas Abraham thomas.abra...@linaro.org

With device core now able to setup the default pin configuration,
the pin configuration code based on the deprecated Samsung specific
gpio bindings is removed.

Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
Signed-off-by: Doug Anderson diand...@chromium.org
Acked-by: Linus Walleij linus.wall...@linaro.org
Reviewed-by: Doug Anderson diand...@chromium.org
Tested-by: Doug Anderson diand...@chromium.org
---
 .../devicetree/bindings/spi/spi-samsung.txt|  8 +--
 drivers/spi/spi-s3c64xx.c  | 66 ++
 2 files changed, 6 insertions(+), 68 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/spi-samsung.txt 
b/Documentation/devicetree/bindings/spi/spi-samsung.txt
index a15ffed..86aa061 100644
--- a/Documentation/devicetree/bindings/spi/spi-samsung.txt
+++ b/Documentation/devicetree/bindings/spi/spi-samsung.txt
@@ -31,9 +31,6 @@ Required Board Specific Properties:
 
 - #address-cells: should be 1.
 - #size-cells: should be 0.
-- gpios: The gpio specifier for clock, mosi and miso interface lines (in the
-  order specified). The format of the gpio specifier depends on the gpio
-  controller.
 
 Optional Board Specific Properties:
 
@@ -86,9 +83,8 @@ Example:
spi_0: spi@12d2 {
#address-cells = 1;
#size-cells = 0;
-   gpios = gpa2 4 2 3 0,
-   gpa2 6 2 3 0,
-   gpa2 7 2 3 0;
+   pinctrl-names = default;
+   pinctrl-0 = spi0_bus;
 
w25q80bw@0 {
#address-cells = 1;
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 4989aeb..4ab992b 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -1148,41 +1148,6 @@ static void s3c64xx_spi_hwinit(struct 
s3c64xx_spi_driver_data *sdd, int channel)
 }
 
 #ifdef CONFIG_OF
-static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd)
-{
-   struct device *dev = sdd-pdev-dev;
-   int idx, gpio, ret;
-
-   /* find gpios for mosi, miso and clock lines */
-   for (idx = 0; idx  3; idx++) {
-   gpio = of_get_gpio(dev-of_node, idx);
-   if (!gpio_is_valid(gpio)) {
-   dev_err(dev, invalid gpio[%d]: %d\n, idx, gpio);
-   goto free_gpio;
-   }
-   sdd-gpios[idx] = gpio;
-   ret = gpio_request(gpio, spi-bus);
-   if (ret) {
-   dev_err(dev, gpio [%d] request failed: %d\n,
-   gpio, ret);
-   goto free_gpio;
-   }
-   }
-   return 0;
-
-free_gpio:
-   while (--idx = 0)
-   gpio_free(sdd-gpios[idx]);
-   return -EINVAL;
-}
-
-static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd)
-{
-   unsigned int idx;
-   for (idx = 0; idx  3; idx++)
-   gpio_free(sdd-gpios[idx]);
-}
-
 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
 {
struct s3c64xx_spi_info *sci;
@@ -1215,15 +1180,6 @@ static struct s3c64xx_spi_info 
*s3c64xx_spi_parse_dt(struct device *dev)
 {
return dev-platform_data;
 }
-
-static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd)
-{
-   return -EINVAL;
-}
-
-static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd)
-{
-}
 #endif
 
 static const struct of_device_id s3c64xx_spi_dt_match[];
@@ -1344,10 +1300,7 @@ static int s3c64xx_spi_probe(struct platform_device 
*pdev)
goto err0;
}
 
-   if (!sci-cfg_gpio  pdev-dev.of_node) {
-   if (s3c64xx_spi_parse_dt_gpio(sdd))
-   return -EBUSY;
-   } else if (sci-cfg_gpio == NULL || sci-cfg_gpio()) {
+   if (sci-cfg_gpio  sci-cfg_gpio()) {
dev_err(pdev-dev, Unable to config gpio\n);
ret = -EBUSY;
goto err0;
@@ -1358,13 +1311,13 @@ static int s3c64xx_spi_probe(struct platform_device 
*pdev)
if (IS_ERR(sdd-clk)) {
dev_err(pdev-dev, Unable to acquire clock 'spi'\n);
ret = PTR_ERR(sdd-clk);
-   goto err1;
+   goto err0;
}
 
if (clk_prepare_enable(sdd-clk)) {
dev_err(pdev-dev, Couldn't enable clock 'spi'\n);
ret = -EBUSY;
-   goto err1;
+   goto err0;
}
 
sprintf(clk_name, spi_busclk%d, sci-src_clk_nr);
@@ -1421,9 +1374,6 @@ err3:
clk_disable_unprepare(sdd-src_clk);
 err2:
clk_disable_unprepare(sdd-clk);
-err1:
-   if (!sdd-cntrlr_info-cfg_gpio  pdev-dev.of_node)
-   s3c64xx_spi_dt_gpio_free(sdd);
 err0:
platform_set_drvdata(pdev, NULL);
spi_master_put(master);
@@ -1446,9 +1396,6 @@ static int s3c64xx_spi_remove(struct platform_device 
*pdev)