Re: [PATCH v3 4/6] clk: samsung: Add set_rate() clk_ops for PLL36xx
Hi Tomasz,
On Sat, Jun 8, 2013 at 5:47 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
On Friday 31 of May 2013 18:01:34 Vikas Sajjan wrote:
This patch adds set_rate and round_rate clk_ops for PLL36xx
Reviewed-by: Doug Anderson diand...@chromium.org
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
---
drivers/clk/samsung/clk-pll.c | 59
+ 1 file changed, 59
insertions(+)
diff --git a/drivers/clk/samsung/clk-pll.c
b/drivers/clk/samsung/clk-pll.c index 9591560..7143ed89 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -210,6 +210,9 @@ struct clk * __init
samsung_clk_register_pll35xx(const char *name, #define
PLL36XX_CON0_OFFSET (0x100)
#define PLL36XX_CON1_OFFSET (0x104)
+/* Maximum lock time can be 3000 * PDIV cycles */
+#define PLL36XX_LOCK_FACTOR (3000)
+
#define PLL36XX_KDIV_MASK(0x)
#define PLL36XX_MDIV_MASK(0x1FF)
#define PLL36XX_PDIV_MASK(0x3F)
@@ -217,6 +220,8 @@ struct clk * __init
samsung_clk_register_pll35xx(const char *name, #define
PLL36XX_MDIV_SHIFT(16)
#define PLL36XX_PDIV_SHIFT (8)
#define PLL36XX_SDIV_SHIFT (0)
+#define PLL36XX_KDIV_SHIFT (0)
+#define PLL36XX_LOCK_STAT_SHIFT (29)
static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
@@ -239,8 +244,57 @@ static unsigned long
samsung_pll36xx_recalc_rate(struct clk_hw *hw, return (unsigned
long)fvco;
}
+static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long
drate, + unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 tmp, pll_con0, pll_con1;
+ const struct samsung_pll_rate_table *rate;
+
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err(%s: Invalid rate : %lu for pll clk %s\n,
__func__,
+ drate, __clk_get_name(hw-clk));
+ return -EINVAL;
+ }
+
+ pll_con0 = pll_readl(pll, PLL36XX_CON0_OFFSET);
+ pll_con1 = pll_readl(pll, PLL36XX_CON1_OFFSET);
Hmm, PLL35xx has a fast path when only the S divisor changes. I'm not sure
about any technical differences between these two PLLs (other than having
the extra K factor and some more tunnables), but maybe it is possible for
this one as well?
Sure, will check and respin once tested.
Yadwinder will respin the next version of this patch series , as i am
off this week.
Otherwise looks fine.
Reviewed-by: Tomasz Figa t.f...@samsung.com
Thanks.
+
+ /* Set PLL lock time. */
+ pll_writel(pll, (rate-pdiv * PLL36XX_LOCK_FACTOR),
+ PLL36XX_LOCK_OFFSET);
+
+ /* Change PLL PMS values */
+ pll_con0 = ~((PLL36XX_MDIV_MASK PLL36XX_MDIV_SHIFT) |
+ (PLL36XX_PDIV_MASK PLL36XX_PDIV_SHIFT) |
+ (PLL36XX_SDIV_MASK PLL36XX_SDIV_SHIFT));
+ pll_con0 |= (rate-mdiv PLL36XX_MDIV_SHIFT) |
+ (rate-pdiv PLL36XX_PDIV_SHIFT) |
+ (rate-sdiv PLL36XX_SDIV_SHIFT);
+ pll_writel(pll, pll_con0, PLL36XX_CON0_OFFSET);
+
+ pll_con1 = ~(PLL36XX_KDIV_MASK PLL36XX_KDIV_SHIFT);
+ pll_con1 |= rate-kdiv PLL36XX_KDIV_SHIFT;
+ pll_writel(pll, pll_con1, PLL36XX_CON1_OFFSET);
+
+ /* wait_lock_time */
+ do {
+ cpu_relax();
+ tmp = pll_readl(pll, PLL36XX_CON0_OFFSET);
+ } while (!(tmp (1 PLL36XX_LOCK_STAT_SHIFT)));
+
+ return 0;
+}
+
static const struct clk_ops samsung_pll36xx_clk_ops = {
.recalc_rate = samsung_pll36xx_recalc_rate,
+ .set_rate = samsung_pll36xx_set_rate,
+ .round_rate = samsung_pll_round_rate,
+};
+
+static const struct clk_ops samsung_pll36xx_clk_min_ops = {
+ .recalc_rate = samsung_pll36xx_recalc_rate,
};
struct clk * __init samsung_clk_register_pll36xx(const char *name,
@@ -264,6 +318,11 @@ struct clk * __init
samsung_clk_register_pll36xx(const char *name, init.parent_names =
pname;
init.num_parents = 1;
+ if (rate_table rate_count)
+ init.ops = samsung_pll36xx_clk_ops;
+ else
+ init.ops = samsung_pll36xx_clk_min_ops;
+
pll-hw.init = init;
pll-base = base;
pll-rate_table = rate_table;
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Re: [PATCH 2/7] clk: samsung: Add clock driver for S3C64xx SoCs
Hi Mike,
On Tuesday 11 of June 2013 19:54:51 Mike Turquette wrote:
Quoting Tomasz Figa (2013-06-05 16:57:26)
This patch adds new, Common Clock Framework-based clock driver for
Samsung S3C64xx SoCs. The driver is just added, without actually
letting the platforms use it yet, since this requires more
intermediate steps.
It seems like there is an awful lot of clock data here that exists
alongside the stuff in DT. Is this how you plan to keep things going
forward or is this conversion just an intermediate step?
Current S3C64xx support contains a lot of boards, for which I don't see
any chance for DT conversion in any time soon, so the driver must cover
both DT and non-DT cases. (Not even saying that DT support for S3C64xx is
not yet submitted, as I want to get all the dependencies merged, or at
least acked, first.)
Also, personally, I don't see anything wrong with having those clocks
defined in the driver. The binding specifies the exact mapping between
clock IDs inside the clock provider and hardware clocks and not all clocks
need to be exported (most of muxes and divs don't need to), so I find it
more reasonable to define them in the driver instead.
Another thing is that it's unlikely for any new SoC from S3C64xx series to
show up, so basically the clock list is fixed.
Best regards,
Tomasz
Regards,
Mike
Signed-off-by: Tomasz Figa tomasz.f...@gmail.com
---
.../bindings/clock/samsung,s3c64xx-clock.txt | 48 ++
drivers/clk/samsung/Makefile | 3 +
drivers/clk/samsung/clk-s3c64xx.c | 503
+
include/dt-bindings/clock/samsung,s3c64xx-clock.h | 144 ++ 4
files changed, 698 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt
create mode 100644 drivers/clk/samsung/clk-s3c64xx.c
create mode 100644 include/dt-bindings/clock/samsung,s3c64xx-clock.h
diff --git
a/Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt
b/Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt
new file mode 100644
index 000..278ab6e
--- /dev/null
+++
b/Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt
@@ -0,0 +1,48 @@
+* Samsung S3C64xx Clock Controller
+
+The S3C64xx clock controller generates and supplies clock to various
controllers +within the SoC. The clock binding described here is
applicable to all SoCs in +the S3C64xx family.
+
+Required Properties:
+
+- comptible: should be one of the following.
+ - samsung,s3c6400-clock - controller compatible with S3C6400 SoC.
+ - samsung,s3c6410-clock - controller compatible with S3C6410 SoC.
+
+- reg: physical base address of the controller and length of memory
mapped + region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes can use this
identifier +to specify the clock which they consume. Some of the
clocks are available only +on a particular S3C64xx SoC and this is
specified where applicable. +
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/samsung,s3c64xx-clock.h header and can be used in
device +tree sources.
+
+Example: Clock controller node:
+
+ clocks: clock-controller@7e00f000 {
+ compatible = samsung,s3c6410-clock;
+ reg = 0x7e00f000 0x1000;
+ #clock-cells = 1;
+ };
+
+Example: UART controller node that consumes the clock generated by
the clock + controller (refer to the standard clock bindings for
information about + clocks and clock-names properties):
+
+ uart0: serial@7f005000 {
+ compatible = samsung,s3c6400-uart;
+ reg = 0x7f005000 0x100;
+ interrupt-parent = vic1;
+ interrupts = 5;
+ clock-names = uart, clk_uart_baud2,
+ clk_uart_baud3;
+ clocks = clocks PCLK_UART0, clocks
PCLK_UART0, + clocks
SCLK_UART;
+ status = disabled;
+ };
diff --git a/drivers/clk/samsung/Makefile
b/drivers/clk/samsung/Makefile index b7c232e..c023474 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -6,3 +6,6 @@ obj-$(CONFIG_COMMON_CLK)+= clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
+ifdef CONFIG_COMMON_CLK
+obj-$(CONFIG_ARCH_S3C64XX) += clk-s3c64xx.o
+endif
diff --git a/drivers/clk/samsung/clk-s3c64xx.c
b/drivers/clk/samsung/clk-s3c64xx.c new file mode 100644
index 000..253a972
--- /dev/null
+++ b/drivers/clk/samsung/clk-s3c64xx.c
@@ -0,0 +1,503 @@
+/*
+ * Copyright (c)
[PATCH V6 4/6] ARM: dts: add clock provider information for i2s controllers in Exynos5250
Add clock lookup information for i2s controllers on exynos5250 SoC.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
arch/arm/boot/dts/exynos5250.dtsi | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 84edf42..0aa9091 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -20,6 +20,8 @@
#include skeleton.dtsi
#include exynos5250-pinctrl.dtsi
+#include dt-bindings/clk/exynos-audss-clk.h
+
/ {
compatible = samsung,exynos5250;
interrupt-parent = gic;
@@ -457,6 +459,10 @@
pdma0 9
pdma0 8;
dma-names = tx, rx, tx-sec;
+ clocks = clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_SCLK_I2S;
+ clock-names = iis, i2s_opclk0, i2s_opclk1;
samsung,supports-6ch;
samsung,supports-rstclr;
samsung,supports-secdai;
@@ -471,6 +477,8 @@
dmas = pdma1 12
pdma1 11;
dma-names = tx, rx;
+ clocks = clock 307, clock 157;
+ clock-names = iis, i2s_opclk0;
pinctrl-names = default;
pinctrl-0 = i2s1_bus;
};
@@ -481,6 +489,8 @@
dmas = pdma0 12
pdma0 11;
dma-names = tx, rx;
+ clocks = clock 308, clock 158;
+ clock-names = iis, i2s_opclk0;
pinctrl-names = default;
pinctrl-0 = i2s2_bus;
};
--
1.7.4.4
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[PATCH V6 0/6] clk: Samsung: audss: Register audio subsytem clocks using common clk framework
Samsung S5PV210 and Exynos SoC has a separate subsystem for audio. This subsystem has a internal clock controller which controls i2s0 and pcm0 clocks. This patch series adds the Samsung audio subsytem clock to the common clock framework and provides the I2S controllers clock information in the dtsi file. This patch series is made based on Kukjin Kim for-next branch Changes since V5: - Added i2s_opclk0 entry for i2s1 and i2s2 nodes - Added Acked-by: Mike Turquette mturque...@linaro.org - Added Reviewed-by: Doug Anderson diand...@chromium.org Changes since V4: - Reworked on the nits given by Doug. - Removed mout_audss and mout_i2s from i2s nodes as we are not getting these clocks in the i2s driver. - Modified the I2S binding documentation for clocks and pinmux. Changes since V3: - Replaced samsung with exynos in the macro prefixes and function names as this driver supports mainly exynos and s5p family. - Added Reviewed-by:Sylwester Nawrocki s.nawro...@samsung.com Changes since V2: - Removed s5pv210 compatible name from driver as it is not yet supported which is different from Exynos series audio subsystem clock conroller. - Removed clkdev lookup support and added alias names in the i2s0 controller node. Changes since V1: - Reworked on all review comments by Sylwester Nawrocki - Added a header file for all clock indexes as requested by Sylwester - Added different compatible names for s5pv210, exynos4 and exynos5 - Registered the pcm clocks with common clock framework Padmavathi Venna (6): ARM: samsung: use #include for all device trees clk: samsung: register audio subsystem clocks using common clock framework ARM: dts: add Exynos audio subsystem clock controller node ARM: dts: add clock provider information for i2s controllers in Exynos5250 ARM: dts: Update Samsung I2S documentation clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2 .../devicetree/bindings/clock/clk-exynos-audss.txt | 64 ++ .../devicetree/bindings/sound/samsung-i2s.txt | 46 +++ arch/arm/boot/dts/exynos4.dtsi |2 +- arch/arm/boot/dts/exynos4210-origen.dts|2 +- arch/arm/boot/dts/exynos4210-smdkv310.dts |2 +- arch/arm/boot/dts/exynos4210-trats.dts |2 +- arch/arm/boot/dts/exynos4210-universal_c210.dts|2 +- arch/arm/boot/dts/exynos4210.dtsi |4 +- arch/arm/boot/dts/exynos4212.dtsi |2 +- arch/arm/boot/dts/exynos4412-odroidx.dts |2 +- arch/arm/boot/dts/exynos4412-origen.dts|2 +- arch/arm/boot/dts/exynos4412-smdk4412.dts |2 +- arch/arm/boot/dts/exynos4412.dtsi |2 +- arch/arm/boot/dts/exynos4x12.dtsi |4 +- arch/arm/boot/dts/exynos5250-arndale.dts |2 +- arch/arm/boot/dts/exynos5250-smdk5250.dts |2 +- arch/arm/boot/dts/exynos5250-snow.dts |4 +- arch/arm/boot/dts/exynos5250.dtsi | 20 +++- arch/arm/boot/dts/exynos5440-sd5v1.dts |2 +- arch/arm/boot/dts/exynos5440-ssdk5440.dts |2 +- arch/arm/boot/dts/exynos5440.dtsi |2 +- arch/arm/boot/dts/s3c2416-smdk2416.dts |2 +- arch/arm/boot/dts/s3c2416.dtsi |4 +- arch/arm/boot/dts/s3c24xx.dtsi |2 +- drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos-audss.c | 133 drivers/clk/samsung/clk-exynos5250.c |5 +- include/dt-bindings/clk/exynos-audss-clk.h | 25 28 files changed, 288 insertions(+), 56 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/clk-exynos-audss.txt create mode 100644 drivers/clk/samsung/clk-exynos-audss.c create mode 100644 include/dt-bindings/clk/exynos-audss-clk.h -- 1.7.4.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V6 6/6] clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2
This patch adds enum entries for div_i2s1 and div_i2s2 which are
required for i2s1 and i2s2 controllers.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
drivers/clk/samsung/clk-exynos5250.c |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index 5c97e75..7c68850 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -87,6 +87,7 @@ enum exynos5250_clks {
sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
+ div_i2s1, div_i2s2,
/* gate clocks */
gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
@@ -291,8 +292,8 @@ struct samsung_div_clock exynos5250_div_clks[] __initdata =
{
DIV(none, div_pcm1, sclk_audio1, DIV_PERIC4, 4, 8),
DIV(none, div_audio2, mout_audio2, DIV_PERIC4, 16, 4),
DIV(none, div_pcm2, sclk_audio2, DIV_PERIC4, 20, 8),
- DIV(none, div_i2s1, sclk_audio1, DIV_PERIC5, 0, 6),
- DIV(none, div_i2s2, sclk_audio2, DIV_PERIC5, 8, 6),
+ DIV(div_i2s1, div_i2s1, sclk_audio1, DIV_PERIC5, 0, 6),
+ DIV(div_i2s2, div_i2s2, sclk_audio2, DIV_PERIC5, 8, 6),
DIV(sclk_pixel, div_hdmi_pixel, sclk_vpll, DIV_DISP1_0, 28, 4),
DIV_A(none, armclk, div_arm, DIV_CPU0, 28, 3, armclk),
DIV_F(none, div_mipi1_pre, div_mipi1,
--
1.7.4.4
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[PATCH V6 1/6] ARM: samsung: use #include for all device trees
Replace /include/ (dtc) with #include (C pre-processor) for all
Samsung DT files
Signed-off-by: Padmavathi Venna padm...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
Reviewed-by: Doug Anderson diand...@chromium.org
---
arch/arm/boot/dts/exynos4.dtsi |2 +-
arch/arm/boot/dts/exynos4210-origen.dts |2 +-
arch/arm/boot/dts/exynos4210-smdkv310.dts |2 +-
arch/arm/boot/dts/exynos4210-trats.dts |2 +-
arch/arm/boot/dts/exynos4210-universal_c210.dts |2 +-
arch/arm/boot/dts/exynos4210.dtsi |4 ++--
arch/arm/boot/dts/exynos4212.dtsi |2 +-
arch/arm/boot/dts/exynos4412-odroidx.dts|2 +-
arch/arm/boot/dts/exynos4412-origen.dts |2 +-
arch/arm/boot/dts/exynos4412-smdk4412.dts |2 +-
arch/arm/boot/dts/exynos4412.dtsi |2 +-
arch/arm/boot/dts/exynos4x12.dtsi |4 ++--
arch/arm/boot/dts/exynos5250-arndale.dts|2 +-
arch/arm/boot/dts/exynos5250-smdk5250.dts |2 +-
arch/arm/boot/dts/exynos5250-snow.dts |4 ++--
arch/arm/boot/dts/exynos5250.dtsi |4 ++--
arch/arm/boot/dts/exynos5440-sd5v1.dts |2 +-
arch/arm/boot/dts/exynos5440-ssdk5440.dts |2 +-
arch/arm/boot/dts/exynos5440.dtsi |2 +-
arch/arm/boot/dts/s3c2416-smdk2416.dts |2 +-
arch/arm/boot/dts/s3c2416.dtsi |4 ++--
arch/arm/boot/dts/s3c24xx.dtsi |2 +-
22 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index bed40ee..3f94fe8 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -19,7 +19,7 @@
* published by the Free Software Foundation.
*/
-/include/ skeleton.dtsi
+#include skeleton.dtsi
/ {
interrupt-parent = gic;
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index bcf8079..5f851d7 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -15,7 +15,7 @@
*/
/dts-v1/;
-/include/ exynos4210.dtsi
+#include exynos4210.dtsi
/ {
model = Insignal Origen evaluation board based on Exynos4210;
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts
b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 91332b7..9c01b71 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -15,7 +15,7 @@
*/
/dts-v1/;
-/include/ exynos4210.dtsi
+#include exynos4210.dtsi
/ {
model = Samsung smdkv310 evaluation board based on Exynos4210;
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts
b/arch/arm/boot/dts/exynos4210-trats.dts
index 9a14484..94eebff 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -13,7 +13,7 @@
*/
/dts-v1/;
-/include/ exynos4210.dtsi
+#include exynos4210.dtsi
/ {
model = Samsung Trats based on Exynos4210;
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts
b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index 345cdb5..889cdad 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -13,7 +13,7 @@
*/
/dts-v1/;
-/include/ exynos4210.dtsi
+#include exynos4210.dtsi
/ {
model = Samsung Universal C210 based on Exynos4210 rev0;
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index d4f8067..b7f358a 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -19,8 +19,8 @@
* published by the Free Software Foundation.
*/
-/include/ exynos4.dtsi
-/include/ exynos4210-pinctrl.dtsi
+#include exynos4.dtsi
+#include exynos4210-pinctrl.dtsi
/ {
compatible = samsung,exynos4210;
diff --git a/arch/arm/boot/dts/exynos4212.dtsi
b/arch/arm/boot/dts/exynos4212.dtsi
index c0f60f4..6f34d7f 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -17,7 +17,7 @@
* published by the Free Software Foundation.
*/
-/include/ exynos4x12.dtsi
+#include exynos4x12.dtsi
/ {
compatible = samsung,exynos4212;
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts
b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 867d945..46c678e 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -12,7 +12,7 @@
*/
/dts-v1/;
-/include/ exynos4412.dtsi
+#include exynos4412.dtsi
/ {
model = Hardkernel ODROID-X board based on Exynos4412;
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts
b/arch/arm/boot/dts/exynos4412-origen.dts
index ca73c42..7993641 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -13,7 +13,7 @@
*/
/dts-v1/;
-/include/ exynos4412.dtsi
+#include exynos4412.dtsi
/ {
model =
[PATCH V6 2/6] clk: samsung: register audio subsystem clocks using common clock framework
Audio subsystem is introduced in s5pv210 and exynos platforms.
This has seperate clock controller which can control i2s0 and
pcm0 clocks. This patch registers the audio subsystem clocks
with the common clock framework on Exynos family.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
Reviewed-by: Doug Anderson diand...@chromium.org
Acked-by: Mike Turquette mturque...@linaro.org
---
.../devicetree/bindings/clock/clk-exynos-audss.txt | 64 ++
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-exynos-audss.c | 133
include/dt-bindings/clk/exynos-audss-clk.h | 25
4 files changed, 223 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
create mode 100644 drivers/clk/samsung/clk-exynos-audss.c
create mode 100644 include/dt-bindings/clk/exynos-audss-clk.h
diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
new file mode 100644
index 000..a120180
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -0,0 +1,64 @@
+* Samsung Audio Subsystem Clock Controller
+
+The Samsung Audio Subsystem clock controller generates and supplies clocks
+to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
+binding described here is applicable to all SoC's in Exynos family.
+
+Required Properties:
+
+- compatible: should be one of the following:
+ - samsung,exynos4210-audss-clock - controller compatible with all Exynos4
SoCs.
+ - samsung,exynos5250-audss-clock - controller compatible with all Exynos5
SoCs.
+
+- reg: physical base address and length of the controller's register set.
+
+- #clock-cells: should be 1.
+
+The following is the list of clocks generated by the controller. Each clock is
+assigned an identifier and client nodes use this identifier to specify the
+clock which they consume. Some of the clocks are available only on a particular
+Exynos4 SoC and this is specified where applicable.
+
+Provided clocks:
+
+Clock ID SoC (if specific)
+---
+
+mout_audss 0
+mout_i2s1
+dout_srp2
+dout_aud_bus3
+dout_i2s4
+srp_clk 5
+i2s_bus 6
+sclk_i2s7
+pcm_bus 8
+sclk_pcm9
+
+Example 1: An example of a clock controller node is listed below.
+
+clock_audss: audss-clock-controller@381 {
+ compatible = samsung,exynos5250-audss-clock;
+ reg = 0x0381 0x0C;
+ #clock-cells = 1;
+};
+
+Example 2: I2S controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+i2s0: i2s@0383 {
+ compatible = samsung,i2s-v5;
+ reg = 0x0383 0x100;
+ dmas = pdma0 10
+ pdma0 9
+ pdma0 8;
+ dma-names = tx, rx, tx-sec;
+ clocks = clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_SCLK_I2S,
+ clock_audss EXYNOS_MOUT_AUDSS,
+ clock_audss EXYNOS_MOUT_I2S;
+ clock-names = iis, i2s_opclk0, i2s_opclk1,
+ mout_audss, mout_i2s;
+};
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index b7c232e..1876810 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_COMMON_CLK)+= clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
+obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
new file mode 100644
index 000..9b1bbd5
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Padmavathi Venna padm...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Audio Subsystem Clock Controller.
+*/
+
+#include linux/clkdev.h
+#include linux/io.h
+#include linux/clk-provider.h
+#include linux/of_address.h
+#include linux/syscore_ops.h
+
+#include dt-bindings/clk/exynos-audss-clk.h
+
+static DEFINE_SPINLOCK(lock);
+static struct clk **clk_table;
+static void __iomem *reg_base;
+static struct clk_onecell_data clk_data;
+
+#define ASS_CLK_SRC 0x0
+#define ASS_CLK_DIV 0x4
+#define ASS_CLK_GATE 0x8
+
+static unsigned long reg_save[][2] = {
+ {ASS_CLK_SRC, 0},
+ {ASS_CLK_DIV, 0},
+ {ASS_CLK_GATE, 0},
[PATCH V6 3/6] ARM: dts: add Exynos audio subsystem clock controller node
Audio subsystem introduced in s5pv210 and exynos platforms
which has a internal clock controller. This patch adds a node
for the same on exynos5250.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
Reviewed-by: Doug Anderson diand...@chromium.org
---
arch/arm/boot/dts/exynos5250.dtsi |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 5cfc5b7..84edf42 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -72,6 +72,12 @@
#clock-cells = 1;
};
+ clock_audss: audss-clock-controller@381 {
+ compatible = samsung,exynos5250-audss-clock;
+ reg = 0x0381 0x0C;
+ #clock-cells = 1;
+ };
+
gic:interrupt-controller@10481000 {
compatible = arm,cortex-a15-gic, arm,cortex-a9-gic;
#interrupt-cells = 3;
--
1.7.4.4
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[PATCH V6 5/6] ARM: dts: Update Samsung I2S documentation
This patch updates the samsung i2s documentation for pinmux and
clock entries.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
.../devicetree/bindings/sound/samsung-i2s.txt | 46 ---
1 files changed, 19 insertions(+), 27 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
index 3070046..025e66b 100644
--- a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
@@ -8,6 +8,16 @@ Required SoC Specific Properties:
- dmas: list of DMA controller phandle and DMA request line ordered pairs.
- dma-names: identifier string for each DMA request line in the dmas property.
These strings correspond 1:1 with the ordered pairs in dmas.
+- clocks: Handle to iis clock and RCLK source clk.
+- clock-names:
+ i2s0 uses some base clks from CMU and some are from audio subsystem internal
+ clock controller. The clock names for i2s0 should be iis, i2s_opclk0 and
+ i2s_opclk1 as shown in the example below.
+ i2s1 and i2s2 uses clocks from CMU. The clock names for i2s1 and i2s2 should
+ be iis and i2s_opclk0.
+ iis is the i2s bus clock and i2s_opclk0, i2s_opclk1 are sources of the root
+ clk. i2s0 has internal mux to select the source of root clk and i2s1 and i2s2
+ doesn't have any such mux.
Optional SoC Specific Properties:
@@ -20,44 +30,26 @@ Optional SoC Specific Properties:
then this flag is enabled.
- samsung,idma-addr: Internal DMA register base address of the audio
sub system(used in secondary sound source).
-
-Required Board Specific Properties:
-
-- gpios: The gpio specifier for data out,data in, LRCLK, CDCLK and SCLK
- interface lines. The format of the gpio specifier depends on the gpio
- controller.
- The syntax of samsung gpio specifier is
- [phandle of the gpio controller node]
-[pin number within the gpio controller]
-[mux function]
-[flags and pull up/down]
-[drive strength]
+- pinctrl-0: Should specify pin control groups used for this controller.
+- pinctrl-names: Should contain only one value - default.
Example:
-- SoC Specific Portion:
-
-i2s@0383 {
+i2s0: i2s@0383 {
compatible = samsung,i2s-v5;
reg = 0x0383 0x100;
dmas = pdma0 10
pdma0 9
pdma0 8;
dma-names = tx, rx, tx-sec;
+ clocks = clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_I2S_BUS,
+ clock_audss EXYNOS_SCLK_I2S;
+ clock-names = iis, i2s_opclk0, i2s_opclk1;
samsung,supports-6ch;
samsung,supports-rstclr;
samsung,supports-secdai;
samsung,idma-addr = 0x0300;
-};
-
-- Board Specific Portion:
-
-i2s@0383 {
- gpios = gpz 0 2 0 0, /* I2S_0_SCLK */
- gpz 1 2 0 0, /* I2S_0_CDCLK */
- gpz 2 2 0 0, /* I2S_0_LRCK */
- gpz 3 2 0 0, /* I2S_0_SDI */
- gpz 4 2 0 0, /* I2S_0_SDO[1] */
- gpz 5 2 0 0, /* I2S_0_SDO[2] */
- gpz 6 2 0 0; /* I2S_0_SDO[3] */
+ pinctrl-names = default;
+ pinctrl-0 = i2s0_bus;
};
--
1.7.4.4
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[PATCH RESEND V2] ARM: dts: Correct the base address of pinctrl_3 on Exynos5250
This patch corrects the base address of pinctrl_3 on Exynos5250
platform.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
Changes since V1:
- Added platform name in the subject line.
arch/arm/boot/dts/exynos5250-pinctrl.dtsi |2 +-
arch/arm/boot/dts/exynos5250.dtsi |4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
index d1650fb..ded558b 100644
--- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
@@ -763,7 +763,7 @@
};
};
- pinctrl@0368 {
+ pinctrl@0386 {
gpz: gpz {
gpio-controller;
#gpio-cells = 2;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 7154e3d..e9bfd13 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -169,9 +169,9 @@
interrupts = 0 50 0;
};
- pinctrl_3: pinctrl@0368 {
+ pinctrl_3: pinctrl@0386 {
compatible = samsung,exynos5250-pinctrl;
- reg = 0x0368000 0x1000;
+ reg = 0x0386 0x1000;
interrupts = 0 47 0;
};
--
1.7.4.4
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[PATCH RESEND V2] ARM: dts: wm8994: Add wm8994 regulator support on smdk5250.
This patch adds the required regulator supplies and properties
for wm8994 codec on smdk5250 board.
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
Changes since V1:
- Clubbed the same supply regulators as suggested by Mark.
arch/arm/boot/dts/exynos5250-smdk5250.dts | 37 +++-
1 files changed, 35 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index f2a025e..dc2ec25 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -37,6 +37,30 @@
};
};
+ vdd:fixed-regulator@0 {
+ compatible = regulator-fixed;
+ regulator-name = vdd-supply;
+ regulator-min-microvolt = 180;
+ regulator-max-microvolt = 180;
+ regulator-always-on;
+ };
+
+ dbvdd:fixed-regulator@1 {
+ compatible = regulator-fixed;
+ regulator-name = dbvdd-supply;
+ regulator-min-microvolt = 330;
+ regulator-max-microvolt = 330;
+ regulator-always-on;
+ };
+
+ spkvdd:fixed-regulator@2 {
+ compatible = regulator-fixed;
+ regulator-name = spkvdd-supply;
+ regulator-min-microvolt = 500;
+ regulator-max-microvolt = 500;
+ regulator-always-on;
+ };
+
i2c@12C7 {
samsung,i2c-sda-delay = 100;
samsung,i2c-max-bus-freq = 2;
@@ -47,8 +71,17 @@
};
wm8994: wm8994@1a {
-compatible = wlf,wm8994;
-reg = 0x1a;
+ compatible = wlf,wm8994;
+ reg = 0x1a;
+
+ gpio-controller;
+ #gpio-cells = 2;
+
+ AVDD2-supply = vdd;
+ CPVDD-supply = vdd;
+ DBVDD-supply = dbvdd;
+ SPKVDD1-supply = spkvdd;
+ SPKVDD2-supply = spkvdd;
};
};
--
1.7.4.4
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Re: About LPAE supporting on EXYNOS5440
On Wednesday 12 June 2013, Subash Patel wrote: I would definitely leave on exynos5440 support in defconfig. It's not a lot of extra code, and if you have a system with less than 4GB memory, you really don't want to enable LPAE because of the overhead. Even if we have = 4GB memory, and the system designers have placed the memory banks in addresses 2^32 bytes, then we need LPAE support. I think we may have such systems in future. So memory capacity is not the only parameter to judge if we need to enable LPAE or not. Yes, but that wasn't the point. You can always build systems with exynos5440 that don't need LPAE, so we should not assume that it is not a reasonable configuration. I would certainly advise system designers to put all the RAM and I/O into normally addressable locations if possible to avoid the need for LPAE, but of course that isn't always possible. We should probably have someone measure the performance impact of LPAE as well. If it's less than a few percent, we might not care all that much. Arnd -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V4 0/3] PCIe support for Samsung Exynos5440 SoC
Hi, This series of patches introduces PCIe support for Samsung Exynos5440, and is based on the latest 'linux-next' tree (20130607). These patches was tested with Intel e1000e LAN card on Exynos5440. This PATCH v4 follows: * PATCH v3, sent on June, 6th 2013 * PATCH v2, sent on March, 23rd 2013 * PATCH v1, sent on March, 4th 2013 Changes between v3 and v4: * Added support for multi domains as reviewed by Jason Gunthorpe, and Arnd Bergmann. * Fixed both MEM space and I/O space in DT. * Removed redundant physical addresses from struct pcie_port, added devm_ioremap_resource() to make add_pcie_port() simpler. * Added clock names and clock enable/disable. Changes between v2 and v3: * Rebased on the top of 3.10-rc4 * Updated names of PCIe PHY registers Changes between v1 and v2: * Moved Exynos PCIe driver from arch/arm to drivers/pci/host. * Added DT properties of PCI DT standard. Thank you. Best regards, Jingoo Han Jingoo Han (3): pci: Add PCIe driver for Samsung Exynos ARM: EXYNOS: Enable PCIe support for Exynos5440 ARM: dts: Add pcie controller node for Samsung EXYNOS5440 SoC arch/arm/boot/dts/exynos5440-ssdk5440.dts |8 ++ arch/arm/boot/dts/exynos5440.dtsi | 38 + arch/arm/Kconfig |1 + arch/arm/mach-exynos/Kconfig |2 ++ .../devicetree/bindings/pci/exynos-pcie.txt| 71 ++ drivers/pci/host/Kconfig |5 + drivers/pci/host/Makefile |1 + drivers/pci/host/pci-exynos.c | 1074 8 files changed, 1200 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/exynos-pcie.txt create mode 100644 drivers/pci/host/pci-exynos.c -- 1.7.10.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V4 2/3] ARM: EXYNOS: Enable PCIe support for Exynos5440
Enable PCIe support for Exynos5440 which has two PCIe controllers. Signed-off-by: Jingoo Han jg1@samsung.com --- Tested on Exynos5440. Changes since v3: - Selected PCI_DOMAINS arch/arm/Kconfig |1 + arch/arm/mach-exynos/Kconfig |2 ++ 2 files changed, 3 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 42d6ea2..53b3b2d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1395,6 +1395,7 @@ config PCI_HOST_ITE8152 select DMABOUNCE source drivers/pci/Kconfig +source drivers/pci/pcie/Kconfig source drivers/pcmcia/Kconfig diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 6aa228d..773b5ee 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -78,6 +78,8 @@ config SOC_EXYNOS5440 select ARCH_HAS_OPP select ARM_ARCH_TIMER select AUTO_ZRELADDR + select MIGHT_HAVE_PCI + select PCI_DOMAINS if PCI select PINCTRL select PINCTRL_EXYNOS5440 select PM_OPP -- 1.7.10.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V4 3/3] ARM: dts: Add pcie controller node for Samsung EXYNOS5440 SoC
Exynos5440 has two PCIe controllers which can be used as root complex
for PCIe interface.
Signed-off-by: Jingoo Han jg1@samsung.com
---
Tested on Exynos5440.
Changes since v3:
- Removed 'bus-range' property from DT
- Added 'interrupt-map-mask', 'interrupt-map' properties to DT
- Fixed the start address of MEM space in DT
- Increased the size of I/O space to 64kB in DT
- Added 'clocks', 'clock-names' properties to DT
arch/arm/boot/dts/exynos5440-ssdk5440.dts |8 ++
arch/arm/boot/dts/exynos5440.dtsi | 38 +
2 files changed, 46 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index d55042b..efe7d39 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -30,4 +30,12 @@
clock-frequency = 5000;
};
};
+
+ pcie0@4000 {
+ reset-gpio = 5;
+ };
+
+ pcie1@6000 {
+ reset-gpio = 22;
+ };
};
diff --git a/arch/arm/boot/dts/exynos5440.dtsi
b/arch/arm/boot/dts/exynos5440.dtsi
index f6b1c89..2c15f9d 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -216,4 +216,42 @@
clock-names = rtc;
status = disabled;
};
+
+ pcie0@0x29 {
+ compatible = samsung,exynos5440-pcie;
+ reg = 0x29 0x1000
+ 0x27 0x1000
+ 0x271000 0x40;
+ interrupts = 0 20 0, 0 21 0, 0 22 0;
+ clocks = clock 28, clock 27;
+ clock-names = pcie, pcie_bus;
+ #address-cells = 3;
+ #size-cells = 2;
+ device_type = pci;
+ ranges = 0x0800 0 0x4000 0x4000 0 0x0020 /*
configuration space */
+ 0x8100 0 0 0x4020 0 0x0001 /*
downstream I/O */
+ 0x8200 0 0x4021 0x4021 0 0x1000; /*
non-prefetchable memory */
+ #interrupt-cells = 1;
+ interrupt-map-mask = 0 0 0 0;
+ interrupt-map = 0x0 0 gic 53;
+ };
+
+ pcie1@2a {
+ compatible = samsung,exynos5440-pcie;
+ reg = 0x2a 0x1000
+ 0x272000 0x1000
+ 0x271040 0x40;
+ interrupts = 0 23 0, 0 24 0, 0 25 0;
+ clocks = clock 29, clock 27;
+ clock-names = pcie, pcie_bus;
+ #address-cells = 3;
+ #size-cells = 2;
+ device_type = pci;
+ ranges = 0x0800 0 0x6000 0x6000 0 0x0020 /*
configuration space */
+ 0x8100 0 0 0x6020 0 0x0001 /*
downstream I/O */
+ 0x8200 0 0x6021 0x6021 0 0x1000; /*
non-prefetchable memory */
+ #interrupt-cells = 1;
+ interrupt-map-mask = 0 0 0 0;
+ interrupt-map = 0x0 0 gic 56;
+ };
};
--
1.7.10.4
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Re: [PATCH V4 0/3] PCIe support for Samsung Exynos5440 SoC
On Wednesday, June 12, 2013 7:18 PM, Jingoo Han wrote: Hi, This series of patches introduces PCIe support for Samsung Exynos5440, and is based on the latest 'linux-next' tree (20130607). These patches was tested with Intel e1000e LAN card on Exynos5440. This PATCH v4 follows: * PATCH v3, sent on June, 6th 2013 * PATCH v2, sent on March, 23rd 2013 * PATCH v1, sent on March, 4th 2013 Changes between v3 and v4: * Added support for multi domains as reviewed by Jason Gunthorpe, and Arnd Bergmann. * Fixed both MEM space and I/O space in DT. * Removed redundant physical addresses from struct pcie_port, added devm_ioremap_resource() to make add_pcie_port() simpler. * Added clock names and clock enable/disable. Changes between v2 and v3: * Rebased on the top of 3.10-rc4 * Updated names of PCIe PHY registers Changes between v1 and v2: * Moved Exynos PCIe driver from arch/arm to drivers/pci/host. * Added DT properties of PCI DT standard. Thank you. Best regards, Jingoo Han Jingoo Han (3): pci: Add PCIe driver for Samsung Exynos ARM: EXYNOS: Enable PCIe support for Exynos5440 ARM: dts: Add pcie controller node for Samsung EXYNOS5440 SoC arch/arm/boot/dts/exynos5440-ssdk5440.dts |8 ++ arch/arm/boot/dts/exynos5440.dtsi | 38 + arch/arm/Kconfig |1 + arch/arm/mach-exynos/Kconfig |2 ++ .../devicetree/bindings/pci/exynos-pcie.txt| 71 ++ drivers/pci/host/Kconfig |5 + drivers/pci/host/Makefile |1 + drivers/pci/host/pci-exynos.c | 1074 8 files changed, 1200 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/exynos-pcie.txt create mode 100644 drivers/pci/host/pci-exynos.c Hi all, Here is the lspci -vv output. :00:00.0 PCI bridge: Samsung Electronics Co Ltd Device a549 (rev 01) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast TAbort- TAbort- MAbort- SERR- PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: -0fff Memory behind bridge: 4030-403f Prefetchable memory behind bridge: 4040-404f Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast TAbort- TAbort- MAbort- SERR- PERR- BridgeCtl: Parity+ SERR- NoISA- VGA- MAbort- Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Power Management version 3 Flags: PMEClk- DSI- D1+ D2- AuxCurrent=375mA PME(D0+,D1+,D2-,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: Data: Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00 DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s 64ns, L1 1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 5GT/s, Width x4, ASPM L0s L1, Latency L0 64ns, L1 2us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk- DLActive+ BWMgmt+ ABWMgmt- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID , PMEStatus- PMEPending- DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- Capabilities: [100 v2] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
Re: [PATCH V4 3/3] ARM: dts: Add pcie controller node for Samsung EXYNOS5440 SoC
Thanks for the update! A few comments again:
On Wednesday 12 June 2013 19:20:00 Jingoo Han wrote:
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index d55042b..efe7d39 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -30,4 +30,12 @@
clock-frequency = 5000;
};
};
+
+ pcie0@4000 {
+ reset-gpio = 5;
+ };
+
+ pcie1@6000 {
+ reset-gpio = 22;
+ };
};
As mentioned before, please use the gpio binding to pass gpio numbers.
diff --git a/arch/arm/boot/dts/exynos5440.dtsi
b/arch/arm/boot/dts/exynos5440.dtsi
index f6b1c89..2c15f9d 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -216,4 +216,42 @@
clock-names = rtc;
status = disabled;
};
+
+ pcie0@0x29 {
+ compatible = samsung,exynos5440-pcie;
+ reg = 0x29 0x1000
+ 0x27 0x1000
+ 0x271000 0x40;
+ interrupts = 0 20 0, 0 21 0, 0 22 0;
+ clocks = clock 28, clock 27;
+ clock-names = pcie, pcie_bus;
+ #address-cells = ;
+ #size-cells = 2;
+ device_type = pci;
+ ranges = 0x0800 0 0x4000 0x4000 0 0x0020
/* configuration space */
+ 0x8100 0 0 0x4020 0 0x0001
/* downstream I/O */
+ 0x8200 0 0x4021 0x4021 0 0x1000;
/* non-prefetchable memory */
I think you did not reply to my question regarding the size of the
memory space. Does it extend from 0x4021 to 0x5021,
or from 0x4021 to 0x5000. You probably meant the latter
but wrote the former. If not, please add a comment for clarification.
+ #interrupt-cells = 1;
+ interrupt-map-mask = 0 0 0 0;
+ interrupt-map = 0x0 0 gic 53;
+ };
So all PCI IntA interrupts are mapped to a single gic interrupt? That
sounds like a bottleneck when you have a lot of devices on the bus.
Do you have MSI support?
Arnd
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Re: [PATCH V4 1/3] pci: Add PCIe driver for Samsung Exynos
On Wednesday 12 June 2013 19:19:05 Jingoo Han wrote:
+
+struct pcie_port {
+ struct device *dev;
+ u8 controller;
+ u8 root_bus_nr;
+ void __iomem*dbi_base;
+ void __iomem*elbi_base;
+ void __iomem*phy_base;
+ void __iomem*purple_base;
+ phys_addr_t cfg0_base;
+ void __iomem*va_cfg0_base;
+ phys_addr_t cfg1_base;
+ void __iomem*va_cfg1_base;
+ phys_addr_t io_base;
+ phys_addr_t mem_base;
+ spinlock_t conf_lock;
+ struct resource cfg;
+ struct resource io;
+ struct resource mem;
+ struct pcie_port_info config;
+ struct clk *clk;
+ struct clk *bus_clk;
+ int irq;
+ int reset_gpio;
+};
This looks much better now.
+
+/* synopsis specific PCIE configuration registers*/
+#define PCIE_PORT_LINK_CONTROL 0x710
+#define PORT_LINK_MODE_MASK (0x3f 16)
+#define PORT_LINK_MODE_4_LANES (0x7 16)
Do you mean this is a Synopsys designware part? In that case it
should really not be called exynos-pcie but designware-pcie
and you should make sure that the driver makes no assumptions about
the platform. A lot of other platforms also use designware
parts and should be able to reuse this driver.
+static void exynos_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev)
+{
+ u32 val;
+ void __iomem *dbi_base = pp-dbi_base;
+
+ /* Program viewport 0 : OUTBOUND : CFG0 */
+ val = PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0;
+ writel_rc(pp, val, dbi_base + PCIE_ATU_VIEWPORT);
+ writel_rc(pp, (u32)pp-cfg0_base, dbi_base + PCIE_ATU_LOWER_BASE);
+ writel_rc(pp, 0, dbi_base + PCIE_ATU_UPPER_BASE);
+ writel_rc(pp, (u32)pp-cfg0_base + pp-config.cfg0_size - 1,
+ dbi_base + PCIE_ATU_LIMIT);
+ writel_rc(pp, busdev, dbi_base + PCIE_ATU_LOWER_TARGET);
+ writel_rc(pp, 0, dbi_base + PCIE_ATU_UPPER_TARGET);
+ writel_rc(pp, PCIE_ATU_TYPE_CFG0, dbi_base + PCIE_ATU_CR1);
+ val = PCIE_ATU_ENABLE;
+ writel_rc(pp, val, dbi_base + PCIE_ATU_CR2);
+}
I think you should not assume that the physical base address is a 32
bit value. The hardware clearly supports lower and upper halves
for the address window, so when resource_size_t is 64 bit, you should
set the upper half accordingly. Since the hardware is always 64 bit,
you can use a u64 type rather than resource_size_t to simplify the
code here.
+static void exynos_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
+{
+ u32 val;
+ void __iomem *dbi_base = pp-dbi_base;
+
+ /* Program viewport 0 : OUTBOUND : MEM */
+ val = PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0;
+ writel_rc(pp, val, dbi_base + PCIE_ATU_VIEWPORT);
+ writel_rc(pp, PCIE_ATU_TYPE_MEM, dbi_base + PCIE_ATU_CR1);
+ val = PCIE_ATU_ENABLE;
+ writel_rc(pp, val, dbi_base + PCIE_ATU_CR2);
+ writel_rc(pp, (u32)pp-mem_base, dbi_base + PCIE_ATU_LOWER_BASE);
+ writel_rc(pp, 0, dbi_base + PCIE_ATU_UPPER_BASE);
+ writel_rc(pp, (u32)(pp-mem_base + pp-config.mem_size - 1),
+ dbi_base + PCIE_ATU_LIMIT);
+ writel_rc(pp, (u32)pp-mem_base, dbi_base + PCIE_ATU_LOWER_TARGET);
+ writel_rc(pp, 0, dbi_base + PCIE_ATU_UPPER_TARGET);
+}
You probably should not assume that there is a 1:1 mapping between
bus addresses and host physical addresses, but rather read both
values from the DT individually. With the ranges defined as
0x8200 0 0x4021 0x4021 0 0x1000; /* non-prefetchable
memory */
the second and third cell should go into
PCIE_ATU_UPPER_TARGET/PCIE_ATU_LOWER_TARGET, while the translated address
(from the third cell) should go into PCIE_ATU_LOWER_BASE/PCIE_ATU_UPPER_BASE
The PCIE_ATU_LIMIT seems to correctly get translated from the last
cell.
+static void exynos_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
+{
+ u32 val;
+ void __iomem *dbi_base = pp-dbi_base;
+
+ /* Program viewport 1 : OUTBOUND : IO */
+ val = PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1;
+ writel_rc(pp, val, dbi_base + PCIE_ATU_VIEWPORT);
+ writel_rc(pp, PCIE_ATU_TYPE_IO, dbi_base + PCIE_ATU_CR1);
+ val = PCIE_ATU_ENABLE;
+ writel_rc(pp, val, dbi_base + PCIE_ATU_CR2);
+ writel_rc(pp, (u32)pp-io_base, dbi_base + PCIE_ATU_LOWER_BASE);
+ writel_rc(pp, 0, dbi_base + PCIE_ATU_UPPER_BASE);
+ writel_rc(pp, (u32)(pp-io_base + pp-config.io_size - 1),
+ dbi_base + PCIE_ATU_LIMIT);
+ writel_rc(pp, (u32)pp-io_base, dbi_base + PCIE_ATU_LOWER_TARGET);
+ writel_rc(pp, 0, dbi_base + PCIE_ATU_UPPER_TARGET);
+}
You don't actually map the I/O space anywhere
[PATCH V2 0/2] ARM: EXYNOS: cpuidle: fixes in exynos cpuidle/PM
This patch series contains a couple of fixes in cpuidle/PM due to 1) exynos5440 platform which does not support cpuidle C1 state. 2) Compilations error when generic PM options are enabled. This patch series depends on earlier posted patch http://www.spinics.net/lists/arm-kernel/msg248831.html Changes in V2: * Rebase against samsung maintainer's for next tree. Amit Daniel Kachhap (2): ARM: SAMSUNG: Add SAMSUNG_PM config option to select pm ARM: EXYNOS: cpuidle: Allow C1 state only in supported SOC's. arch/arm/mach-exynos/Makefile |2 +- arch/arm/mach-exynos/common.c |2 +- arch/arm/mach-exynos/common.h |1 - arch/arm/mach-exynos/cpuidle.c |5 - arch/arm/plat-samsung/Kconfig |7 +++ arch/arm/plat-samsung/Makefile |3 +-- arch/arm/plat-samsung/include/plat/pm.h |8 7 files changed, 18 insertions(+), 10 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH V2 1/2] ARM: SAMSUNG: Add SAMSUNG_PM config option to select pm
This patch enables the selection of samsung pm related stuffs
when SAMSUNG_PM config is enabled and not just when generic PM
config is enabled. Power management for s3c64XX and s3c24XX
is enabled by default and for other platform depends on S5P_PM.
This patch also fixes the following compilation error's when compiling
a platform like exynos5440 which does not select pm stuffs.
arch/arm/mach-exynos/built-in.o: In function `__virt_to_phys':
linux/arch/arm/include/asm/memory.h:175: undefined reference to `s3c_cpu_resume'
linux/arch/arm/include/asm/memory.h:175: undefined reference to `s3c_cpu_resume'
linux/arch/arm/include/asm/memory.h:175: undefined reference to `s3c_cpu_resume'
linux/arch/arm/include/asm/memory.h:175: undefined reference to `s3c_cpu_resume'
arch/arm/mach-exynos/built-in.o: In function `exynos5_init_irq':
linux/arch/arm/mach-exynos/common.c:492: undefined reference to `s3c_irq_wake'
linux/arch/arm/mach-exynos/common.c:492: undefined reference to `s3c_irq_wake'
arch/arm/mach-exynos/built-in.o: In function `exynos4_init_irq':
linux/arch/arm/mach-exynos/common.c:476: undefined reference to `s3c_irq_wake'
linux/arch/arm/mach-exynos/common.c:476: undefined reference to `s3c_irq_wake'
arch/arm/plat-samsung/built-in.o: In function `s3c_irqext_wake':
linux/arch/arm/plat-samsung/pm.c:144: undefined reference to
`s3c_irqwake_eintallow'
linux/arch/arm/plat-samsung/pm.c:144: undefined reference to
`s3c_irqwake_eintallow'
arch/arm/plat-samsung/built-in.o: In function `s3c_pm_enter':
linux/arch/arm/plat-samsung/pm.c:263: undefined reference to
`s3c_irqwake_intallow'
linux/arch/arm/plat-samsung/pm.c:263: undefined reference to
`s3c_irqwake_intallow'
linux/arch/arm/plat-samsung/pm.c:264: undefined reference to
`s3c_irqwake_eintallow'
linux/arch/arm/plat-samsung/pm.c:264: undefined reference to
`s3c_irqwake_eintallow'
linux/arch/arm/plat-samsung/pm.c:275: undefined reference to `s3c_pm_save_core'
linux/arch/arm/plat-samsung/pm.c:279: undefined reference to
`s3c_pm_configure_extint'
linux/arch/arm/plat-samsung/pm.c:310: undefined reference to
`s3c_pm_restore_core'
make: *** [vmlinux] Error 1
Signed-off-by: Amit Daniel Kachhap amit.dan...@samsung.com
---
arch/arm/mach-exynos/Makefile |2 +-
arch/arm/mach-exynos/common.c |2 +-
arch/arm/mach-exynos/common.h |1 -
arch/arm/mach-exynos/cpuidle.c |1 +
arch/arm/plat-samsung/Kconfig |7 +++
arch/arm/plat-samsung/Makefile |3 +--
arch/arm/plat-samsung/include/plat/pm.h |8
7 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 9811f87..3fa277a 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -14,7 +14,7 @@ obj- :=
obj-$(CONFIG_ARCH_EXYNOS) += common.o
-obj-$(CONFIG_PM) += pm.o
+obj-$(CONFIG_S5P_PM) += pm.o
obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 9834357..d2b4f54 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -799,7 +799,7 @@ static struct irq_chip exynos_irq_eint = {
.irq_mask_ack = exynos_irq_eint_maskack,
.irq_ack= exynos_irq_eint_ack,
.irq_set_type = exynos_irq_eint_set_type,
-#ifdef CONFIG_PM
+#ifdef CONFIG_S5P_PM
.irq_set_wake = s3c_irqext_wake,
#endif
};
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 11fc1e2..f2b2e23 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -98,6 +98,5 @@ struct exynos_pmu_conf {
};
extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
-extern void s3c_cpu_resume(void);
#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 4667907..2d071c6 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -25,6 +25,7 @@
#include mach/regs-pmu.h
#include plat/cpu.h
+#include plat/pm.h
#include common.h
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index f8ed2de..6c25aa6 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -31,6 +31,13 @@ config PLAT_S5P
help
Base platform code for Samsung's S5P series SoC.
+config SAMSUNG_PM
+ bool
+ depends on PM (PLAT_S3C24XX || ARCH_S3C64XX || S5P_PM)
+ default y
+ help
+ Base platform power management code for samsung code
+
if PLAT_SAMSUNG
# boot configurations
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index a23c460..1c406b3 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -51,8 +51,7 @@ obj-$(CONFIG_SAMSUNG_DMADEV) += dma-ops.o
# PM support
[PATCH V2 2/2] ARM: EXYNOS: cpuidle: Allow C1 state only in supported SOC's.
This patch registers the basic C0 state for all exynos SOC's but limits the C1(AFTR -Arm off top running) state in only the supported SOC's(ie. EXYNOS 4210, 4212, 4412 and 5250). Signed-off-by: Amit Daniel Kachhap amit.dan...@samsung.com --- arch/arm/mach-exynos/cpuidle.c |4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c index 2d071c6..ccb2b48 100644 --- a/arch/arm/mach-exynos/cpuidle.c +++ b/arch/arm/mach-exynos/cpuidle.c @@ -176,7 +176,9 @@ static int __init exynos4_init_cpuidle(void) device-cpu = cpu_id; /* Support IDLE only */ - if (cpu_id != 0) + if (!(soc_is_exynos4210() || soc_is_exynos4212() || + soc_is_exynos4412() || soc_is_exynos5250()) || + cpu_id != 0) device-state_count = 1; ret = cpuidle_register_device(device); -- 1.7.1 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/3] ARM: dts: add pinctrl support to Exynos5420
Add the required pin configuration support to Exynos5420 using pinctrl
interface.
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
---
arch/arm/boot/dts/exynos5420-pinctrl.dtsi | 680 +
arch/arm/boot/dts/exynos5420.dtsi | 45 ++
2 files changed, 725 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5420-pinctrl.dtsi
diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
new file mode 100644
index 000..23b7521
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
@@ -0,0 +1,680 @@
+/*
+ * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/ {
+ pinctrl@1340 {
+ gpy7: gpy7 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpx0: gpx0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ interrupt-parent = combiner;
+ #interrupt-cells = 2;
+ interrupts = 23 0, 24 0, 25 0, 25 1,
+26 0, 26 1, 27 0, 27 1;
+ };
+
+ gpx1: gpx1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ interrupt-parent = combiner;
+ #interrupt-cells = 2;
+ interrupts = 28 0, 28 1, 29 0, 29 1,
+30 0, 30 1, 31 0, 31 1;
+ };
+
+ gpx2: gpx2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpx3: gpx3 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+ };
+
+ pinctrl@1341 {
+ gpc0: gpc0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpc1: gpc1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpc2: gpc2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpc3: gpc3 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpc4: gpc4 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpy0: gpy0 {
+ gpio-controller;
+ #gpio-cells = 2;
+ };
+
+ gpy1: gpy1 {
+ gpio-controller;
+ #gpio-cells = 2;
+ };
+
+ gpy2: gpy2 {
+ gpio-controller;
+ #gpio-cells = 2;
+ };
+
+ gpy3: gpy3 {
+ gpio-controller;
+ #gpio-cells = 2;
+ };
+
+ gpy4: gpy4 {
+ gpio-controller;
+ #gpio-cells = 2;
+ };
+
+ gpy5: gpy5 {
+ gpio-controller;
+ #gpio-cells = 2;
+ };
+
+ gpy6: gpy6 {
+ gpio-controller;
+ #gpio-cells = 2;
+ };
+
+ sd0_clk: sd0-clk {
+
[PATCH 3/3] gpio: samsung: skip gpiolib registration if pinctrl support is enabled for exynos5420
Skip exynos5420 gpiolib registration if pinctrl support is enabled.
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
---
drivers/gpio/gpio-samsung.c |1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index 83a0d71..b3dd984 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -3033,6 +3033,7 @@ static __init int samsung_gpiolib_init(void)
{ .compatible = samsung,exynos4210-pinctrl, },
{ .compatible = samsung,exynos4x12-pinctrl, },
{ .compatible = samsung,exynos5250-pinctrl, },
+ { .compatible = samsung,exynos5420-pinctrl, },
{ .compatible = samsung,exynos5440-pinctrl, },
{ }
};
--
1.7.10.4
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[PATCH 2/3] pinctrl: exynos: add exynos5420 SoC specific data
Add Samsung Exynos5420 SoC specific data to enable pinctrl support for
all platforms based on Exynos5420.
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
---
.../bindings/pinctrl/samsung-pinctrl.txt |1 +
drivers/pinctrl/pinctrl-exynos.c | 115
drivers/pinctrl/pinctrl-samsung.c |2 +
drivers/pinctrl/pinctrl-samsung.h |1 +
4 files changed, 119 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index b2bc219..fe949c7 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -15,6 +15,7 @@ Required Properties:
- samsung,exynos4210-pinctrl: for Exynos4210 compatible pin-controller.
- samsung,exynos4x12-pinctrl: for Exynos4x12 compatible pin-controller.
- samsung,exynos5250-pinctrl: for Exynos5250 compatible pin-controller.
+ - samsung,exynos5420-pinctrl: for Exynos5420 compatible pin-controller.
- reg: Base address of the pin controller hardware module and length of
the address space it occupies.
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 2d76f66..753a8cd 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -941,3 +941,118 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
.label = exynos5250-gpio-ctrl3,
},
};
+
+/* pin banks of exynos5420 pin-controller 0 */
+static struct samsung_pin_bank exynos5420_pin_banks0[] = {
+ EXYNOS_PIN_BANK_EINTN(8, 0x000, gpy7),
+ EXYNOS_PIN_BANK_EINTW(8, 0xC00, gpx0, 0x00),
+ EXYNOS_PIN_BANK_EINTW(8, 0xC20, gpx1, 0x04),
+ EXYNOS_PIN_BANK_EINTW(8, 0xC40, gpx2, 0x08),
+ EXYNOS_PIN_BANK_EINTW(8, 0xC60, gpx3, 0x0c),
+};
+
+/* pin banks of exynos5420 pin-controller 1 */
+static struct samsung_pin_bank exynos5420_pin_banks1[] = {
+ EXYNOS_PIN_BANK_EINTG(8, 0x000, gpc0, 0x00),
+ EXYNOS_PIN_BANK_EINTG(8, 0x020, gpc1, 0x04),
+ EXYNOS_PIN_BANK_EINTG(7, 0x040, gpc2, 0x08),
+ EXYNOS_PIN_BANK_EINTG(4, 0x060, gpc3, 0x0c),
+ EXYNOS_PIN_BANK_EINTG(2, 0x080, gpc4, 0x10),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0A0, gpd1, 0x14),
+ EXYNOS_PIN_BANK_EINTN(6, 0x0C0, gpy0),
+ EXYNOS_PIN_BANK_EINTN(4, 0x0E0, gpy1),
+ EXYNOS_PIN_BANK_EINTN(6, 0x100, gpy2),
+ EXYNOS_PIN_BANK_EINTN(8, 0x120, gpy3),
+ EXYNOS_PIN_BANK_EINTN(8, 0x140, gpy4),
+ EXYNOS_PIN_BANK_EINTN(8, 0x160, gpy5),
+ EXYNOS_PIN_BANK_EINTN(8, 0x180, gpy6),
+};
+
+/* pin banks of exynos5420 pin-controller 2 */
+static struct samsung_pin_bank exynos5420_pin_banks2[] = {
+ EXYNOS_PIN_BANK_EINTG(8, 0x000, gpe0, 0x00),
+ EXYNOS_PIN_BANK_EINTG(2, 0x020, gpe1, 0x04),
+ EXYNOS_PIN_BANK_EINTG(6, 0x040, gpf0, 0x08),
+ EXYNOS_PIN_BANK_EINTG(8, 0x060, gpf1, 0x0c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x080, gpg0, 0x10),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0A0, gpg1, 0x14),
+ EXYNOS_PIN_BANK_EINTG(2, 0x0C0, gpg2, 0x18),
+ EXYNOS_PIN_BANK_EINTG(4, 0x0E0, gpj4, 0x1c),
+};
+
+/* pin banks of exynos5420 pin-controller 3 */
+static struct samsung_pin_bank exynos5420_pin_banks3[] = {
+ EXYNOS_PIN_BANK_EINTG(8, 0x000, gpa0, 0x00),
+ EXYNOS_PIN_BANK_EINTG(6, 0x020, gpa1, 0x04),
+ EXYNOS_PIN_BANK_EINTG(8, 0x040, gpa2, 0x08),
+ EXYNOS_PIN_BANK_EINTG(5, 0x060, gpb0, 0x0c),
+ EXYNOS_PIN_BANK_EINTG(5, 0x080, gpb1, 0x10),
+ EXYNOS_PIN_BANK_EINTG(4, 0x0A0, gpb2, 0x14),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0C0, gpb3, 0x18),
+ EXYNOS_PIN_BANK_EINTG(2, 0x0E0, gpb4, 0x1c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x100, gph0, 0x20),
+};
+
+/* pin banks of exynos5420 pin-controller 4 */
+static struct samsung_pin_bank exynos5420_pin_banks4[] = {
+ EXYNOS_PIN_BANK_EINTG(8, 0x000, gpz, 0x00),
+};
+
+/*
+ * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes
+ * four gpio/pin-mux/pinconfig controllers.
+ */
+struct samsung_pin_ctrl exynos5420_pin_ctrl[] = {
+ {
+ /* pin-controller instance 0 data */
+ .pin_banks = exynos5420_pin_banks0,
+ .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0),
+ .weint_con = EXYNOS_WKUP_ECON_OFFSET,
+ .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
+ .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
+ .svc= EXYNOS_SVC_OFFSET,
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .eint_wkup_init = exynos_eint_wkup_init,
+ .label = exynos5420-gpio-ctrl0,
+ }, {
+ /* pin-controller instance 1 data */
+ .pin_banks = exynos5420_pin_banks1,
+ .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1),
+ .geint_con =
Re: [PATCH v3 3/6] clk: samsung: Add set_rate() clk_ops for PLL35xx
On Sat, Jun 8, 2013 at 5:42 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
On Friday 31 of May 2013 18:01:33 Vikas Sajjan wrote:
From: Yadwinder Singh Brar yadi.b...@samsung.com
This patch add set_rate() and round_rate() for PLL35xx
Reviewed-by: Doug Anderson diand...@chromium.org
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
---
drivers/clk/samsung/clk-pll.c | 103
- 1 file changed, 102
insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-pll.c
b/drivers/clk/samsung/clk-pll.c index 8226528..9591560 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -27,6 +27,36 @@ struct samsung_clk_pll {
#define pll_writel(pll, val, offset) \
__raw_writel(val, (void __iomem *)(pll-base + (offset)));
+static const struct samsung_pll_rate_table *samsung_get_pll_settings(
+ struct samsung_clk_pll *pll, unsigned long
rate)
+{
+ const struct samsung_pll_rate_table *rate_table = pll-
rate_table;
+ int i;
+
+ for (i = 0; i pll-rate_count; i++) {
+ if (rate == rate_table[i].rate)
+ return rate_table[i];
+ }
+
+ return NULL;
+}
+
+static long samsung_pll_round_rate(struct clk_hw *hw,
+ unsigned long drate, unsigned long *prate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ const struct samsung_pll_rate_table *rate_table = pll-rate_table;
+ int i;
+
+ /* Assumming rate_table is in descending order */
+ for (i = 0; i pll-rate_count; i++) {
+ if (drate = rate_table[i].rate)
+ return rate_table[i].rate;
+ }
+
+ /* return minimum supported value */
+ return rate_table[i - 1].rate;
+}
/*
* PLL35xx Clock Type
*/
@@ -34,12 +64,17 @@ struct samsung_clk_pll {
#define PLL35XX_CON0_OFFSET (0x100)
#define PLL35XX_CON1_OFFSET (0x104)
+/* Maximum lock time can be 270 * PDIV cycles */
+#define PLL35XX_LOCK_FACTOR (270)
+
#define PLL35XX_MDIV_MASK (0x3FF)
#define PLL35XX_PDIV_MASK (0x3F)
#define PLL35XX_SDIV_MASK (0x7)
+#define PLL35XX_LOCK_STAT_MASK (0x1)
#define PLL35XX_MDIV_SHIFT (16)
#define PLL35XX_PDIV_SHIFT (8)
#define PLL35XX_SDIV_SHIFT (0)
+#define PLL35XX_LOCK_STAT_SHIFT (29)
static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
@@ -59,8 +94,70 @@ static unsigned long
samsung_pll35xx_recalc_rate(struct clk_hw *hw, return (unsigned
long)fvco;
}
+static inline bool samsung_pll35xx_mp_change(u32 mdiv, u32 pdiv, u32
pll_con) +{
+ if ((mdiv != ((pll_con PLL35XX_MDIV_SHIFT)
PLL35XX_MDIV_MASK)) ||
+ (pdiv != ((pll_con PLL35XX_PDIV_SHIFT)
PLL35XX_PDIV_MASK)))
+ return 1;
+ else
+ return 0;
Readability of this function could be improved by moving some code out of
the if clause, like:
static inline bool samsung_pll35xx_mp_change(u32 mdiv,
u32 pdiv, u32 pll_con)
{
u32 old_mdiv, old_pdiv;
old_mdiv = (pll_con PLL35XX_MDIV_SHIFT) PLL35XX_MDIV_MASK;
old_pdiv = (pll_con PLL35XX_PDIV_SHIFT) PLL35XX_PDIV_MASK;
return (mdiv != old_mdiv || pdiv != old_pdiv);
}
Yes, it looks neater, I have modified it V4.
+}
+
+static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long
drate, + unsigned long prate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ const struct samsung_pll_rate_table *rate;
+ u32 tmp;
+
+ /* Get required rate settings from table */
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err(%s: Invalid rate : %lu for pll clk %s\n,
__func__,
+ drate, __clk_get_name(hw-clk));
+ return -EINVAL;
+ }
+
+ tmp = pll_readl(pll, PLL35XX_CON0_OFFSET);
+
+ if (!(samsung_pll35xx_mp_change(rate-mdiv, rate-pdiv, tmp))) {
+ /* If only s change, change just s value only*/
+ tmp = ~(PLL35XX_SDIV_MASK PLL35XX_SDIV_SHIFT);
+ tmp |= rate-sdiv PLL35XX_SDIV_SHIFT;
+ pll_writel(pll, tmp, PLL35XX_CON0_OFFSET);
To improve readability of this code, return 0 could be added here and
following code could be moved out of the else clause.
Hmm... I can't see much difference but I have taken this also.
Thanks,
Yadwinder
Best regards,
Tomasz
+ } else {
+ /* Set PLL lock time. */
+ pll_writel(pll, rate-pdiv * PLL35XX_LOCK_FACTOR,
+ PLL35XX_LOCK_OFFSET);
+
+ /* Change PLL PMS values */
+ tmp = ~((PLL35XX_MDIV_MASK PLL35XX_MDIV_SHIFT) |
+ (PLL35XX_PDIV_MASK
Re: [PATCH V3 1/3] Add PCIe driver for Samsung Exynos
On Wednesday 12 June 2013, Jingoo Han wrote:
On Friday, June 07, 2013 7:53 PM, Arnd Bergmann wrote:
On Friday 07 June 2013 18:22:50 Jingoo Han wrote:
+- ranges: ranges for the PCI memory and I/O regions
+- reset-gpio: gpio pin number of power good signal
The 'reset-gpio' property seems incorrect. I think this should either
use the gpio binding or the reset-controller binding. Specifying
bare numbers to use as gpio pins does not work, since the number
space for Linux internal gpio numbers is not necessarily the same
as used by the hardware.
As you mentioned, other Exynos SoCs such as Exynos5250 set
GPIO properties in DT, as below:
(./arch/arm/boot/dts/exynos5250-smdk5250.dts)
hdmi {
hpd-gpio = gpx3 7 0;
};
usb@1211 {
samsung,vbus-gpio = gpx2 6 0;
};
However, the situation of Exynos5440 GPIO is different.
The following bare numbers of GPIO work properly on Exynos5440.
(./arch/arm/boot/dts/exynos5440-ssdk5440.dts)
pcie0@4000 {
reset-gpio = 5;
}
pcie0@4000 {
reset-gpio = 22;
}
Thomas Abraham is the author of pinctrl driver for EXYNOS5440.
(./drivers/pinctrl/pinctrl-exynos5440.c)
Thomas Abraham or Kukjin Kim, can you confirm this?
If I am wrong, please let me know kindly. :)
This is not about the code working at the moment, it is about
it being correct. The current method you are using would stop
working if something changes in the pinctrl code, and would
not be portable to other SoCs.
Arnd
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Re: [PATCH 6/6] ARM: dts: Add pcie controller node for Samsung EXYNOS5440 SoC
On Tuesday 11 June 2013, Jingoo Han wrote: + ranges = 0x0800 0 0x4000 0x4000 0 0x0020 /* configuration space */ + 0x8100 0 0 0x4020 0 0x4000 /* downstream I/O */ + 0x8200 0 0 0x40204000 0 0x1000; /* non-prefetchable memory */ + }; ... Also, shouldn't your memory space end on a 256MB boundary, rather than extend up to 0x50203fff? According to the manual of Exynos PCIe, each memory space for Exynos PCIe can support 512MB, including I/O, CFG regions. Is there any problem when over 256MB boundary is used? Please let me know. :) No, that's not a problem, but I think you should have the window span the entire space that is provided in hardware. If there are 512 MB total, why not use them? You could use ranges = 0x8200 0 0 0x40204000 0 0x1fdfc000; to pass a range for the memory space that extends all the way until 0x5fff. Arnd -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 0/6] Add generic set_rate clk_ops for PLL35xx and PLL36xx for samsung SoCs
This patch series does the following: 1) Unifies the clk strutures used for PLL35xx PLL36xx and usues clk-base instead of clk-con0, to factor out possible common code. 2) Defines a common rate_table which will contain recommended p, m, s and k values for supported rates that needs to be changed for changing corresponding PLL's rate 3) Adds set_rate() and round_rate() clk_ops for PLL35xx and PLL36xx changes since v3: - Used __clk_lookup() instead of adding alias for mout_vpllsrc - Added check for changing only M value in samsung_pll36xx_set_rate() - Modified samsung_pll35xx_mp_change() samsung_pll35xx_set_rate() to improve readabilty. - Made the input rate_table as __init_data which is to be provided while registering PLL and made a copy of that table while registering, so that if multiple tables are their, they can be freed after getting the P, M, S, K setting values from required one. changes since v2: - Added new patch to reorder the MUX registration for mout_vpllsrc MUX before the PLL registrations. And to add the alias for the mout_vpllsrc MUX. - Added a check to confirm parent rate while registrating the PLL rate tables. changes since v1: - removed sorting and bsearch - modified the definition of struct samsung_pll_rate_table - added generic round_rate() - rectified the ops assignment for rate table passed as NULL during PLL registration Is rebased on branch kgene's for-next https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next Vikas Sajjan (3): clk: samsung: Add set_rate() clk_ops for PLL36xx clk: samsung: Reorder MUX registration for mout_vpllsrc clk: samsung: Add EPLL and VPLL freq table for exynos5250 SoC Yadwinder Singh Brar (3): clk: samsung: Use clk-base instead of directly using clk-con0 for PLL3xxx clk: samsung: Add support to register rate_table for PLL3xxx clk: samsung: Add set_rate() clk_ops for PLL35xx drivers/clk/samsung/clk-exynos4.c| 10 +- drivers/clk/samsung/clk-exynos5250.c | 73 +-- drivers/clk/samsung/clk-pll.c| 255 ++ drivers/clk/samsung/clk-pll.h| 35 +- drivers/clk/samsung/clk.h|2 + 5 files changed, 332 insertions(+), 43 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 1/6] clk: samsung: Use clk-base instead of directly using clk-con0 for PLL3xxx
This patch unifies clk strutures used for PLL35xx PLL36xx and uses clk-base
instead of directly using clk-con0, so that possible common code can be
factored out.
It also introdues common pll_[readl/writel] macros for the users of common
samsung_clk_pll struct.
Reviewed-by: Tomasz Figa t.f...@samsung.com
Reviewed-by: Doug Anderson diand...@chromium.org
Tested-by: Doug Anderson diand...@chromium.org
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c| 10 --
drivers/clk/samsung/clk-exynos5250.c | 14
drivers/clk/samsung/clk-pll.c| 54 ++---
drivers/clk/samsung/clk-pll.h|4 +-
4 files changed, 44 insertions(+), 38 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index addc738..ba33bc6 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -97,12 +97,14 @@
#define GATE_IP_PERIL 0xc950
#define E4210_GATE_IP_PERIR0xc960
#define GATE_BLOCK 0xc970
+#define E4X12_MPLL_LOCK0x10008
#define E4X12_MPLL_CON00x10108
#define SRC_DMC0x10200
#define SRC_MASK_DMC 0x10300
#define DIV_DMC0 0x10500
#define DIV_DMC1 0x10504
#define GATE_IP_DMC0x10900
+#define APLL_LOCK 0x14000
#define APLL_CON0 0x14100
#define E4210_MPLL_CON00x14108
#define SRC_CPU0x14200
@@ -1026,13 +1028,13 @@ void __init exynos4_clk_init(struct device_node *np,
enum exynos4_soc exynos4_so
reg_base + VPLL_CON0, pll_4650c);
} else {
apll = samsung_clk_register_pll35xx(fout_apll, fin_pll,
- reg_base + APLL_CON0);
+ reg_base + APLL_LOCK);
mpll = samsung_clk_register_pll35xx(fout_mpll, fin_pll,
- reg_base + E4X12_MPLL_CON0);
+ reg_base + E4X12_MPLL_LOCK);
epll = samsung_clk_register_pll36xx(fout_epll, fin_pll,
- reg_base + EPLL_CON0);
+ reg_base + EPLL_LOCK);
vpll = samsung_clk_register_pll36xx(fout_vpll, fin_pll,
- reg_base + VPLL_CON0);
+ reg_base + VPLL_LOCK);
}
samsung_clk_add_lookup(apll, fout_apll);
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index 5c97e75..687b580 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -491,19 +491,19 @@ void __init exynos5250_clk_init(struct device_node *np)
ext_clk_match);
apll = samsung_clk_register_pll35xx(fout_apll, fin_pll,
- reg_base + 0x100);
+ reg_base);
mpll = samsung_clk_register_pll35xx(fout_mpll, fin_pll,
- reg_base + 0x4100);
+ reg_base + 0x4000);
bpll = samsung_clk_register_pll35xx(fout_bpll, fin_pll,
- reg_base + 0x20110);
+ reg_base + 0x20010);
gpll = samsung_clk_register_pll35xx(fout_gpll, fin_pll,
- reg_base + 0x10150);
+ reg_base + 0x10050);
cpll = samsung_clk_register_pll35xx(fout_cpll, fin_pll,
- reg_base + 0x10120);
+ reg_base + 0x10020);
epll = samsung_clk_register_pll36xx(fout_epll, fin_pll,
- reg_base + 0x10130);
+ reg_base + 0x10030);
vpll = samsung_clk_register_pll36xx(fout_vpll, mout_vpllsrc,
- reg_base + 0x10140);
+ reg_base + 0x10040);
samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
ARRAY_SIZE(exynos5250_fixed_rate_clks));
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 89135f6..a7d8ad9 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -13,9 +13,24 @@
#include clk.h
#include clk-pll.h
+struct samsung_clk_pll {
+ struct clk_hw hw;
+ const void __iomem *base;
+};
+
+#define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw)
+
+#define pll_readl(pll, offset) \
+ __raw_readl((void __iomem *)(pll-base + (offset)));
+#define pll_writel(pll, val, offset) \
+ __raw_writel(val, (void __iomem *)(pll-base + (offset)));
+
/*
* PLL35xx Clock Type
*/
+#define PLL35XX_LOCK_OFFSET(0x0)
+#define PLL35XX_CON0_OFFSET(0x100)
+#define PLL35XX_CON1_OFFSET
[PATCH v4 3/6] clk: samsung: Add set_rate() clk_ops for PLL35xx
This patch add set_rate() and round_rate() for PLL35xx
Reviewed-by: Doug Anderson diand...@chromium.org
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
---
drivers/clk/samsung/clk-pll.c | 104 -
1 files changed, 103 insertions(+), 1 deletions(-)
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index cba73a4..319b52b 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -27,6 +27,37 @@ struct samsung_clk_pll {
#define pll_writel(pll, val, offset) \
__raw_writel(val, (void __iomem *)(pll-base + (offset)));
+static const struct samsung_pll_rate_table *samsung_get_pll_settings(
+ struct samsung_clk_pll *pll, unsigned long rate)
+{
+ const struct samsung_pll_rate_table *rate_table = pll-rate_table;
+ int i;
+
+ for (i = 0; i pll-rate_count; i++) {
+ if (rate == rate_table[i].rate)
+ return rate_table[i];
+ }
+
+ return NULL;
+}
+
+static long samsung_pll_round_rate(struct clk_hw *hw,
+ unsigned long drate, unsigned long *prate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ const struct samsung_pll_rate_table *rate_table = pll-rate_table;
+ int i;
+
+ /* Assumming rate_table is in descending order */
+ for (i = 0; i pll-rate_count; i++) {
+ if (drate = rate_table[i].rate)
+ return rate_table[i].rate;
+ }
+
+ /* return minimum supported value */
+ return rate_table[i - 1].rate;
+}
+
/*
* PLL35xx Clock Type
*/
@@ -34,12 +65,17 @@ struct samsung_clk_pll {
#define PLL35XX_CON0_OFFSET(0x100)
#define PLL35XX_CON1_OFFSET(0x104)
+/* Maximum lock time can be 270 * PDIV cycles */
+#define PLL35XX_LOCK_FACTOR(270)
+
#define PLL35XX_MDIV_MASK (0x3FF)
#define PLL35XX_PDIV_MASK (0x3F)
#define PLL35XX_SDIV_MASK (0x7)
+#define PLL35XX_LOCK_STAT_MASK (0x1)
#define PLL35XX_MDIV_SHIFT (16)
#define PLL35XX_PDIV_SHIFT (8)
#define PLL35XX_SDIV_SHIFT (0)
+#define PLL35XX_LOCK_STAT_SHIFT(29)
static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
@@ -59,8 +95,72 @@ static unsigned long samsung_pll35xx_recalc_rate(struct
clk_hw *hw,
return (unsigned long)fvco;
}
+static inline bool samsung_pll35xx_mp_change(
+ const struct samsung_pll_rate_table *rate, u32 pll_con)
+{
+ u32 old_mdiv, old_pdiv;
+
+ old_mdiv = (pll_con PLL35XX_MDIV_SHIFT) PLL35XX_MDIV_MASK;
+ old_pdiv = (pll_con PLL35XX_PDIV_SHIFT) PLL35XX_PDIV_MASK;
+
+ return (rate-mdiv != old_mdiv || rate-pdiv != old_pdiv);
+}
+
+static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long prate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ const struct samsung_pll_rate_table *rate;
+ u32 tmp;
+
+ /* Get required rate settings from table */
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err(%s: Invalid rate : %lu for pll clk %s\n, __func__,
+ drate, __clk_get_name(hw-clk));
+ return -EINVAL;
+ }
+
+ tmp = pll_readl(pll, PLL35XX_CON0_OFFSET);
+
+ if (!(samsung_pll35xx_mp_change(rate, tmp))) {
+ /* If only s change, change just s value only*/
+ tmp = ~(PLL35XX_SDIV_MASK PLL35XX_SDIV_SHIFT);
+ tmp |= rate-sdiv PLL35XX_SDIV_SHIFT;
+ pll_writel(pll, tmp, PLL35XX_CON0_OFFSET);
+ } else {
+ /* Set PLL lock time. */
+ pll_writel(pll, rate-pdiv * PLL35XX_LOCK_FACTOR,
+ PLL35XX_LOCK_OFFSET);
+
+ /* Change PLL PMS values */
+ tmp = ~((PLL35XX_MDIV_MASK PLL35XX_MDIV_SHIFT) |
+ (PLL35XX_PDIV_MASK PLL35XX_PDIV_SHIFT) |
+ (PLL35XX_SDIV_MASK PLL35XX_SDIV_SHIFT));
+ tmp |= (rate-mdiv PLL35XX_MDIV_SHIFT) |
+ (rate-pdiv PLL35XX_PDIV_SHIFT) |
+ (rate-sdiv PLL35XX_SDIV_SHIFT);
+ pll_writel(pll, tmp, PLL35XX_CON0_OFFSET);
+
+ /* wait_lock_time */
+ do {
+ cpu_relax();
+ tmp = pll_readl(pll, PLL35XX_CON0_OFFSET);
+ } while (!(tmp (PLL35XX_LOCK_STAT_MASK
+PLL35XX_LOCK_STAT_SHIFT)));
+ }
+
+ return 0;
+}
+
static const struct clk_ops samsung_pll35xx_clk_ops = {
.recalc_rate = samsung_pll35xx_recalc_rate,
+ .round_rate = samsung_pll_round_rate,
+ .set_rate = samsung_pll35xx_set_rate,
+};
+
+static const
[PATCH v4 2/6] clk: samsung: Add support to register rate_table for PLL3xxx
This patch defines a common rate_table which will contain recommended p, m, s,
k values for supported rates that needs to be changed for changing
corresponding PLL's rate.
Reviewed-by: Doug Anderson diand...@chromium.org
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c|8 +++---
drivers/clk/samsung/clk-exynos5250.c | 14 ++--
drivers/clk/samsung/clk-pll.c| 22 +++-
drivers/clk/samsung/clk-pll.h| 35 -
4 files changed, 64 insertions(+), 15 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index ba33bc6..e02a342 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1028,13 +1028,13 @@ void __init exynos4_clk_init(struct device_node *np,
enum exynos4_soc exynos4_so
reg_base + VPLL_CON0, pll_4650c);
} else {
apll = samsung_clk_register_pll35xx(fout_apll, fin_pll,
- reg_base + APLL_LOCK);
+ reg_base + APLL_LOCK, NULL, 0);
mpll = samsung_clk_register_pll35xx(fout_mpll, fin_pll,
- reg_base + E4X12_MPLL_LOCK);
+ reg_base + E4X12_MPLL_LOCK, NULL, 0);
epll = samsung_clk_register_pll36xx(fout_epll, fin_pll,
- reg_base + EPLL_LOCK);
+ reg_base + EPLL_LOCK, NULL, 0);
vpll = samsung_clk_register_pll36xx(fout_vpll, fin_pll,
- reg_base + VPLL_LOCK);
+ reg_base + VPLL_LOCK, NULL, 0);
}
samsung_clk_add_lookup(apll, fout_apll);
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index 687b580..ddf10ca 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -491,19 +491,19 @@ void __init exynos5250_clk_init(struct device_node *np)
ext_clk_match);
apll = samsung_clk_register_pll35xx(fout_apll, fin_pll,
- reg_base);
+ reg_base, NULL, 0);
mpll = samsung_clk_register_pll35xx(fout_mpll, fin_pll,
- reg_base + 0x4000);
+ reg_base + 0x4000, NULL, 0);
bpll = samsung_clk_register_pll35xx(fout_bpll, fin_pll,
- reg_base + 0x20010);
+ reg_base + 0x20010, NULL, 0);
gpll = samsung_clk_register_pll35xx(fout_gpll, fin_pll,
- reg_base + 0x10050);
+ reg_base + 0x10050, NULL, 0);
cpll = samsung_clk_register_pll35xx(fout_cpll, fin_pll,
- reg_base + 0x10020);
+ reg_base + 0x10020, NULL, 0);
epll = samsung_clk_register_pll36xx(fout_epll, fin_pll,
- reg_base + 0x10030);
+ reg_base + 0x10030, NULL, 0);
vpll = samsung_clk_register_pll36xx(fout_vpll, mout_vpllsrc,
- reg_base + 0x10040);
+ reg_base + 0x10040, NULL, 0);
samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
ARRAY_SIZE(exynos5250_fixed_rate_clks));
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index a7d8ad9..cba73a4 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -16,6 +16,8 @@
struct samsung_clk_pll {
struct clk_hw hw;
const void __iomem *base;
+ const struct samsung_pll_rate_table *rate_table;
+ unsigned int rate_count;
};
#define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw)
@@ -62,7 +64,9 @@ static const struct clk_ops samsung_pll35xx_clk_ops = {
};
struct clk * __init samsung_clk_register_pll35xx(const char *name,
- const char *pname, const void __iomem *base)
+ const char *pname, const void __iomem *base,
+ const struct samsung_pll_rate_table *rate_table,
+ const unsigned int rate_count)
{
struct samsung_clk_pll *pll;
struct clk *clk;
@@ -80,6 +84,12 @@ struct clk * __init samsung_clk_register_pll35xx(const char
*name,
init.parent_names = pname;
init.num_parents = 1;
+ if (rate_table rate_count) {
+ pll-rate_count = rate_count;
+ pll-rate_table = kmemdup(rate_table, rate_count *
+ sizeof(struct samsung_pll_rate_table), GFP_KERNEL);
+ }
+
pll-hw.init = init;
pll-base = base;
@@ -137,7 +147,9 @@ static const struct clk_ops samsung_pll36xx_clk_ops = {
};
struct clk * __init samsung_clk_register_pll36xx(const
[PATCH v4 4/6] clk: samsung: Add set_rate() clk_ops for PLL36xx
From: Vikas Sajjan vikas.saj...@linaro.org
This patch adds set_rate and round_rate clk_ops for PLL36xx
Reviewed-by: Tomasz Figa t.f...@samsung.com
Reviewed-by: Doug Anderson diand...@chromium.org
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
---
drivers/clk/samsung/clk-pll.c | 79 -
1 files changed, 78 insertions(+), 1 deletions(-)
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 319b52b..42b60b5 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -215,6 +215,9 @@ struct clk * __init samsung_clk_register_pll35xx(const char
*name,
#define PLL36XX_CON0_OFFSET(0x100)
#define PLL36XX_CON1_OFFSET(0x104)
+/* Maximum lock time can be 3000 * PDIV cycles */
+#define PLL36XX_LOCK_FACTOR(3000)
+
#define PLL36XX_KDIV_MASK (0x)
#define PLL36XX_MDIV_MASK (0x1FF)
#define PLL36XX_PDIV_MASK (0x3F)
@@ -222,6 +225,8 @@ struct clk * __init samsung_clk_register_pll35xx(const char
*name,
#define PLL36XX_MDIV_SHIFT (16)
#define PLL36XX_PDIV_SHIFT (8)
#define PLL36XX_SDIV_SHIFT (0)
+#define PLL36XX_KDIV_SHIFT (0)
+#define PLL36XX_LOCK_STAT_SHIFT(29)
static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
@@ -244,8 +249,78 @@ static unsigned long samsung_pll36xx_recalc_rate(struct
clk_hw *hw,
return (unsigned long)fvco;
}
+static inline bool samsung_pll36xx_mpk_change(
+ const struct samsung_pll_rate_table *rate, u32 pll_con0, u32 pll_con1)
+{
+ u32 old_mdiv, old_pdiv, old_kdiv;
+
+ old_mdiv = (pll_con0 PLL36XX_MDIV_SHIFT) PLL36XX_MDIV_MASK;
+ old_pdiv = (pll_con0 PLL36XX_PDIV_SHIFT) PLL36XX_PDIV_MASK;
+ old_kdiv = (pll_con1 PLL36XX_KDIV_SHIFT) PLL36XX_KDIV_MASK;
+
+ return (rate-mdiv != old_mdiv || rate-pdiv != old_pdiv ||
+ rate-kdiv != old_kdiv);
+}
+
+static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 tmp, pll_con0, pll_con1;
+ const struct samsung_pll_rate_table *rate;
+
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err(%s: Invalid rate : %lu for pll clk %s\n, __func__,
+ drate, __clk_get_name(hw-clk));
+ return -EINVAL;
+ }
+
+ pll_con0 = pll_readl(pll, PLL36XX_CON0_OFFSET);
+ pll_con1 = pll_readl(pll, PLL36XX_CON1_OFFSET);
+
+ if (!(samsung_pll36xx_mpk_change(rate, pll_con0, pll_con1))) {
+ /* If only s change, change just s value only*/
+ pll_con0 = ~(PLL36XX_SDIV_MASK PLL36XX_SDIV_SHIFT);
+ pll_con0 |= (rate-sdiv PLL36XX_SDIV_SHIFT);
+ pll_writel(pll, pll_con0, PLL36XX_CON0_OFFSET);
+ return 0;
+ }
+
+ /* Set PLL lock time. */
+ pll_writel(pll, (rate-pdiv * PLL36XX_LOCK_FACTOR),
+ PLL36XX_LOCK_OFFSET);
+
+/* Change PLL PMS values */
+ pll_con0 = ~((PLL36XX_MDIV_MASK PLL36XX_MDIV_SHIFT) |
+ (PLL36XX_PDIV_MASK PLL36XX_PDIV_SHIFT) |
+ (PLL36XX_SDIV_MASK PLL36XX_SDIV_SHIFT));
+ pll_con0 |= (rate-mdiv PLL36XX_MDIV_SHIFT) |
+ (rate-pdiv PLL36XX_PDIV_SHIFT) |
+ (rate-sdiv PLL36XX_SDIV_SHIFT);
+ pll_writel(pll, pll_con0, PLL36XX_CON0_OFFSET);
+
+ pll_con1 = ~(PLL36XX_KDIV_MASK PLL36XX_KDIV_SHIFT);
+ pll_con1 |= rate-kdiv PLL36XX_KDIV_SHIFT;
+ pll_writel(pll, pll_con1, PLL36XX_CON1_OFFSET);
+
+ /* wait_lock_time */
+ do {
+ cpu_relax();
+ tmp = pll_readl(pll, PLL36XX_CON0_OFFSET);
+ } while (!(tmp (1 PLL36XX_LOCK_STAT_SHIFT)));
+
+ return 0;
+}
+
static const struct clk_ops samsung_pll36xx_clk_ops = {
.recalc_rate = samsung_pll36xx_recalc_rate,
+ .set_rate = samsung_pll36xx_set_rate,
+ .round_rate = samsung_pll_round_rate,
+};
+
+static const struct clk_ops samsung_pll36xx_clk_min_ops = {
+ .recalc_rate = samsung_pll36xx_recalc_rate,
};
struct clk * __init samsung_clk_register_pll36xx(const char *name,
@@ -264,7 +339,6 @@ struct clk * __init samsung_clk_register_pll36xx(const char
*name,
}
init.name = name;
- init.ops = samsung_pll36xx_clk_ops;
init.flags = CLK_GET_RATE_NOCACHE;
init.parent_names = pname;
init.num_parents = 1;
@@ -273,6 +347,9 @@ struct clk * __init samsung_clk_register_pll36xx(const char
*name,
pll-rate_count = rate_count;
pll-rate_table = kmemdup(rate_table, rate_count *
sizeof(struct samsung_pll_rate_table), GFP_KERNEL);
+ init.ops = samsung_pll36xx_clk_ops;
+ } else {
+
[PATCH v4 5/6] clk: samsung: Reorder MUX registration for mout_vpllsrc
From: Vikas Sajjan vikas.saj...@linaro.org
While trying to get rate of mout_vpllsrc MUX (parent) for registering the
fout_vpll (child), we found get rate was failing.
So this patch moves the mout_vpllsrc MUX out of the existing common list
and registers the mout_vpllsrc MUX before the PLL registrations.
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
---
drivers/clk/samsung/clk-exynos5250.c |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index ddf10ca..70cc6cf 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -207,6 +207,10 @@ struct samsung_fixed_factor_clock
exynos5250_fixed_factor_clks[] __initdata = {
FFACTOR(none, fout_bplldiv2, fout_bpll, 1, 2, 0),
};
+struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = {
+ MUX(none, mout_vpllsrc, mout_vpllsrc_p, SRC_TOP2, 0, 1),
+};
+
struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
MUX(none, mout_apll, mout_apll_p, SRC_CPU, 0, 1),
MUX(none, mout_cpu, mout_cpu_p, SRC_CPU, 16, 1),
@@ -214,7 +218,6 @@ struct samsung_mux_clock exynos5250_mux_clks[] __initdata =
{
MUX(none, sclk_mpll, mout_mpll_p, SRC_CORE1, 8, 1),
MUX(none, mout_bpll_fout, mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
MUX(none, sclk_bpll, mout_bpll_p, SRC_CDREX, 0, 1),
- MUX(none, mout_vpllsrc, mout_vpllsrc_p, SRC_TOP2, 0, 1),
MUX(none, sclk_vpll, mout_vpll_p, SRC_TOP2, 16, 1),
MUX(none, sclk_epll, mout_epll_p, SRC_TOP2, 12, 1),
MUX(none, sclk_cpll, mout_cpll_p, SRC_TOP2, 8, 1),
@@ -490,6 +493,9 @@ void __init exynos5250_clk_init(struct device_node *np)
ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
ext_clk_match);
+ samsung_clk_register_mux(exynos5250_pll_pmux_clks,
+ ARRAY_SIZE(exynos5250_pll_pmux_clks));
+
apll = samsung_clk_register_pll35xx(fout_apll, fin_pll,
reg_base, NULL, 0);
mpll = samsung_clk_register_pll35xx(fout_mpll, fin_pll,
--
1.7.0.4
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[PATCH v4 6/6] clk: samsung: Add EPLL and VPLL freq table for exynos5250 SoC
Adds the EPLL and VPLL freq table for exynos5250 SoC.
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
---
drivers/clk/samsung/clk-exynos5250.c | 53 --
drivers/clk/samsung/clk.h|2 +
2 files changed, 52 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index 70cc6cf..f98c19d 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -472,11 +472,34 @@ static __initdata struct of_device_id ext_clk_match[] = {
{ },
};
+static __initdata struct samsung_pll_rate_table vpll_24mhz_tbl[] = {
+ /* sorted in descending order */
+ /* PLL_36XX_RATE(rate, m, p, s, k) */
+ PLL_36XX_RATE(26600, 266, 3, 3, 0),
+ /* Not in UM, but need for eDP on snow */
+ PLL_36XX_RATE(7050, 94, 2, 4, 0),
+};
+
+static __initdata struct samsung_pll_rate_table epll_24mhz_tbl[] = {
+ /* sorted in descending order */
+ /* PLL_36XX_RATE(rate, m, p, s, k) */
+ PLL_36XX_RATE(19200, 48, 3, 1, 0),
+ PLL_36XX_RATE(180633600, 45, 3, 1, 10381),
+ PLL_36XX_RATE(18000, 45, 3, 1, 0),
+ PLL_36XX_RATE(73728000, 73, 3, 3, 47710),
+ PLL_36XX_RATE(67737600, 90, 4, 3, 20762),
+ PLL_36XX_RATE(49152000, 49, 3, 3, 9962),
+ PLL_36XX_RATE(45158400, 45, 3, 3, 10381),
+ PLL_36XX_RATE(32768000, 131, 3, 5, 4719),
+};
+
/* register exynox5250 clocks */
void __init exynos5250_clk_init(struct device_node *np)
{
void __iomem *reg_base;
struct clk *apll, *mpll, *epll, *vpll, *bpll, *gpll, *cpll;
+ struct clk *vpllsrc;
+ unsigned long fin_pll_rate, mout_vpllsrc_rate = 0;
if (np) {
reg_base = of_iomap(np, 0);
@@ -496,6 +519,11 @@ void __init exynos5250_clk_init(struct device_node *np)
samsung_clk_register_mux(exynos5250_pll_pmux_clks,
ARRAY_SIZE(exynos5250_pll_pmux_clks));
+ fin_pll_rate = _get_rate(fin_pll);
+ vpllsrc = __clk_lookup(mout_vpllsrc);
+ if (vpllsrc)
+ mout_vpllsrc_rate = clk_get_rate(vpllsrc);
+
apll = samsung_clk_register_pll35xx(fout_apll, fin_pll,
reg_base, NULL, 0);
mpll = samsung_clk_register_pll35xx(fout_mpll, fin_pll,
@@ -506,10 +534,29 @@ void __init exynos5250_clk_init(struct device_node *np)
reg_base + 0x10050, NULL, 0);
cpll = samsung_clk_register_pll35xx(fout_cpll, fin_pll,
reg_base + 0x10020, NULL, 0);
- epll = samsung_clk_register_pll36xx(fout_epll, fin_pll,
- reg_base + 0x10030, NULL, 0);
- vpll = samsung_clk_register_pll36xx(fout_vpll, mout_vpllsrc,
+
+ if (fin_pll_rate == (24 * MHZ)) {
+ epll = samsung_clk_register_pll36xx(fout_epll, fin_pll,
+ reg_base + 0x10030, epll_24mhz_tbl,
+ ARRAY_SIZE(epll_24mhz_tbl));
+ } else {
+ pr_warn(%s: valid epll rate_table missing for\n
+ parent fin_pll:%lu hz\n, __func__, fin_pll_rate);
+ epll = samsung_clk_register_pll36xx(fout_epll, fin_pll,
+ reg_base + 0x10030, NULL, 0);
+ }
+
+ if (mout_vpllsrc_rate == (24 * MHZ)) {
+ vpll = samsung_clk_register_pll36xx(fout_vpll, mout_vpllsrc
+ , reg_base + 0x10040, vpll_24mhz_tbl,
+ ARRAY_SIZE(vpll_24mhz_tbl));
+ } else {
+ pr_warn(%s: valid vpll rate_table missing for\n
+ parent mout_vpllsrc_rate:%lu hz\n, __func__,
+ mout_vpllsrc_rate);
+ samsung_clk_register_pll36xx(fout_vpll, mout_vpllsrc,
reg_base + 0x10040, NULL, 0);
+ }
samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
ARRAY_SIZE(exynos5250_fixed_rate_clks));
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index e4ad6ea..c997649 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -20,6 +20,8 @@
#include linux/of.h
#include linux/of_address.h
+#define MHZ (1000*1000)
+
/**
* struct samsung_clock_alias: information about mux clock
* @id: platform specific id of the clock.
--
1.7.0.4
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Re: [PATCH V6 6/6] clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2
Quoting Padmavathi Venna (2013-06-12 01:07:43)
This patch adds enum entries for div_i2s1 and div_i2s2 which are
required for i2s1 and i2s2 controllers.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Looks good. Did you want me to take the clk patches or just gathering
Acks?
Regards,
Mike
---
drivers/clk/samsung/clk-exynos5250.c |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index 5c97e75..7c68850 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -87,6 +87,7 @@ enum exynos5250_clks {
sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
+ div_i2s1, div_i2s2,
/* gate clocks */
gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
@@ -291,8 +292,8 @@ struct samsung_div_clock exynos5250_div_clks[] __initdata
= {
DIV(none, div_pcm1, sclk_audio1, DIV_PERIC4, 4, 8),
DIV(none, div_audio2, mout_audio2, DIV_PERIC4, 16, 4),
DIV(none, div_pcm2, sclk_audio2, DIV_PERIC4, 20, 8),
- DIV(none, div_i2s1, sclk_audio1, DIV_PERIC5, 0, 6),
- DIV(none, div_i2s2, sclk_audio2, DIV_PERIC5, 8, 6),
+ DIV(div_i2s1, div_i2s1, sclk_audio1, DIV_PERIC5, 0, 6),
+ DIV(div_i2s2, div_i2s2, sclk_audio2, DIV_PERIC5, 8, 6),
DIV(sclk_pixel, div_hdmi_pixel, sclk_vpll, DIV_DISP1_0, 28, 4),
DIV_A(none, armclk, div_arm, DIV_CPU0, 28, 3, armclk),
DIV_F(none, div_mipi1_pre, div_mipi1,
--
1.7.4.4
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Re: [PATCH v4 1/6] clk: samsung: Use clk-base instead of directly using clk-con0 for PLL3xxx
Yadwinder, On Mon, Jun 3, 2013 at 8:09 AM, Yadwinder Singh Brar yadi.b...@samsung.com wrote: This patch unifies clk strutures used for PLL35xx PLL36xx and uses clk-base instead of directly using clk-con0, so that possible common code can be factored out. It also introdues common pll_[readl/writel] macros for the users of common samsung_clk_pll struct. Reviewed-by: Tomasz Figa t.f...@samsung.com Reviewed-by: Doug Anderson diand...@chromium.org Tested-by: Doug Anderson diand...@chromium.org Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com --- drivers/clk/samsung/clk-exynos4.c| 10 -- drivers/clk/samsung/clk-exynos5250.c | 14 drivers/clk/samsung/clk-pll.c| 54 ++--- drivers/clk/samsung/clk-pll.h|4 +- 4 files changed, 44 insertions(+), 38 deletions(-) So. We just found that this type of solution doesn't work on exynos5420, since the LOCK and CON registers aren't always 0x100 away from each other. Perhaps you can adjust to use a solution like Andrew proposed in https://gerrit.chromium.org/gerrit/#/c/58411/? That way we can avoid some churn of changing this code twice. The number of parameters to the register PLL function is starting to get unwieldy. At some point we'll probably want to pass in a structure. I wonder if now would be the time? Certainly it would be easier to handle changes to the code without touching all of the exynos variants... Thanks! -Doug -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 1/6] clk: samsung: Use clk-base instead of directly using clk-con0 for PLL3xxx
Yadwinder, On Wed, Jun 12, 2013 at 1:33 PM, Doug Anderson diand...@chromium.org wrote: So. We just found that this type of solution doesn't work on exynos5420, since the LOCK and CON registers aren't always 0x100 away from each other. Perhaps you can adjust to use a solution like Andrew proposed in https://gerrit.chromium.org/gerrit/#/c/58411/? That way we can avoid some churn of changing this code twice. The number of parameters to the register PLL function is starting to get unwieldy. At some point we'll probably want to pass in a structure. I wonder if now would be the time? Certainly it would be easier to handle changes to the code without touching all of the exynos variants... It's also probably wise to preemptively rebase atop https://patchwork.kernel.org/patch/2704761/ since that looks like it will land in 3.10 and your series is destined for the release after. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 2/6] clk: samsung: Add support to register rate_table for PLL3xxx
Yadwinder,
On Mon, Jun 3, 2013 at 8:09 AM, Yadwinder Singh Brar
yadi.b...@samsung.com wrote:
This patch defines a common rate_table which will contain recommended p, m, s,
k values for supported rates that needs to be changed for changing
corresponding PLL's rate.
Reviewed-by: Doug Anderson diand...@chromium.org
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c|8 +++---
drivers/clk/samsung/clk-exynos5250.c | 14 ++--
drivers/clk/samsung/clk-pll.c| 22 +++-
drivers/clk/samsung/clk-pll.h| 35 -
4 files changed, 64 insertions(+), 15 deletions(-)
Using something like patman
http://git.denx.de/?p=u-boot.git;a=blob;f=tools/patman/README;hb=refs/heads/master
would really help here so you could get some version history. I see
it in 0/6 but that's a bit of a pain...
Did you and Tomasz ever come to an agreement about whether the fin
freq needs to be specified with the PMSK values?
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index ba33bc6..e02a342 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1028,13 +1028,13 @@ void __init exynos4_clk_init(struct device_node *np,
enum exynos4_soc exynos4_so
reg_base + VPLL_CON0, pll_4650c);
} else {
apll = samsung_clk_register_pll35xx(fout_apll, fin_pll,
- reg_base + APLL_LOCK);
+ reg_base + APLL_LOCK, NULL, 0);
mpll = samsung_clk_register_pll35xx(fout_mpll, fin_pll,
- reg_base + E4X12_MPLL_LOCK);
+ reg_base + E4X12_MPLL_LOCK, NULL, 0);
epll = samsung_clk_register_pll36xx(fout_epll, fin_pll,
- reg_base + EPLL_LOCK);
+ reg_base + EPLL_LOCK, NULL, 0);
vpll = samsung_clk_register_pll36xx(fout_vpll, fin_pll,
- reg_base + VPLL_LOCK);
+ reg_base + VPLL_LOCK, NULL, 0);
}
samsung_clk_add_lookup(apll, fout_apll);
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index 687b580..ddf10ca 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -491,19 +491,19 @@ void __init exynos5250_clk_init(struct device_node *np)
ext_clk_match);
apll = samsung_clk_register_pll35xx(fout_apll, fin_pll,
- reg_base);
+ reg_base, NULL, 0);
mpll = samsung_clk_register_pll35xx(fout_mpll, fin_pll,
- reg_base + 0x4000);
+ reg_base + 0x4000, NULL, 0);
bpll = samsung_clk_register_pll35xx(fout_bpll, fin_pll,
- reg_base + 0x20010);
+ reg_base + 0x20010, NULL, 0);
gpll = samsung_clk_register_pll35xx(fout_gpll, fin_pll,
- reg_base + 0x10050);
+ reg_base + 0x10050, NULL, 0);
cpll = samsung_clk_register_pll35xx(fout_cpll, fin_pll,
- reg_base + 0x10020);
+ reg_base + 0x10020, NULL, 0);
epll = samsung_clk_register_pll36xx(fout_epll, fin_pll,
- reg_base + 0x10030);
+ reg_base + 0x10030, NULL, 0);
vpll = samsung_clk_register_pll36xx(fout_vpll, mout_vpllsrc,
- reg_base + 0x10040);
+ reg_base + 0x10040, NULL, 0);
samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
ARRAY_SIZE(exynos5250_fixed_rate_clks));
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index a7d8ad9..cba73a4 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -16,6 +16,8 @@
struct samsung_clk_pll {
struct clk_hw hw;
const void __iomem *base;
+ const struct samsung_pll_rate_table *rate_table;
+ unsigned int rate_count;
};
#define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw)
@@ -62,7 +64,9 @@ static const struct clk_ops samsung_pll35xx_clk_ops = {
};
struct clk * __init samsung_clk_register_pll35xx(const char *name,
- const char *pname, const void __iomem *base)
+ const char *pname, const void __iomem *base,
+ const struct samsung_pll_rate_table *rate_table,
+ const unsigned int rate_count)
{
struct samsung_clk_pll *pll;
struct clk *clk;
@@ -80,6 +84,12 @@ struct clk * __init
Re: [PATCH v4 6/6] clk: samsung: Add EPLL and VPLL freq table for exynos5250 SoC
Yadwinder,
On Mon, Jun 3, 2013 at 8:09 AM, Yadwinder Singh Brar
yadi.b...@samsung.com wrote:
Adds the EPLL and VPLL freq table for exynos5250 SoC.
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
---
drivers/clk/samsung/clk-exynos5250.c | 53
--
drivers/clk/samsung/clk.h|2 +
2 files changed, 52 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index 70cc6cf..f98c19d 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -472,11 +472,34 @@ static __initdata struct of_device_id ext_clk_match[] =
{
{ },
};
+static __initdata struct samsung_pll_rate_table vpll_24mhz_tbl[] = {
+ /* sorted in descending order */
+ /* PLL_36XX_RATE(rate, m, p, s, k) */
+ PLL_36XX_RATE(26600, 266, 3, 3, 0),
+ /* Not in UM, but need for eDP on snow */
+ PLL_36XX_RATE(7050, 94, 2, 4, 0),
+};
+
+static __initdata struct samsung_pll_rate_table epll_24mhz_tbl[] = {
+ /* sorted in descending order */
+ /* PLL_36XX_RATE(rate, m, p, s, k) */
+ PLL_36XX_RATE(19200, 48, 3, 1, 0),
+ PLL_36XX_RATE(180633600, 45, 3, 1, 10381),
+ PLL_36XX_RATE(18000, 45, 3, 1, 0),
+ PLL_36XX_RATE(73728000, 73, 3, 3, 47710),
+ PLL_36XX_RATE(67737600, 90, 4, 3, 20762),
+ PLL_36XX_RATE(49152000, 49, 3, 3, 9962),
+ PLL_36XX_RATE(45158400, 45, 3, 3, 10381),
+ PLL_36XX_RATE(32768000, 131, 3, 5, 4719),
+};
+
/* register exynox5250 clocks */
void __init exynos5250_clk_init(struct device_node *np)
{
void __iomem *reg_base;
struct clk *apll, *mpll, *epll, *vpll, *bpll, *gpll, *cpll;
+ struct clk *vpllsrc;
+ unsigned long fin_pll_rate, mout_vpllsrc_rate = 0;
if (np) {
reg_base = of_iomap(np, 0);
@@ -496,6 +519,11 @@ void __init exynos5250_clk_init(struct device_node *np)
samsung_clk_register_mux(exynos5250_pll_pmux_clks,
ARRAY_SIZE(exynos5250_pll_pmux_clks));
+ fin_pll_rate = _get_rate(fin_pll);
+ vpllsrc = __clk_lookup(mout_vpllsrc);
+ if (vpllsrc)
+ mout_vpllsrc_rate = clk_get_rate(vpllsrc);
+
apll = samsung_clk_register_pll35xx(fout_apll, fin_pll,
reg_base, NULL, 0);
mpll = samsung_clk_register_pll35xx(fout_mpll, fin_pll,
@@ -506,10 +534,29 @@ void __init exynos5250_clk_init(struct device_node *np)
reg_base + 0x10050, NULL, 0);
cpll = samsung_clk_register_pll35xx(fout_cpll, fin_pll,
reg_base + 0x10020, NULL, 0);
- epll = samsung_clk_register_pll36xx(fout_epll, fin_pll,
- reg_base + 0x10030, NULL, 0);
- vpll = samsung_clk_register_pll36xx(fout_vpll, mout_vpllsrc,
+
+ if (fin_pll_rate == (24 * MHZ)) {
+ epll = samsung_clk_register_pll36xx(fout_epll, fin_pll,
+ reg_base + 0x10030, epll_24mhz_tbl,
+ ARRAY_SIZE(epll_24mhz_tbl));
+ } else {
+ pr_warn(%s: valid epll rate_table missing for\n
+ parent fin_pll:%lu hz\n, __func__, fin_pll_rate);
It seems like we could just have a warning once at the top of this
file. ...and since we think nobody has designed a 5250 with a 26MHz
input clock we could even just consider it an error at the moment to
avoid adding a bunch of code.
You could also avoid all of these if statements with a level of indirection.
enum {
EPLL, VPLL
};
samsung_pll_rate_table *plls_24mhz[] = { epll_24mhz_tbl, vpll_24mhz_tbl };
samsung_pll_rate_table *plls_default[] = { };
...of course you'd need a parallel table for sizes. That does suggest
that Tomasz's thought of terminating the list with a sentinal would be
cleaner.
-Doug
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Re: [PATCH 1/3] ARM: dts: add pinctrl support to Exynos5420
Hi Leela Krishna,
On Wednesday 12 of June 2013 20:21:26 Leela Krishna Amudala wrote:
Add the required pin configuration support to Exynos5420 using pinctrl
interface.
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
---
arch/arm/boot/dts/exynos5420-pinctrl.dtsi | 680
+ arch/arm/boot/dts/exynos5420.dtsi
| 45 ++
2 files changed, 725 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5420-pinctrl.dtsi
diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi new file mode 100644
index 000..23b7521
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
@@ -0,0 +1,680 @@
+/*
+ * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed
as device + * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as +
* published by the Free Software Foundation.
+*/
+
+/ {
+ pinctrl@1340 {
+ gpy7: gpy7 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
According to patch 2/3, this bank doesn't support interrupts, as it's
defined using EINTN macro. Which variant is correct?
+ };
+
+ gpx0: gpx0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ interrupt-parent = combiner;
+ #interrupt-cells = 2;
+ interrupts = 23 0, 24 0, 25 0, 25 1,
+ 26 0, 26 1, 27 0, 27 1;
+ };
+
+ gpx1: gpx1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ interrupt-parent = combiner;
+ #interrupt-cells = 2;
+ interrupts = 28 0, 28 1, 29 0, 29 1,
+ 30 0, 30 1, 31 0, 31 1;
+ };
+
+ gpx2: gpx2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpx3: gpx3 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+ };
+
+ pinctrl@1341 {
+ gpc0: gpc0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpc1: gpc1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpc2: gpc2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpc3: gpc3 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpc4: gpc4 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpy0: gpy0 {
+ gpio-controller;
+ #gpio-cells = 2;
+ };
+
+ gpy1: gpy1 {
+ gpio-controller;
+ #gpio-cells = 2;
+ };
+
+ gpy2: gpy2 {
+ gpio-controller;
+ #gpio-cells = 2;
+ };
+
+ gpy3: gpy3 {
+ gpio-controller;
+ #gpio-cells = 2;
+ };
+
+ gpy4: gpy4 {
+ gpio-controller;
+ #gpio-cells = 2;
+ };
+
+ gpy5: gpy5 {
+ gpio-controller;
+ #gpio-cells = 2;
+ };
+
+ gpy6: gpy6 {
+
Re: [PATCH 2/3] pinctrl: exynos: add exynos5420 SoC specific data
Hi Leela Krishna,
On Wednesday 12 of June 2013 20:21:27 Leela Krishna Amudala wrote:
Add Samsung Exynos5420 SoC specific data to enable pinctrl support for
all platforms based on Exynos5420.
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
---
.../bindings/pinctrl/samsung-pinctrl.txt |1 +
drivers/pinctrl/pinctrl-exynos.c | 115
drivers/pinctrl/pinctrl-samsung.c
|2 +
drivers/pinctrl/pinctrl-samsung.h |1 +
4 files changed, 119 insertions(+)
Looks good to me.
Reviewed-by: Tomasz Figa t.f...@samsung.com
Best regards,
Tomasz
diff --git
a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt index
b2bc219..fe949c7 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -15,6 +15,7 @@ Required Properties:
- samsung,exynos4210-pinctrl: for Exynos4210 compatible
pin-controller. - samsung,exynos4x12-pinctrl: for Exynos4x12
compatible pin-controller. - samsung,exynos5250-pinctrl: for
Exynos5250 compatible pin-controller. + -
samsung,exynos5420-pinctrl: for Exynos5420 compatible pin-controller.
- reg: Base address of the pin controller hardware module and length of
the address space it occupies.
diff --git a/drivers/pinctrl/pinctrl-exynos.c
b/drivers/pinctrl/pinctrl-exynos.c index 2d76f66..753a8cd 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -941,3 +941,118 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
.label = exynos5250-gpio-ctrl3,
},
};
+
+/* pin banks of exynos5420 pin-controller 0 */
+static struct samsung_pin_bank exynos5420_pin_banks0[] = {
+ EXYNOS_PIN_BANK_EINTN(8, 0x000, gpy7),
+ EXYNOS_PIN_BANK_EINTW(8, 0xC00, gpx0, 0x00),
+ EXYNOS_PIN_BANK_EINTW(8, 0xC20, gpx1, 0x04),
+ EXYNOS_PIN_BANK_EINTW(8, 0xC40, gpx2, 0x08),
+ EXYNOS_PIN_BANK_EINTW(8, 0xC60, gpx3, 0x0c),
+};
+
+/* pin banks of exynos5420 pin-controller 1 */
+static struct samsung_pin_bank exynos5420_pin_banks1[] = {
+ EXYNOS_PIN_BANK_EINTG(8, 0x000, gpc0, 0x00),
+ EXYNOS_PIN_BANK_EINTG(8, 0x020, gpc1, 0x04),
+ EXYNOS_PIN_BANK_EINTG(7, 0x040, gpc2, 0x08),
+ EXYNOS_PIN_BANK_EINTG(4, 0x060, gpc3, 0x0c),
+ EXYNOS_PIN_BANK_EINTG(2, 0x080, gpc4, 0x10),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0A0, gpd1, 0x14),
+ EXYNOS_PIN_BANK_EINTN(6, 0x0C0, gpy0),
+ EXYNOS_PIN_BANK_EINTN(4, 0x0E0, gpy1),
+ EXYNOS_PIN_BANK_EINTN(6, 0x100, gpy2),
+ EXYNOS_PIN_BANK_EINTN(8, 0x120, gpy3),
+ EXYNOS_PIN_BANK_EINTN(8, 0x140, gpy4),
+ EXYNOS_PIN_BANK_EINTN(8, 0x160, gpy5),
+ EXYNOS_PIN_BANK_EINTN(8, 0x180, gpy6),
+};
+
+/* pin banks of exynos5420 pin-controller 2 */
+static struct samsung_pin_bank exynos5420_pin_banks2[] = {
+ EXYNOS_PIN_BANK_EINTG(8, 0x000, gpe0, 0x00),
+ EXYNOS_PIN_BANK_EINTG(2, 0x020, gpe1, 0x04),
+ EXYNOS_PIN_BANK_EINTG(6, 0x040, gpf0, 0x08),
+ EXYNOS_PIN_BANK_EINTG(8, 0x060, gpf1, 0x0c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x080, gpg0, 0x10),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0A0, gpg1, 0x14),
+ EXYNOS_PIN_BANK_EINTG(2, 0x0C0, gpg2, 0x18),
+ EXYNOS_PIN_BANK_EINTG(4, 0x0E0, gpj4, 0x1c),
+};
+
+/* pin banks of exynos5420 pin-controller 3 */
+static struct samsung_pin_bank exynos5420_pin_banks3[] = {
+ EXYNOS_PIN_BANK_EINTG(8, 0x000, gpa0, 0x00),
+ EXYNOS_PIN_BANK_EINTG(6, 0x020, gpa1, 0x04),
+ EXYNOS_PIN_BANK_EINTG(8, 0x040, gpa2, 0x08),
+ EXYNOS_PIN_BANK_EINTG(5, 0x060, gpb0, 0x0c),
+ EXYNOS_PIN_BANK_EINTG(5, 0x080, gpb1, 0x10),
+ EXYNOS_PIN_BANK_EINTG(4, 0x0A0, gpb2, 0x14),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0C0, gpb3, 0x18),
+ EXYNOS_PIN_BANK_EINTG(2, 0x0E0, gpb4, 0x1c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x100, gph0, 0x20),
+};
+
+/* pin banks of exynos5420 pin-controller 4 */
+static struct samsung_pin_bank exynos5420_pin_banks4[] = {
+ EXYNOS_PIN_BANK_EINTG(8, 0x000, gpz, 0x00),
+};
+
+/*
+ * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC
includes + * four gpio/pin-mux/pinconfig controllers.
+ */
+struct samsung_pin_ctrl exynos5420_pin_ctrl[] = {
+ {
+ /* pin-controller instance 0 data */
+ .pin_banks = exynos5420_pin_banks0,
+ .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0),
+ .weint_con = EXYNOS_WKUP_ECON_OFFSET,
+ .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
+ .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
+ .svc= EXYNOS_SVC_OFFSET,
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .eint_wkup_init = exynos_eint_wkup_init,
+ .label = exynos5420-gpio-ctrl0,
+ }, {
+ /* pin-controller instance 1 data */
+
Re: [PATCH 3/3] gpio: samsung: skip gpiolib registration if pinctrl support is enabled for exynos5420
On Wednesday 12 of June 2013 20:21:28 Leela Krishna Amudala wrote:
Skip exynos5420 gpiolib registration if pinctrl support is enabled.
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
---
drivers/gpio/gpio-samsung.c |1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index 83a0d71..b3dd984 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -3033,6 +3033,7 @@ static __init int samsung_gpiolib_init(void)
{ .compatible = samsung,exynos4210-pinctrl, },
{ .compatible = samsung,exynos4x12-pinctrl, },
{ .compatible = samsung,exynos5250-pinctrl, },
+ { .compatible = samsung,exynos5420-pinctrl, },
{ .compatible = samsung,exynos5440-pinctrl, },
IMHO after Kukjin's patches removing non-DT support for Exynos, we can
just remove Exynos support from this legacy driver. I will send
appropriate patch this Friday, along with other cleanup patches.
Best regards,
Tomasz
{ }
};
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Re: [PATCH v4 3/6] clk: samsung: Add set_rate() clk_ops for PLL35xx
On Monday 03 of June 2013 20:39:53 Yadwinder Singh Brar wrote:
This patch add set_rate() and round_rate() for PLL35xx
Reviewed-by: Doug Anderson diand...@chromium.org
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
---
drivers/clk/samsung/clk-pll.c | 104
- 1 files changed, 103
insertions(+), 1 deletions(-)
diff --git a/drivers/clk/samsung/clk-pll.c
b/drivers/clk/samsung/clk-pll.c index cba73a4..319b52b 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -27,6 +27,37 @@ struct samsung_clk_pll {
#define pll_writel(pll, val, offset) \
__raw_writel(val, (void __iomem *)(pll-base + (offset)));
+static const struct samsung_pll_rate_table *samsung_get_pll_settings(
+ struct samsung_clk_pll *pll, unsigned long
rate)
+{
+ const struct samsung_pll_rate_table *rate_table = pll-
rate_table;
+ int i;
+
+ for (i = 0; i pll-rate_count; i++) {
+ if (rate == rate_table[i].rate)
+ return rate_table[i];
+ }
+
+ return NULL;
+}
+
+static long samsung_pll_round_rate(struct clk_hw *hw,
+ unsigned long drate, unsigned long *prate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ const struct samsung_pll_rate_table *rate_table = pll-rate_table;
+ int i;
+
+ /* Assumming rate_table is in descending order */
+ for (i = 0; i pll-rate_count; i++) {
+ if (drate = rate_table[i].rate)
+ return rate_table[i].rate;
+ }
+
+ /* return minimum supported value */
+ return rate_table[i - 1].rate;
+}
+
/*
* PLL35xx Clock Type
*/
@@ -34,12 +65,17 @@ struct samsung_clk_pll {
#define PLL35XX_CON0_OFFSET (0x100)
#define PLL35XX_CON1_OFFSET (0x104)
+/* Maximum lock time can be 270 * PDIV cycles */
+#define PLL35XX_LOCK_FACTOR (270)
+
#define PLL35XX_MDIV_MASK (0x3FF)
#define PLL35XX_PDIV_MASK (0x3F)
#define PLL35XX_SDIV_MASK (0x7)
+#define PLL35XX_LOCK_STAT_MASK (0x1)
#define PLL35XX_MDIV_SHIFT (16)
#define PLL35XX_PDIV_SHIFT (8)
#define PLL35XX_SDIV_SHIFT (0)
+#define PLL35XX_LOCK_STAT_SHIFT (29)
static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
@@ -59,8 +95,72 @@ static unsigned long
samsung_pll35xx_recalc_rate(struct clk_hw *hw, return (unsigned
long)fvco;
}
+static inline bool samsung_pll35xx_mp_change(
+ const struct samsung_pll_rate_table *rate, u32 pll_con)
+{
+ u32 old_mdiv, old_pdiv;
+
+ old_mdiv = (pll_con PLL35XX_MDIV_SHIFT) PLL35XX_MDIV_MASK;
+ old_pdiv = (pll_con PLL35XX_PDIV_SHIFT) PLL35XX_PDIV_MASK;
+
+ return (rate-mdiv != old_mdiv || rate-pdiv != old_pdiv);
+}
+
+static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long
drate, + unsigned long prate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ const struct samsung_pll_rate_table *rate;
+ u32 tmp;
+
+ /* Get required rate settings from table */
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err(%s: Invalid rate : %lu for pll clk %s\n,
__func__,
+ drate, __clk_get_name(hw-clk));
+ return -EINVAL;
+ }
+
+ tmp = pll_readl(pll, PLL35XX_CON0_OFFSET);
+
+ if (!(samsung_pll35xx_mp_change(rate, tmp))) {
+ /* If only s change, change just s value only*/
+ tmp = ~(PLL35XX_SDIV_MASK PLL35XX_SDIV_SHIFT);
+ tmp |= rate-sdiv PLL35XX_SDIV_SHIFT;
+ pll_writel(pll, tmp, PLL35XX_CON0_OFFSET);
I'd use the same coding style here as in case of PLL36xx, i.e. add return
0 and move following code outside else.
This makes the code a bit more linear and lowers indentation level.
Otherwise looks good.
Reviewed-by: Tomasz Figa t.f...@samsung.com
Best regards,
Tomasz
+ } else {
+ /* Set PLL lock time. */
+ pll_writel(pll, rate-pdiv * PLL35XX_LOCK_FACTOR,
+ PLL35XX_LOCK_OFFSET);
+
+ /* Change PLL PMS values */
+ tmp = ~((PLL35XX_MDIV_MASK PLL35XX_MDIV_SHIFT) |
+ (PLL35XX_PDIV_MASK PLL35XX_PDIV_SHIFT)
|
+ (PLL35XX_SDIV_MASK
PLL35XX_SDIV_SHIFT));
+ tmp |= (rate-mdiv PLL35XX_MDIV_SHIFT) |
+ (rate-pdiv PLL35XX_PDIV_SHIFT) |
+ (rate-sdiv PLL35XX_SDIV_SHIFT);
+ pll_writel(pll, tmp, PLL35XX_CON0_OFFSET);
+
+ /* wait_lock_time */
+ do {
+ cpu_relax();
+ tmp = pll_readl(pll, PLL35XX_CON0_OFFSET);
+ } while (!(tmp
Re: [PATCH v4 4/6] clk: samsung: Add set_rate() clk_ops for PLL36xx
Hi Yadwinder, Vikas,
On Monday 03 of June 2013 20:39:54 Yadwinder Singh Brar wrote:
From: Vikas Sajjan vikas.saj...@linaro.org
This patch adds set_rate and round_rate clk_ops for PLL36xx
Reviewed-by: Tomasz Figa t.f...@samsung.com
Reviewed-by: Doug Anderson diand...@chromium.org
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
---
drivers/clk/samsung/clk-pll.c | 79
- 1 files changed, 78
insertions(+), 1 deletions(-)
diff --git a/drivers/clk/samsung/clk-pll.c
b/drivers/clk/samsung/clk-pll.c index 319b52b..42b60b5 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -215,6 +215,9 @@ struct clk * __init
samsung_clk_register_pll35xx(const char *name, #define
PLL36XX_CON0_OFFSET (0x100)
#define PLL36XX_CON1_OFFSET (0x104)
+/* Maximum lock time can be 3000 * PDIV cycles */
+#define PLL36XX_LOCK_FACTOR (3000)
+
#define PLL36XX_KDIV_MASK(0x)
#define PLL36XX_MDIV_MASK(0x1FF)
#define PLL36XX_PDIV_MASK(0x3F)
@@ -222,6 +225,8 @@ struct clk * __init
samsung_clk_register_pll35xx(const char *name, #define
PLL36XX_MDIV_SHIFT(16)
#define PLL36XX_PDIV_SHIFT (8)
#define PLL36XX_SDIV_SHIFT (0)
+#define PLL36XX_KDIV_SHIFT (0)
+#define PLL36XX_LOCK_STAT_SHIFT (29)
static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
@@ -244,8 +249,78 @@ static unsigned long
samsung_pll36xx_recalc_rate(struct clk_hw *hw, return (unsigned
long)fvco;
}
+static inline bool samsung_pll36xx_mpk_change(
+ const struct samsung_pll_rate_table *rate, u32 pll_con0, u32
pll_con1)
+{
+ u32 old_mdiv, old_pdiv, old_kdiv;
+
+ old_mdiv = (pll_con0 PLL36XX_MDIV_SHIFT) PLL36XX_MDIV_MASK;
+ old_pdiv = (pll_con0 PLL36XX_PDIV_SHIFT) PLL36XX_PDIV_MASK;
+ old_kdiv = (pll_con1 PLL36XX_KDIV_SHIFT) PLL36XX_KDIV_MASK;
+
+ return (rate-mdiv != old_mdiv || rate-pdiv != old_pdiv ||
+ rate-kdiv != old_kdiv);
+}
+
+static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long
drate, + unsigned long parent_rate)
+{
+ struct samsung_clk_pll *pll = to_clk_pll(hw);
+ u32 tmp, pll_con0, pll_con1;
+ const struct samsung_pll_rate_table *rate;
+
+ rate = samsung_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err(%s: Invalid rate : %lu for pll clk %s\n,
__func__,
+ drate, __clk_get_name(hw-clk));
+ return -EINVAL;
+ }
+
+ pll_con0 = pll_readl(pll, PLL36XX_CON0_OFFSET);
+ pll_con1 = pll_readl(pll, PLL36XX_CON1_OFFSET);
+
+ if (!(samsung_pll36xx_mpk_change(rate, pll_con0, pll_con1))) {
+ /* If only s change, change just s value only*/
+ pll_con0 = ~(PLL36XX_SDIV_MASK PLL36XX_SDIV_SHIFT);
+ pll_con0 |= (rate-sdiv PLL36XX_SDIV_SHIFT);
+ pll_writel(pll, pll_con0, PLL36XX_CON0_OFFSET);
nit, I would put an empty line before the return statement here, to make
it stand out a bit more.
Otherwise looks fine for me.
Reviewed-by: Tomasz Figa t.f...@samsung.com
Best regards,
Tomasz
+ return 0;
+ }
+
+ /* Set PLL lock time. */
+ pll_writel(pll, (rate-pdiv * PLL36XX_LOCK_FACTOR),
+ PLL36XX_LOCK_OFFSET);
+
+ /* Change PLL PMS values */
+ pll_con0 = ~((PLL36XX_MDIV_MASK PLL36XX_MDIV_SHIFT) |
+ (PLL36XX_PDIV_MASK PLL36XX_PDIV_SHIFT) |
+ (PLL36XX_SDIV_MASK PLL36XX_SDIV_SHIFT));
+ pll_con0 |= (rate-mdiv PLL36XX_MDIV_SHIFT) |
+ (rate-pdiv PLL36XX_PDIV_SHIFT) |
+ (rate-sdiv PLL36XX_SDIV_SHIFT);
+ pll_writel(pll, pll_con0, PLL36XX_CON0_OFFSET);
+
+ pll_con1 = ~(PLL36XX_KDIV_MASK PLL36XX_KDIV_SHIFT);
+ pll_con1 |= rate-kdiv PLL36XX_KDIV_SHIFT;
+ pll_writel(pll, pll_con1, PLL36XX_CON1_OFFSET);
+
+ /* wait_lock_time */
+ do {
+ cpu_relax();
+ tmp = pll_readl(pll, PLL36XX_CON0_OFFSET);
+ } while (!(tmp (1 PLL36XX_LOCK_STAT_SHIFT)));
+
+ return 0;
+}
+
static const struct clk_ops samsung_pll36xx_clk_ops = {
.recalc_rate = samsung_pll36xx_recalc_rate,
+ .set_rate = samsung_pll36xx_set_rate,
+ .round_rate = samsung_pll_round_rate,
+};
+
+static const struct clk_ops samsung_pll36xx_clk_min_ops = {
+ .recalc_rate = samsung_pll36xx_recalc_rate,
};
struct clk * __init samsung_clk_register_pll36xx(const char *name,
@@ -264,7 +339,6 @@ struct clk * __init
samsung_clk_register_pll36xx(const char *name, }
init.name = name;
- init.ops = samsung_pll36xx_clk_ops;
init.flags = CLK_GET_RATE_NOCACHE;
init.parent_names = pname;
init.num_parents = 1;
@@ -273,6 +347,9 @@ struct clk * __init
samsung_clk_register_pll36xx(const char *name,
Re: [PATCH v4 5/6] clk: samsung: Reorder MUX registration for mout_vpllsrc
On Monday 03 of June 2013 20:39:55 Yadwinder Singh Brar wrote:
From: Vikas Sajjan vikas.saj...@linaro.org
While trying to get rate of mout_vpllsrc MUX (parent) for registering
the fout_vpll (child), we found get rate was failing.
So this patch moves the mout_vpllsrc MUX out of the existing common list
and registers the mout_vpllsrc MUX before the PLL registrations.
Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
---
drivers/clk/samsung/clk-exynos5250.c |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
Reviewed-by: Tomasz Figa t.f...@samsung.com
Best regards,
Tomasz
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c index ddf10ca..70cc6cf 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -207,6 +207,10 @@ struct samsung_fixed_factor_clock
exynos5250_fixed_factor_clks[] __initdata = { FFACTOR(none,
fout_bplldiv2, fout_bpll, 1, 2, 0),
};
+struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = {
+ MUX(none, mout_vpllsrc, mout_vpllsrc_p, SRC_TOP2, 0, 1),
+};
+
struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
MUX(none, mout_apll, mout_apll_p, SRC_CPU, 0, 1),
MUX(none, mout_cpu, mout_cpu_p, SRC_CPU, 16, 1),
@@ -214,7 +218,6 @@ struct samsung_mux_clock exynos5250_mux_clks[]
__initdata = { MUX(none, sclk_mpll, mout_mpll_p, SRC_CORE1, 8, 1),
MUX(none, mout_bpll_fout, mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
MUX(none, sclk_bpll, mout_bpll_p, SRC_CDREX, 0, 1),
- MUX(none, mout_vpllsrc, mout_vpllsrc_p, SRC_TOP2, 0, 1),
MUX(none, sclk_vpll, mout_vpll_p, SRC_TOP2, 16, 1),
MUX(none, sclk_epll, mout_epll_p, SRC_TOP2, 12, 1),
MUX(none, sclk_cpll, mout_cpll_p, SRC_TOP2, 8, 1),
@@ -490,6 +493,9 @@ void __init exynos5250_clk_init(struct device_node
*np) ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
ext_clk_match);
+ samsung_clk_register_mux(exynos5250_pll_pmux_clks,
+ ARRAY_SIZE(exynos5250_pll_pmux_clks));
+
apll = samsung_clk_register_pll35xx(fout_apll, fin_pll,
reg_base, NULL, 0);
mpll = samsung_clk_register_pll35xx(fout_mpll, fin_pll,
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Re: [PATCH 09/13] clk: exynos5420: register clocks using common clock framework
Hi Chander, One more thing inline. On Thursday 06 of June 2013 16:31:23 Chander Kashyap wrote: The Exynos5420 clocks are statically listed and registered using the Samsung specific common clock helper functions. Signed-off-by: Chander Kashyap chander.kash...@linaro.org Signed-off-by: Thomas Abraham thomas.abra...@linaro.org --- .../devicetree/bindings/clock/exynos5420-clock.txt | 201 ++ drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos5420.c | 762 3 files changed, 964 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/exynos5420-clock.txt create mode 100644 drivers/clk/samsung/clk-exynos5420.c diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt new file mode 100644 index 000..72d25fc --- /dev/null +++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt @@ -0,0 +1,201 @@ +* Samsung Exynos5420 Clock Controller + +The Exynos5420 clock controller generates and supplies clock to various +controllers within the Exynos5420 SoC. + +Required Properties: + +- comptible: should be one of the following. + - samsung,exynos5420-clock - controller compatible with Exynos5420 SoC. + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +The following is the list of clocks generated by the controller. Each clock is +assigned an identifier and client nodes use this identifier to specify the +clock which they consume. + + + [Core Clocks] + + Clock ID + + + oscclk 1 + + [Clock Gate for Special Clocks] + + Clock ID + + sclk_uart0 128 + sclk_uart1 129 + sclk_uart2 130 + sclk_uart3 131 + sclk_mmc0 132 + sclk_mmc1 132 + sclk_mmc2 133 + sclk_spi0 134 + sclk_spi1 135 + sclk_spi2 136 + sclk_i2s1 137 + sclk_i2s2 138 + sclk_pcm1 139 + sclk_pcm2 140 + sclk_spdif 141 + sclk_hdmi 142 + sclk_pixel 143 + sclk_dp1 144 + sclk_mipi1 145 + sclk_fimd1 146 + sclk_maudio0 147 + sclk_maupcm0 148 + sclk_usbd300 149 + sclk_usbd301 150 + sclk_usbphy300 151 + sclk_usbphy301 152 + sclk_unipro153 + sclk_pwm 154 + sclk_gscl_wa 155 + sclk_gscl_wb 156 + + [Peripheral Clock Gates] + + Clock ID + + + aclk66_peric 256 + uart0 257 + uart1 258 + uart2 259 + uart3 260 + i2c0 261 + i2c1 262 + i2c2 263 + i2c3 264 + i2c4 265 + i2c5 266 + i2c6 267 + i2c7 268 + i2c_hdmi 269 + tsadc 270 + spi0 271 + spi1 272 + spi2 273 + keyif 274 + i2s1 275 + i2s2 276 + pcm1 277 + pcm2 278 + pwm279 + spdif 280 + i2c8 281 + i2c9 282 + i2c10 283 + aclk66_psgen 300 + chipid 301 + sysreg 302 + tzpc0 303 + tzpc1 304 + tzpc2 305 + tzpc3 306 + tzpc4 307 + tzpc5 308 + tzpc6 309 + tzpc7 310 + tzpc8 311 + tzpc9 312 + hdmi_cec 313 + seckey 314 + mct315 + wdt316 + rtc317 + tmu318 + tmu_gpu319 + pclk66_gpio330 + aclk200_fsys2 350 + mmc0 351 + mmc1 352 + mmc2 353 + sromc 354 + ufs355 + aclk200_fsys 360 + tsi361 + pdma0 362 + pdma1 363 + rtic 364 + usbh20 365 + usbd300366 + usbd301377 + aclk400_mscl
Re: [PATCH v4 1/6] clk: samsung: Use clk-base instead of directly using clk-con0 for PLL3xxx
Hi,
On Wednesday 12 of June 2013 13:33:50 Doug Anderson wrote:
Yadwinder,
On Mon, Jun 3, 2013 at 8:09 AM, Yadwinder Singh Brar
yadi.b...@samsung.com wrote:
This patch unifies clk strutures used for PLL35xx PLL36xx and uses
clk-base instead of directly using clk-con0, so that possible
common code can be factored out.
It also introdues common pll_[readl/writel] macros for the users of
common samsung_clk_pll struct.
Reviewed-by: Tomasz Figa t.f...@samsung.com
Reviewed-by: Doug Anderson diand...@chromium.org
Tested-by: Doug Anderson diand...@chromium.org
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c| 10 --
drivers/clk/samsung/clk-exynos5250.c | 14
drivers/clk/samsung/clk-pll.c| 54
++--- drivers/clk/samsung/clk-pll.h
|4 +-
4 files changed, 44 insertions(+), 38 deletions(-)
So. We just found that this type of solution doesn't work on
exynos5420, since the LOCK and CON registers aren't always 0x100 away
from each other.
Oops, this is what I've been afraid of, ever since we assumed this first
time in our internal patches.
Perhaps you can adjust to use a solution like Andrew
proposed in https://gerrit.chromium.org/gerrit/#/c/58411/? That way
we can avoid some churn of changing this code twice.
The number of parameters to the register PLL function is starting to
get unwieldy. At some point we'll probably want to pass in a
structure. I wonder if now would be the time? Certainly it would be
easier to handle changes to the code without touching all of the
exynos variants...
Hmm, if done properly, it could simplify PLL registration in SoC clock
initialization code a lot.
I'm not sure if this is really the best solution (feel free to suggest
anything better), but we could put PLLs in an array, like other clocks,
e.g.
... exynos4210_pll_clks[] = {
CLK_PLL45XX(...),
CLK_PLL45XX(...),
CLK_PLL46XX(...),
CLK_PLL46XX(...),
};
and then just call a helper like
samsung_clk_register_pll(exynos4210_pll_clks,
ARRAY_SIZE(exynos4210_pll_clks));
Best regards,
Tomasz
Thanks!
-Doug
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Re: [PATCH 1/3] ARM: dts: add pinctrl support to Exynos5420
Tomasz,
On Wed, Jun 12, 2013 at 1:58 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
+ pinctrl@1340 {
+ gpy7: gpy7 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
According to patch 2/3, this bank doesn't support interrupts, as it's
defined using EINTN macro. Which variant is correct?
As far as I know the GPY registers don't support interrupts, so this
should be removed. Nice catch!
+ sd0_bus1: sd0-bus-width1 {
+ samsung,pins = gpc0-3;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 3;
+ samsung,pin-drv = 3;
+ };
+
+ sd0_bus4: sd0-bus-width4 {
+ samsung,pins = gpc0-3, gpc0-4, gpc0-5,
gpc0-6;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 3;
+ samsung,pin-drv = 3;
+ };
+
+ sd0_bus8: sd0-bus-width8 {
+ samsung,pins = gpc3-0, gpc3-1, gpc3-2,
gpc3-3;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 3;
+ samsung,pin-drv = 3;
+ };
It seems like there is some inconsequence here, because sd0_bus4 setting
includes pins of sd0_bus1, while sd0_bus8 doesn't include pins of
sd0_bus4.
I think it should be defined either first or second way, not mixed, but I
don't have any strong preference over any of them.
CCing some people to hopefully get some more opinion on this.
Yeah, I brought this up on 5250, but somehow it looks like it landed
without getting changed. I agree it should be one way or the other.
Feel free to add my Reviewed-by. The differences between the code you
sent up and our ToT are:
* You properly set the i2c4 drive strength to 0 to match all others.
* You don't yet have the HDMI hot plug detect IRQ defined. ...but
that looks slightly wrong in our tree anyway and can be added later.
Reviewed-by: Doug Anderson diand...@chromium.org
-Doug
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Re: [PATCH v4 2/6] clk: samsung: Add support to register rate_table for PLL3xxx
Hi Doug,
On Wednesday 12 of June 2013 13:43:37 Doug Anderson wrote:
Yadwinder,
On Mon, Jun 3, 2013 at 8:09 AM, Yadwinder Singh Brar
yadi.b...@samsung.com wrote:
This patch defines a common rate_table which will contain recommended
p, m, s, k values for supported rates that needs to be changed for
changing corresponding PLL's rate.
Reviewed-by: Doug Anderson diand...@chromium.org
Signed-off-by: Yadwinder Singh Brar yadi.b...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c|8 +++---
drivers/clk/samsung/clk-exynos5250.c | 14 ++--
drivers/clk/samsung/clk-pll.c| 22 +++-
drivers/clk/samsung/clk-pll.h| 35
- 4 files changed, 64 insertions(+),
15 deletions(-)
Using something like patman
http://git.denx.de/?p=u-boot.git;a=blob;f=tools/patman/README;hb=refs/h
eads/master would really help here so you could get some version
history. I see it in 0/6 but that's a bit of a pain...
Did you and Tomasz ever come to an agreement about whether the fin
freq needs to be specified with the PMSK values?
No, not really.
But since
a) there seems to be no input from hardware guys,
b) we want to have this series merged,
c) otherwise this patch looks good
I think for now we can keep support for single input rate.
However, I think it would be resonable to recalculate all the output rates
from PLL equation at registration stage anyway just to eliminate any typos
or other errors in setting table, otherwise you might end up with having
different rate set in the PLL and different assumed by the driver.
Best regards,
Tomasz
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c index ba33bc6..e02a342 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1028,13 +1028,13 @@ void __init exynos4_clk_init(struct
device_node *np, enum exynos4_soc exynos4_so
reg_base + VPLL_CON0,
pll_4650c);
} else {
apll = samsung_clk_register_pll35xx(fout_apll,
fin_pll,
- reg_base + APLL_LOCK);
+ reg_base + APLL_LOCK, NULL,
0);
mpll = samsung_clk_register_pll35xx(fout_mpll,
fin_pll,
- reg_base + E4X12_MPLL_LOCK);
+ reg_base + E4X12_MPLL_LOCK,
NULL, 0);
epll = samsung_clk_register_pll36xx(fout_epll,
fin_pll,
- reg_base + EPLL_LOCK);
+ reg_base + EPLL_LOCK, NULL,
0);
vpll = samsung_clk_register_pll36xx(fout_vpll,
fin_pll,
- reg_base + VPLL_LOCK);
+ reg_base + VPLL_LOCK, NULL,
0);
}
samsung_clk_add_lookup(apll, fout_apll);
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c index 687b580..ddf10ca 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -491,19 +491,19 @@ void __init exynos5250_clk_init(struct
device_node *np)
ext_clk_match);
apll = samsung_clk_register_pll35xx(fout_apll, fin_pll,
- reg_base);
+ reg_base, NULL, 0);
mpll = samsung_clk_register_pll35xx(fout_mpll, fin_pll,
- reg_base + 0x4000);
+ reg_base + 0x4000, NULL, 0);
bpll = samsung_clk_register_pll35xx(fout_bpll, fin_pll,
- reg_base + 0x20010);
+ reg_base + 0x20010, NULL, 0);
gpll = samsung_clk_register_pll35xx(fout_gpll, fin_pll,
- reg_base + 0x10050);
+ reg_base + 0x10050, NULL, 0);
cpll = samsung_clk_register_pll35xx(fout_cpll, fin_pll,
- reg_base + 0x10020);
+ reg_base + 0x10020, NULL, 0);
epll = samsung_clk_register_pll36xx(fout_epll, fin_pll,
- reg_base + 0x10030);
+ reg_base + 0x10030, NULL, 0);
vpll = samsung_clk_register_pll36xx(fout_vpll,
mout_vpllsrc,
- reg_base + 0x10040);
+ reg_base + 0x10040, NULL, 0);
samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
ARRAY_SIZE(exynos5250_fixed_rate_clks));
diff --git a/drivers/clk/samsung/clk-pll.c
b/drivers/clk/samsung/clk-pll.c index a7d8ad9..cba73a4
Re: [PATCH 09/13] clk: exynos5420: register clocks using common clock framework
Tomasz, + apll = samsung_clk_register_pll35xx(fout_apll, oscclk, + reg_base + 0x100); + bpll = samsung_clk_register_pll35xx(fout_bpll, oscclk, + reg_base + 0x20110); + cpll = samsung_clk_register_pll35xx(fout_cpll, oscclk, + reg_base + 0x10120); + dpll = samsung_clk_register_pll35xx(fout_dpll, oscclk, + reg_base + 0x10128); + epll = samsung_clk_register_pll35xx(fout_epll, oscclk, + reg_base + 0x10130); + ipll = samsung_clk_register_pll35xx(fout_ipll, oscclk, + reg_base + 0x10150); + kpll = samsung_clk_register_pll35xx(fout_kpll, oscclk, + reg_base + 0x28100); + mpll = samsung_clk_register_pll35xx(fout_mpll, oscclk, + reg_base + 0x10180); + rpll = samsung_clk_register_pll35xx(fout_rpll, oscclk, + reg_base + 0x10140); + spll = samsung_clk_register_pll35xx(fout_spll, oscclk, + reg_base + 0x10160); + vpll = samsung_clk_register_pll35xx(fout_vpll, oscclk, + reg_base + 0x10170); Are all those PLLs really PLL35xx? At least for VPLL and EPLL a PLL without the K factor looks a bit awkward. No they are not... EPLL and RPLL should be pll36xx, but the rest are pll35xx. Thanks, Andrew -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3] ARM: dts: add pinctrl support to Exynos5420
Tomasz,
On Wed, Jun 12, 2013 at 2:20 PM, Doug Anderson diand...@chromium.org wrote:
Tomasz,
On Wed, Jun 12, 2013 at 1:58 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
+ pinctrl@1340 {
+ gpy7: gpy7 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
According to patch 2/3, this bank doesn't support interrupts, as it's
defined using EINTN macro. Which variant is correct?
As far as I know the GPY registers don't support interrupts, so this
should be removed. Nice catch!
Argh. I'm not sure what I was just searching before (I probably
messed up and searched for gpy6 or something), but I just searched
again and am now seeing that GPY7 actually does support interrupts,
unlike all of the other gpy banks.
-Doug
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Re: [PATCH 2/3] pinctrl: exynos: add exynos5420 SoC specific data
Leela,
On Wed, Jun 12, 2013 at 7:51 AM, Leela Krishna Amudala
l.kris...@samsung.com wrote:
Add Samsung Exynos5420 SoC specific data to enable pinctrl support for
all platforms based on Exynos5420.
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
---
.../bindings/pinctrl/samsung-pinctrl.txt |1 +
drivers/pinctrl/pinctrl-exynos.c | 115
drivers/pinctrl/pinctrl-samsung.c |2 +
drivers/pinctrl/pinctrl-samsung.h |1 +
4 files changed, 119 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index b2bc219..fe949c7 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -15,6 +15,7 @@ Required Properties:
- samsung,exynos4210-pinctrl: for Exynos4210 compatible pin-controller.
- samsung,exynos4x12-pinctrl: for Exynos4x12 compatible pin-controller.
- samsung,exynos5250-pinctrl: for Exynos5250 compatible pin-controller.
+ - samsung,exynos5420-pinctrl: for Exynos5420 compatible pin-controller.
- reg: Base address of the pin controller hardware module and length of
the address space it occupies.
diff --git a/drivers/pinctrl/pinctrl-exynos.c
b/drivers/pinctrl/pinctrl-exynos.c
index 2d76f66..753a8cd 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -941,3 +941,118 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
.label = exynos5250-gpio-ctrl3,
},
};
+
+/* pin banks of exynos5420 pin-controller 0 */
+static struct samsung_pin_bank exynos5420_pin_banks0[] = {
+ EXYNOS_PIN_BANK_EINTN(8, 0x000, gpy7),
As Tomasz points out, it looks like this should be EINTG.
Otherwise looks good.
Reviewed-by: Doug Anderson diand...@chromium.org
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Re: [PATCH 1/3] ARM: dts: add pinctrl support to Exynos5420
On Wednesday 12 of June 2013 14:35:30 Doug Anderson wrote:
Tomasz,
On Wed, Jun 12, 2013 at 2:20 PM, Doug Anderson diand...@chromium.org
wrote:
Tomasz,
On Wed, Jun 12, 2013 at 1:58 PM, Tomasz Figa tomasz.f...@gmail.com
wrote:
+ pinctrl@1340 {
+ gpy7: gpy7 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
According to patch 2/3, this bank doesn't support interrupts, as it's
defined using EINTN macro. Which variant is correct?
As far as I know the GPY registers don't support interrupts, so this
should be removed. Nice catch!
Argh. I'm not sure what I was just searching before (I probably
messed up and searched for gpy6 or something), but I just searched
again and am now seeing that GPY7 actually does support interrupts,
unlike all of the other gpy banks.
This or other way, one of the patches needs to be fixed. If this bank
supports interrupts, the patch adding driver data needs to be adjusted to
use the EINTG macro.
Best regards,
Tomasz
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Re: [PATCH 00/15] Final Samsung PWM support cleanup
Hi, On Wednesday 05 of June 2013 23:18:05 Tomasz Figa wrote: Since we now have a proper Samsung PWM clocksource driver in place, we can proceed with further cleanup of PWM timers support on Samsung SoCs. This series attempts to achieve this goal by: 1) moving remaining Samsung platforms to the new clocksource driver 2) removing old clocksource driver 3) adding new multiplatform- and DT-aware PWM driver 4) moving all Samsung platforms to use the new PWM driver 5) removing old PWM driver 6) removing all PWM-related code that is not used anymore Cleaning up the PWM driver is a bit tricky, because the design of current driver makes it completely unsuitable for DT and multiplatform and would require a heavy rework to make it usable, breaking any existing Samsung PWM users by the way. To avoid any breakage I decided to keep the old driver, add new one, move all platforms to it and then remove the old one. See particular patches for more detailed descriptions. On S3C6410-based Tiny6410 (Mini6410-compatible), after enabling pwm-beeper: Tested-by: Tomasz Figa tomasz.f...@gmail.com Needs testing on other platforms as I could only compile test for them. Tomasz Figa (15): ARM: SAMSUNG: Unify base address definitions of timer block ARM: SAMSUNG: Add new PWM platform device ARM: SAMSUNG: Set PWM platform data ARM: SAMSUNG: Move all platforms to new clocksource driver ARM: SAMSUNG: Remove old samsung-time driver ARM: SAMSUNG: Remove unused PWM timer IRQ chip code pwm: samsung: Rename to pwm-samsung-legacy pwm: Add new pwm-samsung driver ARM: SAMSUNG: Rework private data handling in dev-backlight ARM: SAMSUNG: Modify board files to use new PWM platform device pwm: Remove superseded pwm-samsung-legacy driver ARM: SAMSUNG: Remove old PWM timer platform devices ARM: SAMSUNG: Remove pwm-clock infrastructure ARM: SAMSUNG: Remove remaining uses of plat/regs-timer.h header ARM: SAMSUNG: Remove plat/regs-timer.h header arch/arm/Kconfig | 1 - arch/arm/mach-exynos/common.c | 3 + arch/arm/mach-exynos/include/mach/irqs.h | 3 +- arch/arm/mach-exynos/include/mach/map.h| 1 + arch/arm/mach-exynos/mach-nuri.c | 4 +- arch/arm/mach-exynos/mach-origen.c | 3 +- arch/arm/mach-exynos/mach-smdk4x12.c | 3 +- arch/arm/mach-exynos/mach-smdkv310.c | 3 +- arch/arm/mach-s3c24xx/Kconfig | 12 +- arch/arm/mach-s3c24xx/clock-s3c2410.c | 1 - arch/arm/mach-s3c24xx/clock-s3c2412.c | 1 - arch/arm/mach-s3c24xx/clock-s3c2416.c | 2 - arch/arm/mach-s3c24xx/clock-s3c2443.c | 2 - arch/arm/mach-s3c24xx/common.c | 27 + arch/arm/mach-s3c24xx/include/mach/map.h | 2 + arch/arm/mach-s3c24xx/mach-h1940.c | 4 +- arch/arm/mach-s3c24xx/mach-rx1950.c| 5 +- arch/arm/mach-s3c64xx/Kconfig | 4 +- arch/arm/mach-s3c64xx/clock.c | 2 - arch/arm/mach-s3c64xx/common.c | 32 +- arch/arm/mach-s3c64xx/include/mach/irqs.h | 8 - arch/arm/mach-s3c64xx/include/mach/map.h | 1 + arch/arm/mach-s3c64xx/irq-pm.c | 2 - arch/arm/mach-s3c64xx/mach-crag6410.c | 4 +- arch/arm/mach-s3c64xx/mach-hmt.c | 4 +- arch/arm/mach-s3c64xx/mach-smartq.c| 4 +- arch/arm/mach-s3c64xx/mach-smdk6410.c | 1 + arch/arm/mach-s5p64x0/Kconfig | 4 +- arch/arm/mach-s5p64x0/clock-s5p6440.c | 2 - arch/arm/mach-s5p64x0/clock-s5p6450.c | 2 - arch/arm/mach-s5p64x0/common.c | 27 + arch/arm/mach-s5p64x0/include/mach/irqs.h | 2 - arch/arm/mach-s5p64x0/include/mach/map.h | 1 + arch/arm/mach-s5p64x0/mach-smdk6440.c | 1 + arch/arm/mach-s5p64x0/mach-smdk6450.c | 1 + arch/arm/mach-s5p64x0/pm.c | 3 - arch/arm/mach-s5pc100/Kconfig | 2 +- arch/arm/mach-s5pc100/clock.c | 2 - arch/arm/mach-s5pc100/common.c | 28 + arch/arm/mach-s5pc100/include/mach/irqs.h | 2 - arch/arm/mach-s5pc100/include/mach/map.h | 1 + arch/arm/mach-s5pc100/mach-smdkc100.c | 1 + arch/arm/mach-s5pv210/Kconfig | 2 +- arch/arm/mach-s5pv210/clock.c | 1 - arch/arm/mach-s5pv210/common.c | 28 + arch/arm/mach-s5pv210/include/mach/irqs.h | 2 - arch/arm/mach-s5pv210/include/mach/map.h | 1 + arch/arm/mach-s5pv210/mach-smdkv210.c | 1 + arch/arm/mach-s5pv210/pm.c
Re: [PATCH v4 1/6] clk: samsung: Use clk-base instead of directly using clk-con0 for PLL3xxx
Tomasz,
On Wed, Jun 12, 2013 at 2:19 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
Hmm, if done properly, it could simplify PLL registration in SoC clock
initialization code a lot.
I'm not sure if this is really the best solution (feel free to suggest
anything better), but we could put PLLs in an array, like other clocks,
e.g.
... exynos4210_pll_clks[] = {
CLK_PLL45XX(...),
CLK_PLL45XX(...),
CLK_PLL46XX(...),
CLK_PLL46XX(...),
};
and then just call a helper like
samsung_clk_register_pll(exynos4210_pll_clks,
ARRAY_SIZE(exynos4210_pll_clks));
Something like that looks like what I was thinking. I'd have to see
it actually coded up to see if there's something I'm missing that
would prevent us from doing that, but I don't see anything.
-Doug
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Re: [PATCH v4 1/6] clk: samsung: Use clk-base instead of directly using clk-con0 for PLL3xxx
Doug,
Hmm, if done properly, it could simplify PLL registration in SoC clock
initialization code a lot.
I'm not sure if this is really the best solution (feel free to suggest
anything better), but we could put PLLs in an array, like other clocks,
e.g.
... exynos4210_pll_clks[] = {
CLK_PLL45XX(...),
CLK_PLL45XX(...),
CLK_PLL46XX(...),
CLK_PLL46XX(...),
};
and then just call a helper like
samsung_clk_register_pll(exynos4210_pll_clks,
ARRAY_SIZE(exynos4210_pll_clks));
Something like that looks like what I was thinking. I'd have to see
it actually coded up to see if there's something I'm missing that
would prevent us from doing that, but I don't see anything.
The only issue I see with this is that we may only want to register a
rate table with a PLL only if fin_pll is running at a certain rate.
On 5250 and 5420, for example, we have EPLL and VPLL rate tables that
should only be registered if fin_pll is 24Mhz. We may have to
register those separately, but this approach seems fine otherwise.
-Andrew
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Re: [PATCH 00/15] Final Samsung PWM support cleanup
On Wed, Jun 12, 2013 at 11:48:56PM +0200, Tomasz Figa wrote: Needs testing on other platforms as I could only compile test for them. How/who can help here? WHo has and still cares for other affected platforms? 66 files changed, 627 insertions(+), 1580 deletions(-) Nice cleanup. Any comments for this series? Yes, above. :) In general looks good -- testing coverage is a bit of a concern. -Olof -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 00/15] Final Samsung PWM support cleanup
Hi Olof, On Wednesday 12 of June 2013 16:00:23 Olof Johansson wrote: On Wed, Jun 12, 2013 at 11:48:56PM +0200, Tomasz Figa wrote: Needs testing on other platforms as I could only compile test for them. How/who can help here? WHo has and still cares for other affected platforms? 66 files changed, 627 insertions(+), 1580 deletions(-) I will try to test this on Exynos 4 at work, if I somehow manage to find any way to use PWM on our boards (other than already-tested PWM clocksource). Unfortunately, except S3C6410, I don't have access to other platforms, or at least I won't in any reasonable time. If I remember correctly, in case of my watchdog support cleanup, Kukjin has been able to test it on S5P64x0. Heiko and Sylwester used to have some s3c24xx-based boards, not sure if they still do and are interested in their support in mainline. So all left is S5PC100 (for which I couldn't find anyone who cares) and Exynos5. Nice cleanup. Thanks. Any comments for this series? Yes, above. :) In general looks good -- testing coverage is a bit of a concern. Yeah. Unfortunately all I could do was testing on Tiny6410 and compile testing on others. I hope we find some really helpful people over here who could waste a bit of their precious time for this museum. ;) Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [GIT PULL 3/6] exynos arch
On Wed, Jun 12, 2013 at 06:08:48AM +0900, Kukjin Kim wrote: The following changes since commit 317ddd256b9c24b0d78fa8018f80f1e495481a10: Linux 3.10-rc5 (2013-06-08 17:41:04 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git tags/exynos-arch-1 for you to fetch changes up to d75666024bbb7d1b4fa6f0b00ecd8d834033259a: ARM: EXYNOS: call scu_enable() only in case of cortex-A9 processor (2013-06-10 18:28:04 +0900) update exynos arch part Kukjin, please, write proper tag messages. This adds no value. Give a brief overview of what's in the branch instead. Doug Anderson (1): ARM: EXYNOS: Select PINCTRL_EXYNOS for exynos4/5 at chip level Girish K S (1): ARM: EXYNOS: force MAC ip to 32bit DMA Kukjin Kim (1): ARM: EXYNOS: no more support non-DT for EXYNOS SoCs Leela Krishna Amudala (1): ARM: EXYNOS: call scu_enable() only in case of cortex-A9 processor Thomas Abraham (1): ARM: EXYNOS: Add a platform bus notifier to set dma masks for Exynos5440 This one has outstanding comments from Russell that were not addressed? Not pulled. -Olof -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 00/15] Final Samsung PWM support cleanup
Am Donnerstag, 13. Juni 2013, 01:13:47 schrieb Tomasz Figa: Hi Olof, On Wednesday 12 of June 2013 16:00:23 Olof Johansson wrote: On Wed, Jun 12, 2013 at 11:48:56PM +0200, Tomasz Figa wrote: Needs testing on other platforms as I could only compile test for them. How/who can help here? WHo has and still cares for other affected platforms? 66 files changed, 627 insertions(+), 1580 deletions(-) I will try to test this on Exynos 4 at work, if I somehow manage to find any way to use PWM on our boards (other than already-tested PWM clocksource). Unfortunately, except S3C6410, I don't have access to other platforms, or at least I won't in any reasonable time. If I remember correctly, in case of my watchdog support cleanup, Kukjin has been able to test it on S5P64x0. Heiko and Sylwester used to have some s3c24xx-based boards, not sure if they still do and are interested in their support in mainline. So all left is S5PC100 (for which I couldn't find anyone who cares) and Exynos5. Nice cleanup. Thanks. Any comments for this series? Yes, above. :) In general looks good -- testing coverage is a bit of a concern. Yeah. Unfortunately all I could do was testing on Tiny6410 and compile testing on others. I hope we find some really helpful people over here who could waste a bit of their precious time for this museum. ;) I'll try to give it a testrun tomorrow. And my s3c2416 will always be the first-love-architecture for me ;-) Heiko -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 00/15] Final Samsung PWM support cleanup
On 06/13/2013 01:38 AM, Heiko Stübner wrote: Am Donnerstag, 13. Juni 2013, 01:13:47 schrieb Tomasz Figa: Hi Olof, On Wednesday 12 of June 2013 16:00:23 Olof Johansson wrote: On Wed, Jun 12, 2013 at 11:48:56PM +0200, Tomasz Figa wrote: Needs testing on other platforms as I could only compile test for them. How/who can help here? WHo has and still cares for other affected platforms? 66 files changed, 627 insertions(+), 1580 deletions(-) I will try to test this on Exynos 4 at work, if I somehow manage to find any way to use PWM on our boards (other than already-tested PWM clocksource). Unfortunately, except S3C6410, I don't have access to other platforms, or at least I won't in any reasonable time. If I remember correctly, in case of my watchdog support cleanup, Kukjin has been able to test it on S5P64x0. Heiko and Sylwester used to have some s3c24xx-based boards, not sure if they still do and are interested in their support in mainline. So all left is S5PC100 (for which I couldn't find anyone who cares) and Exynos5. Nice cleanup. Thanks. Any comments for this series? Yes, above. :) In general looks good -- testing coverage is a bit of a concern. Yeah. Unfortunately all I could do was testing on Tiny6410 and compile testing on others. I hope we find some really helpful people over here who could waste a bit of their precious time for this museum. ;) I'll try to give it a testrun tomorrow. And my s3c2416 will always be the first-love-architecture for me ;-) I'll likely test it tomorrow on a Mini2440 board, I was going to do it earlier but got distracted by plenty other things that needed attention too. At least that's one of the reasons I got the board - testing the cross-platform cleanups and ensuring they are not breaking the older platforms. Regards, Sylwester -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [GIT PULL 6/6] s3c24xx driver
On Wed, Jun 12, 2013 at 06:09:10AM +0900, Kukjin Kim wrote: The following changes since commit 317ddd256b9c24b0d78fa8018f80f1e495481a10: Linux 3.10-rc5 (2013-06-08 17:41:04 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git tags/s3c24xx-driver-1 for you to fetch changes up to ae7b6dccf6711e8d5815688f1572ab55bf5b3069: Merge branch 'v3.11-next/driver-cpufreq' into v3.11-next/s3c24xx-driver (2013-06-12 05:24:22 +0900) update driver for s3c24xx - move cpufreq driver into drivers/ - add pinctrl-s3c24xx driver - cleanup OF in gpio driver Heiko Stuebner (1): pinctrl: Add pinctrl-s3c24xx driver Kukjin Kim (3): Merge branch 'v3.11-next/driver-gpio' into v3.11-next/s3c24xx-driver Merge branch 'v3.11-next/driver-pinctrl' into v3.11-next/s3c24xx-driver Merge branch 'v3.11-next/driver-cpufreq' into v3.11-next/s3c24xx-driver Hi, No need to do a merge commit per patch, just do them on a single branch in the future, please. Pulled. -Olof -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [GIT PULL 0/6] Samsung stuff for v3.11
On Wed, Jun 12, 2013 at 06:08:19AM +0900, Kukjin Kim wrote: Hi Arnd, Olof Please pull Samsung stuff for v3.11. If any problems, please kindly let me know. Hi, I've pulled 1, 2, 4 and 6. Please fix the comments on 3 and 5 and send fresh requests. Also, I see you've based a bunch of branches on -rc5. While this is fine, it is more convenient for us to review your branch submission if it doesn't also pull in a newer upstream -rc. Main reason to use the most-recent -rc would be if new code conflicts with fixes in the previous -rc version, but if they don't then feel free to start your branches on an older version instead. -Olof -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH 00/15] Final Samsung PWM support cleanup
Olof Johansson wrote: On Wed, Jun 12, 2013 at 11:48:56PM +0200, Tomasz Figa wrote: Needs testing on other platforms as I could only compile test for them. How/who can help here? WHo has and still cares for other affected platforms? 66 files changed, 627 insertions(+), 1580 deletions(-) Nice cleanup. Any comments for this series? Yes, above. :) In general looks good -- testing coverage is a bit of a concern. Good news, I'm building up team to support samsung stuff in mainline including test on boards, you know, I have the most of smdk/ssdk boards :) But I need some time :( I looked at reply from Sylwester and Heiko, thanks. Let me pick this series after their test. Thanks. - Kukjin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [GIT PULL 6/6] s3c24xx driver
Olof Johansson wrote: On Wed, Jun 12, 2013 at 06:09:10AM +0900, Kukjin Kim wrote: The following changes since commit 317ddd256b9c24b0d78fa8018f80f1e495481a10: Linux 3.10-rc5 (2013-06-08 17:41:04 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git tags/s3c24xx-driver-1 for you to fetch changes up to ae7b6dccf6711e8d5815688f1572ab55bf5b3069: Merge branch 'v3.11-next/driver-cpufreq' into v3.11-next/s3c24xx-driver (2013-06-12 05:24:22 +0900) update driver for s3c24xx - move cpufreq driver into drivers/ - add pinctrl-s3c24xx driver - cleanup OF in gpio driver Heiko Stuebner (1): pinctrl: Add pinctrl-s3c24xx driver Kukjin Kim (3): Merge branch 'v3.11-next/driver-gpio' into v3.11-next/s3c24xx- driver Merge branch 'v3.11-next/driver-pinctrl' into v3.11-next/s3c24xx-driver Merge branch 'v3.11-next/driver-cpufreq' into v3.11-next/s3c24xx-driver Hi, Hi, No need to do a merge commit per patch, just do them on a single branch in the future, please. OK. Pulled. Thanks. - Kukjin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [GIT PULL 5/6] remove non-DT for exynos
Olof Johansson wrote: On Wed, Jun 12, 2013 at 06:09:03AM +0900, Kukjin Kim wrote: The following changes since commit 317ddd256b9c24b0d78fa8018f80f1e495481a10: Linux 3.10-rc5 (2013-06-08 17:41:04 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git tags/remove-nondt-exynos for you to fetch changes up to 8661bc149b95b5d4298b4ffd55c298972c4820d1: ARM: exynos4_defconfig: remove non-DT configuration (2013-06-10 18:37:01 +0900) remove non DT support for exynos Kukjin Kim (2): ARM: EXYNOS: no more support non-DT for EXYNOS SoCs ARM: exynos4_defconfig: remove non-DT configuration arch/arm/configs/exynos4_defconfig | 68 arch/arm/mach-exynos/Kconfig | 320 +--- arch/arm/mach-exynos/Makefile | 26 --- arch/arm/mach-exynos/common.c | 10 -- arch/arm/mach-exynos/dev-ahci.c| 255 - arch/arm/mach-exynos/dev-ohci.c| 52 -- arch/arm/mach-exynos/dma.c | 322 - arch/arm/mach-exynos/pm_domains.c | 7 - 8 files changed, 1 insertion(+), 1059 deletions(-) delete mode 100644 arch/arm/configs/exynos4_defconfig delete mode 100644 arch/arm/mach-exynos/dev-ahci.c delete mode 100644 arch/arm/mach-exynos/dev-ohci.c delete mode 100644 arch/arm/mach-exynos/dma.c Kukjin, Hi Olof, What about the legacy board files? I don't see them removed (nor converted to DT) here, so this is not a full removal. Oops, why are there still the board files :( Probably, there was a mistake... Thanks. Also, the argument to keep exynos4_defconfig was that it needed to enable non-DT boards. I think we might as well just remove the defconfig and make sure all the needed options are enabled in exynos_defconfig -- they should coexist just fine. OK agreed. I'll hold off pulling until the defconfig situation has been resolved, but please follow up on the board file piece too. Sure, thanks. - Kukjin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [GIT PULL 3/6] exynos arch
Olof Johansson wrote: On Wed, Jun 12, 2013 at 06:08:48AM +0900, Kukjin Kim wrote: The following changes since commit 317ddd256b9c24b0d78fa8018f80f1e495481a10: Linux 3.10-rc5 (2013-06-08 17:41:04 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git tags/exynos-arch-1 for you to fetch changes up to d75666024bbb7d1b4fa6f0b00ecd8d834033259a: ARM: EXYNOS: call scu_enable() only in case of cortex-A9 processor (2013-06-10 18:28:04 +0900) update exynos arch part Kukjin, please, write proper tag messages. This adds no value. Give a brief overview of what's in the branch instead. YES, I will. Doug Anderson (1): ARM: EXYNOS: Select PINCTRL_EXYNOS for exynos4/5 at chip level Girish K S (1): ARM: EXYNOS: force MAC ip to 32bit DMA Kukjin Kim (1): ARM: EXYNOS: no more support non-DT for EXYNOS SoCs Leela Krishna Amudala (1): ARM: EXYNOS: call scu_enable() only in case of cortex-A9 processor Thomas Abraham (1): ARM: EXYNOS: Add a platform bus notifier to set dma masks for Exynos5440 This one has outstanding comments from Russell that were not addressed? Oops, I missed the comment from Russell and looked at just now. Thanks. Not pulled. OK. - Kukjin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [GIT PULL 0/6] Samsung stuff for v3.11
Olof Johansson wrote: On Wed, Jun 12, 2013 at 06:08:19AM +0900, Kukjin Kim wrote: Hi Arnd, Olof Please pull Samsung stuff for v3.11. If any problems, please kindly let me know. Hi, I've pulled 1, 2, 4 and 6. Please fix the comments on 3 and 5 and send fresh requests. Thanks. OK, I will. Also, I see you've based a bunch of branches on -rc5. While this is fine, it is more convenient for us to review your branch submission if it doesn't also pull in a newer upstream -rc. Main reason to use the most-recent -rc would be if new code conflicts with fixes in the previous -rc version, but if they don't then feel free to start your branches on an older version instead. Agreed. - Kukjin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V6 6/6] clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2
Hi Mike,
On Wed, Jun 12, 2013 at 10:15 PM, Mike Turquette mturque...@linaro.org wrote:
Quoting Padmavathi Venna (2013-06-12 01:07:43)
This patch adds enum entries for div_i2s1 and div_i2s2 which are
required for i2s1 and i2s2 controllers.
Signed-off-by: Padmavathi Venna padm...@samsung.com
Looks good. Did you want me to take the clk patches or just gathering
Acks?
Please take the patches :).
Thanks
Padma
Regards,
Mike
---
drivers/clk/samsung/clk-exynos5250.c |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index 5c97e75..7c68850 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -87,6 +87,7 @@ enum exynos5250_clks {
sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1,
sclk_spi2,
+ div_i2s1, div_i2s2,
/* gate clocks */
gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
@@ -291,8 +292,8 @@ struct samsung_div_clock exynos5250_div_clks[]
__initdata = {
DIV(none, div_pcm1, sclk_audio1, DIV_PERIC4, 4, 8),
DIV(none, div_audio2, mout_audio2, DIV_PERIC4, 16, 4),
DIV(none, div_pcm2, sclk_audio2, DIV_PERIC4, 20, 8),
- DIV(none, div_i2s1, sclk_audio1, DIV_PERIC5, 0, 6),
- DIV(none, div_i2s2, sclk_audio2, DIV_PERIC5, 8, 6),
+ DIV(div_i2s1, div_i2s1, sclk_audio1, DIV_PERIC5, 0, 6),
+ DIV(div_i2s2, div_i2s2, sclk_audio2, DIV_PERIC5, 8, 6),
DIV(sclk_pixel, div_hdmi_pixel, sclk_vpll, DIV_DISP1_0, 28, 4),
DIV_A(none, armclk, div_arm, DIV_CPU0, 28, 3, armclk),
DIV_F(none, div_mipi1_pre, div_mipi1,
--
1.7.4.4
--
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Re: [RFC 0/2] exynos5250/hdmi: replace dummy hdmiphy clock with pmu reg control
Mr. Dae, Thanks for your valuable inputs. I posted it as RFC because, I also have received comments to register hdmiphy as a clock controller. As we always configure it for specific frequency, hdmi-phy looks similar to a PLL. But it really doesn't belong to that class. Secondly prior to exynos5420, it was a i2c device. I am not sure we can register a I2C device as a clock controller. I wanted to discuss and explore this option here. As you said, in parallel, I will align these changes and along with drm/exynos: hdmi: move hdmiphy related code to hdmiphy driver series and post them. I hope we should be able to close on one of the above approaches for hdmiphy. regards, Rahul Sharma. On Wed, Jun 12, 2013 at 9:57 AM, Inki Dae inki@samsung.com wrote: 2013/6/12 Inki Dae inki@samsung.com Hi Rahul, This patch is important to us. Actually, previous hdmi driver had controlled hdmiphy HDMI_PHY_CONTROL as if that were a clock but now that doesn't exist anymore. So we need to discuss how hdmiphy should be handled. I konw that you had already posted hdmiphy relevant patch set, [PATCH 0/4] drm/exynos: hdmi: move hdmiphy related code to hdmiphy driver. I think we can couple pmu register controlling codes with that patch set without RFC. Could you update and post them again? like below, [PATCH 0/4] drm/exynos: hdmi: move hdmiphy related code to hdmiphy driver + [RFC 0/2] exynos5250/hdmi: replace dummy hdmiphy clock with pmu reg control And then let's start review :) And I think It would be better to move the pmu register controlling codes into hdmiphy driver like drivers/usb/phy/phy-samsung-usb2.c driver does. Thanks, Inki Dae 2013/6/11 Rahul Sharma rahul.sha...@samsung.com Previously, hdmiphy is added as a dummy clock in clock file for exynos SoCs. Enable/Disable to this clock, actually toggles the power control bit in PMU, instead of controlling the clock gate. This RFC adds the support to parse hdmiphy control node which is a child node to hdmi, and map the pmu register to toggle the power control bit. This is based on drm-next branch in Inki Dae's tree. Rahul Sharma (2): drm/exynos: replace dummy hdmiphy clock with pmu register control ARM/dts: add hdmiphy power control pmu register to hdmi dt node arch/arm/boot/dts/exynos5250.dtsi|6 +++ drivers/gpu/drm/exynos/exynos_hdmi.c | 69 ++ drivers/gpu/drm/exynos/regs-hdmi.h |4 ++ 3 files changed, 71 insertions(+), 8 deletions(-) -- 1.7.10.4 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 09/13] clk: exynos5420: register clocks using common clock framework
On 13 June 2013 03:02, Andrew Bresticker abres...@chromium.org wrote: Tomasz, + apll = samsung_clk_register_pll35xx(fout_apll, oscclk, + reg_base + 0x100); + bpll = samsung_clk_register_pll35xx(fout_bpll, oscclk, + reg_base + 0x20110); + cpll = samsung_clk_register_pll35xx(fout_cpll, oscclk, + reg_base + 0x10120); + dpll = samsung_clk_register_pll35xx(fout_dpll, oscclk, + reg_base + 0x10128); + epll = samsung_clk_register_pll35xx(fout_epll, oscclk, + reg_base + 0x10130); + ipll = samsung_clk_register_pll35xx(fout_ipll, oscclk, + reg_base + 0x10150); + kpll = samsung_clk_register_pll35xx(fout_kpll, oscclk, + reg_base + 0x28100); + mpll = samsung_clk_register_pll35xx(fout_mpll, oscclk, + reg_base + 0x10180); + rpll = samsung_clk_register_pll35xx(fout_rpll, oscclk, + reg_base + 0x10140); + spll = samsung_clk_register_pll35xx(fout_spll, oscclk, + reg_base + 0x10160); + vpll = samsung_clk_register_pll35xx(fout_vpll, oscclk, + reg_base + 0x10170); Are all those PLLs really PLL35xx? At least for VPLL and EPLL a PLL without the K factor looks a bit awkward. No they are not... EPLL and RPLL should be pll36xx, but the rest are pll35xx. Yes EPLL and RPLL are pll36xx. Thanks for pointing out. Thanks, Andrew -- with warm regards, Chander Kashyap -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V4 3/3] ARM: dts: Add pcie controller node for Samsung EXYNOS5440 SoC
On Wednesday, June 12, 2013 7:56 PM, Arnd Bergmann wrote:
Thanks for the update! A few comments again:
On Wednesday 12 June 2013 19:20:00 Jingoo Han wrote:
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index d55042b..efe7d39 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -30,4 +30,12 @@
clock-frequency = 5000;
};
};
+
+ pcie0@4000 {
+ reset-gpio = 5;
+ };
+
+ pcie1@6000 {
+ reset-gpio = 22;
+ };
};
As mentioned before, please use the gpio binding to pass gpio numbers.
OK, I will use gpio binding.
diff --git a/arch/arm/boot/dts/exynos5440.dtsi
b/arch/arm/boot/dts/exynos5440.dtsi
index f6b1c89..2c15f9d 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -216,4 +216,42 @@
clock-names = rtc;
status = disabled;
};
+
+ pcie0@0x29 {
+ compatible = samsung,exynos5440-pcie;
+ reg = 0x29 0x1000
+ 0x27 0x1000
+ 0x271000 0x40;
+ interrupts = 0 20 0, 0 21 0, 0 22 0;
+ clocks = clock 28, clock 27;
+ clock-names = pcie, pcie_bus;
+ #address-cells = ;
+ #size-cells = 2;
+ device_type = pci;
+ ranges = 0x0800 0 0x4000 0x4000 0 0x0020
/* configuration space */
+ 0x8100 0 0 0x4020 0 0x0001
/* downstream I/O */
+ 0x8200 0 0x4021 0x4021 0 0x1000;
/* non-prefetchable memory */
I think you did not reply to my question regarding the size of the
memory space. Does it extend from 0x4021 to 0x5021,
or from 0x4021 to 0x5000. You probably meant the latter
but wrote the former. If not, please add a comment for clarification.
OK, I see.
It extends to 0x6000. I will modify it.
+ #interrupt-cells = 1;
+ interrupt-map-mask = 0 0 0 0;
+ interrupt-map = 0x0 0 gic 53;
+ };
So all PCI IntA interrupts are mapped to a single gic interrupt? That
sounds like a bottleneck when you have a lot of devices on the bus.
Do you have MSI support?
INTA, INTB, INTC, and INTD are mapped to a single gic interrupt.
Exynos5440 PCIe has MSI support; however, MSI support patch will
be posted later.
Arnd
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