Re: [PATCH v2 0/7] Add DT nodes for FIMD and DP controller for Exynos5420 SoC

2013-08-14 Thread Vikas Sajjan
Hi Kukjin,

On Wed, Aug 14, 2013 at 11:28 AM, Kukjin Kim kgene@samsung.com wrote:
 Vikas Sajjan wrote:

 This patchset adds DT nodes for FIMD and DP controller for Exynos5420
 based SMDK.

 It moves all common properties of FIMD and DP controller DT node specific
 to
 Exynos5 Socs like 5250 and 5420 to exynos5.dtsi file.

 It also adds required PM domain DT nodes for exynos5420.

 Is rebased on branch kgene's for-next
 https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-
 samsung.git/log/?h=for-next

 The DP PHY DT Node is based on Jingoo Han's inflight patchset at
 http://comments.gmane.org/gmane.linux.drivers.video-input-
 infrastructure/66435

 changes since v1:
   - Addressed comments given by Tomasz Figa tomasz.f...@gmail.com
   and Ajay kumar ajayn...@gmail.com

 Vikas Sajjan (6):
   ARM: dts: Move display-timimg information inside FIMD DT node for
 exynos5250
   ARM: dts: Update FIMD DT node for Exynos5 SoCs
   ARM: dts: Add FIMD DT node to exynos5420 DTS files
   ARM: dts: Update DP controller DT Node for Exynos5 based SoCs
   ARM: dts: Add DP controller DT node to exynos5420 SoC
   ARM: dts: Add pin state information for DP HPD support to Exynos5420

 Yadwinder Singh Brar (1):
   ARM: dts: Add basic PM domains for EXYNOS5420

  arch/arm/boot/dts/exynos5.dtsi|   21 +++
  arch/arm/boot/dts/exynos5250-arndale.dts  |4 ++-
  arch/arm/boot/dts/exynos5250-smdk5250.dts |   32 +
  arch/arm/boot/dts/exynos5250.dtsi |   28 ++-
  arch/arm/boot/dts/exynos5420-pinctrl.dtsi |7 
  arch/arm/boot/dts/exynos5420-smdk5420.dts |   31 
  arch/arm/boot/dts/exynos5420.dtsi |   55
 +
  7 files changed, 145 insertions(+), 33 deletions(-)

 --
 1.7.9.5

 Looks good to me, will apply this whole series with fix typo, timimg? ;-)


Thanks.


 - Kukjin

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Re: [PATCH V2] ARM: dts: Add RTC DT node to Exynos5420 SoC

2013-08-14 Thread Vikas Sajjan
Hi Kukjin,

On Wed, Aug 14, 2013 at 11:14 AM, Kukjin Kim kg...@kernel.org wrote:
 Vikas Sajjan wrote:

 Adds RTC DT node to Exynos5420 SoC.

 Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
 ---
 changes since v1:
   - made DT node status as okay in the dtsi file itself.
 ---
  arch/arm/boot/dts/exynos5.dtsi|2 +-
  arch/arm/boot/dts/exynos5250.dtsi |3 ++-
  arch/arm/boot/dts/exynos5420.dtsi |7 +++
  3 files changed, 10 insertions(+), 2 deletions(-)

 diff --git a/arch/arm/boot/dts/exynos5.dtsi
 b/arch/arm/boot/dts/exynos5.dtsi
 index f65e124..4a8e223 100644
 --- a/arch/arm/boot/dts/exynos5.dtsi
 +++ b/arch/arm/boot/dts/exynos5.dtsi
 @@ -95,7 +95,7 @@
   interrupts = 0 54 0;
   };

 - rtc {
 + rtc@101E {
   compatible = samsung,s3c6410-rtc;
   reg = 0x101E 0x100;
   interrupts = 0 43 0, 0 44 0;
 diff --git a/arch/arm/boot/dts/exynos5250.dtsi
 b/arch/arm/boot/dts/exynos5250.dtsi
 index 88589b7..c82137b 100644
 --- a/arch/arm/boot/dts/exynos5250.dtsi
 +++ b/arch/arm/boot/dts/exynos5250.dtsi
 @@ -178,9 +178,10 @@
   samsung,power-domain = pd_mfc;
   };

 - rtc {
 + rtc@101E {
   clocks = clock 337;
   clock-names = rtc;
 + status = okay;

 Well, according to the subject, 'add rtc dt node to exynos5420', this should
 be handled separately if required.


So, you want me to spit this 5250 modification to a separate patch
OR
Modify the subject line to match the changes.

   };

   tmu@1006 {
 diff --git a/arch/arm/boot/dts/exynos5420.dtsi
 b/arch/arm/boot/dts/exynos5420.dtsi
 index 9e90d1e..8f1bb08 100644
 --- a/arch/arm/boot/dts/exynos5420.dtsi
 +++ b/arch/arm/boot/dts/exynos5420.dtsi
 @@ -145,4 +145,11 @@
   clocks = clock 260, clock 131;
   clock-names = uart, clk_uart_baud0;
   };
 +
 + rtc@101E {

 Please put in the address order or alphabetical.


Sure will do.


 + clocks = clock 317;
 + clock-names = rtc;
 + status = okay;
 +   };
 +

 No need last empty line.

OK.


 - Kukjin

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Re: [GIT PULL] Samsung PWM support cleanup

2013-08-14 Thread Olof Johansson
On Tue, Aug 13, 2013 at 11:16:35PM +0200, Tomasz Figa wrote:
 Dear ARM SoC maintainers,
 
 The following changes since commit 
 c095ba7224d8edc71dcef0d655911399a8bd4a3f:
 
   Linux 3.11-rc4 (2013-08-04 13:46:46 -0700)
 
 are available in the git repository at:
 
   git://github.com/tom3q/linux.git tags/v3.12-pwm-cleanup-for-olof

Thanks, applied.


-Olof
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RE: [GIT PULL] Samsung PWM support cleanup

2013-08-14 Thread Kukjin Kim
Olof Johansson wrote:
 
 On Tue, Aug 13, 2013 at 11:16:35PM +0200, Tomasz Figa wrote:
  Dear ARM SoC maintainers,
 
  The following changes since commit
  c095ba7224d8edc71dcef0d655911399a8bd4a3f:
 
Linux 3.11-rc4 (2013-08-04 13:46:46 -0700)
 
  are available in the git repository at:
 
git://github.com/tom3q/linux.git tags/v3.12-pwm-cleanup-for-olof
 
 Thanks, applied.
 
Same here, this will be merged into samsung tree because of dependency.

Thanks,
Kukjin

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Re: [GIT PULL] Samsung PWM support cleanup

2013-08-14 Thread Olof Johansson
On Wed, Aug 14, 2013 at 12:08 AM, Kukjin Kim kg...@kernel.org wrote:
 Olof Johansson wrote:

 On Tue, Aug 13, 2013 at 11:16:35PM +0200, Tomasz Figa wrote:
  Dear ARM SoC maintainers,
 
  The following changes since commit
  c095ba7224d8edc71dcef0d655911399a8bd4a3f:
 
Linux 3.11-rc4 (2013-08-04 13:46:46 -0700)
 
  are available in the git repository at:
 
git://github.com/tom3q/linux.git tags/v3.12-pwm-cleanup-for-olof

 Thanks, applied.

 Same here, this will be merged into samsung tree because of dependency.

What's the dependency? If it's just two patches (which I think it is),
just send me your acks on them and we can apply them on top instead.


-Olof
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RE: [GIT PULL] Samsung-fixes-2 for v3.11

2013-08-14 Thread Kukjin Kim
Kevin Hilman wrote:
 
 Kukjin Kim kgene@samsung.com writes:
 
  The following changes since commit
 5ae90d8e467e625e447000cb4335c4db973b1095:
 
Linux 3.11-rc3 (2013-07-28 20:53:33 -0700)
 
  are available in the git repository at:
 
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
  tags/samsung-fixes-2
 
  for you to fetch changes up to 35f8550c8f27968af94ba5235cc611e3b6d86981:
 
ARM: SAMSUNG: fix to support for missing cpu specific map_io
  (2013-07-30 13:30:57 +0900)
 
 In the future, please send arm-soc pull request to a...@kernel.org also,
 this makes filtering easier when non-Arnd/Olof folks (like me) are
helping.
 
OK, it's not difficult, BTW I'm not sure what the difference of
linux-arm-kernel ml and arm(at)kernel.org.

- Kukjin

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Re: [GIT PULL] Samsung-fixes-2 for v3.11

2013-08-14 Thread Olof Johansson
On Wed, Aug 14, 2013 at 12:13 AM, Kukjin Kim kg...@kernel.org wrote:
 Kevin Hilman wrote:

 Kukjin Kim kgene@samsung.com writes:

  The following changes since commit
 5ae90d8e467e625e447000cb4335c4db973b1095:
 
Linux 3.11-rc3 (2013-07-28 20:53:33 -0700)
 
  are available in the git repository at:
 
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
  tags/samsung-fixes-2
 
  for you to fetch changes up to 35f8550c8f27968af94ba5235cc611e3b6d86981:
 
ARM: SAMSUNG: fix to support for missing cpu specific map_io
  (2013-07-30 13:30:57 +0900)

 In the future, please send arm-soc pull request to a...@kernel.org also,
 this makes filtering easier when non-Arnd/Olof folks (like me) are
 helping.

 OK, it's not difficult, BTW I'm not sure what the difference of
 linux-arm-kernel ml and arm(at)kernel.org.

a...@kernel.org goes to Arnd, Kevin, Russel and myself. I think there
might be one or two more people on there, but in general it's
arm-soc+arm maintainers.

We haven't wanted to add it to MAINTAINERS since we want to keep the
traffic mostly to the pull requests of platform maintainers, and not
as a cc of patch postings, to keep the traffic volume manageable. :)


-Olof
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RE: [GIT PULL] Samsung PWM support cleanup

2013-08-14 Thread Kukjin Kim
Olof Johansson wrote:
 
 On Wed, Aug 14, 2013 at 12:08 AM, Kukjin Kim kg...@kernel.org wrote:
  Olof Johansson wrote:
 
  On Tue, Aug 13, 2013 at 11:16:35PM +0200, Tomasz Figa wrote:
   Dear ARM SoC maintainers,
  
   The following changes since commit
   c095ba7224d8edc71dcef0d655911399a8bd4a3f:
  
 Linux 3.11-rc4 (2013-08-04 13:46:46 -0700)
  
   are available in the git repository at:
  
 git://github.com/tom3q/linux.git tags/v3.12-pwm-cleanup-for-olof
 
  Thanks, applied.
 
  Same here, this will be merged into samsung tree because of dependency.
 
 What's the dependency? If it's just two patches (which I think it is),
 just send me your acks on them and we can apply them on top instead.
 
Yeah if there are two patches, I can. But there are another dependent series
such as [PATCH v2 0/8] Common Clock Framework support for Samsung S3C64xx
from Tomasz. So I'd like to merge that into the samsung tree.

- Kukjin

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RE: [GIT PULL] Samsung-fixes-2 for v3.11

2013-08-14 Thread Kukjin Kim
Olof Johansson wrote:
 
 On Wed, Aug 14, 2013 at 12:13 AM, Kukjin Kim kg...@kernel.org wrote:
  Kevin Hilman wrote:
 
  Kukjin Kim kgene@samsung.com writes:
 
   The following changes since commit
  5ae90d8e467e625e447000cb4335c4db973b1095:
  
 Linux 3.11-rc3 (2013-07-28 20:53:33 -0700)
  
   are available in the git repository at:
  
 git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-
 samsung.git
   tags/samsung-fixes-2
  
   for you to fetch changes up to
 35f8550c8f27968af94ba5235cc611e3b6d86981:
  
 ARM: SAMSUNG: fix to support for missing cpu specific map_io
   (2013-07-30 13:30:57 +0900)
 
  In the future, please send arm-soc pull request to a...@kernel.org also,
  this makes filtering easier when non-Arnd/Olof folks (like me) are
  helping.
 
  OK, it's not difficult, BTW I'm not sure what the difference of
  linux-arm-kernel ml and arm(at)kernel.org.
 
 a...@kernel.org goes to Arnd, Kevin, Russel and myself. I think there
 might be one or two more people on there, but in general it's
 arm-soc+arm maintainers.
 
 We haven't wanted to add it to MAINTAINERS since we want to keep the
 traffic mostly to the pull requests of platform maintainers, and not
 as a cc of patch postings, to keep the traffic volume manageable. :)
 
OK, I see.

Thanks,
Kukjin

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RE: [PATCH v2 2/7] ARM: dts: Update FIMD DT node for Exynos5 SoCs

2013-08-14 Thread Kukjin Kim
Vikas Sajjan wrote:
 
 Moves the properties of FIMD DT node which are common across Exynos5 based
 SoCs like Exynos5250 and Exxynos5420 to exynos5.dtsi
 
%s/Exxynos/Exynos

 Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
 ---
  arch/arm/boot/dts/exynos5.dtsi   |   10 ++
  arch/arm/boot/dts/exynos5250-arndale.dts |1 +
  arch/arm/boot/dts/exynos5250.dtsi|7 +--
  3 files changed, 12 insertions(+), 6 deletions(-)
 
 diff --git a/arch/arm/boot/dts/exynos5.dtsi
 b/arch/arm/boot/dts/exynos5.dtsi
 index f65e124..d464b6c 100644
 --- a/arch/arm/boot/dts/exynos5.dtsi
 +++ b/arch/arm/boot/dts/exynos5.dtsi
 @@ -108,4 +108,14 @@
   interrupts = 0 42 0;
   status = disabled;
   };
 +
 + fimd@1440 {
 + compatible = samsung,exynos5250-fimd;
 + interrupt-parent = combiner;
 + reg = 0x1440 0x4;
 + interrupt-names = fifo, vsync, lcd_sys;
 + interrupts = 18 4, 18 5, 18 6;
 + status = disabled;
 + };
 +

No need last empty line.

  };
 diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
 b/arch/arm/boot/dts/exynos5250-arndale.dts
 index 96d528d..76825ef 100644
 --- a/arch/arm/boot/dts/exynos5250-arndale.dts
 +++ b/arch/arm/boot/dts/exynos5250-arndale.dts
 @@ -519,6 +519,7 @@
   };
 
   fimd: fimd@1440 {
 + status = okay;
   display-timings {
   native-mode = timing0;
   timing0: timing@0 {
 diff --git a/arch/arm/boot/dts/exynos5250.dtsi
 b/arch/arm/boot/dts/exynos5250.dtsi
 index ef57277..238bdb2 100644
 --- a/arch/arm/boot/dts/exynos5250.dtsi
 +++ b/arch/arm/boot/dts/exynos5250.dtsi
 @@ -630,12 +630,7 @@
   };
   };
 
 - fimd {
 - compatible = samsung,exynos5250-fimd;
 - interrupt-parent = combiner;
 - reg = 0x1440 0x4;
 - interrupt-names = fifo, vsync, lcd_sys;
 - interrupts = 18 4, 18 5, 18 6;
 + fimd@1440 {
   clocks = clock 133, clock 339;
   clock-names = sclk_fimd, fimd;
   };
 --
 1.7.9.5

But you don't need to repost because let me fix when I apply.

Thanks,
Kukjin

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Re: [PATCH v2 2/7] ARM: dts: Update FIMD DT node for Exynos5 SoCs

2013-08-14 Thread Vikas Sajjan
Hi Kukjin,

On 14 August 2013 13:03, Kukjin Kim kg...@kernel.org wrote:
 Vikas Sajjan wrote:

 Moves the properties of FIMD DT node which are common across Exynos5 based
 SoCs like Exynos5250 and Exxynos5420 to exynos5.dtsi

 %s/Exxynos/Exynos

 Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
 ---
  arch/arm/boot/dts/exynos5.dtsi   |   10 ++
  arch/arm/boot/dts/exynos5250-arndale.dts |1 +
  arch/arm/boot/dts/exynos5250.dtsi|7 +--
  3 files changed, 12 insertions(+), 6 deletions(-)

 diff --git a/arch/arm/boot/dts/exynos5.dtsi
 b/arch/arm/boot/dts/exynos5.dtsi
 index f65e124..d464b6c 100644
 --- a/arch/arm/boot/dts/exynos5.dtsi
 +++ b/arch/arm/boot/dts/exynos5.dtsi
 @@ -108,4 +108,14 @@
   interrupts = 0 42 0;
   status = disabled;
   };
 +
 + fimd@1440 {
 + compatible = samsung,exynos5250-fimd;
 + interrupt-parent = combiner;
 + reg = 0x1440 0x4;
 + interrupt-names = fifo, vsync, lcd_sys;
 + interrupts = 18 4, 18 5, 18 6;
 + status = disabled;
 + };
 +

 No need last empty line.

  };
 diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
 b/arch/arm/boot/dts/exynos5250-arndale.dts
 index 96d528d..76825ef 100644
 --- a/arch/arm/boot/dts/exynos5250-arndale.dts
 +++ b/arch/arm/boot/dts/exynos5250-arndale.dts
 @@ -519,6 +519,7 @@
   };

   fimd: fimd@1440 {
 + status = okay;
   display-timings {
   native-mode = timing0;
   timing0: timing@0 {
 diff --git a/arch/arm/boot/dts/exynos5250.dtsi
 b/arch/arm/boot/dts/exynos5250.dtsi
 index ef57277..238bdb2 100644
 --- a/arch/arm/boot/dts/exynos5250.dtsi
 +++ b/arch/arm/boot/dts/exynos5250.dtsi
 @@ -630,12 +630,7 @@
   };
   };

 - fimd {
 - compatible = samsung,exynos5250-fimd;
 - interrupt-parent = combiner;
 - reg = 0x1440 0x4;
 - interrupt-names = fifo, vsync, lcd_sys;
 - interrupts = 18 4, 18 5, 18 6;
 + fimd@1440 {
   clocks = clock 133, clock 339;
   clock-names = sclk_fimd, fimd;
   };
 --
 1.7.9.5

 But you don't need to repost because let me fix when I apply.


OK. Thanks.

 Thanks,
 Kukjin




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Re: [PATCH v2 1/7] ARM: dts: Move display-timimg information inside FIMD DT node for exynos5250

2013-08-14 Thread Tomasz Figa
On Wednesday 14 of August 2013 14:56:55 Kukjin Kim wrote:
 Tomasz Figa wrote:
  Hi Vikas,
  
  On Tuesday 30 of July 2013 16:49:32 Vikas Sajjan wrote:
   As the display-timing information is parsed by FIMD driver, it makes
   sense to move the display-timimg DT node inside FIMD DT node for
   exynos5250
   
   Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
   ---
   
arch/arm/boot/dts/exynos5250-smdk5250.dts |   29
   
   - 1 file changed, 16 insertions(+), 13
   deletions(-)
   
   diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
   b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 49f18c2..d176dbb
   100644
   --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
   +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
   @@ -262,19 +262,22 @@
   
 pinctrl-0 = dp_hpd;
 
 };
   
   - display-timings {
   - native-mode = timing0;
   - timing0: timing@0 {
   - /* 1280x800 */
   - clock-frequency = 5;
   - hactive = 1280;
   - vactive = 800;
   - hfront-porch = 4;
   - hback-porch = 4;
   - hsync-len = 4;
   - vback-porch = 4;
   - vfront-porch = 4;
   - vsync-len = 4;
   + fimd@1440 {
   + status = okay;
   + display-timings {
   + native-mode = timing0;
   + timing0: timing@0 {
   + /* 1280x800 */
   + clock-frequency = 5;
   + hactive = 1280;
   + vactive = 800;
   + hfront-porch = 4;
   + hback-porch = 4;
   + hsync-len = 4;
   + vback-porch = 4;
   + vfront-porch = 4;
   + vsync-len = 4;
   + };
   
 };
 
 };
  
  Looks good to me, but I would like some other people from the device
  tree mailing list to comment on node naming: Do we want to conform to
  the recommendation of ePAPR about node naming, which states that node
  names should be generic, not platform specific or we are free to
  ignore it?
 The name of node looks good to me and the name had been being used for a
 long time

Like a lot of things used in device trees of ARM platforms, since we did 
not have any proper processes defined for creating device tree bindings 
and device trees themselves, including any recommended set of good 
practices.

We are now trying to define all of this and so it's time to rethink all 
the DT related things that has been added for ARM platforms since the time 
DT for ARM was introduced and make sure that everything is reasonable.

 , and if we change that now, that will cause the bigger
 confusion.

Still, I think this patch can go as is and node naming can be fixed in 
separate patches, including any other quirks of Exynos device trees.

So, for the whole series:

Reviewed-by: Tomasz Figa t.f...@samsung.com

Best regards,
Tomasz

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Re: [PATCH V4 1/4] ARM: dts: exynos5420: add i2s controllers

2013-08-14 Thread Tomasz Figa
On Wednesday 14 of August 2013 11:21:40 Padma Venkat wrote:
 Hi Tomasz,
 
 On Mon, Aug 12, 2013 at 10:32 PM, Tomasz Figa tomasz.f...@gmail.com 
wrote:
  On Monday 12 of August 2013 14:12:36 Mark Brown wrote:
  On Mon, Aug 12, 2013 at 01:41:23PM +0200, Tomasz Figa wrote:
   On Monday 12 of August 2013 12:34:48 Mark Brown wrote:
I'd expect that to interact badly with the pinmuxing - unless the
device is disabled it'll try to grab its pins on probe which is
not
going to be a good idea unless it is actually wired up for use in
the system.  Or is there some other mechanism for handling that?
   
   Ah, good point. Now I wonder whether pinctrl nodes shouldn't be
   considered board-specific and specified in board-level dts instead?
  
  It seems a bit cleaner to use the current mechanism in that it stops
  the device appearing at all and hence repeated efforts to probe,
  plus a simple enable is less error prone, the way these SoCs are
  designed you don't have to pick which pinmux is in use for most of
  the IPs.  Where there are multiple options it does seem like a good
  approach though.
  
  Tastes may differ though.
  
  Right, if this SoC has only one pinmux setting for this IP, then it's
  fine.
 
 Yes. This IP has only default pin configuration.
 
  Padmavathi, this was the only issue I spotted, so have my:
  
  Reviewed-by: Tomasz Figa t.f...@samsung.com
 
 Thanks for your review.

You're welcome.

Thanks for keeping up with this series and addressing all the comments. :)

Best regards,
Tomasz

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RE: [PATCH V6 1/4] ARM: dts: Add DP PHY node to exynos5250.dtsi

2013-08-14 Thread Kukjin Kim
Jingoo Han wrote:
 
 Add PHY provider node for the DP PHY.
 
 Signed-off-by: Jingoo Han jg1@samsung.com
 Reviewed-by: Tomasz Figa t.f...@samsung.com
 Acked-by: Felipe Balbi ba...@ti.com

Acked-by: Kukjin Kim kgene@samsung.com

Thanks,
Kukjin

 ---
  arch/arm/boot/dts/exynos5250.dtsi |   13 -
  1 file changed, 8 insertions(+), 5 deletions(-)
 
 diff --git a/arch/arm/boot/dts/exynos5250.dtsi
 b/arch/arm/boot/dts/exynos5250.dtsi
 index fc9fb3d..c326c06 100644
 --- a/arch/arm/boot/dts/exynos5250.dtsi
 +++ b/arch/arm/boot/dts/exynos5250.dtsi
 @@ -616,6 +616,12 @@
   interrupts = 0 94 0;
   };
 
 + dp_phy: video-phy@10040720 {
 + compatible = samsung,exynos5250-dp-video-phy;
 + reg = 0x10040720 4;
 + #phy-cells = 0;
 + };
 +
   dp-controller {
   compatible = samsung,exynos5-dp;
   reg = 0x145b 0x1000;
 @@ -623,11 +629,8 @@
   interrupt-parent = combiner;
   #address-cells = 1;
   #size-cells = 0;
 -
 - dptx-phy {
 - reg = 0x10040720;
 - samsung,enable-mask = 1;
 - };
 + phys = dp_phy;
 + phy-names = dp;
   };
 
   fimd {
 --
 1.7.10.4


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Re: [PATCH V4 0/4] Add i2s support on smdk5420

2013-08-14 Thread Tomasz Figa
On Tuesday 13 of August 2013 13:44:40 Mark Brown wrote:
 On Mon, Aug 12, 2013 at 03:19:50PM +0530, Padmavathi Venna wrote:
  Samsung has different versions of I2S introduced in different
  platforms. Each version has some new support added for multichannel,
  secondary fifo, s/w reset control, internal mux for rclk src clk and
  tdm support. Each newly added change has a quirk. So this patch adds
  all the required quirks as driver data and based on compatible string
  from dtsi fetches the quirks. This also adds i2s support on
  exynos5420.
 
 Applied all these, thanks.

Hmm, this series looks good to me too, except one thing. What about the 
bisection breakage introduced by the hole between patches 1/4 and 4/4 
(after the list of supported compatible changes in the driver and before 
respective dts files are updated)?

Best regards,
Tomasz


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Re: [PATCH v2 1/7] ARM: dts: Move display-timimg information inside FIMD DT node for exynos5250

2013-08-14 Thread Vikas Sajjan
Hi Tomasz,

On Wed, Aug 14, 2013 at 1:46 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
 On Wednesday 14 of August 2013 14:56:55 Kukjin Kim wrote:
 Tomasz Figa wrote:
  Hi Vikas,
 
  On Tuesday 30 of July 2013 16:49:32 Vikas Sajjan wrote:
   As the display-timing information is parsed by FIMD driver, it makes
   sense to move the display-timimg DT node inside FIMD DT node for
   exynos5250
  
   Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
   ---
  
arch/arm/boot/dts/exynos5250-smdk5250.dts |   29
  
   - 1 file changed, 16 insertions(+), 13
   deletions(-)
  
   diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
   b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 49f18c2..d176dbb
   100644
   --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
   +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
   @@ -262,19 +262,22 @@
  
 pinctrl-0 = dp_hpd;
  
 };
  
   - display-timings {
   - native-mode = timing0;
   - timing0: timing@0 {
   - /* 1280x800 */
   - clock-frequency = 5;
   - hactive = 1280;
   - vactive = 800;
   - hfront-porch = 4;
   - hback-porch = 4;
   - hsync-len = 4;
   - vback-porch = 4;
   - vfront-porch = 4;
   - vsync-len = 4;
   + fimd@1440 {
   + status = okay;
   + display-timings {
   + native-mode = timing0;
   + timing0: timing@0 {
   + /* 1280x800 */
   + clock-frequency = 5;
   + hactive = 1280;
   + vactive = 800;
   + hfront-porch = 4;
   + hback-porch = 4;
   + hsync-len = 4;
   + vback-porch = 4;
   + vfront-porch = 4;
   + vsync-len = 4;
   + };
  
 };
  
 };
 
  Looks good to me, but I would like some other people from the device
  tree mailing list to comment on node naming: Do we want to conform to
  the recommendation of ePAPR about node naming, which states that node
  names should be generic, not platform specific or we are free to
  ignore it?
 The name of node looks good to me and the name had been being used for a
 long time

 Like a lot of things used in device trees of ARM platforms, since we did
 not have any proper processes defined for creating device tree bindings
 and device trees themselves, including any recommended set of good
 practices.

 We are now trying to define all of this and so it's time to rethink all
 the DT related things that has been added for ARM platforms since the time
 DT for ARM was introduced and make sure that everything is reasonable.

 , and if we change that now, that will cause the bigger
 confusion.

 Still, I think this patch can go as is and node naming can be fixed in
 separate patches, including any other quirks of Exynos device trees.

 So, for the whole series:

 Reviewed-by: Tomasz Figa t.f...@samsung.com


Thanks for the review.


 Best regards,
 Tomasz

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Build failure on linux-next

2013-08-14 Thread Tushar Behera
Hi,

We are getting a build failure on today's linux-next (next-20130814)
with exynos_defconfig.

  DTC arch/arm/boot/dts/exynos5420-smdk5420.dtb
ERROR (phandle_references): Reference to non-existent node or label pdma1

ERROR (phandle_references): Reference to non-existent node or label pdma1

ERROR (phandle_references): Reference to non-existent node or label pdma0

ERROR (phandle_references): Reference to non-existent node or label pdma0

ERROR: Input tree has errors, aborting (use -f to force output)
make[1]: *** [arch/arm/boot/dts/exynos5420-smdk5420.dtb] Error 2
make: *** [dtbs] Error 2


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[PATCH 20/29] watchdog: s3c2410_wdt: simplify use of devm_ioremap_resource

2013-08-14 Thread Julia Lawall
From: Julia Lawall julia.law...@lip6.fr

Remove unneeded error handling on the result of a call to
platform_get_resource when the value is passed to devm_ioremap_resource.

Move the call to platform_get_resource adjacent to the call to
devm_ioremap_resource to make the connection between them more clear.

A simplified version of the semantic patch that makes this change is as
follows: (http://coccinelle.lip6.fr/)

// smpl
@@
expression pdev,res,n,e,e1;
expression ret != 0;
identifier l;
@@

- res = platform_get_resource(pdev, IORESOURCE_MEM, n);
  ... when != res
- if (res == NULL) { ... \(goto l;\|return ret;\) }
  ... when != res
+ res = platform_get_resource(pdev, IORESOURCE_MEM, n);
  e = devm_ioremap_resource(e1, res);
// /smpl

Signed-off-by: Julia Lawall julia.law...@lip6.fr

---
 drivers/watchdog/s3c2410_wdt.c |7 +--
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
index 6a22cf5..9fbc993 100644
--- a/drivers/watchdog/s3c2410_wdt.c
+++ b/drivers/watchdog/s3c2410_wdt.c
@@ -325,12 +325,6 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
dev = pdev-dev;
wdt_dev = pdev-dev;
 
-   wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-   if (wdt_mem == NULL) {
-   dev_err(dev, no memory resource specified\n);
-   return -ENOENT;
-   }
-
wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
if (wdt_irq == NULL) {
dev_err(dev, no irq resource specified\n);
@@ -339,6 +333,7 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
}
 
/* get the memory region for the watchdog timer */
+   wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
wdt_base = devm_ioremap_resource(dev, wdt_mem);
if (IS_ERR(wdt_base)) {
ret = PTR_ERR(wdt_base);

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[PATCH 0/29] simplify use of devm_ioremap_resource

2013-08-14 Thread Julia Lawall
devm_ioremap_resource often uses the result of a call to
platform_get_resource as its last argument.  devm_ioremap_resource does
appropriate error handling on this argument, so error handling can be
removed from the call site.  To make the connection between the call to
platform_get_resource and the call to devm_ioremap_resource more clear, the
former is also moved down to be adjacent to the latter.

In many cases, this patch changes the specific error value that is
returned on failure of platform_get_resource.

The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)

// smpl
@@
expression pdev,res,n,e,e1;
expression ret != 0;
identifier l;
@@

(
  res = platform_get_resource(pdev, IORESOURCE_MEM, n);
- if (res == NULL) { ... \(goto l;\|return ret;\) }
  e = devm_ioremap_resource(e1, res);
|
- res = platform_get_resource(pdev, IORESOURCE_MEM, n);
  ... when != res
- if (res == NULL) { ... \(goto l;\|return ret;\) }
  ... when != res
+ res = platform_get_resource(pdev, IORESOURCE_MEM, n);
  e = devm_ioremap_resource(e1, res);
)
// /smpl

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[PATCH 12/29] sound/soc/samsung/ac97.c: simplify use of devm_ioremap_resource

2013-08-14 Thread Julia Lawall
From: Julia Lawall julia.law...@lip6.fr

Remove unneeded error handling on the result of a call to
platform_get_resource when the value is passed to devm_ioremap_resource.

Move the call to platform_get_resource adjacent to the call to
devm_ioremap_resource to make the connection between them more clear.

A simplified version of the semantic patch that makes this change is as
follows: (http://coccinelle.lip6.fr/)

// smpl
@@
expression pdev,res,n,e,e1;
expression ret != 0;
identifier l;
@@

- res = platform_get_resource(pdev, IORESOURCE_MEM, n);
  ... when != res
- if (res == NULL) { ... \(goto l;\|return ret;\) }
  ... when != res
+ res = platform_get_resource(pdev, IORESOURCE_MEM, n);
  e = devm_ioremap_resource(e1, res);
// /smpl

Signed-off-by: Julia Lawall julia.law...@lip6.fr

---
 sound/soc/samsung/ac97.c |7 +--
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/sound/soc/samsung/ac97.c b/sound/soc/samsung/ac97.c
index 2dd623f..c732df9 100644
--- a/sound/soc/samsung/ac97.c
+++ b/sound/soc/samsung/ac97.c
@@ -404,18 +404,13 @@ static int s3c_ac97_probe(struct platform_device *pdev)
return -ENXIO;
}
 
-   mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-   if (!mem_res) {
-   dev_err(pdev-dev, Unable to get register resource\n);
-   return -ENXIO;
-   }
-
irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
if (!irq_res) {
dev_err(pdev-dev, AC97 IRQ not provided!\n);
return -ENXIO;
}
 
+   mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
s3c_ac97.regs = devm_ioremap_resource(pdev-dev, mem_res);
if (IS_ERR(s3c_ac97.regs))
return PTR_ERR(s3c_ac97.regs);

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RE: [PATCH 1/2] ARM: dts: Move the common DMA controller nodes to exynos5.dtsi

2013-08-14 Thread Kukjin Kim
Padmavathi Venna wrote:
 
 exynos5250 and exynos5420 has 4 DMA controllers in common. So this patch
 moves these nodes to common file keeping the dma controllers clk info in
 the exynos5250 dtsi file.
 
 Signed-off-by: Padmavathi Venna padm...@samsung.com
 ---
  arch/arm/boot/dts/exynos5.dtsi|   44
 +
  arch/arm/boot/dts/exynos5250.dtsi |   30 -
  2 files changed, 44 insertions(+), 30 deletions(-)
 
 diff --git a/arch/arm/boot/dts/exynos5.dtsi
 b/arch/arm/boot/dts/exynos5.dtsi
 index f65e124..cac35c8 100644
 --- a/arch/arm/boot/dts/exynos5.dtsi
 +++ b/arch/arm/boot/dts/exynos5.dtsi
 @@ -50,6 +50,50 @@
   interrupts = 1 9 0xf04;
   };
 
 + amba {
 + #address-cells = 1;
 + #size-cells = 1;
 + compatible = arm,amba-bus;
 + interrupt-parent = gic;
 + ranges;
 +
 + pdma0: pdma@121A {
 + compatible = arm,pl330, arm,primecell;
 + reg = 0x121A 0x1000;
 + interrupts = 0 34 0;
 + #dma-cells = 1;
 + #dma-channels = 8;
 + #dma-requests = 32;
 + };
 +
 + pdma1: pdma@121B {
 + compatible = arm,pl330, arm,primecell;
 + reg = 0x121B 0x1000;
 + interrupts = 0 35 0;
 + #dma-cells = 1;
 + #dma-channels = 8;
 + #dma-requests = 32;
 + };
 +
 + mdma0: mdma@1080 {
 + compatible = arm,pl330, arm,primecell;
 + reg = 0x1080 0x1000;
 + interrupts = 0 33 0;
 + #dma-cells = 1;
 + #dma-channels = 8;
 + #dma-requests = 1;
 + };
 +
 + mdma1: mdma@11C1 {
 + compatible = arm,pl330, arm,primecell;
 + reg = 0x11C1 0x1000;
 + interrupts = 0 124 0;
 + #dma-cells = 1;
 + #dma-channels = 8;
 + #dma-requests = 1;
 + };
 + };
 +
   dwmmc_0: dwmmc0@1220 {
   compatible = samsung,exynos5250-dw-mshc;
   interrupts = 0 75 0;
 diff --git a/arch/arm/boot/dts/exynos5250.dtsi
 b/arch/arm/boot/dts/exynos5250.dtsi
 index 41cd625..3a474c4 100644
 --- a/arch/arm/boot/dts/exynos5250.dtsi
 +++ b/arch/arm/boot/dts/exynos5250.dtsi
 @@ -511,54 +511,24 @@
   };
 
   amba {
 - #address-cells = 1;
 - #size-cells = 1;
 - compatible = arm,amba-bus;
 - interrupt-parent = gic;
 - ranges;
 -
   pdma0: pdma@121A {
 - compatible = arm,pl330, arm,primecell;
 - reg = 0x121A 0x1000;
 - interrupts = 0 34 0;
   clocks = clock 275;
   clock-names = apb_pclk;
 - #dma-cells = 1;
 - #dma-channels = 8;
 - #dma-requests = 32;
   };
 
   pdma1: pdma@121B {
 - compatible = arm,pl330, arm,primecell;
 - reg = 0x121B 0x1000;
 - interrupts = 0 35 0;
   clocks = clock 276;
   clock-names = apb_pclk;
 - #dma-cells = 1;
 - #dma-channels = 8;
 - #dma-requests = 32;
   };
 
   mdma0: mdma@1080 {
 - compatible = arm,pl330, arm,primecell;
 - reg = 0x1080 0x1000;
 - interrupts = 0 33 0;
   clocks = clock 271;
   clock-names = apb_pclk;
 - #dma-cells = 1;
 - #dma-channels = 8;
 - #dma-requests = 1;
   };
 
   mdma1: mdma@11C1 {
 - compatible = arm,pl330, arm,primecell;
 - reg = 0x11C1 0x1000;
 - interrupts = 0 124 0;
   clocks = clock 271;
   clock-names = apb_pclk;
 - #dma-cells = 1;
 - #dma-channels = 8;
 - #dma-requests = 1;
   };
   };
 
 --
 1.7.4.4

NAK, because the dmac addresses are different on upcoming exynos5 and there
are 2-mdma and only one pdma. So this change can make more complicated.

- Kukjin

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RE: [PATCH 2/2] ARM: dts: Add DMA controller node info on Exynos5420.

2013-08-14 Thread Kukjin Kim
Padmavathi Venna wrote:
 
 Exynos5420 has one separate DMA controller for I2S0 and PCM0. This patch
 adds the same node on exynos5420 dtsi and adds the DMA clk info for the
 remaining DMA controllers.
 
 Signed-off-by: Padmavathi Venna padm...@samsung.com
 ---
  arch/arm/boot/dts/exynos5420.dtsi |   33
+
  1 files changed, 33 insertions(+), 0 deletions(-)
 
 diff --git a/arch/arm/boot/dts/exynos5420.dtsi
 b/arch/arm/boot/dts/exynos5420.dtsi
 index a84f5f1..7035a4b 100644
 --- a/arch/arm/boot/dts/exynos5420.dtsi
 +++ b/arch/arm/boot/dts/exynos5420.dtsi
 @@ -137,6 +137,39 @@
   interrupts = 0 47 0;
   };
 
 + amba {
 + pdma0: pdma@121A {
 + clocks = clock 362;
 + clock-names = apb_pclk;
 + };
 +
 + pdma1: pdma@121B {
 + clocks = clock 363;
 + clock-names = apb_pclk;
 + };
 +
 + mdma0: mdma@1080 {
 + clocks = clock 473;
 + clock-names = apb_pclk;
 + };
 +
 + mdma1: mdma@11C1 {
 + clocks = clock 442;
 + clock-names = apb_pclk;
 + };
 +
 + adma: adma@0388 {
 + compatible = arm,pl330, arm,primecell;
 + reg = 0x0388 0x1000;
 + interrupts = 0 110 0;
 + clocks = clock_audss EXYNOS_ADMA;
 + clock-names = apb_pclk;
 + #dma-cells = 1;
 + #dma-channels = 6;
 + #dma-requests = 16;
 + };
 + };
 +
   serial@12C0 {
   clocks = clock 257, clock 128;
   clock-names = uart, clk_uart_baud0;
 --
 1.7.4.4

See my comments on 1st patch and you need to re-spin for dmac on exynos5420.

Thanks,
Kukjin

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[PATCH] ARM: dts: Enable USB hub on Arndale

2013-08-14 Thread Mark Brown
From: Mark Brown broo...@linaro.org

The Arndale has a SMSC USB3503 connected in hardware only mode like a PHY,
support it using the usb-nop-xceiv binding.

Note that due to a regrettable decision to use a regulator to represent
the reset signal this uses a fixed voltage regulator to do that, there
is a plan to use the reset controller binding once that is merged so it
does not seem worthwhile to fix the usb-nop-xceiv driver at this point.

Signed-off-by: Mark Brown broo...@linaro.org
---

This doesn't 100% work right now since we don't yet have a solution to
ensure that this gets started after the USB controller but those
modifications are small (or can be done at runtime with module loading).

 arch/arm/boot/dts/exynos5250-arndale.dts | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts 
b/arch/arm/boot/dts/exynos5250-arndale.dts
index 96d528d..e477e23 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -539,4 +539,22 @@
rtc {
status = okay;
};
+
+   usb_hub_bus {
+   compatible = simple-bus;
+   #address-cells = 1;
+   #size-cells = 0;
+
+   // SMSC USB3503 connected in hardware only mode as a PHY
+   usb_hub: usb_hub {
+   compatible = smsc,usb3503a;
+
+   reset-gpios = gpx3 5 1;
+   connect-gpios = gpd1 7 1;
+   };
+   };
+
+   usb@1211 {
+   usb-phy = usb2_phy;
+   };
 };
-- 
1.8.4.rc2

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RE: [PATCH v3 3/9] ARM: dts: exynos5250: move common i2c properties to exynos5 dtsi

2013-08-14 Thread Kukjin Kim
Rahul Sharma wrote:
 
 I2C nodes shares many properties across exynos5 SoCs (exynos5250
 and exyno5420). Common code is moved to exynos5.dtsi which is
 included in exyno5250 and exynos5420 SoC files.
 
 Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
 ---
  arch/arm/boot/dts/exynos5.dtsi|   36
 +
  arch/arm/boot/dts/exynos5250-arndale.dts  |1 +
  arch/arm/boot/dts/exynos5250-smdk5250.dts |3 +++
  arch/arm/boot/dts/exynos5250.dtsi |   20 
  4 files changed, 40 insertions(+), 20 deletions(-)
 
 diff --git a/arch/arm/boot/dts/exynos5.dtsi
 b/arch/arm/boot/dts/exynos5.dtsi
 index f65e124..1ae179e 100644
 --- a/arch/arm/boot/dts/exynos5.dtsi
 +++ b/arch/arm/boot/dts/exynos5.dtsi
 @@ -108,4 +108,40 @@
   interrupts = 0 42 0;
   status = disabled;
   };
 +
 + i2c_0: i2c@12C6 {
 + compatible = samsung,s3c2440-i2c;
 + reg = 0x12C6 0x100;
 + interrupts = 0 56 0;
 + #address-cells = 1;
 + #size-cells = 0;
 + status = disabled;
 + };
 +
 + i2c_1: i2c@12C7 {
 + compatible = samsung,s3c2440-i2c;
 + reg = 0x12C7 0x100;
 + interrupts = 0 57 0;
 + #address-cells = 1;
 + #size-cells = 0;
 + status = disabled;
 + };
 +
 + i2c_2: i2c@12C8 {
 + compatible = samsung,s3c2440-i2c;
 + reg = 0x12C8 0x100;
 + interrupts = 0 58 0;
 + #address-cells = 1;
 + #size-cells = 0;
 + status = disabled;
 + };
 +
 + i2c_3: i2c@12C9 {
 + compatible = samsung,s3c2440-i2c;
 + reg = 0x12C9 0x100;
 + interrupts = 0 59 0;
 + #address-cells = 1;
 + #size-cells = 0;
 + status = disabled;
 + };
  };
 diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
 b/arch/arm/boot/dts/exynos5250-arndale.dts
 index 96d528d..83ab780 100644
 --- a/arch/arm/boot/dts/exynos5250-arndale.dts
 +++ b/arch/arm/boot/dts/exynos5250-arndale.dts
 @@ -31,6 +31,7 @@
   };
 
   i2c@12C6 {
 + status = okay;
   samsung,i2c-sda-delay = 100;
   samsung,i2c-max-bus-freq = 2;
   samsung,i2c-slave-addr = 0x66;
 diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
 b/arch/arm/boot/dts/exynos5250-smdk5250.dts
 index 49f18c2..945e6cc 100644
 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
 +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
 @@ -28,6 +28,7 @@
   };
 
   i2c@12C6 {
 + status = okay;
   samsung,i2c-sda-delay = 100;
   samsung,i2c-max-bus-freq = 2;
 
 @@ -62,6 +63,7 @@
   };
 
   i2c@12C7 {
 + status = okay;
   samsung,i2c-sda-delay = 100;
   samsung,i2c-max-bus-freq = 2;
 
 @@ -101,6 +103,7 @@
   };
 
   i2c@12C8 {
 + status = okay;
   samsung,i2c-sda-delay = 100;
   samsung,i2c-max-bus-freq = 66000;
 
 diff --git a/arch/arm/boot/dts/exynos5250.dtsi
 b/arch/arm/boot/dts/exynos5250.dtsi
 index 93d6cc5..de54b38 100644
 --- a/arch/arm/boot/dts/exynos5250.dtsi
 +++ b/arch/arm/boot/dts/exynos5250.dtsi
 @@ -217,11 +217,6 @@
   };
 
   i2c_0: i2c@12C6 {
 - compatible = samsung,s3c2440-i2c;
 - reg = 0x12C6 0x100;
 - interrupts = 0 56 0;
 - #address-cells = 1;
 - #size-cells = 0;
   clocks = clock 294;
   clock-names = i2c;
   pinctrl-names = default;
 @@ -229,11 +224,6 @@
   };
 
   i2c_1: i2c@12C7 {
 - compatible = samsung,s3c2440-i2c;
 - reg = 0x12C7 0x100;
 - interrupts = 0 57 0;
 - #address-cells = 1;
 - #size-cells = 0;
   clocks = clock 295;
   clock-names = i2c;
   pinctrl-names = default;
 @@ -241,11 +231,6 @@
   };
 
   i2c_2: i2c@12C8 {
 - compatible = samsung,s3c2440-i2c;
 - reg = 0x12C8 0x100;
 - interrupts = 0 58 0;
 - #address-cells = 1;
 - #size-cells = 0;
   clocks = clock 296;
   clock-names = i2c;
   pinctrl-names = default;
 @@ -253,11 +238,6 @@
   };
 
   i2c_3: i2c@12C9 {
 - compatible = samsung,s3c2440-i2c;
 - reg = 0x12C9 0x100;
 - interrupts = 0 59 0;
 - #address-cells = 1;
 - #size-cells = 0;
   clocks = clock 297;
   clock-names = i2c;
   pinctrl-names = default;
 --
 1.7.10.4

NAK, there are 8 I2C channels with different address on upcoming exynos5 so
this change is not acceptable. Note please check at least upcoming SoC
before making common something if 

Re: [PATCH V4 0/4] Add i2s support on smdk5420

2013-08-14 Thread Mark Brown
On Wed, Aug 14, 2013 at 10:25:27AM +0200, Tomasz Figa wrote:

 Hmm, this series looks good to me too, except one thing. What about the 
 bisection breakage introduced by the hole between patches 1/4 and 4/4 
 (after the list of supported compatible changes in the driver and before 
 respective dts files are updated)?

It's annoying but relatively localised and obvious rather than the cross
tree stuff that happens so frequently with these platforms.


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Description: Digital signature


RE: [PATCH v3 5/9] ARM: dts: exynos5250: move common hdmi properties to exynos5 dtsi

2013-08-14 Thread Kukjin Kim
Rahul Sharma wrote:
 
 Hdmi Subsystem nodes shares many properties across exynos5 SoCs
 (exynos5250 and exyno5420). Common code is moved to exynos5.dtsi
 which is included in exyno5250 and exynos5420 SoC files.
 
 It also renames the hdmi and mixer nodes as per dt naming
 convention in the format name@phy_add.
 
 Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
 ---
  arch/arm/boot/dts/cros5250-common.dtsi|2 +-
  arch/arm/boot/dts/exynos5.dtsi|   12 
  arch/arm/boot/dts/exynos5250-arndale.dts  |7 ++-
  arch/arm/boot/dts/exynos5250-smdk5250.dts |7 ++-
  arch/arm/boot/dts/exynos5250-snow.dts |8 
  arch/arm/boot/dts/exynos5250.dtsi |8 ++--
  6 files changed, 35 insertions(+), 9 deletions(-)
 
 diff --git a/arch/arm/boot/dts/cros5250-common.dtsi
 b/arch/arm/boot/dts/cros5250-common.dtsi
 index dc259e8b..bef56fa 100644
 --- a/arch/arm/boot/dts/cros5250-common.dtsi
 +++ b/arch/arm/boot/dts/cros5250-common.dtsi
 @@ -299,7 +299,7 @@
   status = disabled;
   };
 
 - hdmi {
 + hdmi@1453 {
   hpd-gpio = gpx3 7 0;
   };
 
 diff --git a/arch/arm/boot/dts/exynos5.dtsi
 b/arch/arm/boot/dts/exynos5.dtsi
 index 1ae179e..dcb4943 100644
 --- a/arch/arm/boot/dts/exynos5.dtsi
 +++ b/arch/arm/boot/dts/exynos5.dtsi
 @@ -144,4 +144,16 @@
   #size-cells = 0;
   status = disabled;
   };
 +
 + hdmi@1453 {
 + reg = 0x1453 0x7;
 + interrupts = 0 95 0;
 + status = disabled;
 + };
 +
 + mixer@1445 {
 + reg = 0x1445 0x1;
 + interrupts = 0 94 0;
 + status = disabled;
 + };
  };
 diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
 b/arch/arm/boot/dts/exynos5250-arndale.dts
 index 83ab780..955ecfc 100644
 --- a/arch/arm/boot/dts/exynos5250-arndale.dts
 +++ b/arch/arm/boot/dts/exynos5250-arndale.dts
 @@ -471,13 +471,18 @@
   };
   };
 
 - hdmi {
 + hdmi@1453 {
 + status = okay;
   hpd-gpio = gpx3 7 2;
   vdd_osc-supply = ldo10_reg;
   vdd_pll-supply = ldo8_reg;
   vdd-supply = ldo8_reg;
   };
 
 + mixer@1445 {
 + status = okay;
 + };
 +
   regulators {
   compatible = simple-bus;
   #address-cells = 1;
 diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
 b/arch/arm/boot/dts/exynos5250-smdk5250.dts
 index 945e6cc..1cce2e8 100644
 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
 +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
 @@ -221,10 +221,15 @@
   status = disabled;
   };
 
 - hdmi {
 + hdmi@1453 {
 + status = okay;
   hpd-gpio = gpx3 7 0;
   };
 
 + mixer@1445 {
 + status = okay;
 + };
 +
   codec@1100 {
   samsung,mfc-r = 0x4300 0x80;
   samsung,mfc-l = 0x5100 0x80;
 diff --git a/arch/arm/boot/dts/exynos5250-snow.dts
 b/arch/arm/boot/dts/exynos5250-snow.dts
 index e79331d..b1378af 100644
 --- a/arch/arm/boot/dts/exynos5250-snow.dts
 +++ b/arch/arm/boot/dts/exynos5250-snow.dts
 @@ -196,4 +196,12 @@
   clock-frequency = 2400;
   };
   };
 +
 + hdmi@1453 {
 + status = okay;
 + };
 +
 + mixer@1445 {
 + status = okay;
 + };
  };
 diff --git a/arch/arm/boot/dts/exynos5250.dtsi
 b/arch/arm/boot/dts/exynos5250.dtsi
 index de54b38..f587cd7 100644
 --- a/arch/arm/boot/dts/exynos5250.dtsi
 +++ b/arch/arm/boot/dts/exynos5250.dtsi
 @@ -578,20 +578,16 @@
   clock-names = gscl;
   };
 
 - hdmi {
 + hdmi@1453 {
   compatible = samsung,exynos4212-hdmi;
 - reg = 0x1453 0x7;
 - interrupts = 0 95 0;
   clocks = clock 344, clock 136, clock 137,
   clock 159, clock 1024;
   clock-names = hdmi, sclk_hdmi, sclk_pixel,
   sclk_hdmiphy, mout_hdmi;
   };
 
 - mixer {
 + mixer@1445 {
   compatible = samsung,exynos5250-mixer;
 - reg = 0x1445 0x1;
 - interrupts = 0 94 0;
   clocks = clock 343, clock 136;
   clock-names = mixer, sclk_hdmi;
   };
 --
 1.7.10.4

NAK, again because of same reason with previous my comments. Note, different
addresses and IRQ# on upcoming exynos5 SoC.

- Kukjin

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RE: [PATCH v3 0/9] ARM: dts: exynos: add support for hdmi subsystem

2013-08-14 Thread Kukjin Kim
Rahul Sharma wrote:
 
 Common properties for I2C and Hdmi Subsystem is moved to exynos5
 dtsi file. It also adds Device tree nodes and clocks information
 for exynos5420 and exynos5250 SoCs. It adds pinctrl node for hdmi
 hpd gpio and update binding documents.
 
 This set is based on kukjin's for-next branch at
 http://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git.
 
 v3:
 1) Rebase to kgene for-next based on 3.11-rc1.
 2) Changes clock numbers as per updated clocks file for
 exyno5250 and exynos5420.
 3) Dropped Sachin patch as already got merged.
 
 v2:
 1) Added patch for moving common i2c properties to exynos5.dtsi
 2) Added patch for moving common hdmi, mixer properties to exynos5.dtsi
 3) moved hpd pinctrl node to board file.
 4) Added Sachin's patch to update binding document for hdmi with hpd
 information.
 
 Andrew Bresticker (1):
   ARM: dts: exynos5420: add i2c device nodes
 
 Rahul Sharma (7):
   ARM: dts: exynos5250: add clocks to hdmi dt node
   ARM: dts: exynos5250: move common i2c properties to exynos5 dtsi
   ARM: dts: exynos5250: move common hdmi properties to exynos5 dtsi
   ARM: dts: exynos5420: add dt nodes for hdmi subsystem
   ARM: dts: exynos5420: add clocks for hdmi subsystem
   ARM: dts: exynos5420: add hdmi hpd gpio pinctrl node
   of/documentation: update with clock information for exynos hdmi
 subsystem
 
 Sean Paul (1):
   ARM: dts: exynos5250: add mixer clocks to mixer node
 
  .../devicetree/bindings/video/exynos_hdmi.txt  |   14 +-
  .../devicetree/bindings/video/exynos_mixer.txt |4 ++
  arch/arm/boot/dts/cros5250-common.dtsi |2 +-
  arch/arm/boot/dts/exynos5.dtsi |   48

  arch/arm/boot/dts/exynos5250-arndale.dts   |8 +++-
  arch/arm/boot/dts/exynos5250-smdk5250.dts  |   10 +++-
  arch/arm/boot/dts/exynos5250-snow.dts  |8 
  arch/arm/boot/dts/exynos5250.dtsi  |   36 +++
  arch/arm/boot/dts/exynos5420-smdk5420.dts  |   31 +
  arch/arm/boot/dts/exynos5420.dtsi  |   46
+++
  10 files changed, 174 insertions(+), 33 deletions(-)
 
 --
 1.7.10.4

See my comments about making common stuff for exynos5 SoCs.

And please don't use title like following,

'ARM: dts: exynos: '.

Because the relatively long prefix of title can cover _real_ title, So just
'ARM: dts:  in exynos000' is better.

One more, devicetree(at)vger.kernel.org is right for dt ml.

- Kukjin

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RE: [PATCH v2] clk: Exynos5250: Add clocks for G3D

2013-08-14 Thread Kukjin Kim
Mike Turquette wrote:
 
 Quoting Kukjin Kim (2013-06-19 06:36:47)
  On 05/27/13 16:20, Arun Kumar K wrote:
   This patch adds the required clocks for ARM Mali IP
   in Exynos5250.
  
   Signed-off-by: Arun Kumar Karun...@samsung.com
 
  (+ Mike)
 
  Looks good to me.
 
  Mike, I'd like take this into samsung tree for v3.11, if you have any
  concerns, please let me know.
 
 Looks good to me too!  Ack.
 
Probably, missed this in a last. But this cannot be merged without updating 
based on latest Mike's tree.

Arun, please re-spin this with my ack so that Mike could take for upcoming 
merge window. Note there is no dependency with samsung tree now :)

Thanks,
Kukjin

 
 
  Thanks,
  - Kukjin
 
   ---
   Changes from v1
   - Removed exporting of parent DIV clock for g3d
  as per Tomsz Figa's comment.
   ---
 .../devicetree/bindings/clock/exynos5250-clock.txt |1 +
 drivers/clk/samsung/clk-exynos5250.c   |   12
 +++-
 2 files changed, 12 insertions(+), 1 deletion(-)
  
   diff --git a/Documentation/devicetree/bindings/clock/exynos5250-
 clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
   index 1a05761..b3700cf 100644
   --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
   +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
   @@ -155,6 +155,7 @@ clock which they consume.
   dp342
   mixer 343
   hdmi  344
   +  g3d345
  
 Example 1: An example of a clock controller node is listed below.
  
   diff --git a/drivers/clk/samsung/clk-exynos5250.c
 b/drivers/clk/samsung/clk-exynos5250.c
   index 5c97e75..0d52c19 100644
   --- a/drivers/clk/samsung/clk-exynos5250.c
   +++ b/drivers/clk/samsung/clk-exynos5250.c
   @@ -23,6 +23,7 @@
 #define DIV_CPU00x500
 #define SRC_CORE1   0x4204
 #define SRC_TOP00x10210
   +#define SRC_TOP1 0x10214
 #define SRC_TOP20x10218
 #define SRC_GSCL0x10220
 #define SRC_DISP1_0 0x1022c
   @@ -55,6 +56,7 @@
 #define DIV_PERIC5  0x1056c
 #define GATE_IP_GSCL0x10920
 #define GATE_IP_MFC 0x1092c
   +#define GATE_IP_G3D  0x10930
 #define GATE_IP_GEN 0x10934
 #define GATE_IP_FSYS0x10944
 #define GATE_IP_PERIC   0x10950
   @@ -98,7 +100,7 @@ enum exynos5250_clks {
 spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1,
 hsi2c2,
 hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0,
 tzpc1,
 tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec,
 mct,
   - wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi,
   + wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g3d,
  
 nr_clks,
 };
   @@ -112,6 +114,7 @@ static __initdata unsigned long
 exynos5250_clk_regs[] = {
 DIV_CPU0,
 SRC_CORE1,
 SRC_TOP0,
   + SRC_TOP1,
 SRC_TOP2,
 SRC_GSCL,
 SRC_DISP1_0,
   @@ -164,10 +167,12 @@ PNAME(mout_vpllsrc_p)   = { fin_pll,
 sclk_hdmi27m };
 PNAME(mout_vpll_p)  = { mout_vpllsrc, fout_vpll };
 PNAME(mout_cpll_p)  = { fin_pll, fout_cpll };
 PNAME(mout_epll_p)  = { fin_pll, fout_epll };
   +PNAME(mout_gpll_p)   = { fin_pll, fout_gpll };
 PNAME(mout_mpll_user_p) = { fin_pll, sclk_mpll };
 PNAME(mout_bpll_user_p) = { fin_pll, sclk_bpll };
 PNAME(mout_aclk166_p)   = { sclk_cpll, sclk_mpll_user };
 PNAME(mout_aclk200_p)   = { sclk_mpll_user, sclk_bpll_user };
   +PNAME(mout_aclk400_p)= { aclk_400_g3d_mid, sclk_gpll };
 PNAME(mout_hdmi_p)  = { div_hdmi_pixel, sclk_hdmiphy };
 PNAME(mout_usb3_p)  = { sclk_mpll_user, sclk_cpll };
 PNAME(mout_group1_p)= { fin_pll, fin_pll, sclk_hdmi27m,
   @@ -223,6 +228,9 @@ struct samsung_mux_clock exynos5250_mux_clks[]
 __initdata = {
 MUX(none, mout_aclk166, mout_aclk166_p, SRC_TOP0, 8, 1),
 MUX(none, mout_aclk333, mout_aclk166_p, SRC_TOP0, 16, 1),
 MUX(none, mout_aclk200, mout_aclk200_p, SRC_TOP0, 12, 1),
   + MUX(none, aclk_400_g3d_mid, mout_aclk200_p, SRC_TOP0, 20, 1),
   + MUX(none, sclk_gpll, mout_gpll_p, SRC_TOP2, 28, 1),
   + MUX(none, mout_aclk400, mout_aclk400_p, SRC_TOP1, 28, 1),
 MUX(none, mout_cam_bayer, mout_group1_p, SRC_GSCL, 12, 4),
 MUX(none, mout_cam0, mout_group1_p, SRC_GSCL, 16, 4),
 MUX(none, mout_cam1, mout_group1_p, SRC_GSCL, 20, 4),
   @@ -262,6 +270,7 @@ struct samsung_div_clock exynos5250_div_clks[]
 __initdata = {
 DIV(none, aclk166, mout_aclk166, DIV_TOP0, 8, 3),
 DIV(none, aclk333, mout_aclk333, DIV_TOP0, 20, 3),
 DIV(none, aclk200, mout_aclk200, DIV_TOP0, 12, 3),
   + DIV(none, aclk_400_g3d, mout_aclk400, DIV_TOP0, 24, 3),
 DIV(none, div_cam_bayer, 

Re: [PATCH] ARM: dts: Enable USB hub on Arndale

2013-08-14 Thread Tushar Behera
On 14 August 2013 15:28, Mark Brown broo...@kernel.org wrote:
 From: Mark Brown broo...@linaro.org

 The Arndale has a SMSC USB3503 connected in hardware only mode like a PHY,
 support it using the usb-nop-xceiv binding.

 Note that due to a regrettable decision to use a regulator to represent
 the reset signal this uses a fixed voltage regulator to do that, there
 is a plan to use the reset controller binding once that is merged so it
 does not seem worthwhile to fix the usb-nop-xceiv driver at this point.

 Signed-off-by: Mark Brown broo...@linaro.org
 ---

 This doesn't 100% work right now since we don't yet have a solution to
 ensure that this gets started after the USB controller but those
 modifications are small (or can be done at runtime with module loading).

  arch/arm/boot/dts/exynos5250-arndale.dts | 18 ++
  1 file changed, 18 insertions(+)

 diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts 
 b/arch/arm/boot/dts/exynos5250-arndale.dts
 index 96d528d..e477e23 100644
 --- a/arch/arm/boot/dts/exynos5250-arndale.dts
 +++ b/arch/arm/boot/dts/exynos5250-arndale.dts
 @@ -539,4 +539,22 @@
 rtc {
 status = okay;
 };
 +
 +   usb_hub_bus {
 +   compatible = simple-bus;
 +   #address-cells = 1;
 +   #size-cells = 0;
 +
 +   // SMSC USB3503 connected in hardware only mode as a PHY
 +   usb_hub: usb_hub {
 +   compatible = smsc,usb3503a;
 +
 +   reset-gpios = gpx3 5 1;
 +   connect-gpios = gpd1 7 1;
 +   };
 +   };
 +


 +   usb@1211 {
 +   usb-phy = usb2_phy;
 +   };

ehci-s5p driver doesn't use 'usb-phy' property to find the PHY driver,
hence this is not required.

Without this change,
Tested-by: Tushar Behera tushar.beh...@linaro.org

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RE: [PATCH v2 0/5] DT/ARCH updates for MFC

2013-08-14 Thread Kukjin Kim
Arun Kumar K wrote:
 
 The patch series updates the DT nodes of MFC in Exynos4,
 Exynos 5250 and creates node in 5420. Also updates the
 memory reserve in exynos5 for mfc-v7.
 
 Changes from v1:
 - Made status disabled in dtsi and enable in dts
   as suggested by Sachin Kamat.
 - Moved common properties to exynos5.dtsi as
   suggested by Chander.
 - Updated binding documentation for special clk removal
 - Updated exynos4 dtsi
 
 Arun Kumar K (5):
   ARM: dts: Update clocks entry in MFC binding documentation
   ARM: dts: Remove unsused MFC clock from exynos4
   ARM: dts: Update 5250 MFC node
   ARM: dts: Add MFC node for exynos 5420
   ARM: EXYNOS: Add mfc-v7 to memory reserve
 
  .../devicetree/bindings/media/s5p-mfc.txt  |   10 +-
  arch/arm/boot/dts/exynos4.dtsi |4 ++--
  arch/arm/boot/dts/exynos5.dtsi |5 +
  arch/arm/boot/dts/exynos5250.dtsi  |4 ++--
  arch/arm/boot/dts/exynos5420-smdk5420.dts  |6 ++
  arch/arm/boot/dts/exynos5420.dtsi  |7 +++
  arch/arm/mach-exynos/mach-exynos5-dt.c |   14 +-
  7 files changed, 36 insertions(+), 14 deletions(-)
 
 --
 1.7.9.5

Basically, looks good to me except making common stuff into the
exynos5.dtsi. Because as I commented on another thread, upcoming exynos5 has
different address and IRQ# for mfc. So please respin so that this could be
merged for v3.12.

Thanks,
Kukjin

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Re: [PATCH] ARM: dts: Enable USB hub on Arndale

2013-08-14 Thread Mark Brown
On Wed, Aug 14, 2013 at 04:00:16PM +0530, Tushar Behera wrote:
 On 14 August 2013 15:28, Mark Brown broo...@kernel.org wrote:

  +   usb@1211 {
  +   usb-phy = usb2_phy;
  +   };

 ehci-s5p driver doesn't use 'usb-phy' property to find the PHY driver,
 hence this is not required.

I added that for documentation since it is actually what gets used - the
obvious way of handing this is for the hub to be treated like a PHY but
that doesn't work since we actually need the built in PHY to talk to the
hub.  Though I did mean it to be a separate patch.


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Re: [PATCH v2] clk: Exynos5250: Add clocks for G3D

2013-08-14 Thread Arun Kumar K
Hi Kukjin,

On Wed, Aug 14, 2013 at 3:53 PM, Kukjin Kim kg...@kernel.org wrote:
 Mike Turquette wrote:

 Quoting Kukjin Kim (2013-06-19 06:36:47)
  On 05/27/13 16:20, Arun Kumar K wrote:
   This patch adds the required clocks for ARM Mali IP
   in Exynos5250.
  
   Signed-off-by: Arun Kumar Karun...@samsung.com
 
  (+ Mike)
 
  Looks good to me.
 
  Mike, I'd like take this into samsung tree for v3.11, if you have any
  concerns, please let me know.

 Looks good to me too!  Ack.

 Probably, missed this in a last. But this cannot be merged without updating 
 based on latest Mike's tree.

 Arun, please re-spin this with my ack so that Mike could take for upcoming 
 merge window. Note there is no dependency with samsung tree now :)


Ok. I will post it again with your ack.

Thanks and regards
Arun
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Re: [PATCH v9 03/16] iommu/exynos: fix page table maintenance

2013-08-14 Thread Joerg Roedel
On Thu, Aug 08, 2013 at 11:28:44AM -0700, Grant Grundler wrote:
 I can't speak to the previous BUG_ON(). I believe the EADDRESSINUSE
 failures could be either WARN_ON or BUG_ON.   This condition is
 clearly a bug in the generic IOMMU allocator and I think that's why
 KyongHo Cho used BUG_ON.
 
 Handing out duplicate addresses will generally lead to some sort of
 data corruption or other fault depending on how robust the underlying
 device drivers are written.  So my preference is a BUG_ON to
 immediately flag this condition instead of hoping a device driver will
 correctly handling the dma mapping failure (Some do, most currently
 don't).
 
 WARN_ON() + return -EADDRESSINUSE would be a good alternative.

Even if it is a real BUG condition, I don't think it is worth to stop
execution at this point. It makes debugging harder and the system less
reliable. I prefer to go with the WARN_ON and an error return value.


Joerg


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Re: [PATCH v9 04/16] iommu/exynos: allocate lv2 page table from own slab

2013-08-14 Thread 'Joerg Roedel'
On Fri, Aug 09, 2013 at 09:55:30AM +0200, Tomasz Figa wrote:
 Oh, this is a valid point, but it was more a nitpick about the coding 
 style. Single path error handling (with goto) is widely used in the kernel 
 in cases when more than one thing has to be undone and so I suggested this 
 method of error handling here as well.

I agree with that review from Tomasz, the error-handling should look
similar to all the other places in the kernel and use goto.


Joerg


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[PATCH V3 2/2] ARM: dts: Fix the RTC DT node name for Exynos5250 SoC

2013-08-14 Thread Vikas Sajjan
Fixes the RTC DT node name for Exynos5250 SoC and also makes status of the
node as okay.

Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
---
 arch/arm/boot/dts/exynos5250.dtsi |3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index 88589b7..c82137b 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -178,9 +178,10 @@
samsung,power-domain = pd_mfc;
};
 
-   rtc {
+   rtc@101E {
clocks = clock 337;
clock-names = rtc;
+   status = okay;
};
 
tmu@1006 {
-- 
1.7.9.5

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[PATCH v3] clk: Exynos5250: Add clocks for G3D

2013-08-14 Thread Arun Kumar K
This patch adds the required clocks for ARM Mali IP
in Exynos5250.

Signed-off-by: Arun Kumar K arun...@samsung.com
Acked-by: Mike Turquette mturque...@linaro.org
Acked-by: Kukjin Kim kgene@samsung.com
---
Changes from v2
- Rebased on clk-next
Changes from v1
- Removed exporting of parent DIV clock for g3d
  as per Tomsz Figa's comment.
---
 .../devicetree/bindings/clock/exynos5250-clock.txt |1 +
 drivers/clk/samsung/clk-exynos5250.c   |   12 +++-
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt 
b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
index 24765c1..bb3dd95 100644
--- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -159,6 +159,7 @@ clock which they consume.
   mixer343
   hdmi 344
   g2d  345
+  g3d  346
 
 
[Clock Muxes]
diff --git a/drivers/clk/samsung/clk-exynos5250.c 
b/drivers/clk/samsung/clk-exynos5250.c
index a9916a4..892a5ac 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -34,6 +34,7 @@
 #define VPLL_CON0  0x10140
 #define GPLL_CON0  0x10150
 #define SRC_TOP0   0x10210
+#define SRC_TOP1   0x10214
 #define SRC_TOP2   0x10218
 #define SRC_GSCL   0x10220
 #define SRC_DISP1_00x1022c
@@ -66,6 +67,7 @@
 #define DIV_PERIC5 0x1056c
 #define GATE_IP_GSCL   0x10920
 #define GATE_IP_MFC0x1092c
+#define GATE_IP_G3D0x10930
 #define GATE_IP_GEN0x10934
 #define GATE_IP_FSYS   0x10944
 #define GATE_IP_PERIC  0x10950
@@ -120,7 +122,7 @@ enum exynos5250_clks {
spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
-   wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d,
+   wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d, g3d,
 
/* mux clocks */
mout_hdmi = 1024,
@@ -137,6 +139,7 @@ static unsigned long exynos5250_clk_regs[] __initdata = {
DIV_CPU0,
SRC_CORE1,
SRC_TOP0,
+   SRC_TOP1,
SRC_TOP2,
SRC_GSCL,
SRC_DISP1_0,
@@ -190,10 +193,12 @@ PNAME(mout_vpllsrc_p) = { fin_pll, sclk_hdmi27m };
 PNAME(mout_vpll_p) = { mout_vpllsrc, fout_vpll };
 PNAME(mout_cpll_p) = { fin_pll, fout_cpll };
 PNAME(mout_epll_p) = { fin_pll, fout_epll };
+PNAME(mout_gpll_p) = { fin_pll, fout_gpll };
 PNAME(mout_mpll_user_p)= { fin_pll, sclk_mpll };
 PNAME(mout_bpll_user_p)= { fin_pll, sclk_bpll };
 PNAME(mout_aclk166_p)  = { sclk_cpll, sclk_mpll_user };
 PNAME(mout_aclk200_p)  = { sclk_mpll_user, sclk_bpll_user };
+PNAME(mout_aclk400_p)  = { aclk_400_g3d_mid, sclk_gpll };
 PNAME(mout_hdmi_p) = { div_hdmi_pixel, sclk_hdmiphy };
 PNAME(mout_usb3_p) = { sclk_mpll_user, sclk_cpll };
 PNAME(mout_group1_p)   = { fin_pll, fin_pll, sclk_hdmi27m,
@@ -252,6 +257,9 @@ static struct samsung_mux_clock exynos5250_mux_clks[] 
__initdata = {
MUX(none, mout_aclk166, mout_aclk166_p, SRC_TOP0, 8, 1),
MUX(none, mout_aclk333, mout_aclk166_p, SRC_TOP0, 16, 1),
MUX(none, mout_aclk200, mout_aclk200_p, SRC_TOP0, 12, 1),
+   MUX(none, aclk_400_g3d_mid, mout_aclk200_p, SRC_TOP0, 20, 1),
+   MUX(none, sclk_gpll, mout_gpll_p, SRC_TOP2, 28, 1),
+   MUX(none, mout_aclk400, mout_aclk400_p, SRC_TOP1, 28, 1),
MUX(none, mout_cam_bayer, mout_group1_p, SRC_GSCL, 12, 4),
MUX(none, mout_cam0, mout_group1_p, SRC_GSCL, 16, 4),
MUX(none, mout_cam1, mout_group1_p, SRC_GSCL, 20, 4),
@@ -291,6 +299,7 @@ static struct samsung_div_clock exynos5250_div_clks[] 
__initdata = {
DIV(none, aclk166, mout_aclk166, DIV_TOP0, 8, 3),
DIV(none, aclk333, mout_aclk333, DIV_TOP0, 20, 3),
DIV(none, aclk200, mout_aclk200, DIV_TOP0, 12, 3),
+   DIV(none, aclk_400_g3d, mout_aclk400, DIV_TOP0, 24, 3),
DIV(none, div_cam_bayer, mout_cam_bayer, DIV_GSCL, 12, 4),
DIV(none, div_cam0, mout_cam0, DIV_GSCL, 16, 4),
DIV(none, div_cam1, mout_cam1, DIV_GSCL, 20, 4),
@@ -492,6 +501,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] 
__initdata = {
GATE(mixer, mixer, aclk200, GATE_IP_DISP1, 5, 0, 0),
GATE(hdmi, hdmi, aclk200, GATE_IP_DISP1, 6, 0, 0),
GATE(g2d, g2d, aclk200, GATE_IP_ACP, 3, 0, 0),
+   GATE(g3d, g3d, aclk_400_g3d, GATE_IP_G3D, 0, 0, 0),
 };
 
 static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = {
-- 
1.7.9.5

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More 

Re: [PATCH v3 0/9] ARM: dts: exynos: add support for hdmi subsystem

2013-08-14 Thread Tomasz Figa
On Wednesday 14 of August 2013 19:11:39 Kukjin Kim wrote:
 Rahul Sharma wrote:
  Common properties for I2C and Hdmi Subsystem is moved to exynos5
  dtsi file. It also adds Device tree nodes and clocks information
  for exynos5420 and exynos5250 SoCs. It adds pinctrl node for hdmi
  hpd gpio and update binding documents.
  
  This set is based on kukjin's for-next branch at
  http://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git.
  
  v3:
  1) Rebase to kgene for-next based on 3.11-rc1.
  2) Changes clock numbers as per updated clocks file for
  exyno5250 and exynos5420.
  3) Dropped Sachin patch as already got merged.
  
  v2:
  1) Added patch for moving common i2c properties to exynos5.dtsi
  2) Added patch for moving common hdmi, mixer properties to exynos5.dtsi
  3) moved hpd pinctrl node to board file.
  4) Added Sachin's patch to update binding document for hdmi with hpd
  information.
  
  Andrew Bresticker (1):
ARM: dts: exynos5420: add i2c device nodes
  
  Rahul Sharma (7):
ARM: dts: exynos5250: add clocks to hdmi dt node
ARM: dts: exynos5250: move common i2c properties to exynos5 dtsi
ARM: dts: exynos5250: move common hdmi properties to exynos5 dtsi
ARM: dts: exynos5420: add dt nodes for hdmi subsystem
ARM: dts: exynos5420: add clocks for hdmi subsystem
ARM: dts: exynos5420: add hdmi hpd gpio pinctrl node
of/documentation: update with clock information for exynos hdmi

  subsystem
  
  Sean Paul (1):
ARM: dts: exynos5250: add mixer clocks to mixer node
   
   .../devicetree/bindings/video/exynos_hdmi.txt  |   14 +-
   .../devicetree/bindings/video/exynos_mixer.txt |4 ++
   arch/arm/boot/dts/cros5250-common.dtsi |2 +-
   arch/arm/boot/dts/exynos5.dtsi |   48
 
 
 
   arch/arm/boot/dts/exynos5250-arndale.dts   |8 +++-
   arch/arm/boot/dts/exynos5250-smdk5250.dts  |   10 +++-
   arch/arm/boot/dts/exynos5250-snow.dts  |8 
   arch/arm/boot/dts/exynos5250.dtsi  |   36
   +++ arch/arm/boot/dts/exynos5420-smdk5420.dts  | 
31 + arch/arm/boot/dts/exynos5420.dtsi 
   |   46
 
 +++
 
   10 files changed, 174 insertions(+), 33 deletions(-)
  
  --
  1.7.10.4
 
 See my comments about making common stuff for exynos5 SoCs.

I agree.

 And please don't use title like following,
 
 'ARM: dts: exynos: '.
 
 Because the relatively long prefix of title can cover _real_ title, So
 just 'ARM: dts:  in exynos000' is better.

Well, I tend to disagree on this. The ARM: dts: platform name: prefix is 
commonly used in arch/arm/boot/dts (see git log --oneline 
arch/arm/boot/dts).

As long as we don't cross the ~75 characters boundary in patch subject, I 
don't think this is any problem.

 
 One more, devicetree(at)vger.kernel.org is right for dt ml.
+1

Also it is nice to Cc the device tree maintainers.

Best regards,
Tomasz

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Re: [PATCH V3 0/2] Add RTC DT node to Exynos5420 SoC and Fix RTC DT node name for 5250 Soc

2013-08-14 Thread Tomasz Figa
Hi Vikas,

On Wednesday 14 of August 2013 16:32:59 Vikas Sajjan wrote:
 changes since v2:
   - split the 5250 related modifications into a separate patch.

I'm not sure whether Kukjin's comment was about this, as it introduces a 
short bisect breakage between patch 1 and patch 2 from this series.

IMHO it would be more sensible to make first patch simply fix name of the 
node and then a separate patch adding the rtc node for exynos5420.

Best regards,
Tomasz

   - placed the RTC node as per the alphabetical order in the DTS file as
   suggested by Kukjin Kim kg...@kernel.org.
 
 changes since v1:
   - made DT node status as okay in the dtsi file itself.
 -
 Vikas Sajjan (2):
   ARM: dts: Add RTC DT node to Exynos5420 SoC
   ARM: dts: Fix the RTC DT node name for Exynos5250 SoC
 
  arch/arm/boot/dts/exynos5.dtsi|2 +-
  arch/arm/boot/dts/exynos5250.dtsi |3 ++-
  arch/arm/boot/dts/exynos5420.dtsi |6 ++
  3 files changed, 9 insertions(+), 2 deletions(-)
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[PATCH v3 3/4] ARM: dts: Update 5250 MFC node

2013-08-14 Thread Arun Kumar K
The patch adds the MFC clock entry for the 5250 SoC.

Signed-off-by: Arun Kumar K arun...@samsung.com
---
 arch/arm/boot/dts/exynos5250.dtsi |2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index 88589b7..7c7b0d2 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -176,6 +176,8 @@
reg = 0x1100 0x1;
interrupts = 0 96 0;
samsung,power-domain = pd_mfc;
+   clocks = clock 266;
+   clock-names = mfc;
};
 
rtc {
-- 
1.7.9.5

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[PATCH v3 0/4] DT/ARCH updates for MFC

2013-08-14 Thread Arun Kumar K
The patch series updates the DT nodes of MFC in Exynos4,
Exynos 5250 and creates node in 5420.
The memory reservation patch for MFC v7 firmware is omitted
in this series as its no longer needed after the new CMA DT
framework by Marek Szyprowski.

Changes from v2:
- Removed register and interrupt properties from common
exynos5.dtsi file as per Kukjin Kim's suggestion.
- Dropped v7 memory reservation patch

Changes from v1:
- Made status disabled in dtsi and enable in dts
as suggested by Sachin Kamat.
- Moved common properties to exynos5.dtsi as
suggested by Chander.
- Updated binding documentation for special clk removal
- Updated exynos4 dtsi

Arun Kumar K (4):
  ARM: dts: Update clocks entry in MFC binding documentation
  ARM: dts: Remove unsused MFC clock from exynos4
  ARM: dts: Update 5250 MFC node
  ARM: dts: Add MFC node for exynos 5420

 .../devicetree/bindings/media/s5p-mfc.txt  |   10 +-
 arch/arm/boot/dts/exynos4.dtsi |4 ++--
 arch/arm/boot/dts/exynos5250.dtsi  |2 ++
 arch/arm/boot/dts/exynos5420.dtsi  |8 
 4 files changed, 17 insertions(+), 7 deletions(-)

-- 
1.7.9.5

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[PATCH v3 2/4] ARM: dts: Remove unsused MFC clock from exynos4

2013-08-14 Thread Arun Kumar K
Removes the unused sclk_mfc from exynos4 dtsi file.

Signed-off-by: Arun Kumar K arun...@samsung.com
---
 arch/arm/boot/dts/exynos4.dtsi |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 597cfcf..42aa0c9 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -248,8 +248,8 @@
reg = 0x1340 0x1;
interrupts = 0 94 0;
samsung,power-domain = pd_mfc;
-   clocks = clock 170, clock 273;
-   clock-names = sclk_mfc, mfc;
+   clocks = clock 273;
+   clock-names = mfc;
status = disabled;
};
 
-- 
1.7.9.5

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[PATCH v3 4/4] ARM: dts: Add MFC node for exynos 5420

2013-08-14 Thread Arun Kumar K
The patch adds MFC nodes for exynos 5420.

Signed-off-by: Arun Kumar K arun...@samsung.com
---
 arch/arm/boot/dts/exynos5420.dtsi |8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
b/arch/arm/boot/dts/exynos5420.dtsi
index 9e90d1e..bbf71e9 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -65,6 +65,14 @@
#clock-cells = 1;
};
 
+   codec@1100 {
+   compatible = samsung,mfc-v7;
+   reg = 0x1100 0x1;
+   interrupts = 0 96 0;
+   clocks = clock 401;
+   clock-names = mfc;
+   };
+
mct@101C {
compatible = samsung,exynos4210-mct;
reg = 0x101C 0x800;
-- 
1.7.9.5

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[PATCH v3 1/4] ARM: dts: Update clocks entry in MFC binding documentation

2013-08-14 Thread Arun Kumar K
MFC driver is updated to use only one clock instead of
two. Correcting this in the binding documentation.

Signed-off-by: Arun Kumar K arun...@samsung.com
---
 .../devicetree/bindings/media/s5p-mfc.txt  |   10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt 
b/Documentation/devicetree/bindings/media/s5p-mfc.txt
index df37b02..d75c3e5 100644
--- a/Documentation/devicetree/bindings/media/s5p-mfc.txt
+++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
@@ -15,9 +15,9 @@ Required properties:
  mapped region.
 
   - interrupts : MFC interrupt number to the CPU.
-  - clocks : from common clock binding: handle to mfc clocks.
-  - clock-names : from common clock binding: must contain sclk_mfc and mfc,
- corresponding to entries in the clocks property.
+  - clocks : from common clock binding: handle to mfc clock.
+  - clock-names : from common clock binding: must contain mfc,
+ corresponding to entry in the clocks property.
 
   - samsung,mfc-r : Base address of the first memory bank used by MFC
for DMA contiguous memory allocation and its size.
@@ -37,8 +37,8 @@ mfc: codec@1340 {
reg = 0x1340 0x1;
interrupts = 0 94 0;
samsung,power-domain = pd_mfc;
-   clocks = clock 170, clock 273;
-   clock-names = sclk_mfc, mfc;
+   clocks = clock 273;
+   clock-names = mfc;
 };
 
 Board specific DT entry:
-- 
1.7.9.5

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[PATCH v2 0/4] ARM: S3C24XX: add dmaengine based dma-driver

2013-08-14 Thread Heiko Stübner
This series tries to provide a basic dmaengine driver for the s3c24xx
SoCs to subsequently retire the old one with custom API.

Since v1 three big changes happened (appart from fixing received comments):

For one the limitation of sg-lists to 1 element is gone.Secondly the
specifics of the virtual channels (target bus, handshake, etc) are not
encoded with channel ids but in the platformdata - making a later dt
binding easier, as these informations can there be gathered by the xlate
function. And lastly I also added a preliminary mechanism to handle the
specific needs for the earlier variants of the driver.

While s3c2443 and later can use any channel for any peripheral with just
marking the target-peripheral-id in a register, earlier SoCs can only use
specific channels and the target-ids also vary depending on the channel.

Therefore on newer SoCs the chansel element only needs to contain the
requested target-id, while on the older variants use it to encode both
the valid channels and the channel-specific peripheral-id.

On affected SoCs the target-id is always 3 bit wide, so we use these and
an additional 4th bit to hold the valid state. As the older SoCs all have
4 dma channels this can live happily in an u16 element.

The s3c24xx series will most likely not see any new offspring, but even
if it happens any new model will probably use the newer more flexible
variant of the dma controller, so this should not restrict anything
in the future.

Example:
SDI is valid on channels 0, 2 and 3 - with varying hw request sources.
For it the chansel field would look like

 ((BIT(3) | 1)  3 * 4) | // channel 3, with request source 1
 ((BIT(3) | 2)  2 * 4) | // channel 2, with request source 2
 ((BIT(3) | 2)  0 * 4)   // channel 0, with request source 2


Heiko Stuebner (4):
  ARM: S3C24XX: number the dma clocks
  dmaengine: add driver for Samsung s3c24xx SoCs
  ARM: S3C24XX: add platform-devices for new dma driver for s3c2412 and
s3c2443
  ARM: SAMSUNG: set s3c24xx_dma_filter for s3c64xx-spi0 device

 arch/arm/mach-s3c24xx/clock-s3c2412.c |8 +-
 arch/arm/mach-s3c24xx/common-s3c2443.c|   12 +-
 arch/arm/mach-s3c24xx/common.c|  106 +++
 arch/arm/mach-s3c24xx/common.h|3 +
 arch/arm/mach-s3c24xx/mach-jive.c |1 +
 arch/arm/mach-s3c24xx/mach-smdk2413.c |1 +
 arch/arm/mach-s3c24xx/mach-smdk2416.c |1 +
 arch/arm/mach-s3c24xx/mach-smdk2443.c |1 +
 arch/arm/mach-s3c24xx/mach-vstms.c|1 +
 arch/arm/plat-samsung/devs.c  |5 +-
 drivers/dma/Kconfig   |   12 +
 drivers/dma/Makefile  |1 +
 drivers/dma/s3c24xx-dma.c | 1255 +
 include/linux/platform_data/dma-s3c24xx.h |   43 +
 14 files changed, 1439 insertions(+), 11 deletions(-)
 create mode 100644 drivers/dma/s3c24xx-dma.c
 create mode 100644 include/linux/platform_data/dma-s3c24xx.h

-- 
1.7.10.4

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[PATCH v2 2/4] dmaengine: add driver for Samsung s3c24xx SoCs

2013-08-14 Thread Heiko Stübner
This adds a new driver to support the s3c24xx dma using the dmaengine
and makes the old one in mach-s3c24xx obsolete in the long run.

Conceptually the s3c24xx-dma feels like a distant relative of the pl08x
with numerous virtual channels being mapped to a lot less physical ones.
The driver therefore borrows a lot from the amba-pl08x driver in this
regard. Functionality-wise the driver gains a memcpy ability in addition
to the slave_sg one.

The driver supports both the method for requesting the peripheral used
by SoCs before the S3C2443 and the different method for S3C2443 and later.

On earlier SoCs the hardware channels usable for specific peripherals is
constrainted while on later SoCs all channels can be used for any peripheral.

Tested on a s3c2416-based board, memcpy using the dmatest module and
slave_sg partially using the spi-s3c64xx driver.

Signed-off-by: Heiko Stuebner he...@sntech.de
---
changes since v1:
- address comments from Linus Walleij
- support sg-lists with more than 1 element
- add support for earlier s3c24xx SoCs
- redo the channeldata definitions:
  - no need for static ids for the virtual channels
  - provide a way to encode constraints for earlier variants
  - better base for later dt bindings

@LinusW: I didn't keep your ack, due to the bigger changes, but feel free
   to re-ack if it still looks alright :-)
 
 drivers/dma/Kconfig   |   12 +
 drivers/dma/Makefile  |1 +
 drivers/dma/s3c24xx-dma.c | 1255 +
 include/linux/platform_data/dma-s3c24xx.h |   43 +
 4 files changed, 1311 insertions(+)
 create mode 100644 drivers/dma/s3c24xx-dma.c
 create mode 100644 include/linux/platform_data/dma-s3c24xx.h

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 6825957..27729c8 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -154,6 +154,18 @@ config TEGRA20_APB_DMA
  This DMA controller transfers data from memory to peripheral fifo
  or vice versa. It does not support memory to memory data transfer.
 
+config S3C24XX_DMAC
+   tristate Samsung S3C24XX DMA support
+   depends on ARCH_S3C24XX  !S3C24XX_DMA
+   select DMA_ENGINE
+   select DMA_VIRTUAL_CHANNELS
+   help
+ Support for the Samsung S3C24XX DMA controller driver. The
+ DMA controller is having multiple DMA channels which can be
+ configured for different peripherals like audio, UART, SPI.
+ The DMA controller can transfer data from memory to peripheral,
+ periphal to memory, periphal to periphal and memory to memory.
+
 source drivers/dma/sh/Kconfig
 
 config COH901318
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 5e0f2ef..5c1655a 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_SIRF_DMA) += sirf-dma.o
 obj-$(CONFIG_TI_EDMA) += edma.o
 obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
 obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o
+obj-$(CONFIG_S3C24XX_DMAC) += s3c24xx-dma.o
 obj-$(CONFIG_PL330_DMA) += pl330.o
 obj-$(CONFIG_PCH_DMA) += pch_dma.o
 obj-$(CONFIG_AMBA_PL08X) += amba-pl08x.o
diff --git a/drivers/dma/s3c24xx-dma.c b/drivers/dma/s3c24xx-dma.c
new file mode 100644
index 000..e4ecd94
--- /dev/null
+++ b/drivers/dma/s3c24xx-dma.c
@@ -0,0 +1,1255 @@
+/*
+ * S3C24XX DMA handling
+ *
+ * Copyright (c) 2013 Heiko Stuebner he...@sntech.de
+ *
+ * based on amba-pl08x.c
+ *
+ * Copyright (c) 2006 ARM Ltd.
+ * Copyright (c) 2010 ST-Ericsson SA
+ *
+ * Author: Peter Pearse peter.pea...@arm.com
+ * Author: Linus Walleij linus.wall...@stericsson.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * The DMA controllers in S3C24XX SoCs have a varying number of DMA signals
+ * that can be routed to any of the 4 to 8 hardware-channels.
+ *
+ * Therefore on these DMA controllers the number of channels
+ * and the number of incoming DMA signals are two totally different things.
+ * It is usually not possible to theoretically handle all physical signals,
+ * so a multiplexing scheme with possible denial of use is necessary.
+ *
+ * Open items:
+ * - bursts
+ */
+
+#include linux/platform_device.h
+#include linux/types.h
+#include linux/dmaengine.h
+#include linux/dma-mapping.h
+#include linux/interrupt.h
+#include linux/clk.h
+#include linux/module.h
+#include linux/slab.h
+#include linux/platform_data/dma-s3c24xx.h
+
+#include dmaengine.h
+#include virt-dma.h
+
+#define MAX_DMA_CHANNELS   8
+
+#define DISRC  (0x00)
+#define DISRCC (0x04)
+#define DISRCC_INC_INCREMENT   (0  0)
+#define DISRCC_INC_FIXED   (1  0)
+#define DISRCC_LOC_AHB (0  1)
+#define DISRCC_LOC_APB (1  1)
+
+#define DIDST  (0x08)

[PATCH v2 4/4] ARM: SAMSUNG: set s3c24xx_dma_filter for s3c64xx-spi0 device

2013-08-14 Thread Heiko Stübner
The spi-s3c64xx device is also used on the s3c2416 and s3c2443 SoCs.
The driver also already uses only generic dma-engine operations.

Therefore add another elif to set the s3c24xx filter.

Signed-off-by: Heiko Stuebner he...@sntech.de
---
 arch/arm/plat-samsung/devs.c |5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 0f9c3f4..fab458f 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -32,6 +32,7 @@
 #include linux/ioport.h
 #include linux/platform_data/s3c-hsudc.h
 #include linux/platform_data/s3c-hsotg.h
+#include linux/platform_data/dma-s3c24xx.h
 
 #include media/s5p_hdmi.h
 
@@ -1513,8 +1514,10 @@ void __init s3c64xx_spi0_set_platdata(int 
(*cfg_gpio)(void), int src_clk_nr,
pd.num_cs = num_cs;
pd.src_clk_nr = src_clk_nr;
pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio;
-#ifdef CONFIG_PL330_DMA
+#if defined(CONFIG_PL330_DMA)
pd.filter = pl330_filter;
+#elif defined(CONFIG_S3C24XX_DMAC)
+   pd.filter = s3c24xx_dma_filter;
 #endif
 
s3c_set_platdata(pd, sizeof(pd), s3c64xx_device_spi0);
-- 
1.7.10.4

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[PATCH v2 3/4] ARM: S3C24XX: add platform-devices for new dma driver for s3c2412 and s3c2443

2013-08-14 Thread Heiko Stübner
This includes defining the mapping for the request sources.

Signed-off-by: Heiko Stuebner he...@sntech.de
---
changes since v1:
- follow new pdata definition

 arch/arm/mach-s3c24xx/common.c|  106 +
 arch/arm/mach-s3c24xx/common.h|3 +
 arch/arm/mach-s3c24xx/mach-jive.c |1 +
 arch/arm/mach-s3c24xx/mach-smdk2413.c |1 +
 arch/arm/mach-s3c24xx/mach-smdk2416.c |1 +
 arch/arm/mach-s3c24xx/mach-smdk2443.c |1 +
 arch/arm/mach-s3c24xx/mach-vstms.c|1 +
 7 files changed, 114 insertions(+)

diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index c157103..6e19167 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -30,6 +30,7 @@
 #include linux/platform_device.h
 #include linux/delay.h
 #include linux/io.h
+#include linux/platform_data/dma-s3c24xx.h
 
 #include mach/hardware.h
 #include mach/regs-clock.h
@@ -43,6 +44,7 @@
 
 #include mach/regs-gpio.h
 #include plat/regs-serial.h
+#include mach/dma.h
 
 #include plat/cpu.h
 #include plat/devs.h
@@ -302,3 +304,107 @@ void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long 
fclk,
clk_p.rate = pclk;
clk_f.rate = fclk;
 }
+
+#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
+defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
+static struct resource s3c2410_dma_resource[] = {
+   [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
+   [1] = DEFINE_RES_IRQ(IRQ_DMA0),
+   [2] = DEFINE_RES_IRQ(IRQ_DMA1),
+   [3] = DEFINE_RES_IRQ(IRQ_DMA2),
+   [4] = DEFINE_RES_IRQ(IRQ_DMA3),
+};
+#endif
+
+#ifdef CONFIG_CPU_S3C2412
+static struct s3c24xx_dma_channel s3c2412_dma_channels[DMACH_MAX] = {
+   [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 },
+   [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 },
+   [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 },
+   [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 },
+   [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 },
+   [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 },
+   [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 },
+   [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 },
+   [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 },
+   [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 },
+   [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 },
+   [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 },
+   [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 },
+   [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 },
+   [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 },
+   [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 },
+   [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, 13 },
+   [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, 14 },
+   [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, 15 },
+   [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, 16 },
+};
+
+static struct s3c24xx_dma_platdata s3c2412_dma_platdata = {
+   .num_phy_channels = 4,
+   .channels = s3c2412_dma_channels,
+   .num_channels = DMACH_MAX,
+};
+
+struct platform_device s3c2412_device_dma = {
+   .name   = s3c2412-dma,
+   .id = 0,
+   .num_resources  = ARRAY_SIZE(s3c2410_dma_resource),
+   .resource   = s3c2410_dma_resource,
+   .dev= {
+   .platform_data  = s3c2412_dma_platdata,
+   },
+};
+#endif
+
+#if defined(CONFIG_CPUS_3C2443) || defined(CONFIG_CPU_S3C2416)
+static struct resource s3c2443_dma_resource[] = {
+   [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
+   [1] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA0),
+   [2] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA1),
+   [3] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA2),
+   [4] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA3),
+   [5] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA4),
+   [6] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA5),
+};
+
+static struct s3c24xx_dma_channel s3c2443_dma_channels[DMACH_MAX] = {
+   [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 },
+   [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 },
+   [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 },
+   [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 },
+   [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 },
+   [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 },
+   [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 },
+   [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 },
+   [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 },
+   [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 },
+   [DMACH_UART3] = { S3C24XX_DMA_APB, true, 25 },
+   [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 },
+   [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 },
+   [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 },
+   [DMACH_UART3_SRC2] = { S3C24XX_DMA_APB, true, 26 },
+   [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 },
+   [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 },
+   [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 },
+   [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, 28 },
+   

[PATCH v2 1/4] ARM: S3C24XX: number the dma clocks

2013-08-14 Thread Heiko Stübner
Each dma channel has its own clock. The upcoming dma driver wants to
handle these itself and therefore needs to be able to get the correct
clock for a channel.

Therefore rename the dma clocks to dma.X for s3c2412, s3c2416 and
s3c2443. This does not change the behaviour for the old dma driver at
all, as all dma clocks are still always on and not handled by the old
dma driver at all.

Signed-off-by: Heiko Stuebner he...@sntech.de
are always enabled in the original code.
---
 arch/arm/mach-s3c24xx/clock-s3c2412.c  |8 
 arch/arm/mach-s3c24xx/common-s3c2443.c |   12 ++--
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-s3c24xx/clock-s3c2412.c 
b/arch/arm/mach-s3c24xx/clock-s3c2412.c
index 2cc017d..26e2bdc 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2412.c
@@ -484,22 +484,22 @@ static struct clk init_clocks_disable[] = {
 
 static struct clk init_clocks[] = {
{
-   .name   = dma,
+   .name   = dma.0,
.parent = clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit= S3C2412_CLKCON_DMA0,
}, {
-   .name   = dma,
+   .name   = dma.1,
.parent = clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit= S3C2412_CLKCON_DMA1,
}, {
-   .name   = dma,
+   .name   = dma.2,
.parent = clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit= S3C2412_CLKCON_DMA2,
}, {
-   .name   = dma,
+   .name   = dma.3,
.parent = clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit= S3C2412_CLKCON_DMA3,
diff --git a/arch/arm/mach-s3c24xx/common-s3c2443.c 
b/arch/arm/mach-s3c24xx/common-s3c2443.c
index f6b9f2e..65d3eef 100644
--- a/arch/arm/mach-s3c24xx/common-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/common-s3c2443.c
@@ -438,32 +438,32 @@ static struct clk init_clocks_off[] = {
 
 static struct clk init_clocks[] = {
{
-   .name   = dma,
+   .name   = dma.0,
.parent = clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit= S3C2443_HCLKCON_DMA0,
}, {
-   .name   = dma,
+   .name   = dma.1,
.parent = clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit= S3C2443_HCLKCON_DMA1,
}, {
-   .name   = dma,
+   .name   = dma.2,
.parent = clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit= S3C2443_HCLKCON_DMA2,
}, {
-   .name   = dma,
+   .name   = dma.3,
.parent = clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit= S3C2443_HCLKCON_DMA3,
}, {
-   .name   = dma,
+   .name   = dma.4,
.parent = clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit= S3C2443_HCLKCON_DMA4,
}, {
-   .name   = dma,
+   .name   = dma.5,
.parent = clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit= S3C2443_HCLKCON_DMA5,
-- 
1.7.10.4

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[PATCH V2] ARM: dts: Add DMA controller node info on Exynos5420.

2013-08-14 Thread Padmavathi Venna
This patch adds dma controller node info on Exynos5420.

Signed-off-by: Padmavathi Venna padm...@samsung.com
---

Changes since V1:
- In V1, dma node common stuff was added in common exynos5.dtsi file. 
  This was removed as per Kukjin comment and added in exynos5420.dtsi.

This patch is dependent on audss clk controller patches that were
posted in the below link.
http://www.spinics.net/lists/linux-samsung-soc/msg20253.html

 arch/arm/boot/dts/exynos5420.dtsi |   63 +
 1 files changed, 63 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
b/arch/arm/boot/dts/exynos5420.dtsi
index 9e90d1e..23cfea4 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -126,6 +126,69 @@
interrupts = 0 47 0;
};
 
+   amba {
+   #address-cells = 1;
+   #size-cells = 1;
+   compatible = arm,amba-bus;
+   interrupt-parent = gic;
+   ranges;
+
+   pdma0: pdma@121A {
+   compatible = arm,pl330, arm,primecell;
+   reg = 0x121A 0x1000;
+   interrupts = 0 34 0;
+   clocks = clock 362;
+   clock-names = apb_pclk;
+   #dma-cells = 1;
+   #dma-channels = 8;
+   #dma-requests = 32;
+   };
+
+   pdma1: pdma@121B {
+   compatible = arm,pl330, arm,primecell;
+   reg = 0x121B 0x1000;
+   interrupts = 0 35 0;
+   clocks = clock 363;
+   clock-names = apb_pclk;
+   #dma-cells = 1;
+   #dma-channels = 8;
+   #dma-requests = 32;
+   };
+
+   mdma0: mdma@1080 {
+   compatible = arm,pl330, arm,primecell;
+   reg = 0x1080 0x1000;
+   interrupts = 0 33 0;
+   clocks = clock 473;
+   clock-names = apb_pclk;
+   #dma-cells = 1;
+   #dma-channels = 8;
+   #dma-requests = 1;
+   };
+
+   mdma1: mdma@11C1 {
+   compatible = arm,pl330, arm,primecell;
+   reg = 0x11C1 0x1000;
+   interrupts = 0 124 0;
+   clocks = clock 442;
+   clock-names = apb_pclk;
+   #dma-cells = 1;
+   #dma-channels = 8;
+   #dma-requests = 1;
+   };
+
+   adma: adma@0388 {
+   compatible = arm,pl330, arm,primecell;
+   reg = 0x0388 0x1000;
+   interrupts = 0 110 0;
+   clocks = clock_audss EXYNOS_ADMA;
+   clock-names = apb_pclk;
+   #dma-cells = 1;
+   #dma-channels = 6;
+   #dma-requests = 16;
+   };
+   };
+
serial@12C0 {
clocks = clock 257, clock 128;
clock-names = uart, clk_uart_baud0;
-- 
1.7.4.4

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Re: [PATCH V3 0/2] Add RTC DT node to Exynos5420 SoC and Fix RTC DT node name for 5250 Soc

2013-08-14 Thread Vikas Sajjan
Hi Tomasz,

On 14 August 2013 17:00, Tomasz Figa t.f...@samsung.com wrote:
 Hi Vikas,

 On Wednesday 14 of August 2013 16:32:59 Vikas Sajjan wrote:
 changes since v2:
   - split the 5250 related modifications into a separate patch.

 I'm not sure whether Kukjin's comment was about this, as it introduces a
 short bisect breakage between patch 1 and patch 2 from this series.

 IMHO it would be more sensible to make first patch simply fix name of the
 node and then a separate patch adding the rtc node for exynos5420.


Are you saying that
patch 1: should contain modifications for exynos5.dtsi and
exynos5250.dtsi   ( basically the RTC name change and status as
okay)
patch 2: should contain modifications only for exynos5420.dtsi ( new
RTC DT node )


 Best regards,
 Tomasz

   - placed the RTC node as per the alphabetical order in the DTS file as
   suggested by Kukjin Kim kg...@kernel.org.

 changes since v1:
   - made DT node status as okay in the dtsi file itself.
 -
 Vikas Sajjan (2):
   ARM: dts: Add RTC DT node to Exynos5420 SoC
   ARM: dts: Fix the RTC DT node name for Exynos5250 SoC

  arch/arm/boot/dts/exynos5.dtsi|2 +-
  arch/arm/boot/dts/exynos5250.dtsi |3 ++-
  arch/arm/boot/dts/exynos5420.dtsi |6 ++
  3 files changed, 9 insertions(+), 2 deletions(-)



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 Vikas Sajjan
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[PATCH 2/2] ARM: dts: Add dwmmc nodes in SOC specific dts file

2013-08-14 Thread Yuvaraj Kumar C D
Exynos5 series SOC's have different versions of DWMMC controller.
So dwmmc device nodes moved from Exynos5 SOC's common dts file to
SOC specific dts file.

Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
---
 arch/arm/boot/dts/exynos5250.dtsi |   12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index 88589b7..ae0d852 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -385,18 +385,30 @@
};
 
dwmmc_0: dwmmc0@1220 {
+   compatible = samsung,exynos5250-dw-mshc;
+   interrupts = 0 75 0;
+   #address-cells = 1;
+   #size-cells = 0;
reg = 0x1220 0x1000;
clocks = clock 280, clock 139;
clock-names = biu, ciu;
};
 
dwmmc_1: dwmmc1@1221 {
+   compatible = samsung,exynos5250-dw-mshc;
+   interrupts = 0 76 0;
+   #address-cells = 1;
+   #size-cells = 0;
reg = 0x1221 0x1000;
clocks = clock 281, clock 140;
clock-names = biu, ciu;
};
 
dwmmc_2: dwmmc2@1222 {
+   compatible = samsung,exynos5250-dw-mshc;
+   interrupts = 0 77 0;
+   #address-cells = 1;
+   #size-cells = 0;
reg = 0x1222 0x1000;
clocks = clock 282, clock 141;
clock-names = biu, ciu;
-- 
1.7.9.5

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[PATCH 1/2] ARM: dts: remove dwmmc nodes from exynos5 common dts file.

2013-08-14 Thread Yuvaraj Kumar C D
Exynos5 series SOC's 5250 and 5420 have different versions of
DWMMC controller.So there is a new compatible string to distinguish
between them.So these nodes should be moved out of Exynos5 series
common device tree source.

Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
---
 arch/arm/boot/dts/exynos5.dtsi |   21 -
 1 file changed, 21 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index f65e124..c9fea70 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -50,27 +50,6 @@
interrupts = 1 9 0xf04;
};
 
-   dwmmc_0: dwmmc0@1220 {
-   compatible = samsung,exynos5250-dw-mshc;
-   interrupts = 0 75 0;
-   #address-cells = 1;
-   #size-cells = 0;
-   };
-
-   dwmmc_1: dwmmc1@1221 {
-   compatible = samsung,exynos5250-dw-mshc;
-   interrupts = 0 76 0;
-   #address-cells = 1;
-   #size-cells = 0;
-   };
-
-   dwmmc_2: dwmmc2@1222 {
-   compatible = samsung,exynos5250-dw-mshc;
-   interrupts = 0 77 0;
-   #address-cells = 1;
-   #size-cells = 0;
-   };
-
serial@12C0 {
compatible = samsung,exynos4210-uart;
reg = 0x12C0 0x100;
-- 
1.7.9.5

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Re: [PATCH V3 0/2] Add RTC DT node to Exynos5420 SoC and Fix RTC DT node name for 5250 Soc

2013-08-14 Thread Tomasz Figa
On Wednesday 14 of August 2013 17:37:47 Vikas Sajjan wrote:
 Hi Tomasz,
 
 On 14 August 2013 17:00, Tomasz Figa t.f...@samsung.com wrote:
  Hi Vikas,
  
  On Wednesday 14 of August 2013 16:32:59 Vikas Sajjan wrote:
  changes since v2:
- split the 5250 related modifications into a separate patch.
  
  I'm not sure whether Kukjin's comment was about this, as it introduces
  a
  short bisect breakage between patch 1 and patch 2 from this series.
  
  IMHO it would be more sensible to make first patch simply fix name of
  the node and then a separate patch adding the rtc node for exynos5420.
 Are you saying that
 patch 1: should contain modifications for exynos5.dtsi and
 exynos5250.dtsi   ( basically the RTC name change and status as
 okay)
 patch 2: should contain modifications only for exynos5420.dtsi ( new
 RTC DT node )

Oh, I forgot about the status property. So ideally there should be 3 
patches:
 - patch 1 changing exynos5.dtsi and exynos5250.dtsi to fix RTC node name,
 - patch 2 adding status=okay to exynos5250.dtsi,
 - patch 3 adding RTC node to exynos5420.dtsi.

Best regards,
Tomasz

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Re: [PATCH v3] clk: Exynos5250: Add clocks for G3D

2013-08-14 Thread Tomasz Figa
Hi Arun,

On Wednesday 14 of August 2013 16:40:05 Arun Kumar K wrote:
 This patch adds the required clocks for ARM Mali IP
 in Exynos5250.
 
 Signed-off-by: Arun Kumar K arun...@samsung.com
 Acked-by: Mike Turquette mturque...@linaro.org
 Acked-by: Kukjin Kim kgene@samsung.com
 ---
 Changes from v2
 - Rebased on clk-next
 Changes from v1
 - Removed exporting of parent DIV clock for g3d
   as per Tomsz Figa's comment.
 ---
  .../devicetree/bindings/clock/exynos5250-clock.txt |1 +
  drivers/clk/samsung/clk-exynos5250.c   |   12 +++-
  2 files changed, 12 insertions(+), 1 deletion(-)
 
 diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
 b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt index
 24765c1..bb3dd95 100644
 --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
 +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
 @@ -159,6 +159,7 @@ clock which they consume.
mixer  343
hdmi   344
g2d345
 +  g3d346
 
 
 [Clock Muxes]
 diff --git a/drivers/clk/samsung/clk-exynos5250.c
 b/drivers/clk/samsung/clk-exynos5250.c index a9916a4..892a5ac 100644
 --- a/drivers/clk/samsung/clk-exynos5250.c
 +++ b/drivers/clk/samsung/clk-exynos5250.c
 @@ -34,6 +34,7 @@
  #define VPLL_CON00x10140
  #define GPLL_CON00x10150
  #define SRC_TOP0 0x10210
 +#define SRC_TOP1 0x10214
  #define SRC_TOP2 0x10218
  #define SRC_GSCL 0x10220
  #define SRC_DISP1_0  0x1022c
 @@ -66,6 +67,7 @@
  #define DIV_PERIC5   0x1056c
  #define GATE_IP_GSCL 0x10920
  #define GATE_IP_MFC  0x1092c
 +#define GATE_IP_G3D  0x10930
  #define GATE_IP_GEN  0x10934
  #define GATE_IP_FSYS 0x10944
  #define GATE_IP_PERIC0x10950
 @@ -120,7 +122,7 @@ enum exynos5250_clks {
   spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
 hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
 tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
 - wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d,
 + wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d, g3d,
 
   /* mux clocks */
   mout_hdmi = 1024,
 @@ -137,6 +139,7 @@ static unsigned long exynos5250_clk_regs[] __initdata
 = { DIV_CPU0,
   SRC_CORE1,
   SRC_TOP0,
 + SRC_TOP1,
   SRC_TOP2,
   SRC_GSCL,
   SRC_DISP1_0,
 @@ -190,10 +193,12 @@ PNAME(mout_vpllsrc_p)   = { fin_pll, 
sclk_hdmi27m
 }; PNAME(mout_vpll_p) = { mout_vpllsrc, fout_vpll };
  PNAME(mout_cpll_p)   = { fin_pll, fout_cpll };
  PNAME(mout_epll_p)   = { fin_pll, fout_epll };
 +PNAME(mout_gpll_p)   = { fin_pll, fout_gpll };
  PNAME(mout_mpll_user_p)  = { fin_pll, sclk_mpll };
  PNAME(mout_bpll_user_p)  = { fin_pll, sclk_bpll };
  PNAME(mout_aclk166_p)= { sclk_cpll, sclk_mpll_user };
  PNAME(mout_aclk200_p)= { sclk_mpll_user, sclk_bpll_user };
 +PNAME(mout_aclk400_p)= { aclk_400_g3d_mid, sclk_gpll };
  PNAME(mout_hdmi_p)   = { div_hdmi_pixel, sclk_hdmiphy };
  PNAME(mout_usb3_p)   = { sclk_mpll_user, sclk_cpll };
  PNAME(mout_group1_p) = { fin_pll, fin_pll, sclk_hdmi27m,
 @@ -252,6 +257,9 @@ static struct samsung_mux_clock exynos5250_mux_clks[]
 __initdata = { MUX(none, mout_aclk166, mout_aclk166_p, SRC_TOP0, 8,
 1),
   MUX(none, mout_aclk333, mout_aclk166_p, SRC_TOP0, 16, 1),
   MUX(none, mout_aclk200, mout_aclk200_p, SRC_TOP0, 12, 1),
 + MUX(none, aclk_400_g3d_mid, mout_aclk200_p, SRC_TOP0, 20, 1),

Name of this clock looks out of line looking at other clocks defined in 
this file. Shouldn't it be something like mout_aclk400_g3d_mid?

 + MUX(none, sclk_gpll, mout_gpll_p, SRC_TOP2, 28, 1),
 + MUX(none, mout_aclk400, mout_aclk400_p, SRC_TOP1, 28, 1),

According to the documentation I have, this clock should be called 
mout_aclk400_g3d.

   MUX(none, mout_cam_bayer, mout_group1_p, SRC_GSCL, 12, 4),
   MUX(none, mout_cam0, mout_group1_p, SRC_GSCL, 16, 4),
   MUX(none, mout_cam1, mout_group1_p, SRC_GSCL, 20, 4),
 @@ -291,6 +299,7 @@ static struct samsung_div_clock exynos5250_div_clks[]
 __initdata = { DIV(none, aclk166, mout_aclk166, DIV_TOP0, 8, 3),
   DIV(none, aclk333, mout_aclk333, DIV_TOP0, 20, 3),
   DIV(none, aclk200, mout_aclk200, DIV_TOP0, 12, 3),
 + DIV(none, aclk_400_g3d, mout_aclk400, DIV_TOP0, 24, 3),

Hmm, what about div_aclk400_g3d, since it is a divider?

Best regards,
Tomasz

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Re: [PATCH v3] clk: Exynos5250: Add clocks for G3D

2013-08-14 Thread Arun Kumar K
Hi Tomasz

On Wed, Aug 14, 2013 at 6:14 PM, Tomasz Figa t.f...@samsung.com wrote:
 Hi Arun,

 On Wednesday 14 of August 2013 16:40:05 Arun Kumar K wrote:
 This patch adds the required clocks for ARM Mali IP
 in Exynos5250.

 Signed-off-by: Arun Kumar K arun...@samsung.com
 Acked-by: Mike Turquette mturque...@linaro.org
 Acked-by: Kukjin Kim kgene@samsung.com
 ---
 Changes from v2
 - Rebased on clk-next
 Changes from v1
 - Removed exporting of parent DIV clock for g3d
   as per Tomsz Figa's comment.
 ---
  .../devicetree/bindings/clock/exynos5250-clock.txt |1 +
  drivers/clk/samsung/clk-exynos5250.c   |   12 +++-
  2 files changed, 12 insertions(+), 1 deletion(-)

 diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
 b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt index
 24765c1..bb3dd95 100644
 --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
 +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
 @@ -159,6 +159,7 @@ clock which they consume.
mixer  343
hdmi   344
g2d345
 +  g3d346


 [Clock Muxes]
 diff --git a/drivers/clk/samsung/clk-exynos5250.c
 b/drivers/clk/samsung/clk-exynos5250.c index a9916a4..892a5ac 100644
 --- a/drivers/clk/samsung/clk-exynos5250.c
 +++ b/drivers/clk/samsung/clk-exynos5250.c
 @@ -34,6 +34,7 @@
  #define VPLL_CON00x10140
  #define GPLL_CON00x10150
  #define SRC_TOP0 0x10210
 +#define SRC_TOP1 0x10214
  #define SRC_TOP2 0x10218
  #define SRC_GSCL 0x10220
  #define SRC_DISP1_0  0x1022c
 @@ -66,6 +67,7 @@
  #define DIV_PERIC5   0x1056c
  #define GATE_IP_GSCL 0x10920
  #define GATE_IP_MFC  0x1092c
 +#define GATE_IP_G3D  0x10930
  #define GATE_IP_GEN  0x10934
  #define GATE_IP_FSYS 0x10944
  #define GATE_IP_PERIC0x10950
 @@ -120,7 +122,7 @@ enum exynos5250_clks {
   spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
 hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
 tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
 - wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d,
 + wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d, g3d,

   /* mux clocks */
   mout_hdmi = 1024,
 @@ -137,6 +139,7 @@ static unsigned long exynos5250_clk_regs[] __initdata
 = { DIV_CPU0,
   SRC_CORE1,
   SRC_TOP0,
 + SRC_TOP1,
   SRC_TOP2,
   SRC_GSCL,
   SRC_DISP1_0,
 @@ -190,10 +193,12 @@ PNAME(mout_vpllsrc_p)   = { fin_pll,
 sclk_hdmi27m
 }; PNAME(mout_vpll_p) = { mout_vpllsrc, fout_vpll };
  PNAME(mout_cpll_p)   = { fin_pll, fout_cpll };
  PNAME(mout_epll_p)   = { fin_pll, fout_epll };
 +PNAME(mout_gpll_p)   = { fin_pll, fout_gpll };
  PNAME(mout_mpll_user_p)  = { fin_pll, sclk_mpll };
  PNAME(mout_bpll_user_p)  = { fin_pll, sclk_bpll };
  PNAME(mout_aclk166_p)= { sclk_cpll, sclk_mpll_user };
  PNAME(mout_aclk200_p)= { sclk_mpll_user, sclk_bpll_user };
 +PNAME(mout_aclk400_p)= { aclk_400_g3d_mid, sclk_gpll };
  PNAME(mout_hdmi_p)   = { div_hdmi_pixel, sclk_hdmiphy };
  PNAME(mout_usb3_p)   = { sclk_mpll_user, sclk_cpll };
  PNAME(mout_group1_p) = { fin_pll, fin_pll, sclk_hdmi27m,
 @@ -252,6 +257,9 @@ static struct samsung_mux_clock exynos5250_mux_clks[]
 __initdata = { MUX(none, mout_aclk166, mout_aclk166_p, SRC_TOP0, 8,
 1),
   MUX(none, mout_aclk333, mout_aclk166_p, SRC_TOP0, 16, 1),
   MUX(none, mout_aclk200, mout_aclk200_p, SRC_TOP0, 12, 1),
 + MUX(none, aclk_400_g3d_mid, mout_aclk200_p, SRC_TOP0, 20, 1),

 Name of this clock looks out of line looking at other clocks defined in
 this file. Shouldn't it be something like mout_aclk400_g3d_mid?


Ok will rename it.

 + MUX(none, sclk_gpll, mout_gpll_p, SRC_TOP2, 28, 1),
 + MUX(none, mout_aclk400, mout_aclk400_p, SRC_TOP1, 28, 1),

 According to the documentation I have, this clock should be called
 mout_aclk400_g3d.


Ok.

   MUX(none, mout_cam_bayer, mout_group1_p, SRC_GSCL, 12, 4),
   MUX(none, mout_cam0, mout_group1_p, SRC_GSCL, 16, 4),
   MUX(none, mout_cam1, mout_group1_p, SRC_GSCL, 20, 4),
 @@ -291,6 +299,7 @@ static struct samsung_div_clock exynos5250_div_clks[]
 __initdata = { DIV(none, aclk166, mout_aclk166, DIV_TOP0, 8, 3),
   DIV(none, aclk333, mout_aclk333, DIV_TOP0, 20, 3),
   DIV(none, aclk200, mout_aclk200, DIV_TOP0, 12, 3),
 + DIV(none, aclk_400_g3d, mout_aclk400, DIV_TOP0, 24, 3),

 Hmm, what about div_aclk400_g3d, since it is a divider?


Ok will change.

Regards
Arun
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Re: [PATCH 2/2] iommu/exynos: Follow kernel coding style for __sysmmu_enable return type

2013-08-14 Thread 'Joerg Roedel'
KyongHo,

On Fri, Jul 26, 2013 at 07:46:01PM +0900, Cho KyongHo wrote:
 __sysmmu_enable() must return 1 if it is called with the same page table.
 I have fixed it exynos_iommu_attach_device() to always return zero on success
 in the next patchset which I will post today.
 
 Thank you.

When you are fine with these patches please put them on-top of your
patch-set when you re-submit. I will take them from there then.


Joerg


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[PATCH v4] clk: Exynos5250: Add clocks for G3D

2013-08-14 Thread Arun Kumar K
This patch adds the required clocks for ARM Mali IP
in Exynos5250.

Signed-off-by: Arun Kumar K arun...@samsung.com
Acked-by: Mike Turquette mturque...@linaro.org
Acked-by: Kukjin Kim kgene@samsung.com
---
Changes from v3
- Renamed some clocks as per Tomasz Figa's comments
Changes from v2
- Rebased on clk-next
Changes from v1
- Removed exporting of parent DIV clock for g3d
  as per Tomsz Figa's comment.
---
 .../devicetree/bindings/clock/exynos5250-clock.txt |1 +
 drivers/clk/samsung/clk-exynos5250.c   |   12 +++-
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt 
b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
index 24765c1..bb3dd95 100644
--- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -159,6 +159,7 @@ clock which they consume.
   mixer343
   hdmi 344
   g2d  345
+  g3d  346
 
 
[Clock Muxes]
diff --git a/drivers/clk/samsung/clk-exynos5250.c 
b/drivers/clk/samsung/clk-exynos5250.c
index a9916a4..8ad2b96 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -34,6 +34,7 @@
 #define VPLL_CON0  0x10140
 #define GPLL_CON0  0x10150
 #define SRC_TOP0   0x10210
+#define SRC_TOP1   0x10214
 #define SRC_TOP2   0x10218
 #define SRC_GSCL   0x10220
 #define SRC_DISP1_00x1022c
@@ -66,6 +67,7 @@
 #define DIV_PERIC5 0x1056c
 #define GATE_IP_GSCL   0x10920
 #define GATE_IP_MFC0x1092c
+#define GATE_IP_G3D0x10930
 #define GATE_IP_GEN0x10934
 #define GATE_IP_FSYS   0x10944
 #define GATE_IP_PERIC  0x10950
@@ -120,7 +122,7 @@ enum exynos5250_clks {
spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
-   wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d,
+   wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d, g3d,
 
/* mux clocks */
mout_hdmi = 1024,
@@ -137,6 +139,7 @@ static unsigned long exynos5250_clk_regs[] __initdata = {
DIV_CPU0,
SRC_CORE1,
SRC_TOP0,
+   SRC_TOP1,
SRC_TOP2,
SRC_GSCL,
SRC_DISP1_0,
@@ -190,10 +193,12 @@ PNAME(mout_vpllsrc_p) = { fin_pll, sclk_hdmi27m };
 PNAME(mout_vpll_p) = { mout_vpllsrc, fout_vpll };
 PNAME(mout_cpll_p) = { fin_pll, fout_cpll };
 PNAME(mout_epll_p) = { fin_pll, fout_epll };
+PNAME(mout_gpll_p) = { fin_pll, fout_gpll };
 PNAME(mout_mpll_user_p)= { fin_pll, sclk_mpll };
 PNAME(mout_bpll_user_p)= { fin_pll, sclk_bpll };
 PNAME(mout_aclk166_p)  = { sclk_cpll, sclk_mpll_user };
 PNAME(mout_aclk200_p)  = { sclk_mpll_user, sclk_bpll_user };
+PNAME(mout_aclk400_p)  = { mout_aclk400_g3d_mid, sclk_gpll };
 PNAME(mout_hdmi_p) = { div_hdmi_pixel, sclk_hdmiphy };
 PNAME(mout_usb3_p) = { sclk_mpll_user, sclk_cpll };
 PNAME(mout_group1_p)   = { fin_pll, fin_pll, sclk_hdmi27m,
@@ -252,6 +257,9 @@ static struct samsung_mux_clock exynos5250_mux_clks[] 
__initdata = {
MUX(none, mout_aclk166, mout_aclk166_p, SRC_TOP0, 8, 1),
MUX(none, mout_aclk333, mout_aclk166_p, SRC_TOP0, 16, 1),
MUX(none, mout_aclk200, mout_aclk200_p, SRC_TOP0, 12, 1),
+   MUX(none, mout_aclk400_g3d_mid, mout_aclk200_p, SRC_TOP0, 20, 1),
+   MUX(none, sclk_gpll, mout_gpll_p, SRC_TOP2, 28, 1),
+   MUX(none, mout_aclk400_g3d, mout_aclk400_p, SRC_TOP1, 28, 1),
MUX(none, mout_cam_bayer, mout_group1_p, SRC_GSCL, 12, 4),
MUX(none, mout_cam0, mout_group1_p, SRC_GSCL, 16, 4),
MUX(none, mout_cam1, mout_group1_p, SRC_GSCL, 20, 4),
@@ -291,6 +299,7 @@ static struct samsung_div_clock exynos5250_div_clks[] 
__initdata = {
DIV(none, aclk166, mout_aclk166, DIV_TOP0, 8, 3),
DIV(none, aclk333, mout_aclk333, DIV_TOP0, 20, 3),
DIV(none, aclk200, mout_aclk200, DIV_TOP0, 12, 3),
+   DIV(none, div_aclk400_g3d, mout_aclk400_g3d, DIV_TOP0, 24, 3),
DIV(none, div_cam_bayer, mout_cam_bayer, DIV_GSCL, 12, 4),
DIV(none, div_cam0, mout_cam0, DIV_GSCL, 16, 4),
DIV(none, div_cam1, mout_cam1, DIV_GSCL, 20, 4),
@@ -492,6 +501,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] 
__initdata = {
GATE(mixer, mixer, aclk200, GATE_IP_DISP1, 5, 0, 0),
GATE(hdmi, hdmi, aclk200, GATE_IP_DISP1, 6, 0, 0),
GATE(g2d, g2d, aclk200, GATE_IP_ACP, 3, 0, 0),
+   GATE(g3d, g3d, div_aclk400_g3d, GATE_IP_G3D, 0, 0, 0),
 };
 
 static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = {
-- 
1.7.9.5

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[PATCH v4 1/3] ARM: dts: Fix the RTC DT node name for Exynos5250 SoC

2013-08-14 Thread Vikas Sajjan
Fixes the RTC DT node name for Exynos5250 SoC as per the DT node naming
convention.

Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
---
 arch/arm/boot/dts/exynos5.dtsi|2 +-
 arch/arm/boot/dts/exynos5250.dtsi |2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index f65e124..4a8e223 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -95,7 +95,7 @@
interrupts = 0 54 0;
};
 
-   rtc {
+   rtc@101E {
compatible = samsung,s3c6410-rtc;
reg = 0x101E 0x100;
interrupts = 0 43 0, 0 44 0;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index 88589b7..f426ce6 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -178,7 +178,7 @@
samsung,power-domain = pd_mfc;
};
 
-   rtc {
+   rtc@101E {
clocks = clock 337;
clock-names = rtc;
};
-- 
1.7.9.5

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[PATCH v4 0/3] Add RTC DT node to Exynos5420 SoC and Fix RTC DT node name for 5250 Soc

2013-08-14 Thread Vikas Sajjan
This patchset does the following 3 things:
 1) Fixes the RTC DT node name for Exynos5250 SoC
 2) Updates the status of RTC DT node of Exynos5250 SoC to okay
 3) Adds RTC DT node to Exynos5420 SoC

changes since v3:
- split the 5250 related modifications into 2 separate patch as 
suggested by Tomasz Figa t.f...@samsung.com

changes since v2:
- split the 5250 related modifications into a separate patch.
- placed the RTC node as per the alphabetical order in the DTS file as
suggested by Kukjin Kim kg...@kernel.org.

changes since v1:
- made DT node status as okay in the dtsi file itself.

Vikas Sajjan (3):
  ARM: dts: Fix the RTC DT node name for Exynos5250 SoC
  ARM: dts: Update the status of RTC DT node of Exynos5250 SoC to
okay
  ARM: dts: Add RTC DT node to Exynos5420 SoC

 arch/arm/boot/dts/exynos5.dtsi|2 +-
 arch/arm/boot/dts/exynos5250.dtsi |3 ++-
 arch/arm/boot/dts/exynos5420.dtsi |6 ++
 3 files changed, 9 insertions(+), 2 deletions(-)

-- 
1.7.9.5

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[PATCH v4 3/3] ARM: dts: Add RTC DT node to Exynos5420 SoC

2013-08-14 Thread Vikas Sajjan
Adds RTC DT node to Exynos5420 SoC

Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
---
 arch/arm/boot/dts/exynos5420.dtsi |6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
b/arch/arm/boot/dts/exynos5420.dtsi
index 9e90d1e..713bb5a 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -126,6 +126,12 @@
interrupts = 0 47 0;
};
 
+   rtc@101E {
+   clocks = clock 317;
+   clock-names = rtc;
+   status = okay;
+   };
+
serial@12C0 {
clocks = clock 257, clock 128;
clock-names = uart, clk_uart_baud0;
-- 
1.7.9.5

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[PATCH v4 2/3] ARM: dts: Update the status of RTC DT node of Exynos5250 SoC to okay

2013-08-14 Thread Vikas Sajjan
Updates the RTC DT node's status to okay, since the bindings in
exynos5250.dtsi depicts the RTC h/w completely.

Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
---
 arch/arm/boot/dts/exynos5250.dtsi |1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index f426ce6..c82137b 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -181,6 +181,7 @@
rtc@101E {
clocks = clock 337;
clock-names = rtc;
+   status = okay;
};
 
tmu@1006 {
-- 
1.7.9.5

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Re: [PATCH 01/15] drivers: phy: add generic PHY framework

2013-08-14 Thread Kishon Vijay Abraham I
Hi,

On Wednesday 14 August 2013 04:34 AM, Tomasz Figa wrote:
 On Wednesday 14 of August 2013 00:19:28 Sylwester Nawrocki wrote:
 W dniu 2013-08-13 14:05, Kishon Vijay Abraham I pisze:
 On Tuesday 13 August 2013 05:07 PM, Tomasz Figa wrote:
 On Tuesday 13 of August 2013 16:14:44 Kishon Vijay Abraham I wrote:
 On Wednesday 31 July 2013 11:45 AM, Felipe Balbi wrote:
 On Wed, Jul 31, 2013 at 11:14:32AM +0530, Kishon Vijay Abraham I 
 wrote:
 IMHO we need a lookup method for PHYs, just like for clocks,
 regulators, PWMs or even i2c busses because there are complex
 cases
 when passing just a name using platform data will not work. I
 would
 second what Stephen said [1] and define a structure doing
 things
 in a
 DT-like way.

 Example;

 [platform code]

 static const struct phy_lookup my_phy_lookup[] = {

PHY_LOOKUP(s3c-hsotg.0, otg, samsung-usbphy.1,
phy.2),

 The only problem here is that if *PLATFORM_DEVID_AUTO* is used
 while
 creating the device, the ids in the device name would change
 and
 PHY_LOOKUP wont be useful.

 I don't think this is a problem. All the existing lookup
 methods
 already
 use ID to identify devices (see regulators, clkdev, PWMs, i2c,
 ...). You
 can simply add a requirement that the ID must be assigned
 manually,
 without using PLATFORM_DEVID_AUTO to use PHY lookup.

 And I'm saying that this idea, of using a specific name and id,
 is
 frought with fragility and will break in the future in various
 ways
 when
 devices get added to systems, making these strings constantly
 have
 to be
 kept up to date with different board configurations.

 People, NEVER, hardcode something like an id.  The fact that
 this
 happens today with the clock code, doesn't make it right, it
 makes
 the
 clock code wrong.  Others have already said that this is wrong
 there
 as
 well, as systems change and dynamic ids get used more and more.

 Let's not repeat the same mistakes of the past just because we
 refuse to
 learn from them...

 So again, the find a phy by a string functions should be
 removed,
 the
 device id should be automatically created by the phy core just
 to
 make
 things unique in sysfs, and no driver code should _ever_ be
 reliant
 on
 the number that is being created, and the pointer to the phy
 structure
 should be used everywhere instead.

 With those types of changes, I will consider merging this
 subsystem,
 but
 without them, sorry, I will not.

 I'll agree with Greg here, the very fact that we see people
 trying to
 add a requirement of *NOT* using PLATFORM_DEVID_AUTO already
 points
 to a big problem in the framework.

 The fact is that if we don't allow PLATFORM_DEVID_AUTO we will
 end up
 adding similar infrastructure to the driver themselves to make
 sure
 we
 don't end up with duplicate names in sysfs in case we have
 multiple
 instances of the same IP in the SoC (or several of the same PCIe
 card).
 I really don't want to go back to that.

 If we are using PLATFORM_DEVID_AUTO, then I dont see any way we
 can
 give the correct binding information to the PHY framework. I think
 we
 can drop having this non-dt support in PHY framework? I see only
 one
 platform (OMAP3) going to be needing this non-dt support and we
 can
 use the USB PHY library for it.

 you shouldn't drop support for non-DT platform, in any case we
 lived
 without DT (and still do) for years. Gotta find a better way ;-)

 hmm..

 how about passing the device names of PHY in platform data of the
 controller? It should be deterministic as the PHY framework assigns
 its
 own id and we *don't* want to add any requirement that the ID must
 be
 assigned manually without using PLATFORM_DEVID_AUTO. We can get rid
 of
 *phy_init_data* in the v10 patch series.

 OK, so the PHY device name would have a fixed part, passed as
 platform data of the controller and a variable part appended
 by the PHY core, depending on the number of registered PHYs ?

 Then same PHY names would be passed as the PHY provider driver's
 platform data ?

 Then if there are 2 instances of the above (same names in platform
 data) how would be determined which PHY controller is linked to
 which PHY supplier ?

 I guess you want each device instance to have different PHY device
 names already in platform data ? That might work. We probably will
 be focused mostly on DT anyway. It seem without DT we are trying
 to find some layer that would allow us to couple relevant devices
 and overcome driver core inconvenience that it provides to means
 to identify specific devices in advance. :) Your proposal sounds
 reasonable, however I might be missing some details or corner cases.

 What about slightly altering the concept of v9 to pass a pointer to
 struct device instead of device name inside phy_init_data?

 As Felipe said, we don't want to pass pointers in platform_data
 to/from random subsystems. We pass data, passing pointers would
 be a total mess IMHO.
 
 Well, this is a total mess anyway... I don't really get the point of using 
 

Re: [PATCH 0/2] Add GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and exynos5250

2013-08-14 Thread Tomasz Figa
Hi Vikas,

On Wednesday 14 of August 2013 10:36:53 Vikas Sajjan wrote:
 Hi Mike,
 
 On Mon, Aug 12, 2013 at 3:32 PM, Vikas Sajjan vikas.saj...@linaro.org 
wrote:
  Adds GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and
  exynos5250.
  
  is rebased on Mike's
  https://git.linaro.org/gitweb?p=people/mturquette/linux.git;a=shortlog;
  h=refs/heads/clk-next 
  Vikas Sajjan (2):
clk: samsung: Add GPLL freq table for exynos5250 SoC
clk: samsung: Add APLL, KPLL, EPLL and VPLL freq table for exynos5420

  SoC
   
   drivers/clk/samsung/clk-exynos5250.c |   19 +++-
   drivers/clk/samsung/clk-exynos5420.c |   81
   ++ 2 files changed, 99 insertions(+),
   1 deletion(-)
 
 Can you apply this patchset.

Please give few more days for the patch to be reviewed by people.

A reasonable period of time which should pass after submitting a patch to 
ping the maintainers is around a week. This allows people to find some time 
to read your patches and share their opinions (and/or give their reviewed-
by/acked-by tags).

Best regards,
Tomasz


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Re: [PATCH 12/29] sound/soc/samsung/ac97.c: simplify use of devm_ioremap_resource

2013-08-14 Thread Mark Brown
On Wed, Aug 14, 2013 at 11:11:16AM +0200, Julia Lawall wrote:
 From: Julia Lawall julia.law...@lip6.fr
 
 Remove unneeded error handling on the result of a call to
 platform_get_resource when the value is passed to devm_ioremap_resource.

Applied, thanks.


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Re: [PATCH 2/4] clk: exynos-audss: allow input clocks to be specified in device tree

2013-08-14 Thread Andrew Bresticker
Hi Tomasz,

 Well, this is basically how it should be done, but in current state of
 clock core I can see a problem: can we really rely on the order of clock
 initialization? I mean, we can't defer initialization of particular clock
 controller until all external clocks it needs are available, because there
 is no probing involved here.

Right, we can't.  The reason I added the device-tree lookup of input
clocks was because Exynos5420 has different names for several of the
input clocks to the audio block.  We already need a separate
compatibility string because of the ADMA clock, so we could just use
that to determine the parent clock names.  It's not ideal, but it's a
workaround for the initialization order issue.  Thoughts?

Thanks,
Andrew
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Re: [PATCH v9 03/16] iommu/exynos: fix page table maintenance

2013-08-14 Thread Grant Grundler
On Wed, Aug 14, 2013 at 3:49 AM, Joerg Roedel j...@8bytes.org wrote:
 On Thu, Aug 08, 2013 at 11:28:44AM -0700, Grant Grundler wrote:
 I can't speak to the previous BUG_ON(). I believe the EADDRESSINUSE
 failures could be either WARN_ON or BUG_ON.   This condition is
 clearly a bug in the generic IOMMU allocator and I think that's why
 KyongHo Cho used BUG_ON.

 Handing out duplicate addresses will generally lead to some sort of
 data corruption or other fault depending on how robust the underlying
 device drivers are written.  So my preference is a BUG_ON to
 immediately flag this condition instead of hoping a device driver will
 correctly handling the dma mapping failure (Some do, most currently
 don't).

 WARN_ON() + return -EADDRESSINUSE would be a good alternative.

 Even if it is a real BUG condition, I don't think it is worth to stop
 execution at this point. It makes debugging harder and the system less
 reliable. I prefer to go with the WARN_ON and an error return value.

I'm ok with WARN_ON and an error return value. This is valid
behavior.  I expect this bug to never happen but if and when it does,
I want a clear symptom (e.g. WARN_ON) that it happened.

My concern is that historically, drivers did not get an error return
value on failure:

ftp://193.166.3.4/pub/linux/kernel/v2.3/patch-html/patch-2.3.47/linux_Documentation_DMA-mapping.txt.html

or later:

https://www.kernel.org/pub/linux/kernel/people/marcelo/linux-2.4/Documentation/DMA-mapping.txt

And thus, some drivers don't check or attempt to handle mapping
failures based on this existing code. Here is a recent example:
 http://comments.gmane.org/gmane.linux.network/272969

I hope very few or none of those exist since Neil Horman demonstrated
dma debugging can flag this behavior.

Just for fun, I'll include this link : (apperently 2003 was a good
year for DMA talks :)
 http://ols.fedoraproject.org/OLS/Reprints-2003/LinuxSymposium2003-2side.pdf
 (three talks on DMA issues)

thanks
grant
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[PATCH 2/2] ARM: dts: Hook up internal PHY on Arndale

2013-08-14 Thread Mark Brown
From: Mark Brown broo...@linaro.org

While the Linux driver stack is capable of figuring this out for itself
document the fact that we really do use the internal PHY even with the
directly wired hub on the board to save anyone else having to work this
out for themselves.

Signed-off-by: Mark Brown broo...@linaro.org
---
 arch/arm/boot/dts/exynos5250-arndale.dts | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts 
b/arch/arm/boot/dts/exynos5250-arndale.dts
index 2428ffd..e477e23 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -553,4 +553,8 @@
connect-gpios = gpd1 7 1;
};
};
+
+   usb@1211 {
+   usb-phy = usb2_phy;
+   };
 };
-- 
1.8.4.rc2

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[PATCH 1/2] ARM: dts: Enable USB hub on Arndale

2013-08-14 Thread Mark Brown
From: Mark Brown broo...@linaro.org

The Arndale has a SMSC USB3503 connected in hardware only mode like a PHY,
support it using the usb-nop-xceiv binding.

Note that due to a regrettable decision to use a regulator to represent
the reset signal this uses a fixed voltage regulator to do that, there
is a plan to use the reset controller binding once that is merged so it
does not seem worthwhile to fix the usb-nop-xceiv driver at this point.

Signed-off-by: Mark Brown broo...@linaro.org
Tested-by: Tushar Behera tushar.beh...@linaro.org
---
 arch/arm/boot/dts/exynos5250-arndale.dts | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts 
b/arch/arm/boot/dts/exynos5250-arndale.dts
index 96d528d..2428ffd 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -539,4 +539,18 @@
rtc {
status = okay;
};
+
+   usb_hub_bus {
+   compatible = simple-bus;
+   #address-cells = 1;
+   #size-cells = 0;
+
+   // SMSC USB3503 connected in hardware only mode as a PHY
+   usb_hub: usb_hub {
+   compatible = smsc,usb3503a;
+
+   reset-gpios = gpx3 5 1;
+   connect-gpios = gpd1 7 1;
+   };
+   };
 };
-- 
1.8.4.rc2

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[PATCH 0/3] Add dt support for exynos hdmiphy settings

2013-08-14 Thread Shirish S
For various revision of chipset if the signal pattern is changed for every 
board, then the phy setting need to be updated correspondingly by measuring
the signal.
With the hdmiphy settings fixed in the driver the only way currently is to
either add a new structure or add compile time option.
To avoid this, we can move the same to dt, wherin we can have different dt
files for every revision. This patchset can be considered as an initiative
towards achieving the same for exynos 5250 and can be later extended to
future chipsets.
Also this patchset moves the entire structure to dt file as-is in the 
driver and hence we can find all the hex values, which are not logically
explained similar to driver.

Shirish S (3):
  ARM: dts: smdk5250: Add hdmi phy settings
  ARM: dts: arndale:  Add hdmi phy settings
  drm: exynos: hdmi: Add dt support for hdmiphy settings

 .../devicetree/bindings/video/exynos_hdmi.txt  |   18 +-
 arch/arm/boot/dts/exynos5250-arndale.dts   |  120 
 arch/arm/boot/dts/exynos5250-smdk5250.dts  |  120 
 drivers/gpu/drm/exynos/exynos_hdmi.c   |  191 +++-
 4 files changed, 320 insertions(+), 129 deletions(-)

-- 
1.7.10.4

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[PATCH 3/3] drm: exynos: hdmi: Add dt support for hdmiphy settings

2013-08-14 Thread Shirish S
This patch adds dt support to hdmiphy config settings
as it is board specific and depends on the signal pattern
of board.

Signed-off-by: Shirish S s.shir...@samsung.com
---
 .../devicetree/bindings/video/exynos_hdmi.txt  |   18 +-
 drivers/gpu/drm/exynos/exynos_hdmi.c   |  191 +++-
 2 files changed, 80 insertions(+), 129 deletions(-)

diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt 
b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
index 323983b..fb8a643 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -12,7 +12,11 @@ Required properties:
a) phandle of the gpio controller node.
b) pin number within the gpio controller.
c) optional flags and pull up/down.
-
+- hdmiphy-confs: following information about the hdmiphy conf settings.
+a) nr-confs specifies the number of pixel clocks supported.
+   b) confX: confX specifies the phy configuration settings,
+   clock-frequency specifies the pixel clock
+   conf specifies the setting for the corresponding pixel clock
 Example:
 
hdmi {
@@ -20,4 +24,16 @@ Example:
reg = 0x1453 0x10;
interrupts = 0 95 0;
hpd-gpio = gpx3 7 1;
+   hdmiphy-confs {
+   nr-confs = 1;
+   conf0: conf0 {
+   clock-frequency = 2520;
+   conf =  /bits/ 8 
+   0x01 0x51 0x2A 0x75 0x40 0x01 0x00 0x08
+   0x82 0x80 0xfc 0xd8 0x45 0xa0 0xac 0x80
+   0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+   0x54 0xf4 0x24 0x00 0x00 0x00 0x01 0x80
+   ;
+   };
+   }
};
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c 
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 2f5c694..cb929ff 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -179,6 +179,11 @@ struct hdmi_conf_regs {
} conf;
 };
 
+struct hdmiphy_config {
+   int pixel_clock;
+   u8 conf[32];
+};
+
 struct hdmi_context {
struct device   *dev;
struct drm_device   *drm_dev;
@@ -199,16 +204,14 @@ struct hdmi_context {
 
struct hdmi_resources   res;
 
+   struct hdmiphy_config   *confs;
+   int nr_confs;
+
int hpd_gpio;
 
enum hdmi_type  type;
 };
 
-struct hdmiphy_config {
-   int pixel_clock;
-   u8 conf[32];
-};
-
 /* list of phy config settings */
 static const struct hdmiphy_config hdmiphy_v13_configs[] = {
{
@@ -258,126 +261,6 @@ static const struct hdmiphy_config hdmiphy_v13_configs[] 
= {
},
 };
 
-static const struct hdmiphy_config hdmiphy_v14_configs[] = {
-   {
-   .pixel_clock = 2520,
-   .conf = {
-   0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08,
-   0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80,
-   0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
-   0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
-   },
-   },
-   {
-   .pixel_clock = 2700,
-   .conf = {
-   0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,
-   0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
-   0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
-   0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
-   },
-   },
-   {
-   .pixel_clock = 27027000,
-   .conf = {
-   0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
-   0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
-   0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
-   0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
-   },
-   },
-   {
-   .pixel_clock = 3600,
-   .conf = {
-   0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08,
-   0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
-   0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
-   0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
-   },
-   },
-   {
-   .pixel_clock = 4000,
-   .conf = {
-   0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08,
-   0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80,
-   0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
-   0x54, 

[PATCH 2/3] ARM: dts: arndale: Add hdmi phy settings

2013-08-14 Thread Shirish S
This patch moves the hdmi phy setting to arndale dts,
as its more of a per board configuration and also
shall be easier for supporting future chipsets.

Signed-off-by: Shirish S s.shir...@samsung.com
---
 arch/arm/boot/dts/exynos5250-arndale.dts |  120 ++
 1 file changed, 120 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts 
b/arch/arm/boot/dts/exynos5250-arndale.dts
index abc7272..59db48a 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -424,6 +424,126 @@
 
hdmi {
hpd-gpio = gpx3 7 2;
+   hdmiphy-confs {
+   nr-confs = 13;
+   conf0: conf0 {
+   clock-frequency = 2520;
+   conf =  /bits/ 8 
+   0x01 0x51 0x2A 0x75 0x40 0x01 0x00 0x08
+   0x82 0x80 0xfc 0xd8 0x45 0xa0 0xac 0x80
+   0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+   0x54 0xf4 0x24 0x00 0x00 0x00 0x01 0x80
+   ;
+   };
+   conf1: conf1 {
+   clock-frequency = 2700;
+   conf = /bits/ 8  
+   0x01 0xd1 0x22 0x51 0x40 0x08 0xfc 0x20
+   0x98 0xa0 0xcb 0xd8 0x45 0xa0 0xac 0x80
+   0x06 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+   0x54 0xe4 0x24 0x00 0x00 0x00 0x01 0x80
+   ;
+   };
+   conf2: conf2 {
+   clock-frequency = 27027000;
+   conf = /bits/ 8  
+   0x01 0xd1 0x2d 0x72 0x40 0x64 0x12 0x08
+   0x43 0xa0 0x0e 0xd9 0x45 0xa0 0xac 0x80
+   0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+   0x54 0xe3 0x24 0x00 0x00 0x00 0x01 0x00
+   ;
+   };
+   conf3: conf3 {
+   clock-frequency = 3600;
+   conf =  /bits/ 8 
+   0x01 0x51 0x2d 0x55 0x40 0x01 0x00 0x08
+   0x82 0x80 0x0e 0xd9 0x45 0xa0 0xac 0x80
+   0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+   0x54 0xab 0x24 0x00 0x00 0x00 0x01 0x80
+   ;
+   };
+   conf4: conf4 {
+   clock-frequency = 4000;
+   conf = /bits/ 8  
+   0x01 0x51 0x32 0x55 0x40 0x01 0x00 0x08
+   0x82 0x80 0x2c 0xd9 0x45 0xa0 0xac 0x80
+   0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+   0x54 0x9a 0x24 0x00 0x00 0x00 0x01 0x80
+   ;
+   };
+   conf5: conf5 {
+   clock-frequency = 6500;
+   conf = /bits/ 8  
+   0x01 0xd1 0x36 0x34 0x40 0x1e 0x0a 0x08
+   0x82 0xa0 0x45 0xd9 0x45 0xa0 0xac 0x80
+   0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+   0x54 0xbd 0x24 0x01 0x00 0x00 0x01 0x80
+   ;
+   };
+   conf6: conf6 {
+   clock-frequency = 74176000;
+   conf = /bits/ 8  
+   0x01 0xd1 0x3e 0x35 0x40 0x5b 0xde 0x08
+   0x82 0xa0 0x73 0xd9 0x45 0xa0 0xac 0x80
+   0x56 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+   0x54 0xa6 0x24 0x01 0x00 0x00 0x01 0x80
+   ;
+   };
+   conf7: conf7 {
+   clock-frequency = 7425;
+   conf = /bits/ 8  
+   0x01 0xd1 0x1f 0x10 0x40 0x40 0xf8 0x08
+   0x81 0xa0 0xba 0xd8 0x45 0xa0 0xac 0x80
+   0x3c 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+   0x54 0xa5 0x24 0x01 0x00 0x00 0x01 0x00
+   ;
+   };
+   conf8: conf8 {
+  

[PATCH 1/3] ARM: dts: smdk5250: Add hdmi phy settings

2013-08-14 Thread Shirish S
This patch moves the hdmi phy setting to smdk5250
dts,as its more of a per board configuration and
also shall be easier for supporting future chipsets.

Signed-off-by: Shirish S s.shir...@samsung.com
---
 arch/arm/boot/dts/exynos5250-smdk5250.dts |  120 +
 1 file changed, 120 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts 
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 49f18c2..95a91a8 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -220,6 +220,126 @@
 
hdmi {
hpd-gpio = gpx3 7 0;
+   hdmiphy-confs {
+   nr-confs = 13;
+   conf0: conf0 {
+   clock-frequency = 2520;
+   conf =  /bits/ 8 
+   0x01 0x51 0x2A 0x75 0x40 0x01 0x00 0x08
+   0x82 0x80 0xfc 0xd8 0x45 0xa0 0xac 0x80
+   0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+   0x54 0xf4 0x24 0x00 0x00 0x00 0x01 0x80
+   ;
+   };
+   conf1: conf1 {
+   clock-frequency = 2700;
+   conf = /bits/ 8  
+   0x01 0xd1 0x22 0x51 0x40 0x08 0xfc 0x20
+   0x98 0xa0 0xcb 0xd8 0x45 0xa0 0xac 0x80
+   0x06 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+   0x54 0xe4 0x24 0x00 0x00 0x00 0x01 0x80
+   ;
+   };
+   conf2: conf2 {
+   clock-frequency = 27027000;
+   conf = /bits/ 8  
+   0x01 0xd1 0x2d 0x72 0x40 0x64 0x12 0x08
+   0x43 0xa0 0x0e 0xd9 0x45 0xa0 0xac 0x80
+   0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+   0x54 0xe3 0x24 0x00 0x00 0x00 0x01 0x00
+   ;
+   };
+   conf3: conf3 {
+   clock-frequency = 3600;
+   conf =  /bits/ 8 
+   0x01 0x51 0x2d 0x55 0x40 0x01 0x00 0x08
+   0x82 0x80 0x0e 0xd9 0x45 0xa0 0xac 0x80
+   0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+   0x54 0xab 0x24 0x00 0x00 0x00 0x01 0x80
+   ;
+   };
+   conf4: conf4 {
+   clock-frequency = 4000;
+   conf = /bits/ 8  
+   0x01 0x51 0x32 0x55 0x40 0x01 0x00 0x08
+   0x82 0x80 0x2c 0xd9 0x45 0xa0 0xac 0x80
+   0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+   0x54 0x9a 0x24 0x00 0x00 0x00 0x01 0x80
+   ;
+   };
+   conf5: conf5 {
+   clock-frequency = 6500;
+   conf = /bits/ 8  
+   0x01 0xd1 0x36 0x34 0x40 0x1e 0x0a 0x08
+   0x82 0xa0 0x45 0xd9 0x45 0xa0 0xac 0x80
+   0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+   0x54 0xbd 0x24 0x01 0x00 0x00 0x01 0x80
+   ;
+   };
+   conf6: conf6 {
+   clock-frequency = 74176000;
+   conf = /bits/ 8  
+   0x01 0xd1 0x3e 0x35 0x40 0x5b 0xde 0x08
+   0x82 0xa0 0x73 0xd9 0x45 0xa0 0xac 0x80
+   0x56 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+   0x54 0xa6 0x24 0x01 0x00 0x00 0x01 0x80
+   ;
+   };
+   conf7: conf7 {
+   clock-frequency = 7425;
+   conf = /bits/ 8  
+   0x01 0xd1 0x1f 0x10 0x40 0x40 0xf8 0x08
+   0x81 0xa0 0xba 0xd8 0x45 0xa0 0xac 0x80
+   0x3c 0x80 0x11 0x04 0x02 0x22 0x44 0x86
+   0x54 0xa5 0x24 0x01 0x00 0x00 0x01 0x00
+   ;
+   };
+   conf8: conf8 {
+  

Re: [PATCH 20/29] watchdog: s3c2410_wdt: simplify use of devm_ioremap_resource

2013-08-14 Thread Guenter Roeck

On 08/14/2013 02:11 AM, Julia Lawall wrote:

From: Julia Lawall julia.law...@lip6.fr

Remove unneeded error handling on the result of a call to
platform_get_resource when the value is passed to devm_ioremap_resource.

Move the call to platform_get_resource adjacent to the call to
devm_ioremap_resource to make the connection between them more clear.

A simplified version of the semantic patch that makes this change is as
follows: (http://coccinelle.lip6.fr/)

// smpl
@@
expression pdev,res,n,e,e1;
expression ret != 0;
identifier l;
@@

- res = platform_get_resource(pdev, IORESOURCE_MEM, n);
   ... when != res
- if (res == NULL) { ... \(goto l;\|return ret;\) }
   ... when != res
+ res = platform_get_resource(pdev, IORESOURCE_MEM, n);
   e = devm_ioremap_resource(e1, res);
// /smpl

Signed-off-by: Julia Lawall julia.law...@lip6.fr



Reviewed-by: Guenter Roeck li...@roeck-us.net


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Re: [PATCH v4 2/3] ARM: dts: Update the status of RTC DT node of Exynos5250 SoC to okay

2013-08-14 Thread Tushar Behera
On 14 August 2013 19:28, Vikas Sajjan vikas.saj...@linaro.org wrote:
 Updates the RTC DT node's status to okay, since the bindings in
 exynos5250.dtsi depicts the RTC h/w completely.

 Signed-off-by: Vikas Sajjan vikas.saj...@linaro.org
 ---
  arch/arm/boot/dts/exynos5250.dtsi |1 +
  1 file changed, 1 insertion(+)

 diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
 b/arch/arm/boot/dts/exynos5250.dtsi
 index f426ce6..c82137b 100644
 --- a/arch/arm/boot/dts/exynos5250.dtsi
 +++ b/arch/arm/boot/dts/exynos5250.dtsi
 @@ -181,6 +181,7 @@
 rtc@101E {
 clocks = clock 337;
 clock-names = rtc;
 +   status = okay;
 };


Sometime back we had a discussion on this, the decision was to enable
it in respective boards.

Also if we are going ahead with this, we would need to remove the
corresponding status statements from board files.

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2013-June/176402.html

-- 
Tushar Behera
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