Re: [PATCH] dma: pl08x: Use correct specifier for size_t values
On Fri, Aug 01, 2014 at 06:09:48PM +0100, Mark Brown wrote: From: Mark Brown broo...@linaro.org When printing size_t values we should use the %zd or %zx format specifier in order to ensure the value is displayed correctly and avoid warnings from sparse. Applied, thanks -- ~Vinod -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V2] ARM: dts: Add DT changes for display on peach_pi
Hi Andreas,
Thanks for the comments.
On Fri, Aug 1, 2014 at 10:24 PM, Andreas Färber afaer...@suse.de wrote:
Hi,
Am 01.08.2014 18:24, schrieb Ajay Kumar:
Add DT nodes for panel-simple auo,b133htn01 panel.
Add backlight enable pin and backlight power supply for pwm-backlight.
Also add panel phandle needed by dp to enable display on peach_pi.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
Changes since V1:
Remove simple-panel compatible string and use only auo,b133htn01.
arch/arm/boot/dts/exynos5800-peach-pi.dts | 27 ++-
1 file changed, 10 insertions(+), 17 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts
b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index f3ee48b..f8c2e61 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -28,11 +28,13 @@
i2c20 = /spi@12d4/cros-ec@0/i2c-tunnel;
};
- backlight {
+ backlight: backlight {
compatible = pwm-backlight;
pwms = pwm 0 100 0;
brightness-levels = 0 100 500 1000 1500 2000 2500 2800;
default-brightness-level = 7;
+ enable-gpios = gpx2 2 0;
For Spring I was asked to use GPIO_ACTIVE_* - here that would mean
s/0/GPIO_ACTIVE_HIGH/ IIUC and if necessary
#include dt-bindings/gpio/gpio.h before the .dtsi #include.
Ok. I will use it.
A modified version of your patch for Snow, rebased onto my cleanups, can
be found on my spring-next branch.
+ power-supply = tps65090_fet1;
pinctrl-0 = pwm0_out;
pinctrl-names = default;
};
@@ -98,6 +100,12 @@
regulator-boot-on;
regulator-always-on;
};
+
+ panel: panel-simple {
Nit: panel-simple seems backwards in English language, and given that
simple-panel would be referring to the implementation, I used just
panel for Spring.
Right. All the platforms just use panel. I will use the same.
+ compatible = auo,b133htn01;
FWIW this depends on auo,b133htn01 getting added to Documentation and
panel-simple, which I think hasn't happened yet?
https://patchwork.kernel.org/patch/4625321/
This version is already old ;)
Latest version is here:
http://www.spinics.net/lists/devicetree/msg44158.html
I hope it will be(is?) merged!
Ajay
+ power-supply = tps65090_fet6;
+ backlight = backlight;
+ };
};
dp {
@@ -111,22 +119,7 @@
samsung,link-rate = 0x0a;
samsung,lane-count = 2;
samsung,hpd-gpio = gpx2 6 0;
-
- display-timings {
- native-mode = timing1;
-
- timing1: timing@1 {
- clock-frequency = 15066;
- hactive = 1920;
- vactive = 1080;
- hfront-porch = 60;
- hback-porch = 172;
- hsync-len = 80;
- vback-porch = 25;
- vfront-porch = 10;
- vsync-len = 10;
- };
- };
+ panel = panel;
};
fimd {
Regards,
Andreas
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[PATCH V3] ARM: dts: Add DT changes for display on peach_pi
Add DT nodes for panel-simple auo,b133htn01 panel.
Add backlight enable pin and backlight power supply for pwm-backlight.
Also, add panel phandle needed by dp to enable display on peach_pi.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
---
Changes since V1:
Remove simple-panel compatible string and use only auo,b133htn01.
Changes since V2:
As suggested by Andreas,
Use GPIO_ACTIVE_HIGH for backlight enable-gpios instead of using 0.
Change panel node naming from panel-simple to panel.
arch/arm/boot/dts/exynos5800-peach-pi.dts | 27 ++-
1 file changed, 10 insertions(+), 17 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts
b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index f3ee48b..f8c2e61 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -28,11 +28,13 @@
i2c20 = /spi@12d4/cros-ec@0/i2c-tunnel;
};
- backlight {
+ backlight: backlight {
compatible = pwm-backlight;
pwms = pwm 0 100 0;
brightness-levels = 0 100 500 1000 1500 2000 2500 2800;
default-brightness-level = 7;
+ enable-gpios = gpx2 2 GPIO_ACTIVE_HIGH;
+ power-supply = tps65090_fet1;
pinctrl-0 = pwm0_out;
pinctrl-names = default;
};
@@ -98,6 +100,12 @@
regulator-boot-on;
regulator-always-on;
};
+
+ panel: panel {
+ compatible = auo,b133htn01;
+ power-supply = tps65090_fet6;
+ backlight = backlight;
+ };
};
dp {
@@ -111,22 +119,7 @@
samsung,link-rate = 0x0a;
samsung,lane-count = 2;
samsung,hpd-gpio = gpx2 6 0;
-
- display-timings {
- native-mode = timing1;
-
- timing1: timing@1 {
- clock-frequency = 15066;
- hactive = 1920;
- vactive = 1080;
- hfront-porch = 60;
- hback-porch = 172;
- hsync-len = 80;
- vback-porch = 25;
- vfront-porch = 10;
- vsync-len = 10;
- };
- };
+ panel = panel;
};
fimd {
--
1.7.9.5
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[PATCH 0/2] sbs-battery: Add missing power class sysfs files
This series add the model_name, manufacturer and voltage_min_design
files from the power supply monitor class sysfs interface that were
missing for the sbs-battery driver. The commits were taken from the
Chrome OS 3.8 downstream kernel and patches were squashed when they
just fixed bugs introduced on previous commits that do the export.
The patch-set was tested on a Exynos5420 based Peach Pit machine by
confirming that the sysfs files existed and provide the right data:
# cat
/sys/class/power_supply/sbs-20-000b/{voltage_min_design,manufacturer,model_name}
750
SANYO
4302A40
Simon Que (1):
sbs-battery: add min design voltage to sbs-battery
cychiang (1):
sbs-battery: export manufacturer and model name to sysfs
drivers/power/sbs-battery.c | 125 +++-
1 file changed, 123 insertions(+), 2 deletions(-)
Best regards,
Javier
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[PATCH 2/2] sbs-battery: add min design voltage to sbs-battery
From: Simon Que s...@chromium.org
sbs-battery has a max design voltage but not a min design voltage field.
The SBS spec only has one design voltage:
http://www.sbs-forum.org/specs/sbdat110.pdf
Currently this is being used for max design voltage. This patch uses it
for min design voltage as well.
Signed-off-by: Simon Que s...@chromium.org
Reviewed-by: Simon Glass s...@chromium.org
Reviewed-by: Todd Broch tbr...@chromium.org
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
drivers/power/sbs-battery.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/power/sbs-battery.c b/drivers/power/sbs-battery.c
index 08feb38..c7b7b40 100644
--- a/drivers/power/sbs-battery.c
+++ b/drivers/power/sbs-battery.c
@@ -48,7 +48,8 @@ enum {
REG_FULL_CHARGE_CAPACITY_CHARGE,
REG_DESIGN_CAPACITY,
REG_DESIGN_CAPACITY_CHARGE,
- REG_DESIGN_VOLTAGE,
+ REG_DESIGN_VOLTAGE_MIN,
+ REG_DESIGN_VOLTAGE_MAX,
REG_MANUFACTURER,
REG_MODEL_NAME,
};
@@ -114,7 +115,9 @@ static const struct chip_data {
SBS_DATA(POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN, 0x18, 0, 65535),
[REG_DESIGN_CAPACITY_CHARGE] =
SBS_DATA(POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN, 0x18, 0, 65535),
- [REG_DESIGN_VOLTAGE] =
+ [REG_DESIGN_VOLTAGE_MIN] =
+ SBS_DATA(POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN, 0x19, 0, 65535),
+ [REG_DESIGN_VOLTAGE_MAX] =
SBS_DATA(POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN, 0x19, 0, 65535),
[REG_SERIAL_NUMBER] =
SBS_DATA(POWER_SUPPLY_PROP_SERIAL_NUMBER, 0x1C, 0, 65535),
@@ -138,6 +141,7 @@ static enum power_supply_property sbs_properties[] = {
POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG,
POWER_SUPPLY_PROP_TIME_TO_FULL_AVG,
POWER_SUPPLY_PROP_SERIAL_NUMBER,
+ POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN,
POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN,
POWER_SUPPLY_PROP_ENERGY_NOW,
POWER_SUPPLY_PROP_ENERGY_FULL,
@@ -431,6 +435,7 @@ static void sbs_unit_adjustment(struct i2c_client *client,
break;
case POWER_SUPPLY_PROP_VOLTAGE_NOW:
+ case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN:
case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
case POWER_SUPPLY_PROP_CURRENT_NOW:
case POWER_SUPPLY_PROP_CHARGE_NOW:
@@ -592,6 +597,7 @@ static int sbs_get_property(struct power_supply *psy,
case POWER_SUPPLY_PROP_TEMP:
case POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG:
case POWER_SUPPLY_PROP_TIME_TO_FULL_AVG:
+ case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN:
case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
ret = sbs_get_property_index(client, psp);
if (ret 0)
--
2.0.0.rc2
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[PATCH 1/2] sbs-battery: export manufacturer and model name to sysfs
From: cychiang cychi...@chromium.org
This CL supports two power_supply_property items for smart battery:
POWER_SUPPLY_PROP_MANUFACTURER and POWER_SUPPLY_PROP_MODEL_NAME such
that battery information 'manufacturer' and 'model_name' can be exported
to sysfs.
Signed-off-by: Cheng-Yi Chiang cychi...@chromium.org
Reviewed-by: Olof Johansson ol...@chromium.org
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
drivers/power/sbs-battery.c | 115
1 file changed, 115 insertions(+)
diff --git a/drivers/power/sbs-battery.c b/drivers/power/sbs-battery.c
index b5f2a76..08feb38 100644
--- a/drivers/power/sbs-battery.c
+++ b/drivers/power/sbs-battery.c
@@ -49,6 +49,8 @@ enum {
REG_DESIGN_CAPACITY,
REG_DESIGN_CAPACITY_CHARGE,
REG_DESIGN_VOLTAGE,
+ REG_MANUFACTURER,
+ REG_MODEL_NAME,
};
/* Battery Mode defines */
@@ -68,6 +70,7 @@ enum sbs_battery_mode {
#define BATTERY_FULL_CHARGED 0x20
#define BATTERY_FULL_DISCHARGED0x10
+/* min_value and max_value are only valid for numerical data */
#define SBS_DATA(_psp, _addr, _min_value, _max_value) { \
.psp = _psp, \
.addr = _addr, \
@@ -115,6 +118,11 @@ static const struct chip_data {
SBS_DATA(POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN, 0x19, 0, 65535),
[REG_SERIAL_NUMBER] =
SBS_DATA(POWER_SUPPLY_PROP_SERIAL_NUMBER, 0x1C, 0, 65535),
+ /* Properties of type `const char *' */
+ [REG_MANUFACTURER] =
+ SBS_DATA(POWER_SUPPLY_PROP_MANUFACTURER, 0x20, 0, 65535),
+ [REG_MODEL_NAME] =
+ SBS_DATA(POWER_SUPPLY_PROP_MODEL_NAME, 0x21, 0, 65535)
};
static enum power_supply_property sbs_properties[] = {
@@ -137,6 +145,9 @@ static enum power_supply_property sbs_properties[] = {
POWER_SUPPLY_PROP_CHARGE_NOW,
POWER_SUPPLY_PROP_CHARGE_FULL,
POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN,
+ /* Properties of type `const char *' */
+ POWER_SUPPLY_PROP_MANUFACTURER,
+ POWER_SUPPLY_PROP_MODEL_NAME
};
struct sbs_info {
@@ -153,6 +164,9 @@ struct sbs_info {
int ignore_changes;
};
+static char model_name[I2C_SMBUS_BLOCK_MAX + 1];
+static char manufacturer[I2C_SMBUS_BLOCK_MAX + 1];
+
static int sbs_read_word_data(struct i2c_client *client, u8 address)
{
struct sbs_info *chip = i2c_get_clientdata(client);
@@ -179,6 +193,74 @@ static int sbs_read_word_data(struct i2c_client *client,
u8 address)
return le16_to_cpu(ret);
}
+static int sbs_read_string_data(struct i2c_client *client, u8 address,
+ char *values)
+{
+ struct sbs_info *chip = i2c_get_clientdata(client);
+ s32 ret = 0, block_length = 0;
+ int retries_length = 1, retries_block = 1;
+ u8 block_buffer[I2C_SMBUS_BLOCK_MAX + 1];
+
+ if (chip-pdata) {
+ retries_length = max(chip-pdata-i2c_retry_count + 1, 1);
+ retries_block = max(chip-pdata-i2c_retry_count + 1, 1);
+ }
+
+ /* Adapter needs to support these two functions */
+ if (!i2c_check_functionality(client-adapter,
+I2C_FUNC_SMBUS_BYTE_DATA |
+I2C_FUNC_SMBUS_I2C_BLOCK)){
+ return -ENODEV;
+ }
+
+ /* Get the length of block data */
+ while (retries_length 0) {
+ ret = i2c_smbus_read_byte_data(client, address);
+ if (ret = 0)
+ break;
+ retries_length--;
+ }
+
+ if (ret 0) {
+ dev_dbg(client-dev,
+ %s: i2c read at address 0x%x failed\n,
+ __func__, address);
+ return ret;
+ }
+
+ /* block_length does not include NULL terminator */
+ block_length = ret;
+ if (block_length I2C_SMBUS_BLOCK_MAX) {
+ dev_err(client-dev,
+ %s: Returned block_length is longer than 0x%x\n,
+ __func__, I2C_SMBUS_BLOCK_MAX);
+ return -EINVAL;
+ }
+
+ /* Get the block data */
+ while (retries_block 0) {
+ ret = i2c_smbus_read_i2c_block_data(
+ client, address,
+ block_length + 1, block_buffer);
+ if (ret = 0)
+ break;
+ retries_block--;
+ }
+
+ if (ret 0) {
+ dev_dbg(client-dev,
+ %s: i2c read at address 0x%x failed\n,
+ __func__, address);
+ return ret;
+ }
+
+ /* block_buffer[0] == block_length */
+ memcpy(values, block_buffer + 1, block_length);
+ values[block_length] = '\0';
+
+ return le16_to_cpu(ret);
+}
+
static int sbs_write_word_data(struct i2c_client *client, u8 address,
u16
Re: [PATCH 1/2] drm/exynos: g2d: make ioctls more robust
On 2014-08-04 02:28, Inki Dae wrote: Oops, sorry. I didn't check v2. No problem :) It would be good if you could also check the libdrm patches that I've resent some while ago. With best wishes, Tobias -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] clk: samsung: Add validation of rate tables for the PLL clocks
Currently there is no mechanism for validation of the PLL rate tables
in the samsung clock driver. In addition, the implementation does not
allow the use ``heterogenous'' tables (i.e., tables whose entries can
correspond to different clock sources).
For instance, consider the VPLL clock from Exynos5410. Its input source
is the MUX mout_vpllsrc, which can generate either 24 MHz or 27 MHz.
The usual way to add rate tables for these two different clock sources
would be:
static const struct samsung_pll_rate_table vpll_24mhz_tbl[] = {
PLL_36XX_RATE(88000, 220, 3, 1, 0),
{ }
};
static const struct samsung_pll_rate_table vpll_27mhz_tbl[] = {
/* ... */
{ }
};
static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
[vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, fout_vpll, mout_vpllsrc,
VPLL_LOCK, VPLL_CON0, NULL),
};
and in the initialization function:
if (_get_rate(mout_vpllsrc) == 24 * MHZ)
exynos5410_plls[vpll].rate_table = vpll_24mhz_tbl;
else if (_get_rate(mout_vpllsrc) == 27 * MHZ)
exynos5410_plls[vpll].rate_table = vpll_27mhz_tbl;
There are many issues with this approach:
- Again, there is no validation for the parameters in the rate tables.
- It is cumbersome, and multiple tables must be defined.
- It adds an explicit dependency to the clock mout_vpllsrc,
which might not be ready at the time we register the tables.
For instance, its rate might depend on an external clock such as fin_pll,
see:
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg35065.html
- The PLL tables are NOT const, hence cannot be marked as __initconst.
This patch adds a new scheme for validation and for the use of heterogenous
tables in the samsung_clk_register_pll function. Among other things, it also:
o Adds support for automatic calculation of rates based on clock parameters
such as mdiv, pdiv, sdiv.
o Defines a new field in the structure samsung_pll_rate_table:
instead of only the field rate, it now has .brate (base rate), which
is the rate of the input clock source, and .orate (output rate), which
is the actual rate of the PLL clock to be used in the set_rate function.
The field .brate is used to differentiate the various input clock sources.
o Automatically sorts the rate table according to the output rate. Hence it
is no longer required that the entries should be in descending order.
o Issues a warning if an entry is incorrect (usually due to round-off errors,
such as in EPLL for exynos5410)
Suggested-by: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Humberto Silva Naves hsna...@gmail.com
---
drivers/clk/samsung/clk-exynos3250.c | 99 +
drivers/clk/samsung/clk-exynos4.c| 130 +---
drivers/clk/samsung/clk-exynos5250.c | 70 +++
drivers/clk/samsung/clk-exynos5260.c | 90
drivers/clk/samsung/clk-exynos5420.c | 48 ++---
drivers/clk/samsung/clk-pll.c| 387 ++-
drivers/clk/samsung/clk-pll.h| 30 +--
drivers/clk/samsung/clk-s3c2410.c| 134 ++--
8 files changed, 567 insertions(+), 421 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos3250.c
b/drivers/clk/samsung/clk-exynos3250.c
index dc85f8e..ede6742 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -704,66 +704,66 @@ static struct samsung_gate_clock gate_clks[] __initdata =
{
/* APLL MPLL BPLL UPLL */
static struct samsung_pll_rate_table exynos3250_pll_rates[] = {
- PLL_35XX_RATE(12, 400, 4, 1),
- PLL_35XX_RATE(11, 275, 3, 1),
- PLL_35XX_RATE(106600, 533, 6, 1),
- PLL_35XX_RATE(10, 250, 3, 1),
- PLL_35XX_RATE( 96000, 320, 4, 1),
- PLL_35XX_RATE( 9, 300, 4, 1),
- PLL_35XX_RATE( 85000, 425, 6, 1),
- PLL_35XX_RATE( 8, 200, 3, 1),
- PLL_35XX_RATE( 7, 175, 3, 1),
- PLL_35XX_RATE( 66700, 667, 12, 1),
- PLL_35XX_RATE( 6, 400, 4, 2),
- PLL_35XX_RATE( 53300, 533, 6, 2),
- PLL_35XX_RATE( 52000, 260, 3, 2),
- PLL_35XX_RATE( 5, 250, 3, 2),
- PLL_35XX_RATE( 4, 200, 3, 2),
- PLL_35XX_RATE( 2, 200, 3, 3),
- PLL_35XX_RATE( 1, 200, 3, 4),
+ PLL_35XX_RATE(12, 2400, 400, 4, 1),
+ PLL_35XX_RATE(11, 2400, 275, 3, 1),
+ PLL_35XX_RATE(106600, 2400, 533, 6, 1),
+ PLL_35XX_RATE(10, 2400, 250, 3, 1),
+ PLL_35XX_RATE( 96000, 2400, 320, 4, 1),
+ PLL_35XX_RATE( 9, 2400, 300, 4, 1),
+ PLL_35XX_RATE( 85000, 2400, 425, 6, 1),
+ PLL_35XX_RATE( 8, 2400, 200, 3, 1),
+ PLL_35XX_RATE( 7, 2400, 175, 3, 1),
+ PLL_35XX_RATE( 66700, 2400, 667, 12, 1),
+ PLL_35XX_RATE( 6, 2400, 400, 4, 2),
+ PLL_35XX_RATE( 53300, 2400,
[PATCH 0/2] PLL registration clean-up
This patch series changes the way PLL clocks are registered, mainly to add validation of rate tables. What follows is a list of changes introduced by the patch: - Validation of PLL rate tables - Added support for heterogenous rate tables. - Removed explicit dependency on the input clock source at the driver initialization - Keeping tables sorted is no longer needed - PLL initialization data is now marked as __initconst For more details, please refer to: http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg35072.html Humberto Silva Naves (2): clk: samsung: Add validation of rate tables for the PLL clocks clk: samsung: Make pll initialization structures read-only. drivers/clk/samsung/clk-exynos3250.c | 105 +- drivers/clk/samsung/clk-exynos4.c| 146 ++--- drivers/clk/samsung/clk-exynos5250.c | 78 +++ drivers/clk/samsung/clk-exynos5260.c | 104 +- drivers/clk/samsung/clk-exynos5410.c | 2 +- drivers/clk/samsung/clk-exynos5420.c | 52 +++-- drivers/clk/samsung/clk-pll.c| 387 ++- drivers/clk/samsung/clk-pll.h| 30 +-- drivers/clk/samsung/clk-s3c2410.c| 142 ++--- drivers/clk/samsung/clk-s3c2412.c| 2 +- drivers/clk/samsung/clk-s3c2443.c| 4 +- drivers/clk/samsung/clk-s3c64xx.c| 2 +- 12 files changed, 600 insertions(+), 454 deletions(-) -- 2.0.1 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] clk: samsung: Make pll initialization structures read-only.
All the structures and tables related to the PLL clock
initialization that were previously as __initdata are now marked
as __initconst.
Signed-off-by: Humberto Silva Naves hsna...@gmail.com
---
drivers/clk/samsung/clk-exynos3250.c | 6 +++---
drivers/clk/samsung/clk-exynos4.c| 16
drivers/clk/samsung/clk-exynos5250.c | 8
drivers/clk/samsung/clk-exynos5260.c | 14 +++---
drivers/clk/samsung/clk-exynos5410.c | 2 +-
drivers/clk/samsung/clk-exynos5420.c | 4 ++--
drivers/clk/samsung/clk-s3c2410.c| 8
drivers/clk/samsung/clk-s3c2412.c| 2 +-
drivers/clk/samsung/clk-s3c2443.c| 4 ++--
drivers/clk/samsung/clk-s3c64xx.c| 2 +-
10 files changed, 33 insertions(+), 33 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos3250.c
b/drivers/clk/samsung/clk-exynos3250.c
index ede6742..691b79b 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -703,7 +703,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
};
/* APLL MPLL BPLL UPLL */
-static struct samsung_pll_rate_table exynos3250_pll_rates[] = {
+static const struct samsung_pll_rate_table exynos3250_pll_rates[] __initconst
= {
PLL_35XX_RATE(12, 2400, 400, 4, 1),
PLL_35XX_RATE(11, 2400, 275, 3, 1),
PLL_35XX_RATE(106600, 2400, 533, 6, 1),
@@ -725,7 +725,7 @@ static struct samsung_pll_rate_table exynos3250_pll_rates[]
= {
};
/* VPLL */
-static struct samsung_pll_rate_table exynos3250_vpll_rates[] = {
+static const struct samsung_pll_rate_table exynos3250_vpll_rates[] __initconst
= {
PLL_36XX_RATE(6, 2400, 100, 2, 1, 0),
PLL_36XX_RATE(53300, 2400, 266, 3, 2, 32768),
PLL_36XX_RATE(519230987, 2400, 173, 2, 2, 5046),
@@ -755,7 +755,7 @@ static struct samsung_pll_rate_table
exynos3250_vpll_rates[] = {
{ /* sentinel */ }
};
-static struct samsung_pll_clock exynos3250_plls[nr_plls] __initdata = {
+static const struct samsung_pll_clock exynos3250_plls[nr_plls] __initconst = {
[apll] = PLL(pll_35xx, CLK_FOUT_APLL, fout_apll, fin_pll,
APLL_LOCK, APLL_CON0, exynos3250_pll_rates),
[mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, fout_mpll, fin_pll,
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index ab690c8..f214a35 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1261,7 +1261,7 @@ static const struct of_device_id ext_clk_match[]
__initconst = {
};
/* PLLs PMS values */
-static struct samsung_pll_rate_table exynos4210_apll_rates[] __initdata = {
+static const struct samsung_pll_rate_table exynos4210_apll_rates[] __initconst
= {
PLL_45XX_RATE(12, 2400, 150, 3, 1, 28),
PLL_45XX_RATE(10, 2400, 250, 6, 1, 28),
PLL_45XX_RATE( 8, 2400, 200, 6, 1, 28),
@@ -1274,7 +1274,7 @@ static struct samsung_pll_rate_table
exynos4210_apll_rates[] __initdata = {
{ /* sentinel */ }
};
-static struct samsung_pll_rate_table exynos4210_epll_rates[] __initdata = {
+static const struct samsung_pll_rate_table exynos4210_epll_rates[] __initconst
= {
PLL_4600_RATE(19200, 2400, 48, 3, 1, 0, 0),
PLL_4600_RATE(180633605, 2400, 45, 3, 1, 10381, 0),
PLL_4600_RATE(18000, 2400, 45, 3, 1, 0, 0),
@@ -1285,7 +1285,7 @@ static struct samsung_pll_rate_table
exynos4210_epll_rates[] __initdata = {
{ /* sentinel */ }
};
-static struct samsung_pll_rate_table exynos4210_vpll_rates[] __initdata = {
+static const struct samsung_pll_rate_table exynos4210_vpll_rates[] __initconst
= {
PLL_4650_RATE(36000, 2400, 44, 3, 0, 1024, 0, 14, 0),
PLL_4650_RATE(32400, 2400, 53, 2, 1, 1024, 1, 1, 1),
PLL_4650_RATE(259617187, 2400, 63, 3, 1, 1950, 0, 20, 1),
@@ -1294,7 +1294,7 @@ static struct samsung_pll_rate_table
exynos4210_vpll_rates[] __initdata = {
{ /* sentinel */ }
};
-static struct samsung_pll_rate_table exynos4x12_apll_rates[] __initdata = {
+static const struct samsung_pll_rate_table exynos4x12_apll_rates[] __initconst
= {
PLL_35XX_RATE(15, 2400, 250, 4, 0),
PLL_35XX_RATE(14, 2400, 175, 3, 0),
PLL_35XX_RATE(13, 2400, 325, 6, 0),
@@ -1312,7 +1312,7 @@ static struct samsung_pll_rate_table
exynos4x12_apll_rates[] __initdata = {
{ /* sentinel */ }
};
-static struct samsung_pll_rate_table exynos4x12_epll_rates[] __initdata = {
+static const struct samsung_pll_rate_table exynos4x12_epll_rates[] __initconst
= {
PLL_36XX_RATE(19200, 2400, 48, 3, 1, 0),
PLL_36XX_RATE(180633605, 2400, 45, 3, 1, 10381),
PLL_36XX_RATE(18000, 2400, 45, 3, 1, 0),
@@ -1323,7 +1323,7 @@ static struct samsung_pll_rate_table
exynos4x12_epll_rates[] __initdata = {
[PATCH v3][next-20140804] ARM: EXYNOS: Fix suspend/resume sequences
From: Tomasz Figa t.f...@samsung.com
Due to recent consolidation of Exynos suspend and cpuidle code, some
parts of suspend and resume sequences are executed two times, once from
exynos_pm_syscore_ops and then from exynos_cpu_pm_notifier() and thus it
breaks suspend, at least on Exynos4-based boards. In addition, simple
core power down from a cpuidle driver could, in case of CPU 0 could
result in calling functions that are specific to suspend and deeper idle
states.
This patch fixes the issue by moving those operations outside the CPU PM
notifier into suspend and AFTR code paths. This leads to a bit of code
duplication, but allows additional code simplification, so in the end
more code is removed than added.
Fixes: 85f9f90808b4 (ARM: EXYNOS: Use the cpu_pm notifier for pm)
Cc: Kukjin Kim kgene@samsung.com
Cc: Arnd Bergmann a...@arndb.de
Cc: Olof Johansson o...@lixom.net
Cc: a...@kernel.org
Signed-off-by: Tomasz Figa t.f...@samsung.com
[b.zolnierkie: ported patch over current changes]
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
---
arch/arm/mach-exynos/pm.c| 163 ++-
drivers/cpuidle/cpuidle-exynos.c | 25 +-
2 files changed, 80 insertions(+), 108 deletions(-)
This is a Tomasz's patch ([1]) ported over current -next kernel.
I'm sending this because Tomasz is on holiday currently and cannot
test the patch (I tested it with Exynos4210 SoC based Origen board
and Exynos4212 SoC based Trats2 target, BTW @Tomasz: on the former
device S2R works even without this patch and on the latter one S2R
doesn't work even with this patch applied). I also need this patch
as a prerequisite for my cpuidle AFTR changes.
Kukjin, could you please apply it to your v3.17 tree? Thanks!
[1] http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg35094.html
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 18646b7..e2c5c7b 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -114,26 +114,6 @@ static int exynos_irq_set_wake(struct irq_data *data,
unsigned int state)
#define S5P_CHECK_AFTR 0xFCBA0D10
#define S5P_CHECK_SLEEP 0x0BAD
-/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
-static void exynos_set_wakeupmask(long mask)
-{
- pmu_raw_writel(mask, S5P_WAKEUP_MASK);
-}
-
-static void exynos_cpu_set_boot_vector(long flags)
-{
- __raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);
- __raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);
-}
-
-void exynos_enter_aftr(void)
-{
- exynos_set_wakeupmask(0xff3e);
- exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
- /* Set value of power down register for aftr mode */
- exynos_sys_powerdown_conf(SYS_AFTR);
-}
-
/* For Cortex-A9 Diagnostic and Power control register */
static unsigned int save_arm_register[2];
@@ -173,6 +153,82 @@ static void exynos_cpu_restore_register(void)
: cc);
}
+static void exynos_pm_central_suspend(void)
+{
+ unsigned long tmp;
+
+ /* Setting Central Sequence Register for power down mode */
+ tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ tmp = ~S5P_CENTRAL_LOWPWR_CFG;
+ pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+}
+
+static int exynos_pm_central_resume(void)
+{
+ unsigned long tmp;
+
+ /*
+* If PMU failed while entering sleep mode, WFI will be
+* ignored by PMU and then exiting cpu_do_idle().
+* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
+* in this situation.
+*/
+ tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ if (!(tmp S5P_CENTRAL_LOWPWR_CFG)) {
+ tmp |= S5P_CENTRAL_LOWPWR_CFG;
+ pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+ /* clear the wakeup state register */
+ pmu_raw_writel(0x0, S5P_WAKEUP_STAT);
+ /* No need to perform below restore code */
+ return -1;
+ }
+
+ return 0;
+}
+
+/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
+static void exynos_set_wakeupmask(long mask)
+{
+ pmu_raw_writel(mask, S5P_WAKEUP_MASK);
+}
+
+static void exynos_cpu_set_boot_vector(long flags)
+{
+ __raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);
+ __raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);
+}
+
+static int exynos_aftr_finisher(unsigned long flags)
+{
+ exynos_set_wakeupmask(0xff3e);
+ exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
+ /* Set value of power down register for aftr mode */
+ exynos_sys_powerdown_conf(SYS_AFTR);
+ cpu_do_idle();
+
+ return 0;
+}
+
+void exynos_enter_aftr(void)
+{
+ cpu_pm_enter();
+
+ exynos_pm_central_suspend();
+ if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
+ exynos_cpu_save_register();
+
+ cpu_suspend(0, exynos_aftr_finisher);
+
+ if
Re: [PATCH v3][next-20140804] ARM: EXYNOS: Fix suspend/resume sequences
Hi,
On Monday, August 04, 2014 04:09:51 PM Bartlomiej Zolnierkiewicz wrote:
From: Tomasz Figa t.f...@samsung.com
Due to recent consolidation of Exynos suspend and cpuidle code, some
parts of suspend and resume sequences are executed two times, once from
exynos_pm_syscore_ops and then from exynos_cpu_pm_notifier() and thus it
breaks suspend, at least on Exynos4-based boards. In addition, simple
core power down from a cpuidle driver could, in case of CPU 0 could
result in calling functions that are specific to suspend and deeper idle
states.
This patch fixes the issue by moving those operations outside the CPU PM
notifier into suspend and AFTR code paths. This leads to a bit of code
duplication, but allows additional code simplification, so in the end
more code is removed than added.
Fixes: 85f9f90808b4 (ARM: EXYNOS: Use the cpu_pm notifier for pm)
Cc: Kukjin Kim kgene@samsung.com
Cc: Arnd Bergmann a...@arndb.de
Cc: Olof Johansson o...@lixom.net
Cc: a...@kernel.org
Signed-off-by: Tomasz Figa t.f...@samsung.com
[b.zolnierkie: ported patch over current changes]
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
---
arch/arm/mach-exynos/pm.c| 163
++-
drivers/cpuidle/cpuidle-exynos.c | 25 +-
2 files changed, 80 insertions(+), 108 deletions(-)
This is a Tomasz's patch ([1]) ported over current -next kernel.
I'm sending this because Tomasz is on holiday currently and cannot
test the patch (I tested it with Exynos4210 SoC based Origen board
and Exynos4212 SoC based Trats2 target, BTW @Tomasz: on the former
device S2R works even without this patch and on the latter one S2R
doesn't work even with this patch applied). I also need this patch
as a prerequisite for my cpuidle AFTR changes.
Kukjin, could you please apply it to your v3.17 tree? Thanks!
I noticed one thing that is not correct (please see below),
I will send updated patch shortly.
[1]
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg35094.html
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 18646b7..e2c5c7b 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -114,26 +114,6 @@ static int exynos_irq_set_wake(struct irq_data *data,
unsigned int state)
#define S5P_CHECK_AFTR 0xFCBA0D10
#define S5P_CHECK_SLEEP 0x0BAD
-/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
-static void exynos_set_wakeupmask(long mask)
-{
- pmu_raw_writel(mask, S5P_WAKEUP_MASK);
-}
-
-static void exynos_cpu_set_boot_vector(long flags)
-{
- __raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);
- __raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);
-}
-
-void exynos_enter_aftr(void)
-{
- exynos_set_wakeupmask(0xff3e);
- exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
- /* Set value of power down register for aftr mode */
- exynos_sys_powerdown_conf(SYS_AFTR);
-}
-
/* For Cortex-A9 Diagnostic and Power control register */
static unsigned int save_arm_register[2];
@@ -173,6 +153,82 @@ static void exynos_cpu_restore_register(void)
: cc);
}
+static void exynos_pm_central_suspend(void)
+{
+ unsigned long tmp;
+
+ /* Setting Central Sequence Register for power down mode */
+ tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ tmp = ~S5P_CENTRAL_LOWPWR_CFG;
+ pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+}
+
+static int exynos_pm_central_resume(void)
+{
+ unsigned long tmp;
+
+ /*
+ * If PMU failed while entering sleep mode, WFI will be
+ * ignored by PMU and then exiting cpu_do_idle().
+ * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
+ * in this situation.
+ */
+ tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ if (!(tmp S5P_CENTRAL_LOWPWR_CFG)) {
+ tmp |= S5P_CENTRAL_LOWPWR_CFG;
+ pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+ /* clear the wakeup state register */
+ pmu_raw_writel(0x0, S5P_WAKEUP_STAT);
+ /* No need to perform below restore code */
+ return -1;
+ }
+
+ return 0;
+}
+
+/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
+static void exynos_set_wakeupmask(long mask)
+{
+ pmu_raw_writel(mask, S5P_WAKEUP_MASK);
+}
+
+static void exynos_cpu_set_boot_vector(long flags)
+{
+ __raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);
+ __raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);
+}
+
+static int exynos_aftr_finisher(unsigned long flags)
+{
+ exynos_set_wakeupmask(0xff3e);
+ exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
+ /* Set value of power down register for aftr mode */
+ exynos_sys_powerdown_conf(SYS_AFTR);
+ cpu_do_idle();
+
+ return 0;
In the original code (before the patch) '1' not '0'
[PATCH v4][next-20140804] ARM: EXYNOS: Fix suspend/resume sequences
From: Tomasz Figa t.f...@samsung.com
Due to recent consolidation of Exynos suspend and cpuidle code, some
parts of suspend and resume sequences are executed two times, once from
exynos_pm_syscore_ops and then from exynos_cpu_pm_notifier() and thus it
breaks suspend, at least on Exynos4-based boards. In addition, simple
core power down from a cpuidle driver could, in case of CPU 0 could
result in calling functions that are specific to suspend and deeper idle
states.
This patch fixes the issue by moving those operations outside the CPU PM
notifier into suspend and AFTR code paths. This leads to a bit of code
duplication, but allows additional code simplification, so in the end
more code is removed than added.
Fixes: 85f9f90808b4 (ARM: EXYNOS: Use the cpu_pm notifier for pm)
Cc: Kukjin Kim kgene@samsung.com
Cc: Arnd Bergmann a...@arndb.de
Cc: Olof Johansson o...@lixom.net
Cc: a...@kernel.org
Signed-off-by: Tomasz Figa t.f...@samsung.com
[b.zolnierkie: ported patch over current changes]
[b.zolnierkie: fixed exynos_aftr_finisher() return value]
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
---
arch/arm/mach-exynos/pm.c| 163 ++-
drivers/cpuidle/cpuidle-exynos.c | 25 -
2 files changed, 80 insertions(+), 108 deletions(-)
v4:
- fixed exynos_aftr_finisher() return value
Index: b/arch/arm/mach-exynos/pm.c
===
--- a/arch/arm/mach-exynos/pm.c 2014-08-04 16:36:18.927125851 +0200
+++ b/arch/arm/mach-exynos/pm.c 2014-08-04 16:36:38.559126369 +0200
@@ -114,26 +114,6 @@ static int exynos_irq_set_wake(struct ir
#define S5P_CHECK_AFTR 0xFCBA0D10
#define S5P_CHECK_SLEEP 0x0BAD
-/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
-static void exynos_set_wakeupmask(long mask)
-{
- pmu_raw_writel(mask, S5P_WAKEUP_MASK);
-}
-
-static void exynos_cpu_set_boot_vector(long flags)
-{
- __raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);
- __raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);
-}
-
-void exynos_enter_aftr(void)
-{
- exynos_set_wakeupmask(0xff3e);
- exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
- /* Set value of power down register for aftr mode */
- exynos_sys_powerdown_conf(SYS_AFTR);
-}
-
/* For Cortex-A9 Diagnostic and Power control register */
static unsigned int save_arm_register[2];
@@ -173,6 +153,82 @@ static void exynos_cpu_restore_register(
: cc);
}
+static void exynos_pm_central_suspend(void)
+{
+ unsigned long tmp;
+
+ /* Setting Central Sequence Register for power down mode */
+ tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ tmp = ~S5P_CENTRAL_LOWPWR_CFG;
+ pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+}
+
+static int exynos_pm_central_resume(void)
+{
+ unsigned long tmp;
+
+ /*
+* If PMU failed while entering sleep mode, WFI will be
+* ignored by PMU and then exiting cpu_do_idle().
+* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
+* in this situation.
+*/
+ tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ if (!(tmp S5P_CENTRAL_LOWPWR_CFG)) {
+ tmp |= S5P_CENTRAL_LOWPWR_CFG;
+ pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+ /* clear the wakeup state register */
+ pmu_raw_writel(0x0, S5P_WAKEUP_STAT);
+ /* No need to perform below restore code */
+ return -1;
+ }
+
+ return 0;
+}
+
+/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
+static void exynos_set_wakeupmask(long mask)
+{
+ pmu_raw_writel(mask, S5P_WAKEUP_MASK);
+}
+
+static void exynos_cpu_set_boot_vector(long flags)
+{
+ __raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);
+ __raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);
+}
+
+static int exynos_aftr_finisher(unsigned long flags)
+{
+ exynos_set_wakeupmask(0xff3e);
+ exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
+ /* Set value of power down register for aftr mode */
+ exynos_sys_powerdown_conf(SYS_AFTR);
+ cpu_do_idle();
+
+ return 1;
+}
+
+void exynos_enter_aftr(void)
+{
+ cpu_pm_enter();
+
+ exynos_pm_central_suspend();
+ if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
+ exynos_cpu_save_register();
+
+ cpu_suspend(0, exynos_aftr_finisher);
+
+ if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9) {
+ scu_enable(S5P_VA_SCU);
+ exynos_cpu_restore_register();
+ }
+
+ exynos_pm_central_resume();
+
+ cpu_pm_exit();
+}
+
static int exynos_cpu_suspend(unsigned long arg)
{
#ifdef CONFIG_CACHE_L2X0
@@ -217,16 +273,6 @@ static void exynos_pm_prepare(void)
pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
}
-static void
Re: [PATCH v6 10/10] ARM: dts: Add exynos5250-spring device tree
Andreas,
On Fri, Aug 1, 2014 at 5:52 PM, Andreas Färber afaer...@suse.de wrote:
Adds initial support for the HP Chromebook 11.
Cc: Vincent Palatin vpala...@chromium.org
Cc: Doug Anderson diand...@chromium.org
Cc: Stephan van Schaik step...@synkhronix.com
Signed-off-by: Andreas Färber afaer...@suse.de
---
v5 - v6:
* Updated for mfc node label
* Reverted to dp-hpd-gpio node in pinctrl_0 (Doug Anderson)
* Fixed alphabetical order of sd1_* nodes (Doug Anderson)
v4 - v5:
* Dropped bogus USB3 regulator (Vincent Palatin, Tomasz Figa)
* Fixed USB3503 reset GPIO (Tomasz Figa)
* Introduced labels to use new referencing style consistently (Tomasz Figa)
* Don't override dp_hpd, moved to pinctrl_0 instead (Tomasz Figa)
* mmc_1: Added comment from Snow's mmc_3 (Tomasz Figa / Doug Anderson)
* Override /codec samsung,mfc-{l,r} properties for alignment with Arndale
* Use more GPIO_ACTIVE_* constants
* Use IRQ_TYPE_* constants
* Dropped s5m_ prefix for s5m8767 LDO regulator labels (max77686 is gone)
* Labeled also all s5m8767 BUCK regulators
v3 - v4:
* Fixed samsung,pin-function 1 - 0 for dp-hpd-gpio
* Replaced dp-hpd-gpio with existing dp_hpd, overriding it
v2 - v3:
* Use GPIO_ACTIVE_{LOW,HIGH} (Doug Anderson)
* Use symbolic KEY_POWER instead of comment
* Moved hsic_reset to new USB3503 node's reset-gpios (Vincent Palatin)
* Use dp_hpd_gpio for dp-controller (Doug Anderson, Ajay Kumar)
* Override sd1_{clk,cmd,cd,bus4} pinctrl similar to Snow (Doug Anderson)
* Added ec_irq pinctrl for cros_ec (Doug Anderson)
* Reordered nodes to minimize diff against Snow (Doug Anderson)
* Dropped obsolete mmc_2 override (Doug Anderson)
* Added lid-switch node (Doug Anderson)
* Added gpio-keys pinctrl (Doug Anderson)
* Added bootargs to avoid empty /chosen node and to document console setting
* Renamed s5m8767_pmic node to avoid underscore
* Use new style for overriding inherited pinctrl nodes, too
* Enable i2s0 node
v1 - v2:
* Use label-based overriding/extension of nodes. (Doug Anderson)
* Dropped tps65090 for now, until we know where to place it.
* Dropped non-Spring nodes from -cros-common.dtsi rather than disabling them.
* Enabled a missing MMC node for access to internal storage.
* Dropped display-timings from dp-controller node. (Ajay Kumar)
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/exynos5250-spring.dts | 536
2 files changed, 537 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5250-spring.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 80a781f76e88..dec4c292f63d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -76,6 +76,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
+ exynos5250-spring.dtb \
exynos5260-xyref5260.dtb \
exynos5410-smdk5410.dtb \
exynos5420-arndale-octa.dtb \
diff --git a/arch/arm/boot/dts/exynos5250-spring.dts
b/arch/arm/boot/dts/exynos5250-spring.dts
new file mode 100644
index ..f5566f84d885
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5250-spring.dts
@@ -0,0 +1,536 @@
+/*
+ * Google Spring board device tree source
+ *
+ * Copyright (c) 2013 Google, Inc
+ * Copyright (c) 2014 SUSE LINUX Products GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include dt-bindings/gpio/gpio.h
+#include dt-bindings/interrupt-controller/irq.h
+#include dt-bindings/input/input.h
+#include exynos5250.dtsi
+
+/ {
+ model = Google Spring;
+ compatible = google,spring, samsung,exynos5250, samsung,exynos5;
+
+ memory {
+ reg = 0x4000 0x8000;
+ };
+
+ chosen {
+ bootargs = console=tty1;
+ };
+
+ gpio-keys {
+ compatible = gpio-keys;
+ pinctrl-names = default;
+ pinctrl-0 = power_key_irq, lid_irq;
+
+ power {
+ label = Power;
+ gpios = gpx1 3 GPIO_ACTIVE_LOW;
+ linux,code = KEY_POWER;
+ gpio-key,wakeup;
+ };
+
+ lid-switch {
+ label = Lid;
+ gpios = gpx3 5 GPIO_ACTIVE_LOW;
+ linux,input-type = 5; /* EV_SW */
+ linux,code = 0; /* SW_LID */
+ debounce-interval = 1;
+ gpio-key,wakeup;
+ };
+ };
+
+ usb-hub {
+ compatible = smsc,usb3503a;
+ reset-gpios = gpe1 0 GPIO_ACTIVE_LOW;
+ };
Last I remember
Re: [PATCH v6 00/10] ARM: dts: exynos: Prepare Spring
Andreas, On Sat, Aug 2, 2014 at 3:25 AM, Andreas Färber afaer...@suse.de wrote: Hi, Am 02.08.2014 06:57, schrieb Doug Anderson: On Fri, Aug 1, 2014 at 7:34 PM, Javier Martinez Canillas javier.marti...@collabora.co.uk wrote: On 08/02/2014 02:52 AM, Andreas Färber wrote: Based on the preinstalled 3.8 based ChromeOS kernel and previous 3.15 based attempts by Stephan and me that broke for 3.16, I've prepared a device tree for the HP Chromebook 11 aka Google Spring. v6 renames a node and reverts dp_hpd. Not yet enabled are trackpad, Wifi and sound. I made a comment on patch 05/10 but the rest of the series looks good to me. So for the remaining patches: Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk NOTE: I thought that Tomasz Figa gave you his Reviewed-by on v5 for the whole series as well but I didn't see his tag on the v6 patches. Yes, I thought that too. I assume he's OK with the small changes you made between v5 and v6. In the very least his Reviewed-by could be present on the patches that didn't change between the last two revs. I did add it to the bootargs, GPIO, USB3503 patches. All other patches were either split off or slightly changed due to dp_hpd[_gpio], so I didn't carry it over. Given Javier's review and Tomasz's review and Vincent's comments, I'll probably skip all the work of reviewing the rest of the series unless someone really wants me to. ;) Could you maybe give an Rb or Ab for the actual Spring patch to have the Cc: updated? :) Done. Note that if there's some problem that can't be resolved by selectively dropping patches, I won't be available next week, so you'll either have to provide fixups for Kukjin to squash or wait till I've returned. One thing I've wondered is whether we should put status = disabled on the dp node with some comment, since it's known not to work as is (but better having the data here than leaving it out, I believe). Don't know about this one. Of course if either of you has input on the discussions on the drm bridge/panel series V6 [1] for how to enable non-simplefb display and iommus, that would be valuable. I've been letting the graphics folks and Samsung hash out the graphics patches, so I don't think I'll be much help here. [1] http://www.spinics.net/lists/linux-samsung-soc/msg35274.html And when one thing is accomplished, I am always quick to look forward: I've taken a quick look at sound nodes: According to 3.8 DT, Spring uses max98089 whereas Snow has 98091, so different codec driver and still lacking DT binding support. I might look into trivially enabling sound/soc/codecs/max98089.c through a maxim,max98089 OF match table once this series lands in linux-next. As for the driver, can we reuse http://git.kernel.org/cgit/linux/kernel/git/broonie/sound.git/tree/sound/soc/samsung/snow.c?h=for-next with a google,spring-audio-max98089, or are code changes needed? I don't know this offhand. Both of you mentioned limitations of cros_ec i2c passthrough leading to a forked tps65090 driver downstream - I don't think I can be of help there, as I guess simply copying a driver will not be an option. ;) https://code.google.com/p/chromium/issues/detail?id=391797 Yup, I think this will be real work for someone. I made a quick attempt and failed at it and I haven't had time to work on it since (and don't necessarily expect to have time in the near future)... I think it is possible for anyone versed in i2c to figure this out based on what I already posted and what's in our local tree... For the touchpad it seems DT support has landed in the input tree as atmel,maxtouch. Backporting just that patch does not make it work though. (Tried the rejected pinctrl approach to be on the safe side.) https://code.google.com/p/chromium/issues/detail?id=371114 https://patchwork.kernel.org/patch/3976801/ This is the same work as needed for pit and pi, I believe. Perhaps Javier or Dmitry has this on their todo list? I thought the internal xhci would have the webcam on it, but I don't see it in lsusb. Does that need some pinctrl or tps65090 regulator? Once appearing on a bus, which driver config option will it need? Perhaps tps65090 FET5? That looks like what the device tree says in our local tree. -Doug -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 10/10] ARM: dts: Add exynos5250-spring device tree
Hello Doug,
On 08/04/2014 05:22 PM, Doug Anderson wrote:
+
+pinctrl_0 {
+ s5m8767_dvs: s5m8767-dvs {
+ samsung,pins = gpd1-0, gpd1-1, gpd1-2;
+ samsung,pin-function = 0;
+ samsung,pin-pud = 1;
+ samsung,pin-drv = 0;
+ };
+
+ dp_hpd_gpio: dp-hpd-gpio {
+ samsung,pins = gpc3-0;
+ samsung,pin-function = 0;
+ samsung,pin-pud = 3;
+ samsung,pin-drv = 0;
+ };
+
+ power_key_irq: power-key-irq {
+ samsung,pins = gpx1-3;
+ samsung,pin-function = 0;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
The fact that snow is missing the pinctrl lines for power and lid is a
bug on snow. Perhaps Javier would be interested in submitting a patch
to fix that?
Sure, added on my TODO list to not only add these missing pin control lines for
lid and power and reference them on gpio-keys but also to double check if there
is anything else missing in the mainline Snow DTS that is on the downstream
Chrome OS one.
I'll wait for Andreas series to be picked by Kukjin before submit a patch though
to avoid any unnecessary churn.
Best regards,
Javier
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Re: [PATCH v6 00/10] ARM: dts: exynos: Prepare Spring
Hello Doug, On 08/04/2014 05:42 PM, Doug Anderson wrote: Both of you mentioned limitations of cros_ec i2c passthrough leading to a forked tps65090 driver downstream - I don't think I can be of help there, as I guess simply copying a driver will not be an option. ;) https://code.google.com/p/chromium/issues/detail?id=391797 Yup, I think this will be real work for someone. I made a quick attempt and failed at it and I haven't had time to work on it since (and don't necessarily expect to have time in the near future)... I think it is possible for anyone versed in i2c to figure this out based on what I already posted and what's in our local tree... I posted a series [0] with the remaining cleanups/fixes for cros_ec that are on the downstream Chrome OS 3.8 kernel. Once these lands it will be easier to add the missing cros_ec functionality on top. I've these on my TODO list but I was going to give priority to the cros_ec user-space interface, LPC bus support and vboot context over the tps65090 Spring support since I don't have access to a Spring machine to test. For the touchpad it seems DT support has landed in the input tree as atmel,maxtouch. Backporting just that patch does not make it work though. (Tried the rejected pinctrl approach to be on the safe side.) https://code.google.com/p/chromium/issues/detail?id=371114 https://patchwork.kernel.org/patch/3976801/ This is the same work as needed for pit and pi, I believe. Perhaps Javier or Dmitry has this on their todo list? Yes, I've this on my TODO list as well. Best regards, Javier [0]: http://www.spinics.net/lists/linux-samsung-soc/msg34897.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 0/5] ARM: EXYNOS: cpuidle: fix AFTR mode on boards with secure firmware enabled
Hi, This patch series adds support for AFTR idle mode on boards with secure firmware enabled and allows EXYNOS cpuidle driver usage on Exynos4x12 SoCs. It has been tested on Trats2 board (using Exynos4412 SoC with secure firmware enabled) on which AFTR mode reduces power consumption by ~12% when EXYNOS cpuidle driver is enabled (in both cases the default exynos_defconfig config is used and CPU1-3 are offlined). Depends on: - next-20140804 branch of linux-next kernel tree - [PATCH v4][next-20140804] ARM: EXYNOS: Fix suspend/resume sequences (http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg35192.html) - [PATCH v2 0/2] Firmware-assisted suspend/resume of Exynos SoCs (http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg34282.html) Changes since v3: - rebased on top of next-20140804 + [PATCH v4][next-20140804] ARM: EXYNOS: Fix suspend/resume sequences (http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg35192.html) [PATCH v2 0/2] Firmware-assisted suspend/resume of Exynos SoCs (http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg34282.html) - (re-)added patch fixing S5P_CENTRAL_SEQ_OPTION register setup Changes since v2: - rebased on top of next-20140708 + [PATCH 5/6] ARM: EXYNOS: Fix suspend/resume sequencies (http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg32809.html) [with rejects fixed] [PATCH 6/6] ARM: EXYNOS: Register cpuidle device only on Exynos4210 and 5250 (http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg32808.html) [PATCH 0/2] Firmware-assisted suspend/resume of Exynos SoCs (http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg32991.html) [with rejects fixed in patch #2] - addressed review comments from Tomasz Figa and Daniel Lezcano Changes since v1: - synced against next-20140602 - added missing Acked-by-s Best regards, -- Bartlomiej Zolnierkiewicz Samsung RD Institute Poland Samsung Electronics Bartlomiej Zolnierkiewicz (5): ARM: EXYNOS: PM: replace EXYNOS_BOOT_VECTOR_* macros by static inlines ARM: EXYNOS: add AFTR mode support to firmware do_idle method ARM: EXYNOS: cpuidle: add secure firmware support to AFTR mode code ARM: EXYNOS: PM: fix register setup for AFTR mode code ARM: EXYNOS: cpuidle: allow driver usage on Exynos4x12 SoCs arch/arm/include/asm/firmware.h | 2 +- arch/arm/mach-exynos/common.h | 5 arch/arm/mach-exynos/exynos.c | 4 ++- arch/arm/mach-exynos/firmware.c | 33 --- arch/arm/mach-exynos/pm.c | 60 - 5 files changed, 69 insertions(+), 35 deletions(-) -- 1.8.2.3 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 1/5] ARM: EXYNOS: PM: replace EXYNOS_BOOT_VECTOR_* macros by static inlines
Replace EXYNOS_BOOT_VECTOR_ADDR and EXYNOS_BOOT_VECTOR_FLAG macros
by exynos_boot_vector_addr() and exynos_boot_vector_flag() static
inlines.
This patch shouldn't cause any functionality changes.
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Acked-by: Daniel Lezcano daniel.lezc...@linaro.org
---
arch/arm/mach-exynos/pm.c | 32
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 80a83b2..eeef8c4 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -101,16 +101,23 @@ static int exynos_irq_set_wake(struct irq_data *data,
unsigned int state)
return -ENOENT;
}
-#define EXYNOS_BOOT_VECTOR_ADDR(samsung_rev() == EXYNOS4210_REV_1_1 ? \
- pmu_base_addr + S5P_INFORM7 : \
- (samsung_rev() == EXYNOS4210_REV_1_0 ? \
- (sysram_base_addr + 0x24) : \
- pmu_base_addr + S5P_INFORM0))
-#define EXYNOS_BOOT_VECTOR_FLAG(samsung_rev() == EXYNOS4210_REV_1_1 ? \
- pmu_base_addr + S5P_INFORM6 : \
- (samsung_rev() == EXYNOS4210_REV_1_0 ? \
- (sysram_base_addr + 0x20) : \
- pmu_base_addr + S5P_INFORM1))
+static inline void __iomem *exynos_boot_vector_addr(void)
+{
+ if (samsung_rev() == EXYNOS4210_REV_1_1)
+ return pmu_base_addr + S5P_INFORM7;
+ else if (samsung_rev() == EXYNOS4210_REV_1_0)
+ return sysram_base_addr + 0x24;
+ return pmu_base_addr + S5P_INFORM0;
+}
+
+static inline void __iomem *exynos_boot_vector_flag(void)
+{
+ if (samsung_rev() == EXYNOS4210_REV_1_1)
+ return pmu_base_addr + S5P_INFORM6;
+ else if (samsung_rev() == EXYNOS4210_REV_1_0)
+ return sysram_base_addr + 0x20;
+ return pmu_base_addr + S5P_INFORM1;
+}
#define S5P_CHECK_AFTR 0xFCBA0D10
#define S5P_CHECK_SLEEP 0x0BAD
@@ -195,8 +202,9 @@ static void exynos_set_wakeupmask(long mask)
static void exynos_cpu_set_boot_vector(long flags)
{
- __raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);
- __raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);
+ __raw_writel(virt_to_phys(exynos_cpu_resume),
+exynos_boot_vector_addr());
+ __raw_writel(flags, exynos_boot_vector_flag());
}
static int exynos_aftr_finisher(unsigned long flags)
--
1.8.2.3
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[PATCH v4 5/5] ARM: EXYNOS: cpuidle: allow driver usage on Exynos4x12 SoCs
Register cpuidle platform device on Exynos4x12 SoCs allowing EXYNOS cpuidle driver usage on these SoCs. AFTR mode reduces power consumption on Trats2 board (Exynos4412 SoC with secure firmware enabled) by ~12% when EXYNOS cpuidle driver is enabled (in both cases the default exynos_defconfig config is used and CPU1-3 are offlined). Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com --- arch/arm/mach-exynos/exynos.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index 6a24e11..15cf86d 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -317,7 +317,9 @@ static void __init exynos_dt_machine_init(void) exynos_sysram_init(); if (of_machine_is_compatible(samsung,exynos4210) || - of_machine_is_compatible(samsung,exynos5250)) + of_machine_is_compatible(samsung,exynos4212) || + of_machine_is_compatible(samsung,exynos4412) || + of_machine_is_compatible(samsung,exynos5250)) platform_device_register(exynos_cpuidle); platform_device_register_simple(exynos-cpufreq, -1, NULL, 0); -- 1.8.2.3 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 3/5] ARM: EXYNOS: cpuidle: add secure firmware support to AFTR mode code
* Move cp15 registers saving to exynos_save_cp15() helper and add
additional helper usage to do_idle firmware method.
* Use resume firmware method instead of exynos_cpu_restore_register()
and skip exynos_cpu_save_register() on boards with secure firmware
enabled.
* Use sysram_ns_base_addr + 0x24/0x20 addresses instead of the default
ones used by exynos_cpu_set_boot_vector() on boards with secure
firmware enabled.
* Use do_idle firmware method instead of cpu_do_idle() on boards with
secure firmware enabled.
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/firmware.c | 23 ---
arch/arm/mach-exynos/pm.c | 17 -
2 files changed, 28 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index e57b7c3..b51b258 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -25,13 +25,27 @@
#include smc.h
#define EXYNOS_SLEEP_MAGIC 0x0bad
+#define EXYNOS_AFTR_MAGIC 0xfcba0d10
#define EXYNOS_BOOT_ADDR 0x8
#define EXYNOS_BOOT_FLAG 0xc
+static void exynos_save_cp15(void)
+{
+ /* Save Power control and Diagnostic registers */
+ asm (mrc p15, 0, %0, c15, c0, 0\n
+mrc p15, 0, %1, c15, c0, 1\n
+: =r (cp15_save_power), =r (cp15_save_diag)
+: : cc);
+}
+
static int exynos_do_idle(unsigned long mode)
{
switch (mode) {
case FW_DO_IDLE_AFTR:
+ exynos_save_cp15();
+ __raw_writel(virt_to_phys(exynos_cpu_resume_ns),
+sysram_ns_base_addr + 0x24);
+ __raw_writel(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0);
break;
case FW_DO_IDLE_SLEEP:
@@ -96,13 +110,8 @@ static int exynos_cpu_suspend(unsigned long arg)
static int exynos_suspend(void)
{
- if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
- /* Save Power control and Diagnostic registers */
- asm (mrc p15, 0, %0, c15, c0, 0\n
- mrc p15, 0, %1, c15, c0, 1\n
- : =r (cp15_save_power), =r (cp15_save_diag)
- : : cc);
- }
+ if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
+ exynos_save_cp15();
writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
writel(virt_to_phys(exynos_cpu_resume_ns),
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index eeef8c4..a61b85c 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -209,11 +209,19 @@ static void exynos_cpu_set_boot_vector(long flags)
static int exynos_aftr_finisher(unsigned long flags)
{
+ int ret;
+
exynos_set_wakeupmask(0xff3e);
- exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
/* Set value of power down register for aftr mode */
exynos_sys_powerdown_conf(SYS_AFTR);
- cpu_do_idle();
+
+ ret = call_firmware_op(do_idle, FW_DO_IDLE_AFTR);
+ if (ret == -ENOSYS) {
+ if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
+ exynos_cpu_save_register();
+ exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
+ cpu_do_idle();
+ }
return 1;
}
@@ -223,14 +231,13 @@ void exynos_enter_aftr(void)
cpu_pm_enter();
exynos_pm_central_suspend();
- if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
- exynos_cpu_save_register();
cpu_suspend(0, exynos_aftr_finisher);
if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9) {
scu_enable(S5P_VA_SCU);
- exynos_cpu_restore_register();
+ if (call_firmware_op(resume) == -ENOSYS)
+ exynos_cpu_restore_register();
}
exynos_pm_central_resume();
--
1.8.2.3
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[PATCH v4 4/5] ARM: EXYNOS: PM: fix register setup for AFTR mode code
Add S5P_CENTRAL_SEQ_OPTION register setup to cpuidle AFTR mode code
by moving the relevant code from exynos_pm_suspend() (used only by
suspend) to exynos_pm_central_suspend() (used by both suspend and
AFTR). Without this setup AFTR mode doesn't show any benefit over
WFI one (at least on Exynos4412 SoC). When this setup is applied
AFTR mode reduces power consumption by ~12% (as measured on Trats2
board).
This change is a preparation for adding secure firmware support to
EXYNOS cpuidle driver.
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/mach-exynos/pm.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index a61b85c..4e32cc6 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -169,6 +169,10 @@ static void exynos_pm_central_suspend(void)
tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
tmp = ~S5P_CENTRAL_LOWPWR_CFG;
pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+
+ /* Setting SEQ_OPTION register */
+ pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
+ S5P_CENTRAL_SEQ_OPTION);
}
static int exynos_pm_central_resume(void)
@@ -291,15 +295,8 @@ static void exynos_pm_prepare(void)
static int exynos_pm_suspend(void)
{
- unsigned long tmp;
-
exynos_pm_central_suspend();
- /* Setting SEQ_OPTION register */
-
- tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
- pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
-
if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
exynos_cpu_save_register();
--
1.8.2.3
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[PATCH v4 2/5] ARM: EXYNOS: add AFTR mode support to firmware do_idle method
On some platforms (i.e. EXYNOS ones) more than one idle mode is
available and we need to distinguish them in firmware do_idle method.
Add mode parameter to do_idle firmware method and AFTR mode support
to EXYNOS do_idle implementation.
This change is a preparation for adding secure firmware support to
EXYNOS cpuidle driver.
This patch shouldn't cause any functionality changes (please note
that do_idle firmware method is unused currently).
Signed-off-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
arch/arm/include/asm/firmware.h | 2 +-
arch/arm/mach-exynos/common.h | 5 +
arch/arm/mach-exynos/firmware.c | 10 --
3 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/firmware.h b/arch/arm/include/asm/firmware.h
index 5904f59..89aefe1 100644
--- a/arch/arm/include/asm/firmware.h
+++ b/arch/arm/include/asm/firmware.h
@@ -28,7 +28,7 @@ struct firmware_ops {
/*
* Enters CPU idle mode
*/
- int (*do_idle)(void);
+ int (*do_idle)(unsigned long mode);
/*
* Sets boot address of specified physical CPU
*/
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index c218200..2d830df 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -119,6 +119,11 @@ extern void __iomem *sysram_base_addr;
extern void __iomem *pmu_base_addr;
void exynos_sysram_init(void);
+enum {
+ FW_DO_IDLE_SLEEP,
+ FW_DO_IDLE_AFTR,
+};
+
void exynos_firmware_init(void);
extern u32 exynos_get_eint_wake_mask(void);
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index f5e626d..e57b7c3 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -28,9 +28,15 @@
#define EXYNOS_BOOT_ADDR 0x8
#define EXYNOS_BOOT_FLAG 0xc
-static int exynos_do_idle(void)
+static int exynos_do_idle(unsigned long mode)
{
- exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
+ switch (mode) {
+ case FW_DO_IDLE_AFTR:
+ exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0);
+ break;
+ case FW_DO_IDLE_SLEEP:
+ exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
+ }
return 0;
}
--
1.8.2.3
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Re: [PATCH 1/1] i2c: Kconfig: Enable HSI2C for Exynos5 platform
On Wed, Jun 25, 2014 at 03:32:03PM +0530, Sachin Kamat wrote: All Exynos5 platforms have HSI2C controllers and are needed by various IPs connected to the boards based on these SoCs. Thus select this by default for Exynos5 platforms. Signed-off-by: Sachin Kamat sachin.ka...@samsung.com Cc: Doug Anderson diand...@chromium.org Applied to for-next, thanks! signature.asc Description: Digital signature
[PATCH] mmc: dw_mmc: change to use recommended reset procedure
This patch changes the fifo reset code to follow the reset procedure
outlined in the documentation of Synopsys Mobile storage host databook.
Signed-off-by: Sonny Rao sonny...@chromium.org
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
Acked-by: Seungwon Jeon tgih@samsung.com
Signed-off-by: Ulf Hansson ulf.hans...@linaro.org
[sonnyrao: fix compile for !CONFIG_MMC_DW_IDMAC case]
---
drivers/mmc/host/dw_mmc.c | 87 ++-
drivers/mmc/host/dw_mmc.h | 5 +++
2 files changed, 69 insertions(+), 23 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 1ac227c..39cf54f 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -111,8 +111,7 @@ static const u8 tuning_blk_pattern_8bit[] = {
0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
};
-static inline bool dw_mci_fifo_reset(struct dw_mci *host);
-static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host);
+static bool dw_mci_reset(struct dw_mci *host);
#if defined(CONFIG_DEBUG_FS)
static int dw_mci_req_show(struct seq_file *s, void *v)
@@ -1235,7 +1234,7 @@ static int dw_mci_data_complete(struct dw_mci *host,
struct mmc_data *data)
* After an error, there may be data lingering
* in the FIFO
*/
- dw_mci_fifo_reset(host);
+ dw_mci_reset(host);
} else {
data-bytes_xfered = data-blocks * data-blksz;
data-error = 0;
@@ -1352,7 +1351,7 @@ static void dw_mci_tasklet_func(unsigned long priv)
/* CMD error in data command */
if (mrq-cmd-error mrq-data)
- dw_mci_fifo_reset(host);
+ dw_mci_reset(host);
host-cmd = NULL;
host-data = NULL;
@@ -1963,14 +1962,8 @@ static void dw_mci_work_routine_card(struct work_struct
*work)
}
/* Power down slot */
- if (present == 0) {
- /* Clear down the FIFO */
- dw_mci_fifo_reset(host);
-#ifdef CONFIG_MMC_DW_IDMAC
- dw_mci_idmac_reset(host);
-#endif
-
- }
+ if (present == 0)
+ dw_mci_reset(host);
spin_unlock_bh(host-lock);
@@ -2208,8 +2201,11 @@ static bool dw_mci_ctrl_reset(struct dw_mci *host, u32
reset)
return false;
}
-static inline bool dw_mci_fifo_reset(struct dw_mci *host)
+static bool dw_mci_reset(struct dw_mci *host)
{
+ u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
+ bool ret = false;
+
/*
* Reseting generates a block interrupt, hence setting
* the scatter-gather pointer to NULL.
@@ -2219,15 +2215,60 @@ static inline bool dw_mci_fifo_reset(struct dw_mci
*host)
host-sg = NULL;
}
- return dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET);
-}
+ if (host-use_dma)
+ flags |= SDMMC_CTRL_DMA_RESET;
-static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host)
-{
- return dw_mci_ctrl_reset(host,
-SDMMC_CTRL_FIFO_RESET |
-SDMMC_CTRL_RESET |
-SDMMC_CTRL_DMA_RESET);
+ if (dw_mci_ctrl_reset(host, flags)) {
+ /*
+* In all cases we clear the RAWINTS register to clear any
+* interrupts.
+*/
+ mci_writel(host, RINTSTS, 0x);
+
+ /* if using dma we wait for dma_req to clear */
+ if (host-use_dma) {
+ unsigned long timeout = jiffies + msecs_to_jiffies(500);
+ u32 status;
+ do {
+ status = mci_readl(host, STATUS);
+ if (!(status SDMMC_STATUS_DMA_REQ))
+ break;
+ cpu_relax();
+ } while (time_before(jiffies, timeout));
+
+ if (status SDMMC_STATUS_DMA_REQ) {
+ dev_err(host-dev,
+ %s: Timeout waiting for dma_req to
+ clear during reset\n, __func__);
+ goto ciu_out;
+ }
+
+ /* when using DMA next we reset the fifo again */
+ if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
+ goto ciu_out;
+ }
+ } else {
+ /* if the controller reset bit did clear, then set clock regs */
+ if (!(mci_readl(host, CTRL) SDMMC_CTRL_RESET)) {
+
