Re: [v3,1/9] clk: samsung: exynos5433: Add clocks for CMU_APOLLO domain
Hi Pankaj and Sylwester,
On Thu, Feb 5, 2015 at 6:56 PM, Sylwester Nawrocki
s.nawro...@samsung.com wrote:
On 05/02/15 08:44, Pankaj Dubey wrote:
+static struct samsung_gate_clock apollo_gate_clks[] __initdata = {
+
+ /* ENABLE_PCLK_APOLLO */
+ GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, pclk_asapbmst_cssys_apollo,
+ div_pclk_dbg_apollo, ENABLE_PCLK_APOLLO,
+ 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PMU_APOLLO, pclk_pmu_apollo, div_pclk_apollo,
+ ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_APOLLO, pclk_pmu_sysreg_apollo,
Isn't pclk_pmu_sysreg_apollo be named as pclk_sysreg_apollo to match
with UM?
You're right. It is my mistake.
Sounds reasonable, Chanwoo, if you agree I'll squash following change
to this patch before sending upstream:
I agree.
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 7a024cd..387e3e3 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -3656,7 +3656,7 @@ static struct samsung_gate_clock apollo_gate_clks[]
__initdata = {
2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_PMU_APOLLO, pclk_pmu_apollo, div_pclk_apollo,
ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
- GATE(CLK_PCLK_SYSREG_APOLLO, pclk_pmu_sysreg_apollo,
+ GATE(CLK_PCLK_SYSREG_APOLLO, pclk_sysreg_apollo,
div_pclk_apollo, ENABLE_PCLK_APOLLO,
0, CLK_IGNORE_UNUSED, 0),
Best Regards,
Chanwoo Choi
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Re: [v3,1/9] clk: samsung: exynos5433: Add clocks for CMU_APOLLO domain
On 05/02/15 08:44, Pankaj Dubey wrote:
+static struct samsung_gate_clock apollo_gate_clks[] __initdata = {
+
+ /* ENABLE_PCLK_APOLLO */
+ GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, pclk_asapbmst_cssys_apollo,
+ div_pclk_dbg_apollo, ENABLE_PCLK_APOLLO,
+ 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_PMU_APOLLO, pclk_pmu_apollo, div_pclk_apollo,
+ ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_APOLLO, pclk_pmu_sysreg_apollo,
Isn't pclk_pmu_sysreg_apollo be named as pclk_sysreg_apollo to match
with UM?
Sounds reasonable, Chanwoo, if you agree I'll squash following change
to this patch before sending upstream:
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 7a024cd..387e3e3 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -3656,7 +3656,7 @@ static struct samsung_gate_clock apollo_gate_clks[]
__initdata = {
2, CLK_IGNORE_UNUSED, 0),
GATE(CLK_PCLK_PMU_APOLLO, pclk_pmu_apollo, div_pclk_apollo,
ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
- GATE(CLK_PCLK_SYSREG_APOLLO, pclk_pmu_sysreg_apollo,
+ GATE(CLK_PCLK_SYSREG_APOLLO, pclk_sysreg_apollo,
div_pclk_apollo, ENABLE_PCLK_APOLLO,
0, CLK_IGNORE_UNUSED, 0),
--
Thanks,
Sylwester
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Re: [v3,1/9] clk: samsung: exynos5433: Add clocks for CMU_APOLLO domain
Hi Chanwoo,
On Tuesday 03 February 2015 05:43 AM, Chanwoo Choi wrote:
This patch adds the mux/divider/gate clocks for CMU_APOLLO domain which
generates the clocks for Cortex-A53 Quad-core processsor.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 15 ++
drivers/clk/samsung/clk-exynos5433.c | 193 +
include/dt-bindings/clock/exynos5433.h | 37
3 files changed, 245 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 9e7ed2d..0a71468 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -32,6 +32,8 @@ Required Properties:
which generates clocks for 3D Graphics Engine IP.
- samsung,exynos5433-cmu-gscl - clock controller compatible for CMU_GSCL
which generates clocks for GSCALER IPs.
+ - samsung,exynos5433-cmu-apollo- clock controller compatible for CMU_APOLLO
+which generates clocks for Cortex-A53 Quad-core processor.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -105,6 +107,10 @@ Required Properties:
- aclk_gscl_111
- aclk_gscl_333
+ Input clocks for apollo clock controller:
+ - oscclk
+ - sclk_bus_pll_apollo
+
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume.
@@ -289,6 +295,15 @@ Example 2: Examples of clock controller nodes are listed
below.
cmu_top CLK_ACLK_GSCL_333;
};
+ cmu_apollo: clock-controller@1190 {
+ compatible = samsung,exynos5433-cmu-apollo;
+ reg = 0x1190 0x1088;
+ #clock-cells = 1;
+
+ clock-names = oscclk, sclk_bus_pll_apollo;
+ clocks = xxti, cmu_mif CLK_SCLK_BUS_PLL_APOLLO;
+ };
+
Example 3: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-exynos5433.c
index 8ae9c48..9a5d33c 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -3393,3 +3393,196 @@ static void __init exynos5433_cmu_gscl_init(struct
device_node *np)
}
CLK_OF_DECLARE(exynos5433_cmu_gscl, samsung,exynos5433-cmu-gscl,
exynos5433_cmu_gscl_init);
+
+/*
+ * Register offset definitions for CMU_APOLLO
+ */
+#define APOLLO_PLL_LOCK0x
+#define APOLLO_PLL_CON00x0100
+#define APOLLO_PLL_CON10x0104
+#define APOLLO_PLL_FREQ_DET0x010c
+#define MUX_SEL_APOLLO00x0200
+#define MUX_SEL_APOLLO10x0204
+#define MUX_SEL_APOLLO20x0208
+#define MUX_ENABLE_APOLLO0 0x0300
+#define MUX_ENABLE_APOLLO1 0x0304
+#define MUX_ENABLE_APOLLO2 0x0308
+#define MUX_STAT_APOLLO0 0x0400
+#define MUX_STAT_APOLLO1 0x0404
+#define MUX_STAT_APOLLO2 0x0408
+#define DIV_APOLLO00x0600
+#define DIV_APOLLO10x0604
+#define DIV_APOLLO_PLL_FREQ_DET0x0608
+#define DIV_STAT_APOLLO0 0x0700
+#define DIV_STAT_APOLLO1 0x0704
+#define DIV_STAT_APOLLO_PLL_FREQ_DET 0x0708
+#define ENABLE_ACLK_APOLLO 0x0800
+#define ENABLE_PCLK_APOLLO 0x0900
+#define ENABLE_SCLK_APOLLO 0x0a00
+#define ENABLE_IP_APOLLO0 0x0b00
+#define ENABLE_IP_APOLLO1 0x0b04
+#define CLKOUT_CMU_APOLLO 0x0c00
+#define CLKOUT_CMU_APOLLO_DIV_STAT 0x0c04
+#define ARMCLK_STOPCTRL0x1000
+#define APOLLO_PWR_CTRL0x1020
+#define APOLLO_PWR_CTRL2 0x1024
+#define APOLLO_INTR_SPREAD_ENABLE 0x1080
+#define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084
+#define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088
+
+static unsigned long apollo_clk_regs[] __initdata = {
+ APOLLO_PLL_LOCK,
+ APOLLO_PLL_CON0,
+ APOLLO_PLL_CON1,
+ APOLLO_PLL_FREQ_DET,
+ MUX_SEL_APOLLO0,
+ MUX_SEL_APOLLO1,
+ MUX_SEL_APOLLO2,
+ MUX_ENABLE_APOLLO0,
+ MUX_ENABLE_APOLLO1,
+ MUX_ENABLE_APOLLO2,
+ MUX_STAT_APOLLO0,
+ MUX_STAT_APOLLO1,
+
