[linux-sunxi] Re: [PATCH 12/12] sunxi: add a defconfig for SoPine w/ official baseboard

[icenowy]

在 2017-06-03 09:19，André Przywara 写道：

Hi,

On 26/04/17 15:50, Icenowy Zheng wrote:
The SoPine is a SoM by Pine64, with an Allwinner A64 SoC, a LPDDR3 
DRAM

chip, an AXP803 PMIC, a SPI NOR Flash and a MicroSD slot. The card
detect pin of the MicroSD slot is broken, however, it doesn't matter 
as

the design of SoPine didn't allow hot-swapping the MicroSD card (The
MicroSD slot is at the back of the SoM, and when the SoM is installed 
on

the baseboard, it's nearly impossible to remove the MicroSD).

The official baseboard of it is a board with nearly the same 
connectors

with the original Pine64+, with the MicroUSB power jack replaced, and
at the position of MicroSD slot a eMMC module slot is added.

Add support for SoPine with the official baseboard by adding its
defconfig file. It still uses the device tree of Pine64, however, it
will change after a proper device tree of SoPine with baseboard is
accepted by Linux mainline.


There is some point in this, but I wonder if we actually need to wait
for Linux. In fact since the SoPine has SPI flash, we don't desperately
need a DT in the Linux source tree, since it could just come with the
device - as in U-Boot's DT passed through to the kernel.

So can we have a separate DT, probably including -pine64.dts and at
least adding the eMMC? Could be copy version of the BPi-M64, for
instance.


In fact changing the defconfig is now enough to initialize the MMC2
controller.

See "CONFIG_MMC_SUNXI_SLOT_EXTRA=2" below.



One more below 


Signed-off-by: Icenowy Zheng 
---
 configs/sopine_baseboard_defconfig | 22 ++
 1 file changed, 22 insertions(+)
 create mode 100644 configs/sopine_baseboard_defconfig

diff --git a/configs/sopine_baseboard_defconfig 
b/configs/sopine_baseboard_defconfig

new file mode 100644
index 00..02ffb43d54
--- /dev/null
+++ b/configs/sopine_baseboard_defconfig
@@ -0,0 +1,22 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN50I=y
+CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
+CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
+CONFIG_DRAM_CLK=552
+CONFIG_DRAM_ZQ=3881949
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN=""
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CONSOLE_MUX=y
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y


Can you add the SPL SPI flash options here? This allows loading U-Boot
from SPI flash and makes this much more useful.


Yes, seems useful...



Cheers,
Andre.


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[linux-sunxi] Re: [PATCH 12/12] sunxi: add a defconfig for SoPine w/ official baseboard

[André Przywara]

Hi,

On 26/04/17 15:50, Icenowy Zheng wrote:
> The SoPine is a SoM by Pine64, with an Allwinner A64 SoC, a LPDDR3 DRAM
> chip, an AXP803 PMIC, a SPI NOR Flash and a MicroSD slot. The card
> detect pin of the MicroSD slot is broken, however, it doesn't matter as
> the design of SoPine didn't allow hot-swapping the MicroSD card (The
> MicroSD slot is at the back of the SoM, and when the SoM is installed on
> the baseboard, it's nearly impossible to remove the MicroSD).
> 
> The official baseboard of it is a board with nearly the same connectors
> with the original Pine64+, with the MicroUSB power jack replaced, and
> at the position of MicroSD slot a eMMC module slot is added.
> 
> Add support for SoPine with the official baseboard by adding its
> defconfig file. It still uses the device tree of Pine64, however, it
> will change after a proper device tree of SoPine with baseboard is
> accepted by Linux mainline.

There is some point in this, but I wonder if we actually need to wait
for Linux. In fact since the SoPine has SPI flash, we don't desperately
need a DT in the Linux source tree, since it could just come with the
device - as in U-Boot's DT passed through to the kernel.

So can we have a separate DT, probably including -pine64.dts and at
least adding the eMMC? Could be copy version of the BPi-M64, for
instance.

One more below 

> Signed-off-by: Icenowy Zheng 
> ---
>  configs/sopine_baseboard_defconfig | 22 ++
>  1 file changed, 22 insertions(+)
>  create mode 100644 configs/sopine_baseboard_defconfig
> 
> diff --git a/configs/sopine_baseboard_defconfig 
> b/configs/sopine_baseboard_defconfig
> new file mode 100644
> index 00..02ffb43d54
> --- /dev/null
> +++ b/configs/sopine_baseboard_defconfig
> @@ -0,0 +1,22 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_SUNXI=y
> +CONFIG_MACH_SUN50I=y
> +CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
> +CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
> +CONFIG_DRAM_CLK=552
> +CONFIG_DRAM_ZQ=3881949
> +CONFIG_DRAM_ODT_EN=y
> +CONFIG_MMC0_CD_PIN=""
> +CONFIG_MMC_SUNXI_SLOT_EXTRA=2
> +CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
> +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> +CONFIG_CONSOLE_MUX=y
> +CONFIG_SPL=y
> +# CONFIG_CMD_IMLS is not set
> +# CONFIG_CMD_FLASH is not set
> +# CONFIG_CMD_FPGA is not set
> +# CONFIG_SPL_DOS_PARTITION is not set
> +# CONFIG_SPL_ISO_PARTITION is not set
> +# CONFIG_SPL_EFI_PARTITION is not set
> +CONFIG_SUN8I_EMAC=y
> +CONFIG_USB_EHCI_HCD=y

Can you add the SPL SPI flash options here? This allows loading U-Boot
from SPI flash and makes this much more useful.

Cheers,
Andre.

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[linux-sunxi] Re: [U-Boot] [PATCH 00/12] Big work on sunxi DW DRAM controllers and some new DDR type support

[André Przywara]

On 02/06/17 19:34, Jagan Teki wrote:
> On Wed, Apr 26, 2017 at 8:19 PM, Icenowy Zheng  wrote:
>> This patchset contains several works on the sunxi DesignWare DRAM
>> controllers.
>>
>> The 1st patch made an option for H3-like DRAM controllers
>> (DesignWare ones), which can ease further import of alike controllers.
>>
>> The 2nd and 3rd patches are for supporting 16-bit DW DRAM controllers,
>> in order to add V3s DRAM support (The controller on V3s is 16-bit).
>>
>> The 4th patch adds bank detection code, in order to support some DDR2
>> chips.
>>
>> The 5th patch adds a framework for select DRAM type and timing -- it's
>> needed for boards that use DRAM chips rather than DDR3.
>>
>> The 6th patch enables dual rank detection in the DW DRAM code on SoCs
>> except R40. For R40 the dual rank facility is still not so clear, so it's
>> temporarily disabled.
>>
>> The 7th~9th patches enables support for DRAM initialization and SPL for
>> the V3s SoC, which integrates a DDR2 chip.
>>
>> The 10th and 11th patches adds support for LPDDR3, with the stock boot0
>> timing. (Seen in A83T boot0 source and some leaked H5/R40 libdram source)
>>
>> The 12th patches adds a defconfig for SoPine w/ official baseboard, which
>> utilizes LPDDR3.
>>
>> Icenowy Zheng (12):
>>   sunxi: makes an invisible option for H3-like DRAM controllers
>>   sunxi: Rename bus-width related macros in H3 DRAM code
>>   sunxi: add option for 16-bit DW DRAM controller
>>   sunxi: add bank detection code to H3 DRAM initialization code
>>   sunxi: Add selective DRAM type and timing
>>   sunxi: enable dual rank detection in DesignWare-like DRAM code
>>   sunxi: add support for the DDR2 in V3s SoC
>>   sunxi: add support for V3s DRAM controller
>>   sunxi: enable DRAM initialization and SPL for V3s SoC
>>   sunxi: add LPDDR3 DRAM type support for DesignWare-like DRAM
>> controller
>>   sunxi: add LPDDR3 timing from stock boot0
>>   sunxi: add a defconfig for SoPine w/ official baseboard
> 
> Can you rebase on master and sen it again, difficult to fix the things
> while applying.

... maybe on the way fix the minor things I mentioned in the lower part
of my reply to 11/12?
https://lists.denx.de/pipermail/u-boot/2017-May/290436.html

Cheers,
Andre.

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[linux-sunxi] Re: [U-Boot] [PATCH 12/12] sunxi: add a defconfig for SoPine w/ official baseboard

[André Przywara]

On 03/06/17 00:59, André Przywara wrote:
> Hi,
> 
> On 02/06/17 19:32, Jagan Teki wrote:
>> On Wed, Apr 26, 2017 at 8:20 PM, Icenowy Zheng  wrote:
>>> The SoPine is a SoM by Pine64, with an Allwinner A64 SoC, a LPDDR3 DRAM
>>> chip, an AXP803 PMIC, a SPI NOR Flash and a MicroSD slot. The card
>>> detect pin of the MicroSD slot is broken, however, it doesn't matter as
>>> the design of SoPine didn't allow hot-swapping the MicroSD card (The
>>> MicroSD slot is at the back of the SoM, and when the SoM is installed on
>>> the baseboard, it's nearly impossible to remove the MicroSD).
>>>
>>> The official baseboard of it is a board with nearly the same connectors
>>> with the original Pine64+, with the MicroUSB power jack replaced, and
>>> at the position of MicroSD slot a eMMC module slot is added.
>>>
>>> Add support for SoPine with the official baseboard by adding its
>>> defconfig file. It still uses the device tree of Pine64, however, it
>>> will change after a proper device tree of SoPine with baseboard is
>>> accepted by Linux mainline.
>>>
>>> Signed-off-by: Icenowy Zheng 
>>> ---
>>>  configs/sopine_baseboard_defconfig | 22 ++
>>>  1 file changed, 22 insertions(+)
>>>  create mode 100644 configs/sopine_baseboard_defconfig
>>>
>>> diff --git a/configs/sopine_baseboard_defconfig
>>
>> Can't this be simply sopine_defconfig
> 
> No, because the SoPine module itself is not complete and the system's DT


> may be much different between using different baseboards. So using the
> term "baseboard" in there is correct. Question is whether we want to
> have a separate sopine.dtsi, which just describes the module, then
> (multiple) baseboard .dts files including this sopine.dtsi. But this is
> a bit premature until we actually see a second baseboard, at which point
> we could still split this up then.

Argh, just saw that I misread defconfig for DT here, sorry. But the
argument still stands: the SoPine module itself has only a bit of
functionality and is not usable on its own, so any board configuration
must be considered as being together with some kind of base board.
For instance the eMMC, HDMI socket and Ethernet PHY is not on the SoPine
module.

Cheers,
Andre.

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[linux-sunxi] Re: [U-Boot] [PATCH 12/12] sunxi: add a defconfig for SoPine w/ official baseboard

[André Przywara]

Hi,

On 02/06/17 19:32, Jagan Teki wrote:
> On Wed, Apr 26, 2017 at 8:20 PM, Icenowy Zheng  wrote:
>> The SoPine is a SoM by Pine64, with an Allwinner A64 SoC, a LPDDR3 DRAM
>> chip, an AXP803 PMIC, a SPI NOR Flash and a MicroSD slot. The card
>> detect pin of the MicroSD slot is broken, however, it doesn't matter as
>> the design of SoPine didn't allow hot-swapping the MicroSD card (The
>> MicroSD slot is at the back of the SoM, and when the SoM is installed on
>> the baseboard, it's nearly impossible to remove the MicroSD).
>>
>> The official baseboard of it is a board with nearly the same connectors
>> with the original Pine64+, with the MicroUSB power jack replaced, and
>> at the position of MicroSD slot a eMMC module slot is added.
>>
>> Add support for SoPine with the official baseboard by adding its
>> defconfig file. It still uses the device tree of Pine64, however, it
>> will change after a proper device tree of SoPine with baseboard is
>> accepted by Linux mainline.
>>
>> Signed-off-by: Icenowy Zheng 
>> ---
>>  configs/sopine_baseboard_defconfig | 22 ++
>>  1 file changed, 22 insertions(+)
>>  create mode 100644 configs/sopine_baseboard_defconfig
>>
>> diff --git a/configs/sopine_baseboard_defconfig
> 
> Can't this be simply sopine_defconfig

No, because the SoPine module itself is not complete and the system's DT
may be much different between using different baseboards. So using the
term "baseboard" in there is correct. Question is whether we want to
have a separate sopine.dtsi, which just describes the module, then
(multiple) baseboard .dts files including this sopine.dtsi. But this is
a bit premature until we actually see a second baseboard, at which point
we could still split this up then.

Cheers,
Andre.

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[linux-sunxi] Re: [PATCH v6 00/21] net-next: stmmac: add dwmac-sun8i ethernet driver

[Maxime Ripard]

Hi,

On Fri, Jun 02, 2017 at 10:22:05AM -0400, David Miller wrote:
> From: Maxime Ripard 
> Date: Fri, 2 Jun 2017 11:13:20 +0200
> 
> > On Fri, Jun 02, 2017 at 08:37:52AM +0200, Maxime Ripard wrote:
> >> On Thu, Jun 01, 2017 at 02:58:19PM -0400, David Miller wrote:
> >> > From: Corentin Labbe 
> >> > Date: Wed, 31 May 2017 09:18:31 +0200
> >> > 
> >> > > This patch series add the driver for dwmac-sun8i which handle the 
> >> > > Ethernet MAC
> >> > > present on Allwinner H3/H5/A83T/A64 SoCs.
> >> > 
> >> > Series applied, but wow that's a lot of DT file changes :-(
> >> 
> >> The DT patches should not go through your tree, but arm-soc, so I
> >> guess this is not an issue for you?
> > 
> > Ok, so I saw that you actually merged them. Can you revert or drop
> > that merge for the DT part?
> > 
> > This will generate a lot of conflicts with our tree, and I'm not sure
> > this would be efficient to make you take all the entirely unrelated to
> > next patches.
> 
> Please tell me which specific changes to revert.
> 
> Thank you.

Ideally everything from 2c0cba482e79 ("arm: sun8i: sunxi-h3-h5: Add dt
node for the syscon control module") to 2428fd0fe550 ("arm64:
defconfig: Enable dwmac-sun8i driver on defconfig")

Thanks!
Maxime

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Re: [linux-sunxi] Re: [RFC PATCH 07/11] drm: sun4i: add support for the TV encoder in H3 SoC

[Maxime Ripard]

On Thu, Jun 01, 2017 at 10:11:14PM +0800, icen...@aosc.io wrote:
> 在 2017-06-01 02:43，Maxime Ripard 写道：
> > On Wed, May 24, 2017 at 04:25:46PM +0800, Icenowy Zheng wrote:
> > > 
> > > 
> > > 于 2017年5月24日 GMT+08:00 下午3:30:19, Maxime Ripard
> > >  写到:
> > > >On Tue, May 23, 2017 at 09:00:59PM +0800, icen...@aosc.io wrote:
> > > >> 在 2017-05-23 20:53，Maxime Ripard 写道：
> > > >> > On Mon, May 22, 2017 at 07:55:56PM +0200, Jernej Škrabec wrote:
> > > >> > > Hi,
> > > >> > >
> > > >> > > Dne sobota, 20. maj 2017 ob 03:37:53 CEST je Chen-Yu Tsai
> > > >napisal(a):
> > > >> > > > On Sat, May 20, 2017 at 2:23 AM, Jernej Škrabec
> > > >
> > > >> > > wrote:
> > > >> > > > > Hi,
> > > >> > > > >
> > > >> > > > > Dne petek, 19. maj 2017 ob 20:08:18 CEST je Icenowy Zheng
> > > >napisal(a):
> > > >> > > > >> 于 2017年5月20日 GMT+08:00 上午2:03:30, Maxime Ripard
> > > > > > >> > > > >
> > > >> > > > > electrons.com> 写到:
> > > >> > > > >> >On Thu, May 18, 2017 at 12:43:50AM +0800, Icenowy Zheng
> > > >wrote:
> > > >> > > > >> >> Allwinner H3 features a TV encoder similar to the one in
> > > >earlier
> > > >> > > > >> >
> > > >> > > > >> >SoCs,
> > > >> > > > >> >
> > > >> > > > >> >> but with some different points about clocks:
> > > >> > > > >> >> - It has a mod clock and a bus clock.
> > > >> > > > >> >> - The mod clock must be at a fixed rate to generate
> > > >signal.
> > > >> > > > >> >
> > > >> > > > >> >Why?
> > > >> > > > >>
> > > >> > > > >> It's experiment result by Jernej.
> > > >> > > > >>
> > > >> > > > >> The clock rates in BSP kernel is also specially designed
> > > >> > > > >> (PLL_DE at 432MHz) in order to be able to feed the TVE.
> > > >> > > > >
> > > >> > > > > My experiments and search through BSP code showed that TVE
> > > >seems to have
> > > >> > > > > additional fixed predivider 8. So if you want to generate 27
> > > >MHz clock,
> > > >> > > > > unit has to be feed with 216 MHz.
> > > >> > > > >
> > > >> > > > > TVE has only one PLL source PLL_DE. And since 216 MHz is a
> > > >bit low for
> > > >> > > > > DE2,
> > > >> > > > > BSP defaults to 432 MHz for PLL_DE and use divider 2 to
> > > >generate 216 MHz.
> > > >> > > > > This clock is then divided by 8 internaly to get final 27
> > > >MHz.
> > > >> > > > >
> > > >> > > > > Please note that I don't have any hard evidence to support
> > > >that, only
> > > >> > > > > experimental data. However, only that explanation make sense
> > > >to me.
> > > >> > > > >
> > > >> > > > > BTW, BSP H3/H5 TV driver supports only PAL and NTSC which
> > > >both use 27 MHz
> > > >> > > > > base clock. Further experiments are needed to check if there
> > > >is any
> > > >> > > > > possibility to have other resolutions by manipulating clocks
> > > >and give
> > > >> > > > > other proper settings. I plan to do that, but not in very
> > > >near future.
> > > >> > > >
> > > >> > > > You only have composite video output, and those are the only 2
> > > >standard
> > > >> > > > resolutions that make any sense.
> > > >> > >
> > > >> > > Right, other resolutions are for VGA.
> > > >> > >
> > > >> > > Anyway, I did some more digging in A10 and R40 datasheets. I
> > > >think
> > > >> > > that H3 TVE
> > > >> > > unit is something in between. R40 TVE has a setting to select "up
> > > >> > > sample".
> > > >> >
> > > >> > That might be just another translation of oversampling :)
> > > >> >
> > > >> > I didn't know it could be applied to composite signals though, but
> > > >I
> > > >> > guess this is just another analog signal after all.
> > > >> >
> > > >> > > Possible settings are 27 MHz, 54 MHz, 108 MHz and 216 MHz. BSP
> > > >> > > driver on R40
> > > >> > > has this setting enabled only for PAL and NTSC and it is always
> > > >216
> > > >> > > MHz. I
> > > >> > > think that H3 may have this hardwired to 216 MHz and this would
> > > >be
> > > >> > > the reason
> > > >> > > why 216 MHz is needed.
> > > >> > >
> > > >> > > Has anyone else any better explanation?
> > > >> >
> > > >> > That's already a pretty good one.
> > > >> >
> > > >> > Either way, wether this is upsampling, oversampling or just a
> > > >> > pre-divider, this can and should be dealt with in the mode_set
> > > >> > callback, and not in the probe.
> > > >>
> > > >> I got a better idea -- let TVE driver have the CLK_TVE as an
> > > >> input and create a subclock output with divider 16, and feed this
> > > >> subclock to TCON lcd-ch1.
> > > >>
> > > >> This is a model of the real hardware -- the clock divider is in
> > > >> TVE, not TCON.
> > > >
> > > >That's definitely not a good representation of the hardware. There's
> > > >one clock, it goes to the TCON, period.
> > > 
> > > No, I still think it goes to the TVE as:
> > > 
> > > 1. it's named TVE in datasheet.
> > 
> > Feel free to come up with a better, more sensible explanation?
> > 
> > > 2. Generating signal with such a low resolution but such
> > > a high dotclock is not a good 

Re: [linux-sunxi] [PATCH 1/2] ARM: sun8i: v3s: add device nodes for DE2 display pipeline

[Maxime Ripard]

On Mon, May 29, 2017 at 09:01:59PM +0800, icen...@aosc.io wrote:
> 在 2017-05-29 16:59，Maxime Ripard 写道：
> > On Thu, May 25, 2017 at 10:28:24PM +0800, Icenowy Zheng wrote:
> > >  +   compatible = "allwinner,sun8i-v3s-de2-mixer";
> > >  +   reg = <0x0110 0x10>;
> > > >>>
> > > >>>The display engine also has an interrupt. Please list it
> > > >>
> > > >> It's a overall interrupt for DE2, not mixer interrupt.
> > > >>
> > > >> I will add it after we have proper interrupt chaining facility
> > > >> for DE2.
> > > >>
> > > >> It cannot fit here in mixer node.
> > > >
> > > > Could you elaborate? If it is just shared, then listing it several
> > > > times is OK. If the interrupt registers are not in this address
> > > > space, then
> > > 
> > > The interrupt dealing code is still not so clear, and totally not
> > > present in BSP DE2 code (the BSP just didn't use the interrupt).
> > > 
> > > We doesn't even know where the interrupt register is, and we cannot
> > > promise it's not broken (as their is even no application of it in
> > > BSP).
> > 
> > Whether it's broken or not is out of the question here. Adding it
> > later would either break the DT compatibility, or introduce a crippled
> > driver for users that do not have a recent enough DT. None of the two
> > are really acceptable.
> > 
> > Especially if your plan is to add support for these.
> 
> I have no such plan -- even the BSP driver doesn't use the IRQ at all.

We'll see how it turns out.. I applied that patch.

Maxime

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[linux-sunxi] Re: [PATCH 19/19] ARM: sun6i: a31s: Enable HDMI display output on the MSI Primo81 tablet

[Maxime Ripard]

On Fri, Jun 02, 2017 at 06:10:24PM +0800, Chen-Yu Tsai wrote:
> The MSI Primo81 tablet has a micro HDMI connector at the bottom.
> This is connected to the SoCs HDMI output.
> 
> Enable the display pipeline and the HDMI output.
> 
> Signed-off-by: Chen-Yu Tsai 
> ---
>  arch/arm/boot/dts/sun6i-a31s-primo81.dts | 25 +
>  1 file changed, 25 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts 
> b/arch/arm/boot/dts/sun6i-a31s-primo81.dts
> index f3712753fa42..26154b2f87a3 100644
> --- a/arch/arm/boot/dts/sun6i-a31s-primo81.dts
> +++ b/arch/arm/boot/dts/sun6i-a31s-primo81.dts
> @@ -52,17 +52,42 @@
>  / {
>   model = "MSI Primo81 tablet";
>   compatible = "msi,primo81", "allwinner,sun6i-a31s";
> +
> + hdmi-connector {
> + compatible = "hdmi-connector";
> + type = "c";

Should we add a connector type for this one?

Maxime

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[linux-sunxi] Re: [PATCH 14/19] drm/sun4i: hdmi: Add support for A31's HDMI controller

[Maxime Ripard]

On Fri, Jun 02, 2017 at 06:10:19PM +0800, Chen-Yu Tsai wrote:
> The HDMI controller found in the A31 SoCs is slightly different
> from the one already supported, which is found in the A10s:
> 
>   - Need different initial values for the PLL related registers
> 
>   - Different behavior of the DDC and TMDS clocks
> 
>   - Different register layout for the DDC portion
> 
>   - Separate DDC parent clock
> 
> This patch adds support for it.
> 
> Signed-off-by: Chen-Yu Tsai 
> ---
>  drivers/gpu/drm/sun4i/sun4i_hdmi.h |   3 +
>  drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c | 141 
> +
>  2 files changed, 144 insertions(+)
> 
> diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h 
> b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
> index c63d0bd95963..2589bc92be59 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_hdmi.h
> +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
> @@ -56,10 +56,13 @@
>  #define SUN4I_HDMI_PAD_CTRL0_TXENBIT(23)
>  
>  #define SUN4I_HDMI_PAD_CTRL1_REG 0x204
> +#define SUN4I_HDMI_PAD_CTRL1_UNKNOWN BIT(24) /* set on A31 */
>  #define SUN4I_HDMI_PAD_CTRL1_AMP_OPT BIT(23)
>  #define SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT   BIT(22)
>  #define SUN4I_HDMI_PAD_CTRL1_EMP_OPT BIT(20)
>  #define SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT   BIT(19)
> +#define SUN4I_HDMI_PAD_CTRL1_PWSCK   BIT(18)
> +#define SUN4I_HDMI_PAD_CTRL1_PWSDT   BIT(17)
>  #define SUN4I_HDMI_PAD_CTRL1_REG_DEN BIT(15)
>  #define SUN4I_HDMI_PAD_CTRL1_REG_DENCK   BIT(14)
>  #define SUN4I_HDMI_PAD_CTRL1_REG_EMP(n)  (((n) & 7) << 10)
> diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c 
> b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
> index 9ded40aaed32..e9abf93eb41c 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
> +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
> @@ -293,6 +293,109 @@ static const struct drm_connector_helper_funcs 
> sun4i_hdmi_connector_helper_funcs
>   .get_modes  = sun4i_hdmi_get_modes,
>  };
>  
> +static int sun6i_hdmi_read_sub_block(struct sun4i_hdmi *hdmi,
> +  unsigned int blk, unsigned int offset,
> +  u8 *buf, unsigned int count)
> +{
> + unsigned long reg;
> + int i;
> +
> + reg = readl(hdmi->base + SUN6I_HDMI_DDC_FIFO_CTRL_REG);
> + writel(reg | SUN6I_HDMI_DDC_FIFO_CTRL_CLEAR,
> +hdmi->base + SUN6I_HDMI_DDC_FIFO_CTRL_REG);
> + writel(SUN6I_HDMI_DDC_ADDR_SEGMENT(offset >> 8) |
> +SUN6I_HDMI_DDC_ADDR_EDDC(DDC_SEGMENT_ADDR << 1) |
> +SUN6I_HDMI_DDC_ADDR_OFFSET(offset) |
> +SUN6I_HDMI_DDC_ADDR_SLAVE(DDC_ADDR),
> +hdmi->base + SUN6I_HDMI_DDC_ADDR_REG);
> +
> + writel(SUN6I_HDMI_DDC_CMD_EXPLICIT_EDDC_READ |
> +SUN6I_HDMI_DDC_CMD_BYTE_COUNT(count),
> +hdmi->base + SUN6I_HDMI_DDC_CMD_REG);
> +
> + reg = readl(hdmi->base + SUN6I_HDMI_DDC_CTRL_REG);
> + writel(reg | SUN6I_HDMI_DDC_CTRL_START_CMD,
> +hdmi->base + SUN6I_HDMI_DDC_CTRL_REG);
> +
> + if (readl_poll_timeout(hdmi->base + SUN6I_HDMI_DDC_CTRL_REG, reg,
> +!(reg & SUN6I_HDMI_DDC_CTRL_START_CMD),
> +100, 10))
> + return -EIO;
> +
> + for (i = 0; i < count; i++)
> + buf[i] = readb(hdmi->base + SUN6I_HDMI_DDC_FIFO_DATA_REG);
> +
> + return 0;
> +}
> +
> +static int sun6i_hdmi_read_edid_block(void *data, u8 *buf, unsigned int blk,
> +   size_t length)
> +{
> + struct sun4i_hdmi *hdmi = data;
> + int retry = 2, i;
> +
> + do {
> + for (i = 0; i < length; i += SUN4I_HDMI_DDC_FIFO_SIZE) {
> + unsigned char offset = blk * EDID_LENGTH + i;
> + unsigned int count = min((unsigned 
> int)SUN4I_HDMI_DDC_FIFO_SIZE,
> +  length - i);
> + int ret;
> +
> + ret = sun6i_hdmi_read_sub_block(hdmi, blk, offset,
> + buf + i, count);
> + if (ret)
> + return ret;
> + }
> + } while (!drm_edid_block_valid(buf, blk, true, NULL) && (retry--));
> +
> + return 0;
> +}
> +
> +static int sun6i_hdmi_get_modes(struct drm_connector *connector)
> +{
> + struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector);
> + u32 reg;
> + struct edid *edid;
> + int ret;
> +
> + clk_set_rate(hdmi->ddc_clk, 10);
> + clk_prepare_enable(hdmi->ddc_clk);
> +
> + /* Reset i2c controller */
> + writel(SUN6I_HDMI_DDC_CTRL_ENABLE | SUN6I_HDMI_DDC_CTRL_RESET |
> +SUN6I_HDMI_DDC_CTRL_SDA_ENABLE |
> +SUN6I_HDMI_DDC_CTRL_SCL_ENABLE,
> +hdmi->base + SUN6I_HDMI_DDC_CTRL_REG);
> + if (readl_poll_timeout(hdmi->base + SUN6I_HDMI_DDC_CTRL_REG, reg,
> +  

[linux-sunxi] Re: [PATCH 13/19] drm/sun4i: hdmi: Add support for controller hardware variants

[Maxime Ripard]

On Fri, Jun 02, 2017 at 06:10:18PM +0800, Chen-Yu Tsai wrote:
> The HDMI controller found in earlier Allwinner SoCs have slight
> differences:
> 
>   - Need different initial values for the PLL related registers
> 
>   - Different behavior of the DDC and TMDS clocks
> 
>   - Different register layout for the DDC portion
> 
>   - Separate DDC parent clock on the A31
> 
>   - Explicit reset control
> 
> The clock variants are supported within their implementations,
> which only expose a create function for each variant.
> 
> The different layout of the DDC registers necessitates a separate
> version of struct drm_connector_helper_funcs.
> 
> A new variant data structure is created to store pointers to the
> above functions, structures, and the different initial values.
> Another flag notates whether there is a separate DDC parent clock.
> If not, the TMDS clock is passed to the DDC clock create function,
> as before.
> 
> Signed-off-by: Chen-Yu Tsai 
> ---
>  drivers/clk/sunxi-ng/ccu-sun6i-a31.c   |   2 +-
>  drivers/gpu/drm/sun4i/sun4i_hdmi.h |   8 +++
>  drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c | 114 
> ++---
>  3 files changed, 100 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c 
> b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
> index 4d6078fca9ac..e48186985a51 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
> @@ -610,7 +610,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", 
> lcd_ch1_parents,
>  
>  static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 0x150, BIT(30), 0);
>  
> -static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0);
> +static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x154, BIT(31), 0);

Unrelated change?

>  
>  static const char * const mbus_parents[] = { "osc24M", "pll-periph",
>"pll-ddr" };
> diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h 
> b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
> index c39c2a245339..c63d0bd95963 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_hdmi.h
> +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
> @@ -155,6 +155,8 @@ enum sun4i_hdmi_pkt_type {
>   SUN4I_HDMI_PKT_END = 15,
>  };
>  
> +struct sun4i_hdmi_variant;
> +
>  struct sun4i_hdmi {
>   struct drm_connectorconnector;
>   struct drm_encoder  encoder;
> @@ -162,9 +164,13 @@ struct sun4i_hdmi {
>  
>   void __iomem*base;
>  
> + /* Reset control */
> + struct reset_control*reset;
> +
>   /* Parent clocks */
>   struct clk  *bus_clk;
>   struct clk  *mod_clk;
> + struct clk  *ddc_parent_clk;
>   struct clk  *pll0_clk;
>   struct clk  *pll1_clk;
>  
> @@ -175,6 +181,8 @@ struct sun4i_hdmi {
>   struct sun4i_drv*drv;
>  
>   boolhdmi_monitor;
> +
> + const struct sun4i_hdmi_variant *variant;
>  };
>  
>  int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *clk);
> diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c 
> b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
> index 457614073501..9ded40aaed32 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
> +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
> @@ -20,8 +20,10 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
> +#include 
>  
>  #include "sun4i_backend.h"
>  #include "sun4i_crtc.h"
> @@ -315,6 +317,56 @@ static const struct drm_connector_funcs 
> sun4i_hdmi_connector_funcs = {
>   .atomic_destroy_state   = drm_atomic_helper_connector_destroy_state,
>  };
>  
> +struct sun4i_hdmi_variant {
> + const struct drm_connector_helper_funcs *connector_helpers;
> + int (*ddc_create)(struct sun4i_hdmi *hdmi, struct clk *clk);
> + int (*tmds_create)(struct sun4i_hdmi *hdmi);
> + bool has_ddc_parent_clk;
> + bool has_reset_control;
> +
> + u32 pad_ctrl0_init_val;
> + u32 pad_ctrl1_init_val;
> + u32 pll_ctrl_init_val;
> +};
> +
> +#define SUN4I_HDMI_PAD_CTRL1_MASK(GENMASK(24, 7) | GENMASK(5, 0))
> +#define SUN4I_HDMI_PLL_CTRL_MASK (GENMASK(31, 8) | GENMASK(3, 0))
> +
> +static const struct sun4i_hdmi_variant sun5i_variant = {
> + .connector_helpers  = _hdmi_connector_helper_funcs,
> + .ddc_create = sun4i_ddc_create,
> + .tmds_create= sun4i_tmds_create,

If we store the variants info for those clocks in that structure, we
don't need those functions anymore. This would be cleaner imho.

> + .has_ddc_parent_clk = false,
> + .has_reset_control  = false,

Those two are the default values


Maxime

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[linux-sunxi] Re: [PATCH 12/19] drm/sun4i: hdmi: Support the DDC clock in the A31's HDMI controller

[Maxime Ripard]

On Fri, Jun 02, 2017 at 06:10:17PM +0800, Chen-Yu Tsai wrote:
> On the A31, the HDMI DDC block is different from the one in the
> other SoCs. As far as the DDC clock goes, it has no pre-divider,
> as it is clocked from a slower parent clock, not the TMDS clock.
> The divider offset from the register value is different. And the
> clock control register is at a different offset.
> 
> This patch adds support for this variant.
> 
> Signed-off-by: Chen-Yu Tsai 
> ---
>  drivers/gpu/drm/sun4i/sun4i_hdmi.h |  1 +
>  drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c | 11 +++
>  2 files changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h 
> b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
> index 08c514672fd3..c39c2a245339 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_hdmi.h
> +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
> @@ -178,6 +178,7 @@ struct sun4i_hdmi {
>  };
>  
>  int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *clk);
> +int sun6i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *clk);
>  int sun4i_tmds_create(struct sun4i_hdmi *hdmi);
>  int sun6i_tmds_create(struct sun4i_hdmi *hdmi);
>  
> diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c 
> b/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
> index 9a6b6243e977..b1395e7b242c 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
> +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
> @@ -151,3 +151,14 @@ int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk 
> *parent)
>  {
>   return _sun4i_ddc_create(hdmi, parent, _variant);
>  }
> +
> +static const struct sun4i_ddc_variant sun6i_variant = {
> + .reg_offset = SUN6I_HDMI_DDC_CLK_REG,

This one should be handled through a regmap_field.

Maxime

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[linux-sunxi] Re: [PATCH 10/19] drm/sun4i: hdmi: Rename internal DDC clock to avoid name collision

[Maxime Ripard]

On Fri, Jun 02, 2017 at 06:10:15PM +0800, Chen-Yu Tsai wrote:
> The DDC parent clock on the A31 SoC is also conveniently named
> "hdmi-ddc", which results in a name collision when the hdmi driver
> registers its internal DDC divider clock.
> 
> Rename the internal clock to "hdmi-ddc-divider".
> 
> Signed-off-by: Chen-Yu Tsai 
> ---
>  drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c 
> b/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
> index e1071838f487..9a6b6243e977 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
> +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
> @@ -125,7 +125,7 @@ static int _sun4i_ddc_create(struct sun4i_hdmi *hdmi, 
> struct clk *parent,
>   if (!ddc)
>   return -ENOMEM;
>  
> - init.name = "hdmi-ddc";
> + init.name = "hdmi-ddc-divider";

Can't we rename the CCU clock instead? Having the clock called
hdmi-ddc being the actual clock output on the DDC bus feels more
natural.

Maxime

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[linux-sunxi] Re: [PATCH 02/19] drm/sun4i: add components in two passes with encoders added in second pass

[Maxime Ripard]

On Fri, Jun 02, 2017 at 06:10:07PM +0800, Chen-Yu Tsai wrote:
> The encoder drivers use drm_of_find_possible_crtcs to get upstream
> crtcs from the device tree using of_graph. For the results to be
> correct, encoders must be probed/bound after _all_ crtcs have been
> created. The existing code uses a depth first recursive traversal
> of the of_graph, which means the encoders downstream of the TCON
> get add right after the first TCON. The second TCON or CRTC will
> never be properly associated with encoders connected to it.
> 
> Other platforms, such as Rockchip, deal with this by probing all
> crtcs first, then all subsequent components. This is easy to do
> since the crtcs correspond to just one device node, and are the
> first nodes in the pipeline.
> 
> However with Allwinner SoCs, the function of the CRTC is split between
> the display backend (DE 1.0) or mixer (DE 2.0), which does scan-out
> and compositing, and the TCON, which generating the display timing
> signals. Further complicating the process, there may be a Dynamic Range
> Controller between the backend and the TCON. Also, the backend is
> preceded by the frontend, with a Display Enhancement Unit possibly
> in between.
> 
> One solution would be, instead of a depth first traversal of the
> component of_graph, we do a breadth first traversal, so that components
> at the same depth are grouped together. This however requires us to
> implement extra code for a queue structure that is only used here.
> 
> Instead, since we can identify TCON device nodes, and since the
> component system can gracefully deal with duplicate entries, we can add
> components in two passes, using the existing recursive depth code. The
> first pass stops right after the TCON is added. The second pass will
> re-add all components up to the TCON, but these will be skipped since
> they will have already been bound with the entries from the first pass.
> The encoders added in the second pass will be the last entries in the
> list.
> 
> Signed-off-by: Chen-Yu Tsai 

This commit log is great. So great actually that it should be a
comment in the code ;)

Maxime

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[linux-sunxi] Re: [U-Boot] [PATCH 00/12] Big work on sunxi DW DRAM controllers and some new DDR type support

[Jagan Teki]

On Wed, Apr 26, 2017 at 8:19 PM, Icenowy Zheng  wrote:
> This patchset contains several works on the sunxi DesignWare DRAM
> controllers.
>
> The 1st patch made an option for H3-like DRAM controllers
> (DesignWare ones), which can ease further import of alike controllers.
>
> The 2nd and 3rd patches are for supporting 16-bit DW DRAM controllers,
> in order to add V3s DRAM support (The controller on V3s is 16-bit).
>
> The 4th patch adds bank detection code, in order to support some DDR2
> chips.
>
> The 5th patch adds a framework for select DRAM type and timing -- it's
> needed for boards that use DRAM chips rather than DDR3.
>
> The 6th patch enables dual rank detection in the DW DRAM code on SoCs
> except R40. For R40 the dual rank facility is still not so clear, so it's
> temporarily disabled.
>
> The 7th~9th patches enables support for DRAM initialization and SPL for
> the V3s SoC, which integrates a DDR2 chip.
>
> The 10th and 11th patches adds support for LPDDR3, with the stock boot0
> timing. (Seen in A83T boot0 source and some leaked H5/R40 libdram source)
>
> The 12th patches adds a defconfig for SoPine w/ official baseboard, which
> utilizes LPDDR3.
>
> Icenowy Zheng (12):
>   sunxi: makes an invisible option for H3-like DRAM controllers
>   sunxi: Rename bus-width related macros in H3 DRAM code
>   sunxi: add option for 16-bit DW DRAM controller
>   sunxi: add bank detection code to H3 DRAM initialization code
>   sunxi: Add selective DRAM type and timing
>   sunxi: enable dual rank detection in DesignWare-like DRAM code
>   sunxi: add support for the DDR2 in V3s SoC
>   sunxi: add support for V3s DRAM controller
>   sunxi: enable DRAM initialization and SPL for V3s SoC
>   sunxi: add LPDDR3 DRAM type support for DesignWare-like DRAM
> controller
>   sunxi: add LPDDR3 timing from stock boot0
>   sunxi: add a defconfig for SoPine w/ official baseboard

Can you rebase on master and sen it again, difficult to fix the things
while applying.

thanks!
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Hyderabad, India.

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[linux-sunxi] Re: [U-Boot] [PATCH 12/12] sunxi: add a defconfig for SoPine w/ official baseboard

[Jagan Teki]

On Wed, Apr 26, 2017 at 8:20 PM, Icenowy Zheng  wrote:
> The SoPine is a SoM by Pine64, with an Allwinner A64 SoC, a LPDDR3 DRAM
> chip, an AXP803 PMIC, a SPI NOR Flash and a MicroSD slot. The card
> detect pin of the MicroSD slot is broken, however, it doesn't matter as
> the design of SoPine didn't allow hot-swapping the MicroSD card (The
> MicroSD slot is at the back of the SoM, and when the SoM is installed on
> the baseboard, it's nearly impossible to remove the MicroSD).
>
> The official baseboard of it is a board with nearly the same connectors
> with the original Pine64+, with the MicroUSB power jack replaced, and
> at the position of MicroSD slot a eMMC module slot is added.
>
> Add support for SoPine with the official baseboard by adding its
> defconfig file. It still uses the device tree of Pine64, however, it
> will change after a proper device tree of SoPine with baseboard is
> accepted by Linux mainline.
>
> Signed-off-by: Icenowy Zheng 
> ---
>  configs/sopine_baseboard_defconfig | 22 ++
>  1 file changed, 22 insertions(+)
>  create mode 100644 configs/sopine_baseboard_defconfig
>
> diff --git a/configs/sopine_baseboard_defconfig

Can't this be simply sopine_defconfig

Please add MAINTAINERS entry as well

thanks!
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Hyderabad, India.

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[linux-sunxi] Re: [U-Boot] [PATCH v2] sun50i: h5: Add initial Orangepi Prime support

[Jagan Teki]

On Fri, Jun 2, 2017 at 6:53 PM, Maxime Ripard
 wrote:
> On Thu, Jun 01, 2017 at 03:25:32PM +, Jagan Teki wrote:
>> From: Jagan Teki 
>>
>> Orangepi Prime is an open-source single-board computer
>> using the Allwinner h5 SOC.
>>
>> H5 Orangepi Prime has
>> - Quad-core Cortex-A53
>> - 2GB DDR3
>> - Debug TTL UART
>> - 1000M/100M Ethernet RJ45
>> - Three USB 2.0
>> - HDMI
>> - Audio and MIC
>> - Wifi + BT
>> - IR receiver
>> - HDMI
>> - Wifi + BT
>>
>> Boot from MMC:
>> -
>> U-Boot SPL 2017.05-00662-ga3f4c05-dirty (May 25 2017 - 13:30:14)
>> DRAM: 2048 MiB
>> Trying to boot from MMC1
>> NOTICE:  BL3-1: Running on H5 (1718) in SRAM A2 (@0x44000)
>> NOTICE:  Configuring SPC Controller
>> NOTICE:  BL3-1: v1.0(debug):aa75c8d
>> NOTICE:  BL3-1: Built : 18:28:27, May 24 2017
>> INFO:BL3-1: Initializing runtime services
>> INFO:BL3-1: Preparing for EL3 exit to normal world
>> INFO:BL3-1: Next image address: 0x4a00, SPSR: 0x3c9
>>
>> U-Boot 2017.05-00662-ga3f4c05-dirty (May 25 2017 - 13:30:14 +) Allwinner 
>> Technology
>>
>> CPU:   Allwinner H5 (SUN50I)
>> Model: OrangePi Prime
>> DRAM:  2 GiB
>> MMC:   SUNXI SD/MMC: 0
>> *** Warning - bad CRC, using default environment
>>
>> In:serial
>> Out:   serial
>> Err:   serial
>> Net:   phy interface7
>> eth0: ethernet@1c3
>> starting USB...
>> USB0:   USB EHCI 1.00
>> USB1:   USB OHCI 1.0
>> scanning bus 0 for devices... 1 USB Device(s) found
>>scanning usb for storage devices... 0 Storage Device(s) found
>> Hit any key to stop autoboot:  0
>>
>> Signed-off-by: Jagan Teki 
>
> Acked-by: Maxime Ripard 

Applied to u-boot-sunxi/master

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

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Re: [linux-sunxi] [PATCH v2] sun50i: h5: Add initial Orangepi Prime support

[Maxime Ripard]

On Fri, Jun 02, 2017 at 10:31:48PM +0800, icen...@aosc.io wrote:
> 在 2017-06-01 23:25，Jagan Teki 写道：
> > From: Jagan Teki 
> > 
> > Orangepi Prime is an open-source single-board computer
> > using the Allwinner h5 SOC.
> > 
> > H5 Orangepi Prime has
> > - Quad-core Cortex-A53
> > - 2GB DDR3
> > - Debug TTL UART
> > - 1000M/100M Ethernet RJ45
> > - Three USB 2.0
> > - HDMI
> > - Audio and MIC
> > - Wifi + BT
> > - IR receiver
> > - HDMI
> > - Wifi + BT
> > 
> > Boot from MMC:
> > -
> > U-Boot SPL 2017.05-00662-ga3f4c05-dirty (May 25 2017 - 13:30:14)
> > DRAM: 2048 MiB
> > Trying to boot from MMC1
> > NOTICE:  BL3-1: Running on H5 (1718) in SRAM A2 (@0x44000)
> > NOTICE:  Configuring SPC Controller
> > NOTICE:  BL3-1: v1.0(debug):aa75c8d
> > NOTICE:  BL3-1: Built : 18:28:27, May 24 2017
> > INFO:BL3-1: Initializing runtime services
> > INFO:BL3-1: Preparing for EL3 exit to normal world
> > INFO:BL3-1: Next image address: 0x4a00, SPSR: 0x3c9
> > 
> > U-Boot 2017.05-00662-ga3f4c05-dirty (May 25 2017 - 13:30:14 +)
> > Allwinner Technology
> > 
> > CPU:   Allwinner H5 (SUN50I)
> > Model: OrangePi Prime
> > DRAM:  2 GiB
> > MMC:   SUNXI SD/MMC: 0
> > *** Warning - bad CRC, using default environment
> > 
> > In:serial
> > Out:   serial
> > Err:   serial
> > Net:   phy interface7
> > eth0: ethernet@1c3
> > starting USB...
> > USB0:   USB EHCI 1.00
> > USB1:   USB OHCI 1.0
> > scanning bus 0 for devices... 1 USB Device(s) found
> >scanning usb for storage devices... 0 Storage Device(s) found
> > Hit any key to stop autoboot:  0
> > 
> > Signed-off-by: Jagan Teki 
> > ---
> > Changes for v2:
> > - Drop http link from commit message
> > - Drop CONFIG_CONSOLE_MUX
> 
> Why drop this?
> 
> I think now vidconsole is working on H5...

Because it doesn't make any sense to have it in only one or a fraction
of the boards we support.

This is something the user should choose, and opt in.

Maxime

-- 
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Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [linux-sunxi] [PATCH v2] sun50i: h5: Add initial Orangepi Prime support

[icenowy]

在 2017-06-01 23:25，Jagan Teki 写道：

From: Jagan Teki 

Orangepi Prime is an open-source single-board computer
using the Allwinner h5 SOC.

H5 Orangepi Prime has
- Quad-core Cortex-A53
- 2GB DDR3
- Debug TTL UART
- 1000M/100M Ethernet RJ45
- Three USB 2.0
- HDMI
- Audio and MIC
- Wifi + BT
- IR receiver
- HDMI
- Wifi + BT

Boot from MMC:
-
U-Boot SPL 2017.05-00662-ga3f4c05-dirty (May 25 2017 - 13:30:14)
DRAM: 2048 MiB
Trying to boot from MMC1
NOTICE:  BL3-1: Running on H5 (1718) in SRAM A2 (@0x44000)
NOTICE:  Configuring SPC Controller
NOTICE:  BL3-1: v1.0(debug):aa75c8d
NOTICE:  BL3-1: Built : 18:28:27, May 24 2017
INFO:BL3-1: Initializing runtime services
INFO:BL3-1: Preparing for EL3 exit to normal world
INFO:BL3-1: Next image address: 0x4a00, SPSR: 0x3c9

U-Boot 2017.05-00662-ga3f4c05-dirty (May 25 2017 - 13:30:14 +)
Allwinner Technology

CPU:   Allwinner H5 (SUN50I)
Model: OrangePi Prime
DRAM:  2 GiB
MMC:   SUNXI SD/MMC: 0
*** Warning - bad CRC, using default environment

In:serial
Out:   serial
Err:   serial
Net:   phy interface7
eth0: ethernet@1c3
starting USB...
USB0:   USB EHCI 1.00
USB1:   USB OHCI 1.0
scanning bus 0 for devices... 1 USB Device(s) found
   scanning usb for storage devices... 0 Storage Device(s) found
Hit any key to stop autoboot:  0

Signed-off-by: Jagan Teki 
---
Changes for v2:
- Drop http link from commit message
- Drop CONFIG_CONSOLE_MUX


Why drop this?

I think now vidconsole is working on H5...



 arch/arm/dts/Makefile |   3 +-
 arch/arm/dts/sun50i-h5-orangepi-prime.dts | 104 
++

 board/sunxi/MAINTAINERS   |   5 ++
 configs/orangepi_prime_defconfig  |  16 +
 4 files changed, 127 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/sun50i-h5-orangepi-prime.dts
 create mode 100644 configs/orangepi_prime_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 82671b3..b8ebd6e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -315,7 +315,8 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \
 dtb-$(CONFIG_MACH_SUN8I_V3S) += \
sun8i-v3s-licheepi-zero.dtb
 dtb-$(CONFIG_MACH_SUN50I_H5) += \
-   sun50i-h5-orangepi-pc2.dtb
+   sun50i-h5-orangepi-pc2.dtb \
+   sun50i-h5-orangepi-prime.dtb
 dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-bananapi-m64.dtb \
sun50i-a64-pine64-plus.dtb \
diff --git a/arch/arm/dts/sun50i-h5-orangepi-prime.dts
b/arch/arm/dts/sun50i-h5-orangepi-prime.dts
new file mode 100644
index 000..67eade7
--- /dev/null
+++ b/arch/arm/dts/sun50i-h5-orangepi-prime.dts
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2017 Jagan Teki 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of 
the

+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h5.dtsi"
+
+#include 
+
+/ {
+   model = "OrangePi Prime";
+   compatible = "xunlong,orangepi-prime", "allwinner,sun50i-h5";
+
+   aliases {
+   serial0 = 
+   };
+
+   chosen {
+  

[linux-sunxi] Re: [PATCH v6 00/21] net-next: stmmac: add dwmac-sun8i ethernet driver

[David Miller]

From: Maxime Ripard 
Date: Fri, 2 Jun 2017 11:13:20 +0200

> On Fri, Jun 02, 2017 at 08:37:52AM +0200, Maxime Ripard wrote:
>> On Thu, Jun 01, 2017 at 02:58:19PM -0400, David Miller wrote:
>> > From: Corentin Labbe 
>> > Date: Wed, 31 May 2017 09:18:31 +0200
>> > 
>> > > This patch series add the driver for dwmac-sun8i which handle the 
>> > > Ethernet MAC
>> > > present on Allwinner H3/H5/A83T/A64 SoCs.
>> > 
>> > Series applied, but wow that's a lot of DT file changes :-(
>> 
>> The DT patches should not go through your tree, but arm-soc, so I
>> guess this is not an issue for you?
> 
> Ok, so I saw that you actually merged them. Can you revert or drop
> that merge for the DT part?
> 
> This will generate a lot of conflicts with our tree, and I'm not sure
> this would be efficient to make you take all the entirely unrelated to
> next patches.

Please tell me which specific changes to revert.

Thank you.

[linux-sunxi] Re: [PATCH v6 00/21] net-next: stmmac: add dwmac-sun8i ethernet driver

[David Miller]

From: Maxime Ripard 
Date: Fri, 2 Jun 2017 08:37:52 +0200

> On Thu, Jun 01, 2017 at 02:58:19PM -0400, David Miller wrote:
>> From: Corentin Labbe 
>> Date: Wed, 31 May 2017 09:18:31 +0200
>> 
>> > This patch series add the driver for dwmac-sun8i which handle the Ethernet 
>> > MAC
>> > present on Allwinner H3/H5/A83T/A64 SoCs.
>> 
>> Series applied, but wow that's a lot of DT file changes :-(
> 
> The DT patches should not go through your tree, but arm-soc, so I
> guess this is not an issue for you?

I already applied them, so if that is the intention, too late.

This needs to be explicitly stated in the header posting.  Otherwise
I assume the entire series is meant to go into my tree.

Also, saying "net-next" in the patch subjects means it's targetting my
tree.

[linux-sunxi] Re: [PATCH v2] sun50i: h5: Add initial Orangepi Prime support

[Maxime Ripard]

On Thu, Jun 01, 2017 at 03:25:32PM +, Jagan Teki wrote:
> From: Jagan Teki 
> 
> Orangepi Prime is an open-source single-board computer
> using the Allwinner h5 SOC.
> 
> H5 Orangepi Prime has
> - Quad-core Cortex-A53
> - 2GB DDR3
> - Debug TTL UART
> - 1000M/100M Ethernet RJ45
> - Three USB 2.0
> - HDMI
> - Audio and MIC
> - Wifi + BT
> - IR receiver
> - HDMI
> - Wifi + BT
> 
> Boot from MMC:
> -
> U-Boot SPL 2017.05-00662-ga3f4c05-dirty (May 25 2017 - 13:30:14)
> DRAM: 2048 MiB
> Trying to boot from MMC1
> NOTICE:  BL3-1: Running on H5 (1718) in SRAM A2 (@0x44000)
> NOTICE:  Configuring SPC Controller
> NOTICE:  BL3-1: v1.0(debug):aa75c8d
> NOTICE:  BL3-1: Built : 18:28:27, May 24 2017
> INFO:BL3-1: Initializing runtime services
> INFO:BL3-1: Preparing for EL3 exit to normal world
> INFO:BL3-1: Next image address: 0x4a00, SPSR: 0x3c9
> 
> U-Boot 2017.05-00662-ga3f4c05-dirty (May 25 2017 - 13:30:14 +) Allwinner 
> Technology
> 
> CPU:   Allwinner H5 (SUN50I)
> Model: OrangePi Prime
> DRAM:  2 GiB
> MMC:   SUNXI SD/MMC: 0
> *** Warning - bad CRC, using default environment
> 
> In:serial
> Out:   serial
> Err:   serial
> Net:   phy interface7
> eth0: ethernet@1c3
> starting USB...
> USB0:   USB EHCI 1.00
> USB1:   USB OHCI 1.0
> scanning bus 0 for devices... 1 USB Device(s) found
>scanning usb for storage devices... 0 Storage Device(s) found
> Hit any key to stop autoboot:  0
> 
> Signed-off-by: Jagan Teki 

Acked-by: Maxime Ripard 

-- 
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Embedded Linux and Kernel engineering
http://free-electrons.com

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[linux-sunxi] [PATCH 18/19] ARM: sun6i: a31s: Enable HDMI display output on the Sinlinx SinA31s

[Chen-Yu Tsai]

The Sinlinx SinA31s has an HDMI connector wired to the HDMI pins
from the SoC.

Enable the display pipeline and the HDMI output.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun6i-a31s-sina31s.dts | 25 +
 1 file changed, 25 insertions(+)

diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts 
b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
index b3d98222bd81..298476485bb4 100644
--- a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
@@ -53,6 +53,17 @@
stdout-path = "serial0:115200n8";
};
 
+   hdmi-connector {
+   compatible = "hdmi-connector";
+   type = "a";
+
+   port {
+   hdmi_con_in: endpoint {
+   remote-endpoint = <_out_con>;
+   };
+   };
+   };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -90,6 +101,10 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+};
+
  {
/* USB 2.0 4 port hub IC */
status = "okay";
@@ -112,6 +127,16 @@
};
 };
 
+ {
+   status = "okay";
+};
+
+_out {
+   hdmi_out_con: endpoint {
+   remote-endpoint = <_con_in>;
+   };
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
-- 
2.11.0

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[linux-sunxi] [PATCH 16/19] ARM: sun6i: a31: Add device node for HDMI controller

[Chen-Yu Tsai]

Now that we support the HDMI controller on the A31 SoC, we can add it
to the device tree.

This adds a device node for the HDMI controller, and the of_graph nodes
connecting it to the 2 TCONs.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 55 
 1 file changed, 55 insertions(+)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index d0cede5aaeb5..36bfb6ad6578 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -284,6 +284,12 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
+
+   tcon0_out_hdmi: endpoint@1 {
+   reg = <1>;
+   remote-endpoint = 
<_in_tcon0>;
+   allwinner,tcon-channel = <1>;
+   };
};
};
};
@@ -321,6 +327,12 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
+
+   tcon1_out_hdmi: endpoint@1 {
+   reg = <1>;
+   remote-endpoint = 
<_in_tcon1>;
+   allwinner,tcon-channel = <1>;
+   };
};
};
};
@@ -401,6 +413,49 @@
#size-cells = <0>;
};
 
+   hdmi: hdmi@01c16000 {
+   compatible = "allwinner,sun6i-a31-hdmi";
+   reg = <0x01c16000 0x1000>;
+   interrupts = ;
+   clocks = < CLK_AHB1_HDMI>, < CLK_HDMI>,
+< CLK_HDMI_DDC>,
+< CLK_PLL_VIDEO0_2X>,
+< CLK_PLL_VIDEO1_2X>;
+   clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
+   resets = < RST_AHB1_HDMI>;
+   reset-names = "ahb";
+   dma-names = "ddc-tx", "ddc-rx", "audio-tx";
+   dmas = < 13>, < 13>, < 14>;
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   hdmi_in: port@0 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0>;
+
+   hdmi_in_tcon0: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = 
<_out_hdmi>;
+   };
+
+   hdmi_in_tcon1: endpoint@1 {
+   reg = <1>;
+   remote-endpoint = 
<_out_hdmi>;
+   };
+   };
+
+   hdmi_out: port@1 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <1>;
+   };
+   };
+   };
+
usb_otg: usb@01c19000 {
compatible = "allwinner,sun6i-a31-musb";
reg = <0x01c19000 0x0400>;
-- 
2.11.0

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[linux-sunxi] [PATCH 14/19] drm/sun4i: hdmi: Add support for A31's HDMI controller

[Chen-Yu Tsai]

The HDMI controller found in the A31 SoCs is slightly different
from the one already supported, which is found in the A10s:

  - Need different initial values for the PLL related registers

  - Different behavior of the DDC and TMDS clocks

  - Different register layout for the DDC portion

  - Separate DDC parent clock

This patch adds support for it.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/gpu/drm/sun4i/sun4i_hdmi.h |   3 +
 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c | 141 +
 2 files changed, 144 insertions(+)

diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h 
b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
index c63d0bd95963..2589bc92be59 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi.h
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
@@ -56,10 +56,13 @@
 #define SUN4I_HDMI_PAD_CTRL0_TXEN  BIT(23)
 
 #define SUN4I_HDMI_PAD_CTRL1_REG   0x204
+#define SUN4I_HDMI_PAD_CTRL1_UNKNOWN   BIT(24) /* set on A31 */
 #define SUN4I_HDMI_PAD_CTRL1_AMP_OPT   BIT(23)
 #define SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT BIT(22)
 #define SUN4I_HDMI_PAD_CTRL1_EMP_OPT   BIT(20)
 #define SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT BIT(19)
+#define SUN4I_HDMI_PAD_CTRL1_PWSCK BIT(18)
+#define SUN4I_HDMI_PAD_CTRL1_PWSDT BIT(17)
 #define SUN4I_HDMI_PAD_CTRL1_REG_DEN   BIT(15)
 #define SUN4I_HDMI_PAD_CTRL1_REG_DENCK BIT(14)
 #define SUN4I_HDMI_PAD_CTRL1_REG_EMP(n)(((n) & 7) << 10)
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c 
b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
index 9ded40aaed32..e9abf93eb41c 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
@@ -293,6 +293,109 @@ static const struct drm_connector_helper_funcs 
sun4i_hdmi_connector_helper_funcs
.get_modes  = sun4i_hdmi_get_modes,
 };
 
+static int sun6i_hdmi_read_sub_block(struct sun4i_hdmi *hdmi,
+unsigned int blk, unsigned int offset,
+u8 *buf, unsigned int count)
+{
+   unsigned long reg;
+   int i;
+
+   reg = readl(hdmi->base + SUN6I_HDMI_DDC_FIFO_CTRL_REG);
+   writel(reg | SUN6I_HDMI_DDC_FIFO_CTRL_CLEAR,
+  hdmi->base + SUN6I_HDMI_DDC_FIFO_CTRL_REG);
+   writel(SUN6I_HDMI_DDC_ADDR_SEGMENT(offset >> 8) |
+  SUN6I_HDMI_DDC_ADDR_EDDC(DDC_SEGMENT_ADDR << 1) |
+  SUN6I_HDMI_DDC_ADDR_OFFSET(offset) |
+  SUN6I_HDMI_DDC_ADDR_SLAVE(DDC_ADDR),
+  hdmi->base + SUN6I_HDMI_DDC_ADDR_REG);
+
+   writel(SUN6I_HDMI_DDC_CMD_EXPLICIT_EDDC_READ |
+  SUN6I_HDMI_DDC_CMD_BYTE_COUNT(count),
+  hdmi->base + SUN6I_HDMI_DDC_CMD_REG);
+
+   reg = readl(hdmi->base + SUN6I_HDMI_DDC_CTRL_REG);
+   writel(reg | SUN6I_HDMI_DDC_CTRL_START_CMD,
+  hdmi->base + SUN6I_HDMI_DDC_CTRL_REG);
+
+   if (readl_poll_timeout(hdmi->base + SUN6I_HDMI_DDC_CTRL_REG, reg,
+  !(reg & SUN6I_HDMI_DDC_CTRL_START_CMD),
+  100, 10))
+   return -EIO;
+
+   for (i = 0; i < count; i++)
+   buf[i] = readb(hdmi->base + SUN6I_HDMI_DDC_FIFO_DATA_REG);
+
+   return 0;
+}
+
+static int sun6i_hdmi_read_edid_block(void *data, u8 *buf, unsigned int blk,
+ size_t length)
+{
+   struct sun4i_hdmi *hdmi = data;
+   int retry = 2, i;
+
+   do {
+   for (i = 0; i < length; i += SUN4I_HDMI_DDC_FIFO_SIZE) {
+   unsigned char offset = blk * EDID_LENGTH + i;
+   unsigned int count = min((unsigned 
int)SUN4I_HDMI_DDC_FIFO_SIZE,
+length - i);
+   int ret;
+
+   ret = sun6i_hdmi_read_sub_block(hdmi, blk, offset,
+   buf + i, count);
+   if (ret)
+   return ret;
+   }
+   } while (!drm_edid_block_valid(buf, blk, true, NULL) && (retry--));
+
+   return 0;
+}
+
+static int sun6i_hdmi_get_modes(struct drm_connector *connector)
+{
+   struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector);
+   u32 reg;
+   struct edid *edid;
+   int ret;
+
+   clk_set_rate(hdmi->ddc_clk, 10);
+   clk_prepare_enable(hdmi->ddc_clk);
+
+   /* Reset i2c controller */
+   writel(SUN6I_HDMI_DDC_CTRL_ENABLE | SUN6I_HDMI_DDC_CTRL_RESET |
+  SUN6I_HDMI_DDC_CTRL_SDA_ENABLE |
+  SUN6I_HDMI_DDC_CTRL_SCL_ENABLE,
+  hdmi->base + SUN6I_HDMI_DDC_CTRL_REG);
+   if (readl_poll_timeout(hdmi->base + SUN6I_HDMI_DDC_CTRL_REG, reg,
+  !(reg & SUN6I_HDMI_DDC_CTRL_RESET),
+  100, 2000)) {
+   dev_err(hdmi->dev, "DDC reset timeout: %08x\n", reg);
+   

[linux-sunxi] [PATCH 12/19] drm/sun4i: hdmi: Support the DDC clock in the A31's HDMI controller

[Chen-Yu Tsai]

On the A31, the HDMI DDC block is different from the one in the
other SoCs. As far as the DDC clock goes, it has no pre-divider,
as it is clocked from a slower parent clock, not the TMDS clock.
The divider offset from the register value is different. And the
clock control register is at a different offset.

This patch adds support for this variant.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/gpu/drm/sun4i/sun4i_hdmi.h |  1 +
 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c | 11 +++
 2 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h 
b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
index 08c514672fd3..c39c2a245339 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi.h
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
@@ -178,6 +178,7 @@ struct sun4i_hdmi {
 };
 
 int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *clk);
+int sun6i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *clk);
 int sun4i_tmds_create(struct sun4i_hdmi *hdmi);
 int sun6i_tmds_create(struct sun4i_hdmi *hdmi);
 
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c 
b/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
index 9a6b6243e977..b1395e7b242c 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
@@ -151,3 +151,14 @@ int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk 
*parent)
 {
return _sun4i_ddc_create(hdmi, parent, _variant);
 }
+
+static const struct sun4i_ddc_variant sun6i_variant = {
+   .reg_offset = SUN6I_HDMI_DDC_CLK_REG,
+   .pre_divider= 1,
+   .m_offset   = 2,
+};
+
+int sun6i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *parent)
+{
+   return _sun4i_ddc_create(hdmi, parent, _variant);
+}
-- 
2.11.0

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[linux-sunxi] [PATCH 15/19] clk: sunxi-ng: sun6i: Export video PLLs

[Chen-Yu Tsai]

The 2x outputs of the 2 video PLL clocks are directly used by the
HDMI controller block.

Export them so they can be referenced in the device tree.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/clk/sunxi-ng/ccu-sun6i-a31.h  | 8 ++--
 include/dt-bindings/clock/sun6i-a31-ccu.h | 4 
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.h 
b/drivers/clk/sunxi-ng/ccu-sun6i-a31.h
index 4e434011e9e7..27e6ad4133ab 100644
--- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.h
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.h
@@ -27,7 +27,9 @@
 #define CLK_PLL_AUDIO_4X   4
 #define CLK_PLL_AUDIO_8X   5
 #define CLK_PLL_VIDEO0 6
-#define CLK_PLL_VIDEO0_2X  7
+
+/* The PLL_VIDEO0_2X clock is exported */
+
 #define CLK_PLL_VE 8
 #define CLK_PLL_DDR9
 
@@ -35,7 +37,9 @@
 
 #define CLK_PLL_PERIPH_2X  11
 #define CLK_PLL_VIDEO1 12
-#define CLK_PLL_VIDEO1_2X  13
+
+/* The PLL_VIDEO1_2X clock is exported */
+
 #define CLK_PLL_GPU14
 #define CLK_PLL_MIPI   15
 #define CLK_PLL9   16
diff --git a/include/dt-bindings/clock/sun6i-a31-ccu.h 
b/include/dt-bindings/clock/sun6i-a31-ccu.h
index 4482530fb6f5..c5d13340184a 100644
--- a/include/dt-bindings/clock/sun6i-a31-ccu.h
+++ b/include/dt-bindings/clock/sun6i-a31-ccu.h
@@ -43,8 +43,12 @@
 #ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_
 #define _DT_BINDINGS_CLK_SUN6I_A31_H_
 
+#define CLK_PLL_VIDEO0_2X  7
+
 #define CLK_PLL_PERIPH 10
 
+#define CLK_PLL_VIDEO1_2X  13
+
 #define CLK_CPU18
 
 #define CLK_AHB1_MIPIDSI   23
-- 
2.11.0

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[linux-sunxi] [PATCH 13/19] drm/sun4i: hdmi: Add support for controller hardware variants

[Chen-Yu Tsai]

The HDMI controller found in earlier Allwinner SoCs have slight
differences:

  - Need different initial values for the PLL related registers

  - Different behavior of the DDC and TMDS clocks

  - Different register layout for the DDC portion

  - Separate DDC parent clock on the A31

  - Explicit reset control

The clock variants are supported within their implementations,
which only expose a create function for each variant.

The different layout of the DDC registers necessitates a separate
version of struct drm_connector_helper_funcs.

A new variant data structure is created to store pointers to the
above functions, structures, and the different initial values.
Another flag notates whether there is a separate DDC parent clock.
If not, the TMDS clock is passed to the DDC clock create function,
as before.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/clk/sunxi-ng/ccu-sun6i-a31.c   |   2 +-
 drivers/gpu/drm/sun4i/sun4i_hdmi.h |   8 +++
 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c | 114 ++---
 3 files changed, 100 insertions(+), 24 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c 
b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
index 4d6078fca9ac..e48186985a51 100644
--- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
@@ -610,7 +610,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", 
lcd_ch1_parents,
 
 static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 0x150, BIT(30), 0);
 
-static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0);
+static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x154, BIT(31), 0);
 
 static const char * const mbus_parents[] = { "osc24M", "pll-periph",
 "pll-ddr" };
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h 
b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
index c39c2a245339..c63d0bd95963 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi.h
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
@@ -155,6 +155,8 @@ enum sun4i_hdmi_pkt_type {
SUN4I_HDMI_PKT_END = 15,
 };
 
+struct sun4i_hdmi_variant;
+
 struct sun4i_hdmi {
struct drm_connectorconnector;
struct drm_encoder  encoder;
@@ -162,9 +164,13 @@ struct sun4i_hdmi {
 
void __iomem*base;
 
+   /* Reset control */
+   struct reset_control*reset;
+
/* Parent clocks */
struct clk  *bus_clk;
struct clk  *mod_clk;
+   struct clk  *ddc_parent_clk;
struct clk  *pll0_clk;
struct clk  *pll1_clk;
 
@@ -175,6 +181,8 @@ struct sun4i_hdmi {
struct sun4i_drv*drv;
 
boolhdmi_monitor;
+
+   const struct sun4i_hdmi_variant *variant;
 };
 
 int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *clk);
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c 
b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
index 457614073501..9ded40aaed32 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
@@ -20,8 +20,10 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
+#include 
 
 #include "sun4i_backend.h"
 #include "sun4i_crtc.h"
@@ -315,6 +317,56 @@ static const struct drm_connector_funcs 
sun4i_hdmi_connector_funcs = {
.atomic_destroy_state   = drm_atomic_helper_connector_destroy_state,
 };
 
+struct sun4i_hdmi_variant {
+   const struct drm_connector_helper_funcs *connector_helpers;
+   int (*ddc_create)(struct sun4i_hdmi *hdmi, struct clk *clk);
+   int (*tmds_create)(struct sun4i_hdmi *hdmi);
+   bool has_ddc_parent_clk;
+   bool has_reset_control;
+
+   u32 pad_ctrl0_init_val;
+   u32 pad_ctrl1_init_val;
+   u32 pll_ctrl_init_val;
+};
+
+#define SUN4I_HDMI_PAD_CTRL1_MASK  (GENMASK(24, 7) | GENMASK(5, 0))
+#define SUN4I_HDMI_PLL_CTRL_MASK   (GENMASK(31, 8) | GENMASK(3, 0))
+
+static const struct sun4i_hdmi_variant sun5i_variant = {
+   .connector_helpers  = _hdmi_connector_helper_funcs,
+   .ddc_create = sun4i_ddc_create,
+   .tmds_create= sun4i_tmds_create,
+   .has_ddc_parent_clk = false,
+   .has_reset_control  = false,
+   .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN |
+ SUN4I_HDMI_PAD_CTRL0_CKEN |
+ SUN4I_HDMI_PAD_CTRL0_PWENG |
+ SUN4I_HDMI_PAD_CTRL0_PWEND |
+ SUN4I_HDMI_PAD_CTRL0_PWENC |
+ SUN4I_HDMI_PAD_CTRL0_LDODEN |
+ SUN4I_HDMI_PAD_CTRL0_LDOCEN |
+ SUN4I_HDMI_PAD_CTRL0_BIASEN,
+   .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) |
+ SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) |
+ SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
+ 

[linux-sunxi] [PATCH 05/19] drm/sun4i: hdmi: Allow using second PLL as TMDS clk parent

[Chen-Yu Tsai]

On SoCs with two display pipelines, it is possible that the two
pipelines are active at the same time, with potentially incompatible
dot clocks.

Let the HDMI encoder's TMDS clock go through all of its parents when
calculating possible clock rates. This allows usage of the second video
PLL as its parent.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c | 51 -
 1 file changed, 28 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c 
b/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
index 5cf2527bffc8..5692e41833ae 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
@@ -71,7 +71,7 @@ static int sun4i_tmds_determine_rate(struct clk_hw *hw,
unsigned long best_parent = 0;
unsigned long rate = req->rate;
int best_div = 1, best_half = 1;
-   int i, j;
+   int i, j, p;
 
/*
 * We only consider PLL3, since the TCON is very likely to be
@@ -79,32 +79,37 @@ static int sun4i_tmds_determine_rate(struct clk_hw *hw,
 * clock, so we should not need to do anything.
 */
 
-   parent = clk_hw_get_parent_by_index(hw, 0);
-   if (!parent)
-   return -EINVAL;
-
-   for (i = 1; i < 3; i++) {
-   for (j = 1; j < 16; j++) {
-   unsigned long ideal = rate * i * j;
-   unsigned long rounded;
-
-   rounded = clk_hw_round_rate(parent, ideal);
-
-   if (rounded == ideal) {
-   best_parent = rounded;
-   best_half = i;
-   best_div = j;
-   goto out;
-   }
-
-   if (abs(rate - rounded / i) <
-   abs(rate - best_parent / best_div)) {
-   best_parent = rounded;
-   best_div = i;
+   for (p = 0; p < clk_hw_get_num_parents(hw); p++) {
+   parent = clk_hw_get_parent_by_index(hw, p);
+   if (!parent)
+   continue;
+
+   for (i = 1; i < 3; i++) {
+   for (j = 1; j < 16; j++) {
+   unsigned long ideal = rate * i * j;
+   unsigned long rounded;
+
+   rounded = clk_hw_round_rate(parent, ideal);
+
+   if (rounded == ideal) {
+   best_parent = rounded;
+   best_half = i;
+   best_div = j;
+   goto out;
+   }
+
+   if (abs(rate - rounded / i) <
+   abs(rate - best_parent / best_div)) {
+   best_parent = rounded;
+   best_div = i;
+   }
}
}
}
 
+   if (!parent)
+   return -EINVAL;
+
 out:
req->rate = best_parent / best_half / best_div;
req->best_parent_rate = best_parent;
-- 
2.11.0

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[linux-sunxi] [PATCH 04/19] drm/sun4i: hdmi: Disable clks in bind function error path and unbind function

[Chen-Yu Tsai]

The HDMI driver enables the bus and mod clocks in the bind function, but
does not disable them if it then bails our due to any errors. Neither
does it disable the clocks in the unbind function.

Fix this by adding a proper error path to the bind function, and
clk_disable_unprepare calls to the unbind function.

Also rename the err_cleanup_connector label to err_cleanup_encoder,
since it is the encoder that gets cleaned up.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c | 25 +
 1 file changed, 17 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c 
b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
index d3398f6250ef..457614073501 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
@@ -350,26 +350,29 @@ static int sun4i_hdmi_bind(struct device *dev, struct 
device *master,
hdmi->mod_clk = devm_clk_get(dev, "mod");
if (IS_ERR(hdmi->mod_clk)) {
dev_err(dev, "Couldn't get the HDMI mod clock\n");
-   return PTR_ERR(hdmi->mod_clk);
+   ret = PTR_ERR(hdmi->mod_clk);
+   goto err_disable_bus_clk;
}
clk_prepare_enable(hdmi->mod_clk);
 
hdmi->pll0_clk = devm_clk_get(dev, "pll-0");
if (IS_ERR(hdmi->pll0_clk)) {
dev_err(dev, "Couldn't get the HDMI PLL 0 clock\n");
-   return PTR_ERR(hdmi->pll0_clk);
+   ret = PTR_ERR(hdmi->pll0_clk);
+   goto err_disable_mod_clk;
}
 
hdmi->pll1_clk = devm_clk_get(dev, "pll-1");
if (IS_ERR(hdmi->pll1_clk)) {
dev_err(dev, "Couldn't get the HDMI PLL 1 clock\n");
-   return PTR_ERR(hdmi->pll1_clk);
+   ret = PTR_ERR(hdmi->pll1_clk);
+   goto err_disable_mod_clk;
}
 
ret = sun4i_tmds_create(hdmi);
if (ret) {
dev_err(dev, "Couldn't create the TMDS clock\n");
-   return ret;
+   goto err_disable_mod_clk;
}
 
writel(SUN4I_HDMI_CTRL_ENABLE, hdmi->base + SUN4I_HDMI_CTRL_REG);
@@ -410,7 +413,7 @@ static int sun4i_hdmi_bind(struct device *dev, struct 
device *master,
ret = sun4i_ddc_create(hdmi, hdmi->tmds_clk);
if (ret) {
dev_err(dev, "Couldn't create the DDC clock\n");
-   return ret;
+   goto err_disable_mod_clk;
}
 
drm_encoder_helper_add(>encoder,
@@ -428,7 +431,7 @@ static int sun4i_hdmi_bind(struct device *dev, struct 
device *master,
hdmi->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm,
  dev->of_node);
if (!hdmi->encoder.possible_crtcs)
-   return -EPROBE_DEFER;
+   goto err_disable_mod_clk;
 
drm_connector_helper_add(>connector,
 _hdmi_connector_helper_funcs);
@@ -438,7 +441,7 @@ static int sun4i_hdmi_bind(struct device *dev, struct 
device *master,
if (ret) {
dev_err(dev,
"Couldn't initialise the HDMI connector\n");
-   goto err_cleanup_connector;
+   goto err_cleanup_encoder;
}
 
/* There is no HPD interrupt, so we need to poll the controller */
@@ -449,8 +452,12 @@ static int sun4i_hdmi_bind(struct device *dev, struct 
device *master,
 
return 0;
 
-err_cleanup_connector:
+err_cleanup_encoder:
drm_encoder_cleanup(>encoder);
+err_disable_mod_clk:
+   clk_disable_unprepare(hdmi->mod_clk);
+err_disable_bus_clk:
+   clk_disable_unprepare(hdmi->bus_clk);
return ret;
 }
 
@@ -461,6 +468,8 @@ static void sun4i_hdmi_unbind(struct device *dev, struct 
device *master,
 
drm_connector_cleanup(>connector);
drm_encoder_cleanup(>encoder);
+   clk_disable_unprepare(hdmi->mod_clk);
+   clk_disable_unprepare(hdmi->bus_clk);
 }
 
 static const struct component_ops sun4i_hdmi_ops = {
-- 
2.11.0

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[linux-sunxi] [PATCH 09/19] drm/sun4i: hdmi: Support different variants of the DDC clock

[Chen-Yu Tsai]

On the A31, the HDMI DDC block is different from the one in the
other SoCs. As far as the DDC clock goes, it has no pre-divider,
as it is clocked from a slower parent clock, not the TMDS clock.
The divider offset from the register value is different. And the
clock control register is at a different offset.

This patch adds support for different variants of the DDC clock.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c | 42 --
 1 file changed, 34 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c 
b/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
index 4692e8c345ed..e1071838f487 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
@@ -15,9 +15,16 @@
 #include "sun4i_tcon.h"
 #include "sun4i_hdmi.h"
 
+struct sun4i_ddc_variant {
+   u32 reg_offset;
+   u8  pre_divider;
+   u8  m_offset;
+};
+
 struct sun4i_ddc {
struct clk_hw   hw;
struct sun4i_hdmi   *hdmi;
+   const struct sun4i_ddc_variant  *variant;
 };
 
 static inline struct sun4i_ddc *hw_to_ddc(struct clk_hw *hw)
@@ -27,6 +34,7 @@ static inline struct sun4i_ddc *hw_to_ddc(struct clk_hw *hw)
 
 static unsigned long sun4i_ddc_calc_divider(unsigned long rate,
unsigned long parent_rate,
+   const struct sun4i_ddc_variant 
*variant,
u8 *m, u8 *n)
 {
unsigned long best_rate = 0;
@@ -36,7 +44,8 @@ static unsigned long sun4i_ddc_calc_divider(unsigned long 
rate,
for (_n = 0; _n < 8; _n++) {
unsigned long tmp_rate;
 
-   tmp_rate = (((parent_rate / 2) / 10) >> _n) / (_m + 1);
+   tmp_rate = (((parent_rate / variant->pre_divider) /
+10) >> _n) / (_m + variant->m_offset);
 
if (tmp_rate > rate)
continue;
@@ -60,7 +69,9 @@ static unsigned long sun4i_ddc_calc_divider(unsigned long 
rate,
 static long sun4i_ddc_round_rate(struct clk_hw *hw, unsigned long rate,
 unsigned long *prate)
 {
-   return sun4i_ddc_calc_divider(rate, *prate, NULL, NULL);
+   struct sun4i_ddc *ddc = hw_to_ddc(hw);
+
+   return sun4i_ddc_calc_divider(rate, *prate, ddc->variant, NULL, NULL);
 }
 
 static unsigned long sun4i_ddc_recalc_rate(struct clk_hw *hw,
@@ -70,11 +81,12 @@ static unsigned long sun4i_ddc_recalc_rate(struct clk_hw 
*hw,
u32 reg;
u8 m, n;
 
-   reg = readl(ddc->hdmi->base + SUN4I_HDMI_DDC_CLK_REG);
-   m = (reg >> 3) & 0x7;
+   reg = readl(ddc->hdmi->base + ddc->variant->reg_offset);
+   m = (reg >> 3) & 0xf;
n = reg & 0x7;
 
-   return (((parent_rate / 2) / 10) >> n) / (m + 1);
+   return (((parent_rate / ddc->variant->pre_divider) / 10) >> n) /
+  (m + ddc->variant->m_offset);
 }
 
 static int sun4i_ddc_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -83,10 +95,11 @@ static int sun4i_ddc_set_rate(struct clk_hw *hw, unsigned 
long rate,
struct sun4i_ddc *ddc = hw_to_ddc(hw);
u8 div_m, div_n;
 
-   sun4i_ddc_calc_divider(rate, parent_rate, _m, _n);
+   sun4i_ddc_calc_divider(rate, parent_rate, ddc->variant,
+  _m, _n);
 
writel(SUN4I_HDMI_DDC_CLK_M(div_m) | SUN4I_HDMI_DDC_CLK_N(div_n),
-  ddc->hdmi->base + SUN4I_HDMI_DDC_CLK_REG);
+  ddc->hdmi->base + ddc->variant->reg_offset);
 
return 0;
 }
@@ -97,7 +110,8 @@ static const struct clk_ops sun4i_ddc_ops = {
.set_rate   = sun4i_ddc_set_rate,
 };
 
-int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *parent)
+static int _sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *parent,
+const struct sun4i_ddc_variant *variant)
 {
struct clk_init_data init;
struct sun4i_ddc *ddc;
@@ -117,6 +131,7 @@ int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk 
*parent)
init.num_parents = 1;
 
ddc->hdmi = hdmi;
+   ddc->variant = variant;
ddc->hw.init = 
 
hdmi->ddc_clk = devm_clk_register(hdmi->dev, >hw);
@@ -125,3 +140,14 @@ int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk 
*parent)
 
return 0;
 }
+
+static const struct sun4i_ddc_variant sun4i_variant = {
+   .reg_offset = SUN4I_HDMI_DDC_CLK_REG,
+   .pre_divider= 2,
+   .m_offset   = 1,
+};
+
+int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *parent)
+{
+   return _sun4i_ddc_create(hdmi, parent, _variant);
+}
-- 
2.11.0

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[linux-sunxi] [PATCH 17/19] ARM: sun6i: a31: Enable HDMI support on the A31 Hummingbird

[Chen-Yu Tsai]

The A31 Humminbird has an HDMI connector wired to the HDMI pins
on the SoC. Enable HDMI support for this board.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 21 +
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts 
b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
index 9ecb5f0b3f83..19e382a11297 100644
--- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
+++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
@@ -62,6 +62,17 @@
stdout-path = "serial0:115200n8";
};
 
+   hdmi-connector {
+   compatible = "hdmi-connector";
+   type = "a";
+
+   port {
+   hdmi_con_in: endpoint {
+   remote-endpoint = <_out_con>;
+   };
+   };
+   };
+
vga-connector {
compatible = "vga-connector";
 
@@ -162,6 +173,16 @@
};
 };
 
+ {
+   status = "okay";
+};
+
+_out {
+   hdmi_out_con: endpoint {
+   remote-endpoint = <_con_in>;
+   };
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
-- 
2.11.0

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[linux-sunxi] [PATCH 08/19] drm/sun4i: hdmi: Support the TMDS clock in the A31's HDMI controller

[Chen-Yu Tsai]

The A31's HDMI controller's TMDS clock is slightly different.
There is an offset of 1 between the divider value and the actual
value programmed into the registers.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/gpu/drm/sun4i/sun4i_hdmi.h  | 1 +
 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c | 7 +++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h 
b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
index 2f2f2ff1ea63..3a4987ab8da8 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi.h
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
@@ -153,5 +153,6 @@ struct sun4i_hdmi {
 
 int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *clk);
 int sun4i_tmds_create(struct sun4i_hdmi *hdmi);
+int sun6i_tmds_create(struct sun4i_hdmi *hdmi);
 
 #endif /* _SUN4I_HDMI_H_ */
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c 
b/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
index 3c304e1fbe3b..6f25c7bd887e 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
@@ -240,3 +240,10 @@ int sun4i_tmds_create(struct sun4i_hdmi *hdmi)
 {
return _sun4i_tmds_create(hdmi, 0);
 }
+
+/* sun6i variant has a different value offset for the divider */
+
+int sun6i_tmds_create(struct sun4i_hdmi *hdmi)
+{
+   return _sun4i_tmds_create(hdmi, 1);
+}
-- 
2.11.0

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[linux-sunxi] [PATCH 03/19] drm/sun4i: tcon: Add support for demuxing TCON output on A31

[Chen-Yu Tsai]

On systems with 2 TCONs such as the A31, it is possible to demux the
output of the TCONs to one encoder.

Add support for this for the A31.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/gpu/drm/sun4i/sun4i_tcon.c | 61 ++
 1 file changed, 61 insertions(+)

diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c 
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index d9791292553e..21bd7fab7aaa 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -14,9 +14,12 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
+#include 
+
 #include 
 #include 
 #include 
@@ -109,11 +112,69 @@ void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, 
bool enable)
 }
 EXPORT_SYMBOL(sun4i_tcon_enable_vblank);
 
+static struct sun4i_tcon *sun4i_get_first_tcon(struct drm_device *drm)
+{
+   struct sun4i_drv *drv = drm->dev_private;
+   struct sun4i_tcon *tcon;
+
+   list_for_each_entry(tcon, >tcon_list, list)
+   if (tcon->id == 0)
+   return tcon;
+
+   dev_warn(drm->dev,
+"TCON0 not found, display output muxing may not work\n");
+
+   return tcon;
+}
+
+static int _sun6i_tcon_set_mux(struct drm_encoder *encoder)
+{
+   struct sun4i_tcon *tcon = sun4i_get_first_tcon(encoder->dev);
+   int tcon_id = drm_crtc_to_sun4i_crtc(encoder->crtc)->tcon->id;
+   u32 shift;
+
+   DRM_DEBUG_DRIVER("Muxing encoder %s to CRTC %s (TCON %d)\n",
+encoder->name, encoder->crtc->name, tcon_id);
+
+   /* Only 2 TCONs */
+   if (tcon_id >= 2)
+   return -EINVAL;
+
+   switch (encoder->encoder_type) {
+   case DRM_MODE_ENCODER_TMDS:
+   /* HDMI */
+   shift = 8;
+   break;
+   case DRM_MODE_ENCODER_DSI:
+   /* No MIPI DSI on A31s */
+   if (of_device_is_compatible(tcon->dev->of_node,
+   "allwinner,sun6i-a31s-tcon"))
+   return -EINVAL;
+   shift = 0;
+   break;
+   default:
+   return -EINVAL;
+   }
+
+   regmap_update_bits(tcon->regs, SUN4I_TCON_MUX_CTRL_REG,
+  0x3 << shift, tcon_id << shift);
+
+   return 0;
+}
+
 void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
struct drm_encoder *encoder)
 {
+   /* Get the device node of the display engine */
+   struct device_node *node = encoder->dev->dev->of_node;
u32 val;
 
+   if (of_device_is_compatible(node, "allwinner,sun6i-a31-display-engine") 
||
+   of_device_is_compatible(node, 
"allwinner,sun6i-a31s-display-engine")) {
+   _sun6i_tcon_set_mux(encoder);
+   return;
+   }
+
if (!tcon->quirks->has_unknown_mux)
return;
 
-- 
2.11.0

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[linux-sunxi] [PATCH 02/19] drm/sun4i: add components in two passes with encoders added in second pass

[Chen-Yu Tsai]

The encoder drivers use drm_of_find_possible_crtcs to get upstream
crtcs from the device tree using of_graph. For the results to be
correct, encoders must be probed/bound after _all_ crtcs have been
created. The existing code uses a depth first recursive traversal
of the of_graph, which means the encoders downstream of the TCON
get add right after the first TCON. The second TCON or CRTC will
never be properly associated with encoders connected to it.

Other platforms, such as Rockchip, deal with this by probing all
crtcs first, then all subsequent components. This is easy to do
since the crtcs correspond to just one device node, and are the
first nodes in the pipeline.

However with Allwinner SoCs, the function of the CRTC is split between
the display backend (DE 1.0) or mixer (DE 2.0), which does scan-out
and compositing, and the TCON, which generating the display timing
signals. Further complicating the process, there may be a Dynamic Range
Controller between the backend and the TCON. Also, the backend is
preceded by the frontend, with a Display Enhancement Unit possibly
in between.

One solution would be, instead of a depth first traversal of the
component of_graph, we do a breadth first traversal, so that components
at the same depth are grouped together. This however requires us to
implement extra code for a queue structure that is only used here.

Instead, since we can identify TCON device nodes, and since the
component system can gracefully deal with duplicate entries, we can add
components in two passes, using the existing recursive depth code. The
first pass stops right after the TCON is added. The second pass will
re-add all components up to the TCON, but these will be skipped since
they will have already been bound with the entries from the first pass.
The encoders added in the second pass will be the last entries in the
list.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/gpu/drm/sun4i/sun4i_drv.c | 24 
 1 file changed, 20 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c 
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index ed75a779ae4b..bc13dcf06783 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -198,7 +198,8 @@ static int compare_of(struct device *dev, void *data)
 
 static int sun4i_drv_add_endpoints(struct device *dev,
   struct component_match **match,
-  struct device_node *node)
+  struct device_node *node,
+  bool add_encoders)
 {
struct device_node *port, *ep, *remote;
int count = 0;
@@ -227,13 +228,16 @@ static int sun4i_drv_add_endpoints(struct device *dev,
count++;
}
 
+   /* Skip downstream encoders during the first pass */
+   if (sun4i_drv_node_is_tcon(node) && !add_encoders)
+   return count;
+
/* Inputs are listed first, then outputs */
port = of_graph_get_port_by_id(node, 1);
if (!port) {
DRM_DEBUG_DRIVER("No output to bind\n");
return count;
}
-
for_each_available_child_of_node(port, ep) {
remote = of_graph_get_remote_port_parent(ep);
if (!remote) {
@@ -262,7 +266,8 @@ static int sun4i_drv_add_endpoints(struct device *dev,
}
 
/* Walk down our tree */
-   count += sun4i_drv_add_endpoints(dev, match, remote);
+   count += sun4i_drv_add_endpoints(dev, match, remote,
+add_encoders);
 
of_node_put(remote);
}
@@ -283,8 +288,19 @@ static int sun4i_drv_probe(struct platform_device *pdev)
if (!pipeline)
break;
 
+   sun4i_drv_add_endpoints(>dev, , pipeline, false);
+   of_node_put(pipeline);
+   }
+
+   for (i = 0;; i++) {
+   struct device_node *pipeline = of_parse_phandle(np,
+   
"allwinner,pipelines",
+   i);
+   if (!pipeline)
+   break;
+
count += sun4i_drv_add_endpoints(>dev, ,
-   pipeline);
+pipeline, true);
of_node_put(pipeline);
 
DRM_DEBUG_DRIVER("Queued %d outputs on pipeline %d\n",
-- 
2.11.0

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[linux-sunxi] [PATCH 19/19] ARM: sun6i: a31s: Enable HDMI display output on the MSI Primo81 tablet

[Chen-Yu Tsai]

The MSI Primo81 tablet has a micro HDMI connector at the bottom.
This is connected to the SoCs HDMI output.

Enable the display pipeline and the HDMI output.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun6i-a31s-primo81.dts | 25 +
 1 file changed, 25 insertions(+)

diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts 
b/arch/arm/boot/dts/sun6i-a31s-primo81.dts
index f3712753fa42..26154b2f87a3 100644
--- a/arch/arm/boot/dts/sun6i-a31s-primo81.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-primo81.dts
@@ -52,17 +52,42 @@
 / {
model = "MSI Primo81 tablet";
compatible = "msi,primo81", "allwinner,sun6i-a31s";
+
+   hdmi-connector {
+   compatible = "hdmi-connector";
+   type = "c";
+
+   port {
+   hdmi_con_in: endpoint {
+   remote-endpoint = <_out_con>;
+   };
+   };
+   };
 };
 
  {
cpu-supply = <_dcdc3>;
 };
 
+ {
+   status = "okay";
+};
+
  {
/* rtl8188etv wifi is connected here */
status = "okay";
 };
 
+ {
+   status = "okay";
+};
+
+_out {
+   hdmi_out_con: endpoint {
+   remote-endpoint = <_con_in>;
+   };
+};
+
  {
/* pull-ups and device VDDIO use AXP221 DLDO3 */
pinctrl-names = "default";
-- 
2.11.0

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[linux-sunxi] [PATCH 11/19] drm/sun4i: hdmi: Add A31 specific DDC register definitions

[Chen-Yu Tsai]

The DDC block for the HDMI controller is different on the A31.

This patch adds the register definitions.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/gpu/drm/sun4i/sun4i_hdmi.h | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h 
b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
index 3a4987ab8da8..08c514672fd3 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi.h
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
@@ -124,6 +124,32 @@
 
 #define SUN4I_HDMI_DDC_FIFO_SIZE   16
 
+/* A31 specific */
+#define SUN6I_HDMI_DDC_CTRL_REG0x500
+#define SUN6I_HDMI_DDC_CTRL_RESET  BIT(31)
+#define SUN6I_HDMI_DDC_CTRL_START_CMD  BIT(27)
+#define SUN6I_HDMI_DDC_CTRL_SDA_ENABLE BIT(6)
+#define SUN6I_HDMI_DDC_CTRL_SCL_ENABLE BIT(4)
+#define SUN6I_HDMI_DDC_CTRL_ENABLE BIT(0)
+
+#define SUN6I_HDMI_DDC_CMD_REG 0x508
+#define SUN6I_HDMI_DDC_CMD_EXPLICIT_EDDC_READ  6
+#define SUN6I_HDMI_DDC_CMD_BYTE_COUNT(count)   ((count) << 16)
+
+#define SUN6I_HDMI_DDC_ADDR_REG0x50c
+#define SUN6I_HDMI_DDC_ADDR_SEGMENT(seg)   (((seg) & 0xff) << 24)
+#define SUN6I_HDMI_DDC_ADDR_EDDC(addr) (((addr) & 0xff) << 16)
+#define SUN6I_HDMI_DDC_ADDR_OFFSET(off)(((off) & 0xff) << 8)
+#define SUN6I_HDMI_DDC_ADDR_SLAVE(addr)(((addr) & 0xff) << 1)
+
+#define SUN6I_HDMI_DDC_FIFO_CTRL_REG   0x518
+#define SUN6I_HDMI_DDC_FIFO_CTRL_CLEAR BIT(15)
+
+#define SUN6I_HDMI_DDC_CLK_REG 0x520
+/* DDC CLK bit fields are the same, but the formula is not */
+
+#define SUN6I_HDMI_DDC_FIFO_DATA_REG   0x580
+
 enum sun4i_hdmi_pkt_type {
SUN4I_HDMI_PKT_AVI = 2,
SUN4I_HDMI_PKT_END = 15,
-- 
2.11.0

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[linux-sunxi] [PATCH 01/19] drm/sun4i: call drm_vblank_init with correct number of crtcs

[Chen-Yu Tsai]

If we want to have vblank on both pipelines at the same time, we need
to call drm_vblank_init with num_crtcs = 2.

Instead, since the crtc init calls correctly set mode_config.num_crtc,
we can move the drm_vblank_init call to after the crtc init code is
called, which is the component bind part. Then we can just pass
mode_config.num_crtc in.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/gpu/drm/sun4i/sun4i_drv.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c 
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index f19100c91c2b..ed75a779ae4b 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -100,11 +100,6 @@ static int sun4i_drv_bind(struct device *dev)
goto free_drm;
}
 
-   /* drm_vblank_init calls kcalloc, which can fail */
-   ret = drm_vblank_init(drm, 1);
-   if (ret)
-   goto free_mem_region;
-
drm_mode_config_init(drm);
 
ret = component_bind_all(drm->dev, drm);
@@ -113,6 +108,11 @@ static int sun4i_drv_bind(struct device *dev)
goto cleanup_mode_config;
}
 
+   /* drm_vblank_init calls kcalloc, which can fail */
+   ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
+   if (ret)
+   goto free_mem_region;
+
drm->irq_enabled = true;
 
/* Remove early framebuffers (ie. simplefb) */
-- 
2.11.0

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[linux-sunxi] [PATCH 00/19] drm/sun4i: hdmi: Support HDMI controller on A31

[Chen-Yu Tsai]

Hi everyone,

This series adds support for the HDMI controller found on Allwinner
A31/A31s SoCs. It builds upon Maxime's work that added support for
the HDMI controller on the Allwinner A10s SoC.

The HDMI controllers in the older generation Allwinner SoCs is very
similar. The A10/A10s/A20 all have the same hardware block, with the
A10 having slightly different initial configuration values. The A31's
variant splits out the DDC parent clock, has different formulas for
the DDC and TMDS clocks, and a different register layout for the DDC
block. Also, it does not expose the CEC pins outside of the SoC, which
is unfortunate.

The first 2 patches allow the sun4i-drm driver to work correctly with
2 display pipelines.

Patch 3 adds support for the TCON demuxing feature on the A31. This is
needed if the user wants to output through HDMI from the second display
pipeline.

Patch 4 adds proper error path cleanup to the HDMI driver.

Patch 5 allows the HDMI TMDS clock to use the second PLL as its parent,
in case the first PLL is driving an incompatible dot clock.

Patch 6 adds the A31 HDMI controller variant to the device tree binding.

Patch 7 adds support for different variants of the TMDS clock, with the
different being an offset value for the divider.

Patch 8 adds support for the A31's TMDS clock variant.

Patch 9 adds support for different variants of the DDC clock, with the
differences being a different register offset, different divider offset,
different pre-divider, and different clock parent.

Patch 10 renames the HDMI block's DDC clock, so that it doesn't conflict
with the A31's SoC level HDMI DDC clock.

Patch 11 adds defines for the A31 specific DDC register offsets.

Patch 12 adds support for the A31's DDC clock variant.

Patch 13 adds support for different variants of the HDMI controller
hardware, with the differences mentioned in the beginning of this
letter.

Patch 14 adds support for the A31's HDMI controller variant.

Patch 15 exports the 2x outputs of the two video PLLs. These feed the
TMDS clock directly.

Patch 16 adds a device node for the HDMI controller on the A31.

Patches 17~19 enable HDMI video output on three boards that I have.


Patches 13 & 14 are somewhat complicated. If the DDC block were factored
out into a proper I2C controller, it might be cleaner. Other than that
this series should be quite straightforward.

I also had simultaneous output on both display pipelines on the SinA31s,
one with an LCD panel and the other using HDMI. After boot, both screens
showed a proper console. The HDMI screen had higher resolution, so the
console was limited to the upper left corner.


Regards
ChenYu

Chen-Yu Tsai (19):
  drm/sun4i: call drm_vblank_init with correct number of crtcs
  drm/sun4i: add components in two passes with encoders added in second
pass
  drm/sun4i: tcon: Add support for demuxing TCON output on A31
  drm/sun4i: hdmi: Disable clks in bind function error path and unbind
function
  drm/sun4i: hdmi: Allow using second PLL as TMDS clk parent
  dt-bindings: display: sun4i: Add binding for A31 HDMI controller
  drm/sun4i: hdmi: Support different variants of the TMDS clock
  drm/sun4i: hdmi: Support the TMDS clock in the A31's HDMI controller
  drm/sun4i: hdmi: Support different variants of the DDC clock
  drm/sun4i: hdmi: Rename internal DDC clock to avoid name collision
  drm/sun4i: hdmi: Add A31 specific DDC register definitions
  drm/sun4i: hdmi: Support the DDC clock in the A31's HDMI controller
  drm/sun4i: hdmi: Add support for controller hardware variants
  drm/sun4i: hdmi: Add support for A31's HDMI controller
  clk: sunxi-ng: sun6i: Export video PLLs
  ARM: sun6i: a31: Add device node for HDMI controller
  ARM: sun6i: a31: Enable HDMI support on the A31 Hummingbird
  ARM: sun6i: a31s: Enable HDMI display output on the Sinlinx SinA31s
  ARM: sun6i: a31s: Enable HDMI display output on the MSI Primo81 tablet

 .../bindings/display/sunxi/sun4i-drm.txt   |   3 +
 arch/arm/boot/dts/sun6i-a31-hummingbird.dts|  21 ++
 arch/arm/boot/dts/sun6i-a31.dtsi   |  55 
 arch/arm/boot/dts/sun6i-a31s-primo81.dts   |  25 ++
 arch/arm/boot/dts/sun6i-a31s-sina31s.dts   |  25 ++
 drivers/clk/sunxi-ng/ccu-sun6i-a31.c   |   2 +-
 drivers/clk/sunxi-ng/ccu-sun6i-a31.h   |   8 +-
 drivers/gpu/drm/sun4i/sun4i_drv.c  |  34 ++-
 drivers/gpu/drm/sun4i/sun4i_hdmi.h |  39 +++
 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c |  55 +++-
 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c | 280 ++---
 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c|  82 +++---
 drivers/gpu/drm/sun4i/sun4i_tcon.c |  61 +
 include/dt-bindings/clock/sun6i-a31-ccu.h  |   4 +
 14 files changed, 613 insertions(+), 81 deletions(-)

-- 
2.11.0

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[linux-sunxi] [PATCH 10/19] drm/sun4i: hdmi: Rename internal DDC clock to avoid name collision

[Chen-Yu Tsai]

The DDC parent clock on the A31 SoC is also conveniently named
"hdmi-ddc", which results in a name collision when the hdmi driver
registers its internal DDC divider clock.

Rename the internal clock to "hdmi-ddc-divider".

Signed-off-by: Chen-Yu Tsai 
---
 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c 
b/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
index e1071838f487..9a6b6243e977 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
@@ -125,7 +125,7 @@ static int _sun4i_ddc_create(struct sun4i_hdmi *hdmi, 
struct clk *parent,
if (!ddc)
return -ENOMEM;
 
-   init.name = "hdmi-ddc";
+   init.name = "hdmi-ddc-divider";
init.ops = _ddc_ops;
init.parent_names = _name;
init.num_parents = 1;
-- 
2.11.0

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[linux-sunxi] [PATCH 06/19] dt-bindings: display: sun4i: Add binding for A31 HDMI controller

[Chen-Yu Tsai]

The HDMI controller in the A31 SoC is slightly different from the
earlier version. In addition to the TMDS clock and DDC controls,
this version now takes a second DDC clock input.

Add a compatible string for it, and add the DDC clock input to the
list of clocks required.

Signed-off-by: Chen-Yu Tsai 
---
 Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt 
b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index b83e6018041d..d23e7cad19d0 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -23,14 +23,17 @@ CEC. It is one end of the pipeline.
 Required properties:
   - compatible: value must be one of:
 * allwinner,sun5i-a10s-hdmi
+* allwinner,sun6i-a31-hdmi
   - reg: base address and size of memory-mapped region
   - interrupts: interrupt associated to this IP
   - clocks: phandles to the clocks feeding the HDMI encoder
 * ahb: the HDMI interface clock
 * mod: the HDMI module clock
+* ddc: the HDMI ddc clock (A31 only)
 * pll-0: the first video PLL
 * pll-1: the second video PLL
   - clock-names: the clock names mentioned above
+  - resets: phandle to the reset control for the HDMI encoder (A31 only)
   - dmas: phandles to the DMA channels used by the HDMI encoder
 * ddc-tx: The channel for DDC transmission
 * ddc-rx: The channel for DDC reception
-- 
2.11.0

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[linux-sunxi] [PATCH 07/19] drm/sun4i: hdmi: Support different variants of the TMDS clock

[Chen-Yu Tsai]

On the A31, the HDMI TMDS clock has a different value offset for the
divider.

This patch adds support for custom offsets to the TMDS clock.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c | 26 +++---
 1 file changed, 19 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c 
b/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
index 5692e41833ae..3c304e1fbe3b 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
@@ -18,6 +18,8 @@
 struct sun4i_tmds {
struct clk_hw   hw;
struct sun4i_hdmi   *hdmi;
+
+   u8  div_offset;
 };
 
 static inline struct sun4i_tmds *hw_to_tmds(struct clk_hw *hw)
@@ -28,6 +30,7 @@ static inline struct sun4i_tmds *hw_to_tmds(struct clk_hw *hw)
 
 static unsigned long sun4i_tmds_calc_divider(unsigned long rate,
 unsigned long parent_rate,
+u8 div_offset,
 u8 *div,
 bool *half)
 {
@@ -35,7 +38,7 @@ static unsigned long sun4i_tmds_calc_divider(unsigned long 
rate,
u8 best_m = 0, m;
bool is_double;
 
-   for (m = 1; m < 16; m++) {
+   for (m = div_offset ?: 1; m < (16 + div_offset); m++) {
u8 d;
 
for (d = 1; d < 3; d++) {
@@ -67,7 +70,8 @@ static unsigned long sun4i_tmds_calc_divider(unsigned long 
rate,
 static int sun4i_tmds_determine_rate(struct clk_hw *hw,
 struct clk_rate_request *req)
 {
-   struct clk_hw *parent;
+   struct sun4i_tmds *tmds = hw_to_tmds(hw);
+   struct clk_hw *parent = NULL;
unsigned long best_parent = 0;
unsigned long rate = req->rate;
int best_div = 1, best_half = 1;
@@ -85,7 +89,8 @@ static int sun4i_tmds_determine_rate(struct clk_hw *hw,
continue;
 
for (i = 1; i < 3; i++) {
-   for (j = 1; j < 16; j++) {
+   for (j = tmds->div_offset ?: 1;
+j < (16 + tmds->div_offset); j++) {
unsigned long ideal = rate * i * j;
unsigned long rounded;
 
@@ -129,7 +134,7 @@ static unsigned long sun4i_tmds_recalc_rate(struct clk_hw 
*hw,
parent_rate /= 2;
 
reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
-   reg = (reg >> 4) & 0xf;
+   reg = ((reg >> 4) & 0xf) + tmds->div_offset;
if (!reg)
reg = 1;
 
@@ -144,7 +149,8 @@ static int sun4i_tmds_set_rate(struct clk_hw *hw, unsigned 
long rate,
u32 reg;
u8 div;
 
-   sun4i_tmds_calc_divider(rate, parent_rate, , );
+   sun4i_tmds_calc_divider(rate, parent_rate, tmds->div_offset,
+   , );
 
reg = readl(tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
reg &= ~SUN4I_HDMI_PAD_CTRL1_HALVE_CLK;
@@ -154,7 +160,7 @@ static int sun4i_tmds_set_rate(struct clk_hw *hw, unsigned 
long rate,
 
reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
reg &= ~SUN4I_HDMI_PLL_CTRL_DIV_MASK;
-   writel(reg | SUN4I_HDMI_PLL_CTRL_DIV(div),
+   writel(reg | SUN4I_HDMI_PLL_CTRL_DIV(div - tmds->div_offset),
   tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
 
return 0;
@@ -195,7 +201,7 @@ static const struct clk_ops sun4i_tmds_ops = {
.set_parent = sun4i_tmds_set_parent,
 };
 
-int sun4i_tmds_create(struct sun4i_hdmi *hdmi)
+static int _sun4i_tmds_create(struct sun4i_hdmi *hdmi, u8 div_offset)
 {
struct clk_init_data init;
struct sun4i_tmds *tmds;
@@ -221,6 +227,7 @@ int sun4i_tmds_create(struct sun4i_hdmi *hdmi)
 
tmds->hdmi = hdmi;
tmds->hw.init = 
+   tmds->div_offset = div_offset;
 
hdmi->tmds_clk = devm_clk_register(hdmi->dev, >hw);
if (IS_ERR(hdmi->tmds_clk))
@@ -228,3 +235,8 @@ int sun4i_tmds_create(struct sun4i_hdmi *hdmi)
 
return 0;
 }
+
+int sun4i_tmds_create(struct sun4i_hdmi *hdmi)
+{
+   return _sun4i_tmds_create(hdmi, 0);
+}
-- 
2.11.0

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[linux-sunxi] Re: [PATCH v6 00/21] net-next: stmmac: add dwmac-sun8i ethernet driver

[Maxime Ripard]

On Fri, Jun 02, 2017 at 08:37:52AM +0200, Maxime Ripard wrote:
> On Thu, Jun 01, 2017 at 02:58:19PM -0400, David Miller wrote:
> > From: Corentin Labbe 
> > Date: Wed, 31 May 2017 09:18:31 +0200
> > 
> > > This patch series add the driver for dwmac-sun8i which handle the 
> > > Ethernet MAC
> > > present on Allwinner H3/H5/A83T/A64 SoCs.
> > 
> > Series applied, but wow that's a lot of DT file changes :-(
> 
> The DT patches should not go through your tree, but arm-soc, so I
> guess this is not an issue for you?

Ok, so I saw that you actually merged them. Can you revert or drop
that merge for the DT part?

This will generate a lot of conflicts with our tree, and I'm not sure
this would be efficient to make you take all the entirely unrelated to
next patches.

Maxime

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[linux-sunxi] Re: [PATCH v6 00/21] net-next: stmmac: add dwmac-sun8i ethernet driver

[Maxime Ripard]

On Thu, Jun 01, 2017 at 02:58:19PM -0400, David Miller wrote:
> From: Corentin Labbe 
> Date: Wed, 31 May 2017 09:18:31 +0200
> 
> > This patch series add the driver for dwmac-sun8i which handle the Ethernet 
> > MAC
> > present on Allwinner H3/H5/A83T/A64 SoCs.
> 
> Series applied, but wow that's a lot of DT file changes :-(

The DT patches should not go through your tree, but arm-soc, so I
guess this is not an issue for you?

Maximee

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