Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock

2017-08-03 Thread Chen-Yu Tsai 
On Fri, Aug 4, 2017 at 12:16 PM, Icenowy Zheng  wrote:
>
>
> 于 2017年8月4日 GMT+08:00 下午12:15:27, Chen-Yu Tsai  写到:
>>Hi,
>>
>>On Tue, Aug 1, 2017 at 9:13 PM, Icenowy Zheng  wrote:
>>> From: Jernej Skrabec 
>>>
>>> When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be
>>set.
>>>
>>> Add CLK_SET_RATE_PARENT flag for H3 HDMI clock.
>>>
>>> Signed-off-by: Jernej Skrabec 
>>> Signed-off-by: Icenowy Zheng 
>>> ---
>>>  drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>>b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>>> index b1127e8629d9..2ebb3d865b01 100644
>>> --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>>> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>>> @@ -474,7 +474,7 @@ static SUNXI_CCU_GATE(avs_clk,
>>"avs",  "osc24M",
>>>
>>>  static const char * const hdmi_parents[] = { "pll-video" };
>>>  static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
>>> -0x150, 0, 4, 24, 2, BIT(31), 0);
>>> +0x150, 0, 4, 24, 2, BIT(31),
>>CLK_SET_RATE_PARENT);
>>
>>Line is longer than 80 characters.
>>
>>This looks independent enough so I've merged this for 4.14 with the
>>offending line wrapped and the following tag added:
>>
>>Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
>
> Please don't merge this now until Jernej send it.

(Dropped Rob, devicetree and dri mailing lists)

Hi Jernej,

Is it OK if we take this patch for the next release? Or rather,
if there anything blocking this patch?

Thanks
ChenYu

>
>>
>>ChenYu
>>
>>>
>>>  static SUNXI_CCU_GATE(hdmi_ddc_clk,"hdmi-ddc", "osc24M",
>>>   0x154, BIT(31), 0);
>>> --
>>> 2.13.0
>>>
>>> --
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Re: [linux-sunxi] [PATCH] drm/panel: simple: Fix width and height for Olimex LCD-OLinuXino-4.3TS

2017-08-03 Thread Chen-Yu Tsai 
On Thu, Jul 20, 2017 at 6:29 PM, Jonathan Liu  wrote:
> The physical size of the panel is 105.5 (W) x 67.2 (H) x 4.05 (D) mm
> but the active display area is 95.04 (W) x 53.856 (H) mm.
>
> The width and height should be set to the active display area.
>
> Signed-off-by: Jonathan Liu 

You probably want:

Fixes: cf5c9e6dc70d ("drm/panel: simple: Add timings for the Olimex
  LCD-OLinuXino-4.3TS")

Otherwise,

Reviewed-by: Chen-Yu Tsai 

against the panel datasheet linked from Olimex's product page.
This should probably go in through drm-misc?

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Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock

2017-08-03 Thread Icenowy Zheng 


于 2017年8月4日 GMT+08:00 下午12:15:27, Chen-Yu Tsai  写到:
>Hi,
>
>On Tue, Aug 1, 2017 at 9:13 PM, Icenowy Zheng  wrote:
>> From: Jernej Skrabec 
>>
>> When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be
>set.
>>
>> Add CLK_SET_RATE_PARENT flag for H3 HDMI clock.
>>
>> Signed-off-by: Jernej Skrabec 
>> Signed-off-by: Icenowy Zheng 
>> ---
>>  drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>> index b1127e8629d9..2ebb3d865b01 100644
>> --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>> @@ -474,7 +474,7 @@ static SUNXI_CCU_GATE(avs_clk, 
>"avs",  "osc24M",
>>
>>  static const char * const hdmi_parents[] = { "pll-video" };
>>  static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
>> -0x150, 0, 4, 24, 2, BIT(31), 0);
>> +0x150, 0, 4, 24, 2, BIT(31),
>CLK_SET_RATE_PARENT);
>
>Line is longer than 80 characters.
>
>This looks independent enough so I've merged this for 4.14 with the
>offending line wrapped and the following tag added:
>
>Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")

Please don't merge this now until Jernej send it.

>
>ChenYu
>
>>
>>  static SUNXI_CCU_GATE(hdmi_ddc_clk,"hdmi-ddc", "osc24M",
>>   0x154, BIT(31), 0);
>> --
>> 2.13.0
>>
>> --
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Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock

2017-08-03 Thread Chen-Yu Tsai 
Hi,

On Tue, Aug 1, 2017 at 9:13 PM, Icenowy Zheng  wrote:
> From: Jernej Skrabec 
>
> When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be set.
>
> Add CLK_SET_RATE_PARENT flag for H3 HDMI clock.
>
> Signed-off-by: Jernej Skrabec 
> Signed-off-by: Icenowy Zheng 
> ---
>  drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c 
> b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> index b1127e8629d9..2ebb3d865b01 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> @@ -474,7 +474,7 @@ static SUNXI_CCU_GATE(avs_clk,  "avs",
>   "osc24M",
>
>  static const char * const hdmi_parents[] = { "pll-video" };
>  static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
> -0x150, 0, 4, 24, 2, BIT(31), 0);
> +0x150, 0, 4, 24, 2, BIT(31), 
> CLK_SET_RATE_PARENT);

Line is longer than 80 characters.

This looks independent enough so I've merged this for 4.14 with the
offending line wrapped and the following tag added:

Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")

ChenYu

>
>  static SUNXI_CCU_GATE(hdmi_ddc_clk,"hdmi-ddc", "osc24M",
>   0x154, BIT(31), 0);
> --
> 2.13.0
>
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Re: [linux-sunxi] [PATCH 06/10] clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3

2017-08-03 Thread Chen-Yu Tsai 
On Mon, Jul 24, 2017 at 11:10 AM, Chen-Yu Tsai  wrote:
> On Sun, Jul 23, 2017 at 6:27 PM, Icenowy Zheng  wrote:
>> The CPUX clock, which is the main clock of the ARM core on Allwinner H3,
>> can be adjusted by changing the frequency of the PLL_CPUX clock.
>>
>> Allowing setting parent clock for the CPUX clock, thus the PLL_CPUX
>> clock can be adjusted when adjusting the CPUX clock.
>>
>> Signed-off-by: Icenowy Zheng 
>
> Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
> Reviewed-by: Chen-Yu Tsai 

Applied for 4.14 with the Fixes tag and Stephen's ack.

ChenYu

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Re: [linux-sunxi] [PATCH 05/10] clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change

2017-08-03 Thread Chen-Yu Tsai 
On Wed, Jul 26, 2017 at 3:14 PM, Chen-Yu Tsai  wrote:
> On Sun, Jul 23, 2017 at 6:27 PM, Icenowy Zheng  wrote:
>> From: Chen-Yu Tsai 
>>
>> This patch utilizes the new PLL clk notifier to gate then ungate the
>> PLL CPU clock after rate changes. This should prevent any system hangs
>> resulting from cpufreq changes to the clk.
>>
>> Reported-by: Ondrej Jirman 
>> Signed-off-by: Chen-Yu Tsai 
>> Tested-by: Icenowy Zheng 
>
> This is missing
>
> Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")

Applied for 4.14 with the Fixes tag and Stephen's ack.

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Re: [linux-sunxi] [PATCH 03/13] drm: sun4i: add support for H3's TCON

2017-08-03 Thread Chen-Yu Tsai 
On Tue, Aug 1, 2017 at 9:12 PM, Icenowy Zheng  wrote:
> From: Icenowy Zheng 
>
> Allwinner H3 has two special TCONs without channel 0.
>
> Add support for this kind of TCON.
>
> Signed-off-by: Icenowy Zheng 

Ideally you would split this into two patches. The first one would add
the quirks support for TCONs without channel 0. I can also use this for
the A80. The second would add the H3 TCON.

ChenYu

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Re: [linux-sunxi] [PATCH] pinctrl: sunxi: fix V3s pinctrl driver IRQ bank base

2017-08-03 Thread icenowy 

在 2017-08-04 10:23，Chen-Yu Tsai 写道：

On Tue, Aug 1, 2017 at 10:54 PM, Icenowy Zheng  wrote:

The V3s pin controller doesn't have the bank 0 (starts at address
0x200), which is like A33. However, this is not workarounded when


   was not worked around

"Work around" is a verb phrase. "Workaround" is a noun.


developing the driver, which makes IRQ not working.


   broke the IRQs.



Fix the IRQ bank base.

Fixes: 56d9e4a76039 ("pinctrl: sunxi: add driver for V3s SoC")
Cc: sta...@vger.kernel.org
Signed-off-by: Icenowy Zheng 


Confirmed this is the same thing we saw on A33.
The fix is the same.

Apart from the typo / grammar errors above,

Reviewed-by: Chen-Yu Tsai 


Should I send a v2 now to fix the language errors?



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Re: [linux-sunxi] USB0 host mode not working on A20 mainline kernel

2017-08-03 Thread Chen-Yu Tsai 
On Sun, Jul 30, 2017 at 2:35 PM, sufi al hussaini hassani kamili
raheemi  wrote:
> Hi All,
>
> I am not able to get USB0 to work in host mode.
> This is an Olimex A20 Olinuxino micro and I have set `dr_mode = "host";` in
> the dts. I have compiled the kernel with USB support and the other USBs are
> working fine.
>
> I found this post
> (https://groups.google.com/forum/#!msg/linux-sunxi/uulK5lf7XrU/QUMtNbVpAQAJ)
> which addresses a similar problem for the lime2 board. I tried making these
> changes but it isn't working for me.
> My kernel version is 4.4.71 and it should have USB support as per the sunxi
> mainlining effort page.
>
> FWIW, I see the following in my boot logs:
> [1.591201] vcc5v0: disabling
> [1.591218] ahci-5v: disabling
> [1.591225] usb0-vbus: disabling
>
>
> I'd appreciate if someone can help me here.

What mode are you compiling the MUSB driver as? If you selected OTG then
you also need a gadget driver. I'm not sure if the bug that needs the
gadget driver to probe before the MUSB driver was fixed in 4.4 or not.

Safe bet is to just compile the MUSB driver in host-only mode. Note this
is separate from what you specified in the device tree.

ChenYu

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Re: [linux-sunxi] [PATCH] pinctrl: sunxi: fix V3s pinctrl driver IRQ bank base

2017-08-03 Thread Chen-Yu Tsai 
On Tue, Aug 1, 2017 at 10:54 PM, Icenowy Zheng  wrote:
> The V3s pin controller doesn't have the bank 0 (starts at address
> 0x200), which is like A33. However, this is not workarounded when

   was not worked around

"Work around" is a verb phrase. "Workaround" is a noun.

> developing the driver, which makes IRQ not working.

   broke the IRQs.

>
> Fix the IRQ bank base.
>
> Fixes: 56d9e4a76039 ("pinctrl: sunxi: add driver for V3s SoC")
> Cc: sta...@vger.kernel.org
> Signed-off-by: Icenowy Zheng 

Confirmed this is the same thing we saw on A33.
The fix is the same.

Apart from the typo / grammar errors above,

Reviewed-by: Chen-Yu Tsai 

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[linux-sunxi] Re: [PATCH v3 00/10] ARM: sun8i: a83t: Add support for MMC controllers

2017-08-03 Thread Chen-Yu Tsai 
On Thu, Aug 3, 2017 at 8:02 PM, Ulf Hansson  wrote:
> On 3 August 2017 at 13:25, Chen-Yu Tsai  wrote:
>> On Thu, Aug 3, 2017 at 7:19 PM, Ulf Hansson  wrote:
>>> On 26 July 2017 at 21:45, Maxime Ripard
>>>  wrote:
 On Wed, Jul 26, 2017 at 10:09:41PM +0800, Chen-Yu Tsai wrote:
> On Mon, Jul 24, 2017 at 9:58 PM, Chen-Yu Tsai  wrote:
> > Hi everyone,
> >
> > This is v3 of my MMC controller support series.
> >
>
> [...]
>
> > Chen-Yu Tsai (10):
> >   clk: sunxi-ng: Add interface to query or configure MMC timing modes.
> >   clk: sunxi-ng: Add MP_MMC clocks that support MMC timing modes
> > switching
> >   clk: sunxi-ng: a83t: Support new timing mode for mmc2 clock
> >   mmc: sunxi: Support controllers that can use both old and new timings
> >   mmc: sunxi: Support MMC DDR52 transfer mode with new timing mode
> >   mmc: sunxi: Add support for A83T eMMC (MMC2)
>
> So this series seems to be ready for inclusion, unless Ulf has further
> concerns about the clk usage.
>
> The first mmc patch have build time dependencies on the first clk patch.
> Shall we put the clk patch on a separate immutable branch for both trees
> to pull? Or we could just merge everything through the mmc tree? I don't
> think we'll touch this part of the sunxi-ng clk driver for the remainder
> of this cycle.

 I guess the easiest would be for it to go through Ulf tree, unless he
 says otherwise of course :)
>>>
>>> Okay, I have picked up the series and applied it for my next branch.
>>
>> I guess I wasn't very clear. When I meant "everything" I meant the mmc
>> and clk patches. We will take the dts patches through the sunxi tree.
>>
>> Can you drop the four dts patches from your tree? That would be the
>> last four patches on mmc/next at the moment.
>
> Done!

Thanks! I applied the remaining dts patches to the sunxi tree.

ChenYu

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[linux-sunxi] Re: [PATCH v2 2/3] dt-bindings: media: Add Allwinner V3s Camera Sensor Interface (CSI)

2017-08-03 Thread Rob Herring 
On Thu, Jul 27, 2017 at 01:01:36PM +0800, Yong Deng wrote:
> Add binding documentation for Allwinner V3s CSI.
> 
> Signed-off-by: Yong Deng 
> ---
>  .../devicetree/bindings/media/sun6i-csi.txt| 49 
> ++
>  1 file changed, 49 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/media/sun6i-csi.txt
> 
> diff --git a/Documentation/devicetree/bindings/media/sun6i-csi.txt 
> b/Documentation/devicetree/bindings/media/sun6i-csi.txt
> new file mode 100644
> index 000..f8d83f6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/sun6i-csi.txt
> @@ -0,0 +1,49 @@
> +Allwinner V3s Camera Sensor Interface
> +--
> +
> +Required properties:
> +  - compatible: value must be "allwinner,sun8i-v3s-csi"
> +  - reg: base address and size of the memory-mapped region.
> +  - interrupts: interrupt associated to this IP
> +  - clocks: phandles to the clocks feeding the CSI
> +* ahb: the CSI interface clock
> +* mod: the CSI module clock
> +* ram: the CSI DRAM clock
> +  - clock-names: the clock names mentioned above
> +  - resets: phandles to the reset line driving the CSI
> +
> +- ports: A ports node with endpoint definitions as defined in
> +  Documentation/devicetree/bindings/media/video-interfaces.txt.

Need to be explicit about how many ports and endpoints and what each one 
represents.

> +
> +Example:
> +
> + csi1: csi@01cb4000 {
> + compatible = "allwinner,sun8i-v3s-csi";
> + reg = <0x01cb4000 0x1000>;
> + interrupts = ;
> + clocks = < CLK_BUS_CSI>,
> +  < CLK_CSI1_SCLK>,
> +  < CLK_DRAM_CSI>;
> + clock-names = "ahb", "mod", "ram";
> + resets = < RST_BUS_CSI>;
> +
> + port {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* Parallel bus endpoint */
> + csi1_ep: endpoint {
> + remote-endpoint = <_ep>;
> + bus-width = <16>;
> + data-shift = <0>;
> +
> + /* If hsync-active/vsync-active are missing,
> +embedded BT.656 sync is used */
> + hsync-active = <0>; /* Active low */
> + vsync-active = <0>; /* Active low */
> + data-active = <1>;  /* Active high */
> + pclk-sample = <1>;  /* Rising */
> + };
> + };
> + };
> +
> -- 
> 1.8.3.1
> 

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[linux-sunxi] Re: [PATCH v2 1/3] DT: mailbox: add binding doc for the ARM SMC mailbox

2017-08-03 Thread Rob Herring 
On Mon, Jul 24, 2017 at 12:23:24AM +0100, Andre Przywara wrote:
> The ARM SMC mailbox binding describes a firmware interface to trigger
> actions in software layers running in the EL2 or EL3 exception levels.
> The term "ARM" here relates to the SMC instruction as part of the ARM
> instruction set, not as a standard endorsed by ARM Ltd.
> 
> Signed-off-by: Andre Przywara 
> ---
>  .../devicetree/bindings/mailbox/arm-smc.txt| 76 
> ++
>  1 file changed, 76 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mailbox/arm-smc.txt
> 
> diff --git a/Documentation/devicetree/bindings/mailbox/arm-smc.txt 
> b/Documentation/devicetree/bindings/mailbox/arm-smc.txt
> new file mode 100644
> index 000..d9de57b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mailbox/arm-smc.txt
> @@ -0,0 +1,76 @@
> +ARM SMC Mailbox Interface
> +=
> +
> +This mailbox uses the ARM smc (secure monitor call) instruction to
> +trigger a mailbox-connected activity in firmware, executing on the very same
> +core as the caller. By nature this operation is synchronous and this
> +mailbox provides no way for asynchronous messages to be delivered the other
> +way round, from firmware to the OS. However the value of r0/w0/x0 the 
> firmware
> +returns after the smc call is delivered as a received message to the
> +mailbox framework, so a synchronous communication can be established.
> +The exact meaning of both the action the mailbox triggers as well as the
> +return value is defined by their users and is not subject to this binding.
> +
> +One use case of this mailbox is the SCP interface, which uses shared memory
> +to transfer commands and parameters, and a mailbox to trigger a function
> +call. This allows SoCs without a separate management processor (or
> +when such a processor is not available or used) to use this standardized
> +interface anyway.
> +
> +This binding describes no hardware, but establishes a firmware interface.
> +Upon receiving an SMC using one of the described SMC function identifiers,
> +the firmware is expected to trigger some mailbox connected functionality.
> +The communication follows the ARM SMC calling convention[1]:
> +Firmware expects an SMC function identifier in r0 or w0 to identify a
> +particular mailbox. The supported identifiers are listed in the the
> +arm,func-ids properties, as described below.
> +Apart from those mandatory SMC function identifier there are no further
> +arguments handled by the receiving end.
> +The firmware can return one value in the first SMC result register, it
> +is expected to be an error value, which shall be propagated to the mailbox
> +client.
> +The C prototype of the function would be:
> + unsigned long smc_mailbox_call(unsigned long mailbox_identifier);
> +The SMC function call is expected to be a fast call and could be from
> +any of the defined function ranges.
> +
> +Any core which supports the SMC or HVC instruction can be used, as long as
> +a firmware component running in EL3 or EL2 is handling these calls.
> +
> +Mailbox Device Node:
> +
> +
> +This node is expected to be a child of the /firmware node.
> +
> +Required properties:
> +
> +- compatible:Shall be "arm,smc-mbox"
> +- #mbox-cellsShall be 1 - the index of the channel needed.
> +- arm,func-ids   An array of 32-bit values specifying the 
> function
> + IDs used by each mailbox channel. Those function IDs
> + follow the ARM SMC calling convention standard [1].
> + There is one identifier per channel and the number
> + of supported channels is determined by the length
> + of this array.

I agree with Jassi's comment on making these a client cell and just 
define the number of channels here. 

> +- method:A string, either:
> + "hvc": if the driver shall use an HVC call, or
> + "smc": if the driver shall use an SMC call.
> +
> +Example:
> +
> +
> + smc_mbox: mailbox {
> + #mbox-cells = <1>;
> + compatible = "arm,smc-mbox";
> + arm,func-ids = <0x8201>, <0x8202>;
> + };
> +
> + scpi {
> + compatible = "arm,scpi";
> + mboxes = < 0>;
> + shmem = <_scp_shmem>;
> + };
> +
> +
> +[1]
> +http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0028a/index.html
> -- 
> 2.8.2
> 

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[linux-sunxi] Re: [PATCH v3 1/5] dt-bindings: update the Allwinner GPADC device tree binding for H3

2017-08-03 Thread Rob Herring 
On Sun, Jul 23, 2017 at 10:13:50PM +0800, Icenowy Zheng wrote:
> Allwinner H3 features a thermal sensor like the one in A33, but has its
> register re-arranged, the clock divider moved to CCU (originally the
> clock divider is in ADC) and added a pair of bus clock and reset.
> 
> Update the binding document to cover H3.
> 
> Signed-off-by: Icenowy Zheng 
> ---
> Changes in v3:
> - Clock name changes.
> - Example node name changes.
> - Add interupts (not yet used by the driver).
> 
>  .../devicetree/bindings/mfd/sun4i-gpadc.txt| 25 
> --
>  1 file changed, 23 insertions(+), 2 deletions(-)

Acked-by: Rob Herring 

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[linux-sunxi] Re: [PATCH 01/10] dt-bindings: add binding for the SY8160A voltage regulator

2017-08-03 Thread Rob Herring 
On Sun, Jul 23, 2017 at 06:27:40PM +0800, Icenowy Zheng wrote:
> From: Ondrej Jirman 
> 
> SY8106A is an I2C-controlled adjustable voltage regulator made by
> Silergy Corp.
> 
> Add its device tree binding.
> 
> Signed-off-by: Ondrej Jirman 
> [Icenowy: Change commit message]
> Signed-off-by: Icenowy Zheng 
> ---
>  .../bindings/regulator/sy8106a-regulator.txt| 21 
> +
>  1 file changed, 21 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/regulator/sy8106a-regulator.txt

Acked-by: Rob Herring 

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[linux-sunxi] Re: [PATCH v3 00/10] ARM: sun8i: a83t: Add support for MMC controllers

2017-08-03 Thread Ulf Hansson 
On 3 August 2017 at 13:25, Chen-Yu Tsai  wrote:
> On Thu, Aug 3, 2017 at 7:19 PM, Ulf Hansson  wrote:
>> On 26 July 2017 at 21:45, Maxime Ripard
>>  wrote:
>>> On Wed, Jul 26, 2017 at 10:09:41PM +0800, Chen-Yu Tsai wrote:
 On Mon, Jul 24, 2017 at 9:58 PM, Chen-Yu Tsai  wrote:
 > Hi everyone,
 >
 > This is v3 of my MMC controller support series.
 >

 [...]

 > Chen-Yu Tsai (10):
 >   clk: sunxi-ng: Add interface to query or configure MMC timing modes.
 >   clk: sunxi-ng: Add MP_MMC clocks that support MMC timing modes
 > switching
 >   clk: sunxi-ng: a83t: Support new timing mode for mmc2 clock
 >   mmc: sunxi: Support controllers that can use both old and new timings
 >   mmc: sunxi: Support MMC DDR52 transfer mode with new timing mode
 >   mmc: sunxi: Add support for A83T eMMC (MMC2)

 So this series seems to be ready for inclusion, unless Ulf has further
 concerns about the clk usage.

 The first mmc patch have build time dependencies on the first clk patch.
 Shall we put the clk patch on a separate immutable branch for both trees
 to pull? Or we could just merge everything through the mmc tree? I don't
 think we'll touch this part of the sunxi-ng clk driver for the remainder
 of this cycle.
>>>
>>> I guess the easiest would be for it to go through Ulf tree, unless he
>>> says otherwise of course :)
>>
>> Okay, I have picked up the series and applied it for my next branch.
>
> I guess I wasn't very clear. When I meant "everything" I meant the mmc
> and clk patches. We will take the dts patches through the sunxi tree.
>
> Can you drop the four dts patches from your tree? That would be the
> last four patches on mmc/next at the moment.

Done!

Kind regards
Uffe

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[linux-sunxi] Re: [PATCH v3 00/10] ARM: sun8i: a83t: Add support for MMC controllers

2017-08-03 Thread Chen-Yu Tsai 
On Thu, Aug 3, 2017 at 7:19 PM, Ulf Hansson  wrote:
> On 26 July 2017 at 21:45, Maxime Ripard
>  wrote:
>> On Wed, Jul 26, 2017 at 10:09:41PM +0800, Chen-Yu Tsai wrote:
>>> On Mon, Jul 24, 2017 at 9:58 PM, Chen-Yu Tsai  wrote:
>>> > Hi everyone,
>>> >
>>> > This is v3 of my MMC controller support series.
>>> >
>>>
>>> [...]
>>>
>>> > Chen-Yu Tsai (10):
>>> >   clk: sunxi-ng: Add interface to query or configure MMC timing modes.
>>> >   clk: sunxi-ng: Add MP_MMC clocks that support MMC timing modes
>>> > switching
>>> >   clk: sunxi-ng: a83t: Support new timing mode for mmc2 clock
>>> >   mmc: sunxi: Support controllers that can use both old and new timings
>>> >   mmc: sunxi: Support MMC DDR52 transfer mode with new timing mode
>>> >   mmc: sunxi: Add support for A83T eMMC (MMC2)
>>>
>>> So this series seems to be ready for inclusion, unless Ulf has further
>>> concerns about the clk usage.
>>>
>>> The first mmc patch have build time dependencies on the first clk patch.
>>> Shall we put the clk patch on a separate immutable branch for both trees
>>> to pull? Or we could just merge everything through the mmc tree? I don't
>>> think we'll touch this part of the sunxi-ng clk driver for the remainder
>>> of this cycle.
>>
>> I guess the easiest would be for it to go through Ulf tree, unless he
>> says otherwise of course :)
>
> Okay, I have picked up the series and applied it for my next branch.

I guess I wasn't very clear. When I meant "everything" I meant the mmc
and clk patches. We will take the dts patches through the sunxi tree.

Can you drop the four dts patches from your tree? That would be the
last four patches on mmc/next at the moment.

Thanks and sorry for the confusion.

ChenYu

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[linux-sunxi] Re: [PATCH v3 00/10] ARM: sun8i: a83t: Add support for MMC controllers

2017-08-03 Thread Ulf Hansson 
On 26 July 2017 at 21:45, Maxime Ripard
 wrote:
> On Wed, Jul 26, 2017 at 10:09:41PM +0800, Chen-Yu Tsai wrote:
>> On Mon, Jul 24, 2017 at 9:58 PM, Chen-Yu Tsai  wrote:
>> > Hi everyone,
>> >
>> > This is v3 of my MMC controller support series.
>> >
>>
>> [...]
>>
>> > Chen-Yu Tsai (10):
>> >   clk: sunxi-ng: Add interface to query or configure MMC timing modes.
>> >   clk: sunxi-ng: Add MP_MMC clocks that support MMC timing modes
>> > switching
>> >   clk: sunxi-ng: a83t: Support new timing mode for mmc2 clock
>> >   mmc: sunxi: Support controllers that can use both old and new timings
>> >   mmc: sunxi: Support MMC DDR52 transfer mode with new timing mode
>> >   mmc: sunxi: Add support for A83T eMMC (MMC2)
>>
>> So this series seems to be ready for inclusion, unless Ulf has further
>> concerns about the clk usage.
>>
>> The first mmc patch have build time dependencies on the first clk patch.
>> Shall we put the clk patch on a separate immutable branch for both trees
>> to pull? Or we could just merge everything through the mmc tree? I don't
>> think we'll touch this part of the sunxi-ng clk driver for the remainder
>> of this cycle.
>
> I guess the easiest would be for it to go through Ulf tree, unless he
> says otherwise of course :)

Okay, I have picked up the series and applied it for my next branch.

Thanks and kind regards
Uffe

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[linux-sunxi] Re: [PATCH] This patch adds support for Sinovoip BPI-M3 A83T based board.

2017-08-03 Thread Philipp Rossak 
Thanks for the infos!

I didn't know that someone is working on some patches for that board.

Philipp Rossak

On Aug 3, 2017 06:31, "Chen-Yu Tsai"  wrote:

On Thu, Aug 3, 2017 at 7:25 AM, Philipp Rossak  wrote:
> From: Philipp Rossak 
>
> It has 2G LPDDR3, UART, ethernet, USB, HDMI, USB Sata, MIPI DSI,
> mic, AP6212 Wifi, etc on it.
> It is paired with AXP813 PMIC which is almost same as AXP818.
>
> Signed-off-by: Vishnu Patekar 
>
> This Patch got somehow lost. This is a resubmit! The original patch
> could be found here: https://patchwork.ozlabs.org/patch/598497/

This didn't get merged because the original patch sets dealt with
a lot of stuff that wasn't settled.

Also, you should keep the author when resending patches.

Finally, I have a more complete version that I plan to send soon:

https://github.com/wens/linux/commit/240a2492b3379646e2f497d5ade701
4ff955f818

Note that the dts file name is changed to bananapi-m3, to match
what we have for most of the other bananapi boards.

ChenYu

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[linux-sunxi] [PATCH 8/8] ARM: sun8i: a83t: h8homlet-v2: Enable USB ports

2017-08-03 Thread Chen-Yu Tsai 
The h8homlet board has the A83T's standard USB 1.1/2.0 host pair routed
to a USB host port on the board. The other USB host port is routed to
USB OTG controller.

Signed-off-by: Chen-Yu Tsai 
---
 .../boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts  | 29 ++
 1 file changed, 29 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts 
b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
index e0055180d29f..1f0d60afb25b 100644
--- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
@@ -58,6 +58,10 @@
};
 };
 
+ {
+   status = "okay";
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins>;
@@ -78,6 +82,20 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+};
+
+_usb0_vbus {
+   gpio = <_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
+   status = "okay";
+};
+
+_usb1_vbus {
+   gpio = <_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
+   status = "okay";
+};
+
 _rsb {
status = "okay";
 
@@ -118,3 +136,14 @@
pinctrl-0 = <_pb_pins>;
status = "okay";
 };
+
+ {
+   usb0_vbus-supply = <_usb0_vbus>;
+   usb1_vbus-supply = <_usb1_vbus>;
+   status = "okay";
+};
+
+_otg {
+   dr_mode = "host";
+   status = "okay";
+};
-- 
2.13.3

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[linux-sunxi] [PATCH 2/8] dt-bindings: phy: sun4i-usb-phy: Add compatible string for A83T

2017-08-03 Thread Chen-Yu Tsai 
The A83T has 3 USB PHYs, 1 for OTG, 1 for standard USB, 1 for USB HSIC.

Add a compatible string for it, and describe the needed properties.

Signed-off-by: Chen-Yu Tsai 
Tested-by: Maxime Ripard 
---
 Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt 
b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
index 893dd01dfe64..cbc7847dbf6c 100644
--- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
@@ -9,6 +9,7 @@ Required properties:
   * allwinner,sun7i-a20-usb-phy
   * allwinner,sun8i-a23-usb-phy
   * allwinner,sun8i-a33-usb-phy
+  * allwinner,sun8i-a83t-usb-phy
   * allwinner,sun8i-h3-usb-phy
   * allwinner,sun8i-v3s-usb-phy
   * allwinner,sun50i-a64-usb-phy
@@ -17,7 +18,7 @@ Required properties:
   * "phy_ctrl"
   * "pmu0" for H3, V3s and A64
   * "pmu1"
-  * "pmu2" for sun4i, sun6i, sun7i or sun8i-h3
+  * "pmu2" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3
   * "pmu3" for sun8i-h3
 - #phy-cells : from the generic phy bindings, must be 1
 - clocks : phandle + clock specifier for the phy clocks
@@ -25,12 +26,13 @@ Required properties:
   * "usb_phy" for sun4i, sun5i or sun7i
   * "usb0_phy", "usb1_phy" and "usb2_phy" for sun6i
   * "usb0_phy", "usb1_phy" for sun8i
+  * "usb0_phy", "usb1_phy", "usb2_phy" and "usb2_hsic_12M" for sun8i-a83t
   * "usb0_phy", "usb1_phy", "usb2_phy" and "usb3_phy" for sun8i-h3
 - resets : a list of phandle + reset specifier pairs
 - reset-names :
   * "usb0_reset"
   * "usb1_reset"
-  * "usb2_reset" for sun4i, sun6i, sun7i or sun8i-h3
+  * "usb2_reset" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3
   * "usb3_reset" for sun8i-h3
 
 Optional properties:
-- 
2.13.3

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[linux-sunxi] [PATCH 7/8] ARM: sun8i: a83t: cubietruck-plus: Enable onboard USB peripherals

2017-08-03 Thread Chen-Yu Tsai 
The Cubietruck-plus has a GL830 USB-to-SATA bridge connected to EHCI0,
and a USB3503 HSIC USB 2.0 hub connected to EHCI1. The USB3503's I2C
control interface is not connected.

This patch enables both EHCI controllers, adds a device node for the
USB hub, and includes sunxi-common-regulators.dtsi for the VBUS
regulators. The existing reg_vcc3v3 is dropped as it is also available
in the set of common regulators. Other unused regulators are disabled.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 49 +---
 1 file changed, 44 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts 
b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
index f583e5b9a1c8..716a205c6dbb 100644
--- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
@@ -44,6 +44,7 @@
 
 /dts-v1/;
 #include "sun8i-a83t.dtsi"
+#include "sunxi-common-regulators.dtsi"
 
 #include 
 
@@ -83,11 +84,15 @@
};
};
 
-   reg_vcc3v3: vcc3v3 {
-   compatible = "regulator-fixed";
-   regulator-name = "vcc3v3";
-   regulator-min-microvolt = <330>;
-   regulator-max-microvolt = <330>;
+   usb-hub {
+   /* I2C is not connected */
+   compatible = "smsc,usb3503";
+   initial-mode = <1>; /* initialize in HUB mode */
+   disabled-ports = <1>;
+   intn-gpios = < 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+   reset-gpios = < 4 16 GPIO_ACTIVE_HIGH>; /* PE16 */
+   connect-gpios = < 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */
+   refclk-frequency = <1920>;
};
 
sound {
@@ -109,6 +114,16 @@
};
 };
 
+ {
+   /* GL830 USB-to-SATA bridge here */
+   status = "okay";
+};
+
+ {
+   /* USB3503 HSIC USB 2.0 hub here */
+   status = "okay";
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins>;
@@ -164,6 +179,24 @@
};
 };
 
+_usb1_vbus {
+   gpio = < 3 29 GPIO_ACTIVE_HIGH>; /* PD29 */
+   status = "okay";
+};
+
+_usb2_vbus {
+   gpio = <_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
+   status = "okay";
+};
+
+_vcc3v0 {
+   status = "disabled";
+};
+
+_vcc5v0 {
+   status = "disabled";
+};
+
  {
status = "okay";
 };
@@ -173,3 +206,9 @@
pinctrl-0 = <_pb_pins>;
status = "okay";
 };
+
+ {
+   usb1_vbus-supply = <_usb1_vbus>;
+   usb2_vbus-supply = <_usb2_vbus>;
+   status = "okay";
+};
-- 
2.13.3

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[linux-sunxi] [PATCH 0/8] ARM: sun8i: a83t: Add USB host support

2017-08-03 Thread Chen-Yu Tsai 
Hi everyone,

This series enables USB host support for the Allwinner A83T SoC.
The A83T's USB OTG PHY uses different controls. The USB 2.0 host
PHYs are the same as previous chips. And the HSIC part is actually
used on some boards.

The external bits needed for proper USB OTG support is not there
yet, namely the regulators and power supplies for VBUS sensing and
control. This will be enabled later on. However the OTG controller
is the same as the one found in previous chips. This has been tested
under U-boot.

Patch 1 adds some properties that were missing for the H3. The H3
has 4 USB host controllers, so there are also 4 USB host PHYs. The
properies for the last one were missing.

Patch 2 adds a compatible string for the A83T USB PHY block.

Patch 3 adds support for a secondary clock for the HSIC PHY. The
HSIC block takes a 480MHz clock and a 12MHz clock. All known chips
only have at most 1 HSIC capable host/PHY.

Patch 4 adds support for the A83T's USB PHYs. The difference is
mainly how the OTG PHY (PHY0) is configured.

Patch 5 adds the device nodes for the USB PHY and hosts.

Patch 6 adds the device node for the USB OTG controller.

Patch 7 enables the USB hosts and peripherals on the Cubietruck Plus.

Patch 8 enables the USB hosts and peripherals on the H8Homlet v2.

The first four patches would go through linux-phy, while I will
take the other four through the sunxi tree. For those who want
to test this, the series is based on my previous "ARM: sun8i: a83t:
Add support for MMC controllers v3" and "mfd: axp20x: Add basic
support for AXP813 v2" series.


Regards
ChenYu

Chen-Yu Tsai (8):
  dt-bindings: phy: sun4i-usb-phy: Add property descriptions for H3
  dt-bindings: phy: sun4i-usb-phy: Add compatible string for A83T
  phy: sun4i-usb: Support secondary clock for HSIC PHY
  phy: sun4i-usb: Support A83T USB PHYs
  ARM: sun8i: a83t: Add USB PHY and host device nodes
  ARM: sun8i: a83t: Add device node for USB OTG controller
  ARM: sun8i: a83t: cubietruck-plus: Enable onboard USB peripherals
  ARM: sun8i: a83t: h8homlet-v2: Enable USB ports

 .../devicetree/bindings/phy/sun4i-usb-phy.txt  | 10 ++-
 .../boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts  | 29 
 arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts   | 49 ++--
 arch/arm/boot/dts/sun8i-a83t.dtsi  | 76 +++
 drivers/phy/allwinner/phy-sun4i-usb.c  | 87 +++---
 5 files changed, 232 insertions(+), 19 deletions(-)

-- 
2.13.3

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[linux-sunxi] [PATCH 3/8] phy: sun4i-usb: Support secondary clock for HSIC PHY

2017-08-03 Thread Chen-Yu Tsai 
On the Allwinner A83T SoC, the last USB PHY is an HSIC PHY. It requires
two clocks instead of one.

On all Allwinner SoCs that share the common USB PHY design supported by
the phy-sun4i-usb driver, the first PHY is always tied to OTG, and there
is at most one HSIC PHY, typically the last.

In this patch we take advantage of these known constraints and store an
index in the compatible-string-related config structure describing which
PHY is HSIC, needing the extra hsic_12M clock.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/phy/allwinner/phy-sun4i-usb.c | 21 +
 1 file changed, 21 insertions(+)

diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c 
b/drivers/phy/allwinner/phy-sun4i-usb.c
index bbf06cfe5898..79157eced75a 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -107,6 +107,7 @@ enum sun4i_usb_phy_type {
 
 struct sun4i_usb_phy_cfg {
int num_phys;
+   int hsic_index;
enum sun4i_usb_phy_type type;
u32 disc_thresh;
u8 phyctl_offset;
@@ -126,6 +127,7 @@ struct sun4i_usb_phy_data {
struct regulator *vbus;
struct reset_control *reset;
struct clk *clk;
+   struct clk *clk2;
bool regulator_on;
int index;
} phys[MAX_PHYS];
@@ -261,8 +263,15 @@ static int sun4i_usb_phy_init(struct phy *_phy)
if (ret)
return ret;
 
+   ret = clk_prepare_enable(phy->clk2);
+   if (ret) {
+   clk_disable_unprepare(phy->clk);
+   return ret;
+   }
+
ret = reset_control_deassert(phy->reset);
if (ret) {
+   clk_disable_unprepare(phy->clk2);
clk_disable_unprepare(phy->clk);
return ret;
}
@@ -315,6 +324,7 @@ static int sun4i_usb_phy_exit(struct phy *_phy)
 
sun4i_usb_phy_passby(phy, 0);
reset_control_assert(phy->reset);
+   clk_disable_unprepare(phy->clk2);
clk_disable_unprepare(phy->clk);
 
return 0;
@@ -706,6 +716,17 @@ static int sun4i_usb_phy_probe(struct platform_device 
*pdev)
return PTR_ERR(phy->clk);
}
 
+   /* The first PHY is always tied to OTG, and never HSIC */
+   if (data->cfg->hsic_index && i == data->cfg->hsic_index) {
+   /* HSIC needs secondary clock */
+   snprintf(name, sizeof(name), "usb%d_hsic_12M", i);
+   phy->clk2 = devm_clk_get(dev, name);
+   if (IS_ERR(phy->clk2)) {
+   dev_err(dev, "failed to get clock %s\n", name);
+   return PTR_ERR(phy->clk2);
+   }
+   }
+
snprintf(name, sizeof(name), "usb%d_reset", i);
phy->reset = devm_reset_control_get(dev, name);
if (IS_ERR(phy->reset)) {
-- 
2.13.3

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[linux-sunxi] [PATCH 4/8] phy: sun4i-usb: Support A83T USB PHYs

2017-08-03 Thread Chen-Yu Tsai 
The A83T has 3 USB PHYs, 1 for OTG, 1 for standard USB, 1 for USB HSIC.
The phy initialization procedure is very different from other SoCs, but
the PMU bits are the same, with additional bits for HSIC.

Signed-off-by: Chen-Yu Tsai 
Tested-by: Maxime Ripard 
---
 drivers/phy/allwinner/phy-sun4i-usb.c | 66 ---
 1 file changed, 54 insertions(+), 12 deletions(-)

diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c 
b/drivers/phy/allwinner/phy-sun4i-usb.c
index 79157eced75a..af16f4fb9707 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -87,6 +87,16 @@
 #define PHY_DISCON_TH_SEL  0x2a
 #define PHY_SQUELCH_DETECT 0x3c
 
+/* A83T specific control bits for PHY0 */
+#define PHY_CTL_VBUSVLDEXT BIT(5)
+#define PHY_CTL_SIDDQ  BIT(3)
+
+/* A83T specific control bits for PHY2 HSIC */
+#define SUNXI_EHCI_HS_FORCEBIT(20)
+#define SUNXI_HSIC_CONNECT_DET BIT(17)
+#define SUNXI_HSIC_CONNECT_INT BIT(16)
+#define SUNXI_HSIC BIT(1)
+
 #define MAX_PHYS   4
 
 /*
@@ -100,6 +110,7 @@ enum sun4i_usb_phy_type {
sun4i_a10_phy,
sun6i_a31_phy,
sun8i_a33_phy,
+   sun8i_a83t_phy,
sun8i_h3_phy,
sun8i_v3s_phy,
sun50i_a64_phy,
@@ -234,6 +245,7 @@ static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, 
u32 addr, u32 data,
 
 static void sun4i_usb_phy_passby(struct sun4i_usb_phy *phy, int enable)
 {
+   struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy);
u32 bits, reg_value;
 
if (!phy->pmu)
@@ -242,6 +254,11 @@ static void sun4i_usb_phy_passby(struct sun4i_usb_phy 
*phy, int enable)
bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
 
+   /* A83T USB2 is HSIC */
+   if (phy_data->cfg->type == sun8i_a83t_phy && phy->index == 2)
+   bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
+   SUNXI_HSIC;
+
reg_value = readl(phy->pmu);
 
if (enable)
@@ -276,21 +293,30 @@ static int sun4i_usb_phy_init(struct phy *_phy)
return ret;
}
 
-   if (phy->pmu && data->cfg->enable_pmu_unk1) {
-   val = readl(phy->pmu + REG_PMU_UNK1);
-   writel(val & ~2, phy->pmu + REG_PMU_UNK1);
-   }
+   if (data->cfg->type == sun8i_a83t_phy) {
+   if (phy->index == 0) {
+   val = readl(data->base + data->cfg->phyctl_offset);
+   val |= PHY_CTL_VBUSVLDEXT;
+   val &= ~PHY_CTL_SIDDQ;
+   writel(val, data->base + data->cfg->phyctl_offset);
+   }
+   } else {
+   if (phy->pmu && data->cfg->enable_pmu_unk1) {
+   val = readl(phy->pmu + REG_PMU_UNK1);
+   writel(val & ~2, phy->pmu + REG_PMU_UNK1);
+   }
 
-   /* Enable USB 45 Ohm resistor calibration */
-   if (phy->index == 0)
-   sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
+   /* Enable USB 45 Ohm resistor calibration */
+   if (phy->index == 0)
+   sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
 
-   /* Adjust PHY's magnitude and rate */
-   sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
+   /* Adjust PHY's magnitude and rate */
+   sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
 
-   /* Disconnect threshold adjustment */
-   sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
-   data->cfg->disc_thresh, 2);
+   /* Disconnect threshold adjustment */
+   sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
+   data->cfg->disc_thresh, 2);
+   }
 
sun4i_usb_phy_passby(phy, 1);
 
@@ -316,6 +342,13 @@ static int sun4i_usb_phy_exit(struct phy *_phy)
struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
 
if (phy->index == 0) {
+   if (data->cfg->type == sun8i_a83t_phy) {
+   void __iomem *phyctl = data->base +
+   data->cfg->phyctl_offset;
+
+   writel(readl(phyctl) | PHY_CTL_SIDDQ, phyctl);
+   }
+
/* Disable pull-ups */
sun4i_usb_phy0_update_iscr(_phy, ISCR_DPDM_PULLUP_EN, 0);
sun4i_usb_phy0_update_iscr(_phy, ISCR_ID_PULLUP_EN, 0);
@@ -853,6 +886,14 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
.enable_pmu_unk1 = false,
 };
 
+static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
+   .num_phys = 3,
+   .hsic_index = 2,
+   .type = sun8i_a83t_phy,
+   .phyctl_offset = REG_PHYCTL_A33,
+   .dedicated_clocks = true,
+};
+

[linux-sunxi] [PATCH 1/8] dt-bindings: phy: sun4i-usb-phy: Add property descriptions for H3

2017-08-03 Thread Chen-Yu Tsai 
The Allwinner H3 SoC has 4 USB PHYs, so it needs four sets of pmu
regions, clocks, resets, and optional vbus properties. These were
not described when the H3 compatible string was added.

Fixes: 626a630e003c ("phy-sun4i-usb: Add support for the host usb-phys
  found on the H3 SoC")
Signed-off-by: Chen-Yu Tsai 
---
 Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt 
b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
index 005bc22938ff..893dd01dfe64 100644
--- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
@@ -17,18 +17,21 @@ Required properties:
   * "phy_ctrl"
   * "pmu0" for H3, V3s and A64
   * "pmu1"
-  * "pmu2" for sun4i, sun6i or sun7i
+  * "pmu2" for sun4i, sun6i, sun7i or sun8i-h3
+  * "pmu3" for sun8i-h3
 - #phy-cells : from the generic phy bindings, must be 1
 - clocks : phandle + clock specifier for the phy clocks
 - clock-names :
   * "usb_phy" for sun4i, sun5i or sun7i
   * "usb0_phy", "usb1_phy" and "usb2_phy" for sun6i
   * "usb0_phy", "usb1_phy" for sun8i
+  * "usb0_phy", "usb1_phy", "usb2_phy" and "usb3_phy" for sun8i-h3
 - resets : a list of phandle + reset specifier pairs
 - reset-names :
   * "usb0_reset"
   * "usb1_reset"
-  * "usb2_reset" for sun4i, sun6i or sun7i
+  * "usb2_reset" for sun4i, sun6i, sun7i or sun8i-h3
+  * "usb3_reset" for sun8i-h3
 
 Optional properties:
 - usb0_id_det-gpios : gpio phandle for reading the otg id pin value
@@ -37,6 +40,7 @@ Optional properties:
 - usb0_vbus-supply : regulator phandle for controller usb0 vbus
 - usb1_vbus-supply : regulator phandle for controller usb1 vbus
 - usb2_vbus-supply : regulator phandle for controller usb2 vbus
+- usb3_vbus-supply : regulator phandle for controller usb3 vbus
 
 Example:
usbphy: phy@0x01c13400 {
-- 
2.13.3

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[linux-sunxi] [PATCH 5/8] ARM: sun8i: a83t: Add USB PHY and host device nodes

2017-08-03 Thread Chen-Yu Tsai 
The A83T has 3 USB PHYs, 1 for USB OTG, 1 for standard USB 2.0, 1 for
USB HSIC. EHCI0/OHCI0 are the standard USB host pair, while EHCI1 is
the host controller for HSIC. OTG is not added yet.

Signed-off-by: Chen-Yu Tsai 
Tested-by: Maxime Ripard 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 62 +++
 1 file changed, 62 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 61304761e8f6..6039f1ea6810 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -242,6 +242,68 @@
#size-cells = <0>;
};
 
+   usbphy: phy@1c19400 {
+   compatible = "allwinner,sun8i-a83t-usb-phy";
+   reg = <0x01c19400 0x10>,
+ <0x01c1a800 0x14>,
+ <0x01c1b800 0x14>;
+   reg-names = "phy_ctrl",
+   "pmu1",
+   "pmu2";
+   clocks = < CLK_USB_PHY0>,
+< CLK_USB_PHY1>,
+< CLK_USB_HSIC>,
+< CLK_USB_HSIC_12M>;
+   clock-names = "usb0_phy",
+ "usb1_phy",
+ "usb2_phy",
+ "usb2_hsic_12M";
+   resets = < RST_USB_PHY0>,
+< RST_USB_PHY1>,
+< RST_USB_HSIC>;
+   reset-names = "usb0_reset",
+ "usb1_reset",
+ "usb2_reset";
+   status = "disabled";
+   #phy-cells = <1>;
+   };
+
+   ehci0: usb@1c1a000 {
+   compatible = "allwinner,sun8i-a83t-ehci",
+"generic-ehci";
+   reg = <0x01c1a000 0x100>;
+   interrupts = ;
+   clocks = < CLK_BUS_EHCI0>;
+   resets = < RST_BUS_EHCI0>;
+   phys = < 1>;
+   phy-names = "usb";
+   status = "disabled";
+   };
+
+   ohci0: usb@1c1a400 {
+   compatible = "allwinner,sun8i-a83t-ohci",
+"generic-ohci";
+   reg = <0x01c1a400 0x100>;
+   interrupts = ;
+   clocks = < CLK_BUS_OHCI0>, < CLK_USB_OHCI0>;
+   resets = < RST_BUS_OHCI0>;
+   phys = < 1>;
+   phy-names = "usb";
+   status = "disabled";
+   };
+
+   ehci1: usb@1c1b000 {
+   compatible = "allwinner,sun8i-a83t-ehci",
+"generic-ehci";
+   reg = <0x01c1b000 0x100>;
+   interrupts = ;
+   clocks = < CLK_BUS_EHCI1>;
+   resets = < RST_BUS_EHCI1>;
+   phys = < 2>;
+   phy-names = "usb";
+   status = "disabled";
+   };
+
ccu: clock@1c2 {
compatible = "allwinner,sun8i-a83t-ccu";
reg = <0x01c2 0x400>;
-- 
2.13.3

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[linux-sunxi] [PATCH 6/8] ARM: sun8i: a83t: Add device node for USB OTG controller

2017-08-03 Thread Chen-Yu Tsai 
The USB OTG controller found on the A83T is compatible with the one
found on the A33.

Add a device node for it.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 6039f1ea6810..f996bd343e50 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -242,6 +242,20 @@
#size-cells = <0>;
};
 
+   usb_otg: usb@01c19000 {
+   compatible = "allwinner,sun8i-a83t-musb",
+"allwinner,sun8i-a33-musb";
+   reg = <0x01c19000 0x0400>;
+   clocks = < CLK_BUS_OTG>;
+   resets = < RST_BUS_OTG>;
+   interrupts = ;
+   interrupt-names = "mc";
+   phys = < 0>;
+   phy-names = "usb";
+   extcon = < 0>;
+   status = "disabled";
+   };
+
usbphy: phy@1c19400 {
compatible = "allwinner,sun8i-a83t-usb-phy";
reg = <0x01c19400 0x10>,
-- 
2.13.3

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