[linux-sunxi] Re: [PATCH v4 09/13] ARM: dts: sun8i: r40: add sata node
在 2018-08-31五的 19:31 +0800，Chen-Yu Tsai写道：
> On Fri, Aug 31, 2018 at 6:54 PM Corentin Labbe
> wrote:
> >
> > On Fri, Aug 31, 2018 at 12:20:21PM +0200, maxime.rip...@bootlin.com
> > wrote:
> > > On Fri, Aug 31, 2018 at 09:56:31AM +0200, Corentin Labbe wrote:
> > > > On Fri, Aug 31, 2018 at 09:35:00AM +0200, Maxime Ripard wrote:
> > > > > On Thu, Aug 30, 2018 at 09:01:16PM +0200, Corentin Labbe
> > > > > wrote:
> > > > > > R40 have a sata controller which is the same as A20.
> > > > > > This patch adds a DT node for it.
> > > > > >
> > > > > > Signed-off-by: Icenowy Zheng
> > > > > > Signed-off-by: Corentin Labbe
> > > > > > ---
> > > > > > arch/arm/boot/dts/sun8i-r40.dtsi | 23
> > > > > > +++
> > > > > > 1 file changed, 23 insertions(+)
> > > > > >
> > > > > > diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi
> > > > > > b/arch/arm/boot/dts/sun8i-r40.dtsi
> > > > > > index 852c2ccc3268..d6b5820da850 100644
> > > > > > --- a/arch/arm/boot/dts/sun8i-r40.dtsi
> > > > > > +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> > > > > > @@ -550,6 +550,29 @@
> > > > > > #size-cells = <0>;
> > > > > > };
> > > > > >
> > > > > > + ahci: sata@1c18000 {
> > > > > > + compatible = "allwinner,sun8i-r40-
> > > > > > ahci";
> > > > > > + reg = <0x01c18000 0x1000>;
> > > > > > + interrupts = > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + clocks = <&ccu CLK_BUS_SATA>, <&ccu
> > > > > > CLK_SATA>;
> > > > > > + resets = <&ccu RST_BUS_SATA>;
> > > > > > + resets-name = "ahci";
> > > > > > + #address-cells = <1>;
> > > > > > + #size-cells = <0>;
> > > > > > + status = "disabled";
> > > > > > +
> > > > > > + sata_port: sata-port@0 {
> > > > > > + reg = <0>;
> > > > > > + phys = <&sata_phy>;
> > > > > > + };
> > > > > > + };
> > > > > > +
> > > > > > + sata_phy: sata-phy@1c180c0 {
> > > > > > + compatible = "allwinner,sun8i-r40-
> > > > > > sata-phy";
> > > > > > + reg = <0x1c180c0 0x200>;
> > > > >
> > > > > Overlapping devices in the DTS is not ok.
> > > > >
> > > >
> > > > I do the same than arch/arm/boot/dts/berlin2.dtsi (sata@e9
> > > > phy@e900a0)
> > > >
> > > > But since it is not a good justification, it seems that regmap
> > > > is my
> > > > only solution ?
> > >
> > > I'm not even sure why you are moving the phy out of its original
> > > node
> > > (and driver).
> > >
> >
> > For using the phy-supply already handled by the code.
> > The other choice is to add another xxx-supply to ahci_platform.
> > Or to use hackily port_regulator for this regulator.
>
> The PHY registers are in the AHCI's "vendor specific registers"
> region. Following that are the per-port registers, which the ahci
> driver will need access to. This doesn't look like it should
> deserve a separate device node.
>
> What's wrong with handling the regulator directly in the ahci-sunxi
> PHY init code?
I remember I sent a patch that did this some times ago, and gets
rejected.
>
> ChenYu
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[linux-sunxi] Re: [PATCH v4 09/13] ARM: dts: sun8i: r40: add sata node
在 2018-08-31五的 19:10 +0800，Chen-Yu Tsai写道：
> On Fri, Aug 31, 2018 at 5:29 PM Corentin Labbe
> wrote:
> >
> > On Fri, Aug 31, 2018 at 03:58:34PM +0800, Chen-Yu Tsai wrote:
> > > On Fri, Aug 31, 2018 at 3:56 PM Corentin Labbe
> > > wrote:
> > > >
> > > > On Fri, Aug 31, 2018 at 09:35:00AM +0200, Maxime Ripard wrote:
> > > > > On Thu, Aug 30, 2018 at 09:01:16PM +0200, Corentin Labbe
> > > > > wrote:
> > > > > > R40 have a sata controller which is the same as A20.
> > > > > > This patch adds a DT node for it.
> > > > > >
> > > > > > Signed-off-by: Icenowy Zheng
> > > > > > Signed-off-by: Corentin Labbe
> > > > > > ---
> > > > > > arch/arm/boot/dts/sun8i-r40.dtsi | 23
> > > > > > +++
> > > > > > 1 file changed, 23 insertions(+)
> > > > > >
> > > > > > diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi
> > > > > > b/arch/arm/boot/dts/sun8i-r40.dtsi
> > > > > > index 852c2ccc3268..d6b5820da850 100644
> > > > > > --- a/arch/arm/boot/dts/sun8i-r40.dtsi
> > > > > > +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> > > > > > @@ -550,6 +550,29 @@
> > > > > > #size-cells = <0>;
> > > > > > };
> > > > > >
> > > > > > + ahci: sata@1c18000 {
> > > > > > + compatible = "allwinner,sun8i-r40-
> > > > > > ahci";
> > > > > > + reg = <0x01c18000 0x1000>;
> > > > > > + interrupts = > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + clocks = <&ccu CLK_BUS_SATA>, <&ccu
> > > > > > CLK_SATA>;
> > > > > > + resets = <&ccu RST_BUS_SATA>;
> > > > > > + resets-name = "ahci";
> > > > > > + #address-cells = <1>;
> > > > > > + #size-cells = <0>;
> > > > > > + status = "disabled";
> > > > > > +
> > > > > > + sata_port: sata-port@0 {
> > > > > > + reg = <0>;
> > > > > > + phys = <&sata_phy>;
> > > > > > + };
> > > > > > + };
> > > > > > +
> > > > > > + sata_phy: sata-phy@1c180c0 {
> > > > > > + compatible = "allwinner,sun8i-r40-sata-
> > > > > > phy";
> > > > > > + reg = <0x1c180c0 0x200>;
> > > > >
> > > > > Overlapping devices in the DTS is not ok.
> > > > >
> > > >
> > > > I do the same than arch/arm/boot/dts/berlin2.dtsi (sata@e9
> > > > phy@e900a0)
> > > > But since it is not a good justification, it seems that regmap
> > > > is my only solution ?
> > >
> > > Since you are effectively splitting one device node into two, you
> > > should
> > > adjust the original (ahci) device nodes register range.
> > >
> >
> > I cannot do that if I remove patch 13, iow If I keep phy init code
> > in both place as you requested.
>
> Then you need to split the phy handling between a10 and r40. A10
> doesn't
> need phy-supply at the moment anyway. And migrating A10 to newer
> binding
> is only causing you problems anyway. Just drop that part, and handle
> the
> R40.
>From the hardware perspective, they're the same. The A10/A20 has also
two dedicated VDD pins for SATA, although on boards they're usually
always on.
>
> ChenYu
>
> ___
> linux-arm-kernel mailing list
> linux-arm-ker...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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[linux-sunxi] Re: [PATCH v4 09/13] ARM: dts: sun8i: r40: add sata node
On Fri, Aug 31, 2018 at 07:31:37PM +0800, Chen-Yu Tsai wrote:
> On Fri, Aug 31, 2018 at 6:54 PM Corentin Labbe
> wrote:
> >
> > On Fri, Aug 31, 2018 at 12:20:21PM +0200, maxime.rip...@bootlin.com wrote:
> > > On Fri, Aug 31, 2018 at 09:56:31AM +0200, Corentin Labbe wrote:
> > > > On Fri, Aug 31, 2018 at 09:35:00AM +0200, Maxime Ripard wrote:
> > > > > On Thu, Aug 30, 2018 at 09:01:16PM +0200, Corentin Labbe wrote:
> > > > > > R40 have a sata controller which is the same as A20.
> > > > > > This patch adds a DT node for it.
> > > > > >
> > > > > > Signed-off-by: Icenowy Zheng
> > > > > > Signed-off-by: Corentin Labbe
> > > > > > ---
> > > > > > arch/arm/boot/dts/sun8i-r40.dtsi | 23 +++
> > > > > > 1 file changed, 23 insertions(+)
> > > > > >
> > > > > > diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi
> > > > > > b/arch/arm/boot/dts/sun8i-r40.dtsi
> > > > > > index 852c2ccc3268..d6b5820da850 100644
> > > > > > --- a/arch/arm/boot/dts/sun8i-r40.dtsi
> > > > > > +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> > > > > > @@ -550,6 +550,29 @@
> > > > > > #size-cells = <0>;
> > > > > > };
> > > > > >
> > > > > > + ahci: sata@1c18000 {
> > > > > > + compatible = "allwinner,sun8i-r40-ahci";
> > > > > > + reg = <0x01c18000 0x1000>;
> > > > > > + interrupts = > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + clocks = <&ccu CLK_BUS_SATA>, <&ccu
> > > > > > CLK_SATA>;
> > > > > > + resets = <&ccu RST_BUS_SATA>;
> > > > > > + resets-name = "ahci";
> > > > > > + #address-cells = <1>;
> > > > > > + #size-cells = <0>;
> > > > > > + status = "disabled";
> > > > > > +
> > > > > > + sata_port: sata-port@0 {
> > > > > > + reg = <0>;
> > > > > > + phys = <&sata_phy>;
> > > > > > + };
> > > > > > + };
> > > > > > +
> > > > > > + sata_phy: sata-phy@1c180c0 {
> > > > > > + compatible = "allwinner,sun8i-r40-sata-phy";
> > > > > > + reg = <0x1c180c0 0x200>;
> > > > >
> > > > > Overlapping devices in the DTS is not ok.
> > > > >
> > > >
> > > > I do the same than arch/arm/boot/dts/berlin2.dtsi (sata@e9
> > > > phy@e900a0)
> > > >
> > > > But since it is not a good justification, it seems that regmap is my
> > > > only solution ?
> > >
> > > I'm not even sure why you are moving the phy out of its original node
> > > (and driver).
> > >
> >
> > For using the phy-supply already handled by the code.
> > The other choice is to add another xxx-supply to ahci_platform.
> > Or to use hackily port_regulator for this regulator.
>
> The PHY registers are in the AHCI's "vendor specific registers"
> region. Following that are the per-port registers, which the ahci
> driver will need access to. This doesn't look like it should
> deserve a separate device node.
>
> What's wrong with handling the regulator directly in the ahci-sunxi
> PHY init code?
>
The reason are that I didnt wanted to use the port-regulator, and I didnt want
to add new code to ahci_platform.
I tried to place a phy-supply in the ahci node, but it doesnt work (with or
without a phy subnode).
Moving PHy code in a dedicated driver seemed to be good, but with all your
comments and Maxime's one, it seems not.
I will keep ahci_sunxi as-is and will try to found how to add the needed
phy-supply.
Regards
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[linux-sunxi] Re: [PATCH v3 20/30] iio: adc: sun4i-gpadc-iio: rework: device specific suspend & resume
On 31.08.2018 11:09, Maxime Ripard wrote: +static int sun4i_ths_suspend(struct sun4i_gpadc_iio *info) suspend is already a hook in the kernel, which hasn't the same meaning than runtime_suspend (and the same applies to resume), so we'd rather pick a better name. And all the functions (and the driver) use gpadc, please continue to use that prefix. I agree. For the newer sensors (from H3) the Sensor is referenced in the datasheets as Thermal Sensor short THS. So I would like to use for the newer sensors that prefix. Is that ok? Philipp -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH v3 21/30] iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor
On 31.08.2018 11:11, Maxime Ripard wrote: + regmap_write(info->regmap, SUN8I_H3_THS_CTRL0, + SUN4I_GPADC_CTRL0_T_ACQ(0xff)); + + regmap_write(info->regmap, SUN8I_H3_THS_CTRL2, + SUN8I_H3_THS_ACQ1(0x3f)); + + regmap_write(info->regmap, SUN8I_H3_THS_STAT, + SUN8I_H3_THS_INTS_TDATA_IRQ_0); + + regmap_write(info->regmap, SUN8I_H3_THS_FILTER, + SUN4I_GPADC_CTRL3_FILTER_EN | + SUN4I_GPADC_CTRL3_FILTER_TYPE(0x2)); + + regmap_write(info->regmap, SUN8I_H3_THS_INTC, + SUN8I_H3_THS_INTC_TDATA_IRQ_EN0 | + SUN8I_H3_THS_TEMP_PERIOD(0x55)); + + regmap_read(info->regmap, SUN8I_H3_THS_CTRL2, &value); + + regmap_write(info->regmap, SUN8I_H3_THS_CTRL2, + SUN8I_H3_THS_TEMP_SENSE_EN0 | value); Ideally, all these values should have a comment explaining what they are. And we really start to have a lot of registers defines. We'd be better off using regmap_fields. I will rework this in the next version. Thanks, Philipp -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] Re: [PATCH v3 21/30] iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor
On 31.08.2018 11:51, Icenowy Zheng wrote: Personally I suggest to leave out all SID or calibration related patches here. Currently we seems to be wrongly converting SID to big endian, however, the orgnization of the THS calibration data on H6 shows that it's surely little endian: It consists a temperature value in 1/10 celsuis as unit, and some thermal register readout values, which are the values read out at the given temperature, and every value here (the temperature and the readout) are all half word length. Let the temperature value be AABB, the two readout values be XXYY and ZZWW, the oragnization is: BB AA YY XX WW ZZ ** ** . When converting the SID to big endian, it becomes: XX YY AA BB ** ** ZZ WW , which is non-sense, and not able to do sub-word cell addressing. Maxime, should I drop the LE2BE conversion in SID driver? (I doubt whether it will break compatibility.) Philipp, could you delay to send any code that uses SID? Yes for sure! I will move the related patches to the end of the series and add a DO-NOT-MERGE flag in the title. So I can get those also ready/reviewed but not merged. Icenowy, do you know more about the A83T SID? From the general specs it could be the same like on the A64 or the H3. Thanks, Philipp -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH v4 09/13] ARM: dts: sun8i: r40: add sata node
On Fri, Aug 31, 2018 at 6:54 PM Corentin Labbe
wrote:
>
> On Fri, Aug 31, 2018 at 12:20:21PM +0200, maxime.rip...@bootlin.com wrote:
> > On Fri, Aug 31, 2018 at 09:56:31AM +0200, Corentin Labbe wrote:
> > > On Fri, Aug 31, 2018 at 09:35:00AM +0200, Maxime Ripard wrote:
> > > > On Thu, Aug 30, 2018 at 09:01:16PM +0200, Corentin Labbe wrote:
> > > > > R40 have a sata controller which is the same as A20.
> > > > > This patch adds a DT node for it.
> > > > >
> > > > > Signed-off-by: Icenowy Zheng
> > > > > Signed-off-by: Corentin Labbe
> > > > > ---
> > > > > arch/arm/boot/dts/sun8i-r40.dtsi | 23 +++
> > > > > 1 file changed, 23 insertions(+)
> > > > >
> > > > > diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi
> > > > > b/arch/arm/boot/dts/sun8i-r40.dtsi
> > > > > index 852c2ccc3268..d6b5820da850 100644
> > > > > --- a/arch/arm/boot/dts/sun8i-r40.dtsi
> > > > > +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> > > > > @@ -550,6 +550,29 @@
> > > > > #size-cells = <0>;
> > > > > };
> > > > >
> > > > > + ahci: sata@1c18000 {
> > > > > + compatible = "allwinner,sun8i-r40-ahci";
> > > > > + reg = <0x01c18000 0x1000>;
> > > > > + interrupts = ;
> > > > > + clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
> > > > > + resets = <&ccu RST_BUS_SATA>;
> > > > > + resets-name = "ahci";
> > > > > + #address-cells = <1>;
> > > > > + #size-cells = <0>;
> > > > > + status = "disabled";
> > > > > +
> > > > > + sata_port: sata-port@0 {
> > > > > + reg = <0>;
> > > > > + phys = <&sata_phy>;
> > > > > + };
> > > > > + };
> > > > > +
> > > > > + sata_phy: sata-phy@1c180c0 {
> > > > > + compatible = "allwinner,sun8i-r40-sata-phy";
> > > > > + reg = <0x1c180c0 0x200>;
> > > >
> > > > Overlapping devices in the DTS is not ok.
> > > >
> > >
> > > I do the same than arch/arm/boot/dts/berlin2.dtsi (sata@e9
> > > phy@e900a0)
> > >
> > > But since it is not a good justification, it seems that regmap is my
> > > only solution ?
> >
> > I'm not even sure why you are moving the phy out of its original node
> > (and driver).
> >
>
> For using the phy-supply already handled by the code.
> The other choice is to add another xxx-supply to ahci_platform.
> Or to use hackily port_regulator for this regulator.
The PHY registers are in the AHCI's "vendor specific registers"
region. Following that are the per-port registers, which the ahci
driver will need access to. This doesn't look like it should
deserve a separate device node.
What's wrong with handling the regulator directly in the ahci-sunxi
PHY init code?
ChenYu
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[linux-sunxi] Re: [PATCH v4 09/13] ARM: dts: sun8i: r40: add sata node
On Fri, Aug 31, 2018 at 5:29 PM Corentin Labbe
wrote:
>
> On Fri, Aug 31, 2018 at 03:58:34PM +0800, Chen-Yu Tsai wrote:
> > On Fri, Aug 31, 2018 at 3:56 PM Corentin Labbe
> > wrote:
> > >
> > > On Fri, Aug 31, 2018 at 09:35:00AM +0200, Maxime Ripard wrote:
> > > > On Thu, Aug 30, 2018 at 09:01:16PM +0200, Corentin Labbe wrote:
> > > > > R40 have a sata controller which is the same as A20.
> > > > > This patch adds a DT node for it.
> > > > >
> > > > > Signed-off-by: Icenowy Zheng
> > > > > Signed-off-by: Corentin Labbe
> > > > > ---
> > > > > arch/arm/boot/dts/sun8i-r40.dtsi | 23 +++
> > > > > 1 file changed, 23 insertions(+)
> > > > >
> > > > > diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi
> > > > > b/arch/arm/boot/dts/sun8i-r40.dtsi
> > > > > index 852c2ccc3268..d6b5820da850 100644
> > > > > --- a/arch/arm/boot/dts/sun8i-r40.dtsi
> > > > > +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> > > > > @@ -550,6 +550,29 @@
> > > > > #size-cells = <0>;
> > > > > };
> > > > >
> > > > > + ahci: sata@1c18000 {
> > > > > + compatible = "allwinner,sun8i-r40-ahci";
> > > > > + reg = <0x01c18000 0x1000>;
> > > > > + interrupts = ;
> > > > > + clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
> > > > > + resets = <&ccu RST_BUS_SATA>;
> > > > > + resets-name = "ahci";
> > > > > + #address-cells = <1>;
> > > > > + #size-cells = <0>;
> > > > > + status = "disabled";
> > > > > +
> > > > > + sata_port: sata-port@0 {
> > > > > + reg = <0>;
> > > > > + phys = <&sata_phy>;
> > > > > + };
> > > > > + };
> > > > > +
> > > > > + sata_phy: sata-phy@1c180c0 {
> > > > > + compatible = "allwinner,sun8i-r40-sata-phy";
> > > > > + reg = <0x1c180c0 0x200>;
> > > >
> > > > Overlapping devices in the DTS is not ok.
> > > >
> > >
> > > I do the same than arch/arm/boot/dts/berlin2.dtsi (sata@e9 phy@e900a0)
> > > But since it is not a good justification, it seems that regmap is my only
> > > solution ?
> >
> > Since you are effectively splitting one device node into two, you should
> > adjust the original (ahci) device nodes register range.
> >
>
> I cannot do that if I remove patch 13, iow If I keep phy init code in both
> place as you requested.
Then you need to split the phy handling between a10 and r40. A10 doesn't
need phy-supply at the moment anyway. And migrating A10 to newer binding
is only causing you problems anyway. Just drop that part, and handle the
R40.
ChenYu
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[linux-sunxi] Re: [PATCH v4 09/13] ARM: dts: sun8i: r40: add sata node
On Fri, Aug 31, 2018 at 12:20:21PM +0200, maxime.rip...@bootlin.com wrote:
> On Fri, Aug 31, 2018 at 09:56:31AM +0200, Corentin Labbe wrote:
> > On Fri, Aug 31, 2018 at 09:35:00AM +0200, Maxime Ripard wrote:
> > > On Thu, Aug 30, 2018 at 09:01:16PM +0200, Corentin Labbe wrote:
> > > > R40 have a sata controller which is the same as A20.
> > > > This patch adds a DT node for it.
> > > >
> > > > Signed-off-by: Icenowy Zheng
> > > > Signed-off-by: Corentin Labbe
> > > > ---
> > > > arch/arm/boot/dts/sun8i-r40.dtsi | 23 +++
> > > > 1 file changed, 23 insertions(+)
> > > >
> > > > diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi
> > > > b/arch/arm/boot/dts/sun8i-r40.dtsi
> > > > index 852c2ccc3268..d6b5820da850 100644
> > > > --- a/arch/arm/boot/dts/sun8i-r40.dtsi
> > > > +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> > > > @@ -550,6 +550,29 @@
> > > > #size-cells = <0>;
> > > > };
> > > >
> > > > + ahci: sata@1c18000 {
> > > > + compatible = "allwinner,sun8i-r40-ahci";
> > > > + reg = <0x01c18000 0x1000>;
> > > > + interrupts = ;
> > > > + clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
> > > > + resets = <&ccu RST_BUS_SATA>;
> > > > + resets-name = "ahci";
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > + status = "disabled";
> > > > +
> > > > + sata_port: sata-port@0 {
> > > > + reg = <0>;
> > > > + phys = <&sata_phy>;
> > > > + };
> > > > + };
> > > > +
> > > > + sata_phy: sata-phy@1c180c0 {
> > > > + compatible = "allwinner,sun8i-r40-sata-phy";
> > > > + reg = <0x1c180c0 0x200>;
> > >
> > > Overlapping devices in the DTS is not ok.
> > >
> >
> > I do the same than arch/arm/boot/dts/berlin2.dtsi (sata@e9
> > phy@e900a0)
> >
> > But since it is not a good justification, it seems that regmap is my
> > only solution ?
>
> I'm not even sure why you are moving the phy out of its original node
> (and driver).
>
For using the phy-supply already handled by the code.
The other choice is to add another xxx-supply to ahci_platform.
Or to use hackily port_regulator for this regulator.
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[linux-sunxi] Re: [PATCH v4 12/13] ARM: dts: sun4i: a10: add sata-port/sata-phy nodes
On Fri, Aug 31, 2018 at 09:53:50AM +0200, Corentin Labbe wrote:
> On Fri, Aug 31, 2018 at 09:37:24AM +0200, Maxime Ripard wrote:
> > On Thu, Aug 30, 2018 at 09:01:19PM +0200, Corentin Labbe wrote:
> > > This patch convert sun4i-a10 sata to the new binding which use a sata
> > > phy node.
> > >
> > > Signed-off-by: Corentin Labbe
> > > ---
> > > arch/arm/boot/dts/sun4i-a10.dtsi | 13 +
> > > 1 file changed, 13 insertions(+)
> > >
> > > diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi
> > > b/arch/arm/boot/dts/sun4i-a10.dtsi
> > > index 3d62a8950720..52d5c2e79499 100644
> > > --- a/arch/arm/boot/dts/sun4i-a10.dtsi
> > > +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
> > > @@ -556,7 +556,20 @@
> > > reg = <0x01c18000 0x1000>;
> > > interrupts = <56>;
> > > clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > status = "disabled";
> > > +
> > > + sata_port: sata-port@0 {
> > > + reg = <0>;
> > > + phys = <&sata_phy>;
> > > + };
> > > + };
> > > +
> > > + sata_phy: sata_phy@1c180c0 {
> > > + compatible = "allwinner,sun4i-a10-sata-phy";
> > > + reg = <0x01c180c0 0x200>;
> > > + #phy-cells = <0>;
> > > };
> >
> > This patch, together with the following one, breaks the DT ABI, this
> > isn't something we can do anymore.
>
> So what can I do ?
Well, you always have the option of not doing anything.
Maxime
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[linux-sunxi] Re: [PATCH v4 09/13] ARM: dts: sun8i: r40: add sata node
On Fri, Aug 31, 2018 at 09:56:31AM +0200, Corentin Labbe wrote:
> On Fri, Aug 31, 2018 at 09:35:00AM +0200, Maxime Ripard wrote:
> > On Thu, Aug 30, 2018 at 09:01:16PM +0200, Corentin Labbe wrote:
> > > R40 have a sata controller which is the same as A20.
> > > This patch adds a DT node for it.
> > >
> > > Signed-off-by: Icenowy Zheng
> > > Signed-off-by: Corentin Labbe
> > > ---
> > > arch/arm/boot/dts/sun8i-r40.dtsi | 23 +++
> > > 1 file changed, 23 insertions(+)
> > >
> > > diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi
> > > b/arch/arm/boot/dts/sun8i-r40.dtsi
> > > index 852c2ccc3268..d6b5820da850 100644
> > > --- a/arch/arm/boot/dts/sun8i-r40.dtsi
> > > +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> > > @@ -550,6 +550,29 @@
> > > #size-cells = <0>;
> > > };
> > >
> > > + ahci: sata@1c18000 {
> > > + compatible = "allwinner,sun8i-r40-ahci";
> > > + reg = <0x01c18000 0x1000>;
> > > + interrupts = ;
> > > + clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
> > > + resets = <&ccu RST_BUS_SATA>;
> > > + resets-name = "ahci";
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + status = "disabled";
> > > +
> > > + sata_port: sata-port@0 {
> > > + reg = <0>;
> > > + phys = <&sata_phy>;
> > > + };
> > > + };
> > > +
> > > + sata_phy: sata-phy@1c180c0 {
> > > + compatible = "allwinner,sun8i-r40-sata-phy";
> > > + reg = <0x1c180c0 0x200>;
> >
> > Overlapping devices in the DTS is not ok.
> >
>
> I do the same than arch/arm/boot/dts/berlin2.dtsi (sata@e9
> phy@e900a0)
>
> But since it is not a good justification, it seems that regmap is my
> only solution ?
I'm not even sure why you are moving the phy out of its original node
(and driver).
Maxime
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[linux-sunxi] Re: [PATCH 0/3] arm64: dts: allwinner: h5: Add device tree for Bananapi M2 Plus H5
On Thu, Aug 30, 2018 at 04:09:23PM +0800, Chen-Yu Tsai wrote: > Hi, > > Allwinner's H5 SoC is pin compatible with the H3 SoC. As such, some > vendors produce H3 and H5 variants for the same device. Such is the > case with Libre Computer's ALL-H3-CC, and the Bananapi M2 Plus. > > This series follows that of the ALL-H3-CC, splitting out a common > board dtsi, and then two SoC-specific dts files that include the > SoC level and common board dtsi's, as well as putting in the board > name. The first patch is a minor fix that I think should be done > before the migration. > > Please have a look. Acked-by: Maxime Ripard > Also, on a related matter, Bananapi recently released revision v1.2 > of the M2 Plus. The original commercially available version was v1.1. > v1.2 adds a GPIO control that can change the CPU cores' supply voltage > between 1.1V and 1.3V. Do we want two extra dts files for this? Put > them in the existing dts files regardless? Or let people handle this > via overlays? If that the sole change, I'd be inclined to merge it as a separate DT for that particular version. Is there any way to detect it at runtime? Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
[linux-sunxi] Re: [PATCH v3 21/30] iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor
在 2018-08-31五的 11:11 +0200，Maxime Ripard写道：
> On Thu, Aug 30, 2018 at 05:45:09PM +0200, Philipp Rossak wrote:
> > This patch adds support for the H3 ths sensor.
> >
> > The H3 supports interrupts. The interrupt is configured to update
> > the
> > the sensor values every second. The calibration data is writen at
> > the
> > begin of the init process.
> >
> > Signed-off-by: Philipp Rossak
> > ---
> > drivers/iio/adc/sun4i-gpadc-iio.c | 91
> > +
> > include/linux/iio/adc/sun4i-gpadc.h | 18
> > 2 files changed, 109 insertions(+)
> >
> > diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
> > b/drivers/iio/adc/sun4i-gpadc-iio.c
> > index c7b46c82e3e5..d5c7971b2558 100644
> > --- a/drivers/iio/adc/sun4i-gpadc-iio.c
> > +++ b/drivers/iio/adc/sun4i-gpadc-iio.c
> > @@ -72,6 +72,7 @@ struct gpadc_data {
> > u32 temp_data_base;
> > int sensor_count;
> > boolsupports_nvmem;
> > + u32 ths_irq_clear;
> > };
> >
> > static irqreturn_t sun4i_gpadc_data_irq_handler(int irq, void
> > *dev_id);
> > @@ -79,6 +80,10 @@ static irqreturn_t
> > sun4i_gpadc_data_irq_handler(int irq, void *dev_id);
> > static int sun4i_ths_resume(struct sun4i_gpadc_iio *info);
> > static int sun4i_ths_suspend(struct sun4i_gpadc_iio *info);
> >
> > +static int sun8i_h3_ths_resume(struct sun4i_gpadc_iio *info);
> > +static int sun8i_h3_ths_suspend(struct sun4i_gpadc_iio *info);
> > +static irqreturn_t sunx8i_h3_irq_thread(int irq, void *data);
> > +
> > static const struct gpadc_data sun4i_gpadc_data = {
> > .temp_offset = -1932,
> > .temp_scale = 133,
> > @@ -137,6 +142,22 @@ static const struct gpadc_data
> > sun8i_a33_gpadc_data = {
> > .sensor_count = 1,
> > };
> >
> > +static const struct gpadc_data sun8i_h3_ths_data = {
> > + .temp_offset = -1791,
> > + .temp_scale = -121,
> > + .temp_data_base = SUN8I_H3_THS_TDATA0,
> > + .ths_irq_thread = sunx8i_h3_irq_thread,
> > + .support_irq = true,
> > + .has_bus_clk = true,
> > + .has_bus_rst = true,
> > + .has_mod_clk = true,
> > + .sensor_count = 1,
> > + .supports_nvmem = true,
> > + .ths_resume = sun8i_h3_ths_resume,
> > + .ths_suspend = sun8i_h3_ths_suspend,
> > + .ths_irq_clear = SUN8I_H3_THS_INTS_TDATA_IRQ_0,
> > +};
> > +
> > struct sun4i_sensor_tzd {
> > struct sun4i_gpadc_iio *info;
> > struct thermal_zone_device *tzd;
> > @@ -409,6 +430,31 @@ static irqreturn_t
> > sun4i_gpadc_data_irq_handler(int irq, void *dev_id)
> > return IRQ_HANDLED;
> > }
> >
> > +static irqreturn_t sunx8i_h3_irq_thread(int irq, void *data)
> > +{
> > + struct sun4i_gpadc_iio *info = data;
> > + int i;
> > +
> > + regmap_write(info->regmap, SUN8I_H3_THS_STAT,
> > + info->data->ths_irq_clear);
> > +
> > + for (i = 0; i < info->data->sensor_count; i++)
> > + thermal_zone_device_update(info->tzds[i].tzd,
> > + THERMAL_EVENT_TEMP_SAMP
> > LE);
> > +
> > + return IRQ_HANDLED;
> > +}
> > +
> > +static int sun8i_h3_calibrate(struct sun4i_gpadc_iio *info)
> > +{
> > +// regmap_write(info->regmap, SUNXI_THS_CDATA_0_1,
> > +// info->calibration_data[0]);
> > +// regmap_write(info->regmap, SUNXI_THS_CDATA_2_3,
> > +// info->calibration_data[1]);
>
> Don't put commented code.
Personally I suggest to leave out all SID or calibration related
patches here.
Currently we seems to be wrongly converting SID to big endian, however,
the orgnization of the THS calibration data on H6 shows that it's
surely little endian:
It consists a temperature value in 1/10 celsuis as unit, and some
thermal register readout values, which are the values read out at the
given temperature, and every value here (the temperature and the
readout) are all half word length.
Let the temperature value be AABB, the two readout values be XXYY and
ZZWW, the oragnization is:
BB AA YY XX WW ZZ ** ** .
When converting the SID to big endian, it becomes:
XX YY AA BB ** ** ZZ WW ,
which is non-sense, and not able to do sub-word cell addressing.
Maxime, should I drop the LE2BE conversion in SID driver? (I doubt
whether it will break compatibility.)
Philipp, could you delay to send any code that uses SID?
>
> > +
> > + return 0;
> > +}
> > +
> > static int sun4i_gpadc_runtime_suspend(struct device *dev)
> > {
> > struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
> > @@ -428,6 +474,16 @@ static int sun4i_ths_suspend(struct
> > sun4i_gpadc_iio *info)
> > return 0;
> > }
> >
> > +static int sun8i_h3_ths_suspend(struct sun4i_gpadc_iio *info)
> > +{
> > + /* Disable ths interrupt */
> > + regmap_write(info->regmap, SUN8I_H3_THS_INTC, 0x0);
> > + /* Disable temperature sensor */
> > + regmap_write(info->regmap, SUN8I_H3_THS_CTRL2, 0x0);
> > +
> > + return 0;
> > +}
> > +
> > static int sun4i_gpadc_runtime_resume(struct device *dev)
> >
[linux-sunxi] Re: [PATCH v4 09/13] ARM: dts: sun8i: r40: add sata node
On Fri, Aug 31, 2018 at 03:58:34PM +0800, Chen-Yu Tsai wrote:
> On Fri, Aug 31, 2018 at 3:56 PM Corentin Labbe
> wrote:
> >
> > On Fri, Aug 31, 2018 at 09:35:00AM +0200, Maxime Ripard wrote:
> > > On Thu, Aug 30, 2018 at 09:01:16PM +0200, Corentin Labbe wrote:
> > > > R40 have a sata controller which is the same as A20.
> > > > This patch adds a DT node for it.
> > > >
> > > > Signed-off-by: Icenowy Zheng
> > > > Signed-off-by: Corentin Labbe
> > > > ---
> > > > arch/arm/boot/dts/sun8i-r40.dtsi | 23 +++
> > > > 1 file changed, 23 insertions(+)
> > > >
> > > > diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi
> > > > b/arch/arm/boot/dts/sun8i-r40.dtsi
> > > > index 852c2ccc3268..d6b5820da850 100644
> > > > --- a/arch/arm/boot/dts/sun8i-r40.dtsi
> > > > +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> > > > @@ -550,6 +550,29 @@
> > > > #size-cells = <0>;
> > > > };
> > > >
> > > > + ahci: sata@1c18000 {
> > > > + compatible = "allwinner,sun8i-r40-ahci";
> > > > + reg = <0x01c18000 0x1000>;
> > > > + interrupts = ;
> > > > + clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
> > > > + resets = <&ccu RST_BUS_SATA>;
> > > > + resets-name = "ahci";
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > + status = "disabled";
> > > > +
> > > > + sata_port: sata-port@0 {
> > > > + reg = <0>;
> > > > + phys = <&sata_phy>;
> > > > + };
> > > > + };
> > > > +
> > > > + sata_phy: sata-phy@1c180c0 {
> > > > + compatible = "allwinner,sun8i-r40-sata-phy";
> > > > + reg = <0x1c180c0 0x200>;
> > >
> > > Overlapping devices in the DTS is not ok.
> > >
> >
> > I do the same than arch/arm/boot/dts/berlin2.dtsi (sata@e9 phy@e900a0)
> > But since it is not a good justification, it seems that regmap is my only
> > solution ?
>
> Since you are effectively splitting one device node into two, you should
> adjust the original (ahci) device nodes register range.
>
I cannot do that if I remove patch 13, iow If I keep phy init code in both
place as you requested.
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[linux-sunxi] Re: [PATCH v3 25/30] ARM: dts: sun8i: h3: add thermal zone to H3
On Thu, Aug 30, 2018 at 05:45:13PM +0200, Philipp Rossak wrote:
> This patch adds the thermal zones to the H3. We have only one sensor and
> that is placed in the cpu.
>
> Signed-off-by: Philipp Rossak
> ---
> arch/arm/boot/dts/sun8i-h3.dtsi| 31 +++
> arch/arm/boot/dts/sunxi-h3-h5.dtsi | 1 +
> 2 files changed, 32 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
> index 5b7994cb1471..954848d5df50 100644
> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> @@ -78,6 +78,8 @@
> clock-names = "cpu";
> operating-points-v2 = <&cpu0_opp_table>;
> #cooling-cells = <2>;
> + cooling-min-level = <0>;
> + cooling-max-level = <15>;
> };
>
> cpu@1 {
> @@ -102,6 +104,35 @@
> };
> };
>
> + thermal-zones {
> + cpu-thermal {
> + /* milliseconds */
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> + thermal-sensors = <&ths>;
> +
> + trips {
> + cpu_hot_trip: cpu-warm {
> + temperature = <65000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> + cpu_very_hot_trip: cpu-very-hot {
> + temperature = <9>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
Where are those trip points coming from?
Maxime
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[linux-sunxi] Re: [PATCH v3 21/30] iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor
On Thu, Aug 30, 2018 at 05:45:09PM +0200, Philipp Rossak wrote:
> This patch adds support for the H3 ths sensor.
>
> The H3 supports interrupts. The interrupt is configured to update the
> the sensor values every second. The calibration data is writen at the
> begin of the init process.
>
> Signed-off-by: Philipp Rossak
> ---
> drivers/iio/adc/sun4i-gpadc-iio.c | 91
> +
> include/linux/iio/adc/sun4i-gpadc.h | 18
> 2 files changed, 109 insertions(+)
>
> diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
> b/drivers/iio/adc/sun4i-gpadc-iio.c
> index c7b46c82e3e5..d5c7971b2558 100644
> --- a/drivers/iio/adc/sun4i-gpadc-iio.c
> +++ b/drivers/iio/adc/sun4i-gpadc-iio.c
> @@ -72,6 +72,7 @@ struct gpadc_data {
> u32 temp_data_base;
> int sensor_count;
> boolsupports_nvmem;
> + u32 ths_irq_clear;
> };
>
> static irqreturn_t sun4i_gpadc_data_irq_handler(int irq, void *dev_id);
> @@ -79,6 +80,10 @@ static irqreturn_t sun4i_gpadc_data_irq_handler(int irq,
> void *dev_id);
> static int sun4i_ths_resume(struct sun4i_gpadc_iio *info);
> static int sun4i_ths_suspend(struct sun4i_gpadc_iio *info);
>
> +static int sun8i_h3_ths_resume(struct sun4i_gpadc_iio *info);
> +static int sun8i_h3_ths_suspend(struct sun4i_gpadc_iio *info);
> +static irqreturn_t sunx8i_h3_irq_thread(int irq, void *data);
> +
> static const struct gpadc_data sun4i_gpadc_data = {
> .temp_offset = -1932,
> .temp_scale = 133,
> @@ -137,6 +142,22 @@ static const struct gpadc_data sun8i_a33_gpadc_data = {
> .sensor_count = 1,
> };
>
> +static const struct gpadc_data sun8i_h3_ths_data = {
> + .temp_offset = -1791,
> + .temp_scale = -121,
> + .temp_data_base = SUN8I_H3_THS_TDATA0,
> + .ths_irq_thread = sunx8i_h3_irq_thread,
> + .support_irq = true,
> + .has_bus_clk = true,
> + .has_bus_rst = true,
> + .has_mod_clk = true,
> + .sensor_count = 1,
> + .supports_nvmem = true,
> + .ths_resume = sun8i_h3_ths_resume,
> + .ths_suspend = sun8i_h3_ths_suspend,
> + .ths_irq_clear = SUN8I_H3_THS_INTS_TDATA_IRQ_0,
> +};
> +
> struct sun4i_sensor_tzd {
> struct sun4i_gpadc_iio *info;
> struct thermal_zone_device *tzd;
> @@ -409,6 +430,31 @@ static irqreturn_t sun4i_gpadc_data_irq_handler(int irq,
> void *dev_id)
> return IRQ_HANDLED;
> }
>
> +static irqreturn_t sunx8i_h3_irq_thread(int irq, void *data)
> +{
> + struct sun4i_gpadc_iio *info = data;
> + int i;
> +
> + regmap_write(info->regmap, SUN8I_H3_THS_STAT,
> + info->data->ths_irq_clear);
> +
> + for (i = 0; i < info->data->sensor_count; i++)
> + thermal_zone_device_update(info->tzds[i].tzd,
> + THERMAL_EVENT_TEMP_SAMPLE);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static int sun8i_h3_calibrate(struct sun4i_gpadc_iio *info)
> +{
> +// regmap_write(info->regmap, SUNXI_THS_CDATA_0_1,
> +// info->calibration_data[0]);
> +// regmap_write(info->regmap, SUNXI_THS_CDATA_2_3,
> +// info->calibration_data[1]);
Don't put commented code.
> +
> + return 0;
> +}
> +
> static int sun4i_gpadc_runtime_suspend(struct device *dev)
> {
> struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
> @@ -428,6 +474,16 @@ static int sun4i_ths_suspend(struct sun4i_gpadc_iio
> *info)
> return 0;
> }
>
> +static int sun8i_h3_ths_suspend(struct sun4i_gpadc_iio *info)
> +{
> + /* Disable ths interrupt */
> + regmap_write(info->regmap, SUN8I_H3_THS_INTC, 0x0);
> + /* Disable temperature sensor */
> + regmap_write(info->regmap, SUN8I_H3_THS_CTRL2, 0x0);
> +
> + return 0;
> +}
> +
> static int sun4i_gpadc_runtime_resume(struct device *dev)
> {
> struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
> @@ -454,6 +510,37 @@ static int sun4i_ths_resume(struct sun4i_gpadc_iio *info)
> return 0;
> }
>
> +static int sun8i_h3_ths_resume(struct sun4i_gpadc_iio *info)
> +{
> + u32 value;
> +
> + sun8i_h3_calibrate(info);
> +
> + regmap_write(info->regmap, SUN8I_H3_THS_CTRL0,
> + SUN4I_GPADC_CTRL0_T_ACQ(0xff));
> +
> + regmap_write(info->regmap, SUN8I_H3_THS_CTRL2,
> + SUN8I_H3_THS_ACQ1(0x3f));
> +
> + regmap_write(info->regmap, SUN8I_H3_THS_STAT,
> + SUN8I_H3_THS_INTS_TDATA_IRQ_0);
> +
> + regmap_write(info->regmap, SUN8I_H3_THS_FILTER,
> + SUN4I_GPADC_CTRL3_FILTER_EN |
> + SUN4I_GPADC_CTRL3_FILTER_TYPE(0x2));
> +
> + regmap_write(info->regmap, SUN8I_H3_THS_INTC,
> + SUN8I_H3_THS_INTC_TDATA_IRQ_EN0 |
> + SUN8I_H3_THS_TEMP_PERIOD(0x55));
> +
> + regmap_read(info->regmap, SUN8I_H3_THS_CTRL2, &value);
> +
> + regmap_write(info->regmap, SUN8I_H3_THS_C
[linux-sunxi] Re: [PATCH v3 20/30] iio: adc: sun4i-gpadc-iio: rework: device specific suspend & resume
On Thu, Aug 30, 2018 at 05:45:08PM +0200, Philipp Rossak wrote:
> Different sensors will have different suspend and resume functions. So
> we are modularize the suspend and resume functions.
>
> The resume function configures and initializes the thermal sensor and
> the suspend function disables the sensors.
>
> Signed-off-by: Philipp Rossak
> ---
> drivers/iio/adc/sun4i-gpadc-iio.c | 20
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
> b/drivers/iio/adc/sun4i-gpadc-iio.c
> index 2fd73d143815..c7b46c82e3e5 100644
> --- a/drivers/iio/adc/sun4i-gpadc-iio.c
> +++ b/drivers/iio/adc/sun4i-gpadc-iio.c
> @@ -76,6 +76,9 @@ struct gpadc_data {
>
> static irqreturn_t sun4i_gpadc_data_irq_handler(int irq, void *dev_id);
>
> +static int sun4i_ths_resume(struct sun4i_gpadc_iio *info);
> +static int sun4i_ths_suspend(struct sun4i_gpadc_iio *info);
> +
> static const struct gpadc_data sun4i_gpadc_data = {
> .temp_offset = -1932,
> .temp_scale = 133,
> @@ -87,6 +90,8 @@ static const struct gpadc_data sun4i_gpadc_data = {
> .ths_irq_thread = sun4i_gpadc_data_irq_handler,
> .support_irq = true,
> .temp_data_base = SUN4I_GPADC_TEMP_DATA,
> + .ths_resume = sun4i_ths_resume,
> + .ths_suspend = sun4i_ths_suspend,
> .sensor_count = 1,
> };
>
> @@ -101,6 +106,8 @@ static const struct gpadc_data sun5i_gpadc_data = {
> .ths_irq_thread = sun4i_gpadc_data_irq_handler,
> .support_irq = true,
> .temp_data_base = SUN4I_GPADC_TEMP_DATA,
> + .ths_resume = sun4i_ths_resume,
> + .ths_suspend = sun4i_ths_suspend,
> .sensor_count = 1,
> };
>
> @@ -115,6 +122,8 @@ static const struct gpadc_data sun6i_gpadc_data = {
> .ths_irq_thread = sun4i_gpadc_data_irq_handler,
> .support_irq = true,
> .temp_data_base = SUN4I_GPADC_TEMP_DATA,
> + .ths_resume = sun4i_ths_resume,
> + .ths_suspend = sun4i_ths_suspend,
> .sensor_count = 1,
> };
>
> @@ -123,6 +132,8 @@ static const struct gpadc_data sun8i_a33_gpadc_data = {
> .temp_scale = 162,
> .tp_mode_en = SUN8I_A33_GPADC_CTRL1_CHOP_TEMP_EN,
> .temp_data_base = SUN4I_GPADC_TEMP_DATA,
> + .ths_resume = sun4i_ths_resume,
> + .ths_suspend = sun4i_ths_suspend,
> .sensor_count = 1,
> };
>
> @@ -401,6 +412,11 @@ static irqreturn_t sun4i_gpadc_data_irq_handler(int irq,
> void *dev_id)
> static int sun4i_gpadc_runtime_suspend(struct device *dev)
> {
> struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
> + return info->data->ths_suspend(info);
> +}
> +
> +static int sun4i_ths_suspend(struct sun4i_gpadc_iio *info)
suspend is already a hook in the kernel, which hasn't the same meaning
than runtime_suspend (and the same applies to resume), so we'd rather
pick a better name. And all the functions (and the driver) use gpadc,
please continue to use that prefix.
Maxime
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[linux-sunxi] Re: [PATCH v3 19/30] iio: adc: sun4i-gpadc-iio: rework: support nvmem calibration data
On Thu, Aug 30, 2018 at 05:45:07PM +0200, Philipp Rossak wrote:
> This patch reworks the driver to support nvmem calibration cells.
> The driver checks if the nvmem calibration is supported and reads out
> the nvmem.
>
> Signed-off-by: Philipp Rossak
> ---
> drivers/iio/adc/sun4i-gpadc-iio.c | 24
> 1 file changed, 24 insertions(+)
>
> diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
> b/drivers/iio/adc/sun4i-gpadc-iio.c
> index 18ab72e52d78..2fd73d143815 100644
> --- a/drivers/iio/adc/sun4i-gpadc-iio.c
> +++ b/drivers/iio/adc/sun4i-gpadc-iio.c
> @@ -27,6 +27,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -70,6 +71,7 @@ struct gpadc_data {
> boolhas_mod_clk;
> u32 temp_data_base;
> int sensor_count;
> + boolsupports_nvmem;
> };
>
> static irqreturn_t sun4i_gpadc_data_irq_handler(int irq, void *dev_id);
> @@ -146,6 +148,7 @@ struct sun4i_gpadc_iio {
> struct clk *bus_clk;
> struct clk *mod_clk;
> struct reset_control*reset;
> + u32 calibration_data[2];
> };
>
> static const struct iio_chan_spec sun4i_gpadc_channels[] = {
> @@ -484,6 +487,9 @@ static int sun4i_gpadc_probe_dt(struct platform_device
> *pdev,
> struct resource *mem;
> void __iomem *base;
> int ret;
> + struct nvmem_cell *cell;
> + ssize_t cell_size;
> + u32 *cell_data;
>
> info->data = of_device_get_match_data(&pdev->dev);
> if (!info->data)
> @@ -494,6 +500,24 @@ static int sun4i_gpadc_probe_dt(struct platform_device
> *pdev,
> if (IS_ERR(base))
> return PTR_ERR(base);
>
> + if (info->data->supports_nvmem) {
> +
> + cell = nvmem_cell_get(&pdev->dev, "calibration");
> + if (IS_ERR(cell)) {
> + if (PTR_ERR(cell) == -EPROBE_DEFER)
> + return PTR_ERR(cell);
You're masking real errors here, if the issue isn't that the property
isn't found.
> + } else {
> + cell_data = (u32 *)nvmem_cell_read(cell, &cell_size);
> + if (cell_size != 8)
> + dev_err(&pdev->dev,
> + "Calibration data has wrong size\n");
> + else {
> + info->calibration_data[0] = cell_data[0];
> + info->calibration_data[1] = cell_data[1];
How are those calibration data organized when there is multiple channels?
Maxime
--
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[linux-sunxi] Re: [PATCH v3 18/30] iio: adc: sun4i-gpadc-iio: rework: support multiple sensors
On Thu, Aug 30, 2018 at 05:45:06PM +0200, Philipp Rossak wrote:
> For adding newer sensor some basic rework of the code is necessary.
>
> This patch reworks the driver to be able to handle more than one
> thermal sensor. Newer SoC like the A80 have 4 thermal sensors.
> Because of this the maximal sensor count value was set to 4.
>
> The sensor_id value is set during sensor registration and is for each
> registered sensor indiviual. This makes it able to differntiate the
> sensors when the value is read from the register.
>
> In function sun4i_gpadc_read_raw(), the sensor number of the ths sensor
> was directly set to 0 (sun4i_gpadc_temp_read(x,x,0)). This selects
> in the temp_read function automatically sensor 0. A check for the
> sensor_id is here not required since the old sensors only have one
> thermal sensor. In addition to that is the sun4i_gpadc_read_raw()
> function only used by the "older" sensors (before A33) where the
> thermal sensor was a cobination of an adc and a thermal sensor.
>
> Signed-off-by: Philipp Rossak
> ---
> drivers/iio/adc/sun4i-gpadc-iio.c | 63
> +
> include/linux/iio/adc/sun4i-gpadc.h | 3 ++
> 2 files changed, 46 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
> b/drivers/iio/adc/sun4i-gpadc-iio.c
> index c12de48c4e86..18ab72e52d78 100644
> --- a/drivers/iio/adc/sun4i-gpadc-iio.c
> +++ b/drivers/iio/adc/sun4i-gpadc-iio.c
> @@ -69,6 +69,7 @@ struct gpadc_data {
> boolhas_bus_rst;
> boolhas_mod_clk;
> u32 temp_data_base;
> + int sensor_count;
> };
>
> static irqreturn_t sun4i_gpadc_data_irq_handler(int irq, void *dev_id);
> @@ -84,6 +85,7 @@ static const struct gpadc_data sun4i_gpadc_data = {
> .ths_irq_thread = sun4i_gpadc_data_irq_handler,
> .support_irq = true,
> .temp_data_base = SUN4I_GPADC_TEMP_DATA,
> + .sensor_count = 1,
> };
>
> static const struct gpadc_data sun5i_gpadc_data = {
> @@ -97,6 +99,7 @@ static const struct gpadc_data sun5i_gpadc_data = {
> .ths_irq_thread = sun4i_gpadc_data_irq_handler,
> .support_irq = true,
> .temp_data_base = SUN4I_GPADC_TEMP_DATA,
> + .sensor_count = 1,
> };
>
> static const struct gpadc_data sun6i_gpadc_data = {
> @@ -110,6 +113,7 @@ static const struct gpadc_data sun6i_gpadc_data = {
> .ths_irq_thread = sun4i_gpadc_data_irq_handler,
> .support_irq = true,
> .temp_data_base = SUN4I_GPADC_TEMP_DATA,
> + .sensor_count = 1,
> };
>
> static const struct gpadc_data sun8i_a33_gpadc_data = {
> @@ -117,6 +121,13 @@ static const struct gpadc_data sun8i_a33_gpadc_data = {
> .temp_scale = 162,
> .tp_mode_en = SUN8I_A33_GPADC_CTRL1_CHOP_TEMP_EN,
> .temp_data_base = SUN4I_GPADC_TEMP_DATA,
> + .sensor_count = 1,
> +};
> +
> +struct sun4i_sensor_tzd {
> + struct sun4i_gpadc_iio *info;
> + struct thermal_zone_device *tzd;
> + unsigned intsensor_id;
> };
>
> struct sun4i_gpadc_iio {
> @@ -130,7 +141,7 @@ struct sun4i_gpadc_iio {
> const struct gpadc_data *data;
> /* prevents concurrent reads of temperature and ADC */
> struct mutexmutex;
> - struct thermal_zone_device *tzd;
> + struct sun4i_sensor_tzd tzds[MAX_SENSOR_COUNT];
> struct device *sensor_device;
> struct clk *bus_clk;
> struct clk *mod_clk;
> @@ -280,7 +291,8 @@ static int sun4i_gpadc_adc_read(struct iio_dev
> *indio_dev, int channel,
> SUN4I_GPADC_IRQ_FIFO_DATA);
> }
>
> -static int sun4i_gpadc_temp_read(struct iio_dev *indio_dev, int *val)
> +static int sun4i_gpadc_temp_read(struct iio_dev *indio_dev, int *val,
> + int sensor)
> {
> struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
>
> @@ -290,7 +302,8 @@ static int sun4i_gpadc_temp_read(struct iio_dev
> *indio_dev, int *val)
>
> pm_runtime_get_sync(indio_dev->dev.parent);
>
> - regmap_read(info->regmap, info->data->temp_data_base, val);
> + regmap_read(info->regmap, info->data->temp_data_base + 0x4 * sensor,
> + val);
>
> pm_runtime_mark_last_busy(indio_dev->dev.parent);
> pm_runtime_put_autosuspend(indio_dev->dev.parent);
> @@ -334,7 +347,7 @@ static int sun4i_gpadc_read_raw(struct iio_dev *indio_dev,
> ret = sun4i_gpadc_adc_read(indio_dev, chan->channel,
> val);
> else
> - ret = sun4i_gpadc_temp_read(indio_dev, val);
> + ret = sun4i_gpadc_temp_read(indio_dev, val, 0);
>
> if (ret)
> return ret;
> @@ -420,10 +433,11 @@ static int sun4i_gpadc_runtime_resume(struct device
> *dev)
>
> static int sun4i_gpadc_get_temp
[linux-sunxi] Re: [PATCH v3 17/30] iio: adc: sun4i-gpadc-iio: rework: support clocks and reset
On Thu, Aug 30, 2018 at 05:45:05PM +0200, Philipp Rossak wrote:
> For adding newer sensor some basic rework of the code is necessary.
>
> The SoCs after H3 has newer thermal sensor ADCs, which have two clock
> inputs (bus clock and sampling clock) and a reset. The registers are
> also re-arranged.
>
> This commit reworks the code, adds the process of the clocks and resets.
>
> Signed-off-by: Philipp Rossak
> ---
> drivers/iio/adc/sun4i-gpadc-iio.c | 72
> +--
> 1 file changed, 70 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
> b/drivers/iio/adc/sun4i-gpadc-iio.c
> index c278e165e161..c12de48c4e86 100644
> --- a/drivers/iio/adc/sun4i-gpadc-iio.c
> +++ b/drivers/iio/adc/sun4i-gpadc-iio.c
> @@ -22,6 +22,7 @@
> * shutdown for not being used.
> */
>
> +#include
> #include
> #include
> #include
> @@ -31,6 +32,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
>
> @@ -63,6 +65,9 @@ struct gpadc_data {
> int (*ths_suspend)(struct sun4i_gpadc_iio *info);
> int (*ths_resume)(struct sun4i_gpadc_iio *info);
> boolsupport_irq;
> + boolhas_bus_clk;
> + boolhas_bus_rst;
> + boolhas_mod_clk;
> u32 temp_data_base;
> };
>
> @@ -127,6 +132,9 @@ struct sun4i_gpadc_iio {
> struct mutexmutex;
> struct thermal_zone_device *tzd;
> struct device *sensor_device;
> + struct clk *bus_clk;
> + struct clk *mod_clk;
> + struct reset_control*reset;
> };
>
> static const struct iio_chan_spec sun4i_gpadc_channels[] = {
> @@ -472,8 +480,13 @@ static int sun4i_gpadc_probe_dt(struct platform_device
> *pdev,
> if (IS_ERR(base))
> return PTR_ERR(base);
>
> - info->regmap = devm_regmap_init_mmio(&pdev->dev, base,
> - &sun4i_gpadc_regmap_config);
> + if (info->data->has_bus_clk)
> + info->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "bus",
> + base, &sun4i_gpadc_regmap_config);
> + else
> + info->regmap = devm_regmap_init_mmio(&pdev->dev, base,
> + &sun4i_gpadc_regmap_config);
> +
> if (IS_ERR(info->regmap)) {
> ret = PTR_ERR(info->regmap);
> dev_err(&pdev->dev, "failed to init regmap: %d\n", ret);
> @@ -498,9 +511,58 @@ static int sun4i_gpadc_probe_dt(struct platform_device
> *pdev,
> }
> }
>
> + if (info->data->has_bus_rst) {
> + info->reset = devm_reset_control_get(&pdev->dev, NULL);
> + if (IS_ERR(info->reset)) {
> + ret = PTR_ERR(info->reset);
> + return ret;
> + }
> +
> + ret = reset_control_deassert(info->reset);
> + if (ret)
> + return ret;
> + }
> +
> + if (info->data->has_bus_clk) {
> + info->bus_clk = devm_clk_get(&pdev->dev, "bus");
> + if (IS_ERR(info->bus_clk)) {
> + ret = PTR_ERR(info->bus_clk);
> + goto assert_reset;
> + }
> +
> + ret = clk_prepare_enable(info->bus_clk);
> + if (ret)
> + goto assert_reset;
That should be done in the runtime_resume hook
> + }
> +
> + if (info->data->has_mod_clk) {
> + info->mod_clk = devm_clk_get(&pdev->dev, "mod");
> + if (IS_ERR(info->mod_clk)) {
> + ret = PTR_ERR(info->mod_clk);
> + goto disable_bus_clk;
> + }
> +
> + /* Running at 4MHz */
> + ret = clk_set_rate(info->mod_clk, 400);
> + if (ret)
> + goto disable_bus_clk;
Why?
> + ret = clk_prepare_enable(info->mod_clk);
> + if (ret)
> + goto disable_bus_clk;
> + }
> +
> info->sensor_device = &pdev->dev;
>
> return 0;
> +
> +disable_bus_clk:
> + clk_disable_unprepare(info->bus_clk);
> +
> +assert_reset:
> + reset_control_assert(info->reset);
You should check for the variables here before calling those
functions, if you end up here with your variable not set, you'll have
improper refcounting.
Maxime
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[linux-sunxi] Re: [PATCH v3 16/30] iio: adc: sun4i-gpadc-iio: rework: readout temp_data
On Thu, Aug 30, 2018 at 05:45:04PM +0200, Philipp Rossak wrote:
> For adding newer sensor some basic rework of the code is necessary.
>
> This commit reworks the code and uses regmap field to read out
> temp_data.
>
> Signed-off-by: Philipp Rossak
> ---
> drivers/iio/adc/sun4i-gpadc-iio.c | 21 +
> 1 file changed, 13 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
> b/drivers/iio/adc/sun4i-gpadc-iio.c
> index d48f338af563..c278e165e161 100644
> --- a/drivers/iio/adc/sun4i-gpadc-iio.c
> +++ b/drivers/iio/adc/sun4i-gpadc-iio.c
> @@ -63,6 +63,7 @@ struct gpadc_data {
> int (*ths_suspend)(struct sun4i_gpadc_iio *info);
> int (*ths_resume)(struct sun4i_gpadc_iio *info);
> boolsupport_irq;
> + u32 temp_data_base;
> };
>
> static irqreturn_t sun4i_gpadc_data_irq_handler(int irq, void *dev_id);
> @@ -77,6 +78,7 @@ static const struct gpadc_data sun4i_gpadc_data = {
> .adc_channel = true,
> .ths_irq_thread = sun4i_gpadc_data_irq_handler,
> .support_irq = true,
> + .temp_data_base = SUN4I_GPADC_TEMP_DATA,
> };
>
> static const struct gpadc_data sun5i_gpadc_data = {
> @@ -89,6 +91,7 @@ static const struct gpadc_data sun5i_gpadc_data = {
> .adc_channel = true,
> .ths_irq_thread = sun4i_gpadc_data_irq_handler,
> .support_irq = true,
> + .temp_data_base = SUN4I_GPADC_TEMP_DATA,
> };
>
> static const struct gpadc_data sun6i_gpadc_data = {
> @@ -101,12 +104,14 @@ static const struct gpadc_data sun6i_gpadc_data = {
> .adc_channel = true,
> .ths_irq_thread = sun4i_gpadc_data_irq_handler,
> .support_irq = true,
> + .temp_data_base = SUN4I_GPADC_TEMP_DATA,
> };
>
> static const struct gpadc_data sun8i_a33_gpadc_data = {
> .temp_offset = -1662,
> .temp_scale = 162,
> .tp_mode_en = SUN8I_A33_GPADC_CTRL1_CHOP_TEMP_EN,
> + .temp_data_base = SUN4I_GPADC_TEMP_DATA,
> };
>
> struct sun4i_gpadc_iio {
> @@ -271,18 +276,18 @@ static int sun4i_gpadc_temp_read(struct iio_dev
> *indio_dev, int *val)
> {
> struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
>
> - if (!info->data->support_irq) {
> - pm_runtime_get_sync(indio_dev->dev.parent);
> + if (info->data->adc_channel)
> + return sun4i_gpadc_read(indio_dev, 0, val,
> + SUN4I_GPADC_IRQ_TEMP_DATA);
>
> - regmap_read(info->regmap, SUN4I_GPADC_TEMP_DATA, val);
> + pm_runtime_get_sync(indio_dev->dev.parent);
>
> - pm_runtime_mark_last_busy(indio_dev->dev.parent);
> - pm_runtime_put_autosuspend(indio_dev->dev.parent);
> + regmap_read(info->regmap, info->data->temp_data_base, val);
>
> - return 0;
> - }
> + pm_runtime_mark_last_busy(indio_dev->dev.parent);
> + pm_runtime_put_autosuspend(indio_dev->dev.parent);
>
> - return sun4i_gpadc_read(indio_dev, 0, val, SUN4I_GPADC_IRQ_TEMP_DATA);
> + return 0;
You should make this patch as small as possible. If you want to add a
variable and to invert a condition, please make two patches.
Maxime
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[linux-sunxi] Re: [PATCH v3 14/30] dt-bindings: update the Allwinner GPADC device tree binding for H3 & A83T
On Thu, Aug 30, 2018 at 05:45:02PM +0200, Philipp Rossak wrote: > Allwinner H3 features a thermal sensor like the one in A33, but has its > register re-arranged, the clock divider moved to CCU (originally the > clock divider is in ADC) and added a pair of bus clock and reset. > > Allwinner A83T features a thermal sensor similar to the H3, the ths clock, > the bus clock and the reset was removed from the CCU. The THS in A83T > has a clock that is directly connected and runs with 24 MHz. > > Update the binding document to cover H3 and A83T. > > Signed-off-by: Philipp Rossak You probably want to have a look at: https://www.spinics.net/lists/arm-kernel/msg670167.html Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
[linux-sunxi] Re: [PATCH v3 11/30] iio: adc: add new compatibles
On Thu, Aug 30, 2018 at 05:44:59PM +0200, Philipp Rossak wrote:
> We are now adding the new compatibles.
>
> Signed-off-by: Philipp Rossak
> ---
> drivers/iio/adc/sun4i-gpadc-iio.c | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
> b/drivers/iio/adc/sun4i-gpadc-iio.c
> index a2027614ee0c..79b8efdab803 100644
> --- a/drivers/iio/adc/sun4i-gpadc-iio.c
> +++ b/drivers/iio/adc/sun4i-gpadc-iio.c
> @@ -435,6 +435,18 @@ static const struct of_device_id sun4i_gpadc_of_id[] = {
> .compatible = "allwinner,sun8i-a33-ths",
> .data = &sun8i_a33_gpadc_data,
> },
> + {
> + .compatible = "allwinner,sun4i-a10-gpadc",
> + .data = &sun4i_gpadc_data
> + },
> + {
> + .compatible = "allwinner,sun5i-a13-gpadc",
> + .data = &sun5i_gpadc_data
> + },
> + {
> + .compatible = "allwinner,sun6i-a31-gpadc",
> + .data = &sun6i_gpadc_data
> + },
Usually the bindings come before the code that use them, and the
commit log is also lacking to explain how we should use them, that
they won't be used at the moment, why, etc.
Maxime
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[linux-sunxi] Re: [PATCH v3 10/30] iio: adc: rework irq and adc_channel handling
Hi,
On Thu, Aug 30, 2018 at 05:44:58PM +0200, Philipp Rossak wrote:
> We rework the irq handling and the adc_channel handling.
> This is requiered since we merge the mfd driver into the adc driver.
>
> Signed-off-by: Philipp Rossak
This patch is actually the opposite of the previous ones, it has too
many things in it, and sohuld be split :)
> ---
> drivers/iio/adc/sun4i-gpadc-iio.c | 157
> --
> include/linux/mfd/sun4i-gpadc.h | 7 --
> 2 files changed, 98 insertions(+), 66 deletions(-)
>
> diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
> b/drivers/iio/adc/sun4i-gpadc-iio.c
> index 658a7e3e3370..a2027614ee0c 100644
> --- a/drivers/iio/adc/sun4i-gpadc-iio.c
> +++ b/drivers/iio/adc/sun4i-gpadc-iio.c
> @@ -49,6 +49,8 @@ static unsigned int sun6i_gpadc_chan_select(unsigned int
> chan)
> return SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(chan);
> }
>
> +struct sun4i_gpadc_iio;
> +
> struct gpadc_data {
> int temp_offset;
> int temp_scale;
> @@ -56,8 +58,15 @@ struct gpadc_data {
> unsigned inttp_adc_select;
> unsigned int(*adc_chan_select)(unsigned int chan);
> unsigned intadc_chan_mask;
> + booladc_channel;
> + irqreturn_t (*ths_irq_thread)(int irq, void *dev_id);
> + int (*ths_suspend)(struct sun4i_gpadc_iio *info);
> + int (*ths_resume)(struct sun4i_gpadc_iio *info);
> + boolsupport_irq;
> };
>
> +static irqreturn_t sun4i_gpadc_data_irq_handler(int irq, void *dev_id);
> +
> static const struct gpadc_data sun4i_gpadc_data = {
> .temp_offset = -1932,
> .temp_scale = 133,
> @@ -65,6 +74,9 @@ static const struct gpadc_data sun4i_gpadc_data = {
> .tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT,
> .adc_chan_select = &sun4i_gpadc_chan_select,
> .adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK,
> + .adc_channel = true,
> + .ths_irq_thread = sun4i_gpadc_data_irq_handler,
> + .support_irq = true,
> };
>
> static const struct gpadc_data sun5i_gpadc_data = {
> @@ -74,6 +86,9 @@ static const struct gpadc_data sun5i_gpadc_data = {
> .tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT,
> .adc_chan_select = &sun4i_gpadc_chan_select,
> .adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK,
> + .adc_channel = true,
> + .ths_irq_thread = sun4i_gpadc_data_irq_handler,
> + .support_irq = true,
> };
>
> static const struct gpadc_data sun6i_gpadc_data = {
> @@ -83,6 +98,9 @@ static const struct gpadc_data sun6i_gpadc_data = {
> .tp_adc_select = SUN6I_GPADC_CTRL1_TP_ADC_SELECT,
> .adc_chan_select = &sun6i_gpadc_chan_select,
> .adc_chan_mask = SUN6I_GPADC_CTRL1_ADC_CHAN_MASK,
> + .adc_channel = true,
> + .ths_irq_thread = sun4i_gpadc_data_irq_handler,
> + .support_irq = true,
So this seems to enable the support for the interrupts without going
through the MFD regmap that was removed in the previous patches.
> };
>
> static const struct gpadc_data sun8i_a33_gpadc_data = {
> @@ -96,13 +114,10 @@ struct sun4i_gpadc_iio {
> struct completion completion;
> int temp_data;
> u32 adc_data;
> + unsigned intirq_data_type;
> struct regmap *regmap;
> - unsigned intfifo_data_irq;
> - atomic_tignore_fifo_data_irq;
> - unsigned inttemp_data_irq;
> - atomic_tignore_temp_data_irq;
> + unsigned intirq;
> const struct gpadc_data *data;
> - boolno_irq;
But at the same time, you remove some fields of that structure, and
rename some other without any explanation.
> /* prevents concurrent reads of temperature and ADC */
> struct mutexmutex;
> struct thermal_zone_device *tzd;
> @@ -130,6 +145,20 @@ static const struct regmap_config
> sun4i_gpadc_regmap_config = {
> .fast_io = true,
> };
>
> +static int sun4i_gpadc_irq_init(struct sun4i_gpadc_iio *info)
> +{
> + u32 reg;
> +
> + if (info->irq_data_type == SUN4I_GPADC_IRQ_FIFO_DATA)
> + reg = SUN4I_GPADC_INT_FIFOC_TEMP_IRQ_EN;
> + else
> + reg = SUN4I_GPADC_INT_FIFOC_TEMP_IRQ_EN;
> +
> + regmap_write(info->regmap, SUN4I_GPADC_INT_FIFOC, reg);
> +
> + return 0;
> +}
> +
> static int sun4i_prepare_for_irq(struct iio_dev *indio_dev, int channel,
>unsigned int irq)
> {
> @@ -151,7 +180,7 @@ static int sun4i_prepare_for_irq(struct iio_dev
> *indio_dev, int channel,
> if (ret)
> return ret;
>
> - if (irq == info->fifo_data_irq) {
> + if (irq == SUN4I_GPADC_IRQ_FIFO_DATA) {
> ret = regmap_write(info->regmap, SUN4I_GPADC_CTRL1,
>
[linux-sunxi] Re: [PATCH v3 09/30] iio: adc: Threat A33 as thermal sensor and remove non thermal sun4i channel
On Thu, Aug 30, 2018 at 05:44:57PM +0200, Philipp Rossak wrote: > We want to use this driver mostly as thermal sensor, that still supports > the adc for the older chips, thus we threat the A33 as thermal sensor. > We also remove the adc channel without thermal support. The A33 can definitely be used as an ADC, so we need to keep that support. Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
[linux-sunxi] Re: [PATCH v3 08/30] iio: adc: remove hwmon structure
On Thu, Aug 30, 2018 at 05:44:56PM +0200, Philipp Rossak wrote: > We remove the hwmon structure that was requiered for the mfd driver. > > Signed-off-by: Philipp Rossak Same thing here, you should merge that in the commit that removes the probe_mfd call. Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
[linux-sunxi] Re: [PATCH v3 07/30] iio: adc: remove mfd_probe & sunwi_irq_init function
On Thu, Aug 30, 2018 at 05:44:55PM +0200, Philipp Rossak wrote: > In the previous commit we removed the function call, now we remove the > unused functions. > > Signed-off-by: Philipp Rossak This will create a warning between the two commits, it should be merged in the previous patch. Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
[linux-sunxi] Re: [PATCH v3 04/30] iio: adc: Kconfig: Update Kconfig to new build options
On Thu, Aug 30, 2018 at 05:44:52PM +0200, Philipp Rossak wrote: > Since we are merging the mfd driver into the iio adc driver we need to > update the Kconfig build options. Most of your commit logs a pretty short, and this is an issue for people lacking context. This would be the reviewers, but also users bisecting to see where there's a bug, or you in a couple of years from now :) Every commit log should be as complete as possible. In this case, you are saying what you are doing, but this is actually redundant with the patch, I can already tell what you are doing by reading the rest of the mail. However, what is really important is *why* you are doing it. > Signed-off-by: Philipp Rossak > --- > drivers/iio/adc/Kconfig | 11 +++ > 1 file changed, 7 insertions(+), 4 deletions(-) > > diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig > index 9da79070357c..5d0cffd6d2e4 100644 > --- a/drivers/iio/adc/Kconfig > +++ b/drivers/iio/adc/Kconfig > @@ -713,13 +713,16 @@ config STX104 > array module parameter. > > config SUN4I_GPADC > - tristate "Support for the Allwinner SoCs GPADC" > + tristate "Allwinner sunxi platforms' GPADC/Thermal driver" I'm really not sure this is worth updating > + select REGMAP_MMIO > + select REGMAP_IRQ > depends on IIO > - depends on MFD_SUN4I_GPADC || MACH_SUN8I > - depends on THERMAL || !THERMAL_OF > + depends on ARCH_SUNXI || MACH_SUN8I > + depends on THERMAL && THERMAL_OF For example, why you are changing the thermal dependency is not really obvious to anyone. > help > Say yes here to build support for Allwinner (A10, A13 and A31) SoCs > - GPADC. This ADC provides 4 channels which can be used as an ADC or as > + GPADC or newer SOCs (A33, H3, A83T, ...) Thermal sensor driver. > + This ADC provides 4 channels which can be used as an ADC or as I'm not sure this is worth updating either, especially when there's information that has been dropped. Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
[linux-sunxi] Re: [PATCH v3 01/30] mfd: Makefile: Remove build option for MFD:sun4i-gpadc
Hi Philipp, First, thanks for doing that rework. It was needed, and it's very much appreciated :) As you can imagine though, I have a bunch of comments. On Thu, Aug 30, 2018 at 05:44:49PM +0200, Philipp Rossak wrote: > Since we are merging the mfd driver into the sun4i-gpadc driver we need > to remove the build options for the sun4i-gpadc driver. > > Signed-off-by: Philipp Rossak > --- > drivers/mfd/Makefile | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile > index e9fd20dba18d..c680994db988 100644 > --- a/drivers/mfd/Makefile > +++ b/drivers/mfd/Makefile > @@ -220,7 +220,6 @@ obj-$(CONFIG_INTEL_SOC_PMIC_CHTDC_TI) += > intel_soc_pmic_chtdc_ti.o > obj-$(CONFIG_MFD_MT6397) += mt6397-core.o > > obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o > -obj-$(CONFIG_MFD_SUN4I_GPADC)+= sun4i-gpadc.o One of the things we should strive for is bisectability, which means being able to have a working driver at every point in time while introducing the features. In this particular case, this isn't really a problem since you're removing part of code that were never really enabled, but you should at least document why in your commit log. Thanks! Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
[linux-sunxi] Re: [PATCH v4 09/13] ARM: dts: sun8i: r40: add sata node
On Fri, Aug 31, 2018 at 3:56 PM Corentin Labbe
wrote:
>
> On Fri, Aug 31, 2018 at 09:35:00AM +0200, Maxime Ripard wrote:
> > On Thu, Aug 30, 2018 at 09:01:16PM +0200, Corentin Labbe wrote:
> > > R40 have a sata controller which is the same as A20.
> > > This patch adds a DT node for it.
> > >
> > > Signed-off-by: Icenowy Zheng
> > > Signed-off-by: Corentin Labbe
> > > ---
> > > arch/arm/boot/dts/sun8i-r40.dtsi | 23 +++
> > > 1 file changed, 23 insertions(+)
> > >
> > > diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi
> > > b/arch/arm/boot/dts/sun8i-r40.dtsi
> > > index 852c2ccc3268..d6b5820da850 100644
> > > --- a/arch/arm/boot/dts/sun8i-r40.dtsi
> > > +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> > > @@ -550,6 +550,29 @@
> > > #size-cells = <0>;
> > > };
> > >
> > > + ahci: sata@1c18000 {
> > > + compatible = "allwinner,sun8i-r40-ahci";
> > > + reg = <0x01c18000 0x1000>;
> > > + interrupts = ;
> > > + clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
> > > + resets = <&ccu RST_BUS_SATA>;
> > > + resets-name = "ahci";
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + status = "disabled";
> > > +
> > > + sata_port: sata-port@0 {
> > > + reg = <0>;
> > > + phys = <&sata_phy>;
> > > + };
> > > + };
> > > +
> > > + sata_phy: sata-phy@1c180c0 {
> > > + compatible = "allwinner,sun8i-r40-sata-phy";
> > > + reg = <0x1c180c0 0x200>;
> >
> > Overlapping devices in the DTS is not ok.
> >
>
> I do the same than arch/arm/boot/dts/berlin2.dtsi (sata@e9 phy@e900a0)
> But since it is not a good justification, it seems that regmap is my only
> solution ?
Since you are effectively splitting one device node into two, you should
adjust the original (ahci) device nodes register range.
ChenYu
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[linux-sunxi] Re: [PATCH v4 09/13] ARM: dts: sun8i: r40: add sata node
On Fri, Aug 31, 2018 at 09:35:00AM +0200, Maxime Ripard wrote:
> On Thu, Aug 30, 2018 at 09:01:16PM +0200, Corentin Labbe wrote:
> > R40 have a sata controller which is the same as A20.
> > This patch adds a DT node for it.
> >
> > Signed-off-by: Icenowy Zheng
> > Signed-off-by: Corentin Labbe
> > ---
> > arch/arm/boot/dts/sun8i-r40.dtsi | 23 +++
> > 1 file changed, 23 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi
> > b/arch/arm/boot/dts/sun8i-r40.dtsi
> > index 852c2ccc3268..d6b5820da850 100644
> > --- a/arch/arm/boot/dts/sun8i-r40.dtsi
> > +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> > @@ -550,6 +550,29 @@
> > #size-cells = <0>;
> > };
> >
> > + ahci: sata@1c18000 {
> > + compatible = "allwinner,sun8i-r40-ahci";
> > + reg = <0x01c18000 0x1000>;
> > + interrupts = ;
> > + clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
> > + resets = <&ccu RST_BUS_SATA>;
> > + resets-name = "ahci";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + status = "disabled";
> > +
> > + sata_port: sata-port@0 {
> > + reg = <0>;
> > + phys = <&sata_phy>;
> > + };
> > + };
> > +
> > + sata_phy: sata-phy@1c180c0 {
> > + compatible = "allwinner,sun8i-r40-sata-phy";
> > + reg = <0x1c180c0 0x200>;
>
> Overlapping devices in the DTS is not ok.
>
I do the same than arch/arm/boot/dts/berlin2.dtsi (sata@e9 phy@e900a0)
But since it is not a good justification, it seems that regmap is my only
solution ?
Regards
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[linux-sunxi] Re: [PATCH v4 12/13] ARM: dts: sun4i: a10: add sata-port/sata-phy nodes
On Fri, Aug 31, 2018 at 09:37:24AM +0200, Maxime Ripard wrote:
> On Thu, Aug 30, 2018 at 09:01:19PM +0200, Corentin Labbe wrote:
> > This patch convert sun4i-a10 sata to the new binding which use a sata
> > phy node.
> >
> > Signed-off-by: Corentin Labbe
> > ---
> > arch/arm/boot/dts/sun4i-a10.dtsi | 13 +
> > 1 file changed, 13 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi
> > b/arch/arm/boot/dts/sun4i-a10.dtsi
> > index 3d62a8950720..52d5c2e79499 100644
> > --- a/arch/arm/boot/dts/sun4i-a10.dtsi
> > +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
> > @@ -556,7 +556,20 @@
> > reg = <0x01c18000 0x1000>;
> > interrupts = <56>;
> > clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > status = "disabled";
> > +
> > + sata_port: sata-port@0 {
> > + reg = <0>;
> > + phys = <&sata_phy>;
> > + };
> > + };
> > +
> > + sata_phy: sata_phy@1c180c0 {
> > + compatible = "allwinner,sun4i-a10-sata-phy";
> > + reg = <0x01c180c0 0x200>;
> > + #phy-cells = <0>;
> > };
>
> This patch, together with the following one, breaks the DT ABI, this
> isn't something we can do anymore.
>
So what can I do ?
Keep the DT in place and drop the patch 13 like wens suggested ?
Regards
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[linux-sunxi] Re: [PATCH v4 00/13] ata: ahci_platform: support allwinner R40 AHCI
Hi Jens,
On Thu, Aug 30, 2018 at 08:52:52PM -0600, Jens Axboe wrote:
> On 8/30/18 8:32 PM, Chen-Yu Tsai wrote:
> > Hi,
> >
> > On Fri, Aug 31, 2018 at 4:31 AM Jens Axboe wrote:
> >>
> >> On 8/30/18 1:01 PM, Corentin Labbe wrote:
> >>> Hello
> >>>
> >>> This patchset add support for allwinner R40 AHCI controller.
> >>>
> >>> The whole patchset is tested on sun8i-r40-bananapi-m2-ultra and
> >>> on sun7i-a20-cubieboard2 which doesnt have any of the ressources added
> >>> by this serie, so no regression should come with it.
> >>>
> >>> The last patch(ata: ahci_sunxi: remove PHY code) should not be merged,
> >>> but will be resent for inclustion when all patchs will have hit linus
> >>> tree.
> >>
> >> Applied 1-12 with Hans's blessing, thanks Corentin.
> >
> > Please don't merge device tree ("dts") patches, i.e. patches 9-12. We will
> > merge them through the sunxi / armsoc tree. Having them in separate trees
> > introduces conflicts when we have other stuff going through our tree.
>
> OK, fair enough, I can drop those.
And the DT bits actually have some issues that would need to change
the code significantly.
Can you drop all of them please?
Thanks!
Maxmie
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Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
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[linux-sunxi] Re: [PATCH v4 12/13] ARM: dts: sun4i: a10: add sata-port/sata-phy nodes
On Thu, Aug 30, 2018 at 09:01:19PM +0200, Corentin Labbe wrote:
> This patch convert sun4i-a10 sata to the new binding which use a sata
> phy node.
>
> Signed-off-by: Corentin Labbe
> ---
> arch/arm/boot/dts/sun4i-a10.dtsi | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi
> b/arch/arm/boot/dts/sun4i-a10.dtsi
> index 3d62a8950720..52d5c2e79499 100644
> --- a/arch/arm/boot/dts/sun4i-a10.dtsi
> +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
> @@ -556,7 +556,20 @@
> reg = <0x01c18000 0x1000>;
> interrupts = <56>;
> clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> status = "disabled";
> +
> + sata_port: sata-port@0 {
> + reg = <0>;
> + phys = <&sata_phy>;
> + };
> + };
> +
> + sata_phy: sata_phy@1c180c0 {
> + compatible = "allwinner,sun4i-a10-sata-phy";
> + reg = <0x01c180c0 0x200>;
> + #phy-cells = <0>;
> };
This patch, together with the following one, breaks the DT ABI, this
isn't something we can do anymore.
Maxime
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Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
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[linux-sunxi] Re: [PATCH v4 09/13] ARM: dts: sun8i: r40: add sata node
On Thu, Aug 30, 2018 at 09:01:16PM +0200, Corentin Labbe wrote:
> R40 have a sata controller which is the same as A20.
> This patch adds a DT node for it.
>
> Signed-off-by: Icenowy Zheng
> Signed-off-by: Corentin Labbe
> ---
> arch/arm/boot/dts/sun8i-r40.dtsi | 23 +++
> 1 file changed, 23 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi
> b/arch/arm/boot/dts/sun8i-r40.dtsi
> index 852c2ccc3268..d6b5820da850 100644
> --- a/arch/arm/boot/dts/sun8i-r40.dtsi
> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> @@ -550,6 +550,29 @@
> #size-cells = <0>;
> };
>
> + ahci: sata@1c18000 {
> + compatible = "allwinner,sun8i-r40-ahci";
> + reg = <0x01c18000 0x1000>;
> + interrupts = ;
> + clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
> + resets = <&ccu RST_BUS_SATA>;
> + resets-name = "ahci";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + sata_port: sata-port@0 {
> + reg = <0>;
> + phys = <&sata_phy>;
> + };
> + };
> +
> + sata_phy: sata-phy@1c180c0 {
> + compatible = "allwinner,sun8i-r40-sata-phy";
> + reg = <0x1c180c0 0x200>;
Overlapping devices in the DTS is not ok.
Maxime
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Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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