Re: [linux-sunxi] Re: [PATCH 2/3] mmc: sunxi: Set the 'New Timing' register for 8 bits DDR transfers

2016-08-02 Thread Hans de Goede 

Hi,

On 01-08-16 15:52, Jean-Francois Moine wrote:

On Sat, 30 Jul 2016 12:19:03 +0200
Hans de Goede  wrote:


Jean-Francois, can you submit a v2 of your patch and make the writing of
SDXC_REG_NTSR depend on a new sun8i-a83t-mmc compatible ?

Also you should probably drop the bits about the clock stuff from the
commit message as that just seems to confuse people.


Hi Hans,

I submitted a new patch (sorry, I forgot the history), but it asks for
some explanation.

- in the old timings, the phase delays are set in the clock.
  That's why there is a function clk_set_phase() which is called from
  the MMC side.

- in the new timings, the delays are in the MMC register SDXC_REG_NTSR
  only.
  In this case, the function clk_set_phase() is of no use
  (also, by test, it seems that the phase delays set by hardware
   reset do work, so, there is no need to set them), but,

- there is a bit in the clock telling that the new timings are used,
  i.e. that the phase delays of the clock must be ignored.

  Not setting this bit prevents the device to work (at least in the
  A83T, the H3 seems more helpful).


Thanks for the explanation, it would be good to put this in the commit
msg of v3 of the patch.

Regards,

Hans

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Re: [linux-sunxi] Re: [PATCH 2/3] mmc: sunxi: Set the 'New Timing' register for 8 bits DDR transfers

2016-08-01 Thread Jean-Francois Moine 
On Sat, 30 Jul 2016 12:19:03 +0200
Hans de Goede  wrote:

> Jean-Francois, can you submit a v2 of your patch and make the writing of
> SDXC_REG_NTSR depend on a new sun8i-a83t-mmc compatible ?
> 
> Also you should probably drop the bits about the clock stuff from the
> commit message as that just seems to confuse people.

Hi Hans,

I submitted a new patch (sorry, I forgot the history), but it asks for
some explanation.

- in the old timings, the phase delays are set in the clock.
  That's why there is a function clk_set_phase() which is called from
  the MMC side.

- in the new timings, the delays are in the MMC register SDXC_REG_NTSR
  only.
  In this case, the function clk_set_phase() is of no use
  (also, by test, it seems that the phase delays set by hardware
   reset do work, so, there is no need to set them), but,

- there is a bit in the clock telling that the new timings are used,
  i.e. that the phase delays of the clock must be ignored.

  Not setting this bit prevents the device to work (at least in the
  A83T, the H3 seems more helpful).

-- 
Ken ar c'hentañ | ** Breizh ha Linux atav! **
Jef |   http://moinejf.free.fr/

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Re: [linux-sunxi] Re: [PATCH 2/3] mmc: sunxi: Set the 'New Timing' register for 8 bits DDR transfers

2016-07-30 Thread Hans de Goede 

Hi,

On 29-07-16 21:17, Maxime Ripard wrote:

On Thu, Jul 21, 2016 at 11:26:55AM +0200, Jean-Francois Moine wrote:

On Thu, 21 Jul 2016 10:56:15 +0200
Maxime Ripard  wrote:


On Wed, Jul 20, 2016 at 08:16:28PM +0200, Jean-Francois Moine wrote:

The 'new timing mode' with 8 bits DDR works correctly when the NewTiming
register is set.


What does that mode brings to the table?


From my tests, the eMMC of the Banana Pi M3 (A83T) cannot work when the
new mode is not used.



Signed-off-by: Jean-Francois Moine 
---
Note about the 'new timing mode'.

This patch assumes that, when the new mode is used, the clock driver
sets the mode select in the MMC clock and multiplies the clock rate
by 2:
- MMC side:
  - with a timing 8 bits DDR at 50MHz, the MMC driver calls
clk_set_rate() with a rate 50*2 = 100MHz,
- clock side:
  - the clock driver sets the hardware MMC clock to 100*2 = 200MHz,
  - setting the 'mode select' of the hardware MMC clock divides the
rate by 2,
- MMC side:
  - setting the MMC clock divider register to 1 divides the rate by 2.
So, the final rate is 50MHz.


What happens if you actually want to set it to 100MHz?


There is no SDXC_CLK_100M in the mainline driver, and 100MHz is asked
only for 8 bits DDR at 50MHz.


You're missing the point.

clk_set_rate is supposed to apply a rate as close as possible as
requested, there's no reason why you would request a rate twice as
high as need.


On all SoCs which support it, requesting DDR-8bit needs a twice as high
clock as the mmc base clock (due to the DDR).

If you look at the current code you will see that what actually happens
is that we pass twice as high clock as the mmc-subsys asks for to
clk_set_rate and set the controllers *internal* divider to 2 (instead of
the usual 1), this is not new and not introduced by Jean-Francois' patch.

All Jean-Francois' patch adds is the setting of the new SDXC_REG_NTSR
reg msb bit when we do this. Note no changes to the clock rate calculations
are made. If this fixes the eMMC on A83T boards this seems like a good
patch to me, but IMHO we should only write the SDXC_REG_NTSR on the A83t
and not everywhere as Jean-Francois' patch does.

Jean-Francois, can you submit a v2 of your patch and make the writing of
SDXC_REG_NTSR depend on a new sun8i-a83t-mmc compatible ?

Also you should probably drop the bits about the clock stuff from the
commit message as that just seems to confuse people.

Regards,

Hans

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[linux-sunxi] Re: [PATCH 2/3] mmc: sunxi: Set the 'New Timing' register for 8 bits DDR transfers

2016-07-29 Thread Jean-Francois Moine 
On Fri, 29 Jul 2016 21:36:34 +0200
Maxime Ripard  wrote:

> On Thu, Jul 21, 2016 at 11:26:55AM +0200, Jean-Francois Moine wrote:
> > On Thu, 21 Jul 2016 10:56:15 +0200
> > Maxime Ripard  wrote:
> > 
> > > On Wed, Jul 20, 2016 at 08:16:28PM +0200, Jean-Francois Moine wrote:
> > > > The 'new timing mode' with 8 bits DDR works correctly when the NewTiming
> > > > register is set.
> > > 
> > > What does that mode brings to the table?
> > 
> > From my tests, the eMMC of the Banana Pi M3 (A83T) cannot work when the
> > new mode is not used.
> 
> That's odd. The one in the Pine64 seems to work just fine, and yet
> there's only the new mode on the A64.

I spent 2 weeks on this problem. You may try it by yourself.

-- 
Ken ar c'hentañ | ** Breizh ha Linux atav! **
Jef |   http://moinejf.free.fr/

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[linux-sunxi] Re: [PATCH 2/3] mmc: sunxi: Set the 'New Timing' register for 8 bits DDR transfers

2016-07-29 Thread Jean-Francois Moine 
On Fri, 29 Jul 2016 21:17:30 +0200
Maxime Ripard  wrote:

> > > What happens if you actually want to set it to 100MHz?
> > 
> > There is no SDXC_CLK_100M in the mainline driver, and 100MHz is asked
> > only for 8 bits DDR at 50MHz.
> 
> You're missing the point.
> 
> clk_set_rate is supposed to apply a rate as close as possible as
> requested, there's no reason why you would request a rate twice as
> high as need.
> 
> You want to switch the clock from one mode to another, fine, create a
> new function for that. But don't hack an existing one.

I will not change the core clock stuff for this marginal case.
Flagging the clock as 'new mode capable' is enough.
Anyway, setting the 'new mode' bit to the clock divides the rate by
two, so, there is no reason to not use it.

-- 
Ken ar c'hentañ | ** Breizh ha Linux atav! **
Jef |   http://moinejf.free.fr/

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[linux-sunxi] Re: [PATCH 2/3] mmc: sunxi: Set the 'New Timing' register for 8 bits DDR transfers

2016-07-29 Thread Maxime Ripard 
On Thu, Jul 21, 2016 at 11:26:55AM +0200, Jean-Francois Moine wrote:
> On Thu, 21 Jul 2016 10:56:15 +0200
> Maxime Ripard  wrote:
> 
> > On Wed, Jul 20, 2016 at 08:16:28PM +0200, Jean-Francois Moine wrote:
> > > The 'new timing mode' with 8 bits DDR works correctly when the NewTiming
> > > register is set.
> > 
> > What does that mode brings to the table?
> 
> From my tests, the eMMC of the Banana Pi M3 (A83T) cannot work when the
> new mode is not used.

That's odd. The one in the Pine64 seems to work just fine, and yet
there's only the new mode on the A64.

Maxime

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Embedded Linux and Kernel engineering
http://free-electrons.com

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[linux-sunxi] Re: [PATCH 2/3] mmc: sunxi: Set the 'New Timing' register for 8 bits DDR transfers

2016-07-29 Thread Maxime Ripard 
On Thu, Jul 21, 2016 at 11:26:55AM +0200, Jean-Francois Moine wrote:
> On Thu, 21 Jul 2016 10:56:15 +0200
> Maxime Ripard  wrote:
> 
> > On Wed, Jul 20, 2016 at 08:16:28PM +0200, Jean-Francois Moine wrote:
> > > The 'new timing mode' with 8 bits DDR works correctly when the NewTiming
> > > register is set.
> > 
> > What does that mode brings to the table?
> 
> From my tests, the eMMC of the Banana Pi M3 (A83T) cannot work when the
> new mode is not used.
> 
> > > 
> > > Signed-off-by: Jean-Francois Moine 
> > > ---
> > > Note about the 'new timing mode'.
> > > 
> > > This patch assumes that, when the new mode is used, the clock driver
> > > sets the mode select in the MMC clock and multiplies the clock rate
> > > by 2:
> > > - MMC side:
> > >   - with a timing 8 bits DDR at 50MHz, the MMC driver calls
> > > clk_set_rate() with a rate 50*2 = 100MHz,
> > > - clock side:
> > >   - the clock driver sets the hardware MMC clock to 100*2 = 200MHz,
> > >   - setting the 'mode select' of the hardware MMC clock divides the
> > > rate by 2,
> > > - MMC side:
> > >   - setting the MMC clock divider register to 1 divides the rate by 2.
> > > So, the final rate is 50MHz.
> > 
> > What happens if you actually want to set it to 100MHz?
> 
> There is no SDXC_CLK_100M in the mainline driver, and 100MHz is asked
> only for 8 bits DDR at 50MHz.

You're missing the point.

clk_set_rate is supposed to apply a rate as close as possible as
requested, there's no reason why you would request a rate twice as
high as need.

You want to switch the clock from one mode to another, fine, create a
new function for that. But don't hack an existing one.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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[linux-sunxi] Re: [PATCH 2/3] mmc: sunxi: Set the 'New Timing' register for 8 bits DDR transfers

2016-07-21 Thread Jean-Francois Moine 
On Thu, 21 Jul 2016 10:56:15 +0200
Maxime Ripard  wrote:

> On Wed, Jul 20, 2016 at 08:16:28PM +0200, Jean-Francois Moine wrote:
> > The 'new timing mode' with 8 bits DDR works correctly when the NewTiming
> > register is set.
> 
> What does that mode brings to the table?

>From my tests, the eMMC of the Banana Pi M3 (A83T) cannot work when the
new mode is not used.

> > 
> > Signed-off-by: Jean-Francois Moine 
> > ---
> > Note about the 'new timing mode'.
> > 
> > This patch assumes that, when the new mode is used, the clock driver
> > sets the mode select in the MMC clock and multiplies the clock rate
> > by 2:
> > - MMC side:
> >   - with a timing 8 bits DDR at 50MHz, the MMC driver calls
> > clk_set_rate() with a rate 50*2 = 100MHz,
> > - clock side:
> >   - the clock driver sets the hardware MMC clock to 100*2 = 200MHz,
> >   - setting the 'mode select' of the hardware MMC clock divides the
> > rate by 2,
> > - MMC side:
> >   - setting the MMC clock divider register to 1 divides the rate by 2.
> > So, the final rate is 50MHz.
> 
> What happens if you actually want to set it to 100MHz?

There is no SDXC_CLK_100M in the mainline driver, and 100MHz is asked
only for 8 bits DDR at 50MHz.

-- 
Ken ar c'hentañ | ** Breizh ha Linux atav! **
Jef |   http://moinejf.free.fr/

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[linux-sunxi] Re: [PATCH 2/3] mmc: sunxi: Set the 'New Timing' register for 8 bits DDR transfers

2016-07-21 Thread Maxime Ripard 
Hi,

On Wed, Jul 20, 2016 at 08:16:28PM +0200, Jean-Francois Moine wrote:
> The 'new timing mode' with 8 bits DDR works correctly when the NewTiming
> register is set.

What does that mode brings to the table?

> 
> Signed-off-by: Jean-Francois Moine 
> ---
> Note about the 'new timing mode'.
> 
> This patch assumes that, when the new mode is used, the clock driver
> sets the mode select in the MMC clock and multiplies the clock rate
> by 2:
> - MMC side:
>   - with a timing 8 bits DDR at 50MHz, the MMC driver calls
> clk_set_rate() with a rate 50*2 = 100MHz,
> - clock side:
>   - the clock driver sets the hardware MMC clock to 100*2 = 200MHz,
>   - setting the 'mode select' of the hardware MMC clock divides the
> rate by 2,
> - MMC side:
>   - setting the MMC clock divider register to 1 divides the rate by 2.
> So, the final rate is 50MHz.

What happens if you actually want to set it to 100MHz?

Maxime

-- 
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Embedded Linux and Kernel engineering
http://free-electrons.com

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