On Thu, 21 Jul 2016 10:56:15 +0200 Maxime Ripard <maxime.rip...@free-electrons.com> wrote:
> On Wed, Jul 20, 2016 at 08:16:28PM +0200, Jean-Francois Moine wrote: > > The 'new timing mode' with 8 bits DDR works correctly when the NewTiming > > register is set. > > What does that mode brings to the table? >From my tests, the eMMC of the Banana Pi M3 (A83T) cannot work when the new mode is not used. > > > > Signed-off-by: Jean-Francois Moine <moin...@free.fr> > > --- > > Note about the 'new timing mode'. > > > > This patch assumes that, when the new mode is used, the clock driver > > sets the mode select in the MMC clock and multiplies the clock rate > > by 2: > > - MMC side: > > - with a timing 8 bits DDR at 50MHz, the MMC driver calls > > clk_set_rate() with a rate 50*2 = 100MHz, > > - clock side: > > - the clock driver sets the hardware MMC clock to 100*2 = 200MHz, > > - setting the 'mode select' of the hardware MMC clock divides the > > rate by 2, > > - MMC side: > > - setting the MMC clock divider register to 1 divides the rate by 2. > > So, the final rate is 50MHz. > > What happens if you actually want to set it to 100MHz? There is no SDXC_CLK_100M in the mainline driver, and 100MHz is asked only for 8 bits DDR at 50MHz. -- Ken ar c'hentañ | ** Breizh ha Linux atav! ** Jef | http://moinejf.free.fr/ -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
