[linux-sunxi] Re: [PATCH 3/3] mmc: sunxi: Add support to the Allwinner A83T

[Jean-Francois Moine]

On Thu, 21 Jul 2016 11:18:51 +0200
Jean-Francois Moine  wrote:

> > On Wed, Jul 20, 2016 at 08:28:47PM +0200, Jean-Francois Moine wrote:
> > > The rate of the PLL-PERIPH clock is usually set to 1.2GHz in the A83T.
> > 
> > Uh? The datasheet says to set it to 600MHz.
> 
> Right. But the driver of the SDK for the Banana Pi M3 (A83T) sets it
> to 1.2GHz.

I tested again, and, with the pll-periph at 600MHz, both the SDcard and
the eMMC are working fine.
So, you may forget about this patch, sorry for the noise.

-- 
Ken ar c'hentañ | ** Breizh ha Linux atav! **
Jef |   http://moinejf.free.fr/

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[linux-sunxi] Re: [PATCH 3/3] mmc: sunxi: Add support to the Allwinner A83T

[Jean-Francois Moine]

On Thu, 21 Jul 2016 10:58:38 +0200
Maxime Ripard  wrote:

> On Wed, Jul 20, 2016 at 08:28:47PM +0200, Jean-Francois Moine wrote:
> > The rate of the PLL-PERIPH clock is usually set to 1.2GHz in the A83T.
> 
> Uh? The datasheet says to set it to 600MHz.

Right. But the driver of the SDK for the Banana Pi M3 (A83T) sets it
to 1.2GHz.

> > This patch sets the phase delays of the output and sample clocks
> > accordingly.
> > 
> > Signed-off-by: Jean-Francois Moine 
> > ---
> > Note: The impacted phase delays are only for 50MHz.
> > The phase delays are not used in 50MHz 8 bits DDR (new timing mode).
> 
> Actually, they seem to be, in the new timing mode register.

In the SDK driver, nothing is set in the new timing mode register.
Anyway, the eMMC works fine in both the Banana Pis M2+ and M3
with no delay.

-- 
Ken ar c'hentañ | ** Breizh ha Linux atav! **
Jef |   http://moinejf.free.fr/

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[linux-sunxi] Re: [PATCH 3/3] mmc: sunxi: Add support to the Allwinner A83T

[Maxime Ripard]

Maxime

On Wed, Jul 20, 2016 at 08:28:47PM +0200, Jean-Francois Moine wrote:
> The rate of the PLL-PERIPH clock is usually set to 1.2GHz in the A83T.

Uh? The datasheet says to set it to 600MHz.

> This patch sets the phase delays of the output and sample clocks
> accordingly.
> 
> Signed-off-by: Jean-Francois Moine 
> ---
> Note: The impacted phase delays are only for 50MHz.
> The phase delays are not used in 50MHz 8 bits DDR (new timing mode).

Actually, they seem to be, in the new timing mode register.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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