On Thu, 21 Jul 2016 10:58:38 +0200 Maxime Ripard <maxime.rip...@free-electrons.com> wrote:
> On Wed, Jul 20, 2016 at 08:28:47PM +0200, Jean-Francois Moine wrote: > > The rate of the PLL-PERIPH clock is usually set to 1.2GHz in the A83T. > > Uh? The datasheet says to set it to 600MHz. Right. But the driver of the SDK for the Banana Pi M3 (A83T) sets it to 1.2GHz. > > This patch sets the phase delays of the output and sample clocks > > accordingly. > > > > Signed-off-by: Jean-Francois Moine <moin...@free.fr> > > --- > > Note: The impacted phase delays are only for 50MHz. > > The phase delays are not used in 50MHz 8 bits DDR (new timing mode). > > Actually, they seem to be, in the new timing mode register. In the SDK driver, nothing is set in the new timing mode register. Anyway, the eMMC works fine in both the Banana Pis M2+ and M3 with no delay. -- Ken ar c'hentañ | ** Breizh ha Linux atav! ** Jef | http://moinejf.free.fr/ -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
