[PATCH] USB: ohci: da8xx: remove clk con_id

[David Lechner]

The ohci-da8xx device only has one clock, so a con_id is not needed, so
remove it. This way we don't have to add an unnecessary property to the
device tree bindings for the clock.

Signed-off-by: David Lechner 
---
 drivers/usb/host/ohci-da8xx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/usb/host/ohci-da8xx.c b/drivers/usb/host/ohci-da8xx.c
index 0c507a0..a55cbba 100644
--- a/drivers/usb/host/ohci-da8xx.c
+++ b/drivers/usb/host/ohci-da8xx.c
@@ -413,7 +413,7 @@ static int ohci_da8xx_probe(struct platform_device *pdev)
da8xx_ohci = to_da8xx_ohci(hcd);
da8xx_ohci->hcd = hcd;
 
-   da8xx_ohci->usb11_clk = devm_clk_get(>dev, "usb11");
+   da8xx_ohci->usb11_clk = devm_clk_get(>dev, NULL);
if (IS_ERR(da8xx_ohci->usb11_clk)) {
error = PTR_ERR(da8xx_ohci->usb11_clk);
if (error != -EPROBE_DEFER)
-- 
2.7.4

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[PATCH] USB: musb: da8xx: remove clock con_id

[David Lechner]

There is only one clock for the DA8xx MUSB device, so we don't need the
con_id, so remove it. This way we don't have to add an unnecessary
property to the device tree bindings for the clock.

Signed-off-by: David Lechner 
---
 drivers/usb/musb/da8xx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/usb/musb/da8xx.c b/drivers/usb/musb/da8xx.c
index 6c036de..b8295ce 100644
--- a/drivers/usb/musb/da8xx.c
+++ b/drivers/usb/musb/da8xx.c
@@ -520,7 +520,7 @@ static int da8xx_probe(struct platform_device *pdev)
if (!glue)
return -ENOMEM;
 
-   clk = devm_clk_get(>dev, "usb20");
+   clk = devm_clk_get(>dev, NULL);
if (IS_ERR(clk)) {
dev_err(>dev, "failed to get clock\n");
return PTR_ERR(clk);
-- 
2.7.4

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[PATCH v3 3/3] ARM: dts: r7s72100: add USB device to device tree

[Chris Brandt]

Add USB device support.

Signed-off-by: Chris Brandt 
Reviewed-by: Geert Uytterhoeven 
---
v3:
 * Changed from "renesas,usbhs-r7s72100" to "renesas,rza1-usbhs"
v2:
 * Node name is now generic 'usb@'
 * GIC_SPI (73-32) is now just GIC_SPI 41
 * All hex number are lower case
 * Added Reviewed-by
---
 arch/arm/boot/dts/r7s72100.dtsi | 20 
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index ab9645a42eca..d94431767913 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -667,4 +667,24 @@
power-domains = <_clocks>;
status = "disabled";
};
+
+   usbhs0: usb@e801 {
+   compatible = "renesas,rza1-usbhs";
+   reg = <0xe801 0x1a0>;
+   interrupts = ;
+   clocks = <_clks R7S72100_CLK_USB0>;
+   renesas,buswait = <4>;
+   power-domains = <_clocks>;
+   status = "disabled";
+   };
+
+   usbhs1: usb@e8207000 {
+   compatible = "renesas,rza1-usbhs";
+   reg = <0xe8207000 0x1a0>;
+   interrupts = ;
+   clocks = <_clks R7S72100_CLK_USB1>;
+   renesas,buswait = <4>;
+   power-domains = <_clocks>;
+   status = "disabled";
+   };
 };
-- 
2.15.1


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[PATCH v3 2/3] dt-bindings: usb: renesas_usbhs: Add support for RZ/A1

[Chris Brandt]

Document support for RZ/A1 SoCs

Signed-off-by: Chris Brandt 
Reviewed-by: Geert Uytterhoeven 
---
v3:
 * Removed "renesas,usbhs-r7s72100"
v2:
 * Added Reviewed-by
---
 Documentation/devicetree/bindings/usb/renesas_usbhs.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt 
b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
index 47394ab788e3..fa16d8d33815 100644
--- a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
+++ b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
@@ -15,6 +15,7 @@ Required properties:
- "renesas,usbhs-r8a77995" for r8a77995 (R-Car D3) compatible device
- "renesas,rcar-gen2-usbhs" for R-Car Gen2 or RZ/G1 compatible devices
- "renesas,rcar-gen3-usbhs" for R-Car Gen3 compatible device
+   - "renesas,rza1-usbhs" for RZ/A1 compatible device
 
When compatible with the generic version, nodes must list the
SoC-specific version corresponding to the platform first followed
-- 
2.15.1


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[PATCH v3 0/3] usb: renesas_usbhs: Add RZ/A1 support

[Chris Brandt]

This series adds RZ/A1 gadget support to the renesas_usbhs driver.
Basically, it's almost the same HW as the R-Car (and SH) parts.
The only real difference is the some extra registers for the PHY.

This was tested on an RSK board by connecting to a PC as an
Ethernet CDC gadget.

v3:
 * Changed from "renesas,usbhs-r7s72100" to "renesas,rza1-usbhs"
 * Removed "renesas,usbhs-r7s72100"
 * Changed License of rza.c
v2:
 * Node name is now generic 'usb@'
 * GIC_SPI (73-32) is now just GIC_SPI 41
 * All hex number are lower case
 * Added Reviewed-by


Chris Brandt (3):
  usb: renesas_usbhs: Add support for RZ/A1
  dt-bindings: usb: renesas_usbhs: Add support for RZ/A1
  ARM: dts: r7s72100: add USB device to device tree

 .../devicetree/bindings/usb/renesas_usbhs.txt  |  1 +
 arch/arm/boot/dts/r7s72100.dtsi| 20 +
 drivers/usb/renesas_usbhs/Makefile |  2 +-
 drivers/usb/renesas_usbhs/common.c | 13 ++
 drivers/usb/renesas_usbhs/common.h |  6 +++
 drivers/usb/renesas_usbhs/rza.c| 52 ++
 drivers/usb/renesas_usbhs/rza.h|  4 ++
 include/linux/usb/renesas_usbhs.h  |  1 +
 8 files changed, 98 insertions(+), 1 deletion(-)
 create mode 100644 drivers/usb/renesas_usbhs/rza.c
 create mode 100644 drivers/usb/renesas_usbhs/rza.h

-- 
2.15.1


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[PATCH v3 1/3] usb: renesas_usbhs: Add support for RZ/A1

[Chris Brandt]

This patch adds the capability to support RZ/A1 SoCs.

Signed-off-by: Chris Brandt 
---
v2:
 * Removed "renesas,usbhs-r7s72100"
 * Changed license of rza.c
---
 drivers/usb/renesas_usbhs/Makefile |  2 +-
 drivers/usb/renesas_usbhs/common.c | 13 ++
 drivers/usb/renesas_usbhs/common.h |  6 +
 drivers/usb/renesas_usbhs/rza.c| 52 ++
 drivers/usb/renesas_usbhs/rza.h|  4 +++
 include/linux/usb/renesas_usbhs.h  |  1 +
 6 files changed, 77 insertions(+), 1 deletion(-)
 create mode 100644 drivers/usb/renesas_usbhs/rza.c
 create mode 100644 drivers/usb/renesas_usbhs/rza.h

diff --git a/drivers/usb/renesas_usbhs/Makefile 
b/drivers/usb/renesas_usbhs/Makefile
index fac147a3ad23..5c5b51bb48ef 100644
--- a/drivers/usb/renesas_usbhs/Makefile
+++ b/drivers/usb/renesas_usbhs/Makefile
@@ -5,7 +5,7 @@
 
 obj-$(CONFIG_USB_RENESAS_USBHS)+= renesas_usbhs.o
 
-renesas_usbhs-y:= common.o mod.o pipe.o fifo.o rcar2.o 
rcar3.o
+renesas_usbhs-y:= common.o mod.o pipe.o fifo.o rcar2.o 
rcar3.o rza.o
 
 ifneq ($(CONFIG_USB_RENESAS_USBHS_HCD),)
renesas_usbhs-y += mod_host.o
diff --git a/drivers/usb/renesas_usbhs/common.c 
b/drivers/usb/renesas_usbhs/common.c
index c5289b3ecf8d..4310df46639d 100644
--- a/drivers/usb/renesas_usbhs/common.c
+++ b/drivers/usb/renesas_usbhs/common.c
@@ -17,6 +17,7 @@
 #include "common.h"
 #include "rcar2.h"
 #include "rcar3.h"
+#include "rza.h"
 
 /*
  * image of renesas_usbhs
@@ -488,6 +489,10 @@ static const struct of_device_id usbhs_of_match[] = {
.compatible = "renesas,rcar-gen3-usbhs",
.data = (void *)USBHS_TYPE_RCAR_GEN3,
},
+   {
+   .compatible = "renesas,rza1-usbhs",
+   .data = (void *)USBHS_TYPE_RZA1,
+   },
{ },
 };
 MODULE_DEVICE_TABLE(of, usbhs_of_match);
@@ -520,6 +525,11 @@ static struct renesas_usbhs_platform_info 
*usbhs_parse_dt(struct device *dev)
dparam->pipe_size = ARRAY_SIZE(usbhsc_new_pipe);
}
 
+   if (dparam->type == USBHS_TYPE_RZA1) {
+   dparam->pipe_configs = usbhsc_new_pipe;
+   dparam->pipe_size = ARRAY_SIZE(usbhsc_new_pipe);
+   }
+
return info;
 }
 
@@ -591,6 +601,9 @@ static int usbhs_probe(struct platform_device *pdev)
dev_err(>dev, "no notifier registered\n");
}
break;
+   case USBHS_TYPE_RZA1:
+   priv->pfunc = usbhs_rza1_ops;
+   break;
default:
if (!info->platform_callback.get_id) {
dev_err(>dev, "no platform callbacks");
diff --git a/drivers/usb/renesas_usbhs/common.h 
b/drivers/usb/renesas_usbhs/common.h
index c9747f064601..f619afeae2b8 100644
--- a/drivers/usb/renesas_usbhs/common.h
+++ b/drivers/usb/renesas_usbhs/common.h
@@ -98,6 +98,7 @@ struct usbhs_priv;
 #define D2FIFOCTR  0x00F2  /* for R-Car Gen2 */
 #define D3FIFOSEL  0x00F4  /* for R-Car Gen2 */
 #define D3FIFOCTR  0x00F6  /* for R-Car Gen2 */
+#define SUSPMODE   0x0102  /* for RZ/A */
 
 /* SYSCFG */
 #define SCKE   (1 << 10)   /* USB Module Clock Enable */
@@ -106,6 +107,8 @@ struct usbhs_priv;
 #define DRPD   (1 << 5)/* D+ Line/D- Line Resistance Control */
 #define DPRPU  (1 << 4)/* D+ Line Resistance Control */
 #define USBE   (1 << 0)/* USB Module Operation Enable */
+#define UCKSEL (1 << 2)/* Clock Select for RZ/A1 */
+#define UPLLE  (1 << 1)/* USB PLL Enable for RZ/A1 */
 
 /* DVSTCTR */
 #define EXTLP  (1 << 10)   /* Controls the EXTLP pin output state */
@@ -233,6 +236,9 @@ struct usbhs_priv;
 #define USBSPD_SPEED_FULL  0x2
 #define USBSPD_SPEED_HIGH  0x3
 
+/* SUSPMODE */
+#define SUSPM  (1 << 14)   /* SuspendM Control */
+
 /*
  * struct
  */
diff --git a/drivers/usb/renesas_usbhs/rza.c b/drivers/usb/renesas_usbhs/rza.c
new file mode 100644
index ..5b287257ec11
--- /dev/null
+++ b/drivers/usb/renesas_usbhs/rza.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas USB driver RZ/A initialization and power control
+ *
+ * Copyright (C) 2018 Chris Brandt
+ * Copyright (C) 2018 Renesas Electronics Corporation
+ */
+
+#include 
+#include 
+#include 
+#include "common.h"
+#include "rza.h"
+
+static int usbhs_rza1_hardware_init(struct platform_device *pdev)
+{
+   struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
+   struct device_node *usb_x1_clk, *extal_clk;
+   u32 freq_usb = 0, freq_extal = 0;
+
+   /* Input Clock Selection (NOTE: ch0 controls both ch0 and ch1) */
+   usb_x1_clk = of_find_node_by_name(NULL, "usb_x1");
+   extal_clk = of_find_node_by_name(NULL, "extal");
+   of_property_read_u32(usb_x1_clk, "clock-frequency", _usb);
+   of_property_read_u32(extal_clk, "clock-frequency", _extal);
+  

Re: [PATCH 13/15] usb: dwc3: Track DWC_usb31 VERSIONTYPE

[Thinh Nguyen]

On 1/5/2018 1:43 PM, Sergei Shtylyov wrote:

> Hello!
> 
> On 1/5/2018 11:16 PM, Thinh Nguyen wrote:
> 
>> Add a new variable to dwc3 structure to track VERSIONTYPE. The
> 
>  That's called field, not variable.

Thanks for pointing that out. I'll make an update.

>> VERSIONTYPE is represented in ASCII in the 32-bit VERSIONTYPE register.
>> In DWC_usb31, sub releases for each version are tracked with VERSIONTYPE
>> such as "ea01" and "ea02".
>>
>> Signed-off-by: Thinh Nguyen 
> [...]
> 
> MBR, Sergei
> 

BR,
Thinh
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Re: [PATCH 13/15] usb: dwc3: Track DWC_usb31 VERSIONTYPE

[Sergei Shtylyov]

Hello!

On 1/5/2018 11:16 PM, Thinh Nguyen wrote:


Add a new variable to dwc3 structure to track VERSIONTYPE. The


   That's called field, not variable.


VERSIONTYPE is represented in ASCII in the 32-bit VERSIONTYPE register.
In DWC_usb31, sub releases for each version are tracked with VERSIONTYPE
such as "ea01" and "ea02".

Signed-off-by: Thinh Nguyen 

[...]

MBR, Sergei
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RE: [PATCH v2 1/3] usb: renesas_usbhs: Add support for RZ/A1

[Chris Brandt]

Hi Geert,

On Friday, January 05, 2018, Geert Uytterhoeven wrote:
> > +   {
> > +   .compatible = "renesas,usbhs-r7s72100",
> > +   .data = (void *)USBHS_TYPE_RZA1,
> > +   },
> 
> I think it suffices to drop the part above...
> 
> > {
> > .compatible = "renesas,rcar-gen2-usbhs",
> > .data = (void *)USBHS_TYPE_RCAR_GEN2,
> > @@ -488,6 +493,10 @@ static const struct of_device_id usbhs_of_match[] =
> {
> > .compatible = "renesas,rcar-gen3-usbhs",
> > .data = (void *)USBHS_TYPE_RCAR_GEN3,
> > },
> > +   {
> > +   .compatible = "renesas,rza1-usbhs",
> > +   .data = (void *)USBHS_TYPE_RZA1,
> > +   },
> 
> ... and just let the driver match against the generic compatible value.
> But then you have to add "renesas,rza1-usbhs" to the DTS, too.

OK. I can do that.

I keep forgetting all the new/old DT rules.
I thought there was something about you always need a generic name and
also a device specific name.

I'm happy with just "renesas,rza1-usbhs".


> > --- /dev/null
> > +++ b/drivers/usb/renesas_usbhs/rza.c
> > @@ -0,0 +1,52 @@
> > +// SPDX-License-Identifier: GPL-1.0+
> 
> Not GPL-2.0?

Oops. Copy/paste error.


I'll submit a V3 of the series.


Thanks!

Chris

Re: [PATCH v2 1/3] usb: renesas_usbhs: Add support for RZ/A1

[Geert Uytterhoeven]

Hi Chris,

On Fri, Jan 5, 2018 at 7:46 PM, Chris Brandt  wrote:
> This patch adds the capability to support RZ/A1 SoCs.
>
> Signed-off-by: Chris Brandt 

Thanks for your patch!

> index c5289b3ecf8d..2abefd3d6050 100644
> --- a/drivers/usb/renesas_usbhs/common.c
> +++ b/drivers/usb/renesas_usbhs/common.c

> @@ -480,6 +481,10 @@ static const struct of_device_id usbhs_of_match[] = {
> .compatible = "renesas,usbhs-r8a77995",
> .data = (void *)USBHS_TYPE_RCAR_GEN3_WITH_PLL,
> },
> +   {
> +   .compatible = "renesas,usbhs-r7s72100",
> +   .data = (void *)USBHS_TYPE_RZA1,
> +   },

I think it suffices to drop the part above...

> {
> .compatible = "renesas,rcar-gen2-usbhs",
> .data = (void *)USBHS_TYPE_RCAR_GEN2,
> @@ -488,6 +493,10 @@ static const struct of_device_id usbhs_of_match[] = {
> .compatible = "renesas,rcar-gen3-usbhs",
> .data = (void *)USBHS_TYPE_RCAR_GEN3,
> },
> +   {
> +   .compatible = "renesas,rza1-usbhs",
> +   .data = (void *)USBHS_TYPE_RZA1,
> +   },

... and just let the driver match against the generic compatible value.
But then you have to add "renesas,rza1-usbhs" to the DTS, too.

> --- /dev/null
> +++ b/drivers/usb/renesas_usbhs/rza.c
> @@ -0,0 +1,52 @@
> +// SPDX-License-Identifier: GPL-1.0+

Not GPL-2.0?

> +++ b/drivers/usb/renesas_usbhs/rza.h
> @@ -0,0 +1,4 @@
> +// SPDX-License-Identifier: GPL-2.0

like here?

Gr{oetje,eeting}s,

Geert

--
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In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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Re: [PATCH v2 3/3] ARM: dts: r7s72100: add USB device to device tree

[Geert Uytterhoeven]

On Fri, Jan 5, 2018 at 7:46 PM, Chris Brandt  wrote:
> Add USB device support.
>
> Signed-off-by: Chris Brandt 
> Reviewed-by: Geert Uytterhoeven 

> --- a/arch/arm/boot/dts/r7s72100.dtsi
> +++ b/arch/arm/boot/dts/r7s72100.dtsi
> @@ -667,4 +667,24 @@
> power-domains = <_clocks>;
> status = "disabled";
> };
> +
> +   usbhs0: usb@e801 {
> +   compatible = "renesas,usbhs-r7s72100";

+ "renesas,rza1-usbhs"

Gr{oetje,eeting}s,

Geert

--
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In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
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[PATCH 10/15] usb: dwc3: gadget: Set maxpacket size for ep0 IN

[Thinh Nguyen]

There are 2 control endpoint structures for DWC3. However, the driver
only updates the OUT direction control endpoint structure during
ConnectDone event. DWC3 driver needs to update the endpoint max packet
size for control IN endpoint as well. If the max packet size is not
properly set, then the driver will incorrectly calculate the data
transfer size and fail to send ZLP for HS/FS 3-stage control read
transfer.

The fix is simply to update the max packet size for the ep0 IN direction
during ConnectDone event.

Signed-off-by: Thinh Nguyen 
---
 drivers/usb/dwc3/gadget.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index bdf2a2014ebd..6ae924d95cbc 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -2751,6 +2751,8 @@ static void dwc3_gadget_conndone_interrupt(struct dwc3 
*dwc)
break;
}
 
+   dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket;
+
/* Enable USB2 LPM Capability */
 
if ((dwc->revision > DWC3_REVISION_194A) &&
-- 
2.11.0

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[PATCH 15/15] usb: dwc3: Add workaround for isoc start transfer failure

[Thinh Nguyen]

In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
isochronous IN, BIT[15:14] of the 16-bit microframe number reported by
the XferNotReady event are invalid. The driver uses this number to
schedule the isochronous transfer and passes it to the START TRANSFER
command. Because this number is invalid, the command may fail. If
BIT[15:14] matches the internal 16-bit microframe, the START TRANSFER
command will pass and the transfer will start at the scheduled time, if
it is off by 1, the command will still pass, but the transfer will start
2 seconds in the future. All other conditions the START TRANSFER command
will fail with bus-expiry.

In order to workaround this issue, we can issue multiple START TRANSFER
commands with different values of BIT[15:14]: 'b00, 'b01, 'b02, and 'b03
and do an END TRANSFER command. Each combination is 2 seconds apart. 4
seconds into the future will cause a bus-expiry failure. As the result,
within the 4 possible combinations for BIT[15:14], there will be 2
successful and 2 failure START COMMAND status. One of the 2 successful
command status will result in a 2-second delay. The smaller BIT[15:14]
value is the correct one.

Since there are only 4 outcomes and the results are ordered, we can
simply test 2 START TRANSFER commands with BIT[15:14] combinations 'b00
and 'b01 to deduce the smallest successful combination.

+-+-+
| BIT(15) | BIT(14) |
+=+=+
 test0  |   0 |0|
+-+-+
 test1  |   0 |1|
+-+-+

With test0 and test1 BIT[15:14] combinations, here is the logic:
if test0 passes and test1 passes, BIT[15:14] is 'b00
if test0 passes and test1 fails, BIT[15:14] is 'b11
if test0 fails and test1 fails, BIT[15:14] is 'b10
if test0 fails and test1 passes, BIT[15:14] is 'b01

Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
endpoints.

Signed-off-by: Thinh Nguyen 
---
 drivers/usb/dwc3/core.c   |   2 +
 drivers/usb/dwc3/core.h   |  13 
 drivers/usb/dwc3/gadget.c | 189 --
 3 files changed, 199 insertions(+), 5 deletions(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index ab0912e4f837..25a75849306e 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -1071,6 +1071,8 @@ static void dwc3_get_properties(struct dwc3 *dwc)
"snps,is-utmi-l1-suspend");
device_property_read_u8(dev, "snps,hird-threshold",
_threshold);
+   dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
+   "snps,dis_start_transfer_quirk");
dwc->usb3_lpm_capable = device_property_read_bool(dev,
"snps,usb3_lpm_capable");
dwc->rx_thr_sel_prd = device_property_read_bool(dev,
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 764dc896d07a..255540ac5263 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -555,6 +555,10 @@ struct dwc3_event_buffer {
  * @name: a human readable name e.g. ep1out-bulk
  * @direction: true for TX, false for RX
  * @stream_capable: true when streams are enabled
+ * @frame_number_15_14: BIT[15:14] of the frame number to test isochronous
+ * START TRANSFER command failure workaround
+ * @test0_status: the result of testing START TRANSFER command with
+ * frame_number_15_14 = 'b00 (non-zero means failure)
  */
 struct dwc3_ep {
struct usb_ep   endpoint;
@@ -608,6 +612,10 @@ struct dwc3_ep {
 
unsigneddirection:1;
unsignedstream_capable:1;
+
+   /* Isochronous START TRANSFER workaround for STAR 9001202023 */
+   u8  frame_number_15_14;
+   int test0_status;
 };
 
 enum dwc3_phy {
@@ -862,6 +870,8 @@ struct dwc3_scratchpad_array {
  * @pullups_connected: true when Run/Stop bit is set
  * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
  * @three_stage_setup: set if we perform a three phase setup
+ * @dis_start_transfer_quirk: set if start_transfer failure SW workaround is
+ * not needed for DWC_usb31 version 1.70a-ea06 and below
  * @usb3_lpm_capable: set if hadrware supports Link Power Management
  * @rx_thr_sel_prd: set to enable ESS receive packet threshold
  * @tx_thr_sel_prd: set to enable ESS transmit packet threshold
@@ -984,10 +994,12 @@ struct dwc3 {
 #define DWC3_REVISION_IS_DWC31 0x8000
 #define DWC3_USB31_REVISION_110A   (0x3131302a | DWC3_REVISION_IS_DWC31)
 #define DWC3_USB31_REVISION_120A   (0x3132302a | DWC3_REVISION_IS_DWC31)
+#define DWC3_USB31_REVISION_170A   (0x3137302a | DWC3_REVISION_IS_DWC31)
 
u32 ver_type;
 
 #define DWC3_USB31_VERSIONTYPE_EA010x65613031

[PATCH 13/15] usb: dwc3: Track DWC_usb31 VERSIONTYPE

[Thinh Nguyen]

Add a new variable to dwc3 structure to track VERSIONTYPE. The
VERSIONTYPE is represented in ASCII in the 32-bit VERSIONTYPE register.
In DWC_usb31, sub releases for each version are tracked with VERSIONTYPE
such as "ea01" and "ea02".

Signed-off-by: Thinh Nguyen 
---
 drivers/usb/dwc3/core.c | 2 ++
 drivers/usb/dwc3/core.h | 5 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 56ca39b40a77..ab0912e4f837 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -642,6 +642,7 @@ static bool dwc3_core_is_valid(struct dwc3 *dwc)
 {
u32 reg;
 
+   dwc->ver_type = 0;
reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 
/* This should read as U3 followed by revision number */
@@ -652,6 +653,7 @@ static bool dwc3_core_is_valid(struct dwc3 *dwc)
/* Detected DWC_usb31 IP */
dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
dwc->revision |= DWC3_REVISION_IS_DWC31;
+   dwc->ver_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
} else {
return false;
}
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 21a6dcd379f1..764dc896d07a 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -810,6 +810,7 @@ struct dwc3_scratchpad_array {
  * @u1u2: only used on revisions <1.83a for workaround
  * @maximum_speed: maximum speed requested (mainly for testing purposes)
  * @revision: revision register contents
+ * @ver_type: VERSIONTYPE register contents, a sub release of a revision
  * @dr_mode: requested mode of operation
  * @current_dr_role: current role of operation when in dual-role mode
  * @desired_dr_role: desired role of operation when in dual-role mode
@@ -984,6 +985,10 @@ struct dwc3 {
 #define DWC3_USB31_REVISION_110A   (0x3131302a | DWC3_REVISION_IS_DWC31)
 #define DWC3_USB31_REVISION_120A   (0x3132302a | DWC3_REVISION_IS_DWC31)
 
+   u32 ver_type;
+
+#define DWC3_USB31_VERSIONTYPE_EA010x65613031
+
enum dwc3_ep0_next  ep0_next_event;
enum dwc3_ep0_state ep0state;
enum dwc3_link_statelink_state;
-- 
2.11.0

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[PATCH 14/15] usb: dwc3: Add disabling of start_transfer failure quirk

[Thinh Nguyen]

In DWC_usb31 version 1.70a-ea06 and prior needs a SW workaround for isoc
START TRANSFER command failure. However, some affected versions may have
RTL patches to fix this without a SW workaround. Add this quirk to
disable the SW workaround when it is not needed.

Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
endpoints.

Cc: John Youn 
Signed-off-by: Thinh Nguyen 
---
 Documentation/devicetree/bindings/usb/dwc3.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt 
b/Documentation/devicetree/bindings/usb/dwc3.txt
index 02dde83d02fa..c03a3b363cde 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -15,6 +15,9 @@ Optional properties:
  - phys: from the *Generic PHY* bindings
  - phy-names: from the *Generic PHY* bindings; supported names are "usb2-phy"
or "usb3-phy".
+ - snps,dis_start_transfer_quirk: when set, disable isoc START TRANSFER command
+   failure SW work-around for DWC_usb31 version 1.70a-ea06
+   and prior.
  - snps,usb3_lpm_capable: determines if platform is USB3 LPM capable
  - snps,disable_scramble_quirk: true when SW should disable data scrambling.
Only really useful for FPGA builds.
-- 
2.11.0

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[PATCH 02/15] usb: core: urb: Check SSP isoc ep comp descriptor

[Thinh Nguyen]

The maximum bytes per interval for USB SuperSpeed Plus can be set by
isoc endpoint companion descriptor when it is above 48K. If the
descriptor is provided, then use its value.

USB 3.1 spec 9.6.8

Signed-off-by: Thinh Nguyen 
---
 drivers/usb/core/urb.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/usb/core/urb.c b/drivers/usb/core/urb.c
index 9fdf137c4865..0ab4b896e3f3 100644
--- a/drivers/usb/core/urb.c
+++ b/drivers/usb/core/urb.c
@@ -433,6 +433,14 @@ int usb_submit_urb(struct urb *urb, gfp_t mem_flags)
max *= mult;
}
 
+   if (dev->speed == USB_SPEED_SUPER_PLUS &&
+   USB_SS_SSP_ISOC_COMP(ep->ss_ep_comp.bmAttributes)) {
+   struct usb_ssp_isoc_ep_comp_descriptor *isoc_ep_comp;
+
+   isoc_ep_comp = >ssp_isoc_ep_comp;
+   max = le32_to_cpu(isoc_ep_comp->dwBytesPerInterval);
+   }
+
/* "high bandwidth" mode, 1-3 packets/uframe? */
if (dev->speed == USB_SPEED_HIGH)
max *= usb_endpoint_maxp_mult(>desc);
-- 
2.11.0

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[PATCH 12/15] usb: dwc3: Dump LSP and BMU debug info

[Thinh Nguyen]

Dump LSP and BMU debug info.

Signed-off-by: Thinh Nguyen 
---
 drivers/usb/dwc3/core.h| 5 +
 drivers/usb/dwc3/debugfs.c | 5 +
 2 files changed, 10 insertions(+)

diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 83a74d10fa82..21a6dcd379f1 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -100,6 +100,11 @@
 #define DWC3_GHWPARAMS70xc15c
 #define DWC3_GDBGFIFOSPACE 0xc160
 #define DWC3_GDBGLTSSM 0xc164
+#define DWC3_GDBGBMU   0xc16c
+#define DWC3_GDBGLSPMUX0xc170
+#define DWC3_GDBGLSP   0xc174
+#define DWC3_GDBGEPINFO0   0xc178
+#define DWC3_GDBGEPINFO1   0xc17c
 #define DWC3_GPRTBIMAP_HS0 0xc180
 #define DWC3_GPRTBIMAP_HS1 0xc184
 #define DWC3_GPRTBIMAP_FS0 0xc188
diff --git a/drivers/usb/dwc3/debugfs.c b/drivers/usb/dwc3/debugfs.c
index 00e65530c81e..f09072395afe 100644
--- a/drivers/usb/dwc3/debugfs.c
+++ b/drivers/usb/dwc3/debugfs.c
@@ -81,6 +81,11 @@ static const struct debugfs_reg32 dwc3_regs[] = {
dump_register(GHWPARAMS7),
dump_register(GDBGFIFOSPACE),
dump_register(GDBGLTSSM),
+   dump_register(GDBGBMU),
+   dump_register(GDBGLSPMUX),
+   dump_register(GDBGLSP),
+   dump_register(GDBGEPINFO0),
+   dump_register(GDBGEPINFO1),
dump_register(GPRTBIMAP_HS0),
dump_register(GPRTBIMAP_HS1),
dump_register(GPRTBIMAP_FS0),
-- 
2.11.0

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[Bug] Endless deferred probe of dwc2 on RPi 3

[Stefan Wahren]

Hi,
i noticed on my Raspberry Pi 3 (Linux 4.15rc6, ARM64, defconfig) that probing 
of dwc2 driver is deferred endlessly. This issue is triggered by a recent DT 
clean up 014d6da6cb25 ("ARM: dts: bcm283x: Fix DTC warnings about missing 
phy-cells") which is correct according to 
Documentation/devicetree/bindings/usb/usb-nop-xceiv.txt

Here is the call stack which always returns -EPROBE_DEFER on this platform:
dwc2_lowlevel_hw_init()
devm_phy_get()
phy_get()
_of_phy_get()

Btw Raspberry Pi 2 (ARM, multi_v7_defconfig) is also affected, but not 
Raspberry Pi Zero W (ARM, bcm2835_config) while all 3 platforms share the same 
USB DT nodes.

Any ideas to fix this issue are welcome.

Best regards
Stefan
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[PATCH 07/15] usb: dwc3: Add DWC_usb31 GTXTHRCFG reg fields

[Thinh Nguyen]

Add new GTXTHRCFG bit field macros for DWC_usb31. The GTXTHRCFG register
fields for DWC_usb31 is as follows:
 +---+--+---+
 | BITS  | Name | Description   |
 +===+==+===+
 | 31:27 | reserved |   |
 | 26| UsbTxPktCntSel   | Async ESS transmit packet |
 |   |  | threshold enable  |
 | 25:21 | UsbTxPktCnt  | Async ESS transmit packet |
 |   |  | threshold count   |
 | 20:16 | UsbMaxTxBurstSize| Async ESS Max transmit burst size |
 | 15| UsbTxThrNumPktSel_HS_Prd | HS high bandwidth periodic|
 |   |  | transmit packet threshold enable  |
 | 14:13 | UsbTxThrNumPkt_HS_Prd| HS high bandwidth periodic|
 |   |  | transmit packet threshold count   |
 | 12:11 | reserved |   |
 | 10| UsbTxThrNumPktSel_Prd| Periodic ESS transmit packet  |
 |   |  | threshold enable  |
 | 9:5   | UsbTxThrNumPkt_Prd   | Periodic ESS transmit packet  |
 |   |  | threshold count   |
 | 4:0   | UsbMaxTxBurstSize_Prd| Max periodic ESS TX burst size|
 +---+--+---+

Signed-off-by: Thinh Nguyen 
---
 drivers/usb/dwc3/core.h | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 7c4ba7f74f27..ce10954afe49 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -181,6 +181,16 @@
 #define DWC3_USB31_RXTHRNUMPKT_PRD(n)  (((n) & 0x1f) << 5)
 #define DWC3_USB31_MAXRXBURSTSIZE_PRD(n)   ((n) & 0x1f)
 
+/* Global TX Threshold Configuration Register for DWC_usb31 only */
+#define DWC3_USB31_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0x1f) << 16)
+#define DWC3_USB31_GTXTHRCFG_TXPKTCNT(n)   (((n) & 0x1f) << 21)
+#define DWC3_USB31_GTXTHRCFG_PKTCNTSEL BIT(26)
+#define DWC3_USB31_TXTHRNUMPKTSEL_HS_PRD   BIT(15)
+#define DWC3_USB31_TXTHRNUMPKT_HS_PRD(n)   (((n) & 0x3) << 13)
+#define DWC3_USB31_TXTHRNUMPKTSEL_PRD  BIT(10)
+#define DWC3_USB31_TXTHRNUMPKT_PRD(n)  (((n) & 0x1f) << 5)
+#define DWC3_USB31_MAXTXBURSTSIZE_PRD(n)   ((n) & 0x1f)
+
 /* Global Configuration Register */
 #define DWC3_GCTL_PWRDNSCALE(n)((n) << 19)
 #define DWC3_GCTL_U2RSTECN BIT(16)
-- 
2.11.0

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[PATCH 01/15] usb: dwc3: Device SoftReset PHY synchonization delay

[Thinh Nguyen]

>From DWC_usb31 databook section 1.3.2, once DWC3_DCTL_CSFTRST bit is
cleared, we must wait at least 50ms before accessing the PHY domain
(synchronization delay).

Signed-off-by: Thinh Nguyen 
---
 drivers/usb/dwc3/core.c | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 07832509584f..7d21f21707f5 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -228,12 +228,23 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc)
do {
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
if (!(reg & DWC3_DCTL_CSFTRST))
-   return 0;
+   goto done;
 
udelay(1);
} while (--retries);
 
return -ETIMEDOUT;
+
+done:
+   /*
+* For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared,
+* we must wait at least 50ms before accessing the PHY domain
+* (synchronization delay). DWC_usb31 Databook section 1.3.2.
+*/
+   if (dwc3_is_usb31(dwc))
+   mdelay(50);
+
+   return 0;
 }
 
 /*
-- 
2.11.0

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[PATCH 09/15] usb: dwc3: Check for ESS TX/RX threshold config

[Thinh Nguyen]

Check and configure TX/RX threshold for DWC_usb31. Update dwc3 structure
with new variables to store these threshold configurations.

Signed-off-by: Thinh Nguyen 
---
 drivers/usb/dwc3/core.c | 57 +
 drivers/usb/dwc3/core.h | 12 +++
 2 files changed, 69 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 7d21f21707f5..56ca39b40a77 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -830,6 +830,41 @@ static int dwc3_core_init(struct dwc3 *dwc)
dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
}
 
+   /* Enable USB periodic ESS transmit and receive packet threshold */
+   if (dwc3_is_usb31(dwc) && dwc->dr_mode == USB_DR_MODE_HOST) {
+   if (dwc->rx_thr_sel_prd) {
+   u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
+   u8 rx_maxburst = dwc->rx_max_burst_prd;
+
+   reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
+   reg |= DWC3_USB31_RXTHRNUMPKTSEL_PRD;
+
+   reg &= ~DWC3_USB31_RXTHRNUMPKT_PRD(~0);
+   reg |= DWC3_USB31_RXTHRNUMPKT_PRD(rx_thr_num);
+
+   reg &= ~DWC3_USB31_MAXRXBURSTSIZE_PRD(~0);
+   reg |= DWC3_USB31_MAXRXBURSTSIZE_PRD(rx_maxburst);
+
+   dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
+   }
+
+   if (dwc->tx_thr_sel_prd) {
+   u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
+   u8 tx_maxburst = dwc->tx_max_burst_prd;
+
+   reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
+   reg |= DWC3_USB31_TXTHRNUMPKTSEL_PRD;
+
+   reg &= ~DWC3_USB31_TXTHRNUMPKT_PRD(~0);
+   reg |= DWC3_USB31_TXTHRNUMPKT_PRD(tx_thr_num);
+
+   reg &= ~DWC3_USB31_MAXTXBURSTSIZE_PRD(~0);
+   reg |= DWC3_USB31_MAXTXBURSTSIZE_PRD(tx_maxburst);
+
+   dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
+   }
+   }
+
return 0;
 
 err4:
@@ -998,6 +1033,10 @@ static void dwc3_get_properties(struct dwc3 *dwc)
u8  lpm_nyet_threshold;
u8  tx_de_emphasis;
u8  hird_threshold;
+   u8  rx_thr_num_pkt_prd;
+   u8  rx_max_burst_prd;
+   u8  tx_thr_num_pkt_prd;
+   u8  tx_max_burst_prd;
 
/* default to highest possible threshold */
lpm_nyet_threshold = 0xff;
@@ -1032,6 +1071,18 @@ static void dwc3_get_properties(struct dwc3 *dwc)
_threshold);
dwc->usb3_lpm_capable = device_property_read_bool(dev,
"snps,usb3_lpm_capable");
+   dwc->rx_thr_sel_prd = device_property_read_bool(dev,
+   "snps,rx_thr_sel_prd");
+   device_property_read_u8(dev, "snps,rx_thr_num_pkt_prd",
+   _thr_num_pkt_prd);
+   device_property_read_u8(dev, "snps,rx_max_burst_prd",
+   _max_burst_prd);
+   dwc->tx_thr_sel_prd = device_property_read_bool(dev,
+   "snps,tx_thr_sel_prd");
+   device_property_read_u8(dev, "snps,tx_thr_num_pkt_prd",
+   _thr_num_pkt_prd);
+   device_property_read_u8(dev, "snps,tx_max_burst_prd",
+   _max_burst_prd);
 
dwc->disable_scramble_quirk = device_property_read_bool(dev,
"snps,disable_scramble_quirk");
@@ -1079,6 +1130,12 @@ static void dwc3_get_properties(struct dwc3 *dwc)
dwc->hird_threshold = hird_threshold
| (dwc->is_utmi_l1_suspend << 4);
 
+   dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
+   dwc->rx_max_burst_prd = rx_max_burst_prd;
+
+   dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
+   dwc->tx_max_burst_prd = tx_max_burst_prd;
+
dwc->imod_interval = 0;
 }
 
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index ce10954afe49..83a74d10fa82 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -835,6 +835,10 @@ struct dwc3_scratchpad_array {
  * @test_mode_nr: test feature selector
  * @lpm_nyet_threshold: LPM NYET response threshold
  * @hird_threshold: HIRD threshold
+ * @rx_thr_num_pkt_prd: periodic ESS receive packet count
+ * @rx_max_burst_prd: max periodic ESS receive burst size
+ * @tx_thr_num_pkt_prd: periodic ESS transmit packet count
+ * @tx_max_burst_prd: max periodic ESS transmit burst size
  * @hsphy_interface: "utmi" or "ulpi"
  * @connected: true when we're connected to a host, false otherwise
  * @delayed_status: true when gadget driver asks for delayed status
@@ -853,6 +857,8 @@ struct dwc3_scratchpad_array {
  * 

[PATCH 03/15] usb: dwc3: Update DWC_usb31 GTXFIFOSIZ reg fields

[Thinh Nguyen]

Update two GTXFIFOSIZ bit fields for the DWC_usb31 controller. TXFDEP
is a 15-bit value instead of 16-bit value, and bit 15 is TXFRAMNUM.

The GTXFIFOSIZ register for DWC_usb31 is as follows:
 +---+---+--+
 | BITS  | Name  | Description  |
 +===+===+==+
 | 31:16 | TXFSTADDR | Transmit FIFOn RAM Start Address |
 | 15| TXFRAMNUM | Asynchronous/Periodic TXFIFO |
 | 14:0  | TXFDEP| TXFIFO Depth |
 +---+---+--+

Signed-off-by: Thinh Nguyen 
---
 drivers/usb/dwc3/core.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 4a4a4c98508c..6ebf7ddc547d 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -239,6 +239,8 @@
 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n)  ((n) << 1)
 
 /* Global TX Fifo Size Register */
+#define DWC3_USB31_GTXFIFOSIZ_TXFRAMNUMBIT(15) /* DWC_usb31 
only */
+#define DWC3_USB31_GTXFIFOSIZ_TXFDEF(n)((n) & 0x7fff)  /* DWC_usb31 
only */
 #define DWC3_GTXFIFOSIZ_TXFDEF(n)  ((n) & 0x)
 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n)   ((n) & 0x)
 
-- 
2.11.0

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[PATCH 00/15] usb: dwc3: Add new updates for DWC_usb31

[Thinh Nguyen]

This patch series adds new updates and some fixes for DWC_usb31.


Thinh Nguyen (15):
  usb: dwc3: Device SoftReset PHY synchonization delay
  usb: core: urb: Check SSP isoc ep comp descriptor
  usb: dwc3: Update DWC_usb31 GTXFIFOSIZ reg fields
  usb: dwc3: Check IP revision for GTXFIFOSIZ
  usb: dwc3: Add DWC_usb31 GRXTHRCFG bit fields
  usb: dwc3: gadget: Check IP revision for GRXTHRCFG
  usb: dwc3: Add DWC_usb31 GTXTHRCFG reg fields
  usb: dwc3: Make RX/TX threshold configurable
  usb: dwc3: Check for ESS TX/RX threshold config
  usb: dwc3: gadget: Set maxpacket size for ep0 IN
  usb: dwc3: ep0: Reset TRB counter for ep0 IN
  usb: dwc3: Dump LSP and BMU debug info
  usb: dwc3: Track DWC_usb31 VERSIONTYPE
  usb: dwc3: Add disabling of start_transfer failure quirk
  usb: dwc3: Add workaround for isoc start transfer failure

 Documentation/devicetree/bindings/usb/dwc3.txt |   9 ++
 drivers/usb/core/urb.c |   8 +
 drivers/usb/dwc3/core.c|  74 -
 drivers/usb/dwc3/core.h|  57 +++
 drivers/usb/dwc3/debugfs.c |   5 +
 drivers/usb/dwc3/ep0.c |   7 +-
 drivers/usb/dwc3/gadget.c  | 202 -
 7 files changed, 353 insertions(+), 9 deletions(-)

-- 
2.11.0

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[PATCH 06/15] usb: dwc3: gadget: Check IP revision for GRXTHRCFG

[Thinh Nguyen]

DWC_usb31 controller has a different UsbRxPktCnt bit fields from
GRXTHRCFG register. Check for DWC_usb31 IP revision to read the
appropriate value.

Signed-off-by: Thinh Nguyen 
---
 drivers/usb/dwc3/gadget.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 36ff281d59c6..bdf2a2014ebd 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -1858,7 +1858,11 @@ static int __dwc3_gadget_start(struct dwc3 *dwc)
 * bursts of data without going through any sort of endpoint throttling.
 */
reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
-   reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
+   if (dwc3_is_usb31(dwc))
+   reg &= ~DWC3_USB31_GRXTHRCFG_PKTCNTSEL;
+   else
+   reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
+
dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
 
dwc3_gadget_setup_nump(dwc);
-- 
2.11.0

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[PATCH 11/15] usb: dwc3: ep0: Reset TRB counter for ep0 IN

[Thinh Nguyen]

In control read transfer completion handler, the driver needs to reset
the TRB enqueue counter. Since there is one control endpoint structure
for each direction, we must also track the TRB enqueue counter for each
direction. Currently the driver only resets the TRB counter for control
OUT endpoint only. Check for the data direction and properly reset the
TRB counter from correct control endpoint.

Signed-off-by: Thinh Nguyen 
---
 drivers/usb/dwc3/ep0.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index fd3e7ad2eb0e..618b4260f0d9 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -858,7 +858,12 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
trb++;
trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
trace_dwc3_complete_trb(ep0, trb);
-   ep0->trb_enqueue = 0;
+
+   if (r->direction)
+   dwc->eps[1]->trb_enqueue = 0;
+   else
+   dwc->eps[0]->trb_enqueue = 0;
+
dwc->ep0_bounced = false;
}
 
-- 
2.11.0

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[PATCH 04/15] usb: dwc3: Check IP revision for GTXFIFOSIZ

[Thinh Nguyen]

DWC_usb31 controller has different GTXFIFOSIZE bit field for TXFDEF.
Check for DWC_usb31 IP revision to read the appropriate bit fields.

Signed-off-by: Thinh Nguyen 
---
 drivers/usb/dwc3/gadget.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 639dd1b163a0..36ff281d59c6 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -2100,7 +2100,10 @@ static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, 
u8 total)
mdwidth /= 8;
 
size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num));
-   size = DWC3_GTXFIFOSIZ_TXFDEF(size);
+   if (dwc3_is_usb31(dwc))
+   size = DWC3_USB31_GTXFIFOSIZ_TXFDEF(size);
+   else
+   size = DWC3_GTXFIFOSIZ_TXFDEF(size);
 
/* FIFO Depth is in MDWDITH bytes. Multiply */
size *= mdwidth;
-- 
2.11.0

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[PATCH 08/15] usb: dwc3: Make RX/TX threshold configurable

[Thinh Nguyen]

DWC_usb31 periodic transfer at 48K+ bytes per interval may need
modification to the TX/RX packet threshold to achieve optimal result.
Add properties to make it configurable.

Cc: John Youn 
Signed-off-by: Thinh Nguyen 
---
 Documentation/devicetree/bindings/usb/dwc3.txt | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt 
b/Documentation/devicetree/bindings/usb/dwc3.txt
index 52fb41046b34..02dde83d02fa 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -55,6 +55,12 @@ Optional properties:
  - snps,quirk-frame-length-adjustment: Value for GFLADJ_30MHZ field of GFLADJ
register for post-silicon frame length adjustment when the
fladj_30mhz_sdbnd signal is invalid or incorrect.
+ - snps,rx_thr_sel_prd: set to enable periodic ESS RX packet threshold.
+ - snps,rx_thr_num_pkt_prd: periodic ESS RX packet threshold count.
+ - snps,rx_max_burst_prd: Max periodic ESS RX burst size.
+ - snps,tx_thr_sel_prd: set to enable periodic ESS TX packet threshold.
+ - snps,tx_thr_num_pkt_prd: periodic ESS TX packet threshold count.
+ - snps,tx_max_burst_prd: Max periodic ESS TX burst size.
 
  -  tx-fifo-resize: determines if the FIFO *has* to be reallocated.
 
-- 
2.11.0

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[PATCH 05/15] usb: dwc3: Add DWC_usb31 GRXTHRCFG bit fields

[Thinh Nguyen]

Add new GRXTHRCFG bit field macros for DWC_usb31. The GRXTHRCFG register
fields for DWC_usb31 is as follows:
 +---+--+--+
 | BITS  | Name | Description  |
 +===+==+==+
 | 31:27 | reserved |  |
 | 26| UsbRxPktCntSel   | Async ESS receive packet |
 |   |  | threshold enable |
 | 25:21 | UsbRxPktCnt  | Async ESS receive packet |
 |   |  | threshold count  |
 | 20:16 | UsbMaxRxBurstSize| Async ESS Max receive burst size |
 | 15| UsbRxThrNumPktSel_HS_Prd | HS high bandwidth periodic   |
 |   |  | receive packet threshold enable  |
 | 14:13 | UsbRxThrNumPkt_HS_Prd| HS high bandwidth periodic   |
 |   |  | receive packet threshold count   |
 | 12:11 | reserved |  |
 | 10| UsbRxThrNumPktSel_Prd| Periodic ESS receive packet  |
 |   |  | threshold enable |
 | 9:5   | UsbRxThrNumPkt_Prd   | Periodic ESS receive packet  |
 |   |  | threshold count  |
 | 4:0   | UsbMaxRxBurstSize_Prd| Max periodic ESS RX burst size   |
 +---+--+--+

Signed-off-by: Thinh Nguyen 
---
 drivers/usb/dwc3/core.h | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 6ebf7ddc547d..7c4ba7f74f27 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -171,6 +171,16 @@
 #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
 #define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29)
 
+/* Global RX Threshold Configuration Register for DWC_usb31 only */
+#define DWC3_USB31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16)
+#define DWC3_USB31_GRXTHRCFG_RXPKTCNT(n)   (((n) & 0x1f) << 21)
+#define DWC3_USB31_GRXTHRCFG_PKTCNTSEL BIT(26)
+#define DWC3_USB31_RXTHRNUMPKTSEL_HS_PRD   BIT(15)
+#define DWC3_USB31_RXTHRNUMPKT_HS_PRD(n)   (((n) & 0x3) << 13)
+#define DWC3_USB31_RXTHRNUMPKTSEL_PRD  BIT(10)
+#define DWC3_USB31_RXTHRNUMPKT_PRD(n)  (((n) & 0x1f) << 5)
+#define DWC3_USB31_MAXRXBURSTSIZE_PRD(n)   ((n) & 0x1f)
+
 /* Global Configuration Register */
 #define DWC3_GCTL_PWRDNSCALE(n)((n) << 19)
 #define DWC3_GCTL_U2RSTECN BIT(16)
-- 
2.11.0

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Re: xhci: Reset Renesas uPD72020x USB controller for 32-bit DMA issue

[Troy Kisky]

On 1/5/2018 1:10 AM, Marc Zyngier wrote:
> On 05/01/18 02:09, Troy Kisky wrote:
>> On 12/29/2017 3:34 AM, Marc Zyngier wrote:
>>> On Wed, 27 Dec 2017 20:37:07 +,
>>> Troy Kisky wrote:

 On 12/27/2017 2:37 AM, Marc Zyngier wrote:
> On Tue, 26 Dec 2017 21:57:58 +,
> Troy Kisky wrote:
>>
>> On 12/26/2017 1:52 PM, Troy Kisky wrote:
>>> On 12/25/2017 2:10 AM, Marc Zyngier wrote:
 On Sun, 24 Dec 2017 23:01:33 +,
 Troy Kisky wrote:
>
> commit 8466489ef5ba48272ba4fa4ea9f8f403306de4c7
> Author: Marc Zyngier 
> Date:   Tue Aug 1 20:11:08 2017 -0500
>
> xhci: Reset Renesas uPD72020x USB controller for 32-bit DMA issue
> ...
> ...
> ...
> --- a/drivers/usb/host/xhci-pci.c
> +++ b/drivers/usb/host/xhci-pci.c
> @@ -284,6 +284,13 @@ static int xhci_pci_probe(struct pci_dev *dev, 
> const struct pci_device_id *id)
>
> driver = (struct hc_driver *)id->driver_data;
>
> +   /* For some HW implementation, a XHCI reset is just not 
> enough... */
> +   if (usb_xhci_needs_pci_reset(dev)) {
> +   dev_info(>dev, "Resetting\n");
> +   if (pci_reset_function_locked(dev))
> +   dev_warn(>dev, "Reset failed");
> +   }
> +
> 
>
>
> This pci_reset_function_locked call, causes my i.mx6qp processor to
> hang. It no longer responds to the MAGIC_SYSRQ key (break on serial
> port).
>
>
> If I comment it out, things return to normal when testing on
> Linux-next (20171222).
>
> If you need more info, let me know.

 Well, for a start:

 - Does it fail with 4.13 or 4.14 too?
>>>
>>> v4.13-rc4 - good
>>> v4.13-rc5 - fail
>>> v4.13 - fail
>>> v4.14 - fail
>>>
>>>
>>>
 - Can you work out where it is locking up exactly (going slightly
   deeper than the pci_reset_function_locked() call)?
>>>
>>> With this patch
>>> diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
>>> index 05104bd2b611..8782945a9f70 100644
>>> --- a/drivers/usb/host/xhci.c
>>> +++ b/drivers/usb/host/xhci.c
>>> @@ -4808,8 +4808,10 @@ int xhci_gen_setup(struct usb_hcd *hcd, 
>>> xhci_get_quirks_t get_quirks)
>>>
>>> mutex_init(>mutex);
>>> xhci->cap_regs = hcd->regs;
>>> +   pr_err("%s: 1\n", __func__);
>>> xhci->op_regs = hcd->regs +
>>> HC_LENGTH(readl(>cap_regs->hc_capbase));
>>> +   pr_err("%s: 2\n", __func__);
>>> xhci->run_regs = hcd->regs +
>>> (readl(>cap_regs->run_regs_off) & RTSOFF_MASK);
>>> /* Cache read-only capability registers */
>>> _
>>>
>>> The last thing printed is
>>> [  OK  ] Reached target System Initialization.
>>> [  OK  ] Listening on D-Bus System Message Bus Socket.
>>> [  OK  ] Reached target Sockets.
>>> [  OK  ] Started Daily Cleanup of Temporary Directories.
>>> [   15.770319] xhci_gen_setup: 1
>
> OK, so it looks like the CPU is blocked reading from the
> device. Almost feels like the device is not clocked (that's about the
> only reason why the CPU would be stuck on such a read).
>
>>>
>>>
 - Do you get the symptom at boot time?
>>>
>>> Boot
>>>
 On resume? Is the USB driver
   compiled as a module or built-in?
>>>
>>>   INSTALL drivers/usb/host/xhci-hcd.ko
>>>   INSTALL drivers/usb/host/xhci-pci.ko
>>>   INSTALL drivers/usb/host/xhci-renesas.ko
>>>
 - What is your exact platform (something a bit more precise than just
   i.MX6...)?
>>>
>>> It is a custom board not in mainline. It does need to load firmware.
>>>
>>> I tried moving pci_reset_function_locked before 
>>> renesas_check_if_fw_dl_is_needed
>>> but that did not help.
>>>
>>
>>
>>
>> Which I should say I also have this patch
>>
>>
>> commit 01ac5cfd811088b5fe8c97f28f96086e30393c66
>> Author: Christian Lamparter 
>> Date:   Wed Jun 8 00:14:57 2016 +0200
>>
>> usb: xhci: handle uPD720201 and uPD720202 w/o ROM
>>
>> This patch adds a firmware check for the uPD720201K8-711-BAC-A
>> and uPD720202K8-711-BAA-A variant. Both of these chips are listed
>> in Renesas' R19UH0078EJ0500 Rev.5.00 "User's Manual: Hardware" as
>> devices which need a firmware in order to work as they do not have
>> support to load the firmware from an external ROM.
>>
>> __
>>
>> Sorry for not saying earlier.
>
> That's a very 

[PATCH v2 2/3] dt-bindings: usb: renesas_usbhs: Add support for RZ/A1

[Chris Brandt]

Document support for RZ/A1 SoCs

Signed-off-by: Chris Brandt 
Reviewed-by: Geert Uytterhoeven 
---
v2:
 * Added Reviewed-by
---
 Documentation/devicetree/bindings/usb/renesas_usbhs.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt 
b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
index 47394ab788e3..d060172f1529 100644
--- a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
+++ b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
@@ -13,8 +13,10 @@ Required properties:
- "renesas,usbhs-r8a7795" for r8a7795 (R-Car H3) compatible device
- "renesas,usbhs-r8a7796" for r8a7796 (R-Car M3-W) compatible device
- "renesas,usbhs-r8a77995" for r8a77995 (R-Car D3) compatible device
+   - "renesas,usbhs-r7s72100" for r7s72100 (RZ/A1) compatible device
- "renesas,rcar-gen2-usbhs" for R-Car Gen2 or RZ/G1 compatible devices
- "renesas,rcar-gen3-usbhs" for R-Car Gen3 compatible device
+   - "renesas,rza1-usbhs" for RZ/A1 compatible device
 
When compatible with the generic version, nodes must list the
SoC-specific version corresponding to the platform first followed
-- 
2.15.1


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[PATCH v2 0/3] usb: renesas_usbhs: Add RZ/A1 support

[Chris Brandt]

This series adds RZ/A1 gadget support to the renesas_usbhs driver.
Basically, it's almost the same HW as the R-Car (and SH) parts.
The only real difference is the some extra registers for the PHY.

This was tested on an RSK board by connecting to a PC as an
Ethernet CDC gadget.

v2:
 * Node name is now generic 'usb@'
 * GIC_SPI (73-32) is now just GIC_SPI 41
 * All hex number are lower case
 * Added Reviewed-by

Chris Brandt (3):
  usb: renesas_usbhs: Add support for RZ/A1
  dt-bindings: usb: renesas_usbhs: Add support for RZ/A1
  ARM: dts: r7s72100: add USB device to device tree

 .../devicetree/bindings/usb/renesas_usbhs.txt  |  2 +
 arch/arm/boot/dts/r7s72100.dtsi| 20 +
 drivers/usb/renesas_usbhs/Makefile |  2 +-
 drivers/usb/renesas_usbhs/common.c | 17 +++
 drivers/usb/renesas_usbhs/common.h |  6 +++
 drivers/usb/renesas_usbhs/rza.c| 52 ++
 drivers/usb/renesas_usbhs/rza.h|  4 ++
 include/linux/usb/renesas_usbhs.h  |  1 +
 8 files changed, 103 insertions(+), 1 deletion(-)
 create mode 100644 drivers/usb/renesas_usbhs/rza.c
 create mode 100644 drivers/usb/renesas_usbhs/rza.h

-- 
2.15.1


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[PATCH v2 3/3] ARM: dts: r7s72100: add USB device to device tree

[Chris Brandt]

Add USB device support.

Signed-off-by: Chris Brandt 
Reviewed-by: Geert Uytterhoeven 
---
v2:
 * Node name is now generic 'usb@'
 * GIC_SPI (73-32) is now just GIC_SPI 41
 * All hex number are lower case
 * Added Reviewed-by
---
 arch/arm/boot/dts/r7s72100.dtsi | 20 
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index ab9645a42eca..f863f74b1b30 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -667,4 +667,24 @@
power-domains = <_clocks>;
status = "disabled";
};
+
+   usbhs0: usb@e801 {
+   compatible = "renesas,usbhs-r7s72100";
+   reg = <0xe801 0x1a0>;
+   interrupts = ;
+   clocks = <_clks R7S72100_CLK_USB0>;
+   renesas,buswait = <4>;
+   power-domains = <_clocks>;
+   status = "disabled";
+   };
+
+   usbhs1: usb@e8207000 {
+   compatible = "renesas,usbhs-r7s72100";
+   reg = <0xe8207000 0x1a0>;
+   interrupts = ;
+   clocks = <_clks R7S72100_CLK_USB1>;
+   renesas,buswait = <4>;
+   power-domains = <_clocks>;
+   status = "disabled";
+   };
 };
-- 
2.15.1


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[PATCH v2 1/3] usb: renesas_usbhs: Add support for RZ/A1

[Chris Brandt]

This patch adds the capability to support RZ/A1 SoCs.

Signed-off-by: Chris Brandt 
---
 drivers/usb/renesas_usbhs/Makefile |  2 +-
 drivers/usb/renesas_usbhs/common.c | 17 +
 drivers/usb/renesas_usbhs/common.h |  6 +
 drivers/usb/renesas_usbhs/rza.c| 52 ++
 drivers/usb/renesas_usbhs/rza.h|  4 +++
 include/linux/usb/renesas_usbhs.h  |  1 +
 6 files changed, 81 insertions(+), 1 deletion(-)
 create mode 100644 drivers/usb/renesas_usbhs/rza.c
 create mode 100644 drivers/usb/renesas_usbhs/rza.h

diff --git a/drivers/usb/renesas_usbhs/Makefile 
b/drivers/usb/renesas_usbhs/Makefile
index fac147a3ad23..5c5b51bb48ef 100644
--- a/drivers/usb/renesas_usbhs/Makefile
+++ b/drivers/usb/renesas_usbhs/Makefile
@@ -5,7 +5,7 @@
 
 obj-$(CONFIG_USB_RENESAS_USBHS)+= renesas_usbhs.o
 
-renesas_usbhs-y:= common.o mod.o pipe.o fifo.o rcar2.o 
rcar3.o
+renesas_usbhs-y:= common.o mod.o pipe.o fifo.o rcar2.o 
rcar3.o rza.o
 
 ifneq ($(CONFIG_USB_RENESAS_USBHS_HCD),)
renesas_usbhs-y += mod_host.o
diff --git a/drivers/usb/renesas_usbhs/common.c 
b/drivers/usb/renesas_usbhs/common.c
index c5289b3ecf8d..2abefd3d6050 100644
--- a/drivers/usb/renesas_usbhs/common.c
+++ b/drivers/usb/renesas_usbhs/common.c
@@ -17,6 +17,7 @@
 #include "common.h"
 #include "rcar2.h"
 #include "rcar3.h"
+#include "rza.h"
 
 /*
  * image of renesas_usbhs
@@ -480,6 +481,10 @@ static const struct of_device_id usbhs_of_match[] = {
.compatible = "renesas,usbhs-r8a77995",
.data = (void *)USBHS_TYPE_RCAR_GEN3_WITH_PLL,
},
+   {
+   .compatible = "renesas,usbhs-r7s72100",
+   .data = (void *)USBHS_TYPE_RZA1,
+   },
{
.compatible = "renesas,rcar-gen2-usbhs",
.data = (void *)USBHS_TYPE_RCAR_GEN2,
@@ -488,6 +493,10 @@ static const struct of_device_id usbhs_of_match[] = {
.compatible = "renesas,rcar-gen3-usbhs",
.data = (void *)USBHS_TYPE_RCAR_GEN3,
},
+   {
+   .compatible = "renesas,rza1-usbhs",
+   .data = (void *)USBHS_TYPE_RZA1,
+   },
{ },
 };
 MODULE_DEVICE_TABLE(of, usbhs_of_match);
@@ -520,6 +529,11 @@ static struct renesas_usbhs_platform_info 
*usbhs_parse_dt(struct device *dev)
dparam->pipe_size = ARRAY_SIZE(usbhsc_new_pipe);
}
 
+   if (dparam->type == USBHS_TYPE_RZA1) {
+   dparam->pipe_configs = usbhsc_new_pipe;
+   dparam->pipe_size = ARRAY_SIZE(usbhsc_new_pipe);
+   }
+
return info;
 }
 
@@ -591,6 +605,9 @@ static int usbhs_probe(struct platform_device *pdev)
dev_err(>dev, "no notifier registered\n");
}
break;
+   case USBHS_TYPE_RZA1:
+   priv->pfunc = usbhs_rza1_ops;
+   break;
default:
if (!info->platform_callback.get_id) {
dev_err(>dev, "no platform callbacks");
diff --git a/drivers/usb/renesas_usbhs/common.h 
b/drivers/usb/renesas_usbhs/common.h
index c9747f064601..f619afeae2b8 100644
--- a/drivers/usb/renesas_usbhs/common.h
+++ b/drivers/usb/renesas_usbhs/common.h
@@ -98,6 +98,7 @@ struct usbhs_priv;
 #define D2FIFOCTR  0x00F2  /* for R-Car Gen2 */
 #define D3FIFOSEL  0x00F4  /* for R-Car Gen2 */
 #define D3FIFOCTR  0x00F6  /* for R-Car Gen2 */
+#define SUSPMODE   0x0102  /* for RZ/A */
 
 /* SYSCFG */
 #define SCKE   (1 << 10)   /* USB Module Clock Enable */
@@ -106,6 +107,8 @@ struct usbhs_priv;
 #define DRPD   (1 << 5)/* D+ Line/D- Line Resistance Control */
 #define DPRPU  (1 << 4)/* D+ Line Resistance Control */
 #define USBE   (1 << 0)/* USB Module Operation Enable */
+#define UCKSEL (1 << 2)/* Clock Select for RZ/A1 */
+#define UPLLE  (1 << 1)/* USB PLL Enable for RZ/A1 */
 
 /* DVSTCTR */
 #define EXTLP  (1 << 10)   /* Controls the EXTLP pin output state */
@@ -233,6 +236,9 @@ struct usbhs_priv;
 #define USBSPD_SPEED_FULL  0x2
 #define USBSPD_SPEED_HIGH  0x3
 
+/* SUSPMODE */
+#define SUSPM  (1 << 14)   /* SuspendM Control */
+
 /*
  * struct
  */
diff --git a/drivers/usb/renesas_usbhs/rza.c b/drivers/usb/renesas_usbhs/rza.c
new file mode 100644
index ..b76e836d2c3d
--- /dev/null
+++ b/drivers/usb/renesas_usbhs/rza.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-1.0+
+/*
+ * Renesas USB driver RZ/A initialization and power control
+ *
+ * Copyright (C) 2018 Chris Brandt
+ * Copyright (C) 2018 Renesas Electronics Corporation
+ */
+
+#include 
+#include 
+#include 
+#include "common.h"
+#include "rza.h"
+
+static int usbhs_rza1_hardware_init(struct platform_device *pdev)
+{
+   struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
+   struct device_node *usb_x1_clk, 

Re: xhci: Reset Renesas uPD72020x USB controller for 32-bit DMA issue

[Troy Kisky]

On 1/5/2018 1:10 AM, Marc Zyngier wrote:
> On 05/01/18 02:09, Troy Kisky wrote:
>> On 12/29/2017 3:34 AM, Marc Zyngier wrote:
>>> On Wed, 27 Dec 2017 20:37:07 +,
>>> Troy Kisky wrote:

 On 12/27/2017 2:37 AM, Marc Zyngier wrote:
> On Tue, 26 Dec 2017 21:57:58 +,
> Troy Kisky wrote:
>>
>> On 12/26/2017 1:52 PM, Troy Kisky wrote:
>>> On 12/25/2017 2:10 AM, Marc Zyngier wrote:
 On Sun, 24 Dec 2017 23:01:33 +,
 Troy Kisky wrote:
>
> commit 8466489ef5ba48272ba4fa4ea9f8f403306de4c7
> Author: Marc Zyngier 
> Date:   Tue Aug 1 20:11:08 2017 -0500
>
> xhci: Reset Renesas uPD72020x USB controller for 32-bit DMA issue
> ...
> ...
> ...
> --- a/drivers/usb/host/xhci-pci.c
> +++ b/drivers/usb/host/xhci-pci.c
> @@ -284,6 +284,13 @@ static int xhci_pci_probe(struct pci_dev *dev, 
> const struct pci_device_id *id)
>
> driver = (struct hc_driver *)id->driver_data;
>
> +   /* For some HW implementation, a XHCI reset is just not 
> enough... */
> +   if (usb_xhci_needs_pci_reset(dev)) {
> +   dev_info(>dev, "Resetting\n");
> +   if (pci_reset_function_locked(dev))
> +   dev_warn(>dev, "Reset failed");
> +   }
> +
> 
>
>
> This pci_reset_function_locked call, causes my i.mx6qp processor to
> hang. It no longer responds to the MAGIC_SYSRQ key (break on serial
> port).
>
>
> If I comment it out, things return to normal when testing on
> Linux-next (20171222).
>
> If you need more info, let me know.

 Well, for a start:

 - Does it fail with 4.13 or 4.14 too?
>>>
>>> v4.13-rc4 - good
>>> v4.13-rc5 - fail
>>> v4.13 - fail
>>> v4.14 - fail
>>>
>>>
>>>
 - Can you work out where it is locking up exactly (going slightly
   deeper than the pci_reset_function_locked() call)?
>>>
>>> With this patch
>>> diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
>>> index 05104bd2b611..8782945a9f70 100644
>>> --- a/drivers/usb/host/xhci.c
>>> +++ b/drivers/usb/host/xhci.c
>>> @@ -4808,8 +4808,10 @@ int xhci_gen_setup(struct usb_hcd *hcd, 
>>> xhci_get_quirks_t get_quirks)
>>>
>>> mutex_init(>mutex);
>>> xhci->cap_regs = hcd->regs;
>>> +   pr_err("%s: 1\n", __func__);
>>> xhci->op_regs = hcd->regs +
>>> HC_LENGTH(readl(>cap_regs->hc_capbase));
>>> +   pr_err("%s: 2\n", __func__);
>>> xhci->run_regs = hcd->regs +
>>> (readl(>cap_regs->run_regs_off) & RTSOFF_MASK);
>>> /* Cache read-only capability registers */
>>> _
>>>
>>> The last thing printed is
>>> [  OK  ] Reached target System Initialization.
>>> [  OK  ] Listening on D-Bus System Message Bus Socket.
>>> [  OK  ] Reached target Sockets.
>>> [  OK  ] Started Daily Cleanup of Temporary Directories.
>>> [   15.770319] xhci_gen_setup: 1
>
> OK, so it looks like the CPU is blocked reading from the
> device. Almost feels like the device is not clocked (that's about the
> only reason why the CPU would be stuck on such a read).
>
>>>
>>>
 - Do you get the symptom at boot time?
>>>
>>> Boot
>>>
 On resume? Is the USB driver
   compiled as a module or built-in?
>>>
>>>   INSTALL drivers/usb/host/xhci-hcd.ko
>>>   INSTALL drivers/usb/host/xhci-pci.ko
>>>   INSTALL drivers/usb/host/xhci-renesas.ko
>>>
 - What is your exact platform (something a bit more precise than just
   i.MX6...)?
>>>
>>> It is a custom board not in mainline. It does need to load firmware.
>>>
>>> I tried moving pci_reset_function_locked before 
>>> renesas_check_if_fw_dl_is_needed
>>> but that did not help.
>>>
>>
>>
>>
>> Which I should say I also have this patch
>>
>>
>> commit 01ac5cfd811088b5fe8c97f28f96086e30393c66
>> Author: Christian Lamparter 
>> Date:   Wed Jun 8 00:14:57 2016 +0200
>>
>> usb: xhci: handle uPD720201 and uPD720202 w/o ROM
>>
>> This patch adds a firmware check for the uPD720201K8-711-BAC-A
>> and uPD720202K8-711-BAA-A variant. Both of these chips are listed
>> in Renesas' R19UH0078EJ0500 Rev.5.00 "User's Manual: Hardware" as
>> devices which need a firmware in order to work as they do not have
>> support to load the firmware from an external ROM.
>>
>> __
>>
>> Sorry for not saying earlier.
>
> That's a very 

Re: [v2 PATCH 5/6] dt-bindings: usb: mtk-xhci: update USB wakeup properties

[Rob Herring]

On Wed, Jan 03, 2018 at 04:53:21PM +0800, Chunfeng Yun wrote:
> Add two arguments in "mediatek,syscon-wakeup" to support multi
> wakeup glue layer between SSUSB and SPM, and use standard property
> "wakeup-source" to replace the private "mediatek,wakeup-src"
> 
> Signed-off-by: Chunfeng Yun 
> ---
>  .../devicetree/bindings/usb/mediatek,mtk-xhci.txt| 16 
> ++--
>  1 file changed, 10 insertions(+), 6 deletions(-)

Reviewed-by: Rob Herring 
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Re: [v2 PATCH 3/6] dt-bindings: usb: mtu3: update USB wakeup properties

[Rob Herring]

On Wed, Jan 03, 2018 at 04:53:19PM +0800, Chunfeng Yun wrote:
> Add two arguments in "mediatek,syscon-wakeup" to support multi
> wakeup glue layer between SSUSB and SPM, and use standard property
> "wakeup-source" to replace the private "mediatek,enable-wakeup"
> 
> Signed-off-by: Chunfeng Yun 
> ---
>  Documentation/devicetree/bindings/usb/mediatek,mtu3.txt | 15 ++-
>  1 file changed, 10 insertions(+), 5 deletions(-)

Reviewed-by: Rob Herring 

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Re: [RFC 0/2] Add driver for Xaptum ENF Access card (XAP-EA-00x)

[David R. Bild]

On Fri, Jan 5, 2018 at 8:41 AM, Greg Kroah-Hartman
 wrote:
> I've been a "bit" busy over the past few months, and haven't had the
> chance to review new drivers like this, for obvious reasons.
>
> Don't worry, the patches aren't lost, they are still in my queue.

That's what I figured --- just making sure. Thanks.

> Wait, I don't review RFC patch series, as obviously you don't think it's
> ready to be merged :)
>
> Care to redo this without that marking, if you really think it is ready?

Gotcha - I'll resend as a patch.

Thanks,
David
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Re: [RFC 0/2] Add driver for Xaptum ENF Access card (XAP-EA-00x)

[Greg Kroah-Hartman]

On Fri, Dec 22, 2017 at 11:16:18AM -0600, David R. Bild wrote:
> This series add a driver for the Xaptum ENF Access card line
> (XAP-EA-00x), a series of mini PCI-e cards containing a TPM 2.0 chip
> used to authenticate IoT devices and gateways.
> 
> The hardware is essentially a USB-SPI bridge and an SPI TPM 2.0
> chip. The first patch registers the bridge as an SPI controller and
> the TPM as an SPI device. The second patch performs the TPM platform
> initialization that would normally be done by the BIOS.
> 
> David R. Bild (2):
>   usb: misc: xapea00x: add driver for Xaptum ENF Access Card
>   usb: misc: xapea00x: perform platform initialization of TPM

Wait, I don't review RFC patch series, as obviously you don't think it's
ready to be merged :)

Care to redo this without that marking, if you really think it is ready?

thanks,

greg k-h
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Re: [RFC 0/2] Add driver for Xaptum ENF Access card (XAP-EA-00x)

[Greg Kroah-Hartman]

On Fri, Jan 05, 2018 at 08:29:58AM -0600, David R. Bild wrote:
> On Fri, Dec 22, 2017 at 11:16 AM, David R. Bild  wrote:
> >
> > This series add a driver for the Xaptum ENF Access card line
> > (XAP-EA-00x), a series of mini PCI-e cards containing a TPM 2.0 chip
> > used to authenticate IoT devices and gateways.
> 
> Greg,
> 
> Do I need to do anything else to get this new driver queued up for
> review?  Not trying to rush things --- just making sure I haven't
> missed a step or submitted to the wrong place.

I've been a "bit" busy over the past few months, and haven't had the
chance to review new drivers like this, for obvious reasons.  Hopefully
will catch up with my pending queue in a week or so, if this nonsense
dies down...

Don't worry, the patches aren't lost, they are still in my queue.  And
of course, if others can review it, that would be great and make it
easier for me as well.

thanks,

greg k-h
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Re: [RFC 0/2] Add driver for Xaptum ENF Access card (XAP-EA-00x)

[David R. Bild]

On Fri, Dec 22, 2017 at 11:16 AM, David R. Bild  wrote:
>
> This series add a driver for the Xaptum ENF Access card line
> (XAP-EA-00x), a series of mini PCI-e cards containing a TPM 2.0 chip
> used to authenticate IoT devices and gateways.

Greg,

Do I need to do anything else to get this new driver queued up for
review?  Not trying to rush things --- just making sure I haven't
missed a step or submitted to the wrong place.

Thanks,
David
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RE: [PATCH 3/3] ARM: dts: r7s72100: add USB device to device tree

[Chris Brandt]

Hi Geert,

On Friday, January 05, 2018, Geert Uytterhoeven wrote:
> > But then...the number goes back to '73' when you look at it in
> > /proc/interrupts.
> 
> Having an identical number in /proc/interrupts is a coincidence.
> These numbers are virtual, and may change even across reboots.

I'm not talking about the id number (the 1st column). I'm talking 
about the 4th column.

$ uname -rs
Linux 4.15.0-rc5-8-g366d22ea091b
$ cat /proc/interrupts
   CPU0
 17:   2365 GIC-0 135 Edge  ostm
 18:  0 GIC-0 230 Level e8008000.serial:rx err
 19: 45 GIC-0 231 Level e8008000.serial:rx full
 20:194 GIC-0 232 Level e8008000.serial:tx empty
 21:  0 GIC-0 229 Level e8008000.serial:break
 24:  0 GIC-0 189 Level riic-tend
 25:  0 GIC-0 190 Edge  riic-rdrf
 26:  0 GIC-0 191 Edge  riic-tdre
 27:  0 GIC-0 192 Level riic-stop
 29:  0 GIC-0 194 Level riic-nack
 32:160 GIC-0 213 Level riic-tend
 33:160 GIC-0 214 Edge  riic-rdrf
 34:480 GIC-0 215 Edge  riic-tdre
 35:240 GIC-0 216 Level riic-stop
 37:  0 GIC-0 218 Level riic-nack
 40:  0 GIC-0 139 Level fcff.timer
 42:  0 GIC-0 305 Level e804e800.sd
 43: 52 GIC-0 306 Level e804e800.sd
 44:  0 GIC-0 307 Level e804e800.sd
 45:  0 GIC-0 308 Edge  sh-rtc period
 46:  0 GIC-0 309 Edge  sh-rtc carry
 47:  0 GIC-0 310 Edge  sh-rtc alarm
 48:  0 GIC-0  73 Level e801.usbhs
Err:  0


> > Any opinions
> 
> Not really, except that no single .dts(i) file seems to have "- 32".

Then I can be a pioneer of new software!!  ;)


I'll just change it back to a single number when I upstream code just to
be consistent.


Thanks,
Chris

Re: [PATCH 3/3] ARM: dts: r7s72100: add USB device to device tree

[Geert Uytterhoeven]

Hi Chris,

On Fri, Jan 5, 2018 at 1:54 PM, Chris Brandt  wrote:
> On Friday, January 05, 2018, Geert Uytterhoeven wrote:
>> > +   interrupts = ;
>>
>> "41", all other interrupt properties already have the SPI offset
>> subtracted?
>
> The actual HW vector number in the hardware manual is '73'.
> As you know, you need to subtract 32 for the number you use in the
> device tree.
> But then...the number goes back to '73' when you look at it in
> /proc/interrupts.

Having an identical number in /proc/interrupts is a coincidence.
These numbers are virtual, and may change even across reboots.

> So it was confusing to people on what number you needed to use.
>
> Therefore in the RZ/A1 BSP, I was doing (xx-32) so at least people could
> see the relationship between what's in the hardware manual and what
> gets put into the device tree.
>
> So, if doing (73-32) looks wrong, I can change it back to '41' for the
> upstream version.
>
> Any opinions

Not really, except that no single .dts(i) file seems to have "- 32".

Note that e.g. the R-Car Gen3 manuals do list both "interrupt ID"
and "SGI, PPI, or SPI No" in the documentation for INTC-AP.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
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RE: [PATCH 3/3] ARM: dts: r7s72100: add USB device to device tree

[Chris Brandt]

Hi Geert,

Thanks for the review.

On Friday, January 05, 2018, Geert Uytterhoeven wrote:
> > +   interrupts = ;
> 
> "41", all other interrupt properties already have the SPI offset
> subtracted?

The actual HW vector number in the hardware manual is '73'.
As you know, you need to subtract 32 for the number you use in the 
device tree.
But then...the number goes back to '73' when you look at it in 
/proc/interrupts.

So it was confusing to people on what number you needed to use.

Therefore in the RZ/A1 BSP, I was doing (xx-32) so at least people could
see the relationship between what's in the hardware manual and what 
gets put into the device tree.

So, if doing (73-32) looks wrong, I can change it back to '41' for the 
upstream version.


Any opinions


Chris

RE: [PATCH 3/3] ARM: dts: r7s72100: add USB device to device tree

[Chris Brandt]

On Friday, January 05, 2018, Sergei Shtylyov wrote:
> > +   usbhs0: usbhs@e801 {
> 
> The node names should be generic, i.e "usb@e801".
> 
> > +   compatible = "renesas,usbhs-r7s72100";
> > +   reg = <0xe801 0x1A0>;
> 
> Lowercase in the hex values, please be consistent...
> 
> > +   interrupts = ;
> > +   clocks = <_clks R7S72100_CLK_USB0>;
> > +   renesas,buswait = <4>;
> > +   power-domains = <_clocks>;
> > +   status = "disabled";
> > +   };
> > +
> > +   usbhs1: usbhs@e8207000 {
> > +   compatible = "renesas,usbhs-r7s72100";
> > +   reg = <0xe8207000 0x1A0>;
> > +   interrupts = ;
> > +   clocks = <_clks R7S72100_CLK_USB1>;
> > +   renesas,buswait = <4>;
> > +   power-domains = <_clocks>;
> > +   status = "disabled";
> > +   };
> >   };
> 
> The same comments for the 2nd device.

Thank you for the review.

I'll make the changes and resubmit.

Chris

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Re: [PATCH v4 14/16] phy: Add USB speed related PHY modes

[Kishon Vijay Abraham I]

Hi,

On Wednesday 03 January 2018 04:58 PM, Manu Gautam wrote:
> Add following USB speed related PHY modes:
> LS (Low Speed), FS (Full Speed), HS (High Speed), SS (Super Speed)
> 
> Speed related information is required by some QCOM PHY drivers
> to program PHY monitor resume/remote-wakeup events in suspended
> state. Speed is needed in order to set correct polarity of wakeup
> events for detection. E.g. QUSB2 PHY monitors DP/DM line state
> depending on whether speed is LS or FS/HS to detect resume.
> Similarly QMP USB3 PHY in SS mode should monitor RX terminations
> attach/detach and LFPS events depending on SSPHY is active or not.
> 
> Signed-off-by: Manu Gautam 
> ---
>  drivers/phy/phy-core.c  | 15 +++
>  include/linux/phy/phy.h | 32 
>  2 files changed, 39 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
> index b4964b0..e4f0525 100644
> --- a/drivers/phy/phy-core.c
> +++ b/drivers/phy/phy-core.c
> @@ -357,6 +357,21 @@ int phy_set_mode(struct phy *phy, enum phy_mode mode)
>  }
>  EXPORT_SYMBOL_GPL(phy_set_mode);
>  
> +enum phy_mode phy_get_mode(struct phy *phy)
> +{
> + enum phy_mode ret;
> +
> + if (!phy || !phy->ops->get_mode)
> + return PHY_MODE_INVALID;
> +
> + mutex_lock(>mutex);
> + ret = phy->ops->get_mode(phy);

Since get_mode only has to return the phy mode, there is no need for an ops
here. Just add phy_mode in phy_attrs in set_mode and return it here.

Thanks
Kishon
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Re: [GIT PULL] Qualcomm ARM64 Defconfig updates for 4.16

[Arnd Bergmann]

On Mon, Jan 1, 2018 at 7:53 AM, Andy Gross  wrote:
> The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
>
>   Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
>
> are available in the git repository at:
>
>   git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git 
> tags/qcom-arm64-defconfig-for-4.16
>
> for you to fetch changes up to d2fa1f37d21bf9729ae9ee79cb6bfc8de1f0a9a4:
>
>   arm64: defconfig: remove CONFIG_USB_QCOM_8X16_PHY (2017-12-21 13:28:11 
> -0600)
>
> 
> Qualcomm ARM64 Based defconfig Updates for v4.16
>
> * Remove legacy QCOM config options
>
> 
> Alex Elder (3):
>   arm64: defconfig: remove CONFIG_USB_EHCI_MSM
>   arm64: defconfig: remove CONFIG_USB_MSM_OTG
>   arm64: defconfig: remove CONFIG_USB_QCOM_8X16_PHY

Thanks for taking care of this, merged into next/soc.

I wonder what the long-term plan is for the other drivers/usb/phy drivers now
that one more has been removed.
I just checked what's left there and found:

a) many users of usb-nop-xceiv
b) a few drivers in use on actively maintained platforms (ti,am335x-usb-phy,
ti,twl6030-usb, ti,keystone-usbphy, fsl,imx23-usbphy,
nvidia,tegra20-usb-phy)
c) some more drivers used only by very old platforms (fsl-usb2-otg, gpio-vbus,
mv-otg, isp1301, isp1301_omap, omap_otg, tahvo-usb)

I assume nobody is touching the ones in category c) any more, but should
we encourage the ones using category a) and b) to get replaced with
drivers/phy/ drivers like the Qualcomm ones were?

 Arnd
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[PATCH 1/4] arm: dts: ls1021a: Enable usb3-lpm-capable for usb3 node

[Ran Wang]

Enable USB3 HW LPM feature for ls1021a and active patch for
snps erratum A-010131. It will disable U1/U2 temperary when
initiate U3 request.

Signed-off-by: Ran Wang 
---
 arch/arm/boot/dts/ls1021a.dtsi |2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index f81fad2..21a4488 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -709,6 +709,8 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+   usb3-lpm-capable;
+   snps,dis-u1u2-when-u3-quirk;
};
 
pcie@340 {
-- 
1.7.1

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[PATCH 2/4] arm64: dts: ls1043a: Enable usb3-lpm-capable for usb3 node

[Ran Wang]

Enable USB3 HW LPM feature for ls1043a and active patch for
snps erratum A-010131. It will disable U1/U2 temperary when
initiate U3 request.

Signed-off-by: Ran Wang 
---
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |6 ++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index e4fed04..686c7db 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -698,6 +698,8 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+   usb3-lpm-capable;
+   snps,dis-u1u2-when-u3-quirk;
};
 
usb1: usb3@300 {
@@ -707,6 +709,8 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+   usb3-lpm-capable;
+   snps,dis-u1u2-when-u3-quirk;
};
 
usb2: usb3@310 {
@@ -716,6 +720,8 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+   usb3-lpm-capable;
+   snps,dis-u1u2-when-u3-quirk;
};
 
sata: sata@320 {
-- 
1.7.1

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[PATCH 3/4] arm64: dts: ls1046a: Enable usb3-lpm-capable for usb3 node

[Ran Wang]

Enable USB3 HW LPM feature for ls1046a and active patch for
snps erratum A-010131. It will disable U1/U2 temperary when
initiate U3 request.

Signed-off-by: Ran Wang 
---
 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi |6 ++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index c115f17..07ca420 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -611,6 +611,8 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+   usb3-lpm-capable;
+   snps,dis-u1u2-when-u3-quirk;
};
 
usb1: usb@300 {
@@ -620,6 +622,8 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+   usb3-lpm-capable;
+   snps,dis-u1u2-when-u3-quirk;
};
 
usb2: usb@310 {
@@ -629,6 +633,8 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+   usb3-lpm-capable;
+   snps,dis-u1u2-when-u3-quirk;
};
 
sata: sata@320 {
-- 
1.7.1

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[PATCH 4/4] xHCI: Handle dwc3 erratum on USB3 HW LPM feature.

[Ran Wang]

Synopsys STARS ticket: 9969472(A-010131)

Description: This erratum is applicable for the USB 3.0 Super
Speed host mode operation. When the U2 timer expires while in
U1 mode, the USB 3.0 controller completes a U1->U2 entry operation
lasting three mac3_clk (24 ns). If the xHCI driver issues a
U3 request during this operation, thecontroller drops this request.

Impact: The controller ignores the request when the xHCI driver
programs the U3 entry (PORTSC.PLS = U3).

Workaround:
1. Before initiating U3 entry, save PORTPMSC.
2. Disable U2 entry by programming PORTPMSC[U2 Timeout] = h'FF.
3. After U3 entry, re-enable the U2 timer by programming PORTPMSC
with the value saved in Step 1.

Signed-off-by: Ran Wang 
---
 drivers/usb/host/xhci-hub.c  |   22 ++
 drivers/usb/host/xhci-plat.c |6 +-
 drivers/usb/host/xhci.h  |1 +
 3 files changed, 28 insertions(+), 1 deletions(-)

diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c
index f070f94..a61185e 100644
--- a/drivers/usb/host/xhci-hub.c
+++ b/drivers/usb/host/xhci-hub.c
@@ -676,12 +676,34 @@ void xhci_set_link_state(struct xhci_hcd *xhci, __le32 
__iomem **port_array,
int port_id, u32 link_state)
 {
u32 temp;
+   u32 portpmsc_u2_backup = 0;
+
+   /* Backup U2 timeout info before initiating U3 entry erratum A-010131 */
+   if (xhci->shared_hcd->speed >= HCD_USB3 &&
+   link_state == USB_SS_PORT_LS_U3 &&
+   (xhci->quirks & XHCI_DIS_U1U2_WHEN_U3)) {
+   portpmsc_u2_backup = readl(port_array[port_id] + PORTPMSC);
+   portpmsc_u2_backup &= PORT_U2_TIMEOUT_MASK;
+   temp = readl(port_array[port_id] + PORTPMSC);
+   temp |= PORT_U2_TIMEOUT_MASK;
+   writel(temp, port_array[port_id] + PORTPMSC);
+   }
 
temp = readl(port_array[port_id]);
temp = xhci_port_state_to_neutral(temp);
temp &= ~PORT_PLS_MASK;
temp |= PORT_LINK_STROBE | link_state;
writel(temp, port_array[port_id]);
+
+   /* Restore U2 timeout info after U3 entry complete */
+   if (xhci->shared_hcd->speed >= HCD_USB3 &&
+   link_state == USB_SS_PORT_LS_U3 &&
+   (xhci->quirks & XHCI_DIS_U1U2_WHEN_U3)) {
+   temp = readl(port_array[port_id] + PORTPMSC);
+   temp &= ~PORT_U2_TIMEOUT_MASK;
+   temp |= portpmsc_u2_backup;
+   writel(temp, port_array[port_id] + PORTPMSC);
+   }
 }
 
 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
index 1969e56..616c56e 100644
--- a/drivers/usb/host/xhci-plat.c
+++ b/drivers/usb/host/xhci-plat.c
@@ -266,8 +266,12 @@ static int xhci_plat_probe(struct platform_device *pdev)
if (device_property_read_bool(sysdev, "usb2-lpm-disable"))
xhci->quirks |= XHCI_HW_LPM_DISABLE;
 
-   if (device_property_read_bool(sysdev, "usb3-lpm-capable"))
+   if (device_property_read_bool(sysdev, "usb3-lpm-capable")) {
xhci->quirks |= XHCI_LPM_SUPPORT;
+   if (device_property_read_bool(sysdev,
+   "snps,dis-u1u2-when-u3-quirk"))
+   xhci->quirks |= XHCI_DIS_U1U2_WHEN_U3;
+   }
 
if (device_property_read_bool(>dev, "quirk-broken-port-ped"))
xhci->quirks |= XHCI_BROKEN_PORT_PED;
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index b966cd8..9704779 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1835,6 +1835,7 @@ struct xhci_hcd {
 /* Reserved. It was XHCI_U2_DISABLE_WAKE */
 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL(1 << 28)
 #define XHCI_HW_LPM_DISABLE(1 << 29)
+#define XHCI_DIS_U1U2_WHEN_U3 (1 << 30)
 
unsigned intnum_active_eps;
unsigned intlimit_active_eps;
-- 
1.7.1

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Re: [PATCH 3/3] ARM: dts: r7s72100: add USB device to device tree

[Simon Horman]

On Thu, Jan 04, 2018 at 03:01:50PM -0500, Chris Brandt wrote:
> Add USB device support.
> 
> Signed-off-by: Chris Brandt 

Hi Chris,

it looks like there have been some requests for (minor) changes to this
patch. Please consider addressing those and reposting.
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Re: xhci: Reset Renesas uPD72020x USB controller for 32-bit DMA issue

[Marc Zyngier]

On 05/01/18 02:09, Troy Kisky wrote:
> On 12/29/2017 3:34 AM, Marc Zyngier wrote:
>> On Wed, 27 Dec 2017 20:37:07 +,
>> Troy Kisky wrote:
>>>
>>> On 12/27/2017 2:37 AM, Marc Zyngier wrote:
 On Tue, 26 Dec 2017 21:57:58 +,
 Troy Kisky wrote:
>
> On 12/26/2017 1:52 PM, Troy Kisky wrote:
>> On 12/25/2017 2:10 AM, Marc Zyngier wrote:
>>> On Sun, 24 Dec 2017 23:01:33 +,
>>> Troy Kisky wrote:

 commit 8466489ef5ba48272ba4fa4ea9f8f403306de4c7
 Author: Marc Zyngier 
 Date:   Tue Aug 1 20:11:08 2017 -0500

 xhci: Reset Renesas uPD72020x USB controller for 32-bit DMA issue
 ...
 ...
 ...
 --- a/drivers/usb/host/xhci-pci.c
 +++ b/drivers/usb/host/xhci-pci.c
 @@ -284,6 +284,13 @@ static int xhci_pci_probe(struct pci_dev *dev, 
 const struct pci_device_id *id)

 driver = (struct hc_driver *)id->driver_data;

 +   /* For some HW implementation, a XHCI reset is just not 
 enough... */
 +   if (usb_xhci_needs_pci_reset(dev)) {
 +   dev_info(>dev, "Resetting\n");
 +   if (pci_reset_function_locked(dev))
 +   dev_warn(>dev, "Reset failed");
 +   }
 +
 


 This pci_reset_function_locked call, causes my i.mx6qp processor to
 hang. It no longer responds to the MAGIC_SYSRQ key (break on serial
 port).


 If I comment it out, things return to normal when testing on
 Linux-next (20171222).

 If you need more info, let me know.
>>>
>>> Well, for a start:
>>>
>>> - Does it fail with 4.13 or 4.14 too?
>>
>> v4.13-rc4 - good
>> v4.13-rc5 - fail
>> v4.13 - fail
>> v4.14 - fail
>>
>>
>>
>>> - Can you work out where it is locking up exactly (going slightly
>>>   deeper than the pci_reset_function_locked() call)?
>>
>> With this patch
>> diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
>> index 05104bd2b611..8782945a9f70 100644
>> --- a/drivers/usb/host/xhci.c
>> +++ b/drivers/usb/host/xhci.c
>> @@ -4808,8 +4808,10 @@ int xhci_gen_setup(struct usb_hcd *hcd, 
>> xhci_get_quirks_t get_quirks)
>>
>> mutex_init(>mutex);
>> xhci->cap_regs = hcd->regs;
>> +   pr_err("%s: 1\n", __func__);
>> xhci->op_regs = hcd->regs +
>> HC_LENGTH(readl(>cap_regs->hc_capbase));
>> +   pr_err("%s: 2\n", __func__);
>> xhci->run_regs = hcd->regs +
>> (readl(>cap_regs->run_regs_off) & RTSOFF_MASK);
>> /* Cache read-only capability registers */
>> _
>>
>> The last thing printed is
>> [  OK  ] Reached target System Initialization.
>> [  OK  ] Listening on D-Bus System Message Bus Socket.
>> [  OK  ] Reached target Sockets.
>> [  OK  ] Started Daily Cleanup of Temporary Directories.
>> [   15.770319] xhci_gen_setup: 1

 OK, so it looks like the CPU is blocked reading from the
 device. Almost feels like the device is not clocked (that's about the
 only reason why the CPU would be stuck on such a read).

>>
>>
>>> - Do you get the symptom at boot time?
>>
>> Boot
>>
>>> On resume? Is the USB driver
>>>   compiled as a module or built-in?
>>
>>   INSTALL drivers/usb/host/xhci-hcd.ko
>>   INSTALL drivers/usb/host/xhci-pci.ko
>>   INSTALL drivers/usb/host/xhci-renesas.ko
>>
>>> - What is your exact platform (something a bit more precise than just
>>>   i.MX6...)?
>>
>> It is a custom board not in mainline. It does need to load firmware.
>>
>> I tried moving pci_reset_function_locked before 
>> renesas_check_if_fw_dl_is_needed
>> but that did not help.
>>
>
>
>
> Which I should say I also have this patch
>
>
> commit 01ac5cfd811088b5fe8c97f28f96086e30393c66
> Author: Christian Lamparter 
> Date:   Wed Jun 8 00:14:57 2016 +0200
>
> usb: xhci: handle uPD720201 and uPD720202 w/o ROM
>
> This patch adds a firmware check for the uPD720201K8-711-BAC-A
> and uPD720202K8-711-BAA-A variant. Both of these chips are listed
> in Renesas' R19UH0078EJ0500 Rev.5.00 "User's Manual: Hardware" as
> devices which need a firmware in order to work as they do not have
> support to load the firmware from an external ROM.
>
> __
>
> Sorry for not saying earlier.

 That's a very interesting piece of information. Looking at that
 patch[1], it doesn't provide any FW loader, and simply detects whether
 the firmware is correctly present and running.

 

Re: [PATCH 3/3] ARM: dts: r7s72100: add USB device to device tree

[Sergei Shtylyov]

Hello!

On 1/4/2018 11:01 PM, Chris Brandt wrote:


Add USB device support.

Signed-off-by: Chris Brandt 
---
  arch/arm/boot/dts/r7s72100.dtsi | 20 
  1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index ab9645a42eca..eb414e735185 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -667,4 +667,24 @@
power-domains = <_clocks>;
status = "disabled";
};
+
+   usbhs0: usbhs@e801 {


   The node names should be generic, i.e "usb@e801".


+   compatible = "renesas,usbhs-r7s72100";
+   reg = <0xe801 0x1A0>;


   Lowercase in the hex values, please be consistent...


+   interrupts = ;
+   clocks = <_clks R7S72100_CLK_USB0>;
+   renesas,buswait = <4>;
+   power-domains = <_clocks>;
+   status = "disabled";
+   };
+
+   usbhs1: usbhs@e8207000 {
+   compatible = "renesas,usbhs-r7s72100";
+   reg = <0xe8207000 0x1A0>;
+   interrupts = ;
+   clocks = <_clks R7S72100_CLK_USB1>;
+   renesas,buswait = <4>;
+   power-domains = <_clocks>;
+   status = "disabled";
+   };
  };


   The same comments for the 2nd device.

MBR, Sergei
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Re: [PATCH 3/3] ARM: dts: r7s72100: add USB device to device tree

[Geert Uytterhoeven]

On Thu, Jan 4, 2018 at 9:01 PM, Chris Brandt  wrote:
> Add USB device support.
>
> Signed-off-by: Chris Brandt 

Reviewed-by: Geert Uytterhoeven 

Minor nits below.

> --- a/arch/arm/boot/dts/r7s72100.dtsi
> +++ b/arch/arm/boot/dts/r7s72100.dtsi
> @@ -667,4 +667,24 @@
> power-domains = <_clocks>;
> status = "disabled";
> };
> +
> +   usbhs0: usbhs@e801 {
> +   compatible = "renesas,usbhs-r7s72100";
> +   reg = <0xe801 0x1A0>;

0x1a0

> +   interrupts = ;

"41", all other interrupt properties already have the SPI offset subtracted?

> +   clocks = <_clks R7S72100_CLK_USB0>;
> +   renesas,buswait = <4>;
> +   power-domains = <_clocks>;
> +   status = "disabled";
> +   };
> +
> +   usbhs1: usbhs@e8207000 {
> +   compatible = "renesas,usbhs-r7s72100";
> +   reg = <0xe8207000 0x1A0>;

0x1a0

> +   interrupts = ;

"42", all other interrupt properties already have the SPI offset subtracted?

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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Re: [PATCH 2/3] dt-bindings: usb: renesas_usbhs: Add support for RZ/A1

[Geert Uytterhoeven]

On Thu, Jan 4, 2018 at 9:01 PM, Chris Brandt  wrote:
> Document support for RZ/A1 SoCs
>
> Signed-off-by: Chris Brandt 

Reviewed-by: Geert Uytterhoeven 

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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