libfdt: Seval cleanups to parameter checking (v2)
This patch makes a couple of small cleanups to parameter checking of
libfdt functions.
- In several functions which take a node offset, we use an
idiom involving fdt_next_tag() first to check that we have indeed been
given a node offset. This patch adds a helper function
_fdt_check_node_offset() to encapsulate this usage of fdt_next_tag().
- In fdt_rw.c in several places we have the expanded version
of the RW_CHECK_HEADER() macro for no particular reason. This patch
replaces those instances with an invocation of the macro; that's what
it's for.
- In fdt_sw.c we rename the check_header_sw() function to
sw_check_header() to match the analgous function in fdt_rw.c, and we
provide an SW_CHECK_HEADER() wrapper macro as RW_CHECK_HEADER()
functions in fdt_rw.c
Signed-off-by: David Gibson <[EMAIL PROTECTED]>
---
libfdt/fdt.c | 17 -
libfdt/fdt_ro.c | 26 --
libfdt/fdt_rw.c | 23 ---
libfdt/fdt_sw.c | 31 +++
libfdt/libfdt_internal.h |1 +
5 files changed, 44 insertions(+), 54 deletions(-)
Index: dtc/libfdt/fdt.c
===
--- dtc.orig/libfdt/fdt.c 2008-03-24 13:04:47.0 +1100
+++ dtc/libfdt/fdt.c2008-05-20 15:54:41.0 +1000
@@ -129,16 +129,23 @@ uint32_t fdt_next_tag(const void *fdt, i
return tag;
}
+int _fdt_check_node_offset(const void *fdt, int offset)
+{
+ if ((offset < 0) || (offset % FDT_TAGSIZE)
+ || (fdt_next_tag(fdt, offset, &offset) != FDT_BEGIN_NODE))
+ return -FDT_ERR_BADOFFSET;
+
+ return offset;
+}
+
int fdt_next_node(const void *fdt, int offset, int *depth)
{
int nextoffset = 0;
uint32_t tag;
- if (offset >= 0) {
- tag = fdt_next_tag(fdt, offset, &nextoffset);
- if (tag != FDT_BEGIN_NODE)
- return -FDT_ERR_BADOFFSET;
- }
+ if (offset >= 0)
+ if ((nextoffset = _fdt_check_node_offset(fdt, offset)) < 0)
+ return nextoffset;
do {
offset = nextoffset;
Index: dtc/libfdt/libfdt_internal.h
===
--- dtc.orig/libfdt/libfdt_internal.h 2008-03-24 13:04:47.0 +1100
+++ dtc/libfdt/libfdt_internal.h2008-05-20 15:46:41.0 +1000
@@ -66,6 +66,7 @@
}
uint32_t _fdt_next_tag(const void *fdt, int startoffset, int *nextoffset);
+int _fdt_check_node_offset(const void *fdt, int offset);
const char *_fdt_find_string(const char *strtab, int tabsize, const char *s);
int _fdt_node_end_offset(void *fdt, int nodeoffset);
Index: dtc/libfdt/fdt_ro.c
===
--- dtc.orig/libfdt/fdt_ro.c2008-03-24 13:04:47.0 +1100
+++ dtc/libfdt/fdt_ro.c 2008-05-20 16:01:09.0 +1000
@@ -157,16 +157,12 @@ int fdt_path_offset(const void *fdt, con
const char *fdt_get_name(const void *fdt, int nodeoffset, int *len)
{
- const struct fdt_node_header *nh;
+ const struct fdt_node_header *nh = _fdt_offset_ptr(fdt, nodeoffset);
int err;
- if ((err = fdt_check_header(fdt)) != 0)
- goto fail;
-
- err = -FDT_ERR_BADOFFSET;
- nh = fdt_offset_ptr(fdt, nodeoffset, sizeof(*nh));
- if (!nh || (fdt32_to_cpu(nh->tag) != FDT_BEGIN_NODE))
- goto fail;
+ if (((err = fdt_check_header(fdt)) != 0)
+ || ((err = _fdt_check_node_offset(fdt, nodeoffset)) < 0))
+ goto fail;
if (len)
*len = strlen(nh->name);
@@ -189,17 +185,11 @@ const struct fdt_property *fdt_get_prope
int offset, nextoffset;
int err;
- if ((err = fdt_check_header(fdt)) != 0)
- goto fail;
-
- err = -FDT_ERR_BADOFFSET;
- if (nodeoffset % FDT_TAGSIZE)
- goto fail;
-
- tag = fdt_next_tag(fdt, nodeoffset, &nextoffset);
- if (tag != FDT_BEGIN_NODE)
- goto fail;
+ if (((err = fdt_check_header(fdt)) != 0)
+ || ((err = _fdt_check_node_offset(fdt, nodeoffset)) < 0))
+ goto fail;
+ nextoffset = err;
do {
offset = nextoffset;
Index: dtc/libfdt/fdt_rw.c
===
--- dtc.orig/libfdt/fdt_rw.c2008-05-20 16:03:11.0 +1000
+++ dtc/libfdt/fdt_rw.c 2008-05-20 16:13:32.0 +1000
@@ -172,8 +172,7 @@ int fdt_add_mem_rsv(void *fdt, uint64_t
struct fdt_reserve_entry *re;
int err;
- if ((err = rw_check_header(fdt)))
- return err;
+ RW_CHECK_HEADER(fdt);
re = _fdt_mem_rsv_w(fdt, fdt_num_mem_rsv(fdt));
err = _blob_splice_mem_rsv(fdt, re, 0, 1);
@@ -190,8 +189,8 @@ int fdt_del_mem_rsv(vo
Re: libfdt: Seval cleanups to parameter checking
On Tue, May 20, 2008 at 04:23:34PM +1000, David Gibson wrote: > This patch makes a couple of small cleanups to parameter checking of > libfdt functions. > > - In several functions which take a node offset, we use an > idiom involving fdt_next_tag() first to check that we have indeed been > given a node offset. This patch adds a helper function > _fdt_check_node_offset() to encapsulate this usage of fdt_next_tag(). > - In fdt_rw.c in several places we have the expanded version of the > RW_CHECK_HEADER() macro for no particular reason. This patch replaces > those instances with an invocation of the macro; that's what it's for. > > Signed-off-by: David Gibson <[EMAIL PROTECTED]> Blah, sorry, ignore. Improved version coming. -- David Gibson| I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 2/4 V5] MSI support on 83xx/85xx/86xx board
On May 19, 2008, at 9:26 PM, Jin Zhengxiong wrote: -Original Message- From: Michael Ellerman [mailto:[EMAIL PROTECTED] Sent: Monday, May 19, 2008 10:09 AM To: Jin Zhengxiong Cc: [EMAIL PROTECTED]; linuxppc-dev@ozlabs.org; [EMAIL PROTECTED] Subject: Re: [PATCH 2/4 V5] MSI support on 83xx/85xx/86xx board On Fri, 2008-05-16 at 17:50 +0800, Jason Jin wrote: This MSI driver can be used on 83xx/85xx/86xx board. In this driver, virtual interrupt host and chip were setup. There are 256 MSI interrupts in this host, Every 32 MSI interrupts cascaded to one IPIC/MPIC interrupt. The chip was treated as edge sensitive and some necessary functions were setup for this chip. Before using the MSI interrupt, PCI/PCIE device need to ask for a MSI interrupt in the 256 MSI interrupts. A 256bit bitmap show which MSI interrupt was used, reserve bit in the bitmap can be used to force the device use some designate MSI interrupt in the 256 MSI interrupts. Sometimes this is useful for testing the all the MSI interrupts. The msi-available-ranges property in the dts file was used for this purpose. Signed-off-by: Jason Jin <[EMAIL PROTECTED]> --- In the V5 version: Make the msi-availble-ranges optional, remove the match function from the driver, change the compatible according the change in dts. Looks good, MSI bits: Acked-by: Michael Ellerman <[EMAIL PROTECTED]> cheers Thanks, Michael. Kumar, Could you please apply the MSI related patches. Thanks See my comments about the compatible. Once those changes are made I'll apply these patches. - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 1/4 V3] booting-without-of for Freescale MSI
On May 16, 2008, at 4:50 AM, Jason Jin wrote: Binding document adding for Freescale MSI support. Signed-off-by: Jason Jin <[EMAIL PROTECTED]> --- Change the compatible name in this V3 version. Documentation/powerpc/booting-without-of.txt | 41 + - 1 files changed, 40 insertions(+), 1 deletions(-) diff --git a/Documentation/powerpc/booting-without-of.txt b/ Documentation/powerpc/booting-without-of.txt index 1d2a772..789cd5a 100644 --- a/Documentation/powerpc/booting-without-of.txt +++ b/Documentation/powerpc/booting-without-of.txt @@ -57,7 +57,10 @@ Table of Contents n) 4xx/Axon EMAC ethernet nodes o) Xilinx IP cores p) Freescale Synchronous Serial Interface - q) USB EHCI controllers + q) USB EHCI controllers + r) Freescale Display Interface Unit + s) Freescale on board FPGA + t) Freescael MSI interrupt controller VII - Marvell Discovery mv64[345]6x System Controller chips 1) The /system-controller node @@ -2870,6 +2873,42 @@ platforms are moved over to use the flattened- device-tree model. reg = <0xe800 32>; }; +t) Freescale MSI interrupt controller + +Reguired properities: +- compatible : set as "fsl,mpc8610-msi" for all the cpu which use MPIC, + and set as "fsl,mpc8379-msi" for those use IPIC. I'd like to see "fsl,ipic-msi" and "fsl,mpic-msi". If we are going to use "chip" names we should use the first in each family that had the support so it would be: "fsl,mpc8641-msi", "fsl,mpc8379-msi", and "fsl,mpc8548-msi". However I've never been a big fan of using the "first" in family like this. It becomes difficult later to use this if we have to deal with errata on a given device to distinguish things. So my preference it that we have: compatible = "fsl,mpc8610-msi", "fsl,mpic-msi"; for the 8610, and for 8572 we'd have: compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; so like DMA its "fsl,CHIP-msi", and either "fsl,mpic-msi" or "fsl,ipic- msi" depending on the parent type. - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
libfdt: Seval cleanups to parameter checking
This patch makes a couple of small cleanups to parameter checking of
libfdt functions.
- In several functions which take a node offset, we use an
idiom involving fdt_next_tag() first to check that we have indeed been
given a node offset. This patch adds a helper function
_fdt_check_node_offset() to encapsulate this usage of fdt_next_tag().
- In fdt_rw.c in several places we have the expanded version of the
RW_CHECK_HEADER() macro for no particular reason. This patch replaces
those instances with an invocation of the macro; that's what it's for.
Signed-off-by: David Gibson <[EMAIL PROTECTED]>
---
libfdt/fdt.c | 17 -
libfdt/fdt_ro.c | 26 --
libfdt/fdt_rw.c | 23 ---
libfdt/libfdt_internal.h |1 +
4 files changed, 29 insertions(+), 38 deletions(-)
Index: dtc/libfdt/fdt.c
===
--- dtc.orig/libfdt/fdt.c 2008-03-24 13:04:47.0 +1100
+++ dtc/libfdt/fdt.c2008-05-20 15:54:41.0 +1000
@@ -129,16 +129,23 @@ uint32_t fdt_next_tag(const void *fdt, i
return tag;
}
+int _fdt_check_node_offset(const void *fdt, int offset)
+{
+ if ((offset < 0) || (offset % FDT_TAGSIZE)
+ || (fdt_next_tag(fdt, offset, &offset) != FDT_BEGIN_NODE))
+ return -FDT_ERR_BADOFFSET;
+
+ return offset;
+}
+
int fdt_next_node(const void *fdt, int offset, int *depth)
{
int nextoffset = 0;
uint32_t tag;
- if (offset >= 0) {
- tag = fdt_next_tag(fdt, offset, &nextoffset);
- if (tag != FDT_BEGIN_NODE)
- return -FDT_ERR_BADOFFSET;
- }
+ if (offset >= 0)
+ if ((nextoffset = _fdt_check_node_offset(fdt, offset)) < 0)
+ return nextoffset;
do {
offset = nextoffset;
Index: dtc/libfdt/libfdt_internal.h
===
--- dtc.orig/libfdt/libfdt_internal.h 2008-03-24 13:04:47.0 +1100
+++ dtc/libfdt/libfdt_internal.h2008-05-20 15:46:41.0 +1000
@@ -66,6 +66,7 @@
}
uint32_t _fdt_next_tag(const void *fdt, int startoffset, int *nextoffset);
+int _fdt_check_node_offset(const void *fdt, int offset);
const char *_fdt_find_string(const char *strtab, int tabsize, const char *s);
int _fdt_node_end_offset(void *fdt, int nodeoffset);
Index: dtc/libfdt/fdt_ro.c
===
--- dtc.orig/libfdt/fdt_ro.c2008-03-24 13:04:47.0 +1100
+++ dtc/libfdt/fdt_ro.c 2008-05-20 16:01:09.0 +1000
@@ -157,16 +157,12 @@ int fdt_path_offset(const void *fdt, con
const char *fdt_get_name(const void *fdt, int nodeoffset, int *len)
{
- const struct fdt_node_header *nh;
+ const struct fdt_node_header *nh = _fdt_offset_ptr(fdt, nodeoffset);
int err;
- if ((err = fdt_check_header(fdt)) != 0)
- goto fail;
-
- err = -FDT_ERR_BADOFFSET;
- nh = fdt_offset_ptr(fdt, nodeoffset, sizeof(*nh));
- if (!nh || (fdt32_to_cpu(nh->tag) != FDT_BEGIN_NODE))
- goto fail;
+ if (((err = fdt_check_header(fdt)) != 0)
+ || ((err = _fdt_check_node_offset(fdt, nodeoffset)) < 0))
+ goto fail;
if (len)
*len = strlen(nh->name);
@@ -189,17 +185,11 @@ const struct fdt_property *fdt_get_prope
int offset, nextoffset;
int err;
- if ((err = fdt_check_header(fdt)) != 0)
- goto fail;
-
- err = -FDT_ERR_BADOFFSET;
- if (nodeoffset % FDT_TAGSIZE)
- goto fail;
-
- tag = fdt_next_tag(fdt, nodeoffset, &nextoffset);
- if (tag != FDT_BEGIN_NODE)
- goto fail;
+ if (((err = fdt_check_header(fdt)) != 0)
+ || ((err = _fdt_check_node_offset(fdt, nodeoffset)) < 0))
+ goto fail;
+ nextoffset = err;
do {
offset = nextoffset;
Index: dtc/libfdt/fdt_rw.c
===
--- dtc.orig/libfdt/fdt_rw.c2008-05-20 16:03:11.0 +1000
+++ dtc/libfdt/fdt_rw.c 2008-05-20 16:13:32.0 +1000
@@ -172,8 +172,7 @@ int fdt_add_mem_rsv(void *fdt, uint64_t
struct fdt_reserve_entry *re;
int err;
- if ((err = rw_check_header(fdt)))
- return err;
+ RW_CHECK_HEADER(fdt);
re = _fdt_mem_rsv_w(fdt, fdt_num_mem_rsv(fdt));
err = _blob_splice_mem_rsv(fdt, re, 0, 1);
@@ -190,8 +189,8 @@ int fdt_del_mem_rsv(void *fdt, int n)
struct fdt_reserve_entry *re = _fdt_mem_rsv_w(fdt, n);
int err;
- if ((err = rw_check_header(fdt)))
- return err;
+ RW_CHECK_HEADER(fdt);
+
if (n >= fdt_num_mem_rsv(fdt))
return -FDT_ERR_NOTFOUND;
@@ -223,15 +2
Re: [PATCH 1/7] [POWERPC] sysdev: implement FSL GTM support
On May 19, 2008, at 12:46 PM, Anton Vorontsov wrote:
GTM stands for General-purpose Timers Module and able to generate
timer{1,2,3,4} interrupts. These timers are used by the drivers that
need time precise interrupts (like for USB transactions scheduling for
the Freescale USB Host controller as found in some QE and CPM chips),
or these timers could be used as wakeup events from the CPU deep-sleep
mode.
Things unimplemented:
1. Cascaded (32 bit) timers (1-2, 3-4).
This is straightforward to implement when needed, two timers should
be marked as "requested" and configured as appropriate.
2. Super-cascaded (64 bit) timers (1-2-3-4).
This is also straightforward to implement when needed, all timers
should be marked as "requested" and configured as appropriate.
Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
---
Documentation/powerpc/booting-without-of.txt | 37 +++-
arch/powerpc/Kconfig |5 +
arch/powerpc/sysdev/Makefile |1 +
arch/powerpc/sysdev/fsl_gtm.c| 424 +
+
include/asm-powerpc/fsl_gtm.h| 47 +++
5 files changed, 513 insertions(+), 1 deletions(-)
create mode 100644 arch/powerpc/sysdev/fsl_gtm.c
create mode 100644 include/asm-powerpc/fsl_gtm.h
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 3934e26..e5d3366 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -538,6 +538,11 @@ config FSL_LBC
help
Freescale Localbus support
+config FSL_GTM
+ bool
I'd prefer something like:
depends on PPC_83xx || QUICC_ENGINE || CPM2
+ help
+ Freescale General-purpose Timers support
+
# Yes MCA RS/6000s exist but Linux-PPC does not currently support any
config MCA
bool
diff --git a/arch/powerpc/sysdev/fsl_gtm.c b/arch/powerpc/sysdev/
fsl_gtm.c
new file mode 100644
index 000..8b35cc4
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_gtm.c
@@ -0,0 +1,424 @@
+/*
+ * Freescale General-purpose Timers Module
+ *
+ * Copyright (c) Freescale Semicondutor, Inc. 2006.
+ * Shlomi Gridish <[EMAIL PROTECTED]>
+ * Jerry Huang <[EMAIL PROTECTED]>
+ * Copyright (c) MontaVista Software, Inc. 2008.
+ * Anton Vorontsov <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or
modify it
+ * under the terms of the GNU General Public License as
published by the
+ * Free Software Foundation; either version 2 of the License, or
(at your
+ * option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define GTCFR_STP(x) ((x) & 1 ? 1 << 5 : 1 << 1)
+#define GTCFR_RST(x) ((x) & 1 ? 1 << 4 : 1 << 0)
+
+#define GTMDR_ICLK_MASK(3 << 1)
+#define GTMDR_ICLK_ICAS(0 << 1)
+#define GTMDR_ICLK_ICLK(1 << 1)
+#define GTMDR_ICLK_SLGO(2 << 1)
+#define GTMDR_FRR (1 << 3)
+#define GTMDR_ORI (1 << 4)
+#define GTMDR_SPS(x) ((x) << 8)
+
+struct gtm_timers_regs {
+ u8 gtcfr1; /* Timer 1, Timer 2 global config register */
+ u8 res0[0x3];
+ u8 gtcfr2; /* Timer 3, timer 4 global config register */
+ u8 res1[0xB];
+ __be16 gtmdr1; /* Timer 1 mode register */
+ __be16 gtmdr2; /* Timer 2 mode register */
+ __be16 gtrfr1; /* Timer 1 reference register */
+ __be16 gtrfr2; /* Timer 2 reference register */
+ __be16 gtcpr1; /* Timer 1 capture register */
+ __be16 gtcpr2; /* Timer 2 capture register */
+ __be16 gtcnr1; /* Timer 1 counter */
+ __be16 gtcnr2; /* Timer 2 counter */
+ __be16 gtmdr3; /* Timer 3 mode register */
+ __be16 gtmdr4; /* Timer 4 mode register */
+ __be16 gtrfr3; /* Timer 3 reference register */
+ __be16 gtrfr4; /* Timer 4 reference register */
+ __be16 gtcpr3; /* Timer 3 capture register */
+ __be16 gtcpr4; /* Timer 4 capture register */
+ __be16 gtcnr3; /* Timer 3 counter */
+ __be16 gtcnr4; /* Timer 4 counter */
+ __be16 gtevr1; /* Timer 1 event register */
+ __be16 gtevr2; /* Timer 2 event register */
+ __be16 gtevr3; /* Timer 3 event register */
+ __be16 gtevr4; /* Timer 4 event register */
+ __be16 gtpsr1; /* Timer 1 prescale register */
+ __be16 gtpsr2; /* Timer 2 prescale register */
+ __be16 gtpsr3; /* Timer 3 prescale register */
+ __be16 gtpsr4; /* Timer 4 prescale register */
+ u8 res2[0x40];
+} __attribute__ ((packed));
+
+struct gtm {
+ unsigned int clock;
+ struct gtm_timers_regs __iomem *regs;
+ struct gtm_timer timers[4];
+ spinl
[PATCH 4/4] [POWERPC] Fix mpc8377_mds.dts DMA nodes to match spec
Signed-off-by: Kumar Gala <[EMAIL PROTECTED]>
---
arch/powerpc/boot/dts/mpc8377_mds.dts | 18 +-
1 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts
b/arch/powerpc/boot/dts/mpc8377_mds.dts
index 1e7802c..fea5925 100644
--- a/arch/powerpc/boot/dts/mpc8377_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8377_mds.dts
@@ -271,27 +271,35 @@
[EMAIL PROTECTED] {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "fsl,mpc8349-dma";
+ compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
reg = <0x82a8 4>;
ranges = <0 0x8100 0x1a8>;
interrupt-parent = <&ipic>;
interrupts = <0x47 8>;
cell-index = <0>;
[EMAIL PROTECTED] {
- compatible = "fsl,mpc8349-dma-channel";
+ compatible = "fsl,mpc8377-dma-channel",
"fsl,elo-dma-channel";
reg = <0 0x80>;
+ interrupt-parent = <&ipic>;
+ interrupts = <0x47 8>;
};
[EMAIL PROTECTED] {
- compatible = "fsl,mpc8349-dma-channel";
+ compatible = "fsl,mpc8377-dma-channel",
"fsl,elo-dma-channel";
reg = <0x80 0x80>;
+ interrupt-parent = <&ipic>;
+ interrupts = <0x47 8>;
};
[EMAIL PROTECTED] {
- compatible = "fsl,mpc8349-dma-channel";
+ compatible = "fsl,mpc8377-dma-channel",
"fsl,elo-dma-channel";
reg = <0x100 0x80>;
+ interrupt-parent = <&ipic>;
+ interrupts = <0x47 8>;
};
[EMAIL PROTECTED] {
- compatible = "fsl,mpc8349-dma-channel";
+ compatible = "fsl,mpc8377-dma-channel",
"fsl,elo-dma-channel";
reg = <0x180 0x28>;
+ interrupt-parent = <&ipic>;
+ interrupts = <0x47 8>;
};
};
--
1.5.4.5
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[PATCH 3/4] [POWERPC] Update arch/powerpc/boot/.gitignore
* Add dtbImage.* * Added zImage.holly * Folded zImage.coff.lds into zImage.*lds * Removed some unused zImage. ignores Signed-off-by: Kumar Gala <[EMAIL PROTECTED]> --- arch/powerpc/boot/.gitignore |8 +++- 1 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/boot/.gitignore b/arch/powerpc/boot/.gitignore index 2347294..2f50acd 100644 --- a/arch/powerpc/boot/.gitignore +++ b/arch/powerpc/boot/.gitignore @@ -20,21 +20,19 @@ kernel-vmlinux.strip.gz mktree uImage cuImage.* +dtbImage.* treeImage.* zImage +zImage.initrd zImage.bin.* zImage.chrp zImage.coff -zImage.coff.lds -zImage.ep* +zImage.holly zImage.iseries zImage.*lds zImage.miboot zImage.pmac zImage.pseries -zImage.redboot* -zImage.sandpoint -zImage.vmode zconf.h zlib.h zutil.h -- 1.5.4.5 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH 2/4] [POWERPC] Remove generated files on make clean
dtbImage.* and several zImage. targets get created but never cleaned up. Also, moved zImage to the clean-files line associated with all other image results (was previously duplicated). Signed-off-by: Kumar Gala <[EMAIL PROTECTED]> --- arch/powerpc/boot/Makefile |6 -- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile index 7822d25..f5e0b2a 100644 --- a/arch/powerpc/boot/Makefile +++ b/arch/powerpc/boot/Makefile @@ -99,7 +99,7 @@ $(obj)/zImage.lds $(obj)/zImage.coff.lds $(obj)/zImage.ps3.lds: $(obj)/%: $(srct @cp $< $@ clean-files := $(zlib) $(zlibheader) $(zliblinuxheader) \ - empty.c zImage zImage.coff.lds zImage.ps3.lds zImage.lds + empty.c zImage.coff.lds zImage.ps3.lds zImage.lds quiet_cmd_bootcc = BOOTCC $@ cmd_bootcc = $(CROSS32CC) -Wp,-MD,$(depfile) $(BOOTCFLAGS) -c -o $@ $< @@ -339,7 +339,9 @@ install: $(CONFIGURE) $(addprefix $(obj)/, $(image-y)) sh -x $(srctree)/$(src)/install.sh "$(KERNELRELEASE)" vmlinux System.map "$(INSTALL_PATH)" $< # anything not in $(targets) -clean-files += $(image-) $(initrd-) zImage zImage.initrd cuImage.* treeImage.* \ +clean-files += $(image-) $(initrd-) cuImage.* dtbImage.* treeImage.* \ + zImage zImage.initrd zImage.chrp zImage.coff zImage.holly \ + zImage.iseries zImage.miboot zImage.pmac zImage.pseries \ otheros.bld *.dtb # clean up files cached by wrapper -- 1.5.4.5 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH 1/4] lmb: Fix compile warning
lib/lmb.c: In function 'lmb_dump_all':
lib/lmb.c:51: warning: format '%lx' expects type 'long unsigned int', but
argument 2 has type 'u64'
Signed-off-by: Kumar Gala <[EMAIL PROTECTED]>
Acked-by: David S. Miller <[EMAIL PROTECTED]>
---
lib/lmb.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/lib/lmb.c b/lib/lmb.c
index 867f7b5..5d7b928 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -48,7 +48,8 @@ void lmb_dump_all(void)
}
pr_info("reserved.cnt = 0x%lx\n", lmb.reserved.cnt);
- pr_info("reserved.size= 0x%lx\n", lmb.reserved.size);
+ pr_info("reserved.size= 0x%llx\n",
+ (unsigned long long)lmb.memory.size);
for (i=0; i < lmb.reserved.cnt ;i++) {
pr_info("reserved.region[0x%lx].base = 0x%llx\n",
i, (unsigned long long)lmb.reserved.region[i].base);
--
1.5.4.5
___
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Linuxppc-dev@ozlabs.org
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[PATCH v2 0/4] Fixes for 2.6.26
Please pull from 'for-2.6.26' branch of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc.git for-2.6.26 to receive the following updates: arch/powerpc/boot/.gitignore |8 +++- arch/powerpc/boot/Makefile|6 -- arch/powerpc/boot/dts/mpc8377_mds.dts | 18 +- lib/lmb.c |3 ++- 4 files changed, 22 insertions(+), 13 deletions(-) Kumar Gala (4): lmb: Fix compile warning [POWERPC] Remove generated files on make clean [POWERPC] Update arch/powerpc/boot/.gitignore [POWERPC] Fix mpc8377_mds.dts DMA nodes to match spec ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 0/4] minor fixes for 2.6.26
On May 20, 2008, at 12:10 AM, David Gibson wrote: On Mon, May 19, 2008 at 11:52:31PM -0500, Kumar Gala wrote: On May 19, 2008, at 6:07 PM, Paul Mackerras wrote: Kumar Gala writes: Kumar Gala (4): lmb: Fix compile warning [POWERPC] Remove generated files on make clean I think that adding zImage.* to clean-files is a bad idea, because we have zImage.lds.S, zImage.coff.lds.S and zImage.ps3.lds.S in arch/powerpc/boot that we don't want deleted. It would be OK for compiling with a separate object directory but would be bad for compiling in the source directory. We already had them in clean-files: clean-files := $(zlib) $(zlibheader) $(zliblinuxheader) \ empty.c zImage zImage.coff.lds zImage.ps3.lds zImage.lds Not quite. Those are the zImage.lds files, Paul is talking about the zImage.lds.S files from which the former are generated. Ah, missed that minor detail. - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH] Add port multiplier (PMP) support in sata_fsl driver
From: Ashish Kalra <[EMAIL PROTECTED]>
PMP support for sata_fsl driver.
Signed-off-by: Ashish Kalra <[EMAIL PROTECTED]>
---
Jeff,
The following commit (4c9bf4e799ce06a7378f1196587084802a414c03):
libata: replace tf_read with qc_fill_rtf for non-SFF drivers
Broke the sata_fsl.c driver in 2.6.26. I know the following patch fixes
the issue, it clearly also adds port multipler support. I'm not sure if
you are willing to take that as part of 2.6.26 or not, but the current
2.6.26 driver is broken.
On boot with debug enabled we get something like (w/o this patch):
spurious interrupt!!, CC = 0x1
interrupt status 0x1
xx_scr_read, reg_in = 1
spurious interrupt!!, CC = 0x1
interrupt status 0x1
xx_scr_read, reg_in = 1
spurious interrupt!!, CC = 0x1
interrupt status 0x1
xx_scr_read, reg_in = 1
.. continues for ever.
- k
drivers/ata/sata_fsl.c | 224 +++-
1 files changed, 163 insertions(+), 61 deletions(-)
diff --git a/drivers/ata/sata_fsl.c b/drivers/ata/sata_fsl.c
index 853559e..3924e72 100644
--- a/drivers/ata/sata_fsl.c
+++ b/drivers/ata/sata_fsl.c
@@ -34,7 +34,7 @@ enum {
SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
- ATA_FLAG_NCQ),
+ ATA_FLAG_PMP | ATA_FLAG_NCQ),
SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH,
SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */
@@ -395,7 +395,7 @@ static void sata_fsl_qc_prep(struct ata_queued_cmd *qc)
cd = (struct command_desc *)pp->cmdentry + tag;
cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE;
- ata_tf_to_fis(&qc->tf, 0, 1, (u8 *) &cd->cfis);
+ ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis);
VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
cd->cfis[0], cd->cfis[1], cd->cfis[2]);
@@ -438,6 +438,8 @@ static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd
*qc)
ioread32(CA + hcr_base),
ioread32(CE + hcr_base), ioread32(CC + hcr_base));
+ iowrite32(qc->dev->link->pmp, CQPMP + hcr_base);
+
/* Simply queue command to the controller/device */
iowrite32(1 << tag, CQ + hcr_base);
@@ -558,11 +560,36 @@ static void sata_fsl_thaw(struct ata_port *ap)
ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
}
+static void sata_fsl_pmp_attach(struct ata_port *ap)
+{
+ struct sata_fsl_host_priv *host_priv = ap->host->private_data;
+ void __iomem *hcr_base = host_priv->hcr_base;
+ u32 temp;
+
+ temp = ioread32(hcr_base + HCONTROL);
+ iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL);
+}
+
+static void sata_fsl_pmp_detach(struct ata_port *ap)
+{
+ struct sata_fsl_host_priv *host_priv = ap->host->private_data;
+ void __iomem *hcr_base = host_priv->hcr_base;
+ u32 temp;
+
+ temp = ioread32(hcr_base + HCONTROL);
+ temp &= ~HCONTROL_PMP_ATTACHED;
+ iowrite32(temp, hcr_base + HCONTROL);
+
+ /* enable interrupts on the controller/port */
+ temp = ioread32(hcr_base + HCONTROL);
+ iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
+
+}
+
static int sata_fsl_port_start(struct ata_port *ap)
{
struct device *dev = ap->host->dev;
struct sata_fsl_port_priv *pp;
- int retval;
void *mem;
dma_addr_t mem_dma;
struct sata_fsl_host_priv *host_priv = ap->host->private_data;
@@ -688,12 +715,13 @@ static int sata_fsl_prereset(struct ata_link *link,
unsigned long deadline)
}
static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
- unsigned long deadline)
+ unsigned long deadline)
{
struct ata_port *ap = link->ap;
struct sata_fsl_port_priv *pp = ap->private_data;
struct sata_fsl_host_priv *host_priv = ap->host->private_data;
void __iomem *hcr_base = host_priv->hcr_base;
+ int pmp = sata_srst_pmp(link);
u32 temp;
struct ata_taskfile tf;
u8 *cfis;
@@ -703,6 +731,9 @@ static int sata_fsl_softreset(struct ata_link *link,
unsigned int *class,
DPRINTK("in xx_softreset\n");
+ if (pmp != SATA_PMP_CTRL_PORT)
+ goto issue_srst;
+
try_offline_again:
/*
* Force host controller to go off-line, aborting current operations
@@ -746,6 +777,7 @@ try_offline_again:
temp = ioread32(hcr_base + HCONTROL);
temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE);
+ temp |= HCONTROL_PMP_ATTACHED;
iowrite32(temp, hcr_base + HCONTROL);
temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, 0, 1, 500);
@@ -771,7 +803,8 @@ try_offline_again:
ata_port_printk(ap, KERN_WARNING,
"No Device OR PHYRDY change,Hstatus = 0x%x\n"
Re: [PATCH 3/4] spi: Add OF binding support for SPI busses
On Mon, May 19, 2008 at 10:30 AM, Guennadi Liakhovetski
<[EMAIL PROTECTED]> wrote:
> On Mon, 19 May 2008, Grant Likely wrote:
>> But that is Linux internal
>> details; this discussion is about device tree bindings.
>>
>> Note that I did say that drivers can define additional properties for
>> supporting chip select changes as needed. I'm just not attempting to
>> encode them into the formal binding. There is simply just too many
>> different ways to manipulate chip select signals and so I don't feel
>> confident trying to define a *common* binding at this moment in time.
>
> Yes, I understand, that physically there can be many ways SPI chipselects
> can be controlled. But I thought there could be a generic way to cover
> them all by defining a separate entry on your SPI bus. Like
>
> +SPI example for an MPC5200 SPI bus:
> + [EMAIL PROTECTED] {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
> + reg = <0xf00 0x20>;
> + interrupts = <2 13 0 2 14 0>;
> + interrupt-parent = <&mpc5200_pic>;
> + [EMAIL PROTECTED] {
> + compatible = "oem,cs-type";
> + };
> +
> + [EMAIL PROTECTED] {
> + compatible = "micrel,ks8995m";
> + linux,modalias = "ks8995";
> + max-speed = <100>;
> + reg = <0>;
> + cs-parent = <&/.../[EMAIL PROTECTED]/[EMAIL
> PROTECTED]>;
> + };
> ...
> + };
>
> Then whatever method is used to actually switch the CS, a driver should be
> registered to handle [EMAIL PROTECTED], providing the required calls.
> Without such a driver [EMAIL PROTECTED] will not probe successfully.
> Wouldn't this cover all possible cases? One could even consider actually
> putting SPI devices on SPI chipselect busses, but that won't look very
> elegant:-)
Hurr...
I'm not so fond of this approach. cs-parent doesn't seem to make much
sense to me. It might be better to have a cs-handler property on the
SPI bus node instead of on the SPI slave nodes, but even then it
leaves a number of questions about what it really means. In some
cases it would be overkill. For example, if the SPI node simply had
multiple GPIO lines then an extra cs-parent node wouldn't be needed at
all. Then there are the complex arrangements. When setting CS
requires inserting a special 'set cs' SPI message at the right time.
Or worse; when setting CS requires /modifying/ the sent SPI message.
Essentially, the binding would need to describe the ability to
completely intercept and rewrite all SPI messages going through the CS
scheme.
I'm not saying it's not possible to do, but I am saying that I'd like
to have a better feel for all the use cases before it is defined. I'm
not convinced that adding a cs-parent phandle will do that
appropriately. That being said, my gut feel is that the solution will
be to support spi-bridge nodes that handle the complex CS
configuration settings; the spi-bridge would be a child of the
spi-master and the parent of the spi devices; and simple CS settings
being handled with regular old GPIO bindings. (Much like the last
suggestion you make; except that I think that it *does* looks
elegant.) :-)
example; here's an SPI bus that has 2 GPIOs for two bus CS lines and
an SPI bridge that uses both CSes; one address for accessing the
bridge's CS register and one CS to access the downstream devices.
+SPI example for an MPC5200 SPI bus:
+ [EMAIL PROTECTED] {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
+ reg = <0xf00 0x20>;
+ interrupts = <2 13 0 2 14 0>;
+ interrupt-parent = <&mpc5200_pic>;
+ gpios = <&gpio1 0 0 &gpio1 1 0>;
+ [EMAIL PROTECTED] {
+ compatible = "oem,spi-bridge-type";
+ reg = < 0 1 >; // note: 2 SPI CS addresses;
first one to access bridge registers
+
+ [EMAIL PROTECTED] {
+ compatible = "micrel,ks8995m";
+ linux,modalias = "ks8995";
+ max-speed = <100>;
+ reg = <0>;
+ };
... // and more SPI child nodes here...
+ };
+ };
But even this doesn't reflect the hardware layout well. What if the
SS lines are on SPI GPIO expanders on the same bus? Then does it make
sense for them to be layed out as spi bridges?
Cheers,
g.
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technolo
Re: [PATCH 0/4] minor fixes for 2.6.26
On Mon, May 19, 2008 at 11:52:31PM -0500, Kumar Gala wrote: > > On May 19, 2008, at 6:07 PM, Paul Mackerras wrote: > >> Kumar Gala writes: >> Kumar Gala (4): lmb: Fix compile warning [POWERPC] Remove generated files on make clean >> >> I think that adding zImage.* to clean-files is a bad idea, because we >> have zImage.lds.S, zImage.coff.lds.S and zImage.ps3.lds.S in >> arch/powerpc/boot that we don't want deleted. It would be OK for >> compiling with a separate object directory but would be bad for >> compiling in the source directory. > > We already had them in clean-files: > > clean-files := $(zlib) $(zlibheader) $(zliblinuxheader) \ > empty.c zImage zImage.coff.lds zImage.ps3.lds zImage.lds Not quite. Those are the zImage.lds files, Paul is talking about the zImage.lds.S files from which the former are generated. -- David Gibson| I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH v4] [POWERPC] Move to runtime allocated exception stacks
For the additonal exception levels (critical, debug, machine check) on 40x/book-e we were using "static" allocations of the stack in the associated head.S. Move to a runtime allocation to make the code a bit easier to read as we mimic how we handle IRQ stacks. Its also a bit easier to setup the stack with a "dummy" thread_info in C code. Signed-off-by: Kumar Gala <[EMAIL PROTECTED]> --- Fixed 40x handling based on Josh's feedback and help. - k arch/powerpc/kernel/head_40x.S | 19 +-- arch/powerpc/kernel/head_44x.S |9 - arch/powerpc/kernel/head_booke.h | 29 +++-- arch/powerpc/kernel/head_fsl_booke.S |9 - arch/powerpc/kernel/irq.c| 33 + arch/powerpc/kernel/setup_32.c | 24 include/asm-powerpc/irq.h| 13 + 7 files changed, 86 insertions(+), 50 deletions(-) diff --git a/arch/powerpc/kernel/head_40x.S b/arch/powerpc/kernel/head_40x.S index 8552e67..8ef77e3 100644 --- a/arch/powerpc/kernel/head_40x.S +++ b/arch/powerpc/kernel/head_40x.S @@ -148,14 +148,15 @@ _ENTRY(crit_r11) mfcrr10;/* save CR in r10 for now */\ mfspr r11,SPRN_SRR3; /* check whether user or kernel*/\ andi. r11,r11,MSR_PR; \ - lis r11,[EMAIL PROTECTED]; \ - ori r11,r11,[EMAIL PROTECTED]; \ + lis r11,[EMAIL PROTECTED]; \ + tophys(r11,r11); \ + lwz r11,[EMAIL PROTECTED](r11); \ beq 1f; \ /* COMING FROM USER MODE */ \ mfspr r11,SPRN_SPRG3; /* if from user, start at top of */\ lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\ - addir11,r11,THREAD_SIZE; \ -1: subir11,r11,INT_FRAME_SIZE; /* Allocate an exception frame */\ +1: addir11,r11,THREAD_SIZE; \ + subir11,r11,INT_FRAME_SIZE; /* Allocate an exception frame */\ tophys(r11,r11); \ stw r10,_CCR(r11); /* save various registers */\ stw r12,GPR12(r11); \ @@ -996,16 +997,6 @@ empty_zero_page: swapper_pg_dir: .space PGD_TABLE_SIZE - -/* Stack for handling critical exceptions from kernel mode */ - .section .bss -.align 12 -exception_stack_bottom: - .space 4096 -critical_stack_top: - .globl exception_stack_top -exception_stack_top: - /* Room for two PTE pointers, usually the kernel and current user pointers * to their respective root page table. */ diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S index c2b9dc4..47ea8af 100644 --- a/arch/powerpc/kernel/head_44x.S +++ b/arch/powerpc/kernel/head_44x.S @@ -737,15 +737,6 @@ empty_zero_page: swapper_pg_dir: .space PGD_TABLE_SIZE -/* Reserved 4k for the critical exception stack & 4k for the machine - * check stack per CPU for kernel mode exceptions */ - .section .bss -.align 12 -exception_stack_bottom: - .space BOOKE_EXCEPTION_STACK_SIZE - .globl exception_stack_top -exception_stack_top: - /* * Room for two PTE pointers, usually the kernel and current user pointers * to their respective root page table. diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h index 721faef..9eacf4c 100644 --- a/arch/powerpc/kernel/head_booke.h +++ b/arch/powerpc/kernel/head_booke.h @@ -43,9 +43,7 @@ SAVE_2GPRS(7, r11) /* To handle the additional exception priority levels on 40x and Book-E - * processors we allocate a 4k stack per additional priority level. The various - * head_xxx.S files allocate space (exception_stack_top) for each priority's - * stack times the number of CPUs + * processors we allocate a stack per additional priority level. * * On 40x critical is the only additional level * On 44x/e500 we have critical and machine check @@ -61,36 +59,31 @@ * going to critical or their own debug level we aren't currently * providing configurations that micro-optimize space usage. */ -#ifdef CONFIG_44x -#define NUM_EXCEPTION_LVLS 2 -#else -#define NUM_EXCEPTION_LVLS 3 -#endif -#define BOOKE_EXCEPTION_STACK_SIZE (4096 * NUM_EXCEPTION_LVLS) /* CRIT_SPRG only used in critical exception handling */ #define CRIT_SPRG SPRN_SPRG2 /* MCHECK_SPRG only used in machine check exception handling */ #define MCHECK_SPRGSPRN_
Re: [PATCH v3 3/3] [POWERPC] 40x/Book-E: Save/restore volatile exception registers
--- a/arch/powerpc/kernel/entry_32.S +++ b/arch/powerpc/kernel/entry_32.S +#ifdef CONFIG_40x .globl ret_from_crit_exc ret_from_crit_exc: + mfspr r9,SPRN_SPRG3 lis r10,[EMAIL PROTECTED]; lwz r10,[EMAIL PROTECTED](r10); tovirt(r9,r9); + stw r10,KSP_LIMIT(r9) lis r9, [EMAIL PROTECTED]; lwz r9, [EMAIL PROTECTED](r9); lis r10, [EMAIL PROTECTED]; lwz r10, [EMAIL PROTECTED](r10); + mtspr SPRN_SRR0,r9; + mtspr SPRN_SRR1,r10; RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, RFCI) +#endif /* CONFIG_40x */ With the above changes, I no longer get kernel panics on returning from critical exceptions. Breakpoints and single stepping worked on my 405GP board. Again, not stress tested but it's looking much better. josh Thanks. I've just posted v5 with the various fixes for 40x. Can you test those out to make sure they still work. - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH v4] [POWERPC] Rework EXC_LEVEL_EXCEPTION_PROLOG code
* Cleanup the code a bit my allocating an INT_FRAME on our exception
stack there by make references go from GPR11-INT_FRAME_SIZE(r8) to
just GPR11(r8)
* simplify {lvl}_transfer_to_handler code by moving the copying of the
temp registers we use if we come from user space into the PROLOG
* If the exception came from kernel mode copy thread_info flags,
preempt, and task pointer from the process thread_info.
Signed-off-by: Kumar Gala <[EMAIL PROTECTED]>
---
arch/powerpc/kernel/entry_32.S | 13 -
arch/powerpc/kernel/head_booke.h | 54 -
2 files changed, 35 insertions(+), 32 deletions(-)
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index 888a364..c94aba5 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -44,29 +44,16 @@
#endif
#ifdef CONFIG_BOOKE
-#include "head_booke.h"
-#define TRANSFER_TO_HANDLER_EXC_LEVEL(exc_level) \
- mtspr exc_level##_SPRG,r8;\
- BOOKE_LOAD_EXC_LEVEL_STACK(exc_level); \
- lwz r0,GPR10-INT_FRAME_SIZE(r8);\
- stw r0,GPR10(r11); \
- lwz r0,GPR11-INT_FRAME_SIZE(r8);\
- stw r0,GPR11(r11); \
- mfspr r8,exc_level##_SPRG
-
.globl mcheck_transfer_to_handler
mcheck_transfer_to_handler:
- TRANSFER_TO_HANDLER_EXC_LEVEL(MCHECK)
b transfer_to_handler_full
.globl debug_transfer_to_handler
debug_transfer_to_handler:
- TRANSFER_TO_HANDLER_EXC_LEVEL(DEBUG)
b transfer_to_handler_full
.globl crit_transfer_to_handler
crit_transfer_to_handler:
- TRANSFER_TO_HANDLER_EXC_LEVEL(CRIT)
/* fall through */
#endif
diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h
index 9eacf4c..b0874d2 100644
--- a/arch/powerpc/kernel/head_booke.h
+++ b/arch/powerpc/kernel/head_booke.h
@@ -72,18 +72,20 @@
#define DEBUG_STACK_BASE dbgirq_ctx
#define DEBUG_SPRG SPRN_SPRG6W
+#define EXC_LVL_FRAME_OVERHEAD (THREAD_SIZE - INT_FRAME_SIZE)
+
#ifdef CONFIG_SMP
#define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
mfspr r8,SPRN_PIR;\
slwir8,r8,2;\
addis r8,r8,[EMAIL PROTECTED];\
lwz r8,[EMAIL PROTECTED](r8); \
- addir8,r8,THREAD_SIZE;
+ addir8,r8,EXC_LVL_FRAME_OVERHEAD;
#else
#define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
lis r8,[EMAIL PROTECTED]; \
lwz r8,[EMAIL PROTECTED](r8); \
- addir8,r8,THREAD_SIZE;
+ addir8,r8,EXC_LVL_FRAME_OVERHEAD;
#endif
/*
@@ -97,22 +99,36 @@
#define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, exc_level_srr0, exc_level_srr1) \
mtspr exc_level##_SPRG,r8; \
BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level
stack*/ \
- stw r10,GPR10-INT_FRAME_SIZE(r8);\
- stw r11,GPR11-INT_FRAME_SIZE(r8);\
- mfcrr10;/* save CR in r10 for now */\
- mfspr r11,exc_level_srr1; /* check whether user or kernel*/\
- andi. r11,r11,MSR_PR; \
- mr r11,r8; \
- mfspr r8,exc_level##_SPRG; \
- beq 1f; \
- /* COMING FROM USER MODE */ \
+ stw r9,GPR9(r8);/* save various registers */\
+ mfcrr9; /* save CR in r9 for now */\
+ stw r10,GPR10(r8); \
+ stw r11,GPR11(r8); \
+ stw r9,_CCR(r8);/* save CR on stack*/\
+ mfspr r10,exc_level_srr1; /* check whether user or kernel*/\
+ andi. r10,r10,MSR_PR; \
mfspr r11,SPRN_SPRG3; /* if from user, start at top of */\
lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
- addir11,r11,THREAD_SIZE; \
-1: subir11,r11,INT_FRAME_SIZE; /* Allocate an exception frame */\
- stw r10,_CCR(r11); /* save various registers */\
- stw r12,GPR12(r11); \
+ addir11,r11,EXC_LVL_FRAME_OVERHEAD; /* allocate stack frame*/\
+ beq 1f;
[PATCH v4] [POWERPC] 40x/Book-E: Save/restore volatile exception registers
On machines with more than one exception level any system register that
might be modified by the "normal" exception level needs to be saved and
restored on taking a higher level exception. We already are saving
and restoring ESR and DEAR.
For critical level add SRR0/1.
For debug level add CSRR0/1 and SRR0/1.
For machine check level add DSRR0/1, CSRR0/1, and SRR0/1.
On FSL Book-E parts we always save/restore the MAS registers for critical,
debug, and machine check level exceptions. On 44x we always save/restore
the MMUCR.
Additionally, we save and restore the ksp_limit since we have to adjust it
for each exception level.
Signed-off-by: Kumar Gala <[EMAIL PROTECTED]>
---
* Fixed mismerge in asm-offsets.c pointed out by Stephen
* Fixed 40x handling. The critical return path was restoring state as
if it was in real mode.(again, Josh helped debug and fix this).
arch/powerpc/kernel/asm-offsets.c | 23 +++
arch/powerpc/kernel/entry_32.S| 125 -
arch/powerpc/kernel/head_40x.S|6 ++
arch/powerpc/kernel/head_booke.h | 23 +++-
4 files changed, 174 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/asm-offsets.c
b/arch/powerpc/kernel/asm-offsets.c
index ec9228d..8655c76 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -52,6 +52,10 @@
#include
#endif
+#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
+#include "head_booke.h"
+#endif
+
int main(void)
{
DEFINE(THREAD, offsetof(struct task_struct, thread));
@@ -242,6 +246,25 @@ int main(void)
DEFINE(_SRR1, STACK_FRAME_OVERHEAD+sizeof(struct pt_regs)+8);
#endif /* CONFIG_PPC64 */
+#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
+ DEFINE(EXC_LVL_SIZE, STACK_EXC_LVL_FRAME_SIZE);
+ DEFINE(MAS0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs,
mas0));
+ /* we overload MMUCR for 44x on MAS0 since they are mutually exclusive
*/
+ DEFINE(MMUCR, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs,
mas0));
+ DEFINE(MAS1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs,
mas1));
+ DEFINE(MAS2, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs,
mas2));
+ DEFINE(MAS3, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs,
mas3));
+ DEFINE(MAS6, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs,
mas6));
+ DEFINE(MAS7, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs,
mas7));
+ DEFINE(_SRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs,
srr0));
+ DEFINE(_SRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs,
srr1));
+ DEFINE(_CSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs,
csrr0));
+ DEFINE(_CSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs,
csrr1));
+ DEFINE(_DSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs,
dsrr0));
+ DEFINE(_DSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs,
dsrr1));
+ DEFINE(SAVED_KSP_LIMIT, STACK_INT_FRAME_SIZE+offsetof(struct
exception_regs, saved_ksp_limit));
+#endif
+
DEFINE(CLONE_VM, CLONE_VM);
DEFINE(CLONE_UNTRACED, CLONE_UNTRACED);
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index c94aba5..fe21674 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -46,14 +46,52 @@
#ifdef CONFIG_BOOKE
.globl mcheck_transfer_to_handler
mcheck_transfer_to_handler:
- b transfer_to_handler_full
+ mfspr r0,SPRN_DSRR0
+ stw r0,_DSRR0(r11)
+ mfspr r0,SPRN_DSRR1
+ stw r0,_DSRR1(r11)
+ /* fall through */
.globl debug_transfer_to_handler
debug_transfer_to_handler:
- b transfer_to_handler_full
+ mfspr r0,SPRN_CSRR0
+ stw r0,_CSRR0(r11)
+ mfspr r0,SPRN_CSRR1
+ stw r0,_CSRR1(r11)
+ /* fall through */
.globl crit_transfer_to_handler
crit_transfer_to_handler:
+#ifdef CONFIG_FSL_BOOKE
+ mfspr r0,SPRN_MAS0
+ stw r0,MAS0(r11)
+ mfspr r0,SPRN_MAS1
+ stw r0,MAS1(r11)
+ mfspr r0,SPRN_MAS2
+ stw r0,MAS2(r11)
+ mfspr r0,SPRN_MAS3
+ stw r0,MAS3(r11)
+ mfspr r0,SPRN_MAS6
+ stw r0,MAS6(r11)
+#ifdef CONFIG_PHYS_64BIT
+ mfspr r0,SPRN_MAS7
+ stw r0,MAS7(r11)
+#endif /* CONFIG_PHYS_64BIT */
+#endif /* CONFIG_FSL_BOOKE */
+#ifdef CONFIG_44x
+ mfspr r0,SPRN_MMUCR
+ stw r0,MMUCR(r11)
+#endif
+ mfspr r0,SPRN_SRR0
+ stw r0,_SRR0(r11)
+ mfspr r0,SPRN_SRR1
+ stw r0,_SRR1(r11)
+
+ mfspr r8,SPRN_SPRG3
+ lwz r0,KSP_LIMIT(r8)
+ stw r0,SAVED_KSP_LIMIT(r11)
+ rlwimi r0,r1,0,0,(31-THREAD_SHIFT)
+ stw r0,KSP_LIMIT(r8)
/* fall through */
#endif
@@ -64,6 +102,16 @@ crit_transfer_to_handler:
stw r0,GPR10(r11)
lwz r0,[EMAIL PROTECTED](0)
Re: [PATCH 0/4] minor fixes for 2.6.26
On May 19, 2008, at 6:07 PM, Paul Mackerras wrote: Kumar Gala writes: Kumar Gala (4): lmb: Fix compile warning [POWERPC] Remove generated files on make clean I think that adding zImage.* to clean-files is a bad idea, because we have zImage.lds.S, zImage.coff.lds.S and zImage.ps3.lds.S in arch/powerpc/boot that we don't want deleted. It would be OK for compiling with a separate object directory but would be bad for compiling in the source directory. We already had them in clean-files: clean-files := $(zlib) $(zlibheader) $(zliblinuxheader) \ empty.c zImage zImage.coff.lds zImage.ps3.lds zImage.lds - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
dtc: Remove reference to dead Makefile variables
Previous cleanups have removed the LIBFDT_CLEANFILES and DTC_CLEANFILES variables from the Makefiles. However, they're still referenced by the Makefile. This patch gets rid of these last vestiges. Signed-off-by: David Gibson <[EMAIL PROTECTED]> Index: dtc/Makefile === --- dtc.orig/Makefile 2008-05-20 14:47:38.0 +1000 +++ dtc/Makefile2008-05-20 14:48:06.0 +1000 @@ -150,7 +150,6 @@ $(LIBFDT_lib): $(addprefix $(LIBFDT_objd libfdt_clean: @$(VECHO) CLEAN "(libfdt)" rm -f $(addprefix $(LIBFDT_objdir)/,$(STD_CLEANFILES)) - rm -f $(addprefix $(LIBFDT_objdir)/,$(LIBFDT_CLEANFILES)) ifneq ($(DEPTARGETS),) -include $(LIBFDT_OBJS:%.o=$(LIBFDT_objdir)/%.d) @@ -170,7 +169,7 @@ STD_CLEANFILES = *~ *.o *.d *.a *.i *.s clean: libfdt_clean tests_clean @$(VECHO) CLEAN - rm -f $(STD_CLEANFILES) $(DTC_CLEANFILES) + rm -f $(STD_CLEANFILES) rm -f $(VERSION_FILE) rm -f $(BIN) -- David Gibson| I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 2/7] [POWERPC] QE: add support for QE USB clocks routing
Hi Anton, On Mon, 19 May 2008 21:46:55 +0400 Anton Vorontsov <[EMAIL PROTECTED]> wrote: > > +++ b/arch/powerpc/sysdev/qe_lib/usb.c > +#include Nothing in this file requires anything in linux/of.h or asm/of.h ... -- Cheers, Stephen Rothwell[EMAIL PROTECTED] http://www.canb.auug.org.au/~sfr/ pgpO14gUH1XTt.pgp Description: PGP signature ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
dtc: Fix some printf() format warnings when compiling 64-bit
Currently, dtc generates a few gcc build warnings if built for a
64-bit target, due to the altered type of uint64_t and size_t. This
patch fixes the warnings (without generating new warnings for 32-bit).
Signed-off-by: David Gibson <[EMAIL PROTECTED]>
Index: dtc/tests/dtbs_equal_ordered.c
===
--- dtc.orig/tests/dtbs_equal_ordered.c 2008-05-20 13:06:50.0 +1000
+++ dtc/tests/dtbs_equal_ordered.c 2008-05-20 13:07:41.0 +1000
@@ -49,7 +49,10 @@ void compare_mem_rsv(const void *fdt1, c
if ((addr1 != addr2) || (size1 != size2))
FAIL("Mismatch in reserve entry %d: "
"(0x%llx, 0x%llx) != (0x%llx, 0x%llx)", i,
-addr1, size1, addr2, size2);
+(unsigned long long)addr1,
+(unsigned long long)size1,
+(unsigned long long)addr2,
+(unsigned long long)size2);
}
}
Index: dtc/tests/references.c
===
--- dtc.orig/tests/references.c 2008-05-20 13:05:21.0 +1000
+++ dtc/tests/references.c 2008-05-20 13:05:53.0 +1000
@@ -38,7 +38,7 @@ void check_ref(const void *fdt, int node
if (!p)
FAIL("fdt_getprop(%d, \"ref\"): %s", node, fdt_strerror(len));
if (len != sizeof(*p))
- FAIL("'ref' in node at %d has wrong size (%d instead of %d)",
+ FAIL("'ref' in node at %d has wrong size (%d instead of %zd)",
node, len, sizeof(*p));
ref = fdt32_to_cpu(*p);
if (ref != checkref)
@@ -49,7 +49,7 @@ void check_ref(const void *fdt, int node
if (!p)
FAIL("fdt_getprop(%d, \"lref\"): %s", node, fdt_strerror(len));
if (len != sizeof(*p))
- FAIL("'lref' in node at %d has wrong size (%d instead of %d)",
+ FAIL("'lref' in node at %d has wrong size (%d instead of %zd)",
node, len, sizeof(*p));
ref = fdt32_to_cpu(*p);
if (ref != checkref)
--
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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Re: dtc: Add program to convert dts files from v0 to v1
On Mon, May 19, 2008 at 09:23:02PM -0500, Jon Loeliger wrote: > > This patch adds a new utility program, convert-dtsv0, to the dtc > > sources. This program will convert dts files from v0 to v1, > > preserving comments and spacing. It also includes some heuristics to > > guess an appropriate base to use in the v1 output (so it will use hex > > for the contents of reg properties and decimal for clock-frequency > > properties, for example). They're limited and imperfect, but not > > terrible. > > > > The guts of the converter program is a modified version of the lexer > > from dtc itself. > > > > Signed-off-by: David Gibson <[EMAIL PROTECTED]> > > Applied. > > For the record, I'd like to eventually retire this program > as well as support for /dts-v0/. Noted. I think having this program available will help speed up the arrival of the day we can do that, though. -- David Gibson| I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 0/4] minor fixes for 2.6.26
On Tue, May 20, 2008 at 04:22:40AM +0200, Segher Boessenkool wrote: Arguably this suggests we should rename either the lds files or the zImages so that we *can* get a pattern to match. >>> >>> Not really. Just define a $(ALL_ZIMAGES) var and use that everywhere. >>> I would be pretty upset if "make clean" decided to delete my >>> zImage.backup, >>> etc. >> >> That won't work for .gitignore. > > Sure, * is fine in .gitignore (and then un-ignore the few files you > don't want ignored). .gitignore is just a convenience thing, after > all. > >> Besides it's hard to generate, since >> zImage. can be generated based on dts names. > > Tricky. But if make can generate the name _at all_ (and it can), > it can do it here, too. It just needs some fairy dust sprinkling. > >> Oh, and variables like that are usually a bad idea for clean rules, >> because if new things have just been added/removed from the list, it >> will fail to clean up things built before the makefile change was >> made. > > Yes. OTOH, using xx* in "make clean" is an even worse idea. Well, yeah, hence with the name-changing... -- David Gibson| I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [patch v2] LMB: Add basic spin locking to lmb
From: Benjamin Herrenschmidt <[EMAIL PROTECTED]> Date: Mon, 19 May 2008 22:32:58 -0400 > I think the core memory hotplug is... However, we used to not change the > LMB when doing so (afaik, I'm travelling and not looking at the code > right now). However, things like PS3 memory hotplug tries to keep LMB is > sync for the sake of /dev/mem or similar and that happens before the > memory is added to the core. But if the memory hotplug is synchronized, so are changes to the LMB tables. And if there are LMB read side access concernes outside of the hotplug event, ideally we should use the synchronization mechanism that hotplug uses instead of adding a new one. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [patch v2] LMB: Add basic spin locking to lmb
On Mon, 2008-05-19 at 19:22 -0700, David Miller wrote: > From: Geoff Levand <[EMAIL PROTECTED]> > Date: Mon, 19 May 2008 17:55:45 -0700 > > > Add a spinlock to struct lmb to enforce concurrency in > > lmb_add(), lmb_remove(), lmb_analyze(), lmb_find(), and > > lmb_dump_all(). > > > > This locking is needed for SMP systems that access the lmb structure > > during hot memory add and remove operations after secondary cpus > > have been started. > > > > Signed-off-by: Geoff Levand <[EMAIL PROTECTED]> > > --- > > > > v2: o Add locking to lmb_find(). > > I'm not against this patch, but I'm pretty sure it's not > necessary. Isn't memory hotplug already synchronized at > a higher level? > > If not, it should be. I think the core memory hotplug is... However, we used to not change the LMB when doing so (afaik, I'm travelling and not looking at the code right now). However, things like PS3 memory hotplug tries to keep LMB is sync for the sake of /dev/mem or similar and that happens before the memory is added to the core. Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
RE: [PATCH 2/4 V5] MSI support on 83xx/85xx/86xx board
> -Original Message- > From: Michael Ellerman [mailto:[EMAIL PROTECTED] > Sent: Monday, May 19, 2008 10:09 AM > To: Jin Zhengxiong > Cc: [EMAIL PROTECTED]; linuxppc-dev@ozlabs.org; > [EMAIL PROTECTED] > Subject: Re: [PATCH 2/4 V5] MSI support on 83xx/85xx/86xx board > > On Fri, 2008-05-16 at 17:50 +0800, Jason Jin wrote: > > This MSI driver can be used on 83xx/85xx/86xx board. > > In this driver, virtual interrupt host and chip were setup. > There are > > 256 MSI interrupts in this host, Every 32 MSI interrupts > cascaded to > > one IPIC/MPIC interrupt. > > The chip was treated as edge sensitive and some necessary functions > > were setup for this chip. > > > > Before using the MSI interrupt, PCI/PCIE device need to ask > for a MSI > > interrupt in the 256 MSI interrupts. A 256bit bitmap show which MSI > > interrupt was used, reserve bit in the bitmap can be used > to force the > > device use some designate MSI interrupt in the 256 MSI interrupts. > > Sometimes this is useful for testing the all the MSI > interrupts. The > > msi-available-ranges property in the dts file was used for this > > purpose. > > > > Signed-off-by: Jason Jin <[EMAIL PROTECTED]> > > --- > > In the V5 version: > > Make the msi-availble-ranges optional, remove the match > function from > > the driver, change the compatible according the change in dts. > > Looks good, MSI bits: > > Acked-by: Michael Ellerman <[EMAIL PROTECTED]> > > cheers Thanks, Michael. Kumar, Could you please apply the MSI related patches. Thanks Jason ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
RE: [PATCH 2/4 V5] MSI support on 83xx/85xx/86xx board
Hi Stephen,
Thanks for the comments, I'd like to clean up some of the
codes by patch after some updates(such as irq_alloc_host you
mentioned).
Jason
> -Original Message-
> From: Stephen Rothwell [mailto:[EMAIL PROTECTED]
> Sent: Monday, May 19, 2008 11:34 AM
> To: Jin Zhengxiong
> Cc: [EMAIL PROTECTED]; linuxppc-dev@ozlabs.org
> Subject: Re: [PATCH 2/4 V5] MSI support on 83xx/85xx/86xx board
>
> Hi Jason,
>
> Just a couple of comments. All of which you may ignore. :-)
>
> On Fri, 16 May 2008 17:50:45 +0800 Jason Jin
> <[EMAIL PROTECTED]> wrote:
> >
> > +static int fsl_msi_free_dt_hwirqs(struct fsl_msi *msi) {
>
> > + if ((len % 0x8) != 0) {
>
> why not (len % (2 * sizeof(u32))) ?
>
> > + /* Format is: ( )+ */
> > + len /= sizeof(u32);
> > + len /= 2;
>
> len /= 2 * sizeof(u32);
>
> > + for (i = 0; i < len; i++, p += 2)
>
> for (len /= 2 * sizeof(u32); len; len--, p += 2)
>
> These are just style so you can ignore me if you like :-)
>
> > +static int __devinit fsl_of_msi_probe(struct of_device *dev,
> > + const struct of_device_id *match) {
> > + struct fsl_msi *msi;
> > + struct resource res;
> > + int err, i, count;
> > + int rc;
> > + int virt_msir;
> > + const u32 *p;
> > + struct fsl_msi_feature *tmp_data;
> > +
> > + printk(KERN_DEBUG "Setting up Freescale MSI support\n");
> > +
> > + msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
> > + if (!msi) {
> > + dev_err(&dev->dev, "No memory for MSI structure\n");
> > + err = -ENOMEM;
> > + goto error_out;
> > + }
> > +
> > + msi->of_node = dev->node;
>
> You need to of_node_get dev->node [i.e. msi->of_node =
> of_node_get(dev->node)] and if you delay this as far as
> possible, you won't need of_node_put(msi->of_node) in the erro path.
>
> > + msi->irqhost = irq_alloc_host(of_node_get(dev->node),
>
> irq_alloc_host should do the of_node_get if it needs to.
> Which it doesn't (at the moment), so just leave it as you
> have it and it will be cleaned up when irq_alloc_host is fixed.
>
> --
> Cheers,
> Stephen Rothwell[EMAIL PROTECTED]
> http://www.canb.auug.org.au/~sfr/
>
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Re: dtc: Add program to convert dts files from v0 to v1
> This patch adds a new utility program, convert-dtsv0, to the dtc > sources. This program will convert dts files from v0 to v1, > preserving comments and spacing. It also includes some heuristics to > guess an appropriate base to use in the v1 output (so it will use hex > for the contents of reg properties and decimal for clock-frequency > properties, for example). They're limited and imperfect, but not > terrible. > > The guts of the converter program is a modified version of the lexer > from dtc itself. > > Signed-off-by: David Gibson <[EMAIL PROTECTED]> Applied. For the record, I'd like to eventually retire this program as well as support for /dts-v0/. jdl ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 0/4] minor fixes for 2.6.26
Arguably this suggests we should rename either the lds files or the zImages so that we *can* get a pattern to match. Not really. Just define a $(ALL_ZIMAGES) var and use that everywhere. I would be pretty upset if "make clean" decided to delete my zImage.backup, etc. That won't work for .gitignore. Sure, * is fine in .gitignore (and then un-ignore the few files you don't want ignored). .gitignore is just a convenience thing, after all. Besides it's hard to generate, since zImage. can be generated based on dts names. Tricky. But if make can generate the name _at all_ (and it can), it can do it here, too. It just needs some fairy dust sprinkling. Oh, and variables like that are usually a bad idea for clean rules, because if new things have just been added/removed from the list, it will fail to clean up things built before the makefile change was made. Yes. OTOH, using xx* in "make clean" is an even worse idea. Segher ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [patch v2] LMB: Add basic spin locking to lmb
From: Geoff Levand <[EMAIL PROTECTED]> Date: Mon, 19 May 2008 17:55:45 -0700 > Add a spinlock to struct lmb to enforce concurrency in > lmb_add(), lmb_remove(), lmb_analyze(), lmb_find(), and > lmb_dump_all(). > > This locking is needed for SMP systems that access the lmb structure > during hot memory add and remove operations after secondary cpus > have been started. > > Signed-off-by: Geoff Levand <[EMAIL PROTECTED]> > --- > > v2: o Add locking to lmb_find(). I'm not against this patch, but I'm pretty sure it's not necessary. Isn't memory hotplug already synchronized at a higher level? If not, it should be. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH v3 3/3] [POWERPC] 40x/Book-E: Save/restore volatile exception registers
On Fri, 16 May 2008 14:08:00 -0500 (CDT) Kumar Gala <[EMAIL PROTECTED]> wrote: > On machines with more than one exception level any system register that > might be modified by the "normal" exception level needs to be saved and > restored on taking a higher level exception. We already are saving > and restoring ESR and DEAR. > > For critical level add SRR0/1. > For debug level add CSRR0/1 and SRR0/1. > For machine check level add DSRR0/1, CSRR0/1, and SRR0/1. > > On FSL Book-E parts we always save/restore the MAS registers for critical, > debug, and machine check level exceptions. On 44x we always save/restore > the MMUCR. > > Additionally, we save and restore the ksp_limit since we have to adjust it > for each exception level. > > Signed-off-by: Kumar Gala <[EMAIL PROTECTED]> > --- > --- a/arch/powerpc/kernel/entry_32.S > +++ b/arch/powerpc/kernel/entry_32.S > +#ifdef CONFIG_40x > .globl ret_from_crit_exc > ret_from_crit_exc: > + mfspr r9,SPRN_SPRG3 lis r10,[EMAIL PROTECTED]; lwz r10,[EMAIL PROTECTED](r10); tovirt(r9,r9); > + stw r10,KSP_LIMIT(r9) lis r9, [EMAIL PROTECTED]; lwz r9, [EMAIL PROTECTED](r9); lis r10, [EMAIL PROTECTED]; lwz r10, [EMAIL PROTECTED](r10); > + mtspr SPRN_SRR0,r9; > + mtspr SPRN_SRR1,r10; > RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, RFCI) > +#endif /* CONFIG_40x */ With the above changes, I no longer get kernel panics on returning from critical exceptions. Breakpoints and single stepping worked on my 405GP board. Again, not stress tested but it's looking much better. josh ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 0/4] minor fixes for 2.6.26
On Tue, May 20, 2008 at 04:03:47AM +0200, Segher Boessenkool wrote: >>> I think that adding zImage.* to clean-files is a bad idea, because we >>> have zImage.lds.S, zImage.coff.lds.S and zImage.ps3.lds.S in >>> arch/powerpc/boot that we don't want deleted. It would be OK for >>> compiling with a separate object directory but would be bad for >>> compiling in the source directory. >> >> Arguably this suggests we should rename either the lds files or the >> zImages so that we *can* get a pattern to match. > > Not really. Just define a $(ALL_ZIMAGES) var and use that everywhere. > I would be pretty upset if "make clean" decided to delete my > zImage.backup, > etc. That won't work for .gitignore. Besides it's hard to generate, since zImage. can be generated based on dts names. Oh, and variables like that are usually a bad idea for clean rules, because if new things have just been added/removed from the list, it will fail to clean up things built before the makefile change was made. -- David Gibson| I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 0/4] minor fixes for 2.6.26
I think that adding zImage.* to clean-files is a bad idea, because we have zImage.lds.S, zImage.coff.lds.S and zImage.ps3.lds.S in arch/powerpc/boot that we don't want deleted. It would be OK for compiling with a separate object directory but would be bad for compiling in the source directory. Arguably this suggests we should rename either the lds files or the zImages so that we *can* get a pattern to match. Not really. Just define a $(ALL_ZIMAGES) var and use that everywhere. I would be pretty upset if "make clean" decided to delete my zImage.backup, etc. Segher ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 1/5 v3] powerpc: DTS file for the C2K
On Mon, May 19, 2008 at 05:00:23PM -0700, Remi Machet wrote:
> Support for the C2K cPCI Single Board Computer from GEFanuc
> (PowerPC MPC7448 with a Marvell MV64460 chipset)
> All features of the board are not supported yet, but the board
> boots, flash works, all Ethernet ports are working and PCI
> devices are all found (USB and SATA on PCI1 do not work yet).
>
> Part 1 of 5: DTS file describing the board peripherals. As far as I know
> all peripherals except the FPGA are listed in there (I did not included
> the FPGA because a lot of work is needed there).
[snip]
> + [EMAIL PROTECTED] {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "marvell,mv64360-eth-group";
> + reg = <0x2000 0x2000>;
> + PHY0: [EMAIL PROTECTED] {
> + device_type = "ethernet-phy";
> + interrupts = <76>; /* GPP 12 */
> + interrupt-parent = <&PIC>;
> + reg = <0>;
> + };
> + [EMAIL PROTECTED] {
> + device_type = "network";
> + compatible = "marvell,mv64360-eth";
> + reg = <0>;
> + interrupts = <32>;
> + interrupt-parent = <&PIC>;
> + phy = <&PHY0>;
> + local-mac-address = [ 00 00 00 00 00 00 ];
> + };
Not sure if this is new, or I just didn't notice it before. Also not
sure if this is your mistake, or a mistake in the binding for the
marvell device here.
The address in "reg" should be unique within the bus the device
appears on. So having both the PHY and the MAC devices with the same
"reg" and same unit address here is bad.
Having both the PHYs and the MACs as children of the ethernet-group
node is possible, but the addresses must be encoded to distinguish
them (e.g. MACs are 0x0, 0x1, 0x2, PHYS are 0x1000 0x1001 0x1002).
--
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
___
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Re: [PATCH 1/1] ibmvscsi: Non SCSI error status fixup
On Mon, 2008-05-19 at 10:56 -0500, Dave Boutcher wrote: > On Mon, 19 May 2008 10:27:56 -0500, Brian King <[EMAIL PROTECTED]> said: > > > > Some versions of the Virtual I/O Server on Power > > return 0x99 in the non-SCSI error status field as success, > > rather than 0. This fixes the ibmvscsi driver to treat this > > response as success. > > Yeah0x99...that's an intuitive value for success. Hopefully there are no versions that return 0x99 for an error? :) cheers -- Michael Ellerman OzLabs, IBM Australia Development Lab wwweb: http://michael.ellerman.id.au phone: +61 2 6212 1183 (tie line 70 21183) We do not inherit the earth from our ancestors, we borrow it from our children. - S.M.A.R.T Person signature.asc Description: This is a digitally signed message part ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: DTC patches
On Mon, May 19, 2008 at 07:53:14PM -0500, Jon Loeliger wrote: > > On Mon, May 19, 2008 at 02:22:31PM -0500, Jon Loeliger wrote: > > > > This leaves one outstanding dtc patch from me; the v0 to v1 conversion > > program. > > Ah, I wasn't sure if we wanted to include that in > the mess or not. There's a theory that says we've > converted them all and don't need to do it ever again. :-) Well, we've converted the in-kernel ones, but there are probably people out there with other v0 files. Nice to give them a conversion tool too. -- David Gibson| I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 0/4] minor fixes for 2.6.26
On Tue, May 20, 2008 at 09:07:14AM +1000, Paul Mackerras wrote: > Kumar Gala writes: > > > > Kumar Gala (4): > > > lmb: Fix compile warning > > > [POWERPC] Remove generated files on make clean > > I think that adding zImage.* to clean-files is a bad idea, because we > have zImage.lds.S, zImage.coff.lds.S and zImage.ps3.lds.S in > arch/powerpc/boot that we don't want deleted. It would be OK for > compiling with a separate object directory but would be bad for > compiling in the source directory. Arguably this suggests we should rename either the lds files or the zImages so that we *can* get a pattern to match. -- David Gibson| I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[patch v2] LMB: Add basic spin locking to lmb
Add a spinlock to struct lmb to enforce concurrency in
lmb_add(), lmb_remove(), lmb_analyze(), lmb_find(), and
lmb_dump_all().
This locking is needed for SMP systems that access the lmb structure
during hot memory add and remove operations after secondary cpus
have been started.
Signed-off-by: Geoff Levand <[EMAIL PROTECTED]>
---
v2: o Add locking to lmb_find().
include/linux/lmb.h |1
lib/lmb.c | 62
2 files changed, 49 insertions(+), 14 deletions(-)
--- a/include/linux/lmb.h
+++ b/include/linux/lmb.h
@@ -30,6 +30,7 @@ struct lmb_region {
};
struct lmb {
+ spinlock_t lock;
unsigned long debug;
u64 rmo_size;
struct lmb_region memory;
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -32,28 +32,33 @@ early_param("lmb", early_lmb);
void lmb_dump_all(void)
{
unsigned long i;
+ struct lmb tmp;
if (!lmb_debug)
return;
+ spin_lock(&lmb.lock);
+ tmp = lmb;
+ spin_unlock(&lmb.lock);
+
pr_info("lmb_dump_all:\n");
- pr_info("memory.cnt = 0x%lx\n", lmb.memory.cnt);
+ pr_info("memory.cnt = 0x%lx\n", tmp.memory.cnt);
pr_info("memory.size = 0x%llx\n",
- (unsigned long long)lmb.memory.size);
- for (i=0; i < lmb.memory.cnt ;i++) {
+ (unsigned long long)tmp.memory.size);
+ for (i=0; i < tmp.memory.cnt ;i++) {
pr_info("memory.region[0x%lx].base = 0x%llx\n",
- i, (unsigned long long)lmb.memory.region[i].base);
+ i, (unsigned long long)tmp.memory.region[i].base);
pr_info(" .size = 0x%llx\n",
- (unsigned long long)lmb.memory.region[i].size);
+ (unsigned long long)tmp.memory.region[i].size);
}
- pr_info("reserved.cnt = 0x%lx\n", lmb.reserved.cnt);
- pr_info("reserved.size= 0x%lx\n", lmb.reserved.size);
- for (i=0; i < lmb.reserved.cnt ;i++) {
+ pr_info("reserved.cnt = 0x%lx\n", tmp.reserved.cnt);
+ pr_info("reserved.size= 0x%lx\n", tmp.reserved.size);
+ for (i=0; i < tmp.reserved.cnt ;i++) {
pr_info("reserved.region[0x%lx].base = 0x%llx\n",
- i, (unsigned long long)lmb.reserved.region[i].base);
+ i, (unsigned long long)tmp.reserved.region[i].base);
pr_info(" .size = 0x%llx\n",
- (unsigned long long)lmb.reserved.region[i].size);
+ (unsigned long long)tmp.reserved.region[i].size);
}
}
@@ -105,6 +110,8 @@ static void lmb_coalesce_regions(struct
void __init lmb_init(void)
{
+ spin_lock_init(&lmb.lock);
+
/* Create a dummy zero size LMB which will get coalesced away later.
* This simplifies the lmb_add() code below...
*/
@@ -122,10 +129,14 @@ void __init lmb_analyze(void)
{
int i;
+ spin_lock(&lmb.lock);
+
lmb.memory.size = 0;
for (i = 0; i < lmb.memory.cnt; i++)
lmb.memory.size += lmb.memory.region[i].size;
+
+ spin_unlock(&lmb.lock);
}
static long lmb_add_region(struct lmb_region *rgn, u64 base, u64 size)
@@ -194,18 +205,25 @@ static long lmb_add_region(struct lmb_re
long lmb_add(u64 base, u64 size)
{
+ long ret;
struct lmb_region *_rgn = &lmb.memory;
+ spin_lock(&lmb.lock);
+
/* On pSeries LPAR systems, the first LMB is our RMO region. */
if (base == 0)
lmb.rmo_size = size;
- return lmb_add_region(_rgn, base, size);
+ ret = lmb_add_region(_rgn, base, size);
+
+ spin_unlock(&lmb.lock);
+ return ret;
}
long lmb_remove(u64 base, u64 size)
{
+ long ret;
struct lmb_region *rgn = &(lmb.memory);
u64 rgnbegin, rgnend;
u64 end = base + size;
@@ -213,6 +231,8 @@ long lmb_remove(u64 base, u64 size)
rgnbegin = rgnend = 0; /* supress gcc warnings */
+ spin_lock(&lmb.lock);
+
/* Find the region where (base, size) belongs to */
for (i=0; i < rgn->cnt; i++) {
rgnbegin = rgn->region[i].base;
@@ -223,12 +243,15 @@ long lmb_remove(u64 base, u64 size)
}
/* Didn't find the region */
- if (i == rgn->cnt)
+ if (i == rgn->cnt) {
+ spin_unlock(&lmb.lock);
return -1;
+ }
/* Check to see if we are removing entire region */
if ((rgnbegin == base) && (rgnend == end)) {
lmb_remove_region(rgn, i);
+ spin_unlock(&lmb.lock);
return 0;
}
@@ -236,12 +259,14 @@ long lmb_remove(u64 base, u64 size)
if (rgnbegin == base) {
rgn->region[i].base = end;
rgn->region[i].size -= size;
+
Re: DTC patches
> On Mon, May 19, 2008 at 02:22:31PM -0500, Jon Loeliger wrote: > > This leaves one outstanding dtc patch from me; the v0 to v1 conversion > program. Ah, I wasn't sure if we wanted to include that in the mess or not. There's a theory that says we've converted them all and don't need to do it ever again. :-) jdl ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [RFC] GPIO-based flow control in the cpm_uart driver
On Tuesday 15 April 2008, Laurent Pinchart wrote: > Or maybe some kind of gpio_set_option() with flags specific to the > controller ? This could be used to enable open-drain outputs or internal > pull-ups for instance. That presumes that the pin config is associated with the GPIO controller, rather than being an independent modules... In the cases that a platform has such an association, there should be no problem just using a platform-specific code to do the relevant magic. - Dave ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [RFC] GPIO-based flow control in the cpm_uart driver
On Tuesday 15 April 2008, Laurent Pinchart wrote: > I'm implementing flow control and modem control lines support in the > cpm_uart driver. > > The implementation is based on the GPIO lib. Modem control lines are > described in the device tree as GPIO resources and accessed through the OF > GPIO bindings. The I/O ports have to be initialized as GPIOs in the > platform-specific code. I don't follow the "have to be" ... why couldn't the platform setup code know that if a given UART is being used with hardware handshaking, that means a particular pin mux config should be used? Are there maybe some on-chip routing options, so that for example RTS2 could come out on any of three different balls? (In which case that setup code could just be told *which* config to use...) In this case I'm asking specifically about the normal all-works-ok situation ... no errata or similar complications I mention below. > An option would be to export gpio_to_chip from drivers/gpio/gpiolib.c > and use cpm1/2_set_pin in the cpm_uart driver. Help me to understand this a bit. UARTs are a fair example of places where I've seen such pin reconfiguration be useful, but it's never seemed to be generalizable except possibly as callbacks to SOC-specific code (which don't imply updating generic programming interfaces). I've seen examples where the hardware flow control normally works, so that board setup sets up those pins in "hardware flow control" mode when it's told the board has them wired up that way ... but then, some chip revisions have errata forcing the driver to use a particular port's handshake pins as GPIOs in some cases. (Obviously troublesome except at low data rates, so one hopes the board designers just avoid using those UARTs in that mode.) I've also seen examples where the UART clock needs to be disabled in deeper sleep states, but the system still wants the UART to be a wake event source ... by having either the START bit, or maybe BREAK (it gives a longer latch period), kick in a gpio-based pin change IRQ on the UARTn.RX line. Now in *both* of those examples I've seen before, the solution could not be generic. When the pin was used as GPIO, a particular pinmux configuration was needed. (Bitfield X of register Y has value Z ... or maybe a couple registers needed to change.) And when used as a UART signal, a different one was used. (Same setup. Maybe value Z became value W. Or again, maybe a few registers needed changing.) And for different chips in the family, sometimes even different revisions of one chip, the W/X/Y/Z/etc values differed even for UART1. For other UARTs, the same was true. So given that ... how would knowing the GPIO chip help, when I'd still need to find out the W/X/Y/Z/etc values? And if I've got a way to convey W/X/Y/Z/etc -- canonical example being a callback to the relevant SOC-specific code -- why shouldn't that obviate the need for any scheme to look up the gpio chip? - Dave ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[rfc] [patch] LMB: Add basic spin locking to lmb
Add a spinlock to struct lmb to enforce concurrency in
lmb_add(), lmb_remove(), lmb_analyze(), and lmb_dump_all().
This locking is needed for SMP systems that access the lmb structure
during hot memory add and remove operations after secondary cpus
have been started.
Signed-off-by: Geoff Levand <[EMAIL PROTECTED]>
---
This patch just adds locks for the few lmb routines that would
be used for hot memory adding and removing.
-Geoff
include/linux/lmb.h |1
lib/lmb.c | 54 +++-
2 files changed, 42 insertions(+), 13 deletions(-)
--- a/include/linux/lmb.h
+++ b/include/linux/lmb.h
@@ -30,6 +30,7 @@ struct lmb_region {
};
struct lmb {
+ spinlock_t lock;
unsigned long debug;
u64 rmo_size;
struct lmb_region memory;
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -32,28 +32,33 @@ early_param("lmb", early_lmb);
void lmb_dump_all(void)
{
unsigned long i;
+ struct lmb tmp;
if (!lmb_debug)
return;
+ spin_lock(&lmb.lock);
+ tmp = lmb;
+ spin_unlock(&lmb.lock);
+
pr_info("lmb_dump_all:\n");
- pr_info("memory.cnt = 0x%lx\n", lmb.memory.cnt);
+ pr_info("memory.cnt = 0x%lx\n", tmp.memory.cnt);
pr_info("memory.size = 0x%llx\n",
- (unsigned long long)lmb.memory.size);
- for (i=0; i < lmb.memory.cnt ;i++) {
+ (unsigned long long)tmp.memory.size);
+ for (i=0; i < tmp.memory.cnt ;i++) {
pr_info("memory.region[0x%lx].base = 0x%llx\n",
- i, (unsigned long long)lmb.memory.region[i].base);
+ i, (unsigned long long)tmp.memory.region[i].base);
pr_info(" .size = 0x%llx\n",
- (unsigned long long)lmb.memory.region[i].size);
+ (unsigned long long)tmp.memory.region[i].size);
}
- pr_info("reserved.cnt = 0x%lx\n", lmb.reserved.cnt);
- pr_info("reserved.size= 0x%lx\n", lmb.reserved.size);
- for (i=0; i < lmb.reserved.cnt ;i++) {
+ pr_info("reserved.cnt = 0x%lx\n", tmp.reserved.cnt);
+ pr_info("reserved.size= 0x%lx\n", tmp.reserved.size);
+ for (i=0; i < tmp.reserved.cnt ;i++) {
pr_info("reserved.region[0x%lx].base = 0x%llx\n",
- i, (unsigned long long)lmb.reserved.region[i].base);
+ i, (unsigned long long)tmp.reserved.region[i].base);
pr_info(" .size = 0x%llx\n",
- (unsigned long long)lmb.reserved.region[i].size);
+ (unsigned long long)tmp.reserved.region[i].size);
}
}
@@ -105,6 +110,8 @@ static void lmb_coalesce_regions(struct
void __init lmb_init(void)
{
+ spin_lock_init(&lmb.lock);
+
/* Create a dummy zero size LMB which will get coalesced away later.
* This simplifies the lmb_add() code below...
*/
@@ -122,10 +129,14 @@ void __init lmb_analyze(void)
{
int i;
+ spin_lock(&lmb.lock);
+
lmb.memory.size = 0;
for (i = 0; i < lmb.memory.cnt; i++)
lmb.memory.size += lmb.memory.region[i].size;
+
+ spin_unlock(&lmb.lock);
}
static long lmb_add_region(struct lmb_region *rgn, u64 base, u64 size)
@@ -194,18 +205,25 @@ static long lmb_add_region(struct lmb_re
long lmb_add(u64 base, u64 size)
{
+ long ret;
struct lmb_region *_rgn = &lmb.memory;
+ spin_lock(&lmb.lock);
+
/* On pSeries LPAR systems, the first LMB is our RMO region. */
if (base == 0)
lmb.rmo_size = size;
- return lmb_add_region(_rgn, base, size);
+ ret = lmb_add_region(_rgn, base, size);
+
+ spin_unlock(&lmb.lock);
+ return ret;
}
long lmb_remove(u64 base, u64 size)
{
+ long ret;
struct lmb_region *rgn = &(lmb.memory);
u64 rgnbegin, rgnend;
u64 end = base + size;
@@ -213,6 +231,8 @@ long lmb_remove(u64 base, u64 size)
rgnbegin = rgnend = 0; /* supress gcc warnings */
+ spin_lock(&lmb.lock);
+
/* Find the region where (base, size) belongs to */
for (i=0; i < rgn->cnt; i++) {
rgnbegin = rgn->region[i].base;
@@ -223,12 +243,15 @@ long lmb_remove(u64 base, u64 size)
}
/* Didn't find the region */
- if (i == rgn->cnt)
+ if (i == rgn->cnt) {
+ spin_unlock(&lmb.lock);
return -1;
+ }
/* Check to see if we are removing entire region */
if ((rgnbegin == base) && (rgnend == end)) {
lmb_remove_region(rgn, i);
+ spin_unlock(&lmb.lock);
return 0;
}
@@ -236,12 +259,14 @@ long lmb_remove(u64 base, u64 size)
if (rgnbegin == base) {
rgn->region[i].b
Re: DTC patches
On Mon, May 19, 2008 at 02:22:31PM -0500, Jon Loeliger wrote: > > dtc: Simplify error handling for unparseable input [resend] > dtc: Clean up included Makefile fragments [resend] > dtc: Trivial formatting fixes [resend] > dtc: Make dt_from_blob() open its own input file, like the other input > formats [resend] > dtc: Rework handling of boot_cpuid_phys [resend] > > All applied and pushed out. Thanks. > dtc: Rework handling of boot_cpuid_phys [resend] > ^ > | > Please don't do this ---+ > > This forced an edit of each commit message by hand. > If you are going to do this, do this instead: > > Subject: [resend] dtc: Rework handling of boot_cpuid_phys Oops. sorry. This leaves one outstanding dtc patch from me; the v0 to v1 conversion program. -- David Gibson| I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 1/5 v2] powerpc: DTS file for the C2K
On Mon, May 19, 2008 at 10:53:02AM -0700, Remi Machet wrote:
> > On Mon, 2008-05-19 at 10:53 +1000, David Gibson wrote:
> > On Fri, May 16, 2008 at 12:28:48PM -0700, Remi Machet wrote:
> > > Support for the C2K cPCI Single Board Computer from GEFanuc
> > > (PowerPC MPC7448 with a Marvell MV64460 chipset)
> > > All features of the board are not supported yet, but the board
> > > boots, flash works, all Ethernet ports are working and PCI
> > > devices are all found (USB and SATA on PCI1 do not work yet).
> > >
> > > Part 1 of 5: DTS file describing the board peripherals. As far as I know
> > > all peripherals except the FPGA are listed in there (I did not included
> > > the FPGA because a lot of work is needed there).
> >
> > Looking pretty good, but a hanful more comments below.
> >
> > [snip]
> > > + mdio {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + compatible = "marvell,mv64360-mdio";
> >
> > Surely this needs a "reg" property, otherwise how to you access the
> > mdio bus?
> I am afraid this is another situation where the driver is not fully
> using the OF description ... the PHY registers address is hard-coded in
> drivers/net/mv643xx_eth.c. In any case I will add the reg property, and
> later on can try to modify the driver to make use of it.
Yes, do that. Again, the device tree describes hardware not
software's use of it, so just because the driver doesn't use it
properly yet isn't a reason to leave things out.
> > [snip]
> > > + /* Devices attached to the device controller */
> > > + devicebus {
> > > + compatible = "marvell,mv64306-devctrl";
> > > + #address-cells = <1>;
> > > + #size-cells = <1>;
> >
> > This looks like it needs either a "reg" or a "ranges" property. If
> > the address space of this "devicebus" is the same as the parent bus
> > you need an empty "ranges" property. *No* ranges property means the
> > subordinate devices can't be directly accessed at all from the parent
> > bus.
> This is a static bus with chip selects, I will look at other dts files
> to properly implement it (with the chipselect and range properties).
ebony.dts and bamboo.dts have examples of the 4xx EBC, and the
ibm4xx_fixup_ebc_ranges() function in arch/powerpc/boot/4xx.c gives an
example of constructing the ranges property from the bridge register
configuration. booting-without-of.txt has a binding for the freescale
chipselect / localbus.
--
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
___
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[PATCH 1/5 v3] powerpc: DTS file for the C2K
Support for the C2K cPCI Single Board Computer from GEFanuc
(PowerPC MPC7448 with a Marvell MV64460 chipset)
All features of the board are not supported yet, but the board
boots, flash works, all Ethernet ports are working and PCI
devices are all found (USB and SATA on PCI1 do not work yet).
Part 1 of 5: DTS file describing the board peripherals. As far as I know
all peripherals except the FPGA are listed in there (I did not included
the FPGA because a lot of work is needed there).
Signed-off-by: Remi Machet <[EMAIL PROTECTED]>
---
Changes:
v1: original patch
v2: cleaned up the file: removed i2c device_type, changed the name of
the cpu node and added aliases for the pci buses.
v3: removed the mdio entry because the PHY are handled by the Ethernet
driver on this board. Re-prganized the device controller entry to look
similar to other boards static buses (thanks to David Gibson for pointing
that out).
c2k.dts | 364
1 files changed, 364 insertions(+)
diff --git a/arch/powerpc/boot/dts/c2k.dts b/arch/powerpc/boot/dts/c2k.dts
new file mode 100644
index 000..5ef08b2
--- /dev/null
+++ b/arch/powerpc/boot/dts/c2k.dts
@@ -0,0 +1,364 @@
+/* Device Tree Source for GEFanuc C2K
+ *
+ * Author: Remi Machet <[EMAIL PROTECTED]>
+ *
+ * Originated from prpmc2800.dts
+ *
+ * 2008 (c) Stanford University
+ * 2007 (c) MontaVista, Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "C2K";
+ compatible = "GEFanuc,C2K";
+ coherency-off;
+
+ aliases {
+ pci0 = &PCI0;
+ pci1 = &PCI1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ [EMAIL PROTECTED] {
+ device_type = "cpu";
+ compatible = "PowerPC,7447";
+ reg = <0>;
+ clock-frequency = <99600>; /* 996 MHz */
+ bus-frequency = <16667>;/* 166. MHz */
+ timebase-frequency = <4167>;/* 166./4
MHz */
+ i-cache-line-size = <32>;
+ d-cache-line-size = <32>;
+ i-cache-size = <32768>;
+ d-cache-size = <32768>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x 0x4000>; /* 1GB */
+ };
+
+ [EMAIL PROTECTED] { /* Marvell Discovery */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "mv64460";
+ compatible = "marvell,mv64360";
+ clock-frequency = <16667>; /* 166.66... MHz */
+ reg = <0xd800 0x0001>;
+ virtual-reg = <0xd800>;
+ ranges = <0xd400 0xd400 0x0100 /* PCI 0 I/O
Space */
+ 0x8000 0x8000 0x0800 /* PCI 0 MEM
Space */
+ 0xd000 0xd000 0x0100 /* PCI 1 I/O
Space */
+ 0xa000 0xa000 0x0800 /* PCI 1 MEM
Space */
+ 0xd810 0xd810 0x0001 /* FPGA */
+ 0xd811 0xd811 0x0001 /* FPGA USARTs
*/
+ 0xf800 0xf800 0x0800 /* User FLASH */
+ 0x 0xd800 0x0001 /* Bridge's
regs */
+ 0xd814 0xd814 0x0004>;/* Integrated
SRAM */
+
+ [EMAIL PROTECTED] {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,mv64360-eth-group";
+ reg = <0x2000 0x2000>;
+ PHY0: [EMAIL PROTECTED] {
+ device_type = "ethernet-phy";
+ interrupts = <76>; /* GPP 12 */
+ interrupt-parent = <&PIC>;
+ reg = <0>;
+ };
+ [EMAIL PROTECTED] {
+ device_type = "network";
+ compatible = "marvell,mv64360-eth";
+ reg = <0>;
+ interrupts = <32>;
+ interrupt-parent = <&PIC>;
+ phy = <&PHY0>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ };
+ PHY1: [EMAIL PROTECTED] {
+ device_type = "ethernet-phy";
+
Re: [PATCH 0/4] minor fixes for 2.6.26
Kumar Gala writes: > > Kumar Gala (4): > > lmb: Fix compile warning > > [POWERPC] Remove generated files on make clean I think that adding zImage.* to clean-files is a bad idea, because we have zImage.lds.S, zImage.coff.lds.S and zImage.ps3.lds.S in arch/powerpc/boot that we don't want deleted. It would be OK for compiling with a separate object directory but would be bad for compiling in the source directory. Paul. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: .dtb file for mpc8641_hpcn failing on recent kernel/u-boot.
On Mon, 19 May 2008 22:57:29 + (UTC) Gary Hannon <[EMAIL PROTECTED]> wrote: > Am I missing a flag on the dtc? try adding -R 8 -S 0x3000 to the dtc command line. Kim ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
.dtb file for mpc8641_hpcn failing on recent kernel/u-boot.
Hi, I'm trying to boot a recent (2.6.25.4) kernel with a recent u-boot (1.3.3) and it's getting stuck very early in the boot. I'm using ../dtc -I dts -O dtb mpc8641_hpcn.dts > mpc8641_hpcn.dtb in arch/powerpc/boot/dts/ to create the .dtb file. => boot Speed: 100, full duplex Using eTSEC1 device TFTP from server 192.41.172.8; our IP address is 192.41.172.157 Filename 'pluto.uImage'. Load address: 0x100 Loading: # # ### done Bytes transferred = 2352548 (23e5a4 hex) Speed: 100, full duplex Using eTSEC1 device TFTP from server 192.41.172.8; our IP address is 192.41.172.157 Filename 'pluto.dtb'. Load address: 0xc0 Loading: # done Bytes transferred = 8722 (2212 hex) ## Booting kernel from Legacy Image at 0100 ... Image Name: Linux-2.6.25.4 Image Type: PowerPC Linux Kernel Image (gzip compressed) Data Size:2352484 Bytes = 2.2 MB Load Address: Entry Point: Verifying Checksum ... OK Uncompressing Kernel Image ... OK WARNING: adjusting available memory to 1000 ## Flattened Device Tree blob at 00c0 Booting using the fdt blob at 0xc0 Loading Device Tree to 007fd000, end 007ff211 ... OK WARNING: could not create /chosen FDT_ERR_NOSPACE. ERROR: /chosen node create failed - must RESET the board to recover. U-Boot 1.3.3 (May 19 2008 - 15:59:50) Freescale PowerPC CPU: Core: E600 Core 0, Version: 0.2, (0x80040202) System: Unknown, Version: 2.0, (0x80900120) Clocks: CPU:1000 MHz, MPX: 400 MHz, DDR: 200 MHz, LBC: 50 MHz L2: Enabled Board: MPC8641HPCN Results I get when booting are... . . . Continues in an infinite loop. I've not changed anything in the kernel or u-boot source. Do I need to add anything to u-boot's environment? Am I using the .dtb file incorrectly? Am I missing a flag on the dtc? Thanks for any pointers, Gary Hannon CSPI [EMAIL PROTECTED] ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
RE: Oops with PREEMPT-RT on 2.6.25.4
Rune Torgersen wrote:> Scott Wood wrote: > Of course I then ran headfirst into another one > This one seems to happen when I attempt to read flash through an mtd > driver. Both if these is hitting a BUG_ON in kmap_atomic (include/asm-powerpc/highmem.h) > > Oops: Exception in kernel mode, sig: 5 [#1] > PREEMPT Innovative Systems ApMax > Modules linked in: > NIP: c005e780 LR: c005e758 CTR: > REGS: ef2c1d20 TRAP: 0700 Not tainted (2.6.25.4-rt1) > MSR: 00029032 CR: 48222482 XER: 2000 > TASK = ef2a1a90[98] 'S21initenv' THREAD: ef2c > GPR00: 3ffcf581 ef2c1dd0 ef2a1a90 c02cae8c 0002 0001 > 3ffcf580 GPR08: c037 c037000c 28222484 1009ecc0 > 100a5838 GPR16: 1009 1009 1009 > ef2a7100 3ee38385 100955ac GPR24: ef2a4ef0 c27dc700 > c27dcb80 0003 ef359040 c0334f88 NIP [c005e780] > do_wp_page+0x650/0xc2c > LR [c005e758] do_wp_page+0x628/0xc2c > Call Trace: > [ef2c1dd0] [c005e758] do_wp_page+0x628/0xc2c (unreliable) > [ef2c1e10] [c0012420] do_page_fault+0x338/0x4b4 > [ef2c1f40] [c0010120] handle_page_fault+0xc/0x80 > --- Exception: 301 at 0x100322e0 > LR = 0x100322dc > Instruction dump: > 409e0594 4810f2e1 3d20c035 1fa3000f 8129b140 3bbd0003 57ab103a > 7c0b482e 7d6b4a14 540007fa 30e0 7cc70110 <0f06> 3d20c035 > 3d40c035 8129b480 Oops: Exception in kernel mode, sig: 5 [#2] > PREEMPT Innovative Systems ApMax > Modules linked in: > NIP: c005db0c LR: c005dae4 CTR: > REGS: ef29fd00 TRAP: 0700 Tainted: G D (2.6.25.4-rt1) > MSR: 00029032 CR: 48002482 XER: 2000 > TASK = ef26e070[102] 'sed' THREAD: ef29e000 > GPR00: 3ee2d581 ef29fdb0 ef26e070 c02cae8c 0001 > 3ee2d580 GPR08: c037 c037000c 0722 1009ecc0 > 4802dfa4 4802d878 GPR16: 0014f73c 0003 4802cce0 > 0001 0200 GPR24: ef3592e0 0ffece1c ef3592e0 ef2a50fc > ef2a4df4 0003 c27dcfe0 c27ff4c0 NIP [c005db0c] > __do_fault+0x1e0/0x804 > LR [c005dae4] __do_fault+0x1b8/0x804 > Call Trace: > [ef29fdb0] [c005dae4] __do_fault+0x1b8/0x804 (unreliable) > [ef29fe10] [c0012420] do_page_fault+0x338/0x4b4 > [ef29ff40] [c0010120] handle_page_fault+0xc/0x80 > --- Exception: 301 at 0x48017b10 > LR = 0x48007ac8 > Instruction dump: > 409e060c 4810ff55 3d20c035 1fa3000f 8129b140 3bbd0003 57ab103a > 7c0b482e 7d6b4a14 540007fa 30e0 7cc70110 <0f06> 3d20c035 > 3d40c035 8129b480 ___ > Linuxppc-dev mailing list > Linuxppc-dev@ozlabs.org > https://ozlabs.org/mailman/listinfo/linuxppc-dev ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[2.6 patch] powerpc/mm/hash_low_32.S: remove CVS keyword
This patch removes a CVS keyword that wasn't updated for a long time from a comment. Signed-off-by: Adrian Bunk <[EMAIL PROTECTED]> --- 92f17f771c22fa93afe058210ddf51920aca1451 diff --git a/arch/powerpc/mm/hash_low_32.S b/arch/powerpc/mm/hash_low_32.S index ddeaf9e..b9ba7d9 100644 --- a/arch/powerpc/mm/hash_low_32.S +++ b/arch/powerpc/mm/hash_low_32.S @@ -1,6 +1,4 @@ /* - * $Id: hashtable.S,v 1.6 1999/10/08 01:56:15 paulus Exp $ - * * PowerPC version *Copyright (C) 1995-1996 Gary Thomas ([EMAIL PROTECTED]) * Rewritten by Cort Dougan ([EMAIL PROTECTED]) for PReP ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
RE: Oops with PREEMPT-RT on 2.6.25.4
Scott Wood wrote: > Rune Torgersen wrote: >> Scott Wood wrote: >>> Try calling irq_set_chip_and_handler() with handle_level_irq, rather >>> than irq_set_chip(). The -rt patch doesn't seem to have threadified >>> the __do_IRQ() path. >> >> The demuxer is setting itself up with set_irq_chained handler(), any >> pointers on how to change to irq_set_chip_and_handler()? > > No, I mean the call to set_irq_chip() in pci_pic_host_map() where it > sets up the IRQs it manages, not the cascade IRQ itself. Thanks!!! That fixed that particular problem. Of course I then ran headfirst into another one This one seems to happen when I attempt to read flash through an mtd driver. Oops: Exception in kernel mode, sig: 5 [#1] PREEMPT Innovative Systems ApMax Modules linked in: NIP: c005e780 LR: c005e758 CTR: REGS: ef2c1d20 TRAP: 0700 Not tainted (2.6.25.4-rt1) MSR: 00029032 CR: 48222482 XER: 2000 TASK = ef2a1a90[98] 'S21initenv' THREAD: ef2c GPR00: 3ffcf581 ef2c1dd0 ef2a1a90 c02cae8c 0002 0001 3ffcf580 GPR08: c037 c037000c 28222484 1009ecc0 100a5838 GPR16: 1009 1009 1009 ef2a7100 3ee38385 100955ac GPR24: ef2a4ef0 c27dc700 c27dcb80 0003 ef359040 c0334f88 NIP [c005e780] do_wp_page+0x650/0xc2c LR [c005e758] do_wp_page+0x628/0xc2c Call Trace: [ef2c1dd0] [c005e758] do_wp_page+0x628/0xc2c (unreliable) [ef2c1e10] [c0012420] do_page_fault+0x338/0x4b4 [ef2c1f40] [c0010120] handle_page_fault+0xc/0x80 --- Exception: 301 at 0x100322e0 LR = 0x100322dc Instruction dump: 409e0594 4810f2e1 3d20c035 1fa3000f 8129b140 3bbd0003 57ab103a 7c0b482e 7d6b4a14 540007fa 30e0 7cc70110 <0f06> 3d20c035 3d40c035 8129b480 Oops: Exception in kernel mode, sig: 5 [#2] PREEMPT Innovative Systems ApMax Modules linked in: NIP: c005db0c LR: c005dae4 CTR: REGS: ef29fd00 TRAP: 0700 Tainted: G D (2.6.25.4-rt1) MSR: 00029032 CR: 48002482 XER: 2000 TASK = ef26e070[102] 'sed' THREAD: ef29e000 GPR00: 3ee2d581 ef29fdb0 ef26e070 c02cae8c 0001 3ee2d580 GPR08: c037 c037000c 0722 1009ecc0 4802dfa4 4802d878 GPR16: 0014f73c 0003 4802cce0 0001 0200 GPR24: ef3592e0 0ffece1c ef3592e0 ef2a50fc ef2a4df4 0003 c27dcfe0 c27ff4c0 NIP [c005db0c] __do_fault+0x1e0/0x804 LR [c005dae4] __do_fault+0x1b8/0x804 Call Trace: [ef29fdb0] [c005dae4] __do_fault+0x1b8/0x804 (unreliable) [ef29fe10] [c0012420] do_page_fault+0x338/0x4b4 [ef29ff40] [c0010120] handle_page_fault+0xc/0x80 --- Exception: 301 at 0x48017b10 LR = 0x48007ac8 Instruction dump: 409e060c 4810ff55 3d20c035 1fa3000f 8129b140 3bbd0003 57ab103a 7c0b482e 7d6b4a14 540007fa 30e0 7cc70110 <0f06> 3d20c035 3d40c035 8129b480 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: Oops with PREEMPT-RT on 2.6.25.4
Rune Torgersen wrote: Scott Wood wrote: Try calling irq_set_chip_and_handler() with handle_level_irq, rather than irq_set_chip(). The -rt patch doesn't seem to have threadified the __do_IRQ() path. The demuxer is setting itself up with set_irq_chained handler(), any pointers on how to change to irq_set_chip_and_handler()? No, I mean the call to set_irq_chip() in pci_pic_host_map() where it sets up the IRQs it manages, not the cascade IRQ itself. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
RE: Oops with PREEMPT-RT on 2.6.25.4
Scott Wood wrote: > Try calling irq_set_chip_and_handler() with handle_level_irq, rather > than irq_set_chip(). The -rt patch doesn't seem to have threadified > the __do_IRQ() path. The demuxer is setting itself up with set_irq_chained handler(), any pointers on how to change to irq_set_chip_and_handler()? ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: Oops with PREEMPT-RT on 2.6.25.4
Rune Torgersen wrote: Scott Wood wrote: Almost certainly the latter. Is the disk interrupt shared with any other interrupts, that are marked IRQF_NODELAY? The -rt patch doesn't seem to handle mixing the two well. Disk is on a muxed PCI interrupt. None of the other interrupts on the mux is fireing at the time. Regardless of whether they're firing, any request_irq with IRQF_NODELAY will turn off threading for all handlers. Is is possible that the demuxer is not set up right? It is based loosely on pq2-pci-pic.c Try calling irq_set_chip_and_handler() with handle_level_irq, rather than irq_set_chip(). The -rt patch doesn't seem to have threadified the __do_IRQ() path. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
RE: Oops with PREEMPT-RT on 2.6.25.4
Scott Wood wrote: > Almost certainly the latter. Is the disk interrupt shared with any > other interrupts, that are marked IRQF_NODELAY? The -rt > patch doesn't seem to handle mixing the two well. Disk is on a muxed PCI interrupt. None of the other interrupts on the mux is fireing at the time. Is is possible that the demuxer is not set up right? It is based loosely on pq2-pci-pic.c > Oh, and just to be sure: you do have CONFIG_PREEMPT_RT turned on, and > not just CONFIG_PREEMPT, right? The non-preempt-rt versions in the -rt > patch don't look like they disable interrupts, though I may just be > getting lost in a sea of underscores and ifdefs. Full CONFIG_PREEMPT_RT. I was actually going to try CONFIG_PREEMPT to see if anything helped. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH v3 1/3] [POWERPC] Move to runtime allocated exception stacks
On Fri, 16 May 2008 14:04:54 -0500 (CDT) Kumar Gala <[EMAIL PROTECTED]> wrote: > For the additonal exception levels (critical, debug, machine check) on > 40x/book-e we were using "static" allocations of the stack in the > associated head.S. > > Move to a runtime allocation to make the code a bit easier to read as > we mimic how we handle IRQ stacks. Its also a bit easier to setup the > stack with a "dummy" thread_info in C code. > > Signed-off-by: Kumar Gala <[EMAIL PROTECTED]> > --- > arch/powerpc/kernel/head_40x.S | 14 ++ > arch/powerpc/kernel/head_44x.S |9 - > arch/powerpc/kernel/head_booke.h | 29 +++-- > arch/powerpc/kernel/head_fsl_booke.S |9 - > arch/powerpc/kernel/irq.c| 33 + > arch/powerpc/kernel/setup_32.c | 24 > include/asm-powerpc/irq.h| 13 + > 7 files changed, 83 insertions(+), 48 deletions(-) > > diff --git a/arch/powerpc/kernel/head_40x.S b/arch/powerpc/kernel/head_40x.S > index 8552e67..ca75eaf 100644 > --- a/arch/powerpc/kernel/head_40x.S > +++ b/arch/powerpc/kernel/head_40x.S > @@ -148,8 +148,8 @@ _ENTRY(crit_r11) > mfcrr10;/* save CR in r10 for now */\ > mfspr r11,SPRN_SRR3; /* check whether user or kernel*/\ > andi. r11,r11,MSR_PR; \ > - lis r11,[EMAIL PROTECTED]; \ > - ori r11,r11,[EMAIL PROTECTED]; \ > + lis r11,[EMAIL PROTECTED]; \ You need a: tophys(r11,r11); \ here. That fixes the hangs I see on my Walnut (PPC405GP) board when using gdb. The problem is that we're in real mode at this point, but using the virtual address of critirq_ctx. That seems to be a bad idea when trying to load values out of it... ;) > + lwz r11,[EMAIL PROTECTED](r11); > \ > beq 1f; \ > /* COMING FROM USER MODE */ \ > mfspr r11,SPRN_SPRG3; /* if from user, start at top of */\ josh ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: Oops with PREEMPT-RT on 2.6.25.4
Rune Torgersen wrote: Scott Wood wrote: You're recursively entering lock_timer_base, which does a spin_lock_irqsave(). Either interrupts are enabled when they should not be, or an interrupt was supposed to be threaded that isn't. Sort of figured. How do I figure out which one, and how to fix it? Almost certainly the latter. Is the disk interrupt shared with any other interrupts, that are marked IRQF_NODELAY? The -rt patch doesn't seem to handle mixing the two well. Oh, and just to be sure: you do have CONFIG_PREEMPT_RT turned on, and not just CONFIG_PREEMPT, right? The non-preempt-rt versions in the -rt patch don't look like they disable interrupts, though I may just be getting lost in a sea of underscores and ifdefs. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: Oops with PREEMPT-RT on 2.6.25.4
Rune Torgersen wrote: Scott Wood wrote: You're recursively entering lock_timer_base, which does a spin_lock_irqsave(). Either interrupts are enabled when they should not be, or an interrupt was supposed to be threaded that isn't. Sort of figured. How do I figure out which one, and how to fix it? I've never gotten any -rt patchsets to work on this CPU, and it always seems to be related to the disk driver. I've tried since 2.6.16 ppc (2.6.16, 2.6.18 on ppc, 2.6.24 and 25 on powerpc) Even though this is a custom board, I'm pretty sure I can get it to fail on a pq2fads board with the same disk controller. Im not sure if LOCKDEP is available for that architecture. Have you tried it? Its pretty good at flushing these kinds of issues out (assuming its available). -Greg ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] CS4270 node is misplaced in the MPC8610 device tree
Timur Tabi wrote: > Anton Vorontsov wrote: > >> Hm... this should be controlled by the PIXIS' BRDCFG0's I2CSPAN and >> SERSEL bits: > > Since these pins should not have changed from one kernel version to another, > it > doesn't explain how my device "jumped" from I2C2 to I2C1. I'm debugging this > now. I found the problem. Your patch "86xx: mpc8610_hpcd: fix second serial port" fixes it. The original code moved the I2C devices from I2C1 to I2C2. On R1 boards, the default for I2CSPAN was 1 because the chip used on those boards would bridge the two buses together if I2CSPAN==1. On R3 boards, a different chip is used, and I2CSPAN==1 means to use I2C2 instead of I2C1. On R1 boards, the default for BRDCFG0 is 0xBD, but on R3 boards it's 0xB8. So when mpc8610hpcd_set_monitor_port() wrote 0xBD to BRDCFG0, it moved the I2C devices from I2C1 to I2C2. I also had a hard time pinpointing this code because mpc8610hpcd_set_monitor_port() is called only when the DIU is enabled. Since I don't have anything attached to my DIU port, I don't always enable the DIU. So some of my kernels had DIU support, and some of them didn't! Those kernels that have DIU enabled but not your patch will move the devices to I2C2. I was running one of those kernels when I posted my patch. So in summary, this patch "CS4270 node is misplaced in the MPC8610 device tree" should not be applied. The I2C devices should stay on I2C1. -- Timur Tabi Linux kernel developer at Freescale ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
RE: Oops with PREEMPT-RT on 2.6.25.4
Scott Wood wrote: > Rune Torgersen wrote: >> Hi >> I get the following oops when trying to boot a arch/powerpc kernel >> with preempt-rt installed (v2.6.25.4-rt1) >> The board is using a Freescale 8280 as the main CPU and a Silicon >> Image SII3124 SATA controller. The oops seems to happen on >> fileaccess right after init starts. > [snip] >> NIP [c0249618] rt_spin_lock_slowlock+0x9c/0x200 >> LR [c02495ec] rt_spin_lock_slowlock+0x70/0x200 >> Call Trace: >> [ef29d600] [c02495ec] rt_spin_lock_slowlock+0x70/0x200 (unreliable) >> [ef29d670] [c00277d0] lock_timer_base+0x2c/0x64 >> [ef29d690] [c00285e8] del_timer+0x2c/0x78 >> [ef29d6b0] [c019d108] scsi_delete_timer+0x1c/0x3c >> [ef29d6d0] [c01992d0] scsi_done+0x18/0x4c >> [ef29d6f0] [c01b19dc] ata_scsi_qc_complete+0x364/0x380 >> [ef29d720] [c01a8708] __ata_qc_complete+0xd8/0xec >> [ef29d740] [c01b011c] ata_qc_complete_multiple+0xc4/0xec >> [ef29d760] [c01bcaf4] sil24_interrupt+0x46c/0x52c >> [ef29d7a0] [c0048954] handle_IRQ_event+0x64/0x100 >> [ef29d7d0] [c0048b30] __do_IRQ+0x140/0x1bc >> [ef29d7f0] [c00166c4] apmax_int_irq_demux+0x8c/0xb0 >> [ef29d810] [c0006448] do_IRQ+0x68/0xa8 >> [ef29d820] [c0010388] ret_from_except+0x0/0x14 >> --- Exception: 501 at __spin_unlock_irqrestore+0x28/0x4c >> LR = __spin_unlock_irqrestore+0x20/0x4c >> [ef29d8f0] [c0249600] rt_spin_lock_slowlock+0x84/0x200 >> [ef29d960] [c00277d0] lock_timer_base+0x2c/0x64 > > You're recursively entering lock_timer_base, which does a > spin_lock_irqsave(). Either interrupts are enabled when they should > not be, or an interrupt was supposed to be threaded that isn't. Sort of figured. How do I figure out which one, and how to fix it? I've never gotten any -rt patchsets to work on this CPU, and it always seems to be related to the disk driver. I've tried since 2.6.16 ppc (2.6.16, 2.6.18 on ppc, 2.6.24 and 25 on powerpc) Even though this is a custom board, I'm pretty sure I can get it to fail on a pq2fads board with the same disk controller. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: Oops with PREEMPT-RT on 2.6.25.4
Rune Torgersen wrote: Hi I get the following oops when trying to boot a arch/powerpc kernel with preempt-rt installed (v2.6.25.4-rt1) The board is using a Freescale 8280 as the main CPU and a Silicon Image SII3124 SATA controller. The oops seems to happen on fileaccess right after init starts. [snip] NIP [c0249618] rt_spin_lock_slowlock+0x9c/0x200 LR [c02495ec] rt_spin_lock_slowlock+0x70/0x200 Call Trace: [ef29d600] [c02495ec] rt_spin_lock_slowlock+0x70/0x200 (unreliable) [ef29d670] [c00277d0] lock_timer_base+0x2c/0x64 [ef29d690] [c00285e8] del_timer+0x2c/0x78 [ef29d6b0] [c019d108] scsi_delete_timer+0x1c/0x3c [ef29d6d0] [c01992d0] scsi_done+0x18/0x4c [ef29d6f0] [c01b19dc] ata_scsi_qc_complete+0x364/0x380 [ef29d720] [c01a8708] __ata_qc_complete+0xd8/0xec [ef29d740] [c01b011c] ata_qc_complete_multiple+0xc4/0xec [ef29d760] [c01bcaf4] sil24_interrupt+0x46c/0x52c [ef29d7a0] [c0048954] handle_IRQ_event+0x64/0x100 [ef29d7d0] [c0048b30] __do_IRQ+0x140/0x1bc [ef29d7f0] [c00166c4] apmax_int_irq_demux+0x8c/0xb0 [ef29d810] [c0006448] do_IRQ+0x68/0xa8 [ef29d820] [c0010388] ret_from_except+0x0/0x14 --- Exception: 501 at __spin_unlock_irqrestore+0x28/0x4c LR = __spin_unlock_irqrestore+0x20/0x4c [ef29d8f0] [c0249600] rt_spin_lock_slowlock+0x84/0x200 [ef29d960] [c00277d0] lock_timer_base+0x2c/0x64 You're recursively entering lock_timer_base, which does a spin_lock_irqsave(). Either interrupts are enabled when they should not be, or an interrupt was supposed to be threaded that isn't. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
DTC patches
dtc: Simplify error handling for unparseable input [resend] dtc: Clean up included Makefile fragments [resend] dtc: Trivial formatting fixes [resend] dtc: Make dt_from_blob() open its own input file, like the other input formats [resend] dtc: Rework handling of boot_cpuid_phys [resend] All applied and pushed out. dtc: Rework handling of boot_cpuid_phys [resend] ^ | Please don't do this ---+ This forced an edit of each commit message by hand. If you are going to do this, do this instead: Subject: [resend] dtc: Rework handling of boot_cpuid_phys Thanks, jdl ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] CS4270 node is misplaced in the MPC8610 device tree
Anton Vorontsov wrote: > Hm... this should be controlled by the PIXIS' BRDCFG0's I2CSPAN and > SERSEL bits: Since these pins should not have changed from one kernel version to another, it doesn't explain how my device "jumped" from I2C2 to I2C1. I'm debugging this now. > 1: I2C1 and I2C2 are bridged. MPC8610 SPI functions may be used. All I2C >devices may be accessed via I2C1 controller and/or I2C2 (I2C2 depends on >SERSEL setting). I believe this is wrong. The chip documentation says that the pin controlled by I2CSPAN selects which of the two inputs to use. It does not bridge. -- Timur Tabi Linux kernel developer at Freescale ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Oops with PREEMPT-RT on 2.6.25.4
Hi I get the following oops when trying to boot a arch/powerpc kernel with preempt-rt installed (v2.6.25.4-rt1) The board is using a Freescale 8280 as the main CPU and a Silicon Image SII3124 SATA controller. The oops seems to happen on fileaccess right after init starts. I need ideas what to look for. Freeing unused kernel memory: 128k init INIT: version 2.85 booting Activating all swap files/partitions... [ OK ] Mounting proc file system...[ OK ] path=/bin:/usr/bin:/sbin:/usr/sbin Oops: Exception in kernel mode, sig: 5 [#1] PREEMPT Innovative Systems ApMax Modules linked in: NIP: c0249618 LR: c02495ec CTR: REGS: ef29d550 TRAP: 0700 Not tainted (2.6.25.4-rt1) MSR: 00021032 CR: 24044482 XER: TASK = ef26d070[50] 'ldconfig' THREAD: ef29c000 GPR00: 0001 ef29d600 ef26d070 ef29d64c 008c GPR08: ef29d628 ef29d630 ef29c000 100b5eec 100b GPR16: c00c3304 ef29dc48 000c 0014 0001 ef3818c0 GPR24: ef8a4000 0011 c01bc3c4 ef29d698 ef381904 9032 c0354700 NIP [c0249618] rt_spin_lock_slowlock+0x9c/0x200 LR [c02495ec] rt_spin_lock_slowlock+0x70/0x200 Call Trace: [ef29d600] [c02495ec] rt_spin_lock_slowlock+0x70/0x200 (unreliable) [ef29d670] [c00277d0] lock_timer_base+0x2c/0x64 [ef29d690] [c00285e8] del_timer+0x2c/0x78 [ef29d6b0] [c019d108] scsi_delete_timer+0x1c/0x3c [ef29d6d0] [c01992d0] scsi_done+0x18/0x4c [ef29d6f0] [c01b19dc] ata_scsi_qc_complete+0x364/0x380 [ef29d720] [c01a8708] __ata_qc_complete+0xd8/0xec [ef29d740] [c01b011c] ata_qc_complete_multiple+0xc4/0xec [ef29d760] [c01bcaf4] sil24_interrupt+0x46c/0x52c [ef29d7a0] [c0048954] handle_IRQ_event+0x64/0x100 [ef29d7d0] [c0048b30] __do_IRQ+0x140/0x1bc [ef29d7f0] [c00166c4] apmax_int_irq_demux+0x8c/0xb0 [ef29d810] [c0006448] do_IRQ+0x68/0xa8 [ef29d820] [c0010388] ret_from_except+0x0/0x14 --- Exception: 501 at __spin_unlock_irqrestore+0x28/0x4c LR = __spin_unlock_irqrestore+0x20/0x4c [ef29d8f0] [c0249600] rt_spin_lock_slowlock+0x84/0x200 [ef29d960] [c00277d0] lock_timer_base+0x2c/0x64 [ef29d980] [c002790c] __mod_timer+0x34/0xdc [ef29d9b0] [c0154650] blk_plug_device+0x58/0x68 [ef29d9c0] [c0154db0] __make_request+0x2dc/0x34c [ef29da00] [c0153aa4] generic_make_request+0x20c/0x238 [ef29da40] [c01550a8] submit_bio+0x124/0x138 [ef29da80] [c009a490] submit_bh+0x13c/0x174 [ef29daa0] [c009df9c] __bread+0xa4/0x100 [ef29dab0] [c00c2478] ext3_get_branch+0x78/0xfc [ef29dae0] [c00c27dc] ext3_get_blocks_handle+0x94/0x9cc [ef29dba0] [c00c3398] ext3_get_block+0x94/0xdc [ef29dbd0] [c00a458c] do_mpage_readpage+0x1a4/0x63c [ef29dc40] [c00a4b58] mpage_readpages+0xc4/0x11c [ef29dd20] [c00c269c] ext3_readpages+0x24/0x34 [ef29dd30] [c00572e4] __do_page_cache_readahead+0x1a0/0x258 [ef29dd70] [c00512bc] filemap_fault+0x198/0x41c [ef29ddb0] [c005d934] __do_fault+0x6c/0x804 [ef29de10] [c0012420] do_page_fault+0x338/0x4b4 [ef29df40] [c0010120] handle_page_fault+0xc/0x80 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] CS4270 node is misplaced in the MPC8610 device tree
On Mon, May 19, 2008 at 01:20:32PM -0500, Timur Tabi wrote: > Timur Tabi wrote: > > The CS4270 is using the second I2C bus, not the first, on the Freescale > > MPC8610 HPCD, so its node in the device tree belongs under '[EMAIL > > PROTECTED]' > > and not '[EMAIL PROTECTED]'. > > > > Signed-off-by: Timur Tabi <[EMAIL PROTECTED]> > > Please disregard this patch. It turns out that that both I2C controllers are > connected to the same bus, so it technically doesn't matter which node a > device > is a child of. However, tests show that sometimes one parent works, and > sometimes the other parent works. Hm... this should be controlled by the PIXIS' BRDCFG0's I2CSPAN and SERSEL bits: 0: I2C1 and I2C2 buses are separated. System (boot sequencer EEPROM) is on I2C1, all others are on I2C2. MPC8610 SPI functions cannot be used. 1: I2C1 and I2C2 are bridged. MPC8610 SPI functions may be used. All I2C devices may be accessed via I2C1 controller and/or I2C2 (I2C2 depends on SERSEL setting). -- Anton Vorontsov email: [EMAIL PROTECTED] irc://irc.freenode.net/bd2 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH v3 1/3] [POWERPC] Move to runtime allocated exception stacks
On Fri, 16 May 2008 14:04:54 -0500 (CDT) Kumar Gala <[EMAIL PROTECTED]> wrote: > For the additonal exception levels (critical, debug, machine check) on > 40x/book-e we were using "static" allocations of the stack in the > associated head.S. > > Move to a runtime allocation to make the code a bit easier to read as > we mimic how we handle IRQ stacks. Its also a bit easier to setup the > stack with a "dummy" thread_info in C code. For the peanut gallery, I've started testing this series on 44x and 40x. 44x seems to be in fair shape. It boots with all three applied and breakpoints and single step work in gdb. The only "issue" I found was a warning during compile that Kumar already knows about. 40x is in rougher shape. It boots with the first patch applied and userspace seems to function well enough. However whenever you try to run something in gdb it will hang the board completely. No panic, board doesn't ping anymore, just hung. I've by no means stress tested anything here, so for those of you that are adventurous feel free to pitch in and test them out on your boards ;). josh ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH 8/8] [POWERPC] 86xx: mpc8610_hpcd: add watchdog node
Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
---
arch/powerpc/boot/dts/mpc8610_hpcd.dts |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts
b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
index 08a780d..44e9287 100644
--- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts
+++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
@@ -188,6 +188,11 @@
fsl,has-rstcr;
};
+ [EMAIL PROTECTED] {
+ compatible = "fsl,mpc8610-wdt";
+ reg = <0xe4000 0x100>;
+ };
+
[EMAIL PROTECTED] {
compatible = "fsl,mpc8610-ssi";
cell-index = <0>;
--
1.5.5.1
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[PATCH 7/8] [POWERPC] fsl_soc: remove mpc83xx_wdt code
mpc83xx_wdt is the OF driver now, so we don't need fsl_soc constructor.
Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
---
arch/powerpc/sysdev/fsl_soc.c | 46 -
1 files changed, 0 insertions(+), 46 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c
index a5ceeef..32a3ac8 100644
--- a/arch/powerpc/sysdev/fsl_soc.c
+++ b/arch/powerpc/sysdev/fsl_soc.c
@@ -545,52 +545,6 @@ err:
arch_initcall(fsl_i2c_of_init);
#endif
-#ifdef CONFIG_PPC_83xx
-static int __init mpc83xx_wdt_init(void)
-{
- struct resource r;
- struct device_node *np;
- struct platform_device *dev;
- u32 freq = fsl_get_sys_freq();
- int ret;
-
- np = of_find_compatible_node(NULL, "watchdog", "mpc83xx_wdt");
-
- if (!np) {
- ret = -ENODEV;
- goto nodev;
- }
-
- memset(&r, 0, sizeof(r));
-
- ret = of_address_to_resource(np, 0, &r);
- if (ret)
- goto err;
-
- dev = platform_device_register_simple("mpc83xx_wdt", 0, &r, 1);
- if (IS_ERR(dev)) {
- ret = PTR_ERR(dev);
- goto err;
- }
-
- ret = platform_device_add_data(dev, &freq, sizeof(freq));
- if (ret)
- goto unreg;
-
- of_node_put(np);
- return 0;
-
-unreg:
- platform_device_unregister(dev);
-err:
- of_node_put(np);
-nodev:
- return ret;
-}
-
-arch_initcall(mpc83xx_wdt_init);
-#endif
-
static enum fsl_usb2_phy_modes determine_usb_phy(const char *phy_type)
{
if (!phy_type)
--
1.5.5.1
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[PATCH 6/8] [WATCHDOG] mpc8xxx_wdt: add support for MPC8xx watchdogs
The mpc8xxx_wdt driver is using two registers: SWSRR to push magic
numbers, and SWCRR to control the watchdog. Both registers are available
on the MPC8xx, and seem to have the same offsets and semantics as in
MPC83xx/MPC86xx watchdogs. The only difference is prescale value. So this
driver simply works on the MPC8xx CPUs.
One quirk is needed for the MPC8xx, though. It has small prescale value
and slow CPU, so the watchdog resets board prior to the driver has time
to load. To solve this we should split initialization in two steps: start
ping the watchdog early, and register the watchdog userspace interface
later.
MPC823 seem to be the first CPU in MPC8xx line, so we use fsl,mpc823-wdt
compatible matching.
Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
Tested-by: Jochen Friedrich <[EMAIL PROTECTED]>
---
drivers/watchdog/Kconfig |3 +-
drivers/watchdog/mpc8xxx_wdt.c | 44 ++--
2 files changed, 35 insertions(+), 12 deletions(-)
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 008eaa6..f9e617b 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -684,10 +684,11 @@ config 8xx_WDT
config 8xxx_WDT
tristate "MPC8xxx Platform Watchdog Timer"
- depends on PPC_83xx || PPC_86xx
+ depends on PPC_8xx || PPC_83xx || PPC_86xx
help
This driver is for a SoC level watchdog that exists on some
Freescale PowerPC processors. So far this driver supports:
+ - MPC8xx watchdogs
- MPC83xx watchdogs
- MPC86xx watchdogs
diff --git a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c
index 2f0681f..0f7e165 100644
--- a/drivers/watchdog/mpc8xxx_wdt.c
+++ b/drivers/watchdog/mpc8xxx_wdt.c
@@ -1,5 +1,5 @@
/*
- * mpc8xxx_wdt.c - MPC83xx/MPC86xx watchdog userspace interface
+ * mpc8xxx_wdt.c - MPC8xx/MPC83xx/MPC86xx watchdog userspace interface
*
* Authors: Dave Updegraff <[EMAIL PROTECTED]>
* Kumar Gala <[EMAIL PROTECTED]>
@@ -207,13 +207,6 @@ static int __devinit mpc8xxx_wdt_probe(struct of_device
*ofdev,
goto err_unmap;
}
- ret = misc_register(&mpc8xxx_wdt_miscdev);
- if (ret) {
- pr_err("cannot register miscdev on minor=%d (err=%d)\n",
- WATCHDOG_MINOR, ret);
- goto err_unmap;
- }
-
/* Calculate the timeout in seconds */
if (prescale)
timeout_sec = (timeout * wdt_type->prescaler) / freq;
@@ -234,6 +227,7 @@ static int __devinit mpc8xxx_wdt_probe(struct of_device
*ofdev,
return 0;
err_unmap:
iounmap(wd_base);
+ wd_base = NULL;
return ret;
}
@@ -261,6 +255,12 @@ static const struct of_device_id mpc8xxx_wdt_match[] = {
.hw_enabled = true,
},
},
+ {
+ .compatible = "fsl,mpc823-wdt",
+ .data = &(struct mpc8xxx_wdt_type) {
+ .prescaler = 0x800,
+ },
+ },
{},
};
MODULE_DEVICE_TABLE(of, mpc8xxx_wdt_match);
@@ -275,20 +275,42 @@ static struct of_platform_driver mpc8xxx_wdt_driver = {
},
};
+/*
+ * We do wdt initialization in two steps: arch_initcall probes the wdt
+ * very early to start pinging the watchdog (misc devices are not yet
+ * available), and later module_init() just registers the misc device.
+ */
+static int __init mpc8xxx_wdt_init_late(void)
+{
+ int ret;
+
+ if (!wd_base)
+ return -ENODEV;
+
+ ret = misc_register(&mpc8xxx_wdt_miscdev);
+ if (ret) {
+ pr_err("cannot register miscdev on minor=%d (err=%d)\n",
+ WATCHDOG_MINOR, ret);
+ return ret;
+ }
+ return 0;
+}
+module_init(mpc8xxx_wdt_init_late);
+
static int __init mpc8xxx_wdt_init(void)
{
return of_register_platform_driver(&mpc8xxx_wdt_driver);
}
+arch_initcall(mpc8xxx_wdt_init);
static void __exit mpc8xxx_wdt_exit(void)
{
of_unregister_platform_driver(&mpc8xxx_wdt_driver);
}
-
-subsys_initcall(mpc8xxx_wdt_init);
module_exit(mpc8xxx_wdt_exit);
MODULE_AUTHOR("Dave Updegraff, Kumar Gala");
-MODULE_DESCRIPTION("Driver for watchdog timer in MPC83xx/MPC86xx uProcessors");
+MODULE_DESCRIPTION("Driver for watchdog timer in MPC8xx/MPC83xx/MPC86xx "
+ "uProcessors");
MODULE_LICENSE("GPL");
MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
--
1.5.5.1
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[PATCH 5/8] [WATCHDOG] mpc8xxx_wdt: various renames, mostly s/mpc83xx/mpc8xxx/g
mpc83xx_wdt.c renamed to mpc8xxx_wdt.c, now we can do various renames
in the file itself.
Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
---
drivers/watchdog/mpc8xxx_wdt.c | 104
1 files changed, 52 insertions(+), 52 deletions(-)
diff --git a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c
index 19e3082..2f0681f 100644
--- a/drivers/watchdog/mpc8xxx_wdt.c
+++ b/drivers/watchdog/mpc8xxx_wdt.c
@@ -1,5 +1,5 @@
/*
- * mpc83xx_wdt.c - MPC83xx/MPC86xx watchdog userspace interface
+ * mpc8xxx_wdt.c - MPC83xx/MPC86xx watchdog userspace interface
*
* Authors: Dave Updegraff <[EMAIL PROTECTED]>
* Kumar Gala <[EMAIL PROTECTED]>
@@ -29,7 +29,7 @@
#include
#include
-struct mpc83xx_wdt {
+struct mpc8xxx_wdt {
__be32 res0;
__be32 swcrr; /* System watchdog control register */
#define SWCRR_SWTC 0x /* Software Watchdog Time Count. */
@@ -42,12 +42,12 @@ struct mpc83xx_wdt {
u8 res2[0xF0];
};
-struct mpc83xx_wdt_type {
+struct mpc8xxx_wdt_type {
int prescaler;
bool hw_enabled;
};
-static struct mpc83xx_wdt __iomem *wd_base;
+static struct mpc8xxx_wdt __iomem *wd_base;
static u16 timeout = 0x;
module_param(timeout, ushort, 0);
@@ -74,7 +74,7 @@ static unsigned int timeout_sec;
static unsigned long wdt_is_open;
static DEFINE_SPINLOCK(wdt_spinlock);
-static void mpc83xx_wdt_keepalive(void)
+static void mpc8xxx_wdt_keepalive(void)
{
/* Ping the WDT */
spin_lock(&wdt_spinlock);
@@ -83,31 +83,31 @@ static void mpc83xx_wdt_keepalive(void)
spin_unlock(&wdt_spinlock);
}
-static void mpc83xx_wdt_timer_ping(unsigned long arg);
-static DEFINE_TIMER(wdt_timer, mpc83xx_wdt_timer_ping, 0, 0);
+static void mpc8xxx_wdt_timer_ping(unsigned long arg);
+static DEFINE_TIMER(wdt_timer, mpc8xxx_wdt_timer_ping, 0, 0);
-static void mpc83xx_wdt_timer_ping(unsigned long arg)
+static void mpc8xxx_wdt_timer_ping(unsigned long arg)
{
- mpc83xx_wdt_keepalive();
+ mpc8xxx_wdt_keepalive();
/* We're pinging it twice faster than needed, just to be sure. */
mod_timer(&wdt_timer, jiffies + HZ * timeout_sec / 2);
}
-static void mpc83xx_wdt_pr_warn(const char *msg)
+static void mpc8xxx_wdt_pr_warn(const char *msg)
{
- pr_crit("mpc83xx_wdt: %s, expect the %s soon!\n", msg,
+ pr_crit("mpc8xxx_wdt: %s, expect the %s soon!\n", msg,
reset ? "reset" : "machine check exception");
}
-static ssize_t mpc83xx_wdt_write(struct file *file, const char __user *buf,
+static ssize_t mpc8xxx_wdt_write(struct file *file, const char __user *buf,
size_t count, loff_t *ppos)
{
if (count)
- mpc83xx_wdt_keepalive();
+ mpc8xxx_wdt_keepalive();
return count;
}
-static int mpc83xx_wdt_open(struct inode *inode, struct file *file)
+static int mpc8xxx_wdt_open(struct inode *inode, struct file *file)
{
u32 tmp = SWCRR_SWEN;
if (test_and_set_bit(0, &wdt_is_open))
@@ -132,17 +132,17 @@ static int mpc83xx_wdt_open(struct inode *inode, struct
file *file)
return nonseekable_open(inode, file);
}
-static int mpc83xx_wdt_release(struct inode *inode, struct file *file)
+static int mpc8xxx_wdt_release(struct inode *inode, struct file *file)
{
if (!nowayout)
- mpc83xx_wdt_timer_ping(0);
+ mpc8xxx_wdt_timer_ping(0);
else
- mpc83xx_wdt_pr_warn("watchdog closed");
+ mpc8xxx_wdt_pr_warn("watchdog closed");
clear_bit(0, &wdt_is_open);
return 0;
}
-static int mpc83xx_wdt_ioctl(struct inode *inode, struct file *file,
+static int mpc8xxx_wdt_ioctl(struct inode *inode, struct file *file,
unsigned int cmd, unsigned long arg)
{
void __user *argp = (void __user *)arg;
@@ -150,7 +150,7 @@ static int mpc83xx_wdt_ioctl(struct inode *inode, struct
file *file,
static struct watchdog_info ident = {
.options = WDIOF_KEEPALIVEPING,
.firmware_version = 1,
- .identity = "MPC83xx",
+ .identity = "MPC8xxx",
};
switch (cmd) {
@@ -160,7 +160,7 @@ static int mpc83xx_wdt_ioctl(struct inode *inode, struct
file *file,
case WDIOC_GETBOOTSTATUS:
return put_user(0, p);
case WDIOC_KEEPALIVE:
- mpc83xx_wdt_keepalive();
+ mpc8xxx_wdt_keepalive();
return 0;
case WDIOC_GETTIMEOUT:
return put_user(timeout_sec, p);
@@ -169,27 +169,27 @@ static int mpc83xx_wdt_ioctl(struct inode *inode, struct
file *file,
}
}
-static const struct file_operations mpc83xx_wdt_fops = {
+static const struct file_operations mpc8xxx_wdt_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
- .write = mpc83xx_wdt_write,
- .ioctl =
[PATCH 4/8] [WATCHDOG] mpc83xx_wdt: rename to mpc8xxx_wdt
Rename the driver because now we support some MPC86xx processors.
There are no changes to the mpc83xx_wdt.c file, yet. When possible, we do
file renames and changes separately (because Linus once asked so, because
it helps git to track the renamed files).
Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
---
drivers/watchdog/Kconfig | 11 ++-
drivers/watchdog/Makefile |2 +-
drivers/watchdog/mpc83xx_wdt.c | 294
drivers/watchdog/mpc8xxx_wdt.c | 294
4 files changed, 304 insertions(+), 297 deletions(-)
delete mode 100644 drivers/watchdog/mpc83xx_wdt.c
create mode 100644 drivers/watchdog/mpc8xxx_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 2929055..008eaa6 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -682,9 +682,16 @@ config 8xx_WDT
tristate "MPC8xx Watchdog Timer"
depends on 8xx
-config 83xx_WDT
- tristate "MPC83xx/MPC86xx Watchdog Timer"
+config 8xxx_WDT
+ tristate "MPC8xxx Platform Watchdog Timer"
depends on PPC_83xx || PPC_86xx
+ help
+ This driver is for a SoC level watchdog that exists on some
+ Freescale PowerPC processors. So far this driver supports:
+ - MPC83xx watchdogs
+ - MPC86xx watchdogs
+
+ For BookE processors (MPC85xx) use the BOOKE_WDT driver instead.
config MV64X60_WDT
tristate "MV64X60 (Marvell Discovery) Watchdog Timer"
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index f3fb170..d5782f9 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -102,7 +102,7 @@ obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
# POWERPC Architecture
obj-$(CONFIG_8xx_WDT) += mpc8xx_wdt.o
obj-$(CONFIG_MPC5200_WDT) += mpc5200_wdt.o
-obj-$(CONFIG_83xx_WDT) += mpc83xx_wdt.o
+obj-$(CONFIG_8xxx_WDT) += mpc8xxx_wdt.o
obj-$(CONFIG_MV64X60_WDT) += mv64x60_wdt.o
obj-$(CONFIG_BOOKE_WDT) += booke_wdt.o
diff --git a/drivers/watchdog/mpc83xx_wdt.c b/drivers/watchdog/mpc83xx_wdt.c
deleted file mode 100644
index 19e3082..000
--- a/drivers/watchdog/mpc83xx_wdt.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- * mpc83xx_wdt.c - MPC83xx/MPC86xx watchdog userspace interface
- *
- * Authors: Dave Updegraff <[EMAIL PROTECTED]>
- * Kumar Gala <[EMAIL PROTECTED]>
- * Attribution: from 83xx_wst: Florian Schirmer <[EMAIL PROTECTED]>
- * ..and from sc520_wdt
- * Copyright (c) 2008 MontaVista Software, Inc.
- * Anton Vorontsov <[EMAIL PROTECTED]>
- *
- * Note: it appears that you can only actually ENABLE or DISABLE the thing
- * once after POR. Once enabled, you cannot disable, and vice versa.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-struct mpc83xx_wdt {
- __be32 res0;
- __be32 swcrr; /* System watchdog control register */
-#define SWCRR_SWTC 0x /* Software Watchdog Time Count. */
-#define SWCRR_SWEN 0x0004 /* Watchdog Enable bit. */
-#define SWCRR_SWRI 0x0002 /* Software Watchdog Reset/Interrupt Select
bit.*/
-#define SWCRR_SWPR 0x0001 /* Software Watchdog Counter Prescale bit. */
- __be32 swcnr; /* System watchdog count register */
- u8 res1[2];
- __be16 swsrr; /* System watchdog service register */
- u8 res2[0xF0];
-};
-
-struct mpc83xx_wdt_type {
- int prescaler;
- bool hw_enabled;
-};
-
-static struct mpc83xx_wdt __iomem *wd_base;
-
-static u16 timeout = 0x;
-module_param(timeout, ushort, 0);
-MODULE_PARM_DESC(timeout, "Watchdog timeout in ticks. "
-"(0swsrr, 0x556c);
- out_be16(&wd_base->swsrr, 0xaa39);
- spin_unlock(&wdt_spinlock);
-}
-
-static void mpc83xx_wdt_timer_ping(unsigned long arg);
-static DEFINE_TIMER(wdt_timer, mpc83xx_wdt_timer_ping, 0, 0);
-
-static void mpc83xx_wdt_timer_ping(unsigned long arg)
-{
- mpc83xx_wdt_keepalive();
- /* We're pinging it twice faster than needed, just to be sure. */
- mod_timer(&wdt_timer, jiffies + HZ * timeout_sec / 2);
-}
-
-static void mpc83xx_wdt_pr_warn(const char *msg)
-{
- pr_crit("mpc83xx_wdt: %s, expect the %s soon!\n", msg,
- reset ? "reset" : "machine check exception");
-}
-
-static ssize_t mpc83xx_wdt_write(struct file *file, const char __user *buf,
-size_t count, loff_t *ppos)
-{
- if (count)
- mpc83xx_wdt_keepalive();
- return count;
-}
-
-static int mpc83xx_wdt_open(struct inode *inode, struct file *file)
-{
- u32 tmp = SWCRR_SWEN;
- if (test_and_set_bit(0, &wdt_is_op
[PATCH 3/8] [WATCHDOG] mpc83xx_wdt: add support for MPC86xx CPUs
On MPC86xx the watchdog could be enabled only at power-on-reset, and
could not be disabled afterwards. We must ping the watchdog from the
kernel until the userspace handles it.
MPC83xx CPUs are only differ in a way that watchdog could be disabled
once, but after it was enabled via software it becomes just the same
as MPC86xx.
Thus, to support MPC86xx I added the kernel timer which pings the
watchdog until the userspace opens it.
Since we implemented the timer, now we're able to implement proper
handling for the CONFIG_WATCHDOG_NOWAYOUT case, for MPC83xx and MPC86xx.
Also move the probe code into subsys_initcall, because we want start
pinging the watchdog ASAP, and misc devices are available in
subsys_initcall.
Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
---
drivers/watchdog/Kconfig |4 +-
drivers/watchdog/mpc83xx_wdt.c | 80
2 files changed, 74 insertions(+), 10 deletions(-)
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 254d115..2929055 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -683,8 +683,8 @@ config 8xx_WDT
depends on 8xx
config 83xx_WDT
- tristate "MPC83xx Watchdog Timer"
- depends on PPC_83xx
+ tristate "MPC83xx/MPC86xx Watchdog Timer"
+ depends on PPC_83xx || PPC_86xx
config MV64X60_WDT
tristate "MV64X60 (Marvell Discovery) Watchdog Timer"
diff --git a/drivers/watchdog/mpc83xx_wdt.c b/drivers/watchdog/mpc83xx_wdt.c
index 127d85e..19e3082 100644
--- a/drivers/watchdog/mpc83xx_wdt.c
+++ b/drivers/watchdog/mpc83xx_wdt.c
@@ -1,10 +1,12 @@
/*
- * mpc83xx_wdt.c - MPC83xx watchdog userspace interface
+ * mpc83xx_wdt.c - MPC83xx/MPC86xx watchdog userspace interface
*
* Authors: Dave Updegraff <[EMAIL PROTECTED]>
* Kumar Gala <[EMAIL PROTECTED]>
* Attribution: from 83xx_wst: Florian Schirmer <[EMAIL PROTECTED]>
* ..and from sc520_wdt
+ * Copyright (c) 2008 MontaVista Software, Inc.
+ * Anton Vorontsov <[EMAIL PROTECTED]>
*
* Note: it appears that you can only actually ENABLE or DISABLE the thing
* once after POR. Once enabled, you cannot disable, and vice versa.
@@ -18,6 +20,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -39,6 +42,11 @@ struct mpc83xx_wdt {
u8 res2[0xF0];
};
+struct mpc83xx_wdt_type {
+ int prescaler;
+ bool hw_enabled;
+};
+
static struct mpc83xx_wdt __iomem *wd_base;
static u16 timeout = 0x;
@@ -51,6 +59,11 @@ module_param(reset, bool, 0);
MODULE_PARM_DESC(reset, "Watchdog Interrupt/Reset Mode. "
"0 = interrupt, 1 = reset");
+static int nowayout = WATCHDOG_NOWAYOUT;
+module_param(nowayout, int, 0);
+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
+"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
+
/*
* We always prescale, but if someone really doesn't want to they can set this
* to 0
@@ -70,6 +83,22 @@ static void mpc83xx_wdt_keepalive(void)
spin_unlock(&wdt_spinlock);
}
+static void mpc83xx_wdt_timer_ping(unsigned long arg);
+static DEFINE_TIMER(wdt_timer, mpc83xx_wdt_timer_ping, 0, 0);
+
+static void mpc83xx_wdt_timer_ping(unsigned long arg)
+{
+ mpc83xx_wdt_keepalive();
+ /* We're pinging it twice faster than needed, just to be sure. */
+ mod_timer(&wdt_timer, jiffies + HZ * timeout_sec / 2);
+}
+
+static void mpc83xx_wdt_pr_warn(const char *msg)
+{
+ pr_crit("mpc83xx_wdt: %s, expect the %s soon!\n", msg,
+ reset ? "reset" : "machine check exception");
+}
+
static ssize_t mpc83xx_wdt_write(struct file *file, const char __user *buf,
size_t count, loff_t *ppos)
{
@@ -85,7 +114,8 @@ static int mpc83xx_wdt_open(struct inode *inode, struct file
*file)
return -EBUSY;
/* Once we start the watchdog we can't stop it */
- __module_get(THIS_MODULE);
+ if (nowayout)
+ __module_get(THIS_MODULE);
/* Good, fire up the show */
if (prescale)
@@ -97,13 +127,17 @@ static int mpc83xx_wdt_open(struct inode *inode, struct
file *file)
out_be32(&wd_base->swcrr, tmp);
+ del_timer_sync(&wdt_timer);
+
return nonseekable_open(inode, file);
}
static int mpc83xx_wdt_release(struct inode *inode, struct file *file)
{
- printk(KERN_CRIT "Unexpected close, not stopping watchdog!\n");
- mpc83xx_wdt_keepalive();
+ if (!nowayout)
+ mpc83xx_wdt_timer_ping(0);
+ else
+ mpc83xx_wdt_pr_warn("watchdog closed");
clear_bit(0, &wdt_is_open);
return 0;
}
@@ -154,15 +188,25 @@ static int __devinit mpc83xx_wdt_probe(struct of_device
*ofdev,
const struct of_device_id *match)
{
int ret;
+ struct device_node *np = ofdev->node;
+ struct mpc83xx_w
[PATCH 2/8] [WATCHDOG] mpc83xx_wdt: convert to the OF platform driver
This patch simply converts mpc83xx_wdt to the OF platform driver so we
can directly work with the device tree without passing various stuff
through platform data.
Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
Acked-by: Stephen Rothwell <[EMAIL PROTECTED]>
---
drivers/watchdog/mpc83xx_wdt.c | 62 +++
1 files changed, 30 insertions(+), 32 deletions(-)
diff --git a/drivers/watchdog/mpc83xx_wdt.c b/drivers/watchdog/mpc83xx_wdt.c
index 6905712..127d85e 100644
--- a/drivers/watchdog/mpc83xx_wdt.c
+++ b/drivers/watchdog/mpc83xx_wdt.c
@@ -19,11 +19,12 @@
#include
#include
#include
-#include
+#include
#include
#include
#include
#include
+#include
struct mpc83xx_wdt {
__be32 res0;
@@ -149,53 +150,42 @@ static struct miscdevice mpc83xx_wdt_miscdev = {
.fops = &mpc83xx_wdt_fops,
};
-static int __devinit mpc83xx_wdt_probe(struct platform_device *dev)
+static int __devinit mpc83xx_wdt_probe(struct of_device *ofdev,
+ const struct of_device_id *match)
{
- struct resource *r;
int ret;
- unsigned int *freq = dev->dev.platform_data;
+ u32 freq = fsl_get_sys_freq();
- /* get a pointer to the register memory */
- r = platform_get_resource(dev, IORESOURCE_MEM, 0);
+ if (!freq || freq == -1)
+ return -EINVAL;
- if (!r) {
- ret = -ENODEV;
- goto err_out;
- }
-
- wd_base = ioremap(r->start, sizeof(struct mpc83xx_wdt));
-
- if (wd_base == NULL) {
- ret = -ENOMEM;
- goto err_out;
- }
+ wd_base = of_iomap(ofdev->node, 0);
+ if (!wd_base)
+ return -ENOMEM;
ret = misc_register(&mpc83xx_wdt_miscdev);
if (ret) {
- printk(KERN_ERR "cannot register miscdev on minor=%d "
- "(err=%d)\n",
- WATCHDOG_MINOR, ret);
+ pr_err("cannot register miscdev on minor=%d (err=%d)\n",
+ WATCHDOG_MINOR, ret);
goto err_unmap;
}
/* Calculate the timeout in seconds */
if (prescale)
- timeout_sec = (timeout * 0x1) / (*freq);
+ timeout_sec = (timeout * 0x1) / freq;
else
- timeout_sec = timeout / (*freq);
+ timeout_sec = timeout / freq;
- printk(KERN_INFO "WDT driver for MPC83xx initialized. "
- "mode:%s timeout=%d (%d seconds)\n",
- reset ? "reset":"interrupt", timeout, timeout_sec);
+ pr_info("WDT driver for MPC83xx initialized. mode:%s timeout=%d "
+ "(%d seconds)\n", reset ? "reset" : "interrupt", timeout,
+ timeout_sec);
return 0;
-
err_unmap:
iounmap(wd_base);
-err_out:
return ret;
}
-static int __devexit mpc83xx_wdt_remove(struct platform_device *dev)
+static int __devexit mpc83xx_wdt_remove(struct of_device *ofdev)
{
misc_deregister(&mpc83xx_wdt_miscdev);
iounmap(wd_base);
@@ -203,7 +193,16 @@ static int __devexit mpc83xx_wdt_remove(struct
platform_device *dev)
return 0;
}
-static struct platform_driver mpc83xx_wdt_driver = {
+static const struct of_device_id mpc83xx_wdt_match[] = {
+ {
+ .compatible = "mpc83xx_wdt",
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mpc83xx_wdt_match);
+
+static struct of_platform_driver mpc83xx_wdt_driver = {
+ .match_table= mpc83xx_wdt_match,
.probe = mpc83xx_wdt_probe,
.remove = __devexit_p(mpc83xx_wdt_remove),
.driver = {
@@ -214,12 +213,12 @@ static struct platform_driver mpc83xx_wdt_driver = {
static int __init mpc83xx_wdt_init(void)
{
- return platform_driver_register(&mpc83xx_wdt_driver);
+ return of_register_platform_driver(&mpc83xx_wdt_driver);
}
static void __exit mpc83xx_wdt_exit(void)
{
- platform_driver_unregister(&mpc83xx_wdt_driver);
+ of_unregister_platform_driver(&mpc83xx_wdt_driver);
}
module_init(mpc83xx_wdt_init);
@@ -229,4 +228,3 @@ MODULE_AUTHOR("Dave Updegraff, Kumar Gala");
MODULE_DESCRIPTION("Driver for watchdog timer in MPC83xx uProcessor");
MODULE_LICENSE("GPL");
MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
-MODULE_ALIAS("platform:mpc83xx_wdt");
--
1.5.5.1
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[PATCH 1/8] [WATCHDOG] mpc83xx_wdt: fix checkpatch issues
Quite tired of these warnings ;-), checkpatch spitting them when
seeing the rename patch.
WARNING: Use #include instead of
#25: FILE: watchdog/mpc83xx_wdt.c:25:
+#include
WARNING: Use #include instead of
#26: FILE: watchdog/mpc83xx_wdt.c:26:
+#include
WARNING: line over 80 characters
#45: FILE: watchdog/mpc83xx_wdt.c:45:
+MODULE_PARM_DESC(timeout, "Watchdog timeout in ticks. (0start, sizeof (struct mpc83xx_wdt));
total: 0 errors, 5 warnings, 230 lines checked
Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
---
drivers/watchdog/mpc83xx_wdt.c | 12 +++-
1 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/watchdog/mpc83xx_wdt.c b/drivers/watchdog/mpc83xx_wdt.c
index b16c5cd..6905712 100644
--- a/drivers/watchdog/mpc83xx_wdt.c
+++ b/drivers/watchdog/mpc83xx_wdt.c
@@ -22,8 +22,8 @@
#include
#include
#include
-#include
-#include
+#include
+#include
struct mpc83xx_wdt {
__be32 res0;
@@ -42,11 +42,13 @@ static struct mpc83xx_wdt __iomem *wd_base;
static u16 timeout = 0x;
module_param(timeout, ushort, 0);
-MODULE_PARM_DESC(timeout, "Watchdog timeout in ticks. (0start, sizeof (struct mpc83xx_wdt));
+ wd_base = ioremap(r->start, sizeof(struct mpc83xx_wdt));
if (wd_base == NULL) {
ret = -ENOMEM;
--
1.5.5.1
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[PATCH 0/8 v4] mpc83xx_wdt rework, support for mpc8610 and mpc8xx
Hi all,
Much thanks for the review, testing and acks!
New version follows, now tested on MPC8xx.
Kumar, if you're okay with the patches, could you please Ack the
[WATCHDOG] ones?
Thanks,
---
Changes since v3:
- MPC8xx quirk folded into MPC8xx support patch.
- Tested-by: Jochen Friedrich <[EMAIL PROTECTED]>
- "[WATCHDOG] mpc83xx_wdt: convert to the OF platform driver"
Acked-by: Stephen Rothwell <[EMAIL PROTECTED]>
Changes since v2:
- New patch to fix current driver's checkpatch issues;
- New patch supporting MPC8xx watchdogs (ok to drop until tested);
- Removed MODULE_ALIAS("platform:mpc83xx_wdt"), since this driver is no
longer on the platform bus;
- When renaming the driver also mention what kind of CPUs we support.
Also give a pointer for BookE watchdog driver. Though BookE users will
not see the MPC8xxx driver at all, because we're explicitly listing the
CPU families in "depends on". But this tip might be useful for
developers.
- Scott Wood noticed that we don't need device_type anymore. I thought
that OpenFirmware defines this type, but google didn't prove that.
So I just removed the device_type.
Changes since v1:
- Scott Wood asked for mpc83xx_wdt on multiplatform kernels. Done via
OF platform driver;
- Kumar Gala asked for mpc83xx_wdt -> mpc8xxx_wdt rename. Done in two
steps;
- Segher Boessenkool noticed a negligence in the wdt device tree node.
Fixed by removing mpc83xx_wdt compatible entry.
--
Anton Vorontsov
email: [EMAIL PROTECTED]
irc://irc.freenode.net/bd2
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Re: [PATCH] CS4270 node is misplaced in the MPC8610 device tree
Timur Tabi wrote: > The CS4270 is using the second I2C bus, not the first, on the Freescale > MPC8610 HPCD, so its node in the device tree belongs under '[EMAIL PROTECTED]' > and not '[EMAIL PROTECTED]'. > > Signed-off-by: Timur Tabi <[EMAIL PROTECTED]> Please disregard this patch. It turns out that that both I2C controllers are connected to the same bus, so it technically doesn't matter which node a device is a child of. However, tests show that sometimes one parent works, and sometimes the other parent works. -- Timur Tabi Linux kernel developer at Freescale ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 1/5 v2] powerpc: DTS file for the C2K
> On Mon, 2008-05-19 at 10:53 +1000, David Gibson wrote:
> On Fri, May 16, 2008 at 12:28:48PM -0700, Remi Machet wrote:
> > Support for the C2K cPCI Single Board Computer from GEFanuc
> > (PowerPC MPC7448 with a Marvell MV64460 chipset)
> > All features of the board are not supported yet, but the board
> > boots, flash works, all Ethernet ports are working and PCI
> > devices are all found (USB and SATA on PCI1 do not work yet).
> >
> > Part 1 of 5: DTS file describing the board peripherals. As far as I know
> > all peripherals except the FPGA are listed in there (I did not included
> > the FPGA because a lot of work is needed there).
>
> Looking pretty good, but a hanful more comments below.
>
> [snip]
> > + mdio {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "marvell,mv64360-mdio";
>
> Surely this needs a "reg" property, otherwise how to you access the
> mdio bus?
I am afraid this is another situation where the driver is not fully
using the OF description ... the PHY registers address is hard-coded in
drivers/net/mv643xx_eth.c. In any case I will add the reg property, and
later on can try to modify the driver to make use of it.
> [snip]
> > + /* Devices attached to the device controller */
> > + devicebus {
> > + compatible = "marvell,mv64306-devctrl";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
>
> This looks like it needs either a "reg" or a "ranges" property. If
> the address space of this "devicebus" is the same as the parent bus
> you need an empty "ranges" property. *No* ranges property means the
> subordinate devices can't be directly accessed at all from the parent
> bus.
This is a static bus with chip selects, I will look at other dts files
to properly implement it (with the chipselect and range properties).
>
> > + nor_flash {
>
> This needs a unit address, "[EMAIL PROTECTED]".
>
[ snip ]
> > + chosen {
> > + bootargs = "ip=off root=/dev/mtdblock3 rootfstype=jffs2";
>
> You don't usually want to encode a default bootargs into the dts file;
> kernel command line arguments should usually be left to the user.
Ok I will remove that.
Thanks for all the comments, I will re-submit a patch as soon as I have
fixed all that.
Remi
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[PATCH 7/7] [POWERPC] qe_lib: switch to the cpm_muram implementation
This is very trivial patch. We're transitioning to the cpm_muram_*
calls. That's it.
Less trivial changes:
- BD_SC_* defines were defined in the cpm.h and qe.h, so to avoid redefines
we remove BD_SC from the qe.h and use cpm.h along with cpm_muram_*
prototypes;
- qe_muram_dump was unused and thus removed;
- added some code to the cpm_common.c to support legacy QE bindings
(data-only node name).
- For convenience, define qe_* calls to cpm_*. So drivers need not to be
changed.
Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
---
arch/powerpc/sysdev/Makefile |1 +
arch/powerpc/sysdev/cpm_common.c | 16 +-
arch/powerpc/sysdev/qe_lib/qe.c | 92 -
arch/powerpc/sysdev/qe_lib/ucc_fast.c |8 ++--
arch/powerpc/sysdev/qe_lib/ucc_slow.c | 18 +++---
include/asm-powerpc/cpm.h |1 +
include/asm-powerpc/qe.h | 36 +++--
7 files changed, 36 insertions(+), 136 deletions(-)
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index f55e661..620aca6 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -41,6 +41,7 @@ endif
ifeq ($(ARCH),powerpc)
obj-$(CONFIG_CPM) += cpm_common.o
obj-$(CONFIG_CPM2) += cpm2.o cpm2_pic.o
+obj-$(CONFIG_QUICC_ENGINE) += cpm_common.o
obj-$(CONFIG_PPC_DCR) += dcr.o
obj-$(CONFIG_8xx) += mpc8xx_pic.o cpm1.o
obj-$(CONFIG_UCODE_PATCH) += micropatch.o
diff --git a/arch/powerpc/sysdev/cpm_common.c b/arch/powerpc/sysdev/cpm_common.c
index cb7df2d..9b75d16 100644
--- a/arch/powerpc/sysdev/cpm_common.c
+++ b/arch/powerpc/sysdev/cpm_common.c
@@ -85,9 +85,13 @@ int __init cpm_muram_init(void)
np = of_find_compatible_node(NULL, NULL, "fsl,cpm-muram-data");
if (!np) {
- printk(KERN_ERR "Cannot find CPM muram data node");
- ret = -ENODEV;
- goto out;
+ /* try legacy bindings */
+ np = of_find_node_by_name(NULL, "data-only");
+ if (!np) {
+ printk(KERN_ERR "Cannot find CPM muram data node");
+ ret = -ENODEV;
+ goto out;
+ }
}
muram_pbase = of_translate_address(np, zero);
@@ -189,6 +193,12 @@ void __iomem *cpm_muram_addr(unsigned long offset)
}
EXPORT_SYMBOL(cpm_muram_addr);
+unsigned long cpm_muram_offset(void __iomem *addr)
+{
+ return addr - (void __iomem *)muram_vbase;
+}
+EXPORT_SYMBOL(cpm_muram_offset);
+
/**
* cpm_muram_dma - turn a muram virtual address into a DMA address
* @offset: virtual address from cpm_muram_addr() to convert
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
index cff550e..28e05df 100644
--- a/arch/powerpc/sysdev/qe_lib/qe.c
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -35,7 +35,6 @@
#include
static void qe_snums_init(void);
-static void qe_muram_init(void);
static int qe_sdma_init(void);
static DEFINE_SPINLOCK(qe_lock);
@@ -325,97 +324,6 @@ static int qe_sdma_init(void)
return 0;
}
-/*
- * muram_alloc / muram_free bits.
- */
-static DEFINE_SPINLOCK(qe_muram_lock);
-
-/* 16 blocks should be enough to satisfy all requests
- * until the memory subsystem goes up... */
-static rh_block_t qe_boot_muram_rh_block[16];
-static rh_info_t qe_muram_info;
-
-static void qe_muram_init(void)
-{
- struct device_node *np;
- const u32 *address;
- u64 size;
- unsigned int flags;
-
- /* initialize the info header */
- rh_init(&qe_muram_info, 1,
- sizeof(qe_boot_muram_rh_block) /
- sizeof(qe_boot_muram_rh_block[0]), qe_boot_muram_rh_block);
-
- /* Attach the usable muram area */
- /* XXX: This is a subset of the available muram. It
-* varies with the processor and the microcode patches activated.
-*/
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-muram-data");
- if (!np) {
- np = of_find_node_by_name(NULL, "data-only");
- if (!np) {
- WARN_ON(1);
- return;
- }
- }
-
- address = of_get_address(np, 0, &size, &flags);
- WARN_ON(!address);
-
- of_node_put(np);
- if (address)
- rh_attach_region(&qe_muram_info, *address, (int)size);
-}
-
-/* This function returns an index into the MURAM area.
- */
-unsigned long qe_muram_alloc(int size, int align)
-{
- unsigned long start;
- unsigned long flags;
-
- spin_lock_irqsave(&qe_muram_lock, flags);
- start = rh_alloc_align(&qe_muram_info, size, align, "QE");
- spin_unlock_irqrestore(&qe_muram_lock, flags);
-
- return start;
-}
-EXPORT_SYMBOL(qe_muram_alloc);
-
-int qe_muram_free(unsigned long offset)
-{
- int ret;
- unsigned long flags;
-
- spin_lock_irqsave(&qe_muram_lock, flags);
- ret = rh_f
[PATCH 6/7] [POWERPC] booting-without-of: add FHCI USB, FSL MCU, FSL UPM and GPIO LEDs bindings
This patch adds few bindings for the new drivers to be submitted through
appropriate maintainers.
Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
---
Documentation/powerpc/booting-without-of.txt | 125 ++
1 files changed, 125 insertions(+), 0 deletions(-)
diff --git a/Documentation/powerpc/booting-without-of.txt
b/Documentation/powerpc/booting-without-of.txt
index c1044ee..4e15c13 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -61,6 +61,10 @@ Table of Contents
r) Freescale Display Interface Unit
s) Freescale on board FPGA
t) Freescale General-purpose Timers Module
+ u) Freescale QUICC Engine USB Controller
+ v) LEDs on GPIOs
+ w) Freescale MCU with MPC8349E-mITX compatible firmware
+ x) Freescale Localbus UPM programmed to work with NAND flash
VII - Marvell Discovery mv64[345]6x System Controller chips
1) The /system-controller node
@@ -2932,6 +2936,127 @@ platforms are moved over to use the
flattened-device-tree model.
clock-frequency = <0>;
};
+u) Freescale QUICC Engine USB Controller
+
+Required properties:
+ - compatible : should be "fsl,-qe-usb", "fsl,mpc8323-qe-usb";
+ - reg : the first two cells should contain gtm registers location and
+length, the next two two cells should contain PRAM location and
+length.
+ - interrupts : should contain USB interrupt.
+ - interrupt-parent : interrupt source phandle.
+ - fsl,fullspeed-clock : specifies the full speed USB clock source in
+"clk" or "brg" format.
+ - fsl,lowspeed-clock : specifies the low speed USB clock source in
+"clk" or "brg" format.
+ - fsl,usb-mode : should be "host".
+ - linux,hub-power-budget : optional, USB power budget for the root hub
+in mA.
+ - gpios : should specify GPIOs in this order: USBOE, USBTP, USBTN, USBRP,
+USBRN, SPEED (optional), and POWER (optional).
+
+Example:
+
+ [EMAIL PROTECTED] {
+ compatible = "fsl,mpc8360-qe-usb", "fsl,mpc8323-qe-usb";
+ reg = <0x6c0 0x40 0x8b00 0x100>;
+ interrupts = <11>;
+ interrupt-parent = <&qeic>;
+ fsl,fullspeed-clock = "clk21";
+ fsl,usb-mode = "host";
+ gpios = <&qe_pio_b 2 0 /* USBOE */
+&qe_pio_b 3 0 /* USBTP */
+&qe_pio_b 8 0 /* USBTN */
+&qe_pio_b 9 0 /* USBRP */
+&qe_pio_b 11 0 /* USBRN */
+&qe_pio_e 20 0 /* SPEED */
+&qe_pio_e 21 0 /* POWER */>;
+ };
+
+v) LEDs on GPIOs
+
+Required properties:
+ - compatible : should be "linux,gpio-led".
+ - linux,name : LED name.
+ - linux,active-low : property should be present if LED wired as
+active-low.
+ - linux,default-trigger : Linux default trigger for this LED.
+ - linux,brightness : default brightness.
+ - gpios : should specify LED GPIO.
+
+Example:
+
+ [EMAIL PROTECTED] {
+ compatible = "linux,gpio-led";
+ linux,name = "pwr";
+ linux,brightness = <1>;
+ linux,active-low;
+ gpios = <&mcu_pio 0>;
+ };
+
+ [EMAIL PROTECTED] {
+ compatible = "linux,gpio-led";
+ linux,name = "hdd";
+ linux,default-trigger = "ide-disk";
+ linux,active-low;
+ gpios = <&mcu_pio 1>;
+ };
+
+w) Freescale MCU with MPC8349E-mITX compatible firmware
+
+Required properties:
+ - compatible : "fsl,-", "fsl,mcu-mpc8349emitx";
+ - reg : should specify I2C address (0x0a).
+ - #address-cells : should be 0.
+ - #size-cells : should be 0.
+ - #gpio-cells : should be 2.
+ - gpio-controller : should be present;
+
+Example:
+
+ mcu_pio: [EMAIL PROTECTED] {
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #gpio-cells = <2>;
+ compatible = "fsl,mc9s08qg8-mpc8349emitx",
+"fsl,mcu-mpc8349emitx";
+ reg = <0x0a>;
+ gpio-controller;
+ };
+
+x) Freescale Localbus UPM programmed to work with NAND flash
+
+ Required properties:
+ - #address-cells : should be 0;
+ - #size-cells : should be 0;
+ - compatible : "fsl,upm-nand".
+ - reg : should specify localbus chip select and size used for the chip.
+ - fsl,upm-addr-offset : UPM pattern offset for the address latch.
+ - fsl,upm-cmd-offset : UPM pattern offset for the command latch.
+ - gpios : may specify optional GPIO connected to the Ready-Not-Busy pin.
+
+ Example:
+
+ [EMAIL PROTECTED],0 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+ compatible = "fsl,upm
[PATCH 5/7] [POWERPC] 83xx: new board support: MPC8360E-RDK
This is patch adds board file, device tree, and defconfig for the new
board, made by Freescale Semiconductor Inc. and Logic Product Development.
Currently supported:
1. UEC{1,2,7,4};
2. I2C;
3. SPI;
4. NS16550 serial;
5. PCI and miniPCI;
6. Intel NOR StrataFlash X16 64Mbit PC28F640P30T85;
7. Graphics controller, Fujitsu MB86277.
Not supported in this patch:
1. StMICRO NAND512W3A2BN6E, 512 Mbit (supported with FSL UPM NAND driver);
2. FHCI USB (supported with FHCI driver).
3. QE Serial UCCs (tested to not work with ucc_uart driver, reason
unknown, yet);
4. ADC AD7843 (tested to work, but support via device tree depends on
major SPI rework, GPIO API, etc);
Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
---
arch/powerpc/boot/dts/mpc836x_rdk.dts | 397
arch/powerpc/configs/83xx/mpc836x_rdk_defconfig | 1128 +++
arch/powerpc/platforms/83xx/Kconfig | 11 +
arch/powerpc/platforms/83xx/Makefile|1 +
arch/powerpc/platforms/83xx/mpc836x_rdk.c | 111 +++
5 files changed, 1648 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/mpc836x_rdk.dts
create mode 100644 arch/powerpc/configs/83xx/mpc836x_rdk_defconfig
create mode 100644 arch/powerpc/platforms/83xx/mpc836x_rdk.c
diff --git a/arch/powerpc/boot/dts/mpc836x_rdk.dts
b/arch/powerpc/boot/dts/mpc836x_rdk.dts
new file mode 100644
index 000..3402d26
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc836x_rdk.dts
@@ -0,0 +1,397 @@
+/*
+ * MPC8360E RDK Device Tree Source
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ * Copyright 2007-2008 MontaVista Software, Inc.
+ *
+ * Author: Anton Vorontsov <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8360rdk";
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ ethernet3 = &enet3;
+ pci0 = &pci0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,[EMAIL PROTECTED] {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <32768>;
+ i-cache-size = <32768>;
+ /* filled by u-boot */
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ /* filled by u-boot */
+ reg = <0 0>;
+ };
+
+ [EMAIL PROTECTED] {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,mpc8360-immr", "fsl,immr", "fsl,soc",
+"simple-bus";
+ ranges = <0 0xe000 0x20>;
+ reg = <0xe000 0x200>;
+ /* filled by u-boot */
+ bus-frequency = <0>;
+
+ [EMAIL PROTECTED] {
+ compatible = "mpc83xx_wdt";
+ reg = <0x200 0x100>;
+ };
+
+ [EMAIL PROTECTED] {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <14 8>;
+ interrupt-parent = <&ipic>;
+ dfsrr;
+ };
+
+ [EMAIL PROTECTED] {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <16 8>;
+ interrupt-parent = <&ipic>;
+ dfsrr;
+ };
+
+ serial0: [EMAIL PROTECTED] {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>;
+ interrupts = <9 8>;
+ interrupt-parent = <&ipic>;
+ /* filled by u-boot */
+ clock-frequency = <0>;
+ };
+
+
[PATCH 4/7] [POWERPC] QE: implement support for the GPIO LIB API
This is needed to access QE GPIOs via Linux GPIO API.
Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
Acked-By: Timur Tabi <[EMAIL PROTECTED]>
---
Documentation/powerpc/booting-without-of.txt | 27 +
arch/powerpc/sysdev/qe_lib/Kconfig |9 ++
arch/powerpc/sysdev/qe_lib/Makefile |1 +
arch/powerpc/sysdev/qe_lib/gpio.c| 146 ++
include/asm-powerpc/qe.h |3 +
5 files changed, 186 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/sysdev/qe_lib/gpio.c
diff --git a/Documentation/powerpc/booting-without-of.txt
b/Documentation/powerpc/booting-without-of.txt
index fc7a235..c1044ee 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -1738,6 +1738,33 @@ platforms are moved over to use the
flattened-device-tree model.
..
};
+ Note that "par_io" nodes are obsolete, and should not be used for
+ the new device trees. Instead, each Par I/O bank should be represented
+ via its own gpio-controller node:
+
+ Required properties:
+ - #gpio-cells : should be "2".
+ - compatible : should be "fsl,-qe-pario-bank",
+ "fsl,mpc8323-qe-pario-bank".
+ - reg : offset to the register set and its length.
+ - gpio-controller : node to identify gpio controllers.
+
+ Example:
+ qe_pio_a: [EMAIL PROTECTED] {
+ #gpio-cells = <2>;
+ compatible = "fsl,mpc8360-qe-pario-bank",
+"fsl,mpc8323-qe-pario-bank";
+ reg = <0x1400 0x18>;
+ gpio-controller;
+ };
+
+ qe_pio_e: [EMAIL PROTECTED] {
+ #gpio-cells = <2>;
+ compatible = "fsl,mpc8360-qe-pario-bank",
+"fsl,mpc8323-qe-pario-bank";
+ reg = <0x1460 0x18>;
+ gpio-controller;
+ };
vi) Pin configuration nodes
diff --git a/arch/powerpc/sysdev/qe_lib/Kconfig
b/arch/powerpc/sysdev/qe_lib/Kconfig
index 76ffbc4..4bb18f5 100644
--- a/arch/powerpc/sysdev/qe_lib/Kconfig
+++ b/arch/powerpc/sysdev/qe_lib/Kconfig
@@ -24,3 +24,12 @@ config QE_USB
bool
help
QE USB Host Controller support
+
+config QE_GPIO
+ bool "QE GPIO support"
+ depends on QUICC_ENGINE
+ select GENERIC_GPIO
+ select HAVE_GPIO_LIB
+ help
+ Say Y here if you're going to use hardware that connects to the
+ QE GPIOs.
diff --git a/arch/powerpc/sysdev/qe_lib/Makefile
b/arch/powerpc/sysdev/qe_lib/Makefile
index e9ff888..f1855c1 100644
--- a/arch/powerpc/sysdev/qe_lib/Makefile
+++ b/arch/powerpc/sysdev/qe_lib/Makefile
@@ -7,3 +7,4 @@ obj-$(CONFIG_UCC) += ucc.o
obj-$(CONFIG_UCC_SLOW) += ucc_slow.o
obj-$(CONFIG_UCC_FAST) += ucc_fast.o
obj-$(CONFIG_QE_USB) += usb.o
+obj-$(CONFIG_QE_GPIO) += gpio.o
diff --git a/arch/powerpc/sysdev/qe_lib/gpio.c
b/arch/powerpc/sysdev/qe_lib/gpio.c
new file mode 100644
index 000..c712e24
--- /dev/null
+++ b/arch/powerpc/sysdev/qe_lib/gpio.c
@@ -0,0 +1,146 @@
+/*
+ * QUICC Engine GPIOs
+ *
+ * Copyright (c) MontaVista Software, Inc. 2008.
+ *
+ * Author: Anton Vorontsov <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct qe_gpio_chip {
+ struct of_mm_gpio_chip mm_gc;
+ spinlock_t lock;
+
+ /* shadowed data register to clear/set bits safely */
+ u32 cpdata;
+};
+
+static inline struct qe_gpio_chip *
+to_qe_gpio_chip(struct of_mm_gpio_chip *mm_gc)
+{
+ return container_of(mm_gc, struct qe_gpio_chip, mm_gc);
+}
+
+static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
+{
+ struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
+ struct qe_pio_regs __iomem *regs = mm_gc->regs;
+
+ qe_gc->cpdata = in_be32(®s->cpdata);
+}
+
+static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+ struct qe_pio_regs __iomem *regs = mm_gc->regs;
+ u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
+
+ return in_be32(®s->cpdata) & pin_mask;
+}
+
+static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
+{
+ struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+ struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
+ struct qe_pio_regs __iomem *regs = mm_gc->regs;
+ unsigned long flags;
+ u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
+
+ spin_lock_irqsave(&qe_gc->lock, flags);
+
+ if (val)
+ qe_gc->cpdata |= pin_mask;
+ else
+ qe_gc->cpdata &= ~pin_mask;
+
+ out_be32(®s->
[PATCH 3/7] [POWERPC] QE: prepare QE PIO code for GPIO LIB support
- split and export __par_io_config_pin() out of par_io_config_pin(), so we
could use the prefixed version with GPIO LIB API;
- rename struct port_regs to qe_pio_regs, and place it into qe.h;
- rename #define NUM_OF_PINS to QE_PIO_PINS, and place it into qe.h.
Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
Acked-By: Timur Tabi <[EMAIL PROTECTED]>
---
arch/powerpc/sysdev/qe_lib/qe_io.c | 94 +---
include/asm-powerpc/qe.h | 19 +++
2 files changed, 64 insertions(+), 49 deletions(-)
diff --git a/arch/powerpc/sysdev/qe_lib/qe_io.c
b/arch/powerpc/sysdev/qe_lib/qe_io.c
index 93916a4..7c87460 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_io.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_io.c
@@ -28,21 +28,7 @@
#undef DEBUG
-#define NUM_OF_PINS32
-
-struct port_regs {
- __be32 cpodr; /* Open drain register */
- __be32 cpdata; /* Data register */
- __be32 cpdir1; /* Direction register */
- __be32 cpdir2; /* Direction register */
- __be32 cppar1; /* Pin assignment register */
- __be32 cppar2; /* Pin assignment register */
-#ifdef CONFIG_PPC_85xx
- u8 pad[8];
-#endif
-};
-
-static struct port_regs __iomem *par_io;
+static struct qe_pio_regs __iomem *par_io;
static int num_par_io_ports = 0;
int par_io_init(struct device_node *np)
@@ -64,69 +50,79 @@ int par_io_init(struct device_node *np)
return 0;
}
-int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
- int assignment, int has_irq)
+void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir,
+int open_drain, int assignment, int has_irq)
{
- u32 pin_mask1bit, pin_mask2bits, new_mask2bits, tmp_val;
-
- if (!par_io)
- return -1;
+ u32 pin_mask1bit;
+ u32 pin_mask2bits;
+ u32 new_mask2bits;
+ u32 tmp_val;
/* calculate pin location for single and 2 bits information */
- pin_mask1bit = (u32) (1 << (NUM_OF_PINS - (pin + 1)));
+ pin_mask1bit = (u32) (1 << (QE_PIO_PINS - (pin + 1)));
/* Set open drain, if required */
- tmp_val = in_be32(&par_io[port].cpodr);
+ tmp_val = in_be32(&par_io->cpodr);
if (open_drain)
- out_be32(&par_io[port].cpodr, pin_mask1bit | tmp_val);
+ out_be32(&par_io->cpodr, pin_mask1bit | tmp_val);
else
- out_be32(&par_io[port].cpodr, ~pin_mask1bit & tmp_val);
+ out_be32(&par_io->cpodr, ~pin_mask1bit & tmp_val);
/* define direction */
- tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
- in_be32(&par_io[port].cpdir2) :
- in_be32(&par_io[port].cpdir1);
+ tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
+ in_be32(&par_io->cpdir2) :
+ in_be32(&par_io->cpdir1);
/* get all bits mask for 2 bit per port */
- pin_mask2bits = (u32) (0x3 << (NUM_OF_PINS -
- (pin % (NUM_OF_PINS / 2) + 1) * 2));
+ pin_mask2bits = (u32) (0x3 << (QE_PIO_PINS -
+ (pin % (QE_PIO_PINS / 2) + 1) * 2));
/* Get the final mask we need for the right definition */
- new_mask2bits = (u32) (dir << (NUM_OF_PINS -
- (pin % (NUM_OF_PINS / 2) + 1) * 2));
+ new_mask2bits = (u32) (dir << (QE_PIO_PINS -
+ (pin % (QE_PIO_PINS / 2) + 1) * 2));
/* clear and set 2 bits mask */
- if (pin > (NUM_OF_PINS / 2) - 1) {
- out_be32(&par_io[port].cpdir2,
+ if (pin > (QE_PIO_PINS / 2) - 1) {
+ out_be32(&par_io->cpdir2,
~pin_mask2bits & tmp_val);
tmp_val &= ~pin_mask2bits;
- out_be32(&par_io[port].cpdir2, new_mask2bits | tmp_val);
+ out_be32(&par_io->cpdir2, new_mask2bits | tmp_val);
} else {
- out_be32(&par_io[port].cpdir1,
+ out_be32(&par_io->cpdir1,
~pin_mask2bits & tmp_val);
tmp_val &= ~pin_mask2bits;
- out_be32(&par_io[port].cpdir1, new_mask2bits | tmp_val);
+ out_be32(&par_io->cpdir1, new_mask2bits | tmp_val);
}
/* define pin assignment */
- tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
- in_be32(&par_io[port].cppar2) :
- in_be32(&par_io[port].cppar1);
+ tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
+ in_be32(&par_io->cppar2) :
+ in_be32(&par_io->cppar1);
- new_mask2bits = (u32) (assignment << (NUM_OF_PINS -
- (pin % (NUM_OF_PINS / 2) + 1) * 2));
+ new_mask2bits = (u32) (assignment << (QE_PIO_PINS -
+ (pin % (QE_PIO_PINS / 2) + 1) * 2));
/* clear and set 2 bits mask */
- if (pin > (NUM_OF_PINS / 2) - 1) {
-
[PATCH 2/7] [POWERPC] QE: add support for QE USB clocks routing
This patch adds a function to the qe_lib to setup QE USB clocks routing.
To setup clocks safely, cmxgcr register needs locking, so I just reused
ucc_lock since it was used only to protect cmxgcr.
The idea behind placing clocks routing functions into the qe_lib is that
later we'll hopefully switch to the generic Linux Clock API, thus, for
example, FHCI driver may be used for QE and CPM chips without nasty #ifdefs.
This patch also fixes QE_USB_RESTART_TX command definition in the qe.h.
Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
Acked-By: Timur Tabi <[EMAIL PROTECTED]>
---
arch/powerpc/sysdev/qe_lib/Kconfig |4 ++
arch/powerpc/sysdev/qe_lib/Makefile |1 +
arch/powerpc/sysdev/qe_lib/ucc.c|7 ++--
arch/powerpc/sysdev/qe_lib/usb.c| 56 +++
include/asm-powerpc/qe.h| 23 +-
5 files changed, 87 insertions(+), 4 deletions(-)
create mode 100644 arch/powerpc/sysdev/qe_lib/usb.c
diff --git a/arch/powerpc/sysdev/qe_lib/Kconfig
b/arch/powerpc/sysdev/qe_lib/Kconfig
index adc6621..76ffbc4 100644
--- a/arch/powerpc/sysdev/qe_lib/Kconfig
+++ b/arch/powerpc/sysdev/qe_lib/Kconfig
@@ -20,3 +20,7 @@ config UCC
bool
default y if UCC_FAST || UCC_SLOW
+config QE_USB
+ bool
+ help
+ QE USB Host Controller support
diff --git a/arch/powerpc/sysdev/qe_lib/Makefile
b/arch/powerpc/sysdev/qe_lib/Makefile
index 874fe1a..e9ff888 100644
--- a/arch/powerpc/sysdev/qe_lib/Makefile
+++ b/arch/powerpc/sysdev/qe_lib/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_ic.o qe_io.o
obj-$(CONFIG_UCC) += ucc.o
obj-$(CONFIG_UCC_SLOW) += ucc_slow.o
obj-$(CONFIG_UCC_FAST) += ucc_fast.o
+obj-$(CONFIG_QE_USB) += usb.o
diff --git a/arch/powerpc/sysdev/qe_lib/ucc.c b/arch/powerpc/sysdev/qe_lib/ucc.c
index 0e348d9..d3c7f5a 100644
--- a/arch/powerpc/sysdev/qe_lib/ucc.c
+++ b/arch/powerpc/sysdev/qe_lib/ucc.c
@@ -26,7 +26,8 @@
#include
#include
-static DEFINE_SPINLOCK(ucc_lock);
+DEFINE_SPINLOCK(cmxgcr_lock);
+EXPORT_SYMBOL(cmxgcr_lock);
int ucc_set_qe_mux_mii_mng(unsigned int ucc_num)
{
@@ -35,10 +36,10 @@ int ucc_set_qe_mux_mii_mng(unsigned int ucc_num)
if (ucc_num > UCC_MAX_NUM - 1)
return -EINVAL;
- spin_lock_irqsave(&ucc_lock, flags);
+ spin_lock_irqsave(&cmxgcr_lock, flags);
clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,
ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
- spin_unlock_irqrestore(&ucc_lock, flags);
+ spin_unlock_irqrestore(&cmxgcr_lock, flags);
return 0;
}
diff --git a/arch/powerpc/sysdev/qe_lib/usb.c b/arch/powerpc/sysdev/qe_lib/usb.c
new file mode 100644
index 000..69ce78c
--- /dev/null
+++ b/arch/powerpc/sysdev/qe_lib/usb.c
@@ -0,0 +1,56 @@
+/*
+ * QE USB routines
+ *
+ * Copyright (c) Freescale Semicondutor, Inc. 2006.
+ * Shlomi Gridish <[EMAIL PROTECTED]>
+ * Jerry Huang <[EMAIL PROTECTED]>
+ * Copyright (c) MontaVista Software, Inc. 2008.
+ * Anton Vorontsov <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+int qe_usb_clock_set(enum qe_clock clk, int rate)
+{
+ struct qe_mux __iomem *mux = &qe_immr->qmx;
+ unsigned long flags;
+ u32 val;
+
+ switch (clk) {
+ case QE_CLK3: val = QE_CMXGCR_USBCS_CLK3; break;
+ case QE_CLK5: val = QE_CMXGCR_USBCS_CLK5; break;
+ case QE_CLK7: val = QE_CMXGCR_USBCS_CLK7; break;
+ case QE_CLK9: val = QE_CMXGCR_USBCS_CLK9; break;
+ case QE_CLK13: val = QE_CMXGCR_USBCS_CLK13; break;
+ case QE_CLK17: val = QE_CMXGCR_USBCS_CLK17; break;
+ case QE_CLK19: val = QE_CMXGCR_USBCS_CLK19; break;
+ case QE_CLK21: val = QE_CMXGCR_USBCS_CLK21; break;
+ case QE_BRG9: val = QE_CMXGCR_USBCS_BRG9; break;
+ case QE_BRG10: val = QE_CMXGCR_USBCS_BRG10; break;
+ default:
+ pr_err("%s: requested unknown clock %d\n", __func__, clk);
+ return -EINVAL;
+ }
+
+ if (qe_clock_is_brg(clk))
+ qe_setbrg(clk, rate, 1);
+
+ spin_lock_irqsave(&cmxgcr_lock, flags);
+
+ clrsetbits_be32(&mux->cmxgcr, QE_CMXGCR_USBCS, val);
+
+ spin_unlock_irqrestore(&cmxgcr_lock, flags);
+
+ return 0;
+}
+EXPORT_SYMBOL(qe_usb_clock_set);
diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h
index c3be6e2..d217288 100644
--- a/include/asm-powerpc/qe.h
+++ b/include/asm-powerpc/qe.h
@@ -16,6 +16,7 @@
#define _ASM_POWERPC_QE_H
#ifdef __KERNEL__
+#include
#include
#define QE_NUM_OF_SNUM 28
@@ -74,6 +75,13 @@ enum qe_clock {
QE_CLK_DUMMY
};
+static inline b
[PATCH 1/7] [POWERPC] sysdev: implement FSL GTM support
GTM stands for General-purpose Timers Module and able to generate
timer{1,2,3,4} interrupts. These timers are used by the drivers that
need time precise interrupts (like for USB transactions scheduling for
the Freescale USB Host controller as found in some QE and CPM chips),
or these timers could be used as wakeup events from the CPU deep-sleep
mode.
Things unimplemented:
1. Cascaded (32 bit) timers (1-2, 3-4).
This is straightforward to implement when needed, two timers should
be marked as "requested" and configured as appropriate.
2. Super-cascaded (64 bit) timers (1-2-3-4).
This is also straightforward to implement when needed, all timers
should be marked as "requested" and configured as appropriate.
Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
---
Documentation/powerpc/booting-without-of.txt | 37 +++-
arch/powerpc/Kconfig |5 +
arch/powerpc/sysdev/Makefile |1 +
arch/powerpc/sysdev/fsl_gtm.c| 424 ++
include/asm-powerpc/fsl_gtm.h| 47 +++
5 files changed, 513 insertions(+), 1 deletions(-)
create mode 100644 arch/powerpc/sysdev/fsl_gtm.c
create mode 100644 include/asm-powerpc/fsl_gtm.h
diff --git a/Documentation/powerpc/booting-without-of.txt
b/Documentation/powerpc/booting-without-of.txt
index 1d2a772..fc7a235 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -57,7 +57,10 @@ Table of Contents
n) 4xx/Axon EMAC ethernet nodes
o) Xilinx IP cores
p) Freescale Synchronous Serial Interface
- q) USB EHCI controllers
+ q) USB EHCI controllers
+ r) Freescale Display Interface Unit
+ s) Freescale on board FPGA
+ t) Freescale General-purpose Timers Module
VII - Marvell Discovery mv64[345]6x System Controller chips
1) The /system-controller node
@@ -2870,6 +2873,38 @@ platforms are moved over to use the
flattened-device-tree model.
reg = <0xe800 32>;
};
+t) Freescale General-purpose Timers Module
+
+Required properties:
+ - compatible : should be
+"fsl,-gtm", "fsl,gtm" for SOC GTMs
+"fsl,-qe-gtm", "fsl,qe-gtm", "fsl,gtm" for QE GTMs
+"fsl,-cpm2-gtm", "fsl,cpm2-gtm", "fsl,gtm" for CPM2 GTMs
+ - reg : should contain gtm registers location and length (0x40).
+ - interrupts : should contain four interrupts.
+ - interrupt-parent : interrupt source phandle.
+ - clock-frequency : specifies the frequency driving the timer.
+
+Example:
+
+[EMAIL PROTECTED] {
+ compatible = "fsl,mpc8360-gtm", "fsl,gtm";
+ reg = <0x500 0x40>;
+ interrupts = <90 8 78 8 84 8 72 8>;
+ interrupt-parent = <&ipic>;
+ /* filled by u-boot */
+ clock-frequency = <0>;
+};
+
+[EMAIL PROTECTED] {
+ compatible = "fsl,mpc8360-qe-gtm", "fsl,qe-gtm", "fsl,gtm";
+ reg = <0x440 0x40>;
+ interrupts = <12 13 14 15>;
+ interrupt-parent = <&qeic>;
+ /* filled by u-boot */
+ clock-frequency = <0>;
+};
+
VII - Marvell Discovery mv64[345]6x System Controller chips
===
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 3934e26..e5d3366 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -538,6 +538,11 @@ config FSL_LBC
help
Freescale Localbus support
+config FSL_GTM
+ bool
+ help
+ Freescale General-purpose Timers support
+
# Yes MCA RS/6000s exist but Linux-PPC does not currently support any
config MCA
bool
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 2cc5052..f55e661 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
obj-$(CONFIG_FSL_SOC) += fsl_soc.o
obj-$(CONFIG_FSL_PCI) += fsl_pci.o
obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
+obj-$(CONFIG_FSL_GTM) += fsl_gtm.o
obj-$(CONFIG_RAPIDIO) += fsl_rio.o
obj-$(CONFIG_TSI108_BRIDGE)+= tsi108_pci.o tsi108_dev.o
obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
diff --git a/arch/powerpc/sysdev/fsl_gtm.c b/arch/powerpc/sysdev/fsl_gtm.c
new file mode 100644
index 000..8b35cc4
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_gtm.c
@@ -0,0 +1,424 @@
+/*
+ * Freescale General-purpose Timers Module
+ *
+ * Copyright (c) Freescale Semicondutor, Inc. 2006.
+ * Shlomi Gridish <[EMAIL PROTECTED]>
+ * Jerry Huang <[EMAIL PROTECTED]>
+ * Copyright (c) MontaVista Software, Inc. 2008.
+ * Anton Vorontsov <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later ver
[PATCH 0/7] Patches for Kumar's powerpc-next tree
Hello Kumar, Please consider applying these patches. [PATCH 1/7] [POWERPC] sysdev: implement FSL GTM support ^ no changes [PATCH 2/7] [POWERPC] QE: add support for QE USB clocks routing [PATCH 3/7] [POWERPC] QE: prepare QE PIO code for GPIO LIB support [PATCH 4/7] [POWERPC] QE: implement support for the GPIO LIB API ^ added Acked-By: Timur Tabi <[EMAIL PROTECTED]> [PATCH 5/7] [POWERPC] 83xx: new board support: MPC8360E-RDK [PATCH 6/7] [POWERPC] booting-without-of: add FHCI USB, FSL MCU, FSL UPM and GPIO LEDs bindings ^ no changes [PATCH 7/7] [POWERPC] qe_lib: switch to the cpm_muram implementation ^ Added qe_* -> cpm_* defines. Thanks, -- Anton Vorontsov email: [EMAIL PROTECTED] irc://irc.freenode.net/bd2 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH] Correct the size of reg in the spi@ entry to 7.
This is needed because there is a one byte gap between SR and CDM.
Signed-off-by: Gary Jennejohn <[EMAIL PROTECTED]>
---
arch/powerpc/boot/dts/yosemite.dts |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/boot/dts/yosemite.dts
b/arch/powerpc/boot/dts/yosemite.dts
index 0d6d332..26ab1f3 100644
--- a/arch/powerpc/boot/dts/yosemite.dts
+++ b/arch/powerpc/boot/dts/yosemite.dts
@@ -200,7 +200,7 @@
[EMAIL PROTECTED] {
compatible = "amcc,spi-440ep";
- reg = ;
+ reg = ;
interrupts = <8 4>;
interrupt-parent = <&UIC0>;
};
--
1.5.3.6
---
Gary Jennejohn
*
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: [EMAIL PROTECTED]
*
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Re: [PATCH] of/gpio: use dynamic base allocation
On Tue, Apr 29, 2008 at 06:05:24PM +0400, Anton Vorontsov wrote:
> Since gpiolib-dynamic-gpio-number-allocation.patch -mm patch was recently
> merged into Linus' tree (commit 8d0aab2f16c4fa170f32e7a74a52cd0122bbafef),
> we can use dynamic GPIO base allocation now.
>
> This, in turn, removes number of gpios per chip constraint.
>
> Signed-off-by: Anton Vorontsov <[EMAIL PROTECTED]>
> ---
Paul, could you please apply this for the powerpc-next?
Thanks.
> drivers/of/gpio.c | 38 +-
> 1 files changed, 1 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/of/gpio.c b/drivers/of/gpio.c
> index 000681e..1c9cab8 100644
> --- a/drivers/of/gpio.c
> +++ b/drivers/of/gpio.c
> @@ -137,38 +137,6 @@ int of_gpio_simple_xlate(struct of_gpio_chip *of_gc,
> struct device_node *np,
> }
> EXPORT_SYMBOL(of_gpio_simple_xlate);
>
> -/* Should be sufficient for now, later we'll use dynamic bases. */
> -#if defined(CONFIG_PPC32) || defined(CONFIG_SPARC32)
> -#define GPIOS_PER_CHIP 32
> -#else
> -#define GPIOS_PER_CHIP 64
> -#endif
> -
> -static int of_get_gpiochip_base(struct device_node *np)
> -{
> - struct device_node *gc = NULL;
> - int gpiochip_base = 0;
> -
> - while ((gc = of_find_all_nodes(gc))) {
> - if (!of_get_property(gc, "gpio-controller", NULL))
> - continue;
> -
> - if (gc != np) {
> - gpiochip_base += GPIOS_PER_CHIP;
> - continue;
> - }
> -
> - of_node_put(gc);
> -
> - if (gpiochip_base >= ARCH_NR_GPIOS)
> - return -ENOSPC;
> -
> - return gpiochip_base;
> - }
> -
> - return -ENOENT;
> -}
> -
> /**
> * of_mm_gpiochip_add - Add memory mapped GPIO chip (bank)
> * @np: device node of the GPIO chip
> @@ -205,11 +173,7 @@ int of_mm_gpiochip_add(struct device_node *np,
> if (!mm_gc->regs)
> goto err1;
>
> - gc->base = of_get_gpiochip_base(np);
> - if (gc->base < 0) {
> - ret = gc->base;
> - goto err1;
> - }
> + gc->base = -1;
>
> if (!of_gc->xlate)
> of_gc->xlate = of_gpio_simple_xlate;
> --
> 1.5.5.1
--
Anton Vorontsov
email: [EMAIL PROTECTED]
irc://irc.freenode.net/bd2
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Re: ALSA fixes for non-coherent archs (Re: [PATCH] Sam440ep support)
On mer, 14/05/2008 14.26 +0200, Takashi Iwai wrote:
[cut]
> OK, here is another patch for testing. Since I lost my old patch
> somewhere (and it's not worth to dig the archive), I wrote it up
> quickly from scratch. This version should cover both SG and non-SG
> buffers. It's against the latest git tree.
>
> The patch adds a hackish verison of dma_mmap_coherent() for some
> architectures in sound/core/pcm_native.c. I'm not sure whether this
> works. I just tested it on X86. It'd be appreciated if someone can
> test this.
>
> Also, this disables HDSPM driver for non-X86/IA64 since the driver has
> own copy and silence methods that are incompatible with the new
> SG-buffer data.
>
>
> And, yes, I know we need to clean up huge messes in ALSA memory
> handling routines. But, let's fix obvious bugs before starting a big
> rewrite...
>
I've just tested this patch on the sam440ep and it works great (and
sounds great, of course). I had also to make the following changes:
Signed-off-by: Giuseppe Coviello <[EMAIL PROTECTED]>
diff --git a/sound/pci/cs4281.c b/sound/pci/cs4281.c
index 7556fd9..f5f208e 100644
--- a/sound/pci/cs4281.c
+++ b/sound/pci/cs4281.c
@@ -952,6 +952,9 @@ static struct snd_pcm_ops snd_cs4281_playback_ops = {
.prepare = snd_cs4281_playback_prepare,
.trigger = snd_cs4281_trigger,
.pointer = snd_cs4281_pointer,
+ .copy = snd_pcm_sgbuf_ops_copy,
+ .silence = snd_pcm_sgbuf_ops_silence,
+ .page = snd_pcm_sgbuf_ops_page,
};
static struct snd_pcm_ops snd_cs4281_capture_ops = {
@@ -963,6 +966,8 @@ static struct snd_pcm_ops snd_cs4281_capture_ops = {
.prepare = snd_cs4281_capture_prepare,
.trigger = snd_cs4281_trigger,
.pointer = snd_cs4281_pointer,
+ .copy = snd_pcm_sgbuf_ops_copy,
+ .page = snd_pcm_sgbuf_ops_page,
};
static int __devinit snd_cs4281_pcm(struct cs4281 * chip, int device,
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Re: [PATCH 3/4] spi: Add OF binding support for SPI busses
On Mon, May 19, 2008 at 07:09:00PM +0200, Gary Jennejohn wrote: > On Mon, 19 May 2008 09:57:21 -0600 > "Grant Likely" <[EMAIL PROTECTED]> wrote: > > > On Mon, May 19, 2008 at 7:17 AM, Guennadi Liakhovetski > > <[EMAIL PROTECTED]> wrote: > > > On Fri, 16 May 2008, Grant Likely wrote: > > > > > >> +However, the binding does not attempt to define the specific method > > >> for > > >> +assigning chip select numbers. Since SPI chip select configuration > > >> is > > >> +flexible and non-standardized, it is left out of this binding with > > >> the > > >> +assumption that board specific platform code will be used to manage > > >> +chip selects. Individual drivers can define additional properties > > >> to > > >> +support describing the chip select layout. > > > > > > Yes, this looks like a problem to me. This means, SPI devices will need > > > two bindings - OF and platform?... Maybe define an spi_chipselect > > > OF-binding? > > > > Actually, spi devices have *neither*. :-) They bind to the SPI bus. > > Not the platform bus or of_platform bus. But that is Linux internal > > details; this discussion is about device tree bindings. > > > > Note that I did say that drivers can define additional properties for > > supporting chip select changes as needed. I'm just not attempting to > > encode them into the formal binding. There is simply just too many > > different ways to manipulate chip select signals and so I don't feel > > confident trying to define a *common* binding at this moment in time. > > At some point in the future when we have a number of examples to > > choose from then we can extend this binding with chip select related > > properties. > > > > As for the Linux internals, the 5200 SPI bus driver that I posted > > exports a function that allows another driver to call in and > > manipulated the CS lines before the transfer. It isn't the prettiest > > solution, but I'm not locked into the approach and that gives some > > time to consider cleaner interfaces. > > > > I sort of hesitate to hijack this thread, but since we're discussing SPI > and chip selects... > > I have a driver for the SPI controller in the 440EPx. This controller > is very simple and does not have any internal support for a chip select. > The controller seems to also be in the 440GR and 440EP, and may be in > other AMCC CPUs too. > > All chip selects must be done using GPIO. In fact, the board for which > I developed this driver, a modified sequoia, actually uses 2 chip selects. > > My problem was, and is, that there's no generic GPIO support for powerpc. > At least, not that I'm aware of. Please tell me if I'm wrong. Documentation/powerpc/booting-without-of.txt VIII - Specifying GPIO information for devices. And include/linux/of_gpio.h + drivers/of/gpio.c. Soon I'll post some patches for mpc83xx_spi showing how to use GPIOs for the SPI chip selects. -- Anton Vorontsov email: [EMAIL PROTECTED] irc://irc.freenode.net/bd2 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 3/4] spi: Add OF binding support for SPI busses
On Mon, 19 May 2008 09:57:21 -0600 "Grant Likely" <[EMAIL PROTECTED]> wrote: > On Mon, May 19, 2008 at 7:17 AM, Guennadi Liakhovetski > <[EMAIL PROTECTED]> wrote: > > On Fri, 16 May 2008, Grant Likely wrote: > > > >> +However, the binding does not attempt to define the specific method > >> for > >> +assigning chip select numbers. Since SPI chip select configuration is > >> +flexible and non-standardized, it is left out of this binding with the > >> +assumption that board specific platform code will be used to manage > >> +chip selects. Individual drivers can define additional properties to > >> +support describing the chip select layout. > > > > Yes, this looks like a problem to me. This means, SPI devices will need > > two bindings - OF and platform?... Maybe define an spi_chipselect > > OF-binding? > > Actually, spi devices have *neither*. :-) They bind to the SPI bus. > Not the platform bus or of_platform bus. But that is Linux internal > details; this discussion is about device tree bindings. > > Note that I did say that drivers can define additional properties for > supporting chip select changes as needed. I'm just not attempting to > encode them into the formal binding. There is simply just too many > different ways to manipulate chip select signals and so I don't feel > confident trying to define a *common* binding at this moment in time. > At some point in the future when we have a number of examples to > choose from then we can extend this binding with chip select related > properties. > > As for the Linux internals, the 5200 SPI bus driver that I posted > exports a function that allows another driver to call in and > manipulated the CS lines before the transfer. It isn't the prettiest > solution, but I'm not locked into the approach and that gives some > time to consider cleaner interfaces. > I sort of hesitate to hijack this thread, but since we're discussing SPI and chip selects... I have a driver for the SPI controller in the 440EPx. This controller is very simple and does not have any internal support for a chip select. The controller seems to also be in the 440GR and 440EP, and may be in other AMCC CPUs too. All chip selects must be done using GPIO. In fact, the board for which I developed this driver, a modified sequoia, actually uses 2 chip selects. My problem was, and is, that there's no generic GPIO support for powerpc. At least, not that I'm aware of. Please tell me if I'm wrong. So the driver has great gobs of GPIO code in it, most of which I took from u-boot. The code is pretty generic, but some 440EPx-specific stuff may have crept in without my being aware of it. My real question is - should this code be in a platform-specific file such as sequoia.c, which could result in lots of duplicated code, or is it better to leave it in the driver for now until some day we hopefully get generic GPIO support for powerpc? I want to get this driver upstream ASAP. --- Gary Jennejohn * DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: [EMAIL PROTECTED] * ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 3/4] spi: Add OF binding support for SPI busses
On Mon, 19 May 2008, Grant Likely wrote:
> On Mon, May 19, 2008 at 7:17 AM, Guennadi Liakhovetski
> <[EMAIL PROTECTED]> wrote:
> > On Fri, 16 May 2008, Grant Likely wrote:
> >
> >> +However, the binding does not attempt to define the specific method
> >> for
> >> +assigning chip select numbers. Since SPI chip select configuration is
> >> +flexible and non-standardized, it is left out of this binding with the
> >> +assumption that board specific platform code will be used to manage
> >> +chip selects. Individual drivers can define additional properties to
> >> +support describing the chip select layout.
> >
> > Yes, this looks like a problem to me. This means, SPI devices will need
> > two bindings - OF and platform?... Maybe define an spi_chipselect
> > OF-binding?
>
> Actually, spi devices have *neither*. :-) They bind to the SPI bus.
> Not the platform bus or of_platform bus.
Right, sorry, your SPI bus driver scans the bus device bindings and
registers devices on it using spi_of_register_devices().
> But that is Linux internal
> details; this discussion is about device tree bindings.
>
> Note that I did say that drivers can define additional properties for
> supporting chip select changes as needed. I'm just not attempting to
> encode them into the formal binding. There is simply just too many
> different ways to manipulate chip select signals and so I don't feel
> confident trying to define a *common* binding at this moment in time.
Yes, I understand, that physically there can be many ways SPI chipselects
can be controlled. But I thought there could be a generic way to cover
them all by defining a separate entry on your SPI bus. Like
+SPI example for an MPC5200 SPI bus:
+ [EMAIL PROTECTED] {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
+ reg = <0xf00 0x20>;
+ interrupts = <2 13 0 2 14 0>;
+ interrupt-parent = <&mpc5200_pic>;
+ [EMAIL PROTECTED] {
+ compatible = "oem,cs-type";
+ };
+
+ [EMAIL PROTECTED] {
+ compatible = "micrel,ks8995m";
+ linux,modalias = "ks8995";
+ max-speed = <100>;
+ reg = <0>;
+ cs-parent = <&/.../[EMAIL PROTECTED]/[EMAIL
PROTECTED]>;
+ };
...
+ };
Then whatever method is used to actually switch the CS, a driver should be
registered to handle [EMAIL PROTECTED], providing the required calls.
Without such a driver [EMAIL PROTECTED] will not probe successfully.
Wouldn't this cover all possible cases? One could even consider actually
putting SPI devices on SPI chipselect busses, but that won't look very
elegant:-)
Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
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[PATCH 1/1] ibmvscsi: Non SCSI error status fixup
On Mon, 19 May 2008 10:27:56 -0500, Brian King <[EMAIL PROTECTED]> said: > > Some versions of the Virtual I/O Server on Power > return 0x99 in the non-SCSI error status field as success, > rather than 0. This fixes the ibmvscsi driver to treat this > response as success. Yeah0x99...that's an intuitive value for success. Dave B ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 3/4] spi: Add OF binding support for SPI busses
On Mon, May 19, 2008 at 7:17 AM, Guennadi Liakhovetski <[EMAIL PROTECTED]> wrote: > On Fri, 16 May 2008, Grant Likely wrote: > >> +However, the binding does not attempt to define the specific method for >> +assigning chip select numbers. Since SPI chip select configuration is >> +flexible and non-standardized, it is left out of this binding with the >> +assumption that board specific platform code will be used to manage >> +chip selects. Individual drivers can define additional properties to >> +support describing the chip select layout. > > Yes, this looks like a problem to me. This means, SPI devices will need > two bindings - OF and platform?... Maybe define an spi_chipselect > OF-binding? Actually, spi devices have *neither*. :-) They bind to the SPI bus. Not the platform bus or of_platform bus. But that is Linux internal details; this discussion is about device tree bindings. Note that I did say that drivers can define additional properties for supporting chip select changes as needed. I'm just not attempting to encode them into the formal binding. There is simply just too many different ways to manipulate chip select signals and so I don't feel confident trying to define a *common* binding at this moment in time. At some point in the future when we have a number of examples to choose from then we can extend this binding with chip select related properties. As for the Linux internals, the 5200 SPI bus driver that I posted exports a function that allows another driver to call in and manipulated the CS lines before the transfer. It isn't the prettiest solution, but I'm not locked into the approach and that gives some time to consider cleaner interfaces. Cheers, g. -- Grant Likely, B.Sc., P.Eng. Secret Lab Technologies Ltd. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH 1/1] ibmvscsi: Non SCSI error status fixup
Some versions of the Virtual I/O Server on Power
return 0x99 in the non-SCSI error status field as success,
rather than 0. This fixes the ibmvscsi driver to treat this
response as success.
Signed-off-by: Brian King <[EMAIL PROTECTED]>
---
linux-2.6-bjking1/drivers/scsi/ibmvscsi/ibmvscsi.c |2 +-
linux-2.6-bjking1/drivers/scsi/ibmvscsi/viosrp.h |3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff -puN drivers/scsi/ibmvscsi/viosrp.h~ibmvscsi_non_scsi_status_workaround
drivers/scsi/ibmvscsi/viosrp.h
---
linux-2.6/drivers/scsi/ibmvscsi/viosrp.h~ibmvscsi_non_scsi_status_workaround
2008-05-19 10:01:00.0 -0500
+++ linux-2.6-bjking1/drivers/scsi/ibmvscsi/viosrp.h2008-05-19
10:01:33.0 -0500
@@ -65,7 +65,8 @@ enum viosrp_crq_status {
VIOSRP_VIOLATES_MAX_XFER = 0x2,
VIOSRP_PARTNER_PANIC = 0x3,
VIOSRP_DEVICE_BUSY = 0x8,
- VIOSRP_ADAPTER_FAIL = 0x10
+ VIOSRP_ADAPTER_FAIL = 0x10,
+ VIOSRP_OK2 = 0x99,
};
struct viosrp_crq {
diff -puN drivers/scsi/ibmvscsi/ibmvscsi.c~ibmvscsi_non_scsi_status_workaround
drivers/scsi/ibmvscsi/ibmvscsi.c
---
linux-2.6/drivers/scsi/ibmvscsi/ibmvscsi.c~ibmvscsi_non_scsi_status_workaround
2008-05-19 10:01:44.0 -0500
+++ linux-2.6-bjking1/drivers/scsi/ibmvscsi/ibmvscsi.c 2008-05-19
10:02:24.0 -0500
@@ -1348,7 +1348,7 @@ void ibmvscsi_handle_crq(struct viosrp_c
del_timer(&evt_struct->timer);
- if (crq->status != VIOSRP_OK && evt_struct->cmnd)
+ if ((crq->status != VIOSRP_OK && crq->status != VIOSRP_OK2) &&
evt_struct->cmnd)
evt_struct->cmnd->result = DID_ERROR << 16;
if (evt_struct->done)
evt_struct->done(evt_struct);
_
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Re: Using GPIO
arch/ppc/syslib/virtex_devices.c:
// 0 is LEDS_4BIT, 1 is LEDS_POSITIONS, 2 is PUSH_BUTTONS_POSITION
#define XPAR_GPIO(num) { \
.name = "xilinx_gpio", \
.id = num, \
.num_resources = 2, \
That was a 2.
If anybody wants to make a patch out of those few lines of code, I couldn't
figure out how to do this with git... But I will use a more general GPIO
approach as soon as I can put my hands on our custom card.
.resource = (struct resource[]) { \
{ \
.start = XPAR_GPIO_##num##_BASEADDR, \
.end = XPAR_GPIO_##num##_HIGHADDR, \
.flags = IORESOURCE_MEM, \
}, \
{ \
.start = XPAR_INTC_0_GPIO_##num##_VEC_ID, \
.flags = IORESOURCE_IRQ, \
}, \
}, \
}
[...]
/* GPIO instances */
#if defined(XPAR_GPIO_0_BASEADDR)
XPAR_GPIO(0),
#endif
#if defined(XPAR_GPIO_1_BASEADDR)
XPAR_GPIO(1),
#endif
#if defined(XPAR_GPIO_2_BASEADDR)
XPAR_GPIO(2),
#endif
--
Guillaume Dargaud
http://www.gdargaud.net/
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Please pull 'for-2.6.26' branch of 4xx tree
Hi Paul,
Please pull from:
master.kernel.org:/pub/scm/linux/kernel/git/jwboyer/powerpc-4xx.git for-2.6.26
to pick up one bugfix for 4xx. This patch works around an errata for
440{EP,GR,EPx,GRx} chips that can cause hangs on the PLB4 bus.
The tree is based off of Linus' 2.6.26-rc3. If you've no objections
or other patches queued up, Linus can pull directly if he'd like.
josh
Josh Boyer (1):
[POWERPC] 4xx: Workaround for CHIP_11 Errata
arch/powerpc/boot/4xx.c | 21 +
1 files changed, 21 insertions(+), 0 deletions(-)
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Re: Patches added to powerpc.git powerpc-next branch
Timur Tabi wrote: > I don't want to nag, but I would like to know if and when you're planning on > pulling this patch of mine: Sorry, never mind. I just noticed that they've been pulled already. I didn't see your email about them. I must remember to check the git log before asking about patches. I must remember to check the git log before asking about patches. I must remember to check the git log before asking about patches. I must remember to check the git log before asking about patches. I must remember to check the git log before asking about patches. I must remember to check the git log before asking about patches. I must remember to check the git log before asking about patches. I must remember to check the git log before asking about patches. I must remember to check the git log before asking about patches. I must remember to check the git log before asking about patches. :-) -- Timur Tabi Linux kernel developer at Freescale ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: Patches added to powerpc.git powerpc-next branch
Paul Mackerras wrote: > I have pulled Linus' tree into the powerpc-next branch of powerpc.git, > and added the following 4 patches. Paul, I don't want to nag, but I would like to know if and when you're planning on pulling this patch of mine: [PATCH] Add null pointer check to of_find_property I have code in the ASoC repository that depends on this patch. -- Timur Tabi Linux kernel developer at Freescale ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
