[PATCH 3/7] pci: make find_pci_host_bridge global
The patch makes function find_pci_host_bridge() global so that the
platforms (e.g. PPC) can access pci_host_bridge.
Signed-off-by: Gavin Shan sha...@linux.vnet.ibm.com
---
drivers/pci/host-bridge.c |2 +-
include/linux/pci.h |1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/host-bridge.c b/drivers/pci/host-bridge.c
index fc16357..a43d393 100644
--- a/drivers/pci/host-bridge.c
+++ b/drivers/pci/host-bridge.c
@@ -17,7 +17,7 @@ static struct pci_bus *find_pci_root_bus(struct pci_bus *bus)
return bus;
}
-static struct pci_host_bridge *find_pci_host_bridge(struct pci_bus *bus)
+struct pci_host_bridge *find_pci_host_bridge(struct pci_bus *bus)
{
struct pci_bus *root_bus = find_pci_root_bus(bus);
diff --git a/include/linux/pci.h b/include/linux/pci.h
index fefb4e1..615ac90 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -385,6 +385,7 @@ struct pci_host_bridge {
};
#defineto_pci_host_bridge(n) container_of(n, struct pci_host_bridge,
dev)
+struct pci_host_bridge *find_pci_host_bridge(struct pci_bus *bus);
void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
void (*release_fn)(struct pci_host_bridge *),
void *release_data);
--
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[PATCH 4/7] pci: fiddle with conversion of pci and CPU address
The patch fiddles with the those functions used to do conversion
between PCI and CPU address. More specificly, 2 functions are
involved: pcibios_bus_to_resource() and pcibios_resource_to_bus()
Signed-off-by: Yinghai Lu ying...@kernel.org
Signed-off-by: Gavin Shan sha...@linux.vnet.ibm.com
---
drivers/pci/host-bridge.c | 24 +++-
include/linux/pci.h |5 -
2 files changed, 23 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/host-bridge.c b/drivers/pci/host-bridge.c
index a43d393..1854a2d 100644
--- a/drivers/pci/host-bridge.c
+++ b/drivers/pci/host-bridge.c
@@ -37,10 +37,10 @@ static bool resource_contains(struct resource *res1, struct
resource *res2)
return res1-start = res2-start res1-end = res2-end;
}
-void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region
*region,
-struct resource *res)
+void __pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region
*region,
+ struct resource *res)
{
- struct pci_host_bridge *bridge = find_pci_host_bridge(dev-bus);
+ struct pci_host_bridge *bridge = find_pci_host_bridge(bus);
struct pci_host_bridge_window *window;
resource_size_t offset = 0;
@@ -57,6 +57,13 @@ void pcibios_resource_to_bus(struct pci_dev *dev, struct
pci_bus_region *region,
region-start = res-start - offset;
region-end = res-end - offset;
}
+
+void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region
*region,
+struct resource *res)
+{
+ __pcibios_resource_to_bus(dev-bus, region, res);
+}
+
EXPORT_SYMBOL(pcibios_resource_to_bus);
static bool region_contains(struct pci_bus_region *region1,
@@ -65,10 +72,10 @@ static bool region_contains(struct pci_bus_region *region1,
return region1-start = region2-start region1-end = region2-end;
}
-void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+void __pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
struct pci_bus_region *region)
{
- struct pci_host_bridge *bridge = find_pci_host_bridge(dev-bus);
+ struct pci_host_bridge *bridge = find_pci_host_bridge(bus);
struct pci_host_bridge_window *window;
resource_size_t offset = 0;
@@ -90,4 +97,11 @@ void pcibios_bus_to_resource(struct pci_dev *dev, struct
resource *res,
res-start = region-start + offset;
res-end = region-end + offset;
}
+
+void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+struct pci_bus_region *region)
+{
+ __pcibios_bus_to_resource(dev-bus, res, region);
+}
+
EXPORT_SYMBOL(pcibios_bus_to_resource);
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 615ac90..e66f4b2 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -657,9 +657,12 @@ void pcibios_update_irq(struct pci_dev *, int irq);
void pci_fixup_cardbus(struct pci_bus *);
/* Generic PCI functions used internally */
-
+void __pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region
*region,
+ struct resource *res);
void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region
*region,
struct resource *res);
+void __pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
+ struct pci_bus_region *region);
void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
struct pci_bus_region *region);
void pcibios_scan_specific_bus(int busn);
--
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[PATCH V5 0/7] minimal alignment for p2p bars
v1 - v2: * Shorten the varaible names so that they looks more short. * Changelog adjustment so that they looks more meaningful. v2 - v3: * Rebase to 3.5.RC4 v3 - v4: * Merge Yinghai's patches. v3 - v4: * Split patch for easy review. * Add function to retrieve the minimal alignment of p2p bridge. Lu Yinghai(3): pci: change variable name for find_pci_host_bridge pci: argument pci_bus for find_pci_host_bridge pci: fiddle with conversion of pci and CPU address Gavin Shan(4) pci: make find_pci_host_bridge global pci: minimal alignment for bars of P2P bridges pci: function to retrieve alignment of p2p bars pci: resource assignment based on p2p alignment drivers/pci/host-bridge.c | 59 - drivers/pci/probe.c |5 drivers/pci/setup-bus.c | 22 +++-- include/linux/pci.h | 15 +++- 4 files changed, 81 insertions(+), 20 deletions(-) Thanks, Gavin ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 2/7] pci: argument pci_bus for find_pci_host_bridge
The patch changes the argument of find_pci_host_bridge() to pci_bus.
Signed-off-by: Yinghai Lu ying...@kernel.org
Signed-off-by: Gavin Shan sha...@linux.vnet.ibm.com
---
drivers/pci/host-bridge.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/pci/host-bridge.c b/drivers/pci/host-bridge.c
index c19776a..fc16357 100644
--- a/drivers/pci/host-bridge.c
+++ b/drivers/pci/host-bridge.c
@@ -9,20 +9,17 @@
#include pci.h
-static struct pci_bus *find_pci_root_bus(struct pci_dev *dev)
+static struct pci_bus *find_pci_root_bus(struct pci_bus *bus)
{
- struct pci_bus *bus;
-
- bus = dev-bus;
while (bus-parent)
bus = bus-parent;
return bus;
}
-static struct pci_host_bridge *find_pci_host_bridge(struct pci_dev *dev)
+static struct pci_host_bridge *find_pci_host_bridge(struct pci_bus *bus)
{
- struct pci_bus *root_bus = find_pci_root_bus(dev);
+ struct pci_bus *root_bus = find_pci_root_bus(bus);
return to_pci_host_bridge(root_bus-bridge);
}
@@ -43,7 +40,7 @@ static bool resource_contains(struct resource *res1, struct
resource *res2)
void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region
*region,
struct resource *res)
{
- struct pci_host_bridge *bridge = find_pci_host_bridge(dev);
+ struct pci_host_bridge *bridge = find_pci_host_bridge(dev-bus);
struct pci_host_bridge_window *window;
resource_size_t offset = 0;
@@ -71,7 +68,7 @@ static bool region_contains(struct pci_bus_region *region1,
void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
struct pci_bus_region *region)
{
- struct pci_host_bridge *bridge = find_pci_host_bridge(dev);
+ struct pci_host_bridge *bridge = find_pci_host_bridge(dev-bus);
struct pci_host_bridge_window *window;
resource_size_t offset = 0;
--
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[PATCH 7/7] pci: resource assignment based on p2p alignment
The patch changes function pbus_size_io() and pbus_size_mem() to
do resource (I/O, memory and prefetchable memory) reassignment
based on the minimal alignments from the p2p bridge.
Signed-off-by: Gavin Shan sha...@linux.vnet.ibm.com
---
drivers/pci/setup-bus.c | 22 +++---
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index 8fa2d4b..52b60af 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -710,6 +710,7 @@ static void pbus_size_io(struct pci_bus *bus,
resource_size_t min_size,
struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
unsigned long size = 0, size0 = 0, size1 = 0;
resource_size_t children_add_size = 0;
+ resource_size_t io_align;
if (!b_res)
return;
@@ -735,13 +736,15 @@ static void pbus_size_io(struct pci_bus *bus,
resource_size_t min_size,
children_add_size +=
get_res_add_size(realloc_head, r);
}
}
+
+ io_align = pci_align_boundary(bus, IORESOURCE_IO);
size0 = calculate_iosize(size, min_size, size1,
- resource_size(b_res), 4096);
+ resource_size(b_res), io_align);
if (children_add_size add_size)
add_size = children_add_size;
size1 = (!realloc_head || (realloc_head !add_size)) ? size0 :
calculate_iosize(size, min_size, add_size + size1,
- resource_size(b_res), 4096);
+ resource_size(b_res), io_align);
if (!size0 !size1) {
if (b_res-start || b_res-end)
dev_info(bus-self-dev, disabling bridge window
@@ -751,11 +754,11 @@ static void pbus_size_io(struct pci_bus *bus,
resource_size_t min_size,
return;
}
/* Alignment of the IO window is always 4K */
- b_res-start = 4096;
+ b_res-start = io_align;
b_res-end = b_res-start + size0 - 1;
b_res-flags |= IORESOURCE_STARTALIGN;
if (size1 size0 realloc_head) {
- add_to_list(realloc_head, bus-self, b_res, size1-size0, 4096);
+ add_to_list(realloc_head, bus-self, b_res, size1-size0,
io_align);
dev_printk(KERN_DEBUG, bus-self-dev, bridge window
%pR to [bus %02x-%02x] add_size %lx\n, b_res,
bus-secondary, bus-subordinate, size1-size0);
@@ -785,10 +788,15 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned
long mask,
struct resource *b_res = find_free_bus_resource(bus, type);
unsigned int mem64_mask = 0;
resource_size_t children_add_size = 0;
+ resource_size_t mem_align;
+ int mem_align_shift;
if (!b_res)
return 0;
+ mem_align = pci_align_boundary(bus, type);
+ mem_align_shift = __ffs(mem_align);
+
memset(aligns, 0, sizeof(aligns));
max_order = 0;
size = 0;
@@ -818,8 +826,8 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long
mask,
#endif
/* For bridges size != alignment */
align = pci_resource_alignment(dev, r);
- order = __ffs(align) - 20;
- if (order 11) {
+ order = __ffs(align) - mem_align_shift;
+ if (order (11 - (mem_align_shift - 20))) {
dev_warn(dev-dev, disabling BAR %d: %pR
(bad alignment %#llx)\n, i, r,
(unsigned long long) align);
@@ -846,7 +854,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long
mask,
for (order = 0; order = max_order; order++) {
resource_size_t align1 = 1;
- align1 = (order + 20);
+ align1 = (order + mem_align_shift);
if (!align)
min_align = align1;
--
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[PATCH 1/7] pci: change variable name for find_pci_host_bridge
The patch changes the variable name for function find_pci_host_bridge()
so that it looks more meaningful. More specificly, the bus has been
replaced with root_bus.
Signed-off-by: Yinghai Lu ying...@kernel.org
Signed-off-by: Gavin Shan sha...@linux.vnet.ibm.com
---
drivers/pci/host-bridge.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/host-bridge.c b/drivers/pci/host-bridge.c
index a68dc61..c19776a 100644
--- a/drivers/pci/host-bridge.c
+++ b/drivers/pci/host-bridge.c
@@ -22,9 +22,9 @@ static struct pci_bus *find_pci_root_bus(struct pci_dev *dev)
static struct pci_host_bridge *find_pci_host_bridge(struct pci_dev *dev)
{
- struct pci_bus *bus = find_pci_root_bus(dev);
+ struct pci_bus *root_bus = find_pci_root_bus(dev);
- return to_pci_host_bridge(bus-bridge);
+ return to_pci_host_bridge(root_bus-bridge);
}
void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
--
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[PATCH 5/7] pci: minimal alignment for bars of P2P bridges
On some powerpc platforms, device BARs need to be assigned to separate
segments of the address space in order for the error isolation and HW
virtualization mechanisms (EEH) to work properly. Those segments have
a minimum size that can be fairly large (16M). In order to be able to
use the generic resource assignment code rather than re-inventing our
own, we chose to group devices by bus. That way, a simple change of the
minimum alignment requirements of resources assigned to PCI to PCI (P2P)
bridges is enough to ensure that all BARs for devices below those bridges
will fit into contiguous sets of segments and there will be no overlap.
This patch provides a way for the host bridge to override the default
alignment values used by the resource allocation code for that purpose.
Signed-off-by: Gavin Shan sha...@linux.vnet.ibm.com
Reviewed-by: Ram Pai linux...@us.ibm.com
Reviewed-by: Richard Yang weiy...@linux.vnet.ibm.com
---
drivers/pci/probe.c |5 +
include/linux/pci.h |8
2 files changed, 13 insertions(+)
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 658ac97..a196529 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -431,6 +431,11 @@ static struct pci_host_bridge
*pci_alloc_host_bridge(struct pci_bus *b)
if (bridge) {
INIT_LIST_HEAD(bridge-windows);
bridge-bus = b;
+
+ /* Set minimal alignment shift of P2P bridges */
+ bridge-io_align_shift = PCI_DEFAULT_IO_ALIGN_SHIFT;
+ bridge-mem_align_shift = PCI_DEFAULT_MEM_ALIGN_SHIFT;
+ bridge-pmem_align_shift = PCI_DEFAULT_PMEM_ALIGN_SHIFT;
}
return bridge;
diff --git a/include/linux/pci.h b/include/linux/pci.h
index e66f4b2..2b2b38d 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -376,9 +376,17 @@ struct pci_host_bridge_window {
resource_size_t offset; /* bus address + offset = CPU address */
};
+/* Default shits for P2P I/O and MMIO bar minimal alignment shifts */
+#define PCI_DEFAULT_IO_ALIGN_SHIFT 12 /* 4KB */
+#define PCI_DEFAULT_MEM_ALIGN_SHIFT20 /* 1MB */
+#define PCI_DEFAULT_PMEM_ALIGN_SHIFT 20 /* 1MB */
+
struct pci_host_bridge {
struct device dev;
struct pci_bus *bus;/* root bus */
+ int io_align_shift; /* P2P I/O bar minimal alignment shift
*/
+ int mem_align_shift;/* P2P MMIO bar minimal alignment shift
*/
+ int pmem_align_shift; /* P2P prefetchable MMIO bar minimal
alignment shift */
struct list_head windows; /* pci_host_bridge_windows */
void (*release_fn)(struct pci_host_bridge *);
void *release_data;
--
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[PATCH 6/7] pci: function to retrieve alignment of p2p bars
The patch introduces function pci_align_boundary() to retrieve the
minimal alignment of p2p bars according to the argument.
Signed-off-by: Gavin Shan sha...@linux.vnet.ibm.com
---
drivers/pci/host-bridge.c | 24
include/linux/pci.h |1 +
2 files changed, 25 insertions(+)
diff --git a/drivers/pci/host-bridge.c b/drivers/pci/host-bridge.c
index 1854a2d..dc9a95e 100644
--- a/drivers/pci/host-bridge.c
+++ b/drivers/pci/host-bridge.c
@@ -105,3 +105,27 @@ void pcibios_bus_to_resource(struct pci_dev *dev, struct
resource *res,
}
EXPORT_SYMBOL(pcibios_bus_to_resource);
+
+resource_size_t pci_align_boundary(struct pci_bus *bus, unsigned long flags)
+{
+ resource_size_t align = 0;
+ struct pci_host_bridge *bridge = find_pci_host_bridge(bus);
+
+ flags = (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
+ switch (flags) {
+ case IORESOURCE_IO:
+ align = (1 bridge-io_align_shift);
+ break;
+ case IORESOURCE_MEM:
+ align = (1 bridge-mem_align_shift);
+ break;
+ case (IORESOURCE_MEM | IORESOURCE_PREFETCH):
+ align = (1 bridge-pmem_align_shift);
+ break;
+ default:
+ printk(KERN_WARNING %s: invalid flags 0x%lx\n,
+ __func__, flags);
+ }
+
+ return align;
+}
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 2b2b38d..64523ef 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -673,6 +673,7 @@ void __pcibios_bus_to_resource(struct pci_bus *bus, struct
resource *res,
struct pci_bus_region *region);
void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
struct pci_bus_region *region);
+resource_size_t pci_align_boundary(struct pci_bus *bus, unsigned long flags);
void pcibios_scan_specific_bus(int busn);
extern struct pci_bus *pci_find_bus(int domain, int busnr);
void pci_bus_add_devices(const struct pci_bus *bus);
--
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Re: [PATCH 2/3] mtd: delete SBC82xx/SBC8560 MTD mapping support
On Tue, 2012-06-26 at 15:54 -0400, Paul Gortmaker wrote: The SBC8260 support was dropped back when we moved from ppc to powerpc. We are now also dropping the support for the EOL SBC8560, so we can also delete this mapping support, as they were the only users of it. Cc: David Woodhouse david.woodho...@intel.com Cc: linux-...@lists.infradead.org Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com You forgot this: diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile index 68a9a91..deb43e9 100644 --- a/drivers/mtd/maps/Makefile +++ b/drivers/mtd/maps/Makefile @@ -47,7 +47,6 @@ obj-$(CONFIG_MTD_SCB2_FLASH) += scb2_flash.o obj-$(CONFIG_MTD_H720X)+= h720x-flash.o obj-$(CONFIG_MTD_IXP4XX) += ixp4xx.o obj-$(CONFIG_MTD_IXP2000) += ixp2000.o -obj-$(CONFIG_MTD_WRSBC8260)+= wr_sbc82xx_flash.o obj-$(CONFIG_MTD_DMV182) += dmv182.o obj-$(CONFIG_MTD_PLATRAM) += plat-ram.o obj-$(CONFIG_MTD_INTEL_VR_NOR) += intel_vr_nor.o I've amended the patch and pushed to l2-mtd.git tree, thanks! -- Best Regards, Artem Bityutskiy signature.asc Description: This is a digitally signed message part ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/p2041rdb: add NAND node in device tree
NAND on p2041 uses CS1 as chip select.
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
arch/powerpc/boot/dts/p2041rdb.dts | 41 +++-
1 files changed, 40 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/boot/dts/p2041rdb.dts
b/arch/powerpc/boot/dts/p2041rdb.dts
index 2852139..baab034 100644
--- a/arch/powerpc/boot/dts/p2041rdb.dts
+++ b/arch/powerpc/boot/dts/p2041rdb.dts
@@ -121,7 +121,8 @@
lbc: localbus@ffe124000 {
reg = 0xf 0xfe124000 0 0x1000;
- ranges = 0 0 0xf 0xe800 0x0800;
+ ranges = 0 0 0xf 0xe800 0x0800
+ 1 0 0xf 0xffa0 0x0004;
flash@0,0 {
compatible = cfi-flash;
@@ -129,6 +130,44 @@
bank-width = 2;
device-width = 2;
};
+
+ nand@1,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,elbc-fcm-nand;
+ reg = 0x1 0x0 0x4;
+
+ partition@0 {
+ label = NAND U-Boot Image;
+ reg = 0x0 0x0200;
+ read-only;
+ };
+
+ partition@200 {
+ label = NAND Root File System;
+ reg = 0x0200 0x1000;
+ };
+
+ partition@1200 {
+ label = NAND Compressed RFS Image;
+ reg = 0x1200 0x0800;
+ };
+
+ partition@1a00 {
+ label = NAND Linux Kernel Image;
+ reg = 0x1a00 0x0400;
+ };
+
+ partition@1e00 {
+ label = NAND DTB Image;
+ reg = 0x1e00 0x0100;
+ };
+
+ partition@1f00 {
+ label = NAND Writable User area;
+ reg = 0x1f00 0x0100;
+ };
+ };
};
pci0: pcie@ffe20 {
--
1.6.4
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RE: [PATCH v6 1/5] powerpc/85xx: implement hardware timebase sync
-Original Message- From: Linuxppc-dev [mailto:linuxppc-dev-bounces+chenhui.zhao=freescale@lists.ozlabs.org] On Behalf Of Kumar Gala Sent: Friday, June 29, 2012 2:30 AM To: Zhao Chenhui-B35336 Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org list; linux-ker...@vger.kernel.org list Subject: Re: [PATCH v6 1/5] powerpc/85xx: implement hardware timebase sync On Jun 28, 2012, at 5:50 AM, Benjamin Herrenschmidt wrote: On Thu, 2012-06-28 at 11:38 +0800, Zhao Chenhui wrote: The bootloader have done a timebase sync. If we do not need KEXEC or HOTPLUG_CPU feature, it is unnecessary to do it again at boot time of kernel. I only compile the timebase sync routines when users enable KEXEC or HOTPLUG_CPU. Still, how much are you really saving ? Is it worth the added mess and loss of test coverage ? We have too many conditional stuff like that already. Cheers, Ben. I'd also be interested to know how long it actually takes to do time base sync this way. Since you are freezing the timers for some period how long does it really take between the freeze/unfreeze in mpc85xx_give_timebase() + mpc85xx_timebase_freeze(1); ... + mpc85xx_timebase_freeze(0); You can use ATBL/U as a way to see # of cycles taken. - k I measured it using ATBL on MPC8572DS with 1.5GHz core frequency and 600MHz CCB frequency. The average of 10 times is 1019 clock. It seems that most of the time spent by isync and msync. -Chenhui ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] common: dma-mapping: add support for generic dma_mmap_* calls
Marek Szyprowski wrote:
+++ b/drivers/base/dma-mapping.c
...
+int dma_common_mmap(struct device *dev, struct vm_area_struct *vma,
+ void *cpu_addr, dma_addr_t dma_addr, size_t size)
+{
+ int ret = -ENXIO;
+ ...
+ if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, ret))
+ return ret;
This will return -ENXIO if dma_mmap_from_coherent() succeeds.
Regards,
Clemens
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RE: [PATCH] common: dma-mapping: add support for generic dma_mmap_* calls
Hi,
On Friday, June 29, 2012 1:10 PM Clemens Ladisch wrote:
Marek Szyprowski wrote:
+++ b/drivers/base/dma-mapping.c
...
+int dma_common_mmap(struct device *dev, struct vm_area_struct *vma,
+ void *cpu_addr, dma_addr_t dma_addr, size_t size)
+{
+ int ret = -ENXIO;
+ ...
+ if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, ret))
+ return ret;
This will return -ENXIO if dma_mmap_from_coherent() succeeds.
Thanks for spotting this! I will fix it in the next version of the patch.
Best regards
--
Marek Szyprowski
Samsung Poland RD Center
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Re: [PATCH] common: dma-mapping: add support for generic dma_mmap_* calls
Marek Szyprowski wrote:
On Friday, June 29, 2012 1:10 PM Clemens Ladisch wrote:
Marek Szyprowski wrote:
+++ b/drivers/base/dma-mapping.c
...
+int dma_common_mmap(struct device *dev, struct vm_area_struct *vma,
+ void *cpu_addr, dma_addr_t dma_addr, size_t size)
+{
+ int ret = -ENXIO;
+ ...
+ if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, ret))
+ return ret;
This will return -ENXIO if dma_mmap_from_coherent() succeeds.
Thanks for spotting this!
Sorry, I was wrong; ret is actually set by dma_mmap_from_coherent's
output parameter. (That function's documentation appears to be
incomplete.)
Regards,
Clemens
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Re: [PATCH 2/3] mtd: delete SBC82xx/SBC8560 MTD mapping support
On 12-06-29 04:29 AM, Artem Bityutskiy wrote: On Tue, 2012-06-26 at 15:54 -0400, Paul Gortmaker wrote: The SBC8260 support was dropped back when we moved from ppc to powerpc. We are now also dropping the support for the EOL SBC8560, so we can also delete this mapping support, as they were the only users of it. Cc: David Woodhouse david.woodho...@intel.com Cc: linux-...@lists.infradead.org Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com You forgot this: diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile index 68a9a91..deb43e9 100644 --- a/drivers/mtd/maps/Makefile +++ b/drivers/mtd/maps/Makefile @@ -47,7 +47,6 @@ obj-$(CONFIG_MTD_SCB2_FLASH) += scb2_flash.o obj-$(CONFIG_MTD_H720X)+= h720x-flash.o obj-$(CONFIG_MTD_IXP4XX) += ixp4xx.o obj-$(CONFIG_MTD_IXP2000) += ixp2000.o -obj-$(CONFIG_MTD_WRSBC8260)+= wr_sbc82xx_flash.o Agreed. I'd figured that died back in 2.6.2x when the old ppc board got removed, and it never even crossed my mind to git grep for it. Funny that some automated orphan CONFIG_ checker script didn't find it (assuming there is one.) Thanks, Paul. -- obj-$(CONFIG_MTD_DMV182) += dmv182.o obj-$(CONFIG_MTD_PLATRAM) += plat-ram.o obj-$(CONFIG_MTD_INTEL_VR_NOR) += intel_vr_nor.o I've amended the patch and pushed to l2-mtd.git tree, thanks! ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH -V1 1/9] arch/powerpc: Use hpt_va to compute virtual address
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com Don't open code the same Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com --- arch/powerpc/platforms/cell/beat_htab.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/platforms/cell/beat_htab.c b/arch/powerpc/platforms/cell/beat_htab.c index 943c9d3..b83077e 100644 --- a/arch/powerpc/platforms/cell/beat_htab.c +++ b/arch/powerpc/platforms/cell/beat_htab.c @@ -259,7 +259,7 @@ static void beat_lpar_hpte_updateboltedpp(unsigned long newpp, u64 dummy0, dummy1; vsid = get_kernel_vsid(ea, MMU_SEGSIZE_256M); - va = (vsid 28) | (ea 0x0fff); + va = hpt_va(ea, vsid, MMU_SEGSIZE_256M); raw_spin_lock(beat_htab_lock); slot = beat_lpar_hpte_find(va, psize); -- 1.7.10 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH -V1 2/9] arch/powerpc: Convert virtual address to a struct
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This is in preparation to the conversion of 64 bit powerpc virtual address
to the max 78 bits. Later patch will switch struct virt_addr to a struct
of virtual segment id and segment offset.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/kvm_book3s.h |2 +-
arch/powerpc/include/asm/machdep.h |6 +--
arch/powerpc/include/asm/mmu-hash64.h | 24 ++
arch/powerpc/include/asm/tlbflush.h |4 +-
arch/powerpc/kvm/book3s_64_mmu_host.c |3 +-
arch/powerpc/mm/hash_native_64.c| 76 +--
arch/powerpc/mm/hash_utils_64.c | 12 ++---
arch/powerpc/mm/hugetlbpage-hash64.c|3 +-
arch/powerpc/mm/tlb_hash64.c|3 +-
arch/powerpc/platforms/cell/beat_htab.c | 17 +++
arch/powerpc/platforms/ps3/htab.c |6 +--
arch/powerpc/platforms/pseries/lpar.c | 30 ++--
12 files changed, 103 insertions(+), 83 deletions(-)
diff --git a/arch/powerpc/include/asm/kvm_book3s.h
b/arch/powerpc/include/asm/kvm_book3s.h
index fd07f43..374b75d 100644
--- a/arch/powerpc/include/asm/kvm_book3s.h
+++ b/arch/powerpc/include/asm/kvm_book3s.h
@@ -59,7 +59,7 @@ struct hpte_cache {
struct hlist_node list_vpte;
struct hlist_node list_vpte_long;
struct rcu_head rcu_head;
- u64 host_va;
+ struct virt_addr host_va;
u64 pfn;
ulong slot;
struct kvmppc_pte pte;
diff --git a/arch/powerpc/include/asm/machdep.h
b/arch/powerpc/include/asm/machdep.h
index 42ce570..b34d0a9 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -34,19 +34,19 @@ struct machdep_calls {
char*name;
#ifdef CONFIG_PPC64
void(*hpte_invalidate)(unsigned long slot,
- unsigned long va,
+ struct virt_addr va,
int psize, int ssize,
int local);
long(*hpte_updatepp)(unsigned long slot,
unsigned long newpp,
-unsigned long va,
+struct virt_addr va,
int psize, int ssize,
int local);
void(*hpte_updateboltedpp)(unsigned long newpp,
unsigned long ea,
int psize, int ssize);
long(*hpte_insert)(unsigned long hpte_group,
- unsigned long va,
+ struct virt_addr va,
unsigned long prpn,
unsigned long rflags,
unsigned long vflags,
diff --git a/arch/powerpc/include/asm/mmu-hash64.h
b/arch/powerpc/include/asm/mmu-hash64.h
index 1c65a59..5ff936b 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -143,6 +143,10 @@ struct mmu_psize_def
unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */
};
+struct virt_addr {
+ unsigned long addr;
+};
+
#endif /* __ASSEMBLY__ */
/*
@@ -183,11 +187,11 @@ extern int mmu_ci_restrictions;
* This function sets the AVPN and L fields of the HPTE appropriately
* for the page size
*/
-static inline unsigned long hpte_encode_v(unsigned long va, int psize,
+static inline unsigned long hpte_encode_v(struct virt_addr va, int psize,
int ssize)
{
unsigned long v;
- v = (va 23) ~(mmu_psize_defs[psize].avpnm);
+ v = (va.addr 23) ~(mmu_psize_defs[psize].avpnm);
v = HPTE_V_AVPN_SHIFT;
if (psize != MMU_PAGE_4K)
v |= HPTE_V_LARGE;
@@ -218,28 +222,30 @@ static inline unsigned long hpte_encode_r(unsigned long
pa, int psize)
/*
* Build a VA given VSID, EA and segment size
*/
-static inline unsigned long hpt_va(unsigned long ea, unsigned long vsid,
+static inline struct virt_addr hpt_va(unsigned long ea, unsigned long vsid,
int ssize)
{
+ struct virt_addr va;
if (ssize == MMU_SEGSIZE_256M)
- return (vsid 28) | (ea 0xfffUL);
- return (vsid 40) | (ea 0xffUL);
+ va.addr = (vsid 28) | (ea 0xfffUL);
+ va.addr = (vsid 40) | (ea 0xffUL);
+ return va;
}
/*
* This hashes a virtual address
*/
-static inline unsigned long hpt_hash(unsigned long va, unsigned int shift,
+static inline unsigned long hpt_hash(struct virt_addr va, unsigned int shift,
int ssize)
{
unsigned
[PATCH -V1 0/9] arch/powerpc: Add 64TB support to ppc64
Hi, This patchset include patches for supporting 64TB with ppc64. I haven't booted this on hardware with 64TB memory yet. But they boot fine on real hardware with less memory. Changes extend VSID bits to 38 bits for a 256MB segment and 26 bits for 1TB segments. The patches are not for inclusion. I have few Verify tags in the patches for which I would like closer review. Thanks, -aneesh ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH -V1 4/9] arch/powerpc: Use vsid and segment offset to represent virtual address
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This patch enables us to have 78 bit virtual address.
With 1TB segments we use 40 bits of virtual adress as segment offset and
the remaining 24 bits (of the current 64 bit virtual address) are used
to index the virtual segment. Out of the 24 bits we currently use 19 bits
for user context and that leave us with only 4 bits for effective segment
ID. In-order to support more than 16TB of memory we would require more than
4 ESID bits. This patch splits the virtual address to two unsigned long
components, vsid and segment offset thereby allowing us to support 78 bit
virtual address.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/mmu-hash64.h | 62 ---
arch/powerpc/mm/hash_low_64.S | 191 ++---
arch/powerpc/mm/hash_native_64.c | 36 ---
arch/powerpc/mm/hash_utils_64.c |6 +-
arch/powerpc/platforms/ps3/htab.c | 13 +--
arch/powerpc/platforms/pseries/lpar.c | 29 ++---
6 files changed, 192 insertions(+), 145 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-hash64.h
b/arch/powerpc/include/asm/mmu-hash64.h
index 5ff936b..e48c66b 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -143,8 +143,10 @@ struct mmu_psize_def
unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */
};
+/* 78 bit power virtual address */
struct virt_addr {
- unsigned long addr;
+ unsigned long vsid;
+ unsigned long seg_off;
};
#endif /* __ASSEMBLY__ */
@@ -161,6 +163,13 @@ struct virt_addr {
#ifndef __ASSEMBLY__
+static inline int segment_shift(int ssize)
+{
+ if (ssize == MMU_SEGSIZE_256M)
+ return SID_SHIFT;
+ return SID_SHIFT_1T;
+}
+
/*
* The current system page and segment sizes
*/
@@ -184,6 +193,32 @@ extern unsigned long tce_alloc_start, tce_alloc_end;
extern int mmu_ci_restrictions;
/*
+ * This computes the AVPN and B fields of the first dword of a HPTE,
+ * for use when we want to match an existing PTE. The bottom 7 bits
+ * of the returned value are zero.
+ */
+static inline unsigned long hpte_encode_avpn(struct virt_addr va, int psize,
+int ssize)
+{
+ unsigned long v;
+
+ /*
+* The AVA field omits the low-order 23 bits of the 78 bits VA.
+* These bits are not needed in the PTE, because the
+* low-order b of these bits are part of the byte offset
+* into the virtual page and, if b 23, the high-order
+* 23-b of these bits are always used in selecting the
+* PTEGs to be searched
+*/
+ v = va.seg_off 23;
+ v |= va.vsid (segment_shift(ssize) - 23);
+ v = ~(mmu_psize_defs[psize].avpnm);
+ v = HPTE_V_AVPN_SHIFT;
+ v |= ((unsigned long) ssize) HPTE_V_SSIZE_SHIFT;
+ return v;
+}
+
+/*
* This function sets the AVPN and L fields of the HPTE appropriately
* for the page size
*/
@@ -191,11 +226,9 @@ static inline unsigned long hpte_encode_v(struct virt_addr
va, int psize,
int ssize)
{
unsigned long v;
- v = (va.addr 23) ~(mmu_psize_defs[psize].avpnm);
- v = HPTE_V_AVPN_SHIFT;
+ v = hpte_encode_avpn(va, psize, ssize);
if (psize != MMU_PAGE_4K)
v |= HPTE_V_LARGE;
- v |= ((unsigned long) ssize) HPTE_V_SSIZE_SHIFT;
return v;
}
@@ -222,30 +255,31 @@ static inline unsigned long hpte_encode_r(unsigned long
pa, int psize)
/*
* Build a VA given VSID, EA and segment size
*/
-static inline struct virt_addr hpt_va(unsigned long ea, unsigned long vsid,
- int ssize)
+static inline struct virt_addr hpt_va(unsigned long ea, unsigned long vsid,
int ssize)
{
struct virt_addr va;
+
+ va.vsid= vsid;
if (ssize == MMU_SEGSIZE_256M)
- va.addr = (vsid 28) | (ea 0xfffUL);
- va.addr = (vsid 40) | (ea 0xffUL);
+ va.seg_off = ea 0xfffUL;
+ else
+ va.seg_off = ea 0xffUL;
return va;
}
/*
* This hashes a virtual address
*/
-
-static inline unsigned long hpt_hash(struct virt_addr va, unsigned int shift,
-int ssize)
+/* Verify */
+static inline unsigned long hpt_hash(struct virt_addr va, unsigned int shift,
int ssize)
{
unsigned long hash, vsid;
if (ssize == MMU_SEGSIZE_256M) {
- hash = (va.addr 28) ^ ((va.addr 0x0fffUL) shift);
+ hash = (va.vsid 0x007f) ^ (va.seg_off shift);
} else {
- vsid = va.addr 40;
- hash = vsid ^ (vsid 25) ^ ((va.addr 0xffUL)
shift);
+ vsid = va.vsid;
+ hash = vsid ^ (vsid 25) ^ (va.seg_off shift);
}
[PATCH -V1 5/9] arch/powerpc: Make KERN_VIRT_SIZE not dependend on PGTABLE_RANGE
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com As we keep increasing PGTABLE_RANGE we need not increase the virual map area for kernel. Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com --- arch/powerpc/include/asm/pgtable-ppc64.h |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h index c420561..8af1cf2 100644 --- a/arch/powerpc/include/asm/pgtable-ppc64.h +++ b/arch/powerpc/include/asm/pgtable-ppc64.h @@ -41,7 +41,7 @@ #else #define KERN_VIRT_START ASM_CONST(0xD000) #endif -#define KERN_VIRT_SIZE PGTABLE_RANGE +#define KERN_VIRT_SIZE ASM_CONST(0x1000) /* * The vmalloc space starts at the beginning of that region, and -- 1.7.10 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH -V1 3/9] arch/powerpc: Simplify hpte_decode
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This patch simplify hpte_decode for easy switching of virtual address to
vsid and segment offset combination in the later patch
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/mm/hash_native_64.c | 51 ++
1 file changed, 30 insertions(+), 21 deletions(-)
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index cab3892..76c2574 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -357,9 +357,10 @@ static void native_hpte_invalidate(unsigned long slot,
struct virt_addr va,
static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
int *psize, int *ssize, struct virt_addr *va)
{
+ unsigned long avpn, pteg, vpi;
unsigned long hpte_r = hpte-r;
unsigned long hpte_v = hpte-v;
- unsigned long avpn;
+ unsigned long vsid, seg_off;
int i, size, shift, penc;
if (!(hpte_v HPTE_V_LARGE))
@@ -386,32 +387,40 @@ static void hpte_decode(struct hash_pte *hpte, unsigned
long slot,
}
/* This works for all page sizes, and for 256M and 1T segments */
+ *ssize = hpte_v HPTE_V_SSIZE_SHIFT;
shift = mmu_psize_defs[size].shift;
- avpn = (HPTE_V_AVPN_VAL(hpte_v) ~mmu_psize_defs[size].avpnm) 23;
-
- if (shift 23) {
- unsigned long vpi, vsid, pteg;
- pteg = slot / HPTES_PER_GROUP;
- if (hpte_v HPTE_V_SECONDARY)
- pteg = ~pteg;
- switch (hpte_v HPTE_V_SSIZE_SHIFT) {
- case MMU_SEGSIZE_256M:
- vpi = ((avpn 28) ^ pteg) htab_hash_mask;
- break;
- case MMU_SEGSIZE_1T:
- vsid = avpn 40;
+ avpn = (HPTE_V_AVPN_VAL(hpte_v) ~mmu_psize_defs[size].avpnm);
+ pteg = slot / HPTES_PER_GROUP;
+ if (hpte_v HPTE_V_SECONDARY)
+ pteg = ~pteg;
+
+ switch (*ssize) {
+ case MMU_SEGSIZE_256M:
+ /* We only have 28 - 23 bits of seg_off in avpn */
+ seg_off = (avpn 0x1f) 23;
+ vsid= avpn 5;
+ /* We can find more bits from the pteg value */
+ if (shift 23) {
+ vpi = (vsid ^ pteg) htab_hash_mask;
+ seg_off |= vpi shift;
+ }
+ va-addr = vsid 28 | seg_off;
+ case MMU_SEGSIZE_1T:
+ /* We only have 40 - 23 bits of seg_off in avpn */
+ seg_off = (avpn 0x1) 23;
+ vsid= avpn 17;
+ if (shift 23) {
vpi = (vsid ^ (vsid 25) ^ pteg) htab_hash_mask;
- break;
- default:
- avpn = vpi = size = 0;
+ seg_off |= vpi shift;
}
- avpn |= (vpi mmu_psize_defs[size].shift);
+ va-addr = vsid 40 | seg_off;
+ default:
+ seg_off = 0;
+ vsid= 0;
+ va-addr = 0;
}
-
- va-addr = avpn;
*psize = size;
- *ssize = hpte_v HPTE_V_SSIZE_SHIFT;
}
/*
--
1.7.10
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[PATCH -V1 6/9] arch/powerpc: Increase the slice range to 64TB
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This patch makes the high psizes mask as an unsigned char array
so that we can have more than 16TB. Currently we support upto
64TB
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/mmu-hash64.h |7 ++-
arch/powerpc/include/asm/page_64.h|7 ++-
arch/powerpc/mm/hash_utils_64.c | 15 +++---
arch/powerpc/mm/slb_low.S | 35
arch/powerpc/mm/slice.c | 95 +
5 files changed, 109 insertions(+), 50 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-hash64.h
b/arch/powerpc/include/asm/mmu-hash64.h
index e48c66b..47ddfa1 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -456,7 +456,12 @@ typedef struct {
#ifdef CONFIG_PPC_MM_SLICES
u64 low_slices_psize; /* SLB page size encodings */
- u64 high_slices_psize; /* 4 bits per slice for now */
+ /*
+* FIXME!! it should be derived from PGTABLE_RANGE
+* Right now we support 64TB and 4 bits for each
+* 1TB slice we need 32 bytes for 64TB.
+*/
+ unsigned char high_slices_psize[32]; /* 4 bits per slice for now */
#else
u16 sllp; /* SLB page size encoding */
#endif
diff --git a/arch/powerpc/include/asm/page_64.h
b/arch/powerpc/include/asm/page_64.h
index fed85e6..8806e87 100644
--- a/arch/powerpc/include/asm/page_64.h
+++ b/arch/powerpc/include/asm/page_64.h
@@ -82,7 +82,12 @@ extern u64 ppc64_pft_size;
struct slice_mask {
u16 low_slices;
- u16 high_slices;
+ /*
+* FIXME!!
+* This should be derived out of PGTABLE_RANGE. For the current
+* max 64TB, u64 should be ok.
+*/
+ u64 high_slices;
};
struct mm_struct;
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 8b5d3c2..beace0b 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -804,16 +804,19 @@ unsigned int hash_page_do_lazy_icache(unsigned int pp,
pte_t pte, int trap)
#ifdef CONFIG_PPC_MM_SLICES
unsigned int get_paca_psize(unsigned long addr)
{
- unsigned long index, slices;
+ u64 lpsizes;
+ unsigned char *hpsizes;
+ unsigned long index, mask_index;
if (addr SLICE_LOW_TOP) {
- slices = get_paca()-context.low_slices_psize;
+ lpsizes = get_paca()-context.low_slices_psize;
index = GET_LOW_SLICE_INDEX(addr);
- } else {
- slices = get_paca()-context.high_slices_psize;
- index = GET_HIGH_SLICE_INDEX(addr);
+ return (lpsizes (index * 4)) 0xF;
}
- return (slices (index * 4)) 0xF;
+ hpsizes = get_paca()-context.high_slices_psize;
+ index = GET_HIGH_SLICE_INDEX(addr) 1;
+ mask_index = GET_HIGH_SLICE_INDEX(addr) - (index 1);
+ return (hpsizes[index] (mask_index * 4)) 0xF;
}
#else
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index b9ee79ce..c355af6 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -108,17 +108,34 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
* between 4k and 64k standard page size
*/
#ifdef CONFIG_PPC_MM_SLICES
+ /* r10 have esid */
cmpldi r10,16
-
- /* Get the slice index * 4 in r11 and matching slice size mask in r9 */
- ld r9,PACALOWSLICESPSIZE(r13)
- sldir11,r10,2
+ /* below SLICE_LOW_TOP */
blt 5f
- ld r9,PACAHIGHSLICEPSIZE(r13)
- srdir11,r10,(SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT - 2)
- andi. r11,r11,0x3c
-
-5: /* Extract the psize and multiply to get an array offset */
+ /*
+* Handle hpsizes,
+* r9 is get_paca()-context.high_slices_psize[index], r11 is mask_index
+* We use r10 here, later we restore it to esid.
+* Can we use other register instead of r10 ?
+*/
+ srdir10,r10,(SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT) /* index */
+ srdir11,r10,1 /* r11 is array index */
+ addir9,r11,PACAHIGHSLICEPSIZE
+ lbzxr9,r9,r13 /* r9 is hpsizes[r11] */
+ sldir11,r11,1
+ subfr11,r11,r10 /* mask_index = index - (array_index 1) */
+ srdir10,r3,28 /* restore r10 with esid */
+ b 6f
+5:
+ /*
+* Handle lpsizes
+* r9 is get_paca()-context.low_slices_psize, r11 is index
+*/
+ ld r9,PACALOWSLICESPSIZE(r13)
+ mr r11,r10
+6:
+ sldir11,r11,2 /* index * 4 */
+ /* Extract the psize and multiply to get an array offset */
srd r9,r9,r11
andi. r9,r9,0xf
mulli r9,r9,MMUPSIZEDEFSIZE
diff --git a/arch/powerpc/mm/slice.c b/arch/powerpc/mm/slice.c
index 73709f7..302a481 100644
---
[PATCH -V1 7/9] arch/powerpc: Use 50 bits of VSID in slbmte
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com Increase the number of valid VSID bits in slbmte instruction. We will use the new bits when we increase valid VSID bits. Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com --- arch/powerpc/mm/slb_low.S |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S index c355af6..c1fc81c 100644 --- a/arch/powerpc/mm/slb_low.S +++ b/arch/powerpc/mm/slb_low.S @@ -226,7 +226,7 @@ _GLOBAL(slb_allocate_user) */ slb_finish_load: ASM_VSID_SCRAMBLE(r10,r9,256M) - rldimi r11,r10,SLB_VSID_SHIFT,16 /* combine VSID and flags */ + rldimi r11,r10,SLB_VSID_SHIFT,2/* combine VSID and flags */ /* r3 = EA, r11 = VSID data */ /* @@ -290,7 +290,7 @@ _GLOBAL(slb_compare_rr_to_size) slb_finish_load_1T: srdir10,r10,40-28 /* get 1T ESID */ ASM_VSID_SCRAMBLE(r10,r9,1T) - rldimi r11,r10,SLB_VSID_SHIFT_1T,16/* combine VSID and flags */ + rldimi r11,r10,SLB_VSID_SHIFT_1T,2 /* combine VSID and flags */ li r10,MMU_SEGSIZE_1T rldimi r11,r10,SLB_VSID_SSIZE_SHIFT,0 /* insert segment size */ -- 1.7.10 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH -V1 8/9] arch/powerpc: Use 32bit array for slb cache
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
With larger vsid we need to track more bits of ESID in slb cache
for slb invalidate.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/paca.h |2 +-
arch/powerpc/mm/slb_low.S |8
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index daf813f..3e7abba 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -100,7 +100,7 @@ struct paca_struct {
/* SLB related definitions */
u16 vmalloc_sllp;
u16 slb_cache_ptr;
- u16 slb_cache[SLB_CACHE_ENTRIES];
+ u32 slb_cache[SLB_CACHE_ENTRIES];
#endif /* CONFIG_PPC_STD_MMU_64 */
#ifdef CONFIG_PPC_BOOK3E
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index c1fc81c..d522679 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -269,10 +269,10 @@ _GLOBAL(slb_compare_rr_to_size)
bge 1f
/* still room in the slb cache */
- sldir11,r3,1/* r11 = offset * sizeof(u16) */
- rldicl r10,r10,36,28 /* get low 16 bits of the ESID */
- add r11,r11,r13 /* r11 = (u16 *)paca + offset */
- sth r10,PACASLBCACHE(r11) /* paca-slb_cache[offset] = esid */
+ sldir11,r3,2/* r11 = offset * sizeof(u32) */
+ rldicl r10,r10,36,28 /* get the 36 bits of the ESID */
+ add r11,r11,r13 /* r11 = (u32 *)paca + offset */
+ stw r10,PACASLBCACHE(r11) /* paca-slb_cache[offset] = esid */
addir3,r3,1 /* offset++ */
b 2f
1: /* offset = SLB_CACHE_ENTRIES */
--
1.7.10
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[PATCH -V1 9/9] arch/powerpc: Add 64TB support
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com Increase max addressable range to 64TB. This is not tested on real hardware yet. Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com --- arch/powerpc/include/asm/mmu-hash64.h|8 arch/powerpc/include/asm/pgtable-ppc64-4k.h |2 +- arch/powerpc/include/asm/pgtable-ppc64-64k.h |2 +- arch/powerpc/include/asm/processor.h |4 ++-- arch/powerpc/include/asm/sparsemem.h |4 ++-- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h index 47ddfa1..bf042ba 100644 --- a/arch/powerpc/include/asm/mmu-hash64.h +++ b/arch/powerpc/include/asm/mmu-hash64.h @@ -367,16 +367,16 @@ extern void slb_set_size(u16 size); */ #define VSID_MULTIPLIER_256M ASM_CONST(200730139)/* 28-bit prime */ -#define VSID_BITS_256M 36 +#define VSID_BITS_256M 38 #define VSID_MODULUS_256M ((1ULVSID_BITS_256M)-1) #define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */ -#define VSID_BITS_1T 24 +#define VSID_BITS_1T 26 #define VSID_MODULUS_1T((1ULVSID_BITS_1T)-1) #define CONTEXT_BITS 19 -#define USER_ESID_BITS 16 -#define USER_ESID_BITS_1T 4 +#define USER_ESID_BITS 18 +#define USER_ESID_BITS_1T 6 #define USER_VSID_RANGE(1UL (USER_ESID_BITS + SID_SHIFT)) diff --git a/arch/powerpc/include/asm/pgtable-ppc64-4k.h b/arch/powerpc/include/asm/pgtable-ppc64-4k.h index 6eefdcf..b3eccf2 100644 --- a/arch/powerpc/include/asm/pgtable-ppc64-4k.h +++ b/arch/powerpc/include/asm/pgtable-ppc64-4k.h @@ -7,7 +7,7 @@ */ #define PTE_INDEX_SIZE 9 #define PMD_INDEX_SIZE 7 -#define PUD_INDEX_SIZE 7 +#define PUD_INDEX_SIZE 9 #define PGD_INDEX_SIZE 9 #ifndef __ASSEMBLY__ diff --git a/arch/powerpc/include/asm/pgtable-ppc64-64k.h b/arch/powerpc/include/asm/pgtable-ppc64-64k.h index 90533dd..be4e287 100644 --- a/arch/powerpc/include/asm/pgtable-ppc64-64k.h +++ b/arch/powerpc/include/asm/pgtable-ppc64-64k.h @@ -7,7 +7,7 @@ #define PTE_INDEX_SIZE 12 #define PMD_INDEX_SIZE 12 #define PUD_INDEX_SIZE 0 -#define PGD_INDEX_SIZE 4 +#define PGD_INDEX_SIZE 6 #ifndef __ASSEMBLY__ #define PTE_TABLE_SIZE (sizeof(real_pte_t) PTE_INDEX_SIZE) diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 8e2d037..426ed13 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -100,8 +100,8 @@ extern struct task_struct *last_task_used_spe; #endif #ifdef CONFIG_PPC64 -/* 64-bit user address space is 44-bits (16TB user VM) */ -#define TASK_SIZE_USER64 (0x1000UL) +/* 64-bit user address space is 46-bits (64TB user VM) */ +#define TASK_SIZE_USER64 (0x4000UL) /* * 32-bit user address space is 4GB - 1 page diff --git a/arch/powerpc/include/asm/sparsemem.h b/arch/powerpc/include/asm/sparsemem.h index 0c5fa31..f6fc0ee 100644 --- a/arch/powerpc/include/asm/sparsemem.h +++ b/arch/powerpc/include/asm/sparsemem.h @@ -10,8 +10,8 @@ */ #define SECTION_SIZE_BITS 24 -#define MAX_PHYSADDR_BITS 44 -#define MAX_PHYSMEM_BITS44 +#define MAX_PHYSADDR_BITS 46 +#define MAX_PHYSMEM_BITS46 #endif /* CONFIG_SPARSEMEM */ -- 1.7.10 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v6 1/5] powerpc/85xx: implement hardware timebase sync
On Tue, Jun 26, 2012 at 5:25 AM, Zhao Chenhui
chenhui.z...@freescale.com wrote:
Do hardware timebase sync. Firstly, stop all timebases, and transfer
the timebase value of the boot core to the other core. Finally,
start all timebases.
Only apply to dual-core chips, such as MPC8572, P2020, etc.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
Changes for v6:
* added 85xx_TB_SYNC
* added isync() after set_tb()
* removed extra entries from mpc85xx_smp_guts_ids
arch/powerpc/include/asm/fsl_guts.h | 2 +
arch/powerpc/platforms/85xx/Kconfig | 5 ++
arch/powerpc/platforms/85xx/smp.c | 84
+++
3 files changed, 91 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_guts.h
b/arch/powerpc/include/asm/fsl_guts.h
index aa4c488..dd5ba2c 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -48,6 +48,8 @@ struct ccsr_guts {
__be32 dmuxcr; /* 0x.0068 - DMA Mux Control Register
*/
u8 res06c[0x70 - 0x6c];
__be32 devdisr; /* 0x.0070 - Device Disable Control */
+#define CCSR_GUTS_DEVDISR_TB1 0x1000
+#define CCSR_GUTS_DEVDISR_TB0 0x4000
__be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
u8 res078[0x7c - 0x78];
__be32 pmjcr; /* 0x.007c - 4 Power Management Jog Control
Register */
diff --git a/arch/powerpc/platforms/85xx/Kconfig
b/arch/powerpc/platforms/85xx/Kconfig
index f000d81..8dd7147 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -8,6 +8,7 @@ menuconfig FSL_SOC_BOOKE
select FSL_PCI if PCI
select SERIAL_8250_EXTENDED if SERIAL_8250
select SERIAL_8250_SHARE_IRQ if SERIAL_8250
+ select 85xx_TB_SYNC if KEXEC
default y
if FSL_SOC_BOOKE
@@ -267,3 +268,7 @@ endif # FSL_SOC_BOOKE
config TQM85xx
bool
+
+config 85xx_TB_SYNC
+ bool
+ default n
diff --git a/arch/powerpc/platforms/85xx/smp.c
b/arch/powerpc/platforms/85xx/smp.c
index ff42490..edb0cad 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -24,6 +24,7 @@
#include asm/mpic.h
#include asm/cacheflush.h
#include asm/dbell.h
+#include asm/fsl_guts.h
#include sysdev/fsl_soc.h
#include sysdev/mpic.h
@@ -42,6 +43,69 @@ extern void __early_start(void);
#define NUM_BOOT_ENTRY 8
#define SIZE_BOOT_ENTRY (NUM_BOOT_ENTRY * sizeof(u32))
+#ifdef CONFIG_85xx_TB_SYNC
+static struct ccsr_guts __iomem *guts;
+static u64 timebase;
+static int tb_req;
+static int tb_valid;
+
+static void mpc85xx_timebase_freeze(int freeze)
+{
+ unsigned int mask;
'mask' should be uint32_t
+
+ if (!guts)
+ return;
This function should never be called if guts is NULL, so this check
should be unnecessary.
+
+ mask = CCSR_GUTS_DEVDISR_TB0 | CCSR_GUTS_DEVDISR_TB1;
+ if (freeze)
+ setbits32(guts-devdisr, mask);
+ else
+ clrbits32(guts-devdisr, mask);
+
+ in_be32(guts-devdisr);
+}
+
+static void mpc85xx_give_timebase(void)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+
+ while (!tb_req)
+ barrier();
I think tb_req and tb_valid need to be 'volatile'.
+ tb_req = 0;
+
+ mpc85xx_timebase_freeze(1);
+ timebase = get_tb();
+ mb();
+ tb_valid = 1;
+
+ while (tb_valid)
+ barrier();
+
+ mpc85xx_timebase_freeze(0);
+
+ local_irq_restore(flags);
+}
+
+static void mpc85xx_take_timebase(void)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+
+ tb_req = 1;
+ while (!tb_valid)
+ barrier();
+
+ set_tb(timebase 32, timebase 0x);
+ isync();
+ tb_valid = 0;
+
+ local_irq_restore(flags);
+}
+#endif
+
static int __init
smp_85xx_kick_cpu(int nr)
{
@@ -228,6 +292,16 @@ smp_85xx_setup_cpu(int cpu_nr)
doorbell_setup_this_cpu();
}
+static const struct of_device_id mpc85xx_smp_guts_ids[] = {
+ { .compatible = fsl,mpc8572-guts, },
+ { .compatible = fsl,p1020-guts, },
+ { .compatible = fsl,p1021-guts, },
+ { .compatible = fsl,p1022-guts, },
+ { .compatible = fsl,p1023-guts, },
+ { .compatible = fsl,p2020-guts, },
+ {},
+};
I wonder if it's possible to dynamically generate the compatible
string by using the SOC name?
+
void __init mpc85xx_smp_init(void)
{
struct device_node *np;
@@ -249,6 +323,16 @@ void __init mpc85xx_smp_init(void)
smp_85xx_ops.cause_ipi = doorbell_cause_ipi;
}
+ np = of_find_matching_node(NULL, mpc85xx_smp_guts_ids);
+ if (np) {
+#ifdef CONFIG_85xx_TB_SYNC
+
Re: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt platform
On Jun 28, 2012, at 9:36 PM, Jia Hongtao-B38951 wrote: -Original Message- From: Wood Scott-B07421 Sent: Friday, June 29, 2012 12:31 AM To: Jia Hongtao-B38951 Cc: Wood Scott-B07421; ga...@kernel.crashing.org; Li Yang-R58472; ag...@suse.de; linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt platform On 06/27/2012 11:06 PM, Jia Hongtao-B38951 wrote: -Original Message- From: Wood Scott-B07421 Sent: Thursday, June 28, 2012 7:49 AM To: ga...@kernel.crashing.org Cc: ag...@suse.de; linuxppc-dev@lists.ozlabs.org; Jia Hongtao-B38951 Subject: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt platform The QEMU stuff is related to the PCI refactoring because currently we have a hard time selecting a primary bus under QEMU, and also because the generic qemu e500 platform wants a full list of FSL PCI compatibles to check. It seems that not all primary bus has isa node like 8541 and 8555. Do those boards (it's the boards that matter, not chips...) have legacy ISA? If they do, and it's not in the device tree, then we should fix the device tree for consistency, but also retain some sort of hack to remain compatible with old device trees. A board can refrain from using the new common infrastructure if it has a good reason to. I'm not sure that MPC8541CDS (or 8555) has legacy ISA. I just checked in kernel and dts which implies the board has primary bus and no isa node. I will find out the facts later. Pretty sure the boards have ISA, if you see the .dts has references to 'ISA bridge' 'i8259' PIC. - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt platform
On 06/29/2012 10:57 AM, Kumar Gala wrote: On Jun 28, 2012, at 9:36 PM, Jia Hongtao-B38951 wrote: -Original Message- From: Wood Scott-B07421 Sent: Friday, June 29, 2012 12:31 AM To: Jia Hongtao-B38951 Cc: Wood Scott-B07421; ga...@kernel.crashing.org; Li Yang-R58472; ag...@suse.de; linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt platform On 06/27/2012 11:06 PM, Jia Hongtao-B38951 wrote: -Original Message- From: Wood Scott-B07421 Sent: Thursday, June 28, 2012 7:49 AM To: ga...@kernel.crashing.org Cc: ag...@suse.de; linuxppc-dev@lists.ozlabs.org; Jia Hongtao-B38951 Subject: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt platform The QEMU stuff is related to the PCI refactoring because currently we have a hard time selecting a primary bus under QEMU, and also because the generic qemu e500 platform wants a full list of FSL PCI compatibles to check. It seems that not all primary bus has isa node like 8541 and 8555. Do those boards (it's the boards that matter, not chips...) have legacy ISA? If they do, and it's not in the device tree, then we should fix the device tree for consistency, but also retain some sort of hack to remain compatible with old device trees. A board can refrain from using the new common infrastructure if it has a good reason to. I'm not sure that MPC8541CDS (or 8555) has legacy ISA. I just checked in kernel and dts which implies the board has primary bus and no isa node. I will find out the facts later. Pretty sure the boards have ISA, if you see the .dts has references to 'ISA bridge' 'i8259' PIC. OK. How about looking for an i8259 node as well? -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v6 1/5] powerpc/85xx: implement hardware timebase sync
On 06/29/2012 10:39 AM, Tabi Timur-B04825 wrote:
On Tue, Jun 26, 2012 at 5:25 AM, Zhao Chenhui
chenhui.z...@freescale.com wrote:
+static void mpc85xx_give_timebase(void)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+
+ while (!tb_req)
+ barrier();
I think tb_req and tb_valid need to be 'volatile'.
No, barrier() and mb() take care of that.
+static const struct of_device_id mpc85xx_smp_guts_ids[] = {
+ { .compatible = fsl,mpc8572-guts, },
+ { .compatible = fsl,p1020-guts, },
+ { .compatible = fsl,p1021-guts, },
+ { .compatible = fsl,p1022-guts, },
+ { .compatible = fsl,p1023-guts, },
+ { .compatible = fsl,p2020-guts, },
+ {},
+};
I wonder if it's possible to dynamically generate the compatible
string by using the SOC name?
Where are you going to get the SoC name from?
-Scott
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Re: [PATCH v6 1/5] powerpc/85xx: implement hardware timebase sync
Scott Wood wrote: I wonder if it's possible to dynamically generate the compatible string by using the SOC name? Where are you going to get the SoC name from? Well, that is why I said I wonder. I'm disappointed that the cpus node doesn't help much. You'd think the name of the CPU would be in the CPU node somewhere. -- Timur Tabi Linux kernel developer at Freescale ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt platform
On Jun 29, 2012, at 11:01 AM, Scott Wood wrote: On 06/29/2012 10:57 AM, Kumar Gala wrote: On Jun 28, 2012, at 9:36 PM, Jia Hongtao-B38951 wrote: -Original Message- From: Wood Scott-B07421 Sent: Friday, June 29, 2012 12:31 AM To: Jia Hongtao-B38951 Cc: Wood Scott-B07421; ga...@kernel.crashing.org; Li Yang-R58472; ag...@suse.de; linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt platform On 06/27/2012 11:06 PM, Jia Hongtao-B38951 wrote: -Original Message- From: Wood Scott-B07421 Sent: Thursday, June 28, 2012 7:49 AM To: ga...@kernel.crashing.org Cc: ag...@suse.de; linuxppc-dev@lists.ozlabs.org; Jia Hongtao-B38951 Subject: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt platform The QEMU stuff is related to the PCI refactoring because currently we have a hard time selecting a primary bus under QEMU, and also because the generic qemu e500 platform wants a full list of FSL PCI compatibles to check. It seems that not all primary bus has isa node like 8541 and 8555. Do those boards (it's the boards that matter, not chips...) have legacy ISA? If they do, and it's not in the device tree, then we should fix the device tree for consistency, but also retain some sort of hack to remain compatible with old device trees. A board can refrain from using the new common infrastructure if it has a good reason to. I'm not sure that MPC8541CDS (or 8555) has legacy ISA. I just checked in kernel and dts which implies the board has primary bus and no isa node. I will find out the facts later. Pretty sure the boards have ISA, if you see the .dts has references to 'ISA bridge' 'i8259' PIC. OK. How about looking for an i8259 node as well? -Scott Works for me, saves us having to waste time on figuring out how to update .dts for the boards. - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt platform
-Original Message- From: Linuxppc-dev [mailto:linuxppc-dev-bounces+tie- fei.zang=freescale@lists.ozlabs.org] On Behalf Of Kumar Gala Sent: Friday, June 29, 2012 23:58 PM To: Jia Hongtao-B38951 Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; Li Yang-R58472; ag...@suse.de Subject: Re: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt platform On Jun 28, 2012, at 9:36 PM, Jia Hongtao-B38951 wrote: -Original Message- From: Wood Scott-B07421 Sent: Friday, June 29, 2012 12:31 AM To: Jia Hongtao-B38951 Cc: Wood Scott-B07421; ga...@kernel.crashing.org; Li Yang-R58472; ag...@suse.de; linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt platform On 06/27/2012 11:06 PM, Jia Hongtao-B38951 wrote: -Original Message- From: Wood Scott-B07421 Sent: Thursday, June 28, 2012 7:49 AM To: ga...@kernel.crashing.org Cc: ag...@suse.de; linuxppc-dev@lists.ozlabs.org; Jia Hongtao-B38951 Subject: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt platform The QEMU stuff is related to the PCI refactoring because currently we have a hard time selecting a primary bus under QEMU, and also because the generic qemu e500 platform wants a full list of FSL PCI compatibles to check. It seems that not all primary bus has isa node like 8541 and 8555. Do those boards (it's the boards that matter, not chips...) have legacy ISA? If they do, and it's not in the device tree, then we should fix the device tree for consistency, but also retain some sort of hack to remain compatible with old device trees. A board can refrain from using the new common infrastructure if it has a good reason to. I'm not sure that MPC8541CDS (or 8555) has legacy ISA. I just checked in kernel and dts which implies the board has primary bus and no isa node. I will find out the facts later. Pretty sure the boards have ISA, if you see the .dts has references to 'ISA bridge' 'i8259' PIC. It is on the VIA south bridge. Roy ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v6 1/5] powerpc/85xx: implement hardware timebase sync
On 06/29/2012 11:04 AM, Timur Tabi wrote: Scott Wood wrote: I wonder if it's possible to dynamically generate the compatible string by using the SOC name? Where are you going to get the SoC name from? Well, that is why I said I wonder. I'm disappointed that the cpus node doesn't help much. You'd think the name of the CPU would be in the CPU node somewhere. The SoC is not the CPU. The CPU is e500v2. Why is this different from anywhere else where we have a list of compatibles to match, often based on various SoCs? Note that we explicitly want to match only certain SoCs here. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v6 1/5] powerpc/85xx: implement hardware timebase sync
Scott Wood wrote: Why is this different from anywhere else where we have a list of compatibles to match, often based on various SoCs? Note that we explicitly want to match only certain SoCs here. I was just hoping to find a way to avoid an ever increasing list of compatible strings. Other posts on this thread imply that this code could work for all multi-core e500 parts. -- Timur Tabi Linux kernel developer at Freescale ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt platform
-Original Message- From: Wood Scott-B07421 Sent: Friday, June 29, 2012 11:02 AM To: Kumar Gala Cc: Jia Hongtao-B38951; Wood Scott-B07421; Li Yang-R58472; ag...@suse.de; linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt platform On 06/29/2012 10:57 AM, Kumar Gala wrote: On Jun 28, 2012, at 9:36 PM, Jia Hongtao-B38951 wrote: -Original Message- From: Wood Scott-B07421 Sent: Friday, June 29, 2012 12:31 AM To: Jia Hongtao-B38951 Cc: Wood Scott-B07421; ga...@kernel.crashing.org; Li Yang-R58472; ag...@suse.de; linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt platform On 06/27/2012 11:06 PM, Jia Hongtao-B38951 wrote: -Original Message- From: Wood Scott-B07421 Sent: Thursday, June 28, 2012 7:49 AM To: ga...@kernel.crashing.org Cc: ag...@suse.de; linuxppc-dev@lists.ozlabs.org; Jia Hongtao-B38951 Subject: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt platform The QEMU stuff is related to the PCI refactoring because currently we have a hard time selecting a primary bus under QEMU, and also because the generic qemu e500 platform wants a full list of FSL PCI compatibles to check. It seems that not all primary bus has isa node like 8541 and 8555. Do those boards (it's the boards that matter, not chips...) have legacy ISA? If they do, and it's not in the device tree, then we should fix the device tree for consistency, but also retain some sort of hack to remain compatible with old device trees. A board can refrain from using the new common infrastructure if it has a good reason to. I'm not sure that MPC8541CDS (or 8555) has legacy ISA. I just checked in kernel and dts which implies the board has primary bus and no isa node. I will find out the facts later. Pretty sure the boards have ISA, if you see the .dts has references to 'ISA bridge' 'i8259' PIC. OK. How about looking for an i8259 node as well? That could work, but looks hackish. Our proposal for adding a new device tree property is a generic solution. The only problem is that new kernels would work with old device trees. I think we can use your solution for transitional period. And go for a well defined device tree binding for this in long run. - Leo ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: Build regressions/improvements in v3.5-rc4
Hi Paul, On Thu, Jun 28, 2012 at 10:20 AM, Paul Mundt let...@linux-sh.org wrote: On Tue, Jun 26, 2012 at 10:06:27PM +0200, Geert Uytterhoeven wrote: On Tue, Jun 26, 2012 at 9:59 PM, Geert Uytterhoeven ge...@linux-m68k.org wrote: JFYI, when comparing v3.5-rc4 to v3.5-rc3[3], the summaries are: ??- build errors: +11/-219 11 regressions: + arch/sh/include/asm/fixmap.h: error: implicit declaration of function 'BUG_ON' [-Werror=implicit-function-declaration]: = 133:2 + arch/sh/include/asm/thread_info.h: error: implicit declaration of function 'WARN_ON' [-Werror=implicit-function-declaration]: = 172:2 + include/linux/huge_mm.h: error: implicit declaration of function 'BUG' [-Werror=implicit-function-declaration]: = 185:2 shmin_defconfig, se7712_defconfig, se7721_defconfig, sh-allnoconfig I'm unable to reproduce any of these, is there some specific compiler version or warning flag configuration I'm supposed to be using? I'm building with 4.5.1 at the moment. Mine (from Tony) is: sh4-linux-gcc -v Using built-in specs. COLLECT_GCC=/usr/local/gcc-4.6.3-nolibc/sh4-linux/bin/sh4-linux-gcc COLLECT_LTO_WRAPPER=/usr/local/gcc-4.6.3-nolibc/sh4-linux/bin/../libexec/gcc/sh4-linux/4.6.3/lto-wrapper Target: sh4-linux Configured with: /home/tony/buildall/src/gcc/configure --target=sh4-linux --host=x86_64-linux-gnu --build=x86_64-linux-gnu --enable-targets=all --prefix=/opt/cross/gcc-4.6.3-nolibc/sh4-linux/ --enable-languages=c --with-newlib --without-headers --disable-nls --disable-threads --disable-shared --disable-libmudflap --disable-libssp --disable-libgomp --disable-decimal-float --enable-checking=release --with-multilib-list=m4,m4-nofpu --with-mpfr=/home/tony/buildall/src/sys-x86_64 --with-gmp=/home/tony/buildall/src/sys-x86_64 --disable-bootstrap --disable-libquadmath Thread model: single gcc version 4.6.3 (GCC) Using v3.5-rc4: se7721_defconfig: sh4-linux-gcc -Wp,-MD,arch/sh/kernel/.asm-offsets.s.d -nostdinc -isystem /usr/local/gcc-4.6.3-nolibc/sh4-linux/bin/../lib/gcc/sh4-linux/4.6.3/include -Iarch/sh/include -Iarch/sh/include/generated -Iinclude -include include/linux/kconfig.h -D__KERNEL__ -m4-nofpu -ml -Wa,-isa=any -ffreestanding -Iarch/sh/include/cpu-sh3 -Iarch/sh/include/cpu-common -Iarch/sh/include/mach-se -Iarch/sh/include/mach-common -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs -fno-strict-aliasing -fno-common -Werror-implicit-function-declaration -Wno-format-security -fno-delete-null-pointer-checks -O2 -pipe -m4-nofpu -ml -Wa,-isa=any -ffreestanding -Iarch/sh/include/cpu-sh3 -Iarch/sh/include/cpu-common -Iarch/sh/include/mach-se -Iarch/sh/include/mach-common -Wframe-larger-than=1024 -fno-stack-protector -Wno-unused-but-set-variable -fno-omit-frame-pointer -fno-optimize-sibling-calls -g -Wdeclaration-after-statement -Wno-pointer-sign -fno-strict-overflow -fconserve-stack -DCC_HAVE_ASM_GOTO-DKBUILD_STR(s)=#s -DKBUILD_BASENAME=KBUILD_STR(asm_offsets) -DKBUILD_MODNAME=KBUILD_STR(asm_offsets) -fverbose-asm -S -o arch/sh/kernel/asm-offsets.s arch/sh/kernel/asm-offsets.c In file included from include/linux/thread_info.h:54:0, from include/linux/preempt.h:9, from include/linux/spinlock.h:50, from include/linux/mmzone.h:7, from include/linux/gfp.h:4, from include/linux/mm.h:8, from arch/sh/kernel/asm-offsets.c:13: arch/sh/include/asm/thread_info.h: In function 'set_restore_sigmask': arch/sh/include/asm/thread_info.h:172:2: error: implicit declaration of function 'WARN_ON' [-Werror=implicit-function-declaration] In file included from arch/sh/include/asm/pgtable.h:25:0, from include/linux/mm.h:44, from arch/sh/kernel/asm-offsets.c:13: arch/sh/include/asm/fixmap.h: In function 'virt_to_fix': arch/sh/include/asm/fixmap.h:133:2: error: implicit declaration of function 'BUG_ON' [-Werror=implicit-function-declaration] In file included from arch/sh/include/asm/pgtable.h:164:0, from include/linux/mm.h:44, from arch/sh/kernel/asm-offsets.c:13: include/asm-generic/pgtable.h: In function 'pmdp_test_and_clear_young': include/asm-generic/pgtable.h:56:2: error: implicit declaration of function 'BUG' [-Werror=implicit-function-declaration] cc1: some warnings being treated as errors make[1]: *** [arch/sh/kernel/asm-offsets.s] Error 1 allnoconfig: sh4-linux-gcc -Wp,-MD,arch/sh/kernel/.asm-offsets.s.d -nostdinc -isystem /usr/local/gcc-4.6.3-nolibc/sh4-linux/bin/../lib/gcc/sh4-linux/4.6.3/include -Iarch/sh/include -Iarch/sh/include/generated -Iinclude -include include/linux/kconfig.h -D__KERNEL__ -m4-nofpu -ml -Wa,-isa=any -ffreestanding -Iarch/sh/include/cpu-sh2 -Iarch/sh/include/cpu-common -Iarch/sh/include/mach-common -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs -fno-strict-aliasing -fno-common -Werror-implicit-function-declaration -Wno-format-security -fno-delete-null-pointer-checks -O2 -pipe -m4-nofpu -ml
Re: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt platform
On 06/29/2012 11:18 AM, Li Yang-R58472 wrote: -Original Message- From: Wood Scott-B07421 Sent: Friday, June 29, 2012 11:02 AM To: Kumar Gala Cc: Jia Hongtao-B38951; Wood Scott-B07421; Li Yang-R58472; ag...@suse.de; linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH 0/3] powerpc/fsl: PCI refactoring and QEMU paravirt platform On 06/29/2012 10:57 AM, Kumar Gala wrote: Pretty sure the boards have ISA, if you see the .dts has references to 'ISA bridge' 'i8259' PIC. OK. How about looking for an i8259 node as well? That could work, but looks hackish. Our proposal for adding a new device tree property is a generic solution. Yes, all *new* boards should have an isa node. But we want to remain compatible with existing device trees. The only problem is that new kernels would work with old device trees. I think we can use your solution for transitional period. And go for a well defined device tree binding for this in long run. The transitional period is until we no longer care about these specific boards, or any out-of-tree derivatives. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v6 1/5] powerpc/85xx: implement hardware timebase sync
On 06/29/2012 11:12 AM, Timur Tabi wrote: Scott Wood wrote: Why is this different from anywhere else where we have a list of compatibles to match, often based on various SoCs? Note that we explicitly want to match only certain SoCs here. I was just hoping to find a way to avoid an ever increasing list of compatible strings. PCI drivers have to put up with it, why should we be different? :-) Other posts on this thread imply that this code could work for all multi-core e500 parts. That list covers all multi-core e500v2 parts that I know of. Corenet based chips will need a slightly different implementation, since the registers are different. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH -V1 2/9] arch/powerpc: Convert virtual address to a struct
diff --git a/arch/powerpc/include/asm/mmu-hash64.h
b/arch/powerpc/include/asm/mmu-hash64.h
index 1c65a59..5ff936b 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -143,6 +143,10 @@ struct mmu_psize_def
unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */
};
+struct virt_addr {
+ unsigned long addr;
+};
+
#endif /* __ASSEMBLY__ */
/*
@@ -1153,13 +1153,13 @@ void hash_preload(struct mm_struct *mm, unsigned long
ea,
/* WARNING: This is called from hash_low_64.S, if you change this prototype,
* do not forget to update the assembly call site !
*/
I'd suggest having a similar warning next to the definition of struct
virt_addr, as any changes to it mean we'll need to adjust hash_low_64.S
-void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize,
+void flush_hash_page(struct virt_addr va, real_pte_t pte, int psize, int ssize,
int local)
{
unsigned long hash, index, shift, hidx, slot;
- DBG_LOW(flush_hash_page(va=%016lx)\n, va);
- pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
+ DBG_LOW(flush_hash_page(va=%016lx)\n, va.addr);
+ pte_iterate_hashed_subpages(pte, psize, va.addr, index, shift) {
hash = hpt_hash(va, shift, ssize);
hidx = __rpte_to_hidx(pte, index);
if (hidx _PTEIDX_SECONDARY)
--
Cody
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Re: [PATCH] P1021: set IReady in QE Microcode Upload
On Mar 16, 2012, at 11:07 AM, Timur Tabi wrote: Kumar Gala wrote: Haiying said it should be ok, but I haven't tried it yet. I'll try it on Monday. Did you ever test this? No, I forgot all about it. I'll try it today, assuming the lone 8323 board in the board farm still works. Do you remember if you ever tested this? - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] P1021: set IReady in QE Microcode Upload
Kumar Gala wrote: On Mar 16, 2012, at 11:07 AM, Timur Tabi wrote: Kumar Gala wrote: Haiying said it should be ok, but I haven't tried it yet. I'll try it on Monday. Did you ever test this? No, I forgot all about it. I'll try it today, assuming the lone 8323 board in the board farm still works. Do you remember if you ever tested this? No, I forgot again. Ugh, sorry. I'll do it now. -- Timur Tabi Linux kernel developer at Freescale ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: RFC [PATCH] fsl pci quirk to __devinit Re: PCIe end-point on FPGA doesn't show up on PCI bus when configured
On Sep 19, 2011, at 10:35 AM, Matias Garcia wrote: Here's the patch against 2.6.37: Change quirk_fsl_pcie_header from __init to __devinit. Signed-off-by: Matias Garcia mgar...@rossvideo.com applied - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/fsl: Distribute interrupts on all CPUs by default
On Apr 13, 2012, at 5:26 PM, Kim Phillips wrote: At least for crypto/IPSec, doing so provides users with a better performance experience out of the box. Signed-off-by: Kim Phillips kim.phill...@freescale.com --- arch/powerpc/configs/corenet32_smp_defconfig |1 + arch/powerpc/configs/corenet64_smp_defconfig |1 + arch/powerpc/configs/mpc85xx_smp_defconfig |1 + 3 files changed, 3 insertions(+) applied - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v3] powerpc/85xx: Enable MTD/NOR/NAND options by default in defconfig
On Apr 26, 2012, at 10:01 PM, Shengzhou Liu wrote: Enable MTD/NOR/NAND options by default in mpc85xx_defconfig and mpc85xx_smp_defconfig to support NOR, NAND flash. Signed-off-by: Shengzhou Liu shengzhou@freescale.com --- based on master branch of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git tree. v3: remove CONFIG_MTD_NAND_VERIFY_WRITE=y v2: remove typo CONFIG_MPC8xxx_GPIO=y arch/powerpc/configs/mpc85xx_defconfig | 24 arch/powerpc/configs/mpc85xx_smp_defconfig | 24 2 files changed, 48 insertions(+), 0 deletions(-) [ what about the corenet defconfigs?? ] applied - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/2] powerpc/p1022ds/DTS: Add RTC support
On Apr 16, 2012, at 8:42 PM, chang-ming.hu...@freescale.com chang-ming.hu...@freescale.com wrote: From: Jerry Huang chang-ming.hu...@freescale.com Add the RTC support for p1022ds Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com --- arch/powerpc/boot/dts/p1022ds.dtsi |4 1 files changed, 4 insertions(+), 0 deletions(-) applied - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: powerpc/85xx: p2020rdb - move the NAND address.
On May 9, 2012, at 2:53 PM, Sebastian Andrzej Siewior wrote: * Kumar Gala | 2012-03-31 09:48:18 [-0500]: Sorry for the delay Kumar, I though I allready done it. Yes, please do. Here it comes. From 5b3e09992615e5670fa8e432e50424466fa9ca1a Mon Sep 17 00:00:00 2001 From: Sebastian Andrzej Siewior bige...@linutronix.de Date: Wed, 9 May 2012 21:48:42 +0200 Subject: [PATCH] Revert powerpc/85xx: p2020rdb - move the NAND address. This reverts commit 0c00f65653389a408dfbbee7578e671664eea26a. The initial commit was my fault. There are two boards out there: P2020RDB and P2020RDB-PC. I wasn't aware of that and assumed that I have a RDB board in front of me while I the RDB-PC. This patch makes it work for the RDB-PC variant and breaks it for the RDB. Now there is a device tree file available for the RDB-PC which was not there earlier. So with this revert, everything gets back to normal :) Signed-off-by: Sebastian Andrzej Siewior bige...@linutronix.de --- arch/powerpc/boot/dts/p2020rdb.dts |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) applied - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/p1010rdb: add EEPROMs to device tree
On May 23, 2012, at 9:35 AM, Gustavo Zacarias wrote: Add EEPROM to the P1010RDB device tree. The 24c01 acts as a memory SPD so it shouldn't be overwritten without care. The 24c256 is a general purpose memory. Signed-off-by: Gustavo Zacarias gust...@zacarias.com.ar --- arch/powerpc/boot/dts/p1010rdb.dtsi | 12 1 files changed, 12 insertions(+), 0 deletions(-) applied - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 1/3] powerpc: remove Wind River SBC8560 support
On Jun 26, 2012, at 2:54 PM, Paul Gortmaker wrote: This reference board dates back to 2004, and is largely a legacy EOL product. The MPC8560 is a pre e500v2 CPU. The SBC8548 is a more modern, better e500v2 target for people to use as a reference board with today's kernels, should they require one. Removing support for it will also allow us to remove some sbc8560 specific quirk handling in 8250 UART code, and some MTD mapping support. Cc: David Woodhouse david.woodho...@intel.com Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com --- arch/powerpc/boot/Makefile |1 - arch/powerpc/boot/dts/sbc8560.dts | 406 --- arch/powerpc/configs/85xx/sbc8560_defconfig | 65 - arch/powerpc/platforms/85xx/Kconfig |6 - arch/powerpc/platforms/85xx/Makefile|1 - arch/powerpc/platforms/85xx/sbc8560.c | 254 - 6 files changed, 0 insertions(+), 733 deletions(-) delete mode 100644 arch/powerpc/boot/dts/sbc8560.dts delete mode 100644 arch/powerpc/configs/85xx/sbc8560_defconfig delete mode 100644 arch/powerpc/platforms/85xx/sbc8560.c applied - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 1/4] powerpc/83xx: use for_each_node_by_name for km83xx.c
On May 8, 2012, at 8:57 AM, Holger Brunck wrote: Signed-off-by: Holger Brunck holger.bru...@keymile.com cc: Heiko Schocher h...@denx.de cc: Kumar Gala ga...@kernel.crashing.org --- arch/powerpc/platforms/83xx/km83xx.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) applied - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/4] powerpc/83xx: fix RGMII AC values workaround for km83xx
On May 8, 2012, at 8:57 AM, Holger Brunck wrote: From: Christian Herzig christian.her...@keymile.com Fix RGMII workaround code in km83xx.c for MPC8360E and MPC8358E that it correctly identifes all affected SoC chip models and applies the workarounds appropriate for 2.0 and 2.1 revisions as per Freescale MPC8360ECE Errata document Rev.5(9/2011) item QE_ENET10. Signed-off-by: Christian Herzig christian.her...@keymile.com Signed-off-by: Holger Brunck holger.bru...@keymile.com cc: Heiko Schocher h...@denx.de cc: Kumar Gala ga...@kernel.crashing.org --- arch/powerpc/platforms/83xx/km83xx.c | 98 +++--- 1 files changed, 66 insertions(+), 32 deletions(-) applied - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 3/4] powerpc/83xx: update defconfig for kmeter1
On May 8, 2012, at 8:57 AM, Holger Brunck wrote: Switch on UBIFS, HOTPLUG and TIPC and update the config to the latest kernel version. Signed-off-by: Holger Brunck holger.bru...@keymile.com cc: Heiko Schocher h...@denx.de cc: Kumar Gala ga...@kernel.crashing.org --- arch/powerpc/configs/83xx/kmeter1_defconfig | 22 -- 1 files changed, 8 insertions(+), 14 deletions(-) applied - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 4/4] powerpc/82xx: add SPI support for mgcoge
On May 8, 2012, at 8:57 AM, Holger Brunck wrote: Add spi support for mgcoge into the platform code and the dts file. Additionaly SPIDEV is switched on in the defconfig and the updates for the newer kernel version are committed. The SPI interface is used to drive the Maxim DS3106 clock chip. Signed-off-by: Holger Brunck holger.bru...@keymile.com cc: Heiko Schocher h...@denx.de cc: Kumar Gala ga...@kernel.crashing.org --- arch/powerpc/boot/dts/mgcoge.dts | 23 +++ arch/powerpc/configs/mgcoge_defconfig | 12 arch/powerpc/platforms/82xx/km82xx.c |5 + 3 files changed, 32 insertions(+), 8 deletions(-) applied - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 1/2] powerpc/85xx: Add P1024rdb dts support
On May 24, 2012, at 4:08 AM, b29...@freescale.com b29...@freescale.com wrote: From: Tang Yuantian yuantian.t...@freescale.com Signed-off-by: Jin Qing b24...@freescale.com Signed-off-by: Li Yang le...@freescale.com Signed-off-by: Tang Yuantian yuantian.t...@freescale.com --- arch/powerpc/boot/dts/p1024rdb.dtsi| 228 arch/powerpc/boot/dts/p1024rdb_32b.dts | 87 arch/powerpc/boot/dts/p1024rdb_36b.dts | 87 3 files changed, 402 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/boot/dts/p1024rdb.dtsi create mode 100644 arch/powerpc/boot/dts/p1024rdb_32b.dts create mode 100644 arch/powerpc/boot/dts/p1024rdb_36b.dts applied - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/2] powerpc/85xx: Add P1024rdb board support
On May 24, 2012, at 4:08 AM, b29...@freescale.com b29...@freescale.com wrote: From: Tang Yuantian yuantian.t...@freescale.com The p1024rdb has the similar feature as the p1020rdb. Therefore, p1024rdb use the same platform file as the p1/p2 rdb board. Overview of P2020RDB platform - DDR3 1G - NOR flash 16M - 3 Ethernet interfaces - NAND Flash 32M - SPI EEPROM 16M - SD/MMC - 2 USB ports - 4 TDM ports Signed-off-by: Jin Qing b24...@freescale.com Signed-off-by: Li Yang le...@freescale.com Signed-off-by: Tang Yuantian yuantian.t...@freescale.com --- arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 22 ++ 1 files changed, 22 insertions(+), 0 deletions(-) applied - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/p2041rdb: add NAND node in device tree
On Jun 29, 2012, at 4:41 AM, Shaohui Xie wrote: NAND on p2041 uses CS1 as chip select. Signed-off-by: Shaohui Xie shaohui@freescale.com --- arch/powerpc/boot/dts/p2041rdb.dts | 41 +++- 1 files changed, 40 insertions(+), 1 deletions(-) applied - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v2 1/3] powerpc/fsl-pci: get PCI init out of board files
As an alternative incremental starting point to Jia Hongtao's patchset,
get the FSL PCI init out of the board files, but do not yet convert to a
platform driver.
Rather than having each board supply a magic register offset for
determining the primary bus, we look for which PCI host bridge
contains an ISA node within its subtree. If there is no ISA node,
normally that would mean there is no primary bus, but until certain
bugs are fixed we arbitrarily designate a primary in this case.
Conversion to a platform driver and related improvements can happen
after this, as the ordering issues are sorted out.
Signed-off-by: Scott Wood scottw...@freescale.com
---
v2: Honor existing fsl_pci_primary if non-NULL, and update copyright year
No change to the rest of the patchset.
arch/powerpc/sysdev/fsl_pci.c | 71 -
arch/powerpc/sysdev/fsl_pci.h |8 +
2 files changed, 78 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 6073288..fcc9370 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -1,7 +1,7 @@
/*
* MPC83xx/85xx/86xx PCI/PCIE support routing.
*
- * Copyright 2007-2011 Freescale Semiconductor, Inc.
+ * Copyright 2007-2012 Freescale Semiconductor, Inc.
* Copyright 2008-2009 MontaVista Software, Inc.
*
* Initial author: Xianghua Xiao x.x...@freescale.com
@@ -807,3 +807,72 @@ u64 fsl_pci_immrbar_base(struct pci_controller *hose)
return 0;
}
+
+#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
+static const struct of_device_id pci_ids[] = {
+ { .compatible = fsl,mpc8540-pci, },
+ { .compatible = fsl,mpc8548-pcie, },
+ { .compatible = fsl,mpc8610-pci, },
+ { .compatible = fsl,mpc8641-pcie, },
+ { .compatible = fsl,p1022-pcie, },
+ { .compatible = fsl,p1010-pcie, },
+ { .compatible = fsl,p1023-pcie, },
+ { .compatible = fsl,p4080-pcie, },
+ { .compatible = fsl,qoriq-pcie-v2.3, },
+ { .compatible = fsl,qoriq-pcie-v2.2, },
+ {},
+};
+
+struct device_node *fsl_pci_primary;
+
+void __devinit fsl_pci_init(void)
+{
+ struct device_node *node;
+ struct pci_controller *hose;
+ dma_addr_t max = 0x;
+
+ /* Callers can specify the primary bus using other means. */
+ if (!fsl_pci_primary) {
+ /* If a PCI host bridge contains an ISA node, it's primary. */
+ node = of_find_node_by_type(NULL, isa);
+ while ((fsl_pci_primary = of_get_parent(node))) {
+ of_node_put(node);
+ node = fsl_pci_primary;
+
+ if (of_match_node(pci_ids, node))
+ break;
+ }
+ }
+
+ node = NULL;
+ for_each_node_by_type(node, pci) {
+ if (of_match_node(pci_ids, node)) {
+ /*
+* If there's no PCI host bridge with ISA, arbitrarily
+* designate one as primary. This can go away once
+* various bugs with primary-less systems are fixed.
+*/
+ if (!fsl_pci_primary)
+ fsl_pci_primary = node;
+
+ fsl_add_bridge(node, fsl_pci_primary == node);
+ hose = pci_find_hose_for_OF_device(node);
+ max = min(max, hose-dma_window_base_cur +
+ hose-dma_window_size);
+ }
+ }
+
+#ifdef CONFIG_SWIOTLB
+ /*
+* if we couldn't map all of DRAM via the dma windows
+* we need SWIOTLB to handle buffers located outside of
+* dma capable memory region
+*/
+ if (memblock_end_of_DRAM() - 1 max) {
+ ppc_swiotlb_enable = 1;
+ set_pci_dma_ops(swiotlb_dma_ops);
+ ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
+ }
+#endif
+}
+#endif
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index a39ed5c..baa0fd1 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -93,5 +93,13 @@ extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
extern int mpc83xx_add_bridge(struct device_node *dev);
u64 fsl_pci_immrbar_base(struct pci_controller *hose);
+extern struct device_node *fsl_pci_primary;
+
+#ifdef CONFIG_FSL_PCI
+void fsl_pci_init(void);
+#else
+static inline void fsl_pci_init(void) {}
+#endif
+
#endif /* __POWERPC_FSL_PCI_H */
#endif /* __KERNEL__ */
--
1.7.5.4
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[git pull] Please pull powerpc.git merge branch
Hi Linus ! Here are a few powerpc fixes. Arguably some of this should have come to you earlier but I'm only just catching up after my medical leave. Mostly these fixes regressions, a couple are long standing bugs. Cheers, Ben. The following changes since commit 9acc7bde23ebb19a704395f76490685e1513e422: Merge tag 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging (2012-06-28 12:38:51 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git merge for you to fetch changes up to bc6dc752f35488160ffac07ae91bed1bddaea32a: powerpc/pseries: Fix software invalidate TCE (2012-06-29 14:35:37 +1000) Anton Blanchard (1): powerpc: check_and_cede_processor() never cedes Li Zhong (1): powerpc: Fix Section mismatch warnings in prom_init.c Michael Ellerman (1): powerpc: Fix BPF_JIT code to link with multiple TOCs Michael Neuling (2): powerpc: Fix uninitialised error in numa.c powerpc/pseries: Fix software invalidate TCE Steven Rostedt (1): powerpc/ftrace: Do not trace restore_interrupts() Tiejun Chen (1): ppc64: fix missing to check all bits of _TIF_USER_WORK_MASK in preempt arch/powerpc/include/asm/hw_irq.h |5 ++ arch/powerpc/kernel/entry_64.S | 97 ++- arch/powerpc/kernel/irq.c |2 +- arch/powerpc/kernel/prom_init.c |4 +- arch/powerpc/mm/numa.c |2 +- arch/powerpc/net/bpf_jit_64.S |2 + arch/powerpc/platforms/pseries/iommu.c |4 +- arch/powerpc/platforms/pseries/processor_idle.c |2 +- 8 files changed, 54 insertions(+), 64 deletions(-) ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH -V1 2/9] arch/powerpc: Convert virtual address to a struct
On Fri, 2012-06-29 at 19:47 +0530, Aneesh Kumar K.V wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This is in preparation to the conversion of 64 bit powerpc virtual address
to the max 78 bits. Later patch will switch struct virt_addr to a struct
of virtual segment id and segment offset.
I'm not to happy about that.
Mostly, the name of the structure. It's too generic and thus likely to
both collide and cause misunderstandings. Do we really need that
anyways ?
Can't we just replace our use of va's everywhere with vpn's instead and
just avoid the type change ?
Cheers,
Ben.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/kvm_book3s.h |2 +-
arch/powerpc/include/asm/machdep.h |6 +--
arch/powerpc/include/asm/mmu-hash64.h | 24 ++
arch/powerpc/include/asm/tlbflush.h |4 +-
arch/powerpc/kvm/book3s_64_mmu_host.c |3 +-
arch/powerpc/mm/hash_native_64.c| 76
+--
arch/powerpc/mm/hash_utils_64.c | 12 ++---
arch/powerpc/mm/hugetlbpage-hash64.c|3 +-
arch/powerpc/mm/tlb_hash64.c|3 +-
arch/powerpc/platforms/cell/beat_htab.c | 17 +++
arch/powerpc/platforms/ps3/htab.c |6 +--
arch/powerpc/platforms/pseries/lpar.c | 30 ++--
12 files changed, 103 insertions(+), 83 deletions(-)
diff --git a/arch/powerpc/include/asm/kvm_book3s.h
b/arch/powerpc/include/asm/kvm_book3s.h
index fd07f43..374b75d 100644
--- a/arch/powerpc/include/asm/kvm_book3s.h
+++ b/arch/powerpc/include/asm/kvm_book3s.h
@@ -59,7 +59,7 @@ struct hpte_cache {
struct hlist_node list_vpte;
struct hlist_node list_vpte_long;
struct rcu_head rcu_head;
- u64 host_va;
+ struct virt_addr host_va;
u64 pfn;
ulong slot;
struct kvmppc_pte pte;
diff --git a/arch/powerpc/include/asm/machdep.h
b/arch/powerpc/include/asm/machdep.h
index 42ce570..b34d0a9 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -34,19 +34,19 @@ struct machdep_calls {
char*name;
#ifdef CONFIG_PPC64
void(*hpte_invalidate)(unsigned long slot,
-unsigned long va,
+struct virt_addr va,
int psize, int ssize,
int local);
long(*hpte_updatepp)(unsigned long slot,
unsigned long newpp,
- unsigned long va,
+ struct virt_addr va,
int psize, int ssize,
int local);
void(*hpte_updateboltedpp)(unsigned long newpp,
unsigned long ea,
int psize, int ssize);
long(*hpte_insert)(unsigned long hpte_group,
-unsigned long va,
+struct virt_addr va,
unsigned long prpn,
unsigned long rflags,
unsigned long vflags,
diff --git a/arch/powerpc/include/asm/mmu-hash64.h
b/arch/powerpc/include/asm/mmu-hash64.h
index 1c65a59..5ff936b 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -143,6 +143,10 @@ struct mmu_psize_def
unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */
};
+struct virt_addr {
+ unsigned long addr;
+};
+
#endif /* __ASSEMBLY__ */
/*
@@ -183,11 +187,11 @@ extern int mmu_ci_restrictions;
* This function sets the AVPN and L fields of the HPTE appropriately
* for the page size
*/
-static inline unsigned long hpte_encode_v(unsigned long va, int psize,
+static inline unsigned long hpte_encode_v(struct virt_addr va, int psize,
int ssize)
{
unsigned long v;
- v = (va 23) ~(mmu_psize_defs[psize].avpnm);
+ v = (va.addr 23) ~(mmu_psize_defs[psize].avpnm);
v = HPTE_V_AVPN_SHIFT;
if (psize != MMU_PAGE_4K)
v |= HPTE_V_LARGE;
@@ -218,28 +222,30 @@ static inline unsigned long hpte_encode_r(unsigned long
pa, int psize)
/*
* Build a VA given VSID, EA and segment size
*/
-static inline unsigned long hpt_va(unsigned long ea, unsigned long vsid,
+static inline struct virt_addr hpt_va(unsigned long ea, unsigned long vsid,
int ssize)
{
+ struct virt_addr va;
if (ssize == MMU_SEGSIZE_256M)
- return (vsid 28) | (ea 0xfffUL);
- return (vsid 40) | (ea 0xffUL);
+ va.addr = (vsid
Re: [PATCH -V1 4/9] arch/powerpc: Use vsid and segment offset to represent virtual address
On Fri, 2012-06-29 at 19:47 +0530, Aneesh Kumar K.V wrote:
+/* 78 bit power virtual address */
struct virt_addr {
- unsigned long addr;
+ unsigned long vsid;
+ unsigned long seg_off;
};
Do we really need to do that ? It's really nasty...
We are trying to add only a few bits, we get 12 for free by just using a
page number (4k based always, not PAGE_SHIFT based btw) no ? That should
get us going for a while
Cheers,
Ben.
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