Re: new way of writing defconfigs for freescale's powerpc platforms
On Thu, 2015-04-16 at 23:13 -0500, Scott Wood wrote: On Fri, 2015-04-17 at 10:54 +1000, Michael Ellerman wrote: On Thu, 2015-04-09 at 21:52 +, Lijun Pan wrote: Hi Maintainers, We have a proposal for writing the defconfigs for freescale's powperpc platforms in a new way. Can you take a look and provide some feedback? You know currently we have mpc85xx_defconfig, corenet32_defconfig, bsc913x_defconfig, *fman*_defconfig, etc. We are going to extract some common parts from the existing defconfigs, and name it, say, fsl_basic_defconfig. Then, we could create some defconfigs targeting specific features or specific platforms. Say, features specific: kvm_defconfig, fman_defconfig, etc. Platforms specific: p1_defconfig, p2_defcongfig, p4_defconfig, t1_defconfig, t2_defconfig, t2_defconfig, b4_defconfig, etc When we want to make a kernel image for p1 platform, Using the following steps: make ./scripts/kconfig/merge_config.sh arch/powerpc/configs/fsl_basic_config p1_defconfig make What do you think of this new approach? I don't like that the user has to manually run merge_config.sh. How does a user even know that it's an option? It also breaks scripts that auto build the kernel, which expect to be able to do: $ make foo_defconfig $ make Scripts like mine for example :) http://kisskb.ellerman.id.au/kisskb/head/8734/ What I'd be happy with is something that does merge_config under the covers. So a user still runs 'make fsl_plat_foo_defconfig', but under the covers it does a merge config. kvmconfig and tinyconfig are implemented that way already, so with a bit more work hopefully you can do that for arch configs also. kvmconfig and tinyconfig are still separate user-visible steps to be applied after running a base defconfig. Not as of recently: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/scripts/kconfig/Makefile?id=63a91033d52e64a22e571fe84924c0b7f21c280d Which pretty much does what you describe below I think. For breaking a platform defconfig into components, we could do something like this in arch/powerpc/Makefile: # Can't call mergeconfig directly as it isn't defined at this point define domerge @$(MAKE) -f $(srctree)/scripts/kconfig/Makefile $(1).config endef corenet64_smp_defconfig: corenet64_basic_defconfig $(call domerge,smp) $(call domerge,altivec) $(call domerge,corenet_drivers) $(call domerge,embedded_misc) # filesystems etc And this in scripts/kconfig/Makefile: %.config: $(call mergeconfig,$*) One issue with this is that we'd lose the ability to use savedefconfig (at least without manual manipulation of the results) to maintain the defconfigs/fragments. That's probably OK, it's only maintainers who need to do that. cheers ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH kernel v8 12/31] powerpc/spapr: vfio: Switch from iommu_table to new iommu_table_group
On 04/16/2015 03:55 PM, David Gibson wrote:
On Fri, Apr 10, 2015 at 04:30:54PM +1000, Alexey Kardashevskiy wrote:
Modern IBM POWERPC systems support multiple (currently two) TCE tables
per IOMMU group (a.k.a. PE). This adds a iommu_table_group container
for TCE tables. Right now just one table is supported.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
arch/powerpc/include/asm/iommu.h| 18 +++--
arch/powerpc/kernel/iommu.c | 34
arch/powerpc/platforms/powernv/pci-ioda.c | 38 +
arch/powerpc/platforms/powernv/pci-p5ioc2.c | 17 ++--
arch/powerpc/platforms/powernv/pci.c| 2 +-
arch/powerpc/platforms/powernv/pci.h| 4 +-
arch/powerpc/platforms/pseries/iommu.c | 9 ++-
drivers/vfio/vfio_iommu_spapr_tce.c | 120
8 files changed, 160 insertions(+), 82 deletions(-)
diff --git a/arch/powerpc/include/asm/iommu.h b/arch/powerpc/include/asm/iommu.h
index eb75726..667aa1a 100644
--- a/arch/powerpc/include/asm/iommu.h
+++ b/arch/powerpc/include/asm/iommu.h
@@ -90,9 +90,7 @@ struct iommu_table {
struct iommu_pool pools[IOMMU_NR_POOLS];
unsigned long *it_map; /* A simple allocation bitmap for now */
unsigned long it_page_shift;/* table iommu page size */
-#ifdef CONFIG_IOMMU_API
- struct iommu_group *it_group;
-#endif
+ struct iommu_table_group *it_group;
struct iommu_table_ops *it_ops;
void (*set_bypass)(struct iommu_table *tbl, bool enable);
};
@@ -126,14 +124,24 @@ extern void iommu_free_table(struct iommu_table *tbl,
const char *node_name);
*/
extern struct iommu_table *iommu_init_table(struct iommu_table * tbl,
int nid);
+
+#define IOMMU_TABLE_GROUP_MAX_TABLES 1
+
+struct iommu_table_group {
#ifdef CONFIG_IOMMU_API
-extern void iommu_register_group(struct iommu_table *tbl,
+ struct iommu_group *group;
+#endif
+ struct iommu_table tables[IOMMU_TABLE_GROUP_MAX_TABLES];
There's nothing to indicate which of the tables are in use at the
current time. I mean, it doesn't matter now because there's only one,
but the patch doesn't make a whole lot of sense without that.
Later in the patchset, the code will look at @it_size to know if the table
is in use.
+};
+
+#ifdef CONFIG_IOMMU_API
+extern void iommu_register_group(struct iommu_table_group *table_group,
int pci_domain_number, unsigned long pe_num);
extern int iommu_add_device(struct device *dev);
extern void iommu_del_device(struct device *dev);
extern int __init tce_iommu_bus_notifier_init(void);
#else
-static inline void iommu_register_group(struct iommu_table *tbl,
+static inline void iommu_register_group(struct iommu_table_group *table_group,
int pci_domain_number,
unsigned long pe_num)
{
diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c
index b39d00a..fd49c8e 100644
--- a/arch/powerpc/kernel/iommu.c
+++ b/arch/powerpc/kernel/iommu.c
@@ -712,17 +712,20 @@ struct iommu_table *iommu_init_table(struct iommu_table
*tbl, int nid)
struct iommu_table *iommu_table_alloc(int node)
{
- struct iommu_table *tbl;
+ struct iommu_table_group *table_group;
- tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, node);
+ table_group = kzalloc_node(sizeof(struct iommu_table_group), GFP_KERNEL,
+ node);
+ table_group-tables[0].it_group = table_group;
- return tbl;
+ return table_group-tables[0];
}
void iommu_free_table(struct iommu_table *tbl, const char *node_name)
Surely the free function should take a table group rather than a table
as argument.
Please ignore my other response to your reply; I reworked the whole thing
to store iommu_table_group in the pci device node. Thanks.
--
Alexey
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[PATCH v3 09/17] crypto: talitos - Add a feature to tag SEC1
We add a new feature in the features field, to mark compatible
fsl,sec1.0
We also define a helper function called has_ftr_sec1() to help
functions quickly determine if they are running on SEC1 or SEC2+.
When only SEC1 or SEC2 is compiled in, has_ftr_sec1() return
trivial corresponding value. If both are compiled in, feature
field is checked.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 3 +++
drivers/crypto/talitos.h | 17 +
2 files changed, 20 insertions(+)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index bca6ded..db95023 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -2709,6 +2709,9 @@ static int talitos_probe(struct platform_device *ofdev)
TALITOS_FTR_SHA224_HWINIT |
TALITOS_FTR_HMAC_OK;
+ if (of_device_is_compatible(np, fsl,sec1.0))
+ priv-features |= TALITOS_FTR_SEC1;
+
priv-chan = kzalloc(sizeof(struct talitos_channel) *
priv-num_channels, GFP_KERNEL);
if (!priv-chan) {
diff --git a/drivers/crypto/talitos.h b/drivers/crypto/talitos.h
index f078da1..b0bdb4e 100644
--- a/drivers/crypto/talitos.h
+++ b/drivers/crypto/talitos.h
@@ -156,6 +156,23 @@ extern int talitos_submit(struct device *dev, int ch,
struct talitos_desc *desc,
#define TALITOS_FTR_HW_AUTH_CHECK 0x0002
#define TALITOS_FTR_SHA224_HWINIT 0x0004
#define TALITOS_FTR_HMAC_OK 0x0008
+#define TALITOS_FTR_SEC1 0x0010
+
+/*
+ * If both CONFIG_CRYPTO_DEV_TALITOS1 and CONFIG_CRYPTO_DEV_TALITOS2 are
+ * defined, we check the features which are set according to the device tree.
+ * Otherwise, we answer true or false directly
+ */
+static inline bool has_ftr_sec1(struct talitos_private *priv)
+{
+#if defined(CONFIG_CRYPTO_DEV_TALITOS1) defined(CONFIG_CRYPTO_DEV_TALITOS2)
+ return priv-features TALITOS_FTR_SEC1 ? true : false;
+#elif defined(CONFIG_CRYPTO_DEV_TALITOS1)
+ return true;
+#else
+ return false;
+#endif
+}
/*
* TALITOS_xxx_LO addresses point to the low data bits (32-63) of the register
--
2.1.0
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[PATCH v3 10/17] crypto: talitos - fill in talitos descriptor iaw SEC1 or SEC2+
talitos descriptor is slightly different for SEC1 and SEC2+, so
lets the helper function that fills the descriptor take into account
the type of SEC.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 105 ++-
1 file changed, 67 insertions(+), 38 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index db95023..678b528 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -55,25 +55,38 @@
#include talitos.h
-static void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr)
+static void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
+ bool is_sec1)
{
ptr-ptr = cpu_to_be32(lower_32_bits(dma_addr));
- ptr-eptr = upper_32_bits(dma_addr);
+ if (!is_sec1)
+ ptr-eptr = upper_32_bits(dma_addr);
}
-static void to_talitos_ptr_len(struct talitos_ptr *ptr, unsigned short len)
+static void to_talitos_ptr_len(struct talitos_ptr *ptr, unsigned short len,
+ bool is_sec1)
{
- ptr-len = cpu_to_be16(len);
+ if (is_sec1) {
+ ptr-res = 0;
+ ptr-len1 = cpu_to_be16(len);
+ } else {
+ ptr-len = cpu_to_be16(len);
+ }
}
-static unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr)
+static unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr,
+ bool is_sec1)
{
- return be16_to_cpu(ptr-len);
+ if (is_sec1)
+ return be16_to_cpu(ptr-len1);
+ else
+ return be16_to_cpu(ptr-len);
}
-static void to_talitos_ptr_extent_clear(struct talitos_ptr *ptr)
+static void to_talitos_ptr_extent_clear(struct talitos_ptr *ptr, bool is_sec1)
{
- ptr-j_extent = 0;
+ if (!is_sec1)
+ ptr-j_extent = 0;
}
/*
@@ -85,10 +98,12 @@ static void map_single_talitos_ptr(struct device *dev,
enum dma_data_direction dir)
{
dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ bool is_sec1 = has_ftr_sec1(priv);
- to_talitos_ptr_len(ptr, len);
- to_talitos_ptr(ptr, dma_addr);
- to_talitos_ptr_extent_clear(ptr);
+ to_talitos_ptr_len(ptr, len, is_sec1);
+ to_talitos_ptr(ptr, dma_addr, is_sec1);
+ to_talitos_ptr_extent_clear(ptr, is_sec1);
}
/*
@@ -98,8 +113,11 @@ static void unmap_single_talitos_ptr(struct device *dev,
struct talitos_ptr *ptr,
enum dma_data_direction dir)
{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ bool is_sec1 = has_ftr_sec1(priv);
+
dma_unmap_single(dev, be32_to_cpu(ptr-ptr),
-from_talitos_ptr_len(ptr), dir);
+from_talitos_ptr_len(ptr, is_sec1), dir);
}
static int reset_channel(struct device *dev, int ch)
@@ -922,7 +940,7 @@ static int sg_to_link_tbl(struct scatterlist *sg, int
sg_count,
int n_sg = sg_count;
while (n_sg--) {
- to_talitos_ptr(link_tbl_ptr, sg_dma_address(sg));
+ to_talitos_ptr(link_tbl_ptr, sg_dma_address(sg), 0);
link_tbl_ptr-len = cpu_to_be16(sg_dma_len(sg));
link_tbl_ptr-j_extent = 0;
link_tbl_ptr++;
@@ -976,7 +994,7 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct
aead_request *areq,
struct talitos_ptr *tbl_ptr = edesc-link_tbl[tbl_off];
to_talitos_ptr(desc-ptr[1], edesc-dma_link_tbl + tbl_off *
- sizeof(struct talitos_ptr));
+ sizeof(struct talitos_ptr), 0);
desc-ptr[1].j_extent = DESC_PTR_LNKTBL_JUMP;
/* assoc_nents - 1 entries for assoc, 1 for IV */
@@ -987,7 +1005,7 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct
aead_request *areq,
tbl_ptr += sg_count - 1;
tbl_ptr-j_extent = 0;
tbl_ptr++;
- to_talitos_ptr(tbl_ptr, edesc-iv_dma);
+ to_talitos_ptr(tbl_ptr, edesc-iv_dma, 0);
tbl_ptr-len = cpu_to_be16(ivsize);
tbl_ptr-j_extent = DESC_PTR_LNKTBL_RETURN;
@@ -996,14 +1014,14 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct
aead_request *areq,
} else {
if (areq-assoclen)
to_talitos_ptr(desc-ptr[1],
- sg_dma_address(areq-assoc));
+ sg_dma_address(areq-assoc), 0);
else
- to_talitos_ptr(desc-ptr[1], edesc-iv_dma);
+ to_talitos_ptr(desc-ptr[1], edesc-iv_dma, 0);
desc-ptr[1].j_extent = 0;
}
/* cipher iv */
-
[PATCH v3 11/17] crypto: talitos - adaptation of talitos_submit() for SEC1
SEC1 descriptor is a bit different to SEC2+ descriptor.
talitos_submit() will have to copy hdr field into hdr1 field and
send the descriptor starting at hdr1 up to next_desc.
For SEC2, it remains unchanged and next_desc is just ignored.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 23 +++
drivers/crypto/talitos.h | 2 ++
2 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 678b528..e6ea651 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -236,6 +236,7 @@ int talitos_submit(struct device *dev, int ch, struct
talitos_desc *desc,
struct talitos_request *request;
unsigned long flags;
int head;
+ bool is_sec1 = has_ftr_sec1(priv);
spin_lock_irqsave(priv-chan[ch].head_lock, flags);
@@ -249,8 +250,17 @@ int talitos_submit(struct device *dev, int ch, struct
talitos_desc *desc,
request = priv-chan[ch].fifo[head];
/* map descriptor and save caller data */
- request-dma_desc = dma_map_single(dev, desc, sizeof(*desc),
- DMA_BIDIRECTIONAL);
+ if (is_sec1) {
+ desc-hdr1 = desc-hdr;
+ desc-next_desc = 0;
+ request-dma_desc = dma_map_single(dev, desc-hdr1,
+ TALITOS_DESC_SIZE,
+ DMA_BIDIRECTIONAL);
+ } else {
+ request-dma_desc = dma_map_single(dev, desc,
+ TALITOS_DESC_SIZE,
+ DMA_BIDIRECTIONAL);
+ }
request-callback = callback;
request-context = context;
@@ -282,16 +292,21 @@ static void flush_channel(struct device *dev, int ch, int
error, int reset_ch)
struct talitos_request *request, saved_req;
unsigned long flags;
int tail, status;
+ bool is_sec1 = has_ftr_sec1(priv);
spin_lock_irqsave(priv-chan[ch].tail_lock, flags);
tail = priv-chan[ch].tail;
while (priv-chan[ch].fifo[tail].desc) {
+ __be32 hdr;
+
request = priv-chan[ch].fifo[tail];
/* descriptors with their done bits set don't get the error */
rmb();
- if ((request-desc-hdr DESC_HDR_DONE) == DESC_HDR_DONE)
+ hdr = is_sec1 ? request-desc-hdr1 : request-desc-hdr;
+
+ if ((hdr DESC_HDR_DONE) == DESC_HDR_DONE)
status = 0;
else
if (!error)
@@ -300,7 +315,7 @@ static void flush_channel(struct device *dev, int ch, int
error, int reset_ch)
status = error;
dma_unmap_single(dev, request-dma_desc,
-sizeof(struct talitos_desc),
+TALITOS_DESC_SIZE,
DMA_BIDIRECTIONAL);
/* copy entries so we can call callback outside lock */
diff --git a/drivers/crypto/talitos.h b/drivers/crypto/talitos.h
index b0bdb4e..f827c04 100644
--- a/drivers/crypto/talitos.h
+++ b/drivers/crypto/talitos.h
@@ -69,6 +69,8 @@ struct talitos_desc {
__be32 next_desc; /* next descriptor (SEC1) */
};
+#define TALITOS_DESC_SIZE (sizeof(struct talitos_desc) - sizeof(__be32))
+
/**
* talitos_request - descriptor submission request
* @desc: descriptor pointer (kernel virtual)
--
2.1.0
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[PATCH v3 12/17] crypto: talitos - base address for Execution Units
SEC 1.0, 1.2 and 2.x+ have different EU base addresses, so we need to
define pointers for each EU in the driver private data structure.
The proper address is set by the probe function depending on the
SEC type, in order to provide access to the proper address.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 83
drivers/crypto/talitos.h | 72 +
2 files changed, 100 insertions(+), 55 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index e6ea651..6d77699 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -208,7 +208,7 @@ static int init_device(struct device *dev)
/* disable integrity check error interrupts (use writeback instead) */
if (priv-features TALITOS_FTR_HW_AUTH_CHECK)
- setbits32(priv-reg + TALITOS_MDEUICR_LO,
+ setbits32(priv-reg_mdeu + TALITOS_EUICR_LO,
TALITOS_MDEUICR_LO_ICE);
return 0;
@@ -424,44 +424,44 @@ static void report_eu_error(struct device *dev, int ch,
u32 desc_hdr)
switch (desc_hdr DESC_HDR_SEL0_MASK) {
case DESC_HDR_SEL0_AFEU:
dev_err(dev, AFEUISR 0x%08x_%08x\n,
- in_be32(priv-reg + TALITOS_AFEUISR),
- in_be32(priv-reg + TALITOS_AFEUISR_LO));
+ in_be32(priv-reg_afeu + TALITOS_EUISR),
+ in_be32(priv-reg_afeu + TALITOS_EUISR_LO));
break;
case DESC_HDR_SEL0_DEU:
dev_err(dev, DEUISR 0x%08x_%08x\n,
- in_be32(priv-reg + TALITOS_DEUISR),
- in_be32(priv-reg + TALITOS_DEUISR_LO));
+ in_be32(priv-reg_deu + TALITOS_EUISR),
+ in_be32(priv-reg_deu + TALITOS_EUISR_LO));
break;
case DESC_HDR_SEL0_MDEUA:
case DESC_HDR_SEL0_MDEUB:
dev_err(dev, MDEUISR 0x%08x_%08x\n,
- in_be32(priv-reg + TALITOS_MDEUISR),
- in_be32(priv-reg + TALITOS_MDEUISR_LO));
+ in_be32(priv-reg_mdeu + TALITOS_EUISR),
+ in_be32(priv-reg_mdeu + TALITOS_EUISR_LO));
break;
case DESC_HDR_SEL0_RNG:
dev_err(dev, RNGUISR 0x%08x_%08x\n,
- in_be32(priv-reg + TALITOS_RNGUISR),
- in_be32(priv-reg + TALITOS_RNGUISR_LO));
+ in_be32(priv-reg_rngu + TALITOS_ISR),
+ in_be32(priv-reg_rngu + TALITOS_ISR_LO));
break;
case DESC_HDR_SEL0_PKEU:
dev_err(dev, PKEUISR 0x%08x_%08x\n,
- in_be32(priv-reg + TALITOS_PKEUISR),
- in_be32(priv-reg + TALITOS_PKEUISR_LO));
+ in_be32(priv-reg_pkeu + TALITOS_EUISR),
+ in_be32(priv-reg_pkeu + TALITOS_EUISR_LO));
break;
case DESC_HDR_SEL0_AESU:
dev_err(dev, AESUISR 0x%08x_%08x\n,
- in_be32(priv-reg + TALITOS_AESUISR),
- in_be32(priv-reg + TALITOS_AESUISR_LO));
+ in_be32(priv-reg_aesu + TALITOS_EUISR),
+ in_be32(priv-reg_aesu + TALITOS_EUISR_LO));
break;
case DESC_HDR_SEL0_CRCU:
dev_err(dev, CRCUISR 0x%08x_%08x\n,
- in_be32(priv-reg + TALITOS_CRCUISR),
- in_be32(priv-reg + TALITOS_CRCUISR_LO));
+ in_be32(priv-reg_crcu + TALITOS_EUISR),
+ in_be32(priv-reg_crcu + TALITOS_EUISR_LO));
break;
case DESC_HDR_SEL0_KEU:
dev_err(dev, KEUISR 0x%08x_%08x\n,
- in_be32(priv-reg + TALITOS_KEUISR),
- in_be32(priv-reg + TALITOS_KEUISR_LO));
+ in_be32(priv-reg_pkeu + TALITOS_EUISR),
+ in_be32(priv-reg_pkeu + TALITOS_EUISR_LO));
break;
}
@@ -469,13 +469,13 @@ static void report_eu_error(struct device *dev, int ch,
u32 desc_hdr)
case DESC_HDR_SEL1_MDEUA:
case DESC_HDR_SEL1_MDEUB:
dev_err(dev, MDEUISR 0x%08x_%08x\n,
- in_be32(priv-reg + TALITOS_MDEUISR),
- in_be32(priv-reg + TALITOS_MDEUISR_LO));
+ in_be32(priv-reg_mdeu + TALITOS_EUISR),
+ in_be32(priv-reg_mdeu + TALITOS_EUISR_LO));
break;
case DESC_HDR_SEL1_CRCU:
dev_err(dev, CRCUISR 0x%08x_%08x\n,
- in_be32(priv-reg + TALITOS_CRCUISR),
- in_be32(priv-reg + TALITOS_CRCUISR_LO));
+ in_be32(priv-reg_crcu + TALITOS_EUISR),
+ in_be32(priv-reg_crcu +
[PATCH v3 13/17] crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 227 +++
drivers/crypto/talitos.h | 39 +---
2 files changed, 199 insertions(+), 67 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 6d77699..1265405 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -124,12 +124,23 @@ static int reset_channel(struct device *dev, int ch)
{
struct talitos_private *priv = dev_get_drvdata(dev);
unsigned int timeout = TALITOS_TIMEOUT;
+ bool is_sec1 = has_ftr_sec1(priv);
- setbits32(priv-chan[ch].reg + TALITOS_CCCR, TALITOS_CCCR_RESET);
+ if (is_sec1) {
+ setbits32(priv-chan[ch].reg + TALITOS_CCCR_LO,
+ TALITOS1_CCCR_LO_RESET);
- while ((in_be32(priv-chan[ch].reg + TALITOS_CCCR) TALITOS_CCCR_RESET)
- --timeout)
- cpu_relax();
+ while ((in_be32(priv-chan[ch].reg + TALITOS_CCCR_LO)
+ TALITOS1_CCCR_LO_RESET) --timeout)
+ cpu_relax();
+ } else {
+ setbits32(priv-chan[ch].reg + TALITOS_CCCR,
+ TALITOS2_CCCR_RESET);
+
+ while ((in_be32(priv-chan[ch].reg + TALITOS_CCCR)
+ TALITOS2_CCCR_RESET) --timeout)
+ cpu_relax();
+ }
if (timeout == 0) {
dev_err(dev, failed to reset channel %d\n, ch);
@@ -152,11 +163,12 @@ static int reset_device(struct device *dev)
{
struct talitos_private *priv = dev_get_drvdata(dev);
unsigned int timeout = TALITOS_TIMEOUT;
- u32 mcr = TALITOS_MCR_SWR;
+ bool is_sec1 = has_ftr_sec1(priv);
+ u32 mcr = is_sec1 ? TALITOS1_MCR_SWR : TALITOS2_MCR_SWR;
setbits32(priv-reg + TALITOS_MCR, mcr);
- while ((in_be32(priv-reg + TALITOS_MCR) TALITOS_MCR_SWR)
+ while ((in_be32(priv-reg + TALITOS_MCR) mcr)
--timeout)
cpu_relax();
@@ -180,6 +192,7 @@ static int init_device(struct device *dev)
{
struct talitos_private *priv = dev_get_drvdata(dev);
int ch, err;
+ bool is_sec1 = has_ftr_sec1(priv);
/*
* Master reset
@@ -203,8 +216,15 @@ static int init_device(struct device *dev)
}
/* enable channel done and error interrupts */
- setbits32(priv-reg + TALITOS_IMR, TALITOS_IMR_INIT);
- setbits32(priv-reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
+ if (is_sec1) {
+ clrbits32(priv-reg + TALITOS_IMR, TALITOS1_IMR_INIT);
+ clrbits32(priv-reg + TALITOS_IMR_LO, TALITOS1_IMR_LO_INIT);
+ /* disable parity error check in DEU (erroneous? test vect.) */
+ setbits32(priv-reg_deu + TALITOS_EUICR, TALITOS1_DEUICR_KPE);
+ } else {
+ setbits32(priv-reg + TALITOS_IMR, TALITOS2_IMR_INIT);
+ setbits32(priv-reg + TALITOS_IMR_LO, TALITOS2_IMR_LO_INIT);
+ }
/* disable integrity check error interrupts (use writeback instead) */
if (priv-features TALITOS_FTR_HW_AUTH_CHECK)
@@ -349,8 +369,37 @@ static void flush_channel(struct device *dev, int ch, int
error, int reset_ch)
/*
* process completed requests for channels that have done status
*/
-#define DEF_TALITOS_DONE(name, ch_done_mask) \
-static void talitos_done_##name(unsigned long data)\
+#define DEF_TALITOS1_DONE(name, ch_done_mask) \
+static void talitos1_done_##name(unsigned long data) \
+{ \
+ struct device *dev = (struct device *)data; \
+ struct talitos_private *priv = dev_get_drvdata(dev);\
+ unsigned long flags;\
+ \
+ if (ch_done_mask 0x1000)
[PATCH v3 14/17] crypto: talitos - implement scatter/gather copy for SEC1
SEC1 doesn't support scatter/gather, SEC1 doesn't handle link tables.
Therefore, for SEC1 we have to do it by SW. For that, we reserve
space at the end of the extended descriptor, in lieu of the space
reserved for the link tables on SEC2, and we perform sg_copy() when
preparing the descriptors
We also adapt the max buffer size which is only 32k on SEC1 while it
is 64k on SEC2+
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 138 ++-
drivers/crypto/talitos.h | 3 +-
2 files changed, 103 insertions(+), 38 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 1265405..dddf4b3 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -866,9 +866,10 @@ badkey:
* @dst_chained: whether dst is chained or not
* @iv_dma: dma address of iv for checking continuity and link table
* @dma_len: length of dma mapped link_tbl space
- * @dma_link_tbl: bus physical address of link_tbl
+ * @dma_link_tbl: bus physical address of link_tbl/buf
* @desc: h/w descriptor
- * @link_tbl: input and output h/w link tables (if {src,dst}_nents 1)
+ * @link_tbl: input and output h/w link tables (if {src,dst}_nents 1) (SEC2)
+ * @buf: input and output buffeur (if {src,dst}_nents 1) (SEC1)
*
* if decrypting (with authcheck), or either one of src_nents or dst_nents
* is greater than 1, an integrity check value is concatenated to the end
@@ -885,7 +886,10 @@ struct talitos_edesc {
int dma_len;
dma_addr_t dma_link_tbl;
struct talitos_desc desc;
- struct talitos_ptr link_tbl[0];
+ union {
+ struct talitos_ptr link_tbl[0];
+ u8 buf[0];
+ };
};
static int talitos_map_sg(struct device *dev, struct scatterlist *sg,
@@ -1282,8 +1286,11 @@ static struct talitos_edesc *talitos_edesc_alloc(struct
device *dev,
dma_addr_t iv_dma = 0;
gfp_t flags = cryptoflags CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
GFP_ATOMIC;
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ bool is_sec1 = has_ftr_sec1(priv);
+ int max_len = is_sec1 ? TALITOS1_MAX_DATA_LEN : TALITOS2_MAX_DATA_LEN;
- if (cryptlen + authsize TALITOS_MAX_DATA_LEN) {
+ if (cryptlen + authsize max_len) {
dev_err(dev, length exceeds h/w max limit\n);
return ERR_PTR(-EINVAL);
}
@@ -1327,8 +1334,12 @@ static struct talitos_edesc *talitos_edesc_alloc(struct
device *dev,
*/
alloc_len = sizeof(struct talitos_edesc);
if (assoc_nents || src_nents || dst_nents) {
- dma_len = (src_nents + dst_nents + 2 + assoc_nents) *
- sizeof(struct talitos_ptr) + authsize;
+ if (is_sec1)
+ dma_len = src_nents ? cryptlen : 0 +
+ dst_nents ? cryptlen : 0;
+ else
+ dma_len = (src_nents + dst_nents + 2 + assoc_nents) *
+ sizeof(struct talitos_ptr) + authsize;
alloc_len += dma_len;
} else {
dma_len = 0;
@@ -1485,7 +1496,27 @@ static void unmap_sg_talitos_ptr(struct device *dev,
struct scatterlist *src,
struct scatterlist *dst, unsigned int len,
struct talitos_edesc *edesc)
{
- talitos_sg_unmap(dev, edesc, src, dst);
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ bool is_sec1 = has_ftr_sec1(priv);
+
+ if (is_sec1) {
+ if (!edesc-src_nents) {
+ dma_unmap_sg(dev, src, 1,
+dst != src ? DMA_TO_DEVICE
+ : DMA_BIDIRECTIONAL);
+ }
+ if (dst edesc-dst_nents) {
+ dma_sync_single_for_device(dev,
+ edesc-dma_link_tbl + len,
+ len, DMA_FROM_DEVICE);
+ sg_copy_from_buffer(dst, edesc-dst_nents ? : 1,
+ edesc-buf + len, len);
+ } else if (dst dst != src) {
+ dma_unmap_sg(dev, dst, 1, DMA_FROM_DEVICE);
+ }
+ } else {
+ talitos_sg_unmap(dev, edesc, src, dst);
+ }
}
static void common_nonsnoop_unmap(struct device *dev,
@@ -1528,25 +1559,42 @@ int map_sg_in_talitos_ptr(struct device *dev, struct
scatterlist *src,
bool is_sec1 = has_ftr_sec1(priv);
to_talitos_ptr_len(ptr, len, is_sec1);
- to_talitos_ptr_extent_clear(ptr, is_sec1);
- sg_count = talitos_map_sg(dev, src, edesc-src_nents ? : 1, dir,
- edesc-src_chained);
+ if (is_sec1) {
+ sg_count = edesc-src_nents ? : 1;
- if (sg_count == 1)
[PATCH v3 15/17] crypto: talitos - SEC1 bugs on 0 data hash
SEC1 bugs on 0 data hash, so we submit an already padded block representing 0
data
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index dddf4b3..f1406d7b 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -1797,6 +1797,27 @@ static void ahash_done(struct device *dev,
areq-base.complete(areq-base, err);
}
+/*
+ * SEC1 doesn't like hashing of 0 sized message, so we do the padding
+ * ourself and submit a padded block
+ */
+void talitos_handle_buggy_hash(struct talitos_ctx *ctx,
+ struct talitos_edesc *edesc,
+ struct talitos_ptr *ptr)
+{
+ static u8 padded_hash[64] = {
+ 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ };
+
+ pr_err_once(Bug in SEC1, padding ourself\n);
+ edesc-desc.hdr = ~DESC_HDR_MODE0_MDEU_PAD;
+ map_single_talitos_ptr(ctx-dev, ptr, sizeof(padded_hash),
+ (char *)padded_hash, DMA_TO_DEVICE);
+}
+
static int common_nonsnoop_hash(struct talitos_edesc *edesc,
struct ahash_request *areq, unsigned int length,
void (*callback) (struct device *dev,
@@ -1857,6 +1878,9 @@ static int common_nonsnoop_hash(struct talitos_edesc
*edesc,
/* last DWORD empty */
desc-ptr[6] = zero_entry;
+ if (is_sec1 from_talitos_ptr_len(desc-ptr[3], true) == 0)
+ talitos_handle_buggy_hash(ctx, edesc, desc-ptr[3]);
+
ret = talitos_submit(dev, ctx-ch, desc, callback, areq);
if (ret != -EINPROGRESS) {
common_nonsnoop_hash_unmap(dev, edesc, areq);
--
2.1.0
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[PATCH v3 16/17] crypto: talitos - Add fsl,sec1.0 compatible
We add a specific compatible for SEC1, to handle the differences
between SEC1 and SEC2+
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index f1406d7b..c04074d 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -3086,9 +3086,16 @@ err_out:
}
static const struct of_device_id talitos_match[] = {
+#ifdef CONFIG_CRYPTO_DEV_TALITOS1
+ {
+ .compatible = fsl,sec1.0,
+ },
+#endif
+#ifdef CONFIG_CRYPTO_DEV_TALITOS2
{
.compatible = fsl,sec2.0,
},
+#endif
{},
};
MODULE_DEVICE_TABLE(of, talitos_match);
--
2.1.0
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[PATCH v3 17/17] crypto: talitos - Update DT bindings with SEC1
This patch updates the documentation by including SEC1 into SEC2/3 doc Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Documentation/devicetree/bindings/crypto/fsl-sec2.txt | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec2.txt b/Documentation/devicetree/bindings/crypto/fsl-sec2.txt index 38988ef..f0d926b 100644 --- a/Documentation/devicetree/bindings/crypto/fsl-sec2.txt +++ b/Documentation/devicetree/bindings/crypto/fsl-sec2.txt @@ -1,9 +1,11 @@ -Freescale SoC SEC Security Engines versions 2.x-3.x +Freescale SoC SEC Security Engines versions 1.x-2.x-3.x Required properties: - compatible : Should contain entries for this and backward compatible - SEC versions, high to low, e.g., fsl,sec2.1, fsl,sec2.0 + SEC versions, high to low, e.g., fsl,sec2.1, fsl,sec2.0 (SEC2/3) + e.g., fsl,sec1.2, fsl,sec1.0 (SEC1) +warning: SEC1 and SEC2 are mutually exclusive - reg : Offset and length of the register set for the device - interrupts : the SEC's interrupt number - fsl,num-channels : An integer representing the number of channels -- 2.1.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v3 00/17] crypto: talitos - Add support for SEC1
Oops, this is the first time I use directly the output of git format-patch into sendmail, and it looks like the mails are dated with the commit date, not today's date. I will resend now with today's date. Sorry for the noise. Christophe Le 17/04/2015 15:47, Christophe Leroy a écrit : The purpose of this set of patchs is to add to talitos crypto driver the support for the SEC1 version of the security engine, which is found in mpc885 and mpc8272 processors. v3 is a complete rework of the patchset. Since a kernel can be built with support for both MPC82xx and MPC83xx at the same time, talitos driver shall support both SEC1 and SEC2+ at the same time. Based on cryptodev-2.6 tree Christophe Leroy (17): crypto: talitos - Use zero entry to init descriptors ptrs to zero crypto: talitos - Refactor the sg in/out chain allocation crypto: talitos - talitos_ptr renamed ptr for more lisibility crypto: talitos - Add a helper function to clear j_extent field crypto: talitos - remove param 'extent' in map_single_talitos_ptr() crypto: talitos - helper function for ptr len crypto: talitos - enhanced talitos_desc struct for SEC1 crypto: talitos - add sub-choice in talitos CONFIG for SEC1 crypto: talitos - Add a feature to tag SEC1 crypto: talitos - fill in talitos descriptor iaw SEC1 or SEC2+ crypto: talitos - adaptation of talitos_submit() for SEC1 crypto: talitos - base address for Execution Units crypto: talitos - adapt interrupts and reset functions to SEC1 crypto: talitos - implement scatter/gather copy for SEC1 crypto: talitos - SEC1 bugs on 0 data hash crypto: talitos - Add fsl,sec1.0 compatible crypto: talitos - Update DT bindings with SEC1 .../devicetree/bindings/crypto/fsl-sec2.txt| 6 +- drivers/crypto/Kconfig | 18 + drivers/crypto/talitos.c | 727 +++-- drivers/crypto/talitos.h | 153 +++-- 4 files changed, 644 insertions(+), 260 deletions(-) ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v3 00/17] crypto: talitos - Add support for SEC1
The purpose of this set of patchs is to add to talitos crypto driver the support for the SEC1 version of the security engine, which is found in mpc885 and mpc8272 processors. v3 is a complete rework of the patchset. Since a kernel can be built with support for both MPC82xx and MPC83xx at the same time, talitos driver shall support both SEC1 and SEC2+ at the same time. Based on cryptodev-2.6 tree Christophe Leroy (17): crypto: talitos - Use zero entry to init descriptors ptrs to zero crypto: talitos - Refactor the sg in/out chain allocation crypto: talitos - talitos_ptr renamed ptr for more lisibility crypto: talitos - Add a helper function to clear j_extent field crypto: talitos - remove param 'extent' in map_single_talitos_ptr() crypto: talitos - helper function for ptr len crypto: talitos - enhanced talitos_desc struct for SEC1 crypto: talitos - add sub-choice in talitos CONFIG for SEC1 crypto: talitos - Add a feature to tag SEC1 crypto: talitos - fill in talitos descriptor iaw SEC1 or SEC2+ crypto: talitos - adaptation of talitos_submit() for SEC1 crypto: talitos - base address for Execution Units crypto: talitos - adapt interrupts and reset functions to SEC1 crypto: talitos - implement scatter/gather copy for SEC1 crypto: talitos - SEC1 bugs on 0 data hash crypto: talitos - Add fsl,sec1.0 compatible crypto: talitos - Update DT bindings with SEC1 .../devicetree/bindings/crypto/fsl-sec2.txt| 6 +- drivers/crypto/Kconfig | 18 + drivers/crypto/talitos.c | 727 +++-- drivers/crypto/talitos.h | 153 +++-- 4 files changed, 644 insertions(+), 260 deletions(-) -- 2.1.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v3 01/17] crypto: talitos - Use zero entry to init descriptors ptrs to zero
Do use zero_entry value to init the descriptors ptrs to zero instead of
writing 0 in each field
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 857414a..7bf1b2b 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -1373,9 +1373,7 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
int sg_count, ret;
/* first DWORD empty */
- desc-ptr[0].len = 0;
- to_talitos_ptr(desc-ptr[0], 0);
- desc-ptr[0].j_extent = 0;
+ desc-ptr[0] = zero_entry;
/* cipher iv */
to_talitos_ptr(desc-ptr[1], edesc-iv_dma);
@@ -1445,9 +1443,7 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
DMA_FROM_DEVICE);
/* last DWORD empty */
- desc-ptr[6].len = 0;
- to_talitos_ptr(desc-ptr[6], 0);
- desc-ptr[6].j_extent = 0;
+ desc-ptr[6] = zero_entry;
ret = talitos_submit(dev, ctx-ch, desc, callback, areq);
if (ret != -EINPROGRESS) {
--
2.1.0
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[PATCH v3 02/17] crypto: talitos - Refactor the sg in/out chain allocation
This patch refactors the handling of the input and output data that is quite
similar in several functions
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 159 ---
1 file changed, 81 insertions(+), 78 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 7bf1b2b..5a7e345 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -1327,16 +1327,23 @@ static int ablkcipher_setkey(struct crypto_ablkcipher
*cipher,
return 0;
}
+static void unmap_sg_talitos_ptr(struct device *dev, struct scatterlist *src,
+struct scatterlist *dst, unsigned int len,
+struct talitos_edesc *edesc)
+{
+ talitos_sg_unmap(dev, edesc, src, dst);
+}
+
static void common_nonsnoop_unmap(struct device *dev,
struct talitos_edesc *edesc,
struct ablkcipher_request *areq)
{
unmap_single_talitos_ptr(dev, edesc-desc.ptr[5], DMA_FROM_DEVICE);
+
+ unmap_sg_talitos_ptr(dev, areq-src, areq-dst, areq-nbytes, edesc);
unmap_single_talitos_ptr(dev, edesc-desc.ptr[2], DMA_TO_DEVICE);
unmap_single_talitos_ptr(dev, edesc-desc.ptr[1], DMA_TO_DEVICE);
- talitos_sg_unmap(dev, edesc, areq-src, areq-dst);
-
if (edesc-dma_len)
dma_unmap_single(dev, edesc-dma_link_tbl, edesc-dma_len,
DMA_BIDIRECTIONAL);
@@ -1358,6 +1365,65 @@ static void ablkcipher_done(struct device *dev,
areq-base.complete(areq-base, err);
}
+int map_sg_in_talitos_ptr(struct device *dev, struct scatterlist *src,
+ unsigned int len, struct talitos_edesc *edesc,
+ enum dma_data_direction dir, struct talitos_ptr *ptr)
+{
+ int sg_count;
+
+ ptr-len = cpu_to_be16(len);
+ ptr-j_extent = 0;
+
+ sg_count = talitos_map_sg(dev, src, edesc-src_nents ? : 1, dir,
+ edesc-src_chained);
+
+ if (sg_count == 1) {
+ to_talitos_ptr(ptr, sg_dma_address(src));
+ } else {
+ sg_count = sg_to_link_tbl(src, sg_count, len,
+ edesc-link_tbl[0]);
+ if (sg_count 1) {
+ to_talitos_ptr(ptr, edesc-dma_link_tbl);
+ ptr-j_extent |= DESC_PTR_LNKTBL_JUMP;
+ dma_sync_single_for_device(dev, edesc-dma_link_tbl,
+ edesc-dma_len,
+ DMA_BIDIRECTIONAL);
+ } else {
+ /* Only one segment now, so no link tbl needed */
+ to_talitos_ptr(ptr, sg_dma_address(src));
+ }
+ }
+ return sg_count;
+}
+
+void map_sg_out_talitos_ptr(struct device *dev, struct scatterlist *dst,
+ unsigned int len, struct talitos_edesc *edesc,
+ enum dma_data_direction dir,
+ struct talitos_ptr *ptr, int sg_count)
+{
+ ptr-len = cpu_to_be16(len);
+ ptr-j_extent = 0;
+
+ if (dir != DMA_NONE)
+ sg_count = talitos_map_sg(dev, dst, edesc-dst_nents ? : 1,
+ dir, edesc-dst_chained);
+
+ if (sg_count == 1) {
+ to_talitos_ptr(ptr, sg_dma_address(dst));
+ } else {
+ struct talitos_ptr *link_tbl_ptr =
+ edesc-link_tbl[edesc-src_nents + 1];
+
+ to_talitos_ptr(ptr, edesc-dma_link_tbl +
+ (edesc-src_nents + 1) *
+ sizeof(struct talitos_ptr));
+ ptr-j_extent |= DESC_PTR_LNKTBL_JUMP;
+ sg_count = sg_to_link_tbl(dst, sg_count, len, link_tbl_ptr);
+ dma_sync_single_for_device(dev, edesc-dma_link_tbl,
+ edesc-dma_len, DMA_BIDIRECTIONAL);
+ }
+}
+
static int common_nonsnoop(struct talitos_edesc *edesc,
struct ablkcipher_request *areq,
void (*callback) (struct device *dev,
@@ -1387,56 +1453,16 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
/*
* cipher in
*/
- desc-ptr[3].len = cpu_to_be16(cryptlen);
- desc-ptr[3].j_extent = 0;
-
- sg_count = talitos_map_sg(dev, areq-src, edesc-src_nents ? : 1,
- (areq-src == areq-dst) ? DMA_BIDIRECTIONAL
- : DMA_TO_DEVICE,
- edesc-src_chained);
-
- if (sg_count == 1) {
- to_talitos_ptr(desc-ptr[3], sg_dma_address(areq-src));
- } else {
- sg_count = sg_to_link_tbl(areq-src,
[PATCH 3.19 097/101] timers/tick/broadcast-hrtimer: Fix suspicious RCU usage in idle loop
3.19-stable review patch. If anyone has any objections, please let me know.
--
From: Preeti U Murthy pre...@linux.vnet.ibm.com
commit a127d2bcf1fbc8c8e0b5cf0dab54f7d3ff50ce47 upstream.
The hrtimer mode of broadcast queues hrtimers in the idle entry
path so as to wakeup cpus in deep idle states. The associated
call graph is :
cpuidle_idle_call()
| clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, ))
|_tick_broadcast_set_event()
|clockevents_program_event()
|bc_set_next()
The hrtimer_{start/cancel} functions call into tracing which uses RCU.
But it is not legal to call into RCU in cpuidle because it is one of the
quiescent states. Hence protect this region with RCU_NONIDLE which informs
RCU that the cpu is momentarily non-idle.
As an aside it is helpful to point out that the clock event device that is
programmed here is not a per-cpu clock device; it is a
pseudo clock device, used by the broadcast framework alone.
The per-cpu clock device programming never goes through bc_set_next().
Signed-off-by: Preeti U Murthy pre...@linux.vnet.ibm.com
Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
Reviewed-by: Paul E. McKenney paul...@linux.vnet.ibm.com
Cc: linuxppc-...@ozlabs.org
Cc: m...@ellerman.id.au
Cc: t...@linutronix.de
Link:
http://lkml.kernel.org/r/20150318104705.17763.56668.st...@preeti.in.ibm.com
Signed-off-by: Ingo Molnar mi...@kernel.org
Signed-off-by: Greg Kroah-Hartman gre...@linuxfoundation.org
---
kernel/time/tick-broadcast-hrtimer.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
--- a/kernel/time/tick-broadcast-hrtimer.c
+++ b/kernel/time/tick-broadcast-hrtimer.c
@@ -49,6 +49,7 @@ static void bc_set_mode(enum clock_event
*/
static int bc_set_next(ktime_t expires, struct clock_event_device *bc)
{
+ int bc_moved;
/*
* We try to cancel the timer first. If the callback is on
* flight on some other cpu then we let it handle it. If we
@@ -60,9 +61,15 @@ static int bc_set_next(ktime_t expires,
* restart the timer because we are in the callback, but we
* can set the expiry time and let the callback return
* HRTIMER_RESTART.
+*
+* Since we are in the idle loop at this point and because
+* hrtimer_{start/cancel} functions call into tracing,
+* calls to these functions must be bound within RCU_NONIDLE.
*/
- if (hrtimer_try_to_cancel(bctimer) = 0) {
- hrtimer_start(bctimer, expires, HRTIMER_MODE_ABS_PINNED);
+ RCU_NONIDLE(bc_moved = (hrtimer_try_to_cancel(bctimer) = 0) ?
+ !hrtimer_start(bctimer, expires, HRTIMER_MODE_ABS_PINNED) :
+ 0);
+ if (bc_moved) {
/* Bind the device to the cpu */
bc-bound_on = smp_processor_id();
} else if (bc-bound_on == smp_processor_id()) {
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Re: [PATCH kernel v8 14/31] vfio: powerpc/spapr: powerpc/powernv/ioda2: Rework IOMMU ownership control
On 04/16/2015 04:07 PM, David Gibson wrote:
On Fri, Apr 10, 2015 at 04:30:56PM +1000, Alexey Kardashevskiy wrote:
At the moment the iommu_table struct has a set_bypass() which enables/
disables DMA bypass on IODA2 PHB. This is exposed to POWERPC IOMMU code
which calls this callback when external IOMMU users such as VFIO are
about to get over a PHB.
The set_bypass() callback is not really an iommu_table function but
IOMMU/PE function. This introduces a iommu_table_group_ops struct and
adds a set_ownership() callback to it which is called when an external
user takes control over the IOMMU.
Do you really need separate ops structures at both the single table
and table group level? The different tables in a group will all
belong to the same basic iommu won't they?
IOMMU tables exist alone in VIO. Also, the platform code uses just a table
(or it is in bypass mode) and does not care about table groups. It looked
more clean for myself to keep them separated. Should I still merge those?
This renames set_bypass() to set_ownership() as it is not necessarily
just enabling bypassing, it can be something else/more so let's give it
more generic name. The bool parameter is inverted.
The callback is implemented for IODA2 only. Other platforms (P5IOC2,
IODA1) will use the old iommu_take_ownership/iommu_release_ownership API.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
arch/powerpc/include/asm/iommu.h | 14 +-
arch/powerpc/platforms/powernv/pci-ioda.c | 30 ++
drivers/vfio/vfio_iommu_spapr_tce.c | 25 +
3 files changed, 56 insertions(+), 13 deletions(-)
diff --git a/arch/powerpc/include/asm/iommu.h b/arch/powerpc/include/asm/iommu.h
index b9e50d3..d1f8c6c 100644
--- a/arch/powerpc/include/asm/iommu.h
+++ b/arch/powerpc/include/asm/iommu.h
@@ -92,7 +92,6 @@ struct iommu_table {
unsigned long it_page_shift;/* table iommu page size */
struct iommu_table_group *it_group;
struct iommu_table_ops *it_ops;
- void (*set_bypass)(struct iommu_table *tbl, bool enable);
};
/* Pure 2^n version of get_order */
@@ -127,11 +126,24 @@ extern struct iommu_table *iommu_init_table(struct
iommu_table * tbl,
#define IOMMU_TABLE_GROUP_MAX_TABLES 1
+struct iommu_table_group;
+
+struct iommu_table_group_ops {
+ /*
+* Switches ownership from the kernel itself to an external
+* user. While onwership is enabled, the kernel cannot use IOMMU
+* for itself.
+*/
+ void (*set_ownership)(struct iommu_table_group *table_group,
+ bool enable);
The meaning of enable in a function called set_ownership is
entirely obscure.
Suggest something better please :) I have nothing better...
+};
+
struct iommu_table_group {
#ifdef CONFIG_IOMMU_API
struct iommu_group *group;
#endif
struct iommu_table tables[IOMMU_TABLE_GROUP_MAX_TABLES];
+ struct iommu_table_group_ops *ops;
};
#ifdef CONFIG_IOMMU_API
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c
b/arch/powerpc/platforms/powernv/pci-ioda.c
index a964c50..9687731 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -1255,10 +1255,8 @@ static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb
*phb,
__free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs));
}
-static void pnv_pci_ioda2_set_bypass(struct iommu_table *tbl, bool enable)
+static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
{
- struct pnv_ioda_pe *pe = container_of(tbl-it_group, struct pnv_ioda_pe,
- table_group);
uint16_t window_id = (pe-pe_number 1 ) + 1;
int64_t rc;
@@ -1286,7 +1284,8 @@ static void pnv_pci_ioda2_set_bypass(struct iommu_table
*tbl, bool enable)
* host side.
*/
if (pe-pdev)
- set_iommu_table_base(pe-pdev-dev, tbl);
+ set_iommu_table_base(pe-pdev-dev,
+ pe-table_group.tables[0]);
else
pnv_ioda_setup_bus_dma(pe, pe-pbus, false);
}
@@ -1302,13 +1301,27 @@ static void pnv_pci_ioda2_setup_bypass_pe(struct
pnv_phb *phb,
/* TVE #1 is selected by PCI address bit 59 */
pe-tce_bypass_base = 1ull 59;
- /* Install set_bypass callback for VFIO */
- pe-table_group.tables[0].set_bypass = pnv_pci_ioda2_set_bypass;
-
/* Enable bypass by default */
- pnv_pci_ioda2_set_bypass(pe-table_group.tables[0], true);
+ pnv_pci_ioda2_set_bypass(pe, true);
}
+static void pnv_ioda2_set_ownership(struct iommu_table_group *table_group,
+bool enable)
+{
+ struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
+
Re: [PATCH kernel v8 17/31] powerpc/iommu/powernv: Release replaced TCE
On 04/16/2015 04:26 PM, David Gibson wrote:
On Fri, Apr 10, 2015 at 04:30:59PM +1000, Alexey Kardashevskiy wrote:
At the moment writing new TCE value to the IOMMU table fails with EBUSY
if there is a valid entry already. However PAPR specification allows
the guest to write new TCE value without clearing it first.
Another problem this patch is addressing is the use of pool locks for
external IOMMU users such as VFIO. The pool locks are to protect
DMA page allocator rather than entries and since the host kernel does
not control what pages are in use, there is no point in pool locks and
exchange()+put_page(oldtce) is sufficient to avoid possible races.
This adds an exchange() callback to iommu_table_ops which does the same
thing as set() plus it returns replaced TCE and DMA direction so
the caller can release the pages afterwards.
The returned old TCE value is a virtual address as the new TCE value.
This is different from tce_clear() which returns a physical address.
This implements exchange() for P5IOC2/IODA/IODA2. This adds a requirement
for a platform to have exchange() implemented in order to support VFIO.
This replaces iommu_tce_build() and iommu_clear_tce() with
a single iommu_tce_xchg().
This makes sure that TCE permission bits are not set in TCE passed to
IOMMU API as those are to be calculated by platform code from DMA direction.
This moves SetPageDirty() to the IOMMU code to make it work for both
VFIO ioctl interface in in-kernel TCE acceleration (when it becomes
available later).
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
arch/powerpc/include/asm/iommu.h| 17 ++--
arch/powerpc/kernel/iommu.c | 53 +---
arch/powerpc/platforms/powernv/pci-ioda.c | 38 ++
arch/powerpc/platforms/powernv/pci-p5ioc2.c | 3 ++
arch/powerpc/platforms/powernv/pci.c| 17
arch/powerpc/platforms/powernv/pci.h| 2 +
drivers/vfio/vfio_iommu_spapr_tce.c | 62 ++---
7 files changed, 130 insertions(+), 62 deletions(-)
diff --git a/arch/powerpc/include/asm/iommu.h b/arch/powerpc/include/asm/iommu.h
index d1f8c6c..bde7ee7 100644
--- a/arch/powerpc/include/asm/iommu.h
+++ b/arch/powerpc/include/asm/iommu.h
@@ -44,11 +44,22 @@ extern int iommu_is_off;
extern int iommu_force_on;
struct iommu_table_ops {
+ /* When called with direction==DMA_NONE, it is equal to clear() */
int (*set)(struct iommu_table *tbl,
long index, long npages,
unsigned long uaddr,
enum dma_data_direction direction,
struct dma_attrs *attrs);
+#ifdef CONFIG_IOMMU_API
+ /*
+* Exchanges existing TCE with new TCE plus direction bits;
+* returns old TCE and DMA direction mask
+*/
+ int (*exchange)(struct iommu_table *tbl,
+ long index,
+ unsigned long *tce,
+ enum dma_data_direction *direction);
+#endif
void (*clear)(struct iommu_table *tbl,
long index, long npages);
unsigned long (*get)(struct iommu_table *tbl, long index);
@@ -152,6 +163,8 @@ extern void iommu_register_group(struct iommu_table_group
*table_group,
extern int iommu_add_device(struct device *dev);
extern void iommu_del_device(struct device *dev);
extern int __init tce_iommu_bus_notifier_init(void);
+extern long iommu_tce_xchg(struct iommu_table *tbl, unsigned long entry,
+ unsigned long *tce, enum dma_data_direction *direction);
#else
static inline void iommu_register_group(struct iommu_table_group *table_group,
int pci_domain_number,
@@ -231,10 +244,6 @@ extern int iommu_tce_clear_param_check(struct iommu_table
*tbl,
unsigned long npages);
extern int iommu_tce_put_param_check(struct iommu_table *tbl,
unsigned long ioba, unsigned long tce);
-extern int iommu_tce_build(struct iommu_table *tbl, unsigned long entry,
- unsigned long hwaddr, enum dma_data_direction direction);
-extern unsigned long iommu_clear_tce(struct iommu_table *tbl,
- unsigned long entry);
extern void iommu_flush_tce(struct iommu_table *tbl);
extern int iommu_take_ownership(struct iommu_table_group *table_group);
diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c
index 068fe4ff..501e8ee 100644
--- a/arch/powerpc/kernel/iommu.c
+++ b/arch/powerpc/kernel/iommu.c
@@ -982,9 +982,6 @@ EXPORT_SYMBOL_GPL(iommu_tce_clear_param_check);
int iommu_tce_put_param_check(struct iommu_table *tbl,
unsigned long ioba, unsigned long tce)
{
- if (!(tce (TCE_PCI_WRITE | TCE_PCI_READ)))
- return -EINVAL;
-
if (tce ~(IOMMU_PAGE_MASK(tbl) | TCE_PCI_WRITE | TCE_PCI_READ))
return -EINVAL;
@@ -1002,44 +999,20 @@ int
Re: [PATCH kernel v8 15/31] powerpc/iommu: Fix IOMMU ownership control functions
On 04/16/2015 04:10 PM, David Gibson wrote:
On Fri, Apr 10, 2015 at 04:30:57PM +1000, Alexey Kardashevskiy wrote:
This adds missing locks in iommu_take_ownership()/
iommu_release_ownership().
This marks all pages busy in iommu_table::it_map in order to catch
errors if there is an attempt to use this table while ownership over it
is taken.
This only clears TCE content if there is no page marked busy in it_map.
Clearing must be done outside of the table locks as iommu_clear_tce()
called from iommu_clear_tces_and_put_pages() does this.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
Changes:
v5:
* do not store bit#0 value, it has to be set for zero-based table
anyway
* removed test_and_clear_bit
---
arch/powerpc/kernel/iommu.c | 26 ++
1 file changed, 22 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c
index 7d6089b..068fe4ff 100644
--- a/arch/powerpc/kernel/iommu.c
+++ b/arch/powerpc/kernel/iommu.c
@@ -1052,17 +1052,28 @@ EXPORT_SYMBOL_GPL(iommu_tce_build);
static int iommu_table_take_ownership(struct iommu_table *tbl)
{
- unsigned long sz = (tbl-it_size + 7) 3;
+ unsigned long flags, i, sz = (tbl-it_size + 7) 3;
+ int ret = 0;
+
+ spin_lock_irqsave(tbl-large_pool.lock, flags);
+ for (i = 0; i tbl-nr_pools; i++)
+ spin_lock(tbl-pools[i].lock);
if (tbl-it_offset == 0)
clear_bit(0, tbl-it_map);
if (!bitmap_empty(tbl-it_map, tbl-it_size)) {
pr_err(iommu_tce: it_map is not empty);
- return -EBUSY;
+ ret = -EBUSY;
+ if (tbl-it_offset == 0)
+ set_bit(0, tbl-it_map);
This really needs a comment. Why on earth are you changing the it_map
on a failure case?
Does this explain?
/*
* The platform code reserves zero address in iommu_init_table().
* As we cleared busy bit for page @0 before using bitmap_empty(),
* we are restoring it now.
*/
+ } else {
+ memset(tbl-it_map, 0xff, sz);
}
- memset(tbl-it_map, 0xff, sz);
+ for (i = 0; i tbl-nr_pools; i++)
+ spin_unlock(tbl-pools[i].lock);
+ spin_unlock_irqrestore(tbl-large_pool.lock, flags);
return 0;
}
@@ -1095,7 +1106,11 @@ EXPORT_SYMBOL_GPL(iommu_take_ownership);
static void iommu_table_release_ownership(struct iommu_table *tbl)
{
- unsigned long sz = (tbl-it_size + 7) 3;
+ unsigned long flags, i, sz = (tbl-it_size + 7) 3;
+
+ spin_lock_irqsave(tbl-large_pool.lock, flags);
+ for (i = 0; i tbl-nr_pools; i++)
+ spin_lock(tbl-pools[i].lock);
memset(tbl-it_map, 0, sz);
@@ -1103,6 +1118,9 @@ static void iommu_table_release_ownership(struct
iommu_table *tbl)
if (tbl-it_offset == 0)
set_bit(0, tbl-it_map);
+ for (i = 0; i tbl-nr_pools; i++)
+ spin_unlock(tbl-pools[i].lock);
+ spin_unlock_irqrestore(tbl-large_pool.lock, flags);
}
extern void iommu_release_ownership(struct iommu_table_group *table_group)
--
Alexey
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[PATCH v3 01/17] crypto: talitos - Use zero entry to init descriptors ptrs to zero
Do use zero_entry value to init the descriptors ptrs to zero instead of
writing 0 in each field
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 857414a..7bf1b2b 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -1373,9 +1373,7 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
int sg_count, ret;
/* first DWORD empty */
- desc-ptr[0].len = 0;
- to_talitos_ptr(desc-ptr[0], 0);
- desc-ptr[0].j_extent = 0;
+ desc-ptr[0] = zero_entry;
/* cipher iv */
to_talitos_ptr(desc-ptr[1], edesc-iv_dma);
@@ -1445,9 +1443,7 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
DMA_FROM_DEVICE);
/* last DWORD empty */
- desc-ptr[6].len = 0;
- to_talitos_ptr(desc-ptr[6], 0);
- desc-ptr[6].j_extent = 0;
+ desc-ptr[6] = zero_entry;
ret = talitos_submit(dev, ctx-ch, desc, callback, areq);
if (ret != -EINPROGRESS) {
--
2.1.0
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[PATCH v3 03/17] crypto: talitos - talitos_ptr renamed ptr for more lisibility
Linux CodyingStyle recommends to use short variables for local
variables. ptr is just good enough for those 3 lines functions.
It helps keep single lines shorter than 80 characters.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 5a7e345..fca0aed 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -55,37 +55,37 @@
#include talitos.h
-static void to_talitos_ptr(struct talitos_ptr *talitos_ptr, dma_addr_t
dma_addr)
+static void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr)
{
- talitos_ptr-ptr = cpu_to_be32(lower_32_bits(dma_addr));
- talitos_ptr-eptr = upper_32_bits(dma_addr);
+ ptr-ptr = cpu_to_be32(lower_32_bits(dma_addr));
+ ptr-eptr = upper_32_bits(dma_addr);
}
/*
* map virtual single (contiguous) pointer to h/w descriptor pointer
*/
static void map_single_talitos_ptr(struct device *dev,
- struct talitos_ptr *talitos_ptr,
+ struct talitos_ptr *ptr,
unsigned short len, void *data,
unsigned char extent,
enum dma_data_direction dir)
{
dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
- talitos_ptr-len = cpu_to_be16(len);
- to_talitos_ptr(talitos_ptr, dma_addr);
- talitos_ptr-j_extent = extent;
+ ptr-len = cpu_to_be16(len);
+ to_talitos_ptr(ptr, dma_addr);
+ ptr-j_extent = extent;
}
/*
* unmap bus single (contiguous) h/w descriptor pointer
*/
static void unmap_single_talitos_ptr(struct device *dev,
-struct talitos_ptr *talitos_ptr,
+struct talitos_ptr *ptr,
enum dma_data_direction dir)
{
- dma_unmap_single(dev, be32_to_cpu(talitos_ptr-ptr),
-be16_to_cpu(talitos_ptr-len), dir);
+ dma_unmap_single(dev, be32_to_cpu(ptr-ptr),
+be16_to_cpu(ptr-len), dir);
}
static int reset_channel(struct device *dev, int ch)
--
2.1.0
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[PATCH v3 07/17] crypto: talitos - enhanced talitos_desc struct for SEC1
This patch enhances the talitos_desc struct with fields for SEC1.
SEC1 has only one header field, and has a 'next_desc' field in
addition.
This mixed descriptor will continue to fit SEC2, and for SEC1
we will recopy hdr value into hdr1 value in talitos_submit()
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.h | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/crypto/talitos.h b/drivers/crypto/talitos.h
index 61a1405..f078da1 100644
--- a/drivers/crypto/talitos.h
+++ b/drivers/crypto/talitos.h
@@ -37,9 +37,17 @@
/* descriptor pointer entry */
struct talitos_ptr {
- __be16 len; /* length */
- u8 j_extent;/* jump to sg link table and/or extent */
- u8 eptr;/* extended address */
+ union {
+ struct {/* SEC2 format */
+ __be16 len; /* length */
+ u8 j_extent;/* jump to sg link table and/or extent*/
+ u8 eptr;/* extended address */
+ };
+ struct {/* SEC1 format */
+ __be16 res;
+ __be16 len1;/* length */
+ };
+ };
__be32 ptr; /* address */
};
@@ -53,8 +61,12 @@ static const struct talitos_ptr zero_entry = {
/* descriptor */
struct talitos_desc {
__be32 hdr; /* header high bits */
- __be32 hdr_lo; /* header low bits */
+ union {
+ __be32 hdr_lo; /* header low bits */
+ __be32 hdr1;/* header for SEC1 */
+ };
struct talitos_ptr ptr[7]; /* ptr/len pair array */
+ __be32 next_desc; /* next descriptor (SEC1) */
};
/**
--
2.1.0
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[PATCH v3 00/17] crypto: talitos - Add support for SEC1
The purpose of this set of patchs is to add to talitos crypto driver the support for the SEC1 version of the security engine, which is found in mpc885 and mpc8272 processors. v3 is a complete rework of the patchset. Since a kernel can be built with support for both MPC82xx and MPC83xx at the same time, talitos driver shall support both SEC1 and SEC2+ at the same time. Based on cryptodev-2.6 tree Christophe Leroy (17): crypto: talitos - Use zero entry to init descriptors ptrs to zero crypto: talitos - Refactor the sg in/out chain allocation crypto: talitos - talitos_ptr renamed ptr for more lisibility crypto: talitos - Add a helper function to clear j_extent field crypto: talitos - remove param 'extent' in map_single_talitos_ptr() crypto: talitos - helper function for ptr len crypto: talitos - enhanced talitos_desc struct for SEC1 crypto: talitos - add sub-choice in talitos CONFIG for SEC1 crypto: talitos - Add a feature to tag SEC1 crypto: talitos - fill in talitos descriptor iaw SEC1 or SEC2+ crypto: talitos - adaptation of talitos_submit() for SEC1 crypto: talitos - base address for Execution Units crypto: talitos - adapt interrupts and reset functions to SEC1 crypto: talitos - implement scatter/gather copy for SEC1 crypto: talitos - SEC1 bugs on 0 data hash crypto: talitos - Add fsl,sec1.0 compatible crypto: talitos - Update DT bindings with SEC1 .../devicetree/bindings/crypto/fsl-sec2.txt| 6 +- drivers/crypto/Kconfig | 18 + drivers/crypto/talitos.c | 727 +++-- drivers/crypto/talitos.h | 153 +++-- 4 files changed, 644 insertions(+), 260 deletions(-) -- 2.1.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v3 02/17] crypto: talitos - Refactor the sg in/out chain allocation
This patch refactors the handling of the input and output data that is quite
similar in several functions
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 159 ---
1 file changed, 81 insertions(+), 78 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 7bf1b2b..5a7e345 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -1327,16 +1327,23 @@ static int ablkcipher_setkey(struct crypto_ablkcipher
*cipher,
return 0;
}
+static void unmap_sg_talitos_ptr(struct device *dev, struct scatterlist *src,
+struct scatterlist *dst, unsigned int len,
+struct talitos_edesc *edesc)
+{
+ talitos_sg_unmap(dev, edesc, src, dst);
+}
+
static void common_nonsnoop_unmap(struct device *dev,
struct talitos_edesc *edesc,
struct ablkcipher_request *areq)
{
unmap_single_talitos_ptr(dev, edesc-desc.ptr[5], DMA_FROM_DEVICE);
+
+ unmap_sg_talitos_ptr(dev, areq-src, areq-dst, areq-nbytes, edesc);
unmap_single_talitos_ptr(dev, edesc-desc.ptr[2], DMA_TO_DEVICE);
unmap_single_talitos_ptr(dev, edesc-desc.ptr[1], DMA_TO_DEVICE);
- talitos_sg_unmap(dev, edesc, areq-src, areq-dst);
-
if (edesc-dma_len)
dma_unmap_single(dev, edesc-dma_link_tbl, edesc-dma_len,
DMA_BIDIRECTIONAL);
@@ -1358,6 +1365,65 @@ static void ablkcipher_done(struct device *dev,
areq-base.complete(areq-base, err);
}
+int map_sg_in_talitos_ptr(struct device *dev, struct scatterlist *src,
+ unsigned int len, struct talitos_edesc *edesc,
+ enum dma_data_direction dir, struct talitos_ptr *ptr)
+{
+ int sg_count;
+
+ ptr-len = cpu_to_be16(len);
+ ptr-j_extent = 0;
+
+ sg_count = talitos_map_sg(dev, src, edesc-src_nents ? : 1, dir,
+ edesc-src_chained);
+
+ if (sg_count == 1) {
+ to_talitos_ptr(ptr, sg_dma_address(src));
+ } else {
+ sg_count = sg_to_link_tbl(src, sg_count, len,
+ edesc-link_tbl[0]);
+ if (sg_count 1) {
+ to_talitos_ptr(ptr, edesc-dma_link_tbl);
+ ptr-j_extent |= DESC_PTR_LNKTBL_JUMP;
+ dma_sync_single_for_device(dev, edesc-dma_link_tbl,
+ edesc-dma_len,
+ DMA_BIDIRECTIONAL);
+ } else {
+ /* Only one segment now, so no link tbl needed */
+ to_talitos_ptr(ptr, sg_dma_address(src));
+ }
+ }
+ return sg_count;
+}
+
+void map_sg_out_talitos_ptr(struct device *dev, struct scatterlist *dst,
+ unsigned int len, struct talitos_edesc *edesc,
+ enum dma_data_direction dir,
+ struct talitos_ptr *ptr, int sg_count)
+{
+ ptr-len = cpu_to_be16(len);
+ ptr-j_extent = 0;
+
+ if (dir != DMA_NONE)
+ sg_count = talitos_map_sg(dev, dst, edesc-dst_nents ? : 1,
+ dir, edesc-dst_chained);
+
+ if (sg_count == 1) {
+ to_talitos_ptr(ptr, sg_dma_address(dst));
+ } else {
+ struct talitos_ptr *link_tbl_ptr =
+ edesc-link_tbl[edesc-src_nents + 1];
+
+ to_talitos_ptr(ptr, edesc-dma_link_tbl +
+ (edesc-src_nents + 1) *
+ sizeof(struct talitos_ptr));
+ ptr-j_extent |= DESC_PTR_LNKTBL_JUMP;
+ sg_count = sg_to_link_tbl(dst, sg_count, len, link_tbl_ptr);
+ dma_sync_single_for_device(dev, edesc-dma_link_tbl,
+ edesc-dma_len, DMA_BIDIRECTIONAL);
+ }
+}
+
static int common_nonsnoop(struct talitos_edesc *edesc,
struct ablkcipher_request *areq,
void (*callback) (struct device *dev,
@@ -1387,56 +1453,16 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
/*
* cipher in
*/
- desc-ptr[3].len = cpu_to_be16(cryptlen);
- desc-ptr[3].j_extent = 0;
-
- sg_count = talitos_map_sg(dev, areq-src, edesc-src_nents ? : 1,
- (areq-src == areq-dst) ? DMA_BIDIRECTIONAL
- : DMA_TO_DEVICE,
- edesc-src_chained);
-
- if (sg_count == 1) {
- to_talitos_ptr(desc-ptr[3], sg_dma_address(areq-src));
- } else {
- sg_count = sg_to_link_tbl(areq-src,
[PATCH v3 06/17] crypto: talitos - helper function for ptr len
This patch adds a helper function for reads and writes of the len
param of the talitos descriptor. This will help implement
SEC1 later.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 81e5636..bca6ded 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -61,6 +61,16 @@ static void to_talitos_ptr(struct talitos_ptr *ptr,
dma_addr_t dma_addr)
ptr-eptr = upper_32_bits(dma_addr);
}
+static void to_talitos_ptr_len(struct talitos_ptr *ptr, unsigned short len)
+{
+ ptr-len = cpu_to_be16(len);
+}
+
+static unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr)
+{
+ return be16_to_cpu(ptr-len);
+}
+
static void to_talitos_ptr_extent_clear(struct talitos_ptr *ptr)
{
ptr-j_extent = 0;
@@ -76,7 +86,7 @@ static void map_single_talitos_ptr(struct device *dev,
{
dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
- ptr-len = cpu_to_be16(len);
+ to_talitos_ptr_len(ptr, len);
to_talitos_ptr(ptr, dma_addr);
to_talitos_ptr_extent_clear(ptr);
}
@@ -89,7 +99,7 @@ static void unmap_single_talitos_ptr(struct device *dev,
enum dma_data_direction dir)
{
dma_unmap_single(dev, be32_to_cpu(ptr-ptr),
-be16_to_cpu(ptr-len), dir);
+from_talitos_ptr_len(ptr), dir);
}
static int reset_channel(struct device *dev, int ch)
@@ -1375,7 +1385,7 @@ int map_sg_in_talitos_ptr(struct device *dev, struct
scatterlist *src,
{
int sg_count;
- ptr-len = cpu_to_be16(len);
+ to_talitos_ptr_len(ptr, len);
to_talitos_ptr_extent_clear(ptr);
sg_count = talitos_map_sg(dev, src, edesc-src_nents ? : 1, dir,
@@ -1405,7 +1415,7 @@ void map_sg_out_talitos_ptr(struct device *dev, struct
scatterlist *dst,
enum dma_data_direction dir,
struct talitos_ptr *ptr, int sg_count)
{
- ptr-len = cpu_to_be16(len);
+ to_talitos_ptr_len(ptr, len);
to_talitos_ptr_extent_clear(ptr);
if (dir != DMA_NONE)
@@ -1447,7 +1457,7 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
/* cipher iv */
to_talitos_ptr(desc-ptr[1], edesc-iv_dma);
- desc-ptr[1].len = cpu_to_be16(ivsize);
+ to_talitos_ptr_len(desc-ptr[1], ivsize);
to_talitos_ptr_extent_clear(desc-ptr[1]);
/* cipher key */
@@ -1539,11 +1549,11 @@ static void common_nonsnoop_hash_unmap(struct device
*dev,
unmap_sg_talitos_ptr(dev, req_ctx-psrc, NULL, 0, edesc);
/* When using hashctx-in, must unmap it. */
- if (edesc-desc.ptr[1].len)
+ if (from_talitos_ptr_len(edesc-desc.ptr[1]))
unmap_single_talitos_ptr(dev, edesc-desc.ptr[1],
DMA_TO_DEVICE);
- if (edesc-desc.ptr[2].len)
+ if (from_talitos_ptr_len(edesc-desc.ptr[2]))
unmap_single_talitos_ptr(dev, edesc-desc.ptr[2],
DMA_TO_DEVICE);
--
2.1.0
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[PATCH v3 05/17] crypto: talitos - remove param 'extent' in map_single_talitos_ptr()
map_single_talitos_ptr() is always called with extent == 0, so lets remove this
unused parameter
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 21 ++---
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index c93f79b..81e5636 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -72,14 +72,13 @@ static void to_talitos_ptr_extent_clear(struct talitos_ptr
*ptr)
static void map_single_talitos_ptr(struct device *dev,
struct talitos_ptr *ptr,
unsigned short len, void *data,
- unsigned char extent,
enum dma_data_direction dir)
{
dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
ptr-len = cpu_to_be16(len);
to_talitos_ptr(ptr, dma_addr);
- ptr-j_extent = extent;
+ to_talitos_ptr_extent_clear(ptr);
}
/*
@@ -958,7 +957,7 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct
aead_request *areq,
/* hmac key */
map_single_talitos_ptr(dev, desc-ptr[0], ctx-authkeylen, ctx-key,
- 0, DMA_TO_DEVICE);
+ DMA_TO_DEVICE);
/* hmac data */
desc-ptr[1].len = cpu_to_be16(areq-assoclen + ivsize);
@@ -1002,7 +1001,7 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct
aead_request *areq,
/* cipher key */
map_single_talitos_ptr(dev, desc-ptr[3], ctx-enckeylen,
- (char *)ctx-key + ctx-authkeylen, 0,
+ (char *)ctx-key + ctx-authkeylen,
DMA_TO_DEVICE);
/*
@@ -1080,7 +1079,7 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct
aead_request *areq,
}
/* iv out */
- map_single_talitos_ptr(dev, desc-ptr[6], ivsize, ctx-iv, 0,
+ map_single_talitos_ptr(dev, desc-ptr[6], ivsize, ctx-iv,
DMA_FROM_DEVICE);
ret = talitos_submit(dev, ctx-ch, desc, callback, areq);
@@ -1453,7 +1452,7 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
/* cipher key */
map_single_talitos_ptr(dev, desc-ptr[2], ctx-keylen,
- (char *)ctx-key, 0, DMA_TO_DEVICE);
+ (char *)ctx-key, DMA_TO_DEVICE);
/*
* cipher in
@@ -1470,7 +1469,7 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
desc-ptr[4], sg_count);
/* iv out */
- map_single_talitos_ptr(dev, desc-ptr[5], ivsize, ctx-iv, 0,
+ map_single_talitos_ptr(dev, desc-ptr[5], ivsize, ctx-iv,
DMA_FROM_DEVICE);
/* last DWORD empty */
@@ -1595,7 +1594,7 @@ static int common_nonsnoop_hash(struct talitos_edesc
*edesc,
if (!req_ctx-first || req_ctx-swinit) {
map_single_talitos_ptr(dev, desc-ptr[1],
req_ctx-hw_context_size,
- (char *)req_ctx-hw_context, 0,
+ (char *)req_ctx-hw_context,
DMA_TO_DEVICE);
req_ctx-swinit = 0;
} else {
@@ -1607,7 +1606,7 @@ static int common_nonsnoop_hash(struct talitos_edesc
*edesc,
/* HMAC key */
if (ctx-keylen)
map_single_talitos_ptr(dev, desc-ptr[2], ctx-keylen,
- (char *)ctx-key, 0, DMA_TO_DEVICE);
+ (char *)ctx-key, DMA_TO_DEVICE);
else
desc-ptr[2] = zero_entry;
@@ -1624,11 +1623,11 @@ static int common_nonsnoop_hash(struct talitos_edesc
*edesc,
if (req_ctx-last)
map_single_talitos_ptr(dev, desc-ptr[5],
crypto_ahash_digestsize(tfm),
- areq-result, 0, DMA_FROM_DEVICE);
+ areq-result, DMA_FROM_DEVICE);
else
map_single_talitos_ptr(dev, desc-ptr[5],
req_ctx-hw_context_size,
- req_ctx-hw_context, 0, DMA_FROM_DEVICE);
+ req_ctx-hw_context, DMA_FROM_DEVICE);
/* last DWORD empty */
desc-ptr[6] = zero_entry;
--
2.1.0
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[PATCH v3 04/17] crypto: talitos - Add a helper function to clear j_extent field
j_extent field is specific to SEC2 so we add a helper function to clear it
so that SEC1 can redefine that function as nop
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index fca0aed..c93f79b 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -61,6 +61,11 @@ static void to_talitos_ptr(struct talitos_ptr *ptr,
dma_addr_t dma_addr)
ptr-eptr = upper_32_bits(dma_addr);
}
+static void to_talitos_ptr_extent_clear(struct talitos_ptr *ptr)
+{
+ ptr-j_extent = 0;
+}
+
/*
* map virtual single (contiguous) pointer to h/w descriptor pointer
*/
@@ -1372,7 +1377,7 @@ int map_sg_in_talitos_ptr(struct device *dev, struct
scatterlist *src,
int sg_count;
ptr-len = cpu_to_be16(len);
- ptr-j_extent = 0;
+ to_talitos_ptr_extent_clear(ptr);
sg_count = talitos_map_sg(dev, src, edesc-src_nents ? : 1, dir,
edesc-src_chained);
@@ -1402,7 +1407,7 @@ void map_sg_out_talitos_ptr(struct device *dev, struct
scatterlist *dst,
struct talitos_ptr *ptr, int sg_count)
{
ptr-len = cpu_to_be16(len);
- ptr-j_extent = 0;
+ to_talitos_ptr_extent_clear(ptr);
if (dir != DMA_NONE)
sg_count = talitos_map_sg(dev, dst, edesc-dst_nents ? : 1,
@@ -1444,7 +1449,7 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
/* cipher iv */
to_talitos_ptr(desc-ptr[1], edesc-iv_dma);
desc-ptr[1].len = cpu_to_be16(ivsize);
- desc-ptr[1].j_extent = 0;
+ to_talitos_ptr_extent_clear(desc-ptr[1]);
/* cipher key */
map_single_talitos_ptr(dev, desc-ptr[2], ctx-keylen,
--
2.1.0
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[PATCH v3 08/17] crypto: talitos - add sub-choice in talitos CONFIG for SEC1
This patch adds a CONFIG option to select SEC1, SEC2+ or both. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/Kconfig | 18 ++ 1 file changed, 18 insertions(+) diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 800bf41..8a76a01 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -222,6 +222,24 @@ config CRYPTO_DEV_TALITOS To compile this driver as a module, choose M here: the module will be called talitos. +config CRYPTO_DEV_TALITOS1 + bool SEC1 (SEC 1.0 and SEC Lite 1.2) + depends on CRYPTO_DEV_TALITOS + depends on PPC_8xx || PPC_82xx + default y + help + Say 'Y' here to use the Freescale Security Engine (SEC) version 1.0 + found on MPC82xx or the Freescale Security Engine (SEC Lite) + version 1.2 found on MPC8xx + +config CRYPTO_DEV_TALITOS2 + bool SEC2+ (SEC version 2.0 or upper) + depends on CRYPTO_DEV_TALITOS + default y if !PPC_8xx + help + Say 'Y' here to use the Freescale Security Engine (SEC) + version 2 and following as found on MPC83xx, MPC85xx, etc ... + config CRYPTO_DEV_IXP4XX tristate Driver for IXP4xx crypto hardware acceleration depends on ARCH_IXP4XX IXP4XX_QMGR IXP4XX_NPE -- 2.1.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v3 03/17] crypto: talitos - talitos_ptr renamed ptr for more lisibility
Linux CodyingStyle recommends to use short variables for local
variables. ptr is just good enough for those 3 lines functions.
It helps keep single lines shorter than 80 characters.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 5a7e345..fca0aed 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -55,37 +55,37 @@
#include talitos.h
-static void to_talitos_ptr(struct talitos_ptr *talitos_ptr, dma_addr_t
dma_addr)
+static void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr)
{
- talitos_ptr-ptr = cpu_to_be32(lower_32_bits(dma_addr));
- talitos_ptr-eptr = upper_32_bits(dma_addr);
+ ptr-ptr = cpu_to_be32(lower_32_bits(dma_addr));
+ ptr-eptr = upper_32_bits(dma_addr);
}
/*
* map virtual single (contiguous) pointer to h/w descriptor pointer
*/
static void map_single_talitos_ptr(struct device *dev,
- struct talitos_ptr *talitos_ptr,
+ struct talitos_ptr *ptr,
unsigned short len, void *data,
unsigned char extent,
enum dma_data_direction dir)
{
dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
- talitos_ptr-len = cpu_to_be16(len);
- to_talitos_ptr(talitos_ptr, dma_addr);
- talitos_ptr-j_extent = extent;
+ ptr-len = cpu_to_be16(len);
+ to_talitos_ptr(ptr, dma_addr);
+ ptr-j_extent = extent;
}
/*
* unmap bus single (contiguous) h/w descriptor pointer
*/
static void unmap_single_talitos_ptr(struct device *dev,
-struct talitos_ptr *talitos_ptr,
+struct talitos_ptr *ptr,
enum dma_data_direction dir)
{
- dma_unmap_single(dev, be32_to_cpu(talitos_ptr-ptr),
-be16_to_cpu(talitos_ptr-len), dir);
+ dma_unmap_single(dev, be32_to_cpu(ptr-ptr),
+be16_to_cpu(ptr-len), dir);
}
static int reset_channel(struct device *dev, int ch)
--
2.1.0
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[PATCH v3 04/17] crypto: talitos - Add a helper function to clear j_extent field
j_extent field is specific to SEC2 so we add a helper function to clear it
so that SEC1 can redefine that function as nop
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index fca0aed..c93f79b 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -61,6 +61,11 @@ static void to_talitos_ptr(struct talitos_ptr *ptr,
dma_addr_t dma_addr)
ptr-eptr = upper_32_bits(dma_addr);
}
+static void to_talitos_ptr_extent_clear(struct talitos_ptr *ptr)
+{
+ ptr-j_extent = 0;
+}
+
/*
* map virtual single (contiguous) pointer to h/w descriptor pointer
*/
@@ -1372,7 +1377,7 @@ int map_sg_in_talitos_ptr(struct device *dev, struct
scatterlist *src,
int sg_count;
ptr-len = cpu_to_be16(len);
- ptr-j_extent = 0;
+ to_talitos_ptr_extent_clear(ptr);
sg_count = talitos_map_sg(dev, src, edesc-src_nents ? : 1, dir,
edesc-src_chained);
@@ -1402,7 +1407,7 @@ void map_sg_out_talitos_ptr(struct device *dev, struct
scatterlist *dst,
struct talitos_ptr *ptr, int sg_count)
{
ptr-len = cpu_to_be16(len);
- ptr-j_extent = 0;
+ to_talitos_ptr_extent_clear(ptr);
if (dir != DMA_NONE)
sg_count = talitos_map_sg(dev, dst, edesc-dst_nents ? : 1,
@@ -1444,7 +1449,7 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
/* cipher iv */
to_talitos_ptr(desc-ptr[1], edesc-iv_dma);
desc-ptr[1].len = cpu_to_be16(ivsize);
- desc-ptr[1].j_extent = 0;
+ to_talitos_ptr_extent_clear(desc-ptr[1]);
/* cipher key */
map_single_talitos_ptr(dev, desc-ptr[2], ctx-keylen,
--
2.1.0
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[PATCH v3 05/17] crypto: talitos - remove param 'extent' in map_single_talitos_ptr()
map_single_talitos_ptr() is always called with extent == 0, so lets remove this
unused parameter
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 21 ++---
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index c93f79b..81e5636 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -72,14 +72,13 @@ static void to_talitos_ptr_extent_clear(struct talitos_ptr
*ptr)
static void map_single_talitos_ptr(struct device *dev,
struct talitos_ptr *ptr,
unsigned short len, void *data,
- unsigned char extent,
enum dma_data_direction dir)
{
dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
ptr-len = cpu_to_be16(len);
to_talitos_ptr(ptr, dma_addr);
- ptr-j_extent = extent;
+ to_talitos_ptr_extent_clear(ptr);
}
/*
@@ -958,7 +957,7 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct
aead_request *areq,
/* hmac key */
map_single_talitos_ptr(dev, desc-ptr[0], ctx-authkeylen, ctx-key,
- 0, DMA_TO_DEVICE);
+ DMA_TO_DEVICE);
/* hmac data */
desc-ptr[1].len = cpu_to_be16(areq-assoclen + ivsize);
@@ -1002,7 +1001,7 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct
aead_request *areq,
/* cipher key */
map_single_talitos_ptr(dev, desc-ptr[3], ctx-enckeylen,
- (char *)ctx-key + ctx-authkeylen, 0,
+ (char *)ctx-key + ctx-authkeylen,
DMA_TO_DEVICE);
/*
@@ -1080,7 +1079,7 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct
aead_request *areq,
}
/* iv out */
- map_single_talitos_ptr(dev, desc-ptr[6], ivsize, ctx-iv, 0,
+ map_single_talitos_ptr(dev, desc-ptr[6], ivsize, ctx-iv,
DMA_FROM_DEVICE);
ret = talitos_submit(dev, ctx-ch, desc, callback, areq);
@@ -1453,7 +1452,7 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
/* cipher key */
map_single_talitos_ptr(dev, desc-ptr[2], ctx-keylen,
- (char *)ctx-key, 0, DMA_TO_DEVICE);
+ (char *)ctx-key, DMA_TO_DEVICE);
/*
* cipher in
@@ -1470,7 +1469,7 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
desc-ptr[4], sg_count);
/* iv out */
- map_single_talitos_ptr(dev, desc-ptr[5], ivsize, ctx-iv, 0,
+ map_single_talitos_ptr(dev, desc-ptr[5], ivsize, ctx-iv,
DMA_FROM_DEVICE);
/* last DWORD empty */
@@ -1595,7 +1594,7 @@ static int common_nonsnoop_hash(struct talitos_edesc
*edesc,
if (!req_ctx-first || req_ctx-swinit) {
map_single_talitos_ptr(dev, desc-ptr[1],
req_ctx-hw_context_size,
- (char *)req_ctx-hw_context, 0,
+ (char *)req_ctx-hw_context,
DMA_TO_DEVICE);
req_ctx-swinit = 0;
} else {
@@ -1607,7 +1606,7 @@ static int common_nonsnoop_hash(struct talitos_edesc
*edesc,
/* HMAC key */
if (ctx-keylen)
map_single_talitos_ptr(dev, desc-ptr[2], ctx-keylen,
- (char *)ctx-key, 0, DMA_TO_DEVICE);
+ (char *)ctx-key, DMA_TO_DEVICE);
else
desc-ptr[2] = zero_entry;
@@ -1624,11 +1623,11 @@ static int common_nonsnoop_hash(struct talitos_edesc
*edesc,
if (req_ctx-last)
map_single_talitos_ptr(dev, desc-ptr[5],
crypto_ahash_digestsize(tfm),
- areq-result, 0, DMA_FROM_DEVICE);
+ areq-result, DMA_FROM_DEVICE);
else
map_single_talitos_ptr(dev, desc-ptr[5],
req_ctx-hw_context_size,
- req_ctx-hw_context, 0, DMA_FROM_DEVICE);
+ req_ctx-hw_context, DMA_FROM_DEVICE);
/* last DWORD empty */
desc-ptr[6] = zero_entry;
--
2.1.0
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[PATCH v3 06/17] crypto: talitos - helper function for ptr len
This patch adds a helper function for reads and writes of the len
param of the talitos descriptor. This will help implement
SEC1 later.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 81e5636..bca6ded 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -61,6 +61,16 @@ static void to_talitos_ptr(struct talitos_ptr *ptr,
dma_addr_t dma_addr)
ptr-eptr = upper_32_bits(dma_addr);
}
+static void to_talitos_ptr_len(struct talitos_ptr *ptr, unsigned short len)
+{
+ ptr-len = cpu_to_be16(len);
+}
+
+static unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr)
+{
+ return be16_to_cpu(ptr-len);
+}
+
static void to_talitos_ptr_extent_clear(struct talitos_ptr *ptr)
{
ptr-j_extent = 0;
@@ -76,7 +86,7 @@ static void map_single_talitos_ptr(struct device *dev,
{
dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
- ptr-len = cpu_to_be16(len);
+ to_talitos_ptr_len(ptr, len);
to_talitos_ptr(ptr, dma_addr);
to_talitos_ptr_extent_clear(ptr);
}
@@ -89,7 +99,7 @@ static void unmap_single_talitos_ptr(struct device *dev,
enum dma_data_direction dir)
{
dma_unmap_single(dev, be32_to_cpu(ptr-ptr),
-be16_to_cpu(ptr-len), dir);
+from_talitos_ptr_len(ptr), dir);
}
static int reset_channel(struct device *dev, int ch)
@@ -1375,7 +1385,7 @@ int map_sg_in_talitos_ptr(struct device *dev, struct
scatterlist *src,
{
int sg_count;
- ptr-len = cpu_to_be16(len);
+ to_talitos_ptr_len(ptr, len);
to_talitos_ptr_extent_clear(ptr);
sg_count = talitos_map_sg(dev, src, edesc-src_nents ? : 1, dir,
@@ -1405,7 +1415,7 @@ void map_sg_out_talitos_ptr(struct device *dev, struct
scatterlist *dst,
enum dma_data_direction dir,
struct talitos_ptr *ptr, int sg_count)
{
- ptr-len = cpu_to_be16(len);
+ to_talitos_ptr_len(ptr, len);
to_talitos_ptr_extent_clear(ptr);
if (dir != DMA_NONE)
@@ -1447,7 +1457,7 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
/* cipher iv */
to_talitos_ptr(desc-ptr[1], edesc-iv_dma);
- desc-ptr[1].len = cpu_to_be16(ivsize);
+ to_talitos_ptr_len(desc-ptr[1], ivsize);
to_talitos_ptr_extent_clear(desc-ptr[1]);
/* cipher key */
@@ -1539,11 +1549,11 @@ static void common_nonsnoop_hash_unmap(struct device
*dev,
unmap_sg_talitos_ptr(dev, req_ctx-psrc, NULL, 0, edesc);
/* When using hashctx-in, must unmap it. */
- if (edesc-desc.ptr[1].len)
+ if (from_talitos_ptr_len(edesc-desc.ptr[1]))
unmap_single_talitos_ptr(dev, edesc-desc.ptr[1],
DMA_TO_DEVICE);
- if (edesc-desc.ptr[2].len)
+ if (from_talitos_ptr_len(edesc-desc.ptr[2]))
unmap_single_talitos_ptr(dev, edesc-desc.ptr[2],
DMA_TO_DEVICE);
--
2.1.0
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[PATCH v3 07/17] crypto: talitos - enhanced talitos_desc struct for SEC1
This patch enhances the talitos_desc struct with fields for SEC1.
SEC1 has only one header field, and has a 'next_desc' field in
addition.
This mixed descriptor will continue to fit SEC2, and for SEC1
we will recopy hdr value into hdr1 value in talitos_submit()
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.h | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/crypto/talitos.h b/drivers/crypto/talitos.h
index 61a1405..f078da1 100644
--- a/drivers/crypto/talitos.h
+++ b/drivers/crypto/talitos.h
@@ -37,9 +37,17 @@
/* descriptor pointer entry */
struct talitos_ptr {
- __be16 len; /* length */
- u8 j_extent;/* jump to sg link table and/or extent */
- u8 eptr;/* extended address */
+ union {
+ struct {/* SEC2 format */
+ __be16 len; /* length */
+ u8 j_extent;/* jump to sg link table and/or extent*/
+ u8 eptr;/* extended address */
+ };
+ struct {/* SEC1 format */
+ __be16 res;
+ __be16 len1;/* length */
+ };
+ };
__be32 ptr; /* address */
};
@@ -53,8 +61,12 @@ static const struct talitos_ptr zero_entry = {
/* descriptor */
struct talitos_desc {
__be32 hdr; /* header high bits */
- __be32 hdr_lo; /* header low bits */
+ union {
+ __be32 hdr_lo; /* header low bits */
+ __be32 hdr1;/* header for SEC1 */
+ };
struct talitos_ptr ptr[7]; /* ptr/len pair array */
+ __be32 next_desc; /* next descriptor (SEC1) */
};
/**
--
2.1.0
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[PATCH v3 08/17] crypto: talitos - add sub-choice in talitos CONFIG for SEC1
This patch adds a CONFIG option to select SEC1, SEC2+ or both. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- drivers/crypto/Kconfig | 18 ++ 1 file changed, 18 insertions(+) diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 800bf41..8a76a01 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -222,6 +222,24 @@ config CRYPTO_DEV_TALITOS To compile this driver as a module, choose M here: the module will be called talitos. +config CRYPTO_DEV_TALITOS1 + bool SEC1 (SEC 1.0 and SEC Lite 1.2) + depends on CRYPTO_DEV_TALITOS + depends on PPC_8xx || PPC_82xx + default y + help + Say 'Y' here to use the Freescale Security Engine (SEC) version 1.0 + found on MPC82xx or the Freescale Security Engine (SEC Lite) + version 1.2 found on MPC8xx + +config CRYPTO_DEV_TALITOS2 + bool SEC2+ (SEC version 2.0 or upper) + depends on CRYPTO_DEV_TALITOS + default y if !PPC_8xx + help + Say 'Y' here to use the Freescale Security Engine (SEC) + version 2 and following as found on MPC83xx, MPC85xx, etc ... + config CRYPTO_DEV_IXP4XX tristate Driver for IXP4xx crypto hardware acceleration depends on ARCH_IXP4XX IXP4XX_QMGR IXP4XX_NPE -- 2.1.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v3 09/17] crypto: talitos - Add a feature to tag SEC1
We add a new feature in the features field, to mark compatible
fsl,sec1.0
We also define a helper function called has_ftr_sec1() to help
functions quickly determine if they are running on SEC1 or SEC2+.
When only SEC1 or SEC2 is compiled in, has_ftr_sec1() return
trivial corresponding value. If both are compiled in, feature
field is checked.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 3 +++
drivers/crypto/talitos.h | 17 +
2 files changed, 20 insertions(+)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index bca6ded..db95023 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -2709,6 +2709,9 @@ static int talitos_probe(struct platform_device *ofdev)
TALITOS_FTR_SHA224_HWINIT |
TALITOS_FTR_HMAC_OK;
+ if (of_device_is_compatible(np, fsl,sec1.0))
+ priv-features |= TALITOS_FTR_SEC1;
+
priv-chan = kzalloc(sizeof(struct talitos_channel) *
priv-num_channels, GFP_KERNEL);
if (!priv-chan) {
diff --git a/drivers/crypto/talitos.h b/drivers/crypto/talitos.h
index f078da1..b0bdb4e 100644
--- a/drivers/crypto/talitos.h
+++ b/drivers/crypto/talitos.h
@@ -156,6 +156,23 @@ extern int talitos_submit(struct device *dev, int ch,
struct talitos_desc *desc,
#define TALITOS_FTR_HW_AUTH_CHECK 0x0002
#define TALITOS_FTR_SHA224_HWINIT 0x0004
#define TALITOS_FTR_HMAC_OK 0x0008
+#define TALITOS_FTR_SEC1 0x0010
+
+/*
+ * If both CONFIG_CRYPTO_DEV_TALITOS1 and CONFIG_CRYPTO_DEV_TALITOS2 are
+ * defined, we check the features which are set according to the device tree.
+ * Otherwise, we answer true or false directly
+ */
+static inline bool has_ftr_sec1(struct talitos_private *priv)
+{
+#if defined(CONFIG_CRYPTO_DEV_TALITOS1) defined(CONFIG_CRYPTO_DEV_TALITOS2)
+ return priv-features TALITOS_FTR_SEC1 ? true : false;
+#elif defined(CONFIG_CRYPTO_DEV_TALITOS1)
+ return true;
+#else
+ return false;
+#endif
+}
/*
* TALITOS_xxx_LO addresses point to the low data bits (32-63) of the register
--
2.1.0
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[PATCH v3 10/17] crypto: talitos - fill in talitos descriptor iaw SEC1 or SEC2+
talitos descriptor is slightly different for SEC1 and SEC2+, so
lets the helper function that fills the descriptor take into account
the type of SEC.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 105 ++-
1 file changed, 67 insertions(+), 38 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index db95023..678b528 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -55,25 +55,38 @@
#include talitos.h
-static void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr)
+static void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
+ bool is_sec1)
{
ptr-ptr = cpu_to_be32(lower_32_bits(dma_addr));
- ptr-eptr = upper_32_bits(dma_addr);
+ if (!is_sec1)
+ ptr-eptr = upper_32_bits(dma_addr);
}
-static void to_talitos_ptr_len(struct talitos_ptr *ptr, unsigned short len)
+static void to_talitos_ptr_len(struct talitos_ptr *ptr, unsigned short len,
+ bool is_sec1)
{
- ptr-len = cpu_to_be16(len);
+ if (is_sec1) {
+ ptr-res = 0;
+ ptr-len1 = cpu_to_be16(len);
+ } else {
+ ptr-len = cpu_to_be16(len);
+ }
}
-static unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr)
+static unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr,
+ bool is_sec1)
{
- return be16_to_cpu(ptr-len);
+ if (is_sec1)
+ return be16_to_cpu(ptr-len1);
+ else
+ return be16_to_cpu(ptr-len);
}
-static void to_talitos_ptr_extent_clear(struct talitos_ptr *ptr)
+static void to_talitos_ptr_extent_clear(struct talitos_ptr *ptr, bool is_sec1)
{
- ptr-j_extent = 0;
+ if (!is_sec1)
+ ptr-j_extent = 0;
}
/*
@@ -85,10 +98,12 @@ static void map_single_talitos_ptr(struct device *dev,
enum dma_data_direction dir)
{
dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ bool is_sec1 = has_ftr_sec1(priv);
- to_talitos_ptr_len(ptr, len);
- to_talitos_ptr(ptr, dma_addr);
- to_talitos_ptr_extent_clear(ptr);
+ to_talitos_ptr_len(ptr, len, is_sec1);
+ to_talitos_ptr(ptr, dma_addr, is_sec1);
+ to_talitos_ptr_extent_clear(ptr, is_sec1);
}
/*
@@ -98,8 +113,11 @@ static void unmap_single_talitos_ptr(struct device *dev,
struct talitos_ptr *ptr,
enum dma_data_direction dir)
{
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ bool is_sec1 = has_ftr_sec1(priv);
+
dma_unmap_single(dev, be32_to_cpu(ptr-ptr),
-from_talitos_ptr_len(ptr), dir);
+from_talitos_ptr_len(ptr, is_sec1), dir);
}
static int reset_channel(struct device *dev, int ch)
@@ -922,7 +940,7 @@ static int sg_to_link_tbl(struct scatterlist *sg, int
sg_count,
int n_sg = sg_count;
while (n_sg--) {
- to_talitos_ptr(link_tbl_ptr, sg_dma_address(sg));
+ to_talitos_ptr(link_tbl_ptr, sg_dma_address(sg), 0);
link_tbl_ptr-len = cpu_to_be16(sg_dma_len(sg));
link_tbl_ptr-j_extent = 0;
link_tbl_ptr++;
@@ -976,7 +994,7 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct
aead_request *areq,
struct talitos_ptr *tbl_ptr = edesc-link_tbl[tbl_off];
to_talitos_ptr(desc-ptr[1], edesc-dma_link_tbl + tbl_off *
- sizeof(struct talitos_ptr));
+ sizeof(struct talitos_ptr), 0);
desc-ptr[1].j_extent = DESC_PTR_LNKTBL_JUMP;
/* assoc_nents - 1 entries for assoc, 1 for IV */
@@ -987,7 +1005,7 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct
aead_request *areq,
tbl_ptr += sg_count - 1;
tbl_ptr-j_extent = 0;
tbl_ptr++;
- to_talitos_ptr(tbl_ptr, edesc-iv_dma);
+ to_talitos_ptr(tbl_ptr, edesc-iv_dma, 0);
tbl_ptr-len = cpu_to_be16(ivsize);
tbl_ptr-j_extent = DESC_PTR_LNKTBL_RETURN;
@@ -996,14 +1014,14 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct
aead_request *areq,
} else {
if (areq-assoclen)
to_talitos_ptr(desc-ptr[1],
- sg_dma_address(areq-assoc));
+ sg_dma_address(areq-assoc), 0);
else
- to_talitos_ptr(desc-ptr[1], edesc-iv_dma);
+ to_talitos_ptr(desc-ptr[1], edesc-iv_dma, 0);
desc-ptr[1].j_extent = 0;
}
/* cipher iv */
-
[PATCH v3 11/17] crypto: talitos - adaptation of talitos_submit() for SEC1
SEC1 descriptor is a bit different to SEC2+ descriptor.
talitos_submit() will have to copy hdr field into hdr1 field and
send the descriptor starting at hdr1 up to next_desc.
For SEC2, it remains unchanged and next_desc is just ignored.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 23 +++
drivers/crypto/talitos.h | 2 ++
2 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 678b528..e6ea651 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -236,6 +236,7 @@ int talitos_submit(struct device *dev, int ch, struct
talitos_desc *desc,
struct talitos_request *request;
unsigned long flags;
int head;
+ bool is_sec1 = has_ftr_sec1(priv);
spin_lock_irqsave(priv-chan[ch].head_lock, flags);
@@ -249,8 +250,17 @@ int talitos_submit(struct device *dev, int ch, struct
talitos_desc *desc,
request = priv-chan[ch].fifo[head];
/* map descriptor and save caller data */
- request-dma_desc = dma_map_single(dev, desc, sizeof(*desc),
- DMA_BIDIRECTIONAL);
+ if (is_sec1) {
+ desc-hdr1 = desc-hdr;
+ desc-next_desc = 0;
+ request-dma_desc = dma_map_single(dev, desc-hdr1,
+ TALITOS_DESC_SIZE,
+ DMA_BIDIRECTIONAL);
+ } else {
+ request-dma_desc = dma_map_single(dev, desc,
+ TALITOS_DESC_SIZE,
+ DMA_BIDIRECTIONAL);
+ }
request-callback = callback;
request-context = context;
@@ -282,16 +292,21 @@ static void flush_channel(struct device *dev, int ch, int
error, int reset_ch)
struct talitos_request *request, saved_req;
unsigned long flags;
int tail, status;
+ bool is_sec1 = has_ftr_sec1(priv);
spin_lock_irqsave(priv-chan[ch].tail_lock, flags);
tail = priv-chan[ch].tail;
while (priv-chan[ch].fifo[tail].desc) {
+ __be32 hdr;
+
request = priv-chan[ch].fifo[tail];
/* descriptors with their done bits set don't get the error */
rmb();
- if ((request-desc-hdr DESC_HDR_DONE) == DESC_HDR_DONE)
+ hdr = is_sec1 ? request-desc-hdr1 : request-desc-hdr;
+
+ if ((hdr DESC_HDR_DONE) == DESC_HDR_DONE)
status = 0;
else
if (!error)
@@ -300,7 +315,7 @@ static void flush_channel(struct device *dev, int ch, int
error, int reset_ch)
status = error;
dma_unmap_single(dev, request-dma_desc,
-sizeof(struct talitos_desc),
+TALITOS_DESC_SIZE,
DMA_BIDIRECTIONAL);
/* copy entries so we can call callback outside lock */
diff --git a/drivers/crypto/talitos.h b/drivers/crypto/talitos.h
index b0bdb4e..f827c04 100644
--- a/drivers/crypto/talitos.h
+++ b/drivers/crypto/talitos.h
@@ -69,6 +69,8 @@ struct talitos_desc {
__be32 next_desc; /* next descriptor (SEC1) */
};
+#define TALITOS_DESC_SIZE (sizeof(struct talitos_desc) - sizeof(__be32))
+
/**
* talitos_request - descriptor submission request
* @desc: descriptor pointer (kernel virtual)
--
2.1.0
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[PATCH v3 12/17] crypto: talitos - base address for Execution Units
SEC 1.0, 1.2 and 2.x+ have different EU base addresses, so we need to
define pointers for each EU in the driver private data structure.
The proper address is set by the probe function depending on the
SEC type, in order to provide access to the proper address.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 83
drivers/crypto/talitos.h | 72 +
2 files changed, 100 insertions(+), 55 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index e6ea651..6d77699 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -208,7 +208,7 @@ static int init_device(struct device *dev)
/* disable integrity check error interrupts (use writeback instead) */
if (priv-features TALITOS_FTR_HW_AUTH_CHECK)
- setbits32(priv-reg + TALITOS_MDEUICR_LO,
+ setbits32(priv-reg_mdeu + TALITOS_EUICR_LO,
TALITOS_MDEUICR_LO_ICE);
return 0;
@@ -424,44 +424,44 @@ static void report_eu_error(struct device *dev, int ch,
u32 desc_hdr)
switch (desc_hdr DESC_HDR_SEL0_MASK) {
case DESC_HDR_SEL0_AFEU:
dev_err(dev, AFEUISR 0x%08x_%08x\n,
- in_be32(priv-reg + TALITOS_AFEUISR),
- in_be32(priv-reg + TALITOS_AFEUISR_LO));
+ in_be32(priv-reg_afeu + TALITOS_EUISR),
+ in_be32(priv-reg_afeu + TALITOS_EUISR_LO));
break;
case DESC_HDR_SEL0_DEU:
dev_err(dev, DEUISR 0x%08x_%08x\n,
- in_be32(priv-reg + TALITOS_DEUISR),
- in_be32(priv-reg + TALITOS_DEUISR_LO));
+ in_be32(priv-reg_deu + TALITOS_EUISR),
+ in_be32(priv-reg_deu + TALITOS_EUISR_LO));
break;
case DESC_HDR_SEL0_MDEUA:
case DESC_HDR_SEL0_MDEUB:
dev_err(dev, MDEUISR 0x%08x_%08x\n,
- in_be32(priv-reg + TALITOS_MDEUISR),
- in_be32(priv-reg + TALITOS_MDEUISR_LO));
+ in_be32(priv-reg_mdeu + TALITOS_EUISR),
+ in_be32(priv-reg_mdeu + TALITOS_EUISR_LO));
break;
case DESC_HDR_SEL0_RNG:
dev_err(dev, RNGUISR 0x%08x_%08x\n,
- in_be32(priv-reg + TALITOS_RNGUISR),
- in_be32(priv-reg + TALITOS_RNGUISR_LO));
+ in_be32(priv-reg_rngu + TALITOS_ISR),
+ in_be32(priv-reg_rngu + TALITOS_ISR_LO));
break;
case DESC_HDR_SEL0_PKEU:
dev_err(dev, PKEUISR 0x%08x_%08x\n,
- in_be32(priv-reg + TALITOS_PKEUISR),
- in_be32(priv-reg + TALITOS_PKEUISR_LO));
+ in_be32(priv-reg_pkeu + TALITOS_EUISR),
+ in_be32(priv-reg_pkeu + TALITOS_EUISR_LO));
break;
case DESC_HDR_SEL0_AESU:
dev_err(dev, AESUISR 0x%08x_%08x\n,
- in_be32(priv-reg + TALITOS_AESUISR),
- in_be32(priv-reg + TALITOS_AESUISR_LO));
+ in_be32(priv-reg_aesu + TALITOS_EUISR),
+ in_be32(priv-reg_aesu + TALITOS_EUISR_LO));
break;
case DESC_HDR_SEL0_CRCU:
dev_err(dev, CRCUISR 0x%08x_%08x\n,
- in_be32(priv-reg + TALITOS_CRCUISR),
- in_be32(priv-reg + TALITOS_CRCUISR_LO));
+ in_be32(priv-reg_crcu + TALITOS_EUISR),
+ in_be32(priv-reg_crcu + TALITOS_EUISR_LO));
break;
case DESC_HDR_SEL0_KEU:
dev_err(dev, KEUISR 0x%08x_%08x\n,
- in_be32(priv-reg + TALITOS_KEUISR),
- in_be32(priv-reg + TALITOS_KEUISR_LO));
+ in_be32(priv-reg_pkeu + TALITOS_EUISR),
+ in_be32(priv-reg_pkeu + TALITOS_EUISR_LO));
break;
}
@@ -469,13 +469,13 @@ static void report_eu_error(struct device *dev, int ch,
u32 desc_hdr)
case DESC_HDR_SEL1_MDEUA:
case DESC_HDR_SEL1_MDEUB:
dev_err(dev, MDEUISR 0x%08x_%08x\n,
- in_be32(priv-reg + TALITOS_MDEUISR),
- in_be32(priv-reg + TALITOS_MDEUISR_LO));
+ in_be32(priv-reg_mdeu + TALITOS_EUISR),
+ in_be32(priv-reg_mdeu + TALITOS_EUISR_LO));
break;
case DESC_HDR_SEL1_CRCU:
dev_err(dev, CRCUISR 0x%08x_%08x\n,
- in_be32(priv-reg + TALITOS_CRCUISR),
- in_be32(priv-reg + TALITOS_CRCUISR_LO));
+ in_be32(priv-reg_crcu + TALITOS_EUISR),
+ in_be32(priv-reg_crcu +
[PATCH v3 13/17] crypto: talitos - adapt interrupts and reset functions to SEC1
This patch adapts the interrupts handling and reset function for
SEC1. On SEC1, registers are almost similar to SEC2+, but bits
are sometimes located at different places. So we need to define
TALITOS1 and TALITOS2 versions of some fields, and manage according
to whether it is SEC1 or SEC2.
On SEC1, only one interrupt vector is dedicated to the SEC, so only
interrupt_4ch is needed.
On SEC1, interrupts are enabled by clearing related bits in IMR,
while on SEC2, interrupts are enabled by seting the bits in IMR.
SEC1 also performs parity verification in the DES Unit. We have
to disable this feature because the test vectors provided in
the kernel have parity errors.
In reset functions, only SEC2 supports continuation after error.
For SEC1, we have to reset in all cases.
For errors handling, SEC2+ names have been kept, but displayed
text have been amended to reflect exact meaning on SEC1.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 227 +++
drivers/crypto/talitos.h | 39 +---
2 files changed, 199 insertions(+), 67 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 6d77699..1265405 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -124,12 +124,23 @@ static int reset_channel(struct device *dev, int ch)
{
struct talitos_private *priv = dev_get_drvdata(dev);
unsigned int timeout = TALITOS_TIMEOUT;
+ bool is_sec1 = has_ftr_sec1(priv);
- setbits32(priv-chan[ch].reg + TALITOS_CCCR, TALITOS_CCCR_RESET);
+ if (is_sec1) {
+ setbits32(priv-chan[ch].reg + TALITOS_CCCR_LO,
+ TALITOS1_CCCR_LO_RESET);
- while ((in_be32(priv-chan[ch].reg + TALITOS_CCCR) TALITOS_CCCR_RESET)
- --timeout)
- cpu_relax();
+ while ((in_be32(priv-chan[ch].reg + TALITOS_CCCR_LO)
+ TALITOS1_CCCR_LO_RESET) --timeout)
+ cpu_relax();
+ } else {
+ setbits32(priv-chan[ch].reg + TALITOS_CCCR,
+ TALITOS2_CCCR_RESET);
+
+ while ((in_be32(priv-chan[ch].reg + TALITOS_CCCR)
+ TALITOS2_CCCR_RESET) --timeout)
+ cpu_relax();
+ }
if (timeout == 0) {
dev_err(dev, failed to reset channel %d\n, ch);
@@ -152,11 +163,12 @@ static int reset_device(struct device *dev)
{
struct talitos_private *priv = dev_get_drvdata(dev);
unsigned int timeout = TALITOS_TIMEOUT;
- u32 mcr = TALITOS_MCR_SWR;
+ bool is_sec1 = has_ftr_sec1(priv);
+ u32 mcr = is_sec1 ? TALITOS1_MCR_SWR : TALITOS2_MCR_SWR;
setbits32(priv-reg + TALITOS_MCR, mcr);
- while ((in_be32(priv-reg + TALITOS_MCR) TALITOS_MCR_SWR)
+ while ((in_be32(priv-reg + TALITOS_MCR) mcr)
--timeout)
cpu_relax();
@@ -180,6 +192,7 @@ static int init_device(struct device *dev)
{
struct talitos_private *priv = dev_get_drvdata(dev);
int ch, err;
+ bool is_sec1 = has_ftr_sec1(priv);
/*
* Master reset
@@ -203,8 +216,15 @@ static int init_device(struct device *dev)
}
/* enable channel done and error interrupts */
- setbits32(priv-reg + TALITOS_IMR, TALITOS_IMR_INIT);
- setbits32(priv-reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
+ if (is_sec1) {
+ clrbits32(priv-reg + TALITOS_IMR, TALITOS1_IMR_INIT);
+ clrbits32(priv-reg + TALITOS_IMR_LO, TALITOS1_IMR_LO_INIT);
+ /* disable parity error check in DEU (erroneous? test vect.) */
+ setbits32(priv-reg_deu + TALITOS_EUICR, TALITOS1_DEUICR_KPE);
+ } else {
+ setbits32(priv-reg + TALITOS_IMR, TALITOS2_IMR_INIT);
+ setbits32(priv-reg + TALITOS_IMR_LO, TALITOS2_IMR_LO_INIT);
+ }
/* disable integrity check error interrupts (use writeback instead) */
if (priv-features TALITOS_FTR_HW_AUTH_CHECK)
@@ -349,8 +369,37 @@ static void flush_channel(struct device *dev, int ch, int
error, int reset_ch)
/*
* process completed requests for channels that have done status
*/
-#define DEF_TALITOS_DONE(name, ch_done_mask) \
-static void talitos_done_##name(unsigned long data)\
+#define DEF_TALITOS1_DONE(name, ch_done_mask) \
+static void talitos1_done_##name(unsigned long data) \
+{ \
+ struct device *dev = (struct device *)data; \
+ struct talitos_private *priv = dev_get_drvdata(dev);\
+ unsigned long flags;\
+ \
+ if (ch_done_mask 0x1000)
[PATCH v3 14/17] crypto: talitos - implement scatter/gather copy for SEC1
SEC1 doesn't support scatter/gather, SEC1 doesn't handle link tables.
Therefore, for SEC1 we have to do it by SW. For that, we reserve
space at the end of the extended descriptor, in lieu of the space
reserved for the link tables on SEC2, and we perform sg_copy() when
preparing the descriptors
We also adapt the max buffer size which is only 32k on SEC1 while it
is 64k on SEC2+
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 138 ++-
drivers/crypto/talitos.h | 3 +-
2 files changed, 103 insertions(+), 38 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 1265405..dddf4b3 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -866,9 +866,10 @@ badkey:
* @dst_chained: whether dst is chained or not
* @iv_dma: dma address of iv for checking continuity and link table
* @dma_len: length of dma mapped link_tbl space
- * @dma_link_tbl: bus physical address of link_tbl
+ * @dma_link_tbl: bus physical address of link_tbl/buf
* @desc: h/w descriptor
- * @link_tbl: input and output h/w link tables (if {src,dst}_nents 1)
+ * @link_tbl: input and output h/w link tables (if {src,dst}_nents 1) (SEC2)
+ * @buf: input and output buffeur (if {src,dst}_nents 1) (SEC1)
*
* if decrypting (with authcheck), or either one of src_nents or dst_nents
* is greater than 1, an integrity check value is concatenated to the end
@@ -885,7 +886,10 @@ struct talitos_edesc {
int dma_len;
dma_addr_t dma_link_tbl;
struct talitos_desc desc;
- struct talitos_ptr link_tbl[0];
+ union {
+ struct talitos_ptr link_tbl[0];
+ u8 buf[0];
+ };
};
static int talitos_map_sg(struct device *dev, struct scatterlist *sg,
@@ -1282,8 +1286,11 @@ static struct talitos_edesc *talitos_edesc_alloc(struct
device *dev,
dma_addr_t iv_dma = 0;
gfp_t flags = cryptoflags CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
GFP_ATOMIC;
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ bool is_sec1 = has_ftr_sec1(priv);
+ int max_len = is_sec1 ? TALITOS1_MAX_DATA_LEN : TALITOS2_MAX_DATA_LEN;
- if (cryptlen + authsize TALITOS_MAX_DATA_LEN) {
+ if (cryptlen + authsize max_len) {
dev_err(dev, length exceeds h/w max limit\n);
return ERR_PTR(-EINVAL);
}
@@ -1327,8 +1334,12 @@ static struct talitos_edesc *talitos_edesc_alloc(struct
device *dev,
*/
alloc_len = sizeof(struct talitos_edesc);
if (assoc_nents || src_nents || dst_nents) {
- dma_len = (src_nents + dst_nents + 2 + assoc_nents) *
- sizeof(struct talitos_ptr) + authsize;
+ if (is_sec1)
+ dma_len = src_nents ? cryptlen : 0 +
+ dst_nents ? cryptlen : 0;
+ else
+ dma_len = (src_nents + dst_nents + 2 + assoc_nents) *
+ sizeof(struct talitos_ptr) + authsize;
alloc_len += dma_len;
} else {
dma_len = 0;
@@ -1485,7 +1496,27 @@ static void unmap_sg_talitos_ptr(struct device *dev,
struct scatterlist *src,
struct scatterlist *dst, unsigned int len,
struct talitos_edesc *edesc)
{
- talitos_sg_unmap(dev, edesc, src, dst);
+ struct talitos_private *priv = dev_get_drvdata(dev);
+ bool is_sec1 = has_ftr_sec1(priv);
+
+ if (is_sec1) {
+ if (!edesc-src_nents) {
+ dma_unmap_sg(dev, src, 1,
+dst != src ? DMA_TO_DEVICE
+ : DMA_BIDIRECTIONAL);
+ }
+ if (dst edesc-dst_nents) {
+ dma_sync_single_for_device(dev,
+ edesc-dma_link_tbl + len,
+ len, DMA_FROM_DEVICE);
+ sg_copy_from_buffer(dst, edesc-dst_nents ? : 1,
+ edesc-buf + len, len);
+ } else if (dst dst != src) {
+ dma_unmap_sg(dev, dst, 1, DMA_FROM_DEVICE);
+ }
+ } else {
+ talitos_sg_unmap(dev, edesc, src, dst);
+ }
}
static void common_nonsnoop_unmap(struct device *dev,
@@ -1528,25 +1559,42 @@ int map_sg_in_talitos_ptr(struct device *dev, struct
scatterlist *src,
bool is_sec1 = has_ftr_sec1(priv);
to_talitos_ptr_len(ptr, len, is_sec1);
- to_talitos_ptr_extent_clear(ptr, is_sec1);
- sg_count = talitos_map_sg(dev, src, edesc-src_nents ? : 1, dir,
- edesc-src_chained);
+ if (is_sec1) {
+ sg_count = edesc-src_nents ? : 1;
- if (sg_count == 1)
[PATCH v3 15/17] crypto: talitos - SEC1 bugs on 0 data hash
SEC1 bugs on 0 data hash, so we submit an already padded block representing 0
data
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index dddf4b3..f1406d7b 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -1797,6 +1797,27 @@ static void ahash_done(struct device *dev,
areq-base.complete(areq-base, err);
}
+/*
+ * SEC1 doesn't like hashing of 0 sized message, so we do the padding
+ * ourself and submit a padded block
+ */
+void talitos_handle_buggy_hash(struct talitos_ctx *ctx,
+ struct talitos_edesc *edesc,
+ struct talitos_ptr *ptr)
+{
+ static u8 padded_hash[64] = {
+ 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ };
+
+ pr_err_once(Bug in SEC1, padding ourself\n);
+ edesc-desc.hdr = ~DESC_HDR_MODE0_MDEU_PAD;
+ map_single_talitos_ptr(ctx-dev, ptr, sizeof(padded_hash),
+ (char *)padded_hash, DMA_TO_DEVICE);
+}
+
static int common_nonsnoop_hash(struct talitos_edesc *edesc,
struct ahash_request *areq, unsigned int length,
void (*callback) (struct device *dev,
@@ -1857,6 +1878,9 @@ static int common_nonsnoop_hash(struct talitos_edesc
*edesc,
/* last DWORD empty */
desc-ptr[6] = zero_entry;
+ if (is_sec1 from_talitos_ptr_len(desc-ptr[3], true) == 0)
+ talitos_handle_buggy_hash(ctx, edesc, desc-ptr[3]);
+
ret = talitos_submit(dev, ctx-ch, desc, callback, areq);
if (ret != -EINPROGRESS) {
common_nonsnoop_hash_unmap(dev, edesc, areq);
--
2.1.0
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[PATCH v3 16/17] crypto: talitos - Add fsl,sec1.0 compatible
We add a specific compatible for SEC1, to handle the differences
between SEC1 and SEC2+
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index f1406d7b..c04074d 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -3086,9 +3086,16 @@ err_out:
}
static const struct of_device_id talitos_match[] = {
+#ifdef CONFIG_CRYPTO_DEV_TALITOS1
+ {
+ .compatible = fsl,sec1.0,
+ },
+#endif
+#ifdef CONFIG_CRYPTO_DEV_TALITOS2
{
.compatible = fsl,sec2.0,
},
+#endif
{},
};
MODULE_DEVICE_TABLE(of, talitos_match);
--
2.1.0
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[PATCH v3 17/17] crypto: talitos - Update DT bindings with SEC1
This patch updates the documentation by including SEC1 into SEC2/3 doc Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- Documentation/devicetree/bindings/crypto/fsl-sec2.txt | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec2.txt b/Documentation/devicetree/bindings/crypto/fsl-sec2.txt index 38988ef..f0d926b 100644 --- a/Documentation/devicetree/bindings/crypto/fsl-sec2.txt +++ b/Documentation/devicetree/bindings/crypto/fsl-sec2.txt @@ -1,9 +1,11 @@ -Freescale SoC SEC Security Engines versions 2.x-3.x +Freescale SoC SEC Security Engines versions 1.x-2.x-3.x Required properties: - compatible : Should contain entries for this and backward compatible - SEC versions, high to low, e.g., fsl,sec2.1, fsl,sec2.0 + SEC versions, high to low, e.g., fsl,sec2.1, fsl,sec2.0 (SEC2/3) + e.g., fsl,sec1.2, fsl,sec1.0 (SEC1) +warning: SEC1 and SEC2 are mutually exclusive - reg : Offset and length of the register set for the device - interrupts : the SEC's interrupt number - fsl,num-channels : An integer representing the number of channels -- 2.1.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH v3 03/17] crypto: talitos - talitos_ptr renamed ptr for more lisibility
From: Christophe Leroy
Linux CodyingStyle recommends to use short variables for local
variables. ptr is just good enough for those 3 lines functions.
It helps keep single lines shorter than 80 characters.
...
-static void to_talitos_ptr(struct talitos_ptr *talitos_ptr, dma_addr_t
dma_addr)
+static void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr)
{
- talitos_ptr-ptr = cpu_to_be32(lower_32_bits(dma_addr));
- talitos_ptr-eptr = upper_32_bits(dma_addr);
+ ptr-ptr = cpu_to_be32(lower_32_bits(dma_addr));
+ ptr-eptr = upper_32_bits(dma_addr);
}
...
Maybe, but 'ptr' isn't a good choice.
David
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Re: [PATCH v5 0/5] powerpc8xx: Further optimisation of TLB handling
On Fri, 2015-04-17 at 18:32 +0200, root wrote: This patchset provides a further optimisation of TLB handling in the 8xx. Changes are: - Not saving registers like CR when not needed - Adding support to any TASK_SIZE Only the last patch of the set is changed compared to v4 Christophe Leroy (5): powerpc/8xx: macro for handling CPU15 errata powerpc/8xx: Handle CR out of exception PROLOG/EPILOG powerpc/8xx: dont save CR in SCRATCH registers powerpc/8xx: Use SPRG2 instead of DAR for saving r3 powerpc/8xx: Add support for TASK_SIZE greater than 0x8000 arch/powerpc/kernel/head_8xx.S | 79 +++--- 1 file changed, 51 insertions(+), 28 deletions(-) Do you really want your name in the git history to be root? -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: new way of writing defconfigs for freescale's powerpc platforms
-Original Message- From: Michael Ellerman [mailto:m...@ellerman.id.au] Sent: Friday, April 17, 2015 1:19 AM To: Wood Scott-B07421 Cc: Pan Lijun-B44306; linuxppc-...@ozlabs.org; Schmitt Richard-B43082 Subject: Re: new way of writing defconfigs for freescale's powerpc platforms On Thu, 2015-04-16 at 23:13 -0500, Scott Wood wrote: On Fri, 2015-04-17 at 10:54 +1000, Michael Ellerman wrote: On Thu, 2015-04-09 at 21:52 +, Lijun Pan wrote: Hi Maintainers, We have a proposal for writing the defconfigs for freescale's powperpc platforms in a new way. Can you take a look and provide some feedback? You know currently we have mpc85xx_defconfig, corenet32_defconfig, bsc913x_defconfig, *fman*_defconfig, etc. We are going to extract some common parts from the existing defconfigs, and name it, say, fsl_basic_defconfig. Then, we could create some defconfigs targeting specific features or specific platforms. Say, features specific: kvm_defconfig, fman_defconfig, etc. Platforms specific: p1_defconfig, p2_defcongfig, p4_defconfig, t1_defconfig, t2_defconfig, t2_defconfig, b4_defconfig, etc When we want to make a kernel image for p1 platform, Using the following steps: make ./scripts/kconfig/merge_config.sh arch/powerpc/configs/fsl_basic_config p1_defconfig make What do you think of this new approach? I don't like that the user has to manually run merge_config.sh. How does a user even know that it's an option? It also breaks scripts that auto build the kernel, which expect to be able to do: $ make foo_defconfig $ make Scripts like mine for example :) http://kisskb.ellerman.id.au/kisskb/head/8734/ What I'd be happy with is something that does merge_config under the covers. So a user still runs 'make fsl_plat_foo_defconfig', but under the covers it does a merge config. kvmconfig and tinyconfig are implemented that way already, so with a bit more work hopefully you can do that for arch configs also. kvmconfig and tinyconfig are still separate user-visible steps to be applied after running a base defconfig. Not as of recently: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/scripts/kc onfig/Makefile?id=63a91033d52e64a22e571fe84924c0b7f21c280d Above patch is very generic. With this patch, we don't even need to modify arch/powerpc/Makefile. We can just add fragments (like smp.config, kvm_guest.config, etc) under arch/powerpc/configs/ or add platform independent config under kernel/configs/ example might be: make mpc85xx_defconfig make smp.config make kvm_guest.config Which pretty much does what you describe below I think. For breaking a platform defconfig into components, we could do something like this in arch/powerpc/Makefile: # Can't call mergeconfig directly as it isn't defined at this point define domerge @$(MAKE) -f $(srctree)/scripts/kconfig/Makefile $(1).config endef corenet64_smp_defconfig: corenet64_basic_defconfig $(call domerge,smp) $(call domerge,altivec) $(call domerge,corenet_drivers) $(call domerge,embedded_misc) # filesystems etc And this in scripts/kconfig/Makefile: %.config: $(call mergeconfig,$*) One issue with this is that we'd lose the ability to use savedefconfig (at least without manual manipulation of the results) to maintain the defconfigs/fragments. That's probably OK, it's only maintainers who need to do that. cheers ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: new way of writing defconfigs for freescale's powerpc platforms
On Fri, 2015-04-17 at 13:50 -0500, Pan Lijun-B44306 wrote: -Original Message- From: Michael Ellerman [mailto:m...@ellerman.id.au] Sent: Friday, April 17, 2015 1:19 AM To: Wood Scott-B07421 Cc: Pan Lijun-B44306; linuxppc-...@ozlabs.org; Schmitt Richard-B43082 Subject: Re: new way of writing defconfigs for freescale's powerpc platforms On Thu, 2015-04-16 at 23:13 -0500, Scott Wood wrote: On Fri, 2015-04-17 at 10:54 +1000, Michael Ellerman wrote: On Thu, 2015-04-09 at 21:52 +, Lijun Pan wrote: Hi Maintainers, We have a proposal for writing the defconfigs for freescale's powperpc platforms in a new way. Can you take a look and provide some feedback? You know currently we have mpc85xx_defconfig, corenet32_defconfig, bsc913x_defconfig, *fman*_defconfig, etc. We are going to extract some common parts from the existing defconfigs, and name it, say, fsl_basic_defconfig. Then, we could create some defconfigs targeting specific features or specific platforms. Say, features specific: kvm_defconfig, fman_defconfig, etc. Platforms specific: p1_defconfig, p2_defcongfig, p4_defconfig, t1_defconfig, t2_defconfig, t2_defconfig, b4_defconfig, etc When we want to make a kernel image for p1 platform, Using the following steps: make ./scripts/kconfig/merge_config.sh arch/powerpc/configs/fsl_basic_config p1_defconfig make What do you think of this new approach? I don't like that the user has to manually run merge_config.sh. How does a user even know that it's an option? It also breaks scripts that auto build the kernel, which expect to be able to do: $ make foo_defconfig $ make Scripts like mine for example :) http://kisskb.ellerman.id.au/kisskb/head/8734/ What I'd be happy with is something that does merge_config under the covers. So a user still runs 'make fsl_plat_foo_defconfig', but under the covers it does a merge config. kvmconfig and tinyconfig are implemented that way already, so with a bit more work hopefully you can do that for arch configs also. kvmconfig and tinyconfig are still separate user-visible steps to be applied after running a base defconfig. Not as of recently: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/scripts/kc onfig/Makefile?id=63a91033d52e64a22e571fe84924c0b7f21c280d Above patch is very generic. With this patch, we don't even need to modify arch/powerpc/Makefile. We can just add fragments (like smp.config, kvm_guest.config, etc) under arch/powerpc/configs/ or add platform independent config under kernel/configs/ example might be: make mpc85xx_defconfig make smp.config make kvm_guest.config The point is that the user should not have to do that. They can if they want, but there should still be traditional named configs, which would just work differently under the hood. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v3 00/17] crypto: talitos - Add support for SEC1
On Fri, Apr 17, Christophe Leroy wrote: v3 is a complete rework of the patchset. Since a kernel can be built with support for both MPC82xx and MPC83xx at the same time, talitos driver shall support both SEC1 and SEC2+ at the same time. The used git send-email command lacked the --thread option. From this perspective: NACK to the whole series... Olaf ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v5 0/5] powerpc8xx: Further optimisation of TLB handling
This patchset provides a further optimisation of TLB handling in the 8xx. Changes are: - Not saving registers like CR when not needed - Adding support to any TASK_SIZE Only the last patch of the set is changed compared to v4 Christophe Leroy (5): powerpc/8xx: macro for handling CPU15 errata powerpc/8xx: Handle CR out of exception PROLOG/EPILOG powerpc/8xx: dont save CR in SCRATCH registers powerpc/8xx: Use SPRG2 instead of DAR for saving r3 powerpc/8xx: Add support for TASK_SIZE greater than 0x8000 arch/powerpc/kernel/head_8xx.S | 79 +++--- 1 file changed, 51 insertions(+), 28 deletions(-) -- 2.1.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/8xx: mmu_virtual_psize incorrect for 16k pages
mmu_virtual_psize shall be set to MMU_PAGE_16K when 16k pages have
been selected
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/include/asm/mmu-8xx.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/include/asm/mmu-8xx.h
b/arch/powerpc/include/asm/mmu-8xx.h
index 986b9e1..d41200c 100644
--- a/arch/powerpc/include/asm/mmu-8xx.h
+++ b/arch/powerpc/include/asm/mmu-8xx.h
@@ -145,7 +145,14 @@ typedef struct {
} mm_context_t;
#endif /* !__ASSEMBLY__ */
+#if (PAGE_SHIFT == 12)
#define mmu_virtual_psize MMU_PAGE_4K
+#elif (PAGE_SHIFT == 14)
+#define mmu_virtual_psize MMU_PAGE_16K
+#else
+#error Unsupported PAGE_SIZE
+#endif
+
#define mmu_linear_psize MMU_PAGE_8M
#endif /* _ASM_POWERPC_MMU_8XX_H_ */
--
2.1.0
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[PATCH v5 2/5] powerpc/8xx: Handle CR out of exception PROLOG/EPILOG
In order to be able to reduce scope during which CR is saved, we take CR saving/restoring out of exception PROLOG and EPILOG Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 10 +++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 1279018..5a69c5e 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -116,13 +116,13 @@ turn_on_mmu: */ #define EXCEPTION_PROLOG \ EXCEPTION_PROLOG_0; \ + mfcrr10;\ EXCEPTION_PROLOG_1; \ EXCEPTION_PROLOG_2 #define EXCEPTION_PROLOG_0 \ mtspr SPRN_SPRG_SCRATCH0,r10; \ - mtspr SPRN_SPRG_SCRATCH1,r11; \ - mfcrr10 + mtspr SPRN_SPRG_SCRATCH1,r11 #define EXCEPTION_PROLOG_1 \ mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \ @@ -162,7 +162,6 @@ turn_on_mmu: * Exception exit code. */ #define EXCEPTION_EPILOG_0 \ - mtcrr10;\ mfspr r10,SPRN_SPRG_SCRATCH0; \ mfspr r11,SPRN_SPRG_SCRATCH1 @@ -313,6 +312,7 @@ InstructionTLBMiss: mtspr SPRN_DAR, r3 #endif EXCEPTION_PROLOG_0 + mfcrr10 mtspr SPRN_SPRG_SCRATCH2, r10 mfspr r10, SPRN_SRR0 /* Get effective address of fault */ INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10) @@ -363,6 +363,7 @@ InstructionTLBMiss: mtspr SPRN_DAR, r11 /* Tag DAR */ #endif mfspr r10, SPRN_SPRG_SCRATCH2 + mtcrr10 EXCEPTION_EPILOG_0 rfi @@ -372,6 +373,7 @@ DataStoreTLBMiss: mtspr SPRN_DAR, r3 #endif EXCEPTION_PROLOG_0 + mfcrr10 mtspr SPRN_SPRG_SCRATCH2, r10 mfspr r10, SPRN_MD_EPN @@ -437,6 +439,7 @@ DataStoreTLBMiss: #endif mtspr SPRN_DAR, r11 /* Tag DAR */ mfspr r10, SPRN_SPRG_SCRATCH2 + mtcrr10 EXCEPTION_EPILOG_0 rfi @@ -462,6 +465,7 @@ InstructionTLBError: . = 0x1400 DataTLBError: EXCEPTION_PROLOG_0 + mfcrr10 mfspr r11, SPRN_DAR cmpwi cr0, r11, RPN_PATTERN -- 2.1.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: 'perf upgrade' (was: Re: [PATCH v9 00/11] Add support for JSON event files.)
On Wed, Apr 15, 2015 at 01:50:42PM -0700, Sukadev Bhattiprolu wrote: SNIP | | - to blindly follow some poorly constructed vendor format with no |high level structure, that IMHO didn't work very well when OProfile |was written, and misrepresenting it as 'symbolic event names'. | |Take a look at: | | https://download.01.org/perfmon/HSW/Haswell_core_V17.json | |and weep. Evil vendor formats, but to be fair, here is what _we_ have today: perf stat -e r10068,r20036,r40060,r40ac sleep 1 hum, you could also use the 'cpu/event=.../' syntax right? It's not symbolic name, just to be fair ;-) jirka ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v5 1/5] powerpc/8xx: macro for handling CPU15 errata
Having a macro will help keep clear code. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 18 -- 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 9b53fe1..1279018 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -297,6 +297,17 @@ SystemCall: * We have to use the MD_xxx registers for the tablewalk because the * equivalent MI_xxx registers only perform the attribute functions. */ + +#ifdef CONFIG_8xx_CPU15 +#define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) \ + additmp, addr, PAGE_SIZE; \ + tlbie tmp;\ + additmp, addr, -PAGE_SIZE; \ + tlbie tmp +#else +#define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) +#endif + InstructionTLBMiss: #ifdef CONFIG_8xx_CPU6 mtspr SPRN_DAR, r3 @@ -304,12 +315,7 @@ InstructionTLBMiss: EXCEPTION_PROLOG_0 mtspr SPRN_SPRG_SCRATCH2, r10 mfspr r10, SPRN_SRR0 /* Get effective address of fault */ -#ifdef CONFIG_8xx_CPU15 - addir11, r10, PAGE_SIZE - tlbie r11 - addir11, r10, -PAGE_SIZE - tlbie r11 -#endif + INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10) /* If we are faulting a kernel address, we have to use the * kernel page tables. -- 2.1.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: 'perf upgrade' (was: Re: [PATCH v9 00/11] Add support for JSON event files.)
On Fri, Apr 17, 2015 at 05:31:26PM +0200, Jiri Olsa wrote: On Wed, Apr 15, 2015 at 01:50:42PM -0700, Sukadev Bhattiprolu wrote: SNIP | | - to blindly follow some poorly constructed vendor format with no |high level structure, that IMHO didn't work very well when OProfile |was written, and misrepresenting it as 'symbolic event names'. | |Take a look at: | | https://download.01.org/perfmon/HSW/Haswell_core_V17.json | |and weep. Evil vendor formats, but to be fair, here is what _we_ have today: perf stat -e r10068,r20036,r40060,r40ac sleep 1 hum, you could also use the 'cpu/event=.../' syntax right? That's even worse -- same hex numbers, just more redundancy. All the other profilers support symbolic names, which is what users want. -Andi -- a...@linux.intel.com -- Speaking for myself only ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/mm: Use PFN_PHYS() in devmem_is_allowed()
This function can run on systems where physical addresses don't
fit in unsigned long, so make sure to use the macro that contains the
proper cast.
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/mm/mem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index 7297d204..07052d9 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -563,7 +563,7 @@ subsys_initcall(add_system_ram_resources);
*/
int devmem_is_allowed(unsigned long pfn)
{
- if (iomem_is_exclusive(pfn PAGE_SHIFT))
+ if (iomem_is_exclusive(PFN_PHYS(pfn)))
return 0;
if (!page_is_ram(pfn))
return 1;
--
2.1.0
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Re: [3/3] P1021RDB: Add QE TDM support
On Thu, Mar 26, 2015 at 05:16:17PM +0800, ying.zh...@freescale.com wrote:
@@ -96,37 +102,63 @@ static void __init mpc85xx_rdb_setup_arch(void)
#ifdef CONFIG_QUICC_ENGINE
mpc85xx_qe_init();
mpc85xx_qe_par_io_init();
-#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
- if (machine_is(p1025_rdb)) {
- struct device_node *np;
-
- struct ccsr_guts __iomem *guts;
-
- np = of_find_node_by_name(NULL, global-utilities);
- if (np) {
- guts = of_iomap(np, 0);
- if (!guts) {
-
- pr_err(mpc85xx-rdb: could not map global
utilities register\n);
+#ifdef CONFIG_SPI_FSL_SPI
+ for_each_node_by_name(qe_spi, spi)
+ par_io_of_config(qe_spi);
Why are you assuming that any node named spi is a QE SPI?
+#endif /* CONFIG_SPI_FSL_SPI */
- } else {
- /* P1025 has pins muxed for QE and other functions. To
- * enable QE UEC mode, we need to set bit QE0 for UCC1
- * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
- * and QE12 for QE MII management singals in PMUXCR
- * register.
- */
+ np = of_find_node_by_name(NULL, global-utilities);
+ if (np) {
+ guts = of_iomap(np, 0);
+ if (!guts)
+ pr_err(mpc85xx-rdb: could not map global %s\n,
+ utilities register);
+ else {
Don't put a bunch of code in the else of an error check. Factor this out
to its own function and return early if you don't find what you're
looking for.
-Scott
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[PATCH 1/2] powerpc/qman: Change fsl,qman-channel-id to cell-index
It turns out that existing U-Boots will dereference NULL pointers
if the device tree does not have cell-index in the portal nodes.
No patch has yet been merged adding device tree nodes for this binding
(except a dtsi that has not yet been referenced), nor has any driver
yet been merged making use of the binding, so it's not too late to
change the binding in order to keep compatibility with existing
U-Boots.
Signed-off-by: Scott Wood scottw...@freescale.com
Cc: Madalin-Cristian Bucur madalin.bu...@freescale.com
---
Documentation/devicetree/bindings/soc/fsl/qman-portals.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/soc/fsl/qman-portals.txt
b/Documentation/devicetree/bindings/soc/fsl/qman-portals.txt
index 48c4dae..47e46cc 100644
--- a/Documentation/devicetree/bindings/soc/fsl/qman-portals.txt
+++ b/Documentation/devicetree/bindings/soc/fsl/qman-portals.txt
@@ -47,7 +47,7 @@ PROPERTIES
For additional details about the PAMU/LIODN binding(s) see pamu.txt
-- fsl,qman-channel-id
+- cell-index
Usage: Required
Value type: u32
Definition: The hardware index of the channel. This can also be
@@ -136,7 +136,7 @@ The example below shows a (P4080) QMan portals
container/bus node with two porta
reg = 0x4000 0x4000, 0x101000 0x1000;
interrupts = 106 2 0 0;
fsl,liodn = 3 4;
- fsl,qman-channel-id = 1;
+ cell-index = 1;
fman0 {
fsl,liodn = 0x22;
--
2.1.0
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[PATCH 2/2] powerpc/mpc85xx: Add FSL QorIQ DPAA QMan support to device tree(s)
From: Kumar Gala ga...@kernel.crashing.org
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
Signed-off-by: Geoff Thorpe geoff.tho...@freescale.com
Signed-off-by: Hai-Ying Wang haiying.w...@freescale.com
Signed-off-by: Chunhe Lan chunhe@freescale.com
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
[Emil Medve: Sync with the upstream binding]
Signed-off-by: Emil Medve emilian.me...@freescale.com
[Scott Wood: s/fsl,qman-channel-id/cell-index]
Signed-off-by: Scott Wood scottw...@freescale.com
Cc: Madalin-Cristian Bucur madalin.bu...@freescale.com
---
arch/powerpc/boot/dts/b4qds.dtsi | 12 +
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi| 69 +
arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 106 +++
arch/powerpc/boot/dts/fsl/p1023si-post.dtsi| 43 +++
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi| 13 +
arch/powerpc/boot/dts/fsl/p3041si-post.dtsi| 13 +
arch/powerpc/boot/dts/fsl/p4080si-post.dtsi| 13 +
arch/powerpc/boot/dts/fsl/p5020si-post.dtsi| 13 +
arch/powerpc/boot/dts/fsl/p5040si-post.dtsi| 13 +
arch/powerpc/boot/dts/fsl/qoriq-qman1-portals.dtsi | 20 +-
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi| 78 +
arch/powerpc/boot/dts/fsl/t2081si-post.dtsi| 126
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi| 318 +
arch/powerpc/boot/dts/kmcoge4.dts | 12 +
arch/powerpc/boot/dts/oca4080.dts | 12 +
arch/powerpc/boot/dts/p1023rdb.dts | 12 +
arch/powerpc/boot/dts/p2041rdb.dts | 12 +
arch/powerpc/boot/dts/p3041ds.dts | 12 +
arch/powerpc/boot/dts/p4080ds.dts | 12 +
arch/powerpc/boot/dts/p5020ds.dts | 12 +
arch/powerpc/boot/dts/p5040ds.dts | 12 +
arch/powerpc/boot/dts/t104xqds.dtsi| 12 +
arch/powerpc/boot/dts/t104xrdb.dtsi| 12 +
arch/powerpc/boot/dts/t208xqds.dtsi| 12 +
arch/powerpc/boot/dts/t208xrdb.dtsi| 12 +
arch/powerpc/boot/dts/t4240qds.dts | 12 +
arch/powerpc/boot/dts/t4240rdb.dts | 12 +
27 files changed, 995 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/boot/dts/b4qds.dtsi b/arch/powerpc/boot/dts/b4qds.dtsi
index 24ed80d..559d006 100644
--- a/arch/powerpc/boot/dts/b4qds.dtsi
+++ b/arch/powerpc/boot/dts/b4qds.dtsi
@@ -106,6 +106,14 @@
size = 0 0x100;
alignment = 0 0x100;
};
+ qman_fqd: qman-fqd {
+ size = 0 0x40;
+ alignment = 0 0x40;
+ };
+ qman_pfdr: qman-pfdr {
+ size = 0 0x200;
+ alignment = 0 0x200;
+ };
};
dcsr: dcsr@f {
@@ -116,6 +124,10 @@
ranges = 0x0 0xf 0xf400 0x200;
};
+ qportals: qman-portals@ff600 {
+ ranges = 0x0 0xf 0xf600 0x200;
+ };
+
soc: soc@ffe00 {
ranges = 0x 0xf 0xfe00 0x100;
reg = 0xf 0xfe00 0 0x1000;
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index f35e9e0..5af90fd 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -167,6 +167,75 @@
};
};
+qportals {
+ qportal14: qman-portal@38000 {
+ compatible = fsl,qman-portal;
+ reg = 0x38000 0x4000, 0x100e000 0x1000;
+ interrupts = 132 0x2 0 0;
+ cell-index = 0xe;
+ };
+ qportal15: qman-portal@3c000 {
+ compatible = fsl,qman-portal;
+ reg = 0x3c000 0x4000, 0x100f000 0x1000;
+ interrupts = 134 0x2 0 0;
+ cell-index = 0xf;
+ };
+ qportal16: qman-portal@4 {
+ compatible = fsl,qman-portal;
+ reg = 0x4 0x4000, 0x101 0x1000;
+ interrupts = 136 0x2 0 0;
+ cell-index = 0x10;
+ };
+ qportal17: qman-portal@44000 {
+ compatible = fsl,qman-portal;
+ reg = 0x44000 0x4000, 0x1011000 0x1000;
+ interrupts = 138 0x2 0 0;
+ cell-index = 0x11;
+ };
+ qportal18: qman-portal@48000 {
+ compatible = fsl,qman-portal;
+ reg = 0x48000 0x4000, 0x1012000 0x1000;
+ interrupts = 140 0x2 0 0;
+ cell-index = 0x12;
+ };
+ qportal19: qman-portal@4c000 {
+ compatible = fsl,qman-portal;
+ reg = 0x4c000 0x4000, 0x1013000 0x1000;
+ interrupts = 142 0x2 0 0;
+ cell-index = 0x13;
+ };
+ qportal20: qman-portal@5 {
+
[PATCH v5 4/5] powerpc/8xx: Use SPRG2 instead of DAR for saving r3
We now have SPRG2 available as in it not used anymore for saving CR, so we don't need to crash DAR anymore for saving r3 for CPU6 ERRATA handling. Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 9 - 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 150d03f..ba2dc53 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -309,7 +309,7 @@ SystemCall: InstructionTLBMiss: #ifdef CONFIG_8xx_CPU6 - mtspr SPRN_DAR, r3 + mtspr SPRN_SPRG_SCRATCH2, r3 #endif EXCEPTION_PROLOG_0 @@ -362,8 +362,7 @@ InstructionTLBMiss: /* Restore registers */ #ifdef CONFIG_8xx_CPU6 - mfspr r3, SPRN_DAR - mtspr SPRN_DAR, r11 /* Tag DAR */ + mfspr r3, SPRN_SPRG_SCRATCH2 #endif EXCEPTION_EPILOG_0 rfi @@ -371,7 +370,7 @@ InstructionTLBMiss: . = 0x1200 DataStoreTLBMiss: #ifdef CONFIG_8xx_CPU6 - mtspr SPRN_DAR, r3 + mtspr SPRN_SPRG_SCRATCH2, r3 #endif EXCEPTION_PROLOG_0 mfcrr10 @@ -438,7 +437,7 @@ DataStoreTLBMiss: /* Restore registers */ #ifdef CONFIG_8xx_CPU6 - mfspr r3, SPRN_DAR + mfspr r3, SPRN_SPRG_SCRATCH2 #endif mtspr SPRN_DAR, r11 /* Tag DAR */ EXCEPTION_EPILOG_0 -- 2.1.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/defconfig: new way of writing defconfig
It is always a headache dealing with different defconfigs
though they only differ in few places. Hence we are proposing a new
way of writing defconfig:
1. Define a basic defconfig say mpc85xx_basic_defconfig
2. Spin off as much features as possible from mpc85xx_defconfig
and create a separate config file, say, kvm_guest.config
Every time we add a new feature, we don't need to change several
defconfigs, we just add a new *.config
And you could merge any fragments you want into .config with the
current kconfig in Kernel.
Say you want to build mpc85xx_smp_defconfig, you do 3 steps
make mpc85xx_basic_defconfig
make smp.config
make kvm_guest.config
or just
make mpc85xx_smp_defconfig
Signed-off-by: Lijun Pan lijun@freescale.com
---
arch/powerpc/Makefile | 17 ++
...t32_smp_defconfig = corenet32_basic_defconfig} | 0
...t64_smp_defconfig = corenet64_basic_defconfig} | 0
arch/powerpc/configs/kvm_guest.config | 2 +
.../{mpc85xx_defconfig = mpc85xx_basic_defconfig} | 0
arch/powerpc/configs/mpc85xx_smp_defconfig | 244 -
arch/powerpc/configs/smp.config| 1 +
7 files changed, 20 insertions(+), 244 deletions(-)
rename arch/powerpc/configs/{corenet32_smp_defconfig =
corenet32_basic_defconfig} (100%)
rename arch/powerpc/configs/{corenet64_smp_defconfig =
corenet64_basic_defconfig} (100%)
create mode 100644 arch/powerpc/configs/kvm_guest.config
rename arch/powerpc/configs/{mpc85xx_defconfig = mpc85xx_basic_defconfig}
(100%)
delete mode 100644 arch/powerpc/configs/mpc85xx_smp_defconfig
create mode 100644 arch/powerpc/configs/smp.config
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
index fc502e0..590b441 100644
--- a/arch/powerpc/Makefile
+++ b/arch/powerpc/Makefile
@@ -269,6 +269,23 @@ bootwrapper_install:
%.dtb: scripts
$(Q)$(MAKE) ARCH=ppc64 $(build)=$(boot) $(patsubst %,$(boot)/%,$@)
+define domerge
+ $(Q)$(CONFIG_SHELL) $(srctree)/scripts/kconfig/merge_config.sh
$(srctree)/.config $(srctree)/arch/powerpc/configs/$(1).config
+endef
+
+mpc85xx_defconfig: mpc85xx_basic_defconfig
+ @:
+
+mpc85xx_smp_defconfig: mpc85xx_basic_defconfig
+ $(call domerge,smp)
+ $(call domerge,kvm_guest)
+
+corenet32_smp_defconfig: corenet32_basic_defconfig
+ $(call domerge,smp)
+
+corenet64_smp_defconfig: corenet64_basic_defconfig
+ $(call domerge,smp)
+
define archhelp
@echo '* zImage - Build default images selected by kernel config'
@echo ' zImage.*- Compressed kernel image
(arch/$(ARCH)/boot/zImage.*)'
diff --git a/arch/powerpc/configs/corenet32_smp_defconfig
b/arch/powerpc/configs/corenet32_basic_defconfig
similarity index 100%
rename from arch/powerpc/configs/corenet32_smp_defconfig
rename to arch/powerpc/configs/corenet32_basic_defconfig
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig
b/arch/powerpc/configs/corenet64_basic_defconfig
similarity index 100%
rename from arch/powerpc/configs/corenet64_smp_defconfig
rename to arch/powerpc/configs/corenet64_basic_defconfig
diff --git a/arch/powerpc/configs/kvm_guest.config
b/arch/powerpc/configs/kvm_guest.config
new file mode 100644
index 000..615b0a0
--- /dev/null
+++ b/arch/powerpc/configs/kvm_guest.config
@@ -0,0 +1,2 @@
+CONFIG_KVM_GUEST=y
+CONFIG_PPC_QEMU_E500=y
diff --git a/arch/powerpc/configs/mpc85xx_defconfig
b/arch/powerpc/configs/mpc85xx_basic_defconfig
similarity index 100%
rename from arch/powerpc/configs/mpc85xx_defconfig
rename to arch/powerpc/configs/mpc85xx_basic_defconfig
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig
b/arch/powerpc/configs/mpc85xx_smp_defconfig
deleted file mode 100644
index b6c7111..000
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ /dev/null
@@ -1,244 +0,0 @@
-CONFIG_PPC_85xx=y
-CONFIG_PHYS_64BIT=y
-CONFIG_SMP=y
-CONFIG_NR_CPUS=8
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_AUDIT=y
-CONFIG_IRQ_DOMAIN_DEBUG=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_MAC_PARTITION=y
-CONFIG_C293_PCIE=y
-CONFIG_MPC8540_ADS=y
-CONFIG_MPC8560_ADS=y
-CONFIG_MPC85xx_CDS=y
-CONFIG_MPC85xx_MDS=y
-CONFIG_MPC8536_DS=y
-CONFIG_MPC85xx_DS=y
-CONFIG_MPC85xx_RDB=y
-CONFIG_P1010_RDB=y
-CONFIG_P1022_DS=y
-CONFIG_P1022_RDK=y
-CONFIG_P1023_RDB=y
-CONFIG_SOCRATES=y
-CONFIG_KSI8560=y
-CONFIG_XES_MPC85xx=y
-CONFIG_STX_GP3=y
-CONFIG_TQM8540=y
-CONFIG_TQM8541=y
-CONFIG_TQM8548=y
-CONFIG_TQM8555=y
-CONFIG_TQM8560=y
-CONFIG_SBC8548=y
-CONFIG_QUICC_ENGINE=y
-CONFIG_QE_GPIO=y
-CONFIG_HIGHMEM=y
-CONFIG_BINFMT_MISC=m
-CONFIG_MATH_EMULATION=y
-CONFIG_FORCE_MAX_ZONEORDER=12
-CONFIG_PCI=y
-CONFIG_PCI_MSI=y
-CONFIG_RAPIDIO=y
RE: new way of writing defconfigs for freescale's powerpc platforms
-Original Message- From: Wood Scott-B07421 Sent: Friday, April 17, 2015 1:53 PM To: Pan Lijun-B44306 Cc: Michael Ellerman; linuxppc-...@ozlabs.org; Schmitt Richard-B43082 Subject: Re: new way of writing defconfigs for freescale's powerpc platforms On Fri, 2015-04-17 at 13:50 -0500, Pan Lijun-B44306 wrote: -Original Message- From: Michael Ellerman [mailto:m...@ellerman.id.au] Sent: Friday, April 17, 2015 1:19 AM To: Wood Scott-B07421 Cc: Pan Lijun-B44306; linuxppc-...@ozlabs.org; Schmitt Richard-B43082 Subject: Re: new way of writing defconfigs for freescale's powerpc platforms On Thu, 2015-04-16 at 23:13 -0500, Scott Wood wrote: On Fri, 2015-04-17 at 10:54 +1000, Michael Ellerman wrote: On Thu, 2015-04-09 at 21:52 +, Lijun Pan wrote: Hi Maintainers, We have a proposal for writing the defconfigs for freescale's powperpc platforms in a new way. Can you take a look and provide some feedback? You know currently we have mpc85xx_defconfig, corenet32_defconfig, bsc913x_defconfig, *fman*_defconfig, etc. We are going to extract some common parts from the existing defconfigs, and name it, say, fsl_basic_defconfig. Then, we could create some defconfigs targeting specific features or specific platforms. Say, features specific: kvm_defconfig, fman_defconfig, etc. Platforms specific: p1_defconfig, p2_defcongfig, p4_defconfig, t1_defconfig, t2_defconfig, t2_defconfig, b4_defconfig, etc When we want to make a kernel image for p1 platform, Using the following steps: make ./scripts/kconfig/merge_config.sh arch/powerpc/configs/fsl_basic_config p1_defconfig make What do you think of this new approach? I don't like that the user has to manually run merge_config.sh. How does a user even know that it's an option? It also breaks scripts that auto build the kernel, which expect to be able to do: $ make foo_defconfig $ make Scripts like mine for example :) http://kisskb.ellerman.id.au/kisskb/head/8734/ What I'd be happy with is something that does merge_config under the covers. So a user still runs 'make fsl_plat_foo_defconfig', but under the covers it does a merge config. kvmconfig and tinyconfig are implemented that way already, so with a bit more work hopefully you can do that for arch configs also. kvmconfig and tinyconfig are still separate user-visible steps to be applied after running a base defconfig. Not as of recently: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/comm it/scripts/kc onfig/Makefile?id=63a91033d52e64a22e571fe84924c0b7f21c280d Above patch is very generic. With this patch, we don't even need to modify arch/powerpc/Makefile. We can just add fragments (like smp.config, kvm_guest.config, etc) under arch/powerpc/configs/ or add platform independent config under kernel/configs/ example might be: make mpc85xx_defconfig make smp.config make kvm_guest.config The point is that the user should not have to do that. They can if they want, but there should still be traditional named configs, which would just work differently under the hood. -Scott Have just sent out a patch considering the previous discussion. http://patchwork.ozlabs.org/patch/462249/ [PATCH] powerpc/defconfig: new way of writing defconfig ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v3 03/17] crypto: talitos - talitos_ptr renamed ptr for more lisibility
Le 17/04/2015 17:14, David Laight a écrit :
From: Christophe Leroy
Linux CodyingStyle recommends to use short variables for local
variables. ptr is just good enough for those 3 lines functions.
It helps keep single lines shorter than 80 characters.
...
-static void to_talitos_ptr(struct talitos_ptr *talitos_ptr, dma_addr_t
dma_addr)
+static void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr)
{
- talitos_ptr-ptr = cpu_to_be32(lower_32_bits(dma_addr));
- talitos_ptr-eptr = upper_32_bits(dma_addr);
+ ptr-ptr = cpu_to_be32(lower_32_bits(dma_addr));
+ ptr-eptr = upper_32_bits(dma_addr);
}
...
Maybe, but 'ptr' isn't a good choice.
Any suggestion ?
Christophe
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[PATCH v5 3/5] powerpc/8xx: dont save CR in SCRATCH registers
CR only needs to be preserved when checking if we are handling a kernel address. So we can preserve CR in a register: - In ITLBMiss, check is done only when CONFIG_MODULES is defined. Otherwise we don't need to do anything at all with CR. - We use r10, then we reload SRR0/MD_EPN into r10 when CR is restored Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 29 +++-- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 5a69c5e..150d03f 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -312,10 +312,6 @@ InstructionTLBMiss: mtspr SPRN_DAR, r3 #endif EXCEPTION_PROLOG_0 - mfcrr10 - mtspr SPRN_SPRG_SCRATCH2, r10 - mfspr r10, SPRN_SRR0 /* Get effective address of fault */ - INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10) /* If we are faulting a kernel address, we have to use the * kernel page tables. @@ -323,13 +319,20 @@ InstructionTLBMiss: #ifdef CONFIG_MODULES /* Only modules will cause ITLB Misses as we always * pin the first 8MB of kernel memory */ - andis. r11, r10, 0x8000/* Address = 0x8000 */ -#endif + mfspr r11, SPRN_SRR0 /* Get effective address of fault */ + INVALIDATE_ADJACENT_PAGES_CPU15(r10, r11) + mfcrr10 + andis. r11, r11, 0x8000/* Address = 0x8000 */ mfspr r11, SPRN_M_TW /* Get level 1 table */ -#ifdef CONFIG_MODULES beq 3f lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha 3: + mtcrr10 + mfspr r10, SPRN_SRR0 /* Get effective address of fault */ +#else + mfspr r10, SPRN_SRR0 /* Get effective address of fault */ + INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10) + mfspr r11, SPRN_M_TW /* Get level 1 table base address */ #endif /* Insert level 1 index */ rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) 1), (PAGE_SHIFT - 2) 1, 29 @@ -362,8 +365,6 @@ InstructionTLBMiss: mfspr r3, SPRN_DAR mtspr SPRN_DAR, r11 /* Tag DAR */ #endif - mfspr r10, SPRN_SPRG_SCRATCH2 - mtcrr10 EXCEPTION_EPILOG_0 rfi @@ -374,17 +375,19 @@ DataStoreTLBMiss: #endif EXCEPTION_PROLOG_0 mfcrr10 - mtspr SPRN_SPRG_SCRATCH2, r10 - mfspr r10, SPRN_MD_EPN /* If we are faulting a kernel address, we have to use the * kernel page tables. */ - andis. r11, r10, 0x8000 + mfspr r11, SPRN_MD_EPN + andis. r11, r11, 0x8000 mfspr r11, SPRN_M_TW /* Get level 1 table */ beq 3f lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha 3: + mtcrr10 + mfspr r10, SPRN_MD_EPN + /* Insert level 1 index */ rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) 1), (PAGE_SHIFT - 2) 1, 29 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11)/* Get the level 1 entry */ @@ -438,8 +441,6 @@ DataStoreTLBMiss: mfspr r3, SPRN_DAR #endif mtspr SPRN_DAR, r11 /* Tag DAR */ - mfspr r10, SPRN_SPRG_SCRATCH2 - mtcrr10 EXCEPTION_EPILOG_0 rfi -- 2.1.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v5 5/5] powerpc/8xx: Add support for TASK_SIZE greater than 0x80000000
By default, TASK_SIZE is set to 0x8000 for PPC_8xx, which is most likely sufficient for most cases. However, kernel configuration allows to set TASK_SIZE to another value, so the 8xx shall handle it. This patch also takes into account the case of PAGE_OFFSET lower than 0x8000, allthought most of the time it is equal to 0xC000 Signed-off-by: Christophe Leroy christophe.le...@c-s.fr --- arch/powerpc/kernel/head_8xx.S | 25 +++-- 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index ba2dc53..c640bbb 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -48,6 +48,19 @@ mtspr spr, reg #endif +/* Macro to test if an address is a kernel address */ +#if CONFIG_TASK_SIZE = 0x8000 CONFIG_PAGE_OFFSET = 0x8000 +#define IS_KERNEL(tmp, addr) \ + andis. tmp, addr, 0x8000 /* Address = 0x8000 */ +#define BRANCH_UNLESS_KERNEL(label)beq label +#else +#define IS_KERNEL(tmp, addr) \ + rlwinm tmp, addr, 16, 16, 31; \ + cmpli cr0, tmp, PAGE_OFFSET 16 +#define BRANCH_UNLESS_KERNEL(label)blt label +#endif + + /* * Value for the bits that have fixed value in RPN entries. * Also used for tagging DAR for DTLBerror. @@ -322,9 +335,9 @@ InstructionTLBMiss: mfspr r11, SPRN_SRR0 /* Get effective address of fault */ INVALIDATE_ADJACENT_PAGES_CPU15(r10, r11) mfcrr10 - andis. r11, r11, 0x8000/* Address = 0x8000 */ + IS_KERNEL(r11, r11) mfspr r11, SPRN_M_TW /* Get level 1 table */ - beq 3f + BRANCH_UNLESS_KERNEL(3f) lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha 3: mtcrr10 @@ -379,9 +392,9 @@ DataStoreTLBMiss: * kernel page tables. */ mfspr r11, SPRN_MD_EPN - andis. r11, r11, 0x8000 + IS_KERNEL(r11, r11) mfspr r11, SPRN_M_TW /* Get level 1 table */ - beq 3f + BRANCH_UNLESS_KERNEL(3f) lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha 3: mtcrr10 @@ -513,9 +526,9 @@ FixupDAR:/* Entry point for dcbx workaround. */ mtspr SPRN_SPRG_SCRATCH2, r10 /* fetch instruction from memory. */ mfspr r10, SPRN_SRR0 - andis. r11, r10, 0x8000/* Address = 0x8000 */ + IS_KERNEL(r11, r10) mfspr r11, SPRN_M_TW /* Get level 1 table */ - beq 3f + BRANCH_UNLESS_KERNEL(3f) lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha /* Insert level 1 index */ 3: rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) 1), (PAGE_SHIFT - 2) 1, 29 -- 2.1.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
