date:20230912



Le 12/09/2023 à 22:09, Erhard Furtner a écrit :
> On Tue, 12 Sep 2023 17:39:10 +
> Christophe Leroy  wrote:
> 
>> Ah ok, maybe your CPU only has 4 BATs and they are all used, following
>> change would tell us.
>>
>> diff --git a/arch/powerpc/mm/book3s32/mmu.c b/arch/powerpc/mm/book3s32/mmu.c
>> index 850783cfa9c7..bd26767edce7 100644
>> --- a/arch/powerpc/mm/book3s32/mmu.c
>> +++ b/arch/powerpc/mm/book3s32/mmu.c
>> @@ -86,6 +86,7 @@ int __init find_free_bat(void)
>>  if (!(bat[1].batu & 3))
>>  return b;
>>  }
>> +pr_err("NO FREE BAT (%d)\n", n);
>>  return -1;
>>}
>>
>> Or you have 8 BATs in which case it's an alignment problem, you need to
>> increase CONFIG_DATA_SHIFT to 23, for that you need CONFIG_ADVANCED and
>> CONFIG_DATA_SHIFT_BOOL
> 
> Applied all your patches. According to the output my G4 DP seems to have 8 
> BATs. Now I get the following output on screen before the freeze:
> 
> printk: bootconsole [udbg0] enabled
> Total memory = 2048MB; using 4096kB for hash table
> mapin_ram:125
> mmu_mapin_ram:170 0 3000 140 200
> __mmu_mapin_ram:147 0 140
> __mmu_mapin_ram:156 140
> __mmu_mapin_ram:147 140 3000
> NO FREE BAT (8)
> __mmu_mapin_ram:156 2000
> __mapin_ram_chunk:107 2000 3000
> __mapin_ram_chunk:117
> mapin_ram:134
> kasan_mmu_init:132
> kasan_mmu_init:135 0
> kasan_mmu_init:140
> ioremap() called early from btext_map+0x64/0xdc. Use early_ioremap() instead
> Linux version 6.6.0-rc1-PMacG4-dirty (root@T1000) (gcc (Gentoo 
> 12.3.1_p20230526 p2) 12.3.1 20230526, GNU ld (Gentoo 2.40 p7) 2.40.0) #5 SMP 
> Tue Sep 12 16:50:47 CEST 2023
> kasan_init_region: c000 3000 f800 fe00
> NO FREE BAT (8)
> kasan_init_region: loop f800 fe00
> 
> 
> So I set CONFIG_DATA_SHIFT=23 as suggested but then I only get:
> 
> printk: bootconsole [udbg0] enabled
> Total memory = 2048MB; using 4096kB for hash table
> mapin_ram:125
> mmu_mapin_ram:170 0 3000 140 200
> __mmu_mapin_ram:147 0 140
> __mmu_mapin_ram:156 140
> __mmu_mapin_ram:147 140 3000
> NO FREE BAT (8)
> __mmu_mapin_ram:156 2000
> __mapin_ram_chunk:107 2000 3000
> __mapin_ram_chunk:117
> mapin_ram:134
> kasan_mmu_init:132
> kasan_mmu_init:135 0
> kasan_mmu_init:140
> 
> 
> With btext_unmap() left in place in init_32.c I only get:
> 
> printk: bootconsole [udbg0] enabled
> Total memory = 2048MB; using 4096kB for hash table
> mapin_ram:125
> mmu_mapin_ram:170 0 3000 140 200
> __mmu_mapin_ram:147 0 140
> __mmu_mapin_ram:156 140
> __mmu_mapin_ram:147 140 3000
> NO FREE BAT (8)
> __mmu_mapin_ram:156 2000
> __mapin_ram_chunk:107 2000 3000
> __mapin_ram_chunk:117
> mapin_ram:134
> btext_unmap:129
> 
> Hope the output sheds at least some light on what's going wrong!
> 

Can you send me (off-list ?) the two vmlinux binaries (The one with data 
shift 22 and the one with 23) and also your latest .config

About the shift 23, I suspect that ppc32 still doesn't like when .init 
is past the first 32 Mb.

Thanks
Christophe

[powerpc:topic/ppc-kvm] BUILD REGRESSION 5af8497e01ed97410b2f19ca8320a3bcdcfe267b

tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git 
topic/ppc-kvm
branch HEAD: 5af8497e01ed97410b2f19ca8320a3bcdcfe267b  docs: powerpc: Document 
nested KVM on POWER

Error/Warning reports:

https://lore.kernel.org/oe-kbuild-all/202309130700.eru2idwo-...@intel.com
https://lore.kernel.org/oe-kbuild-all/202309130935.bj7eusw4-...@intel.com

Error/Warning: (recently discovered and may have been fixed)

arch/powerpc/kvm/book3s_hv_nestedv2.c:465:29: error: variable 'amor' set but 
not used [-Werror=unused-but-set-variable]
arch/powerpc/kvm/guest-state-buffer.c:505: warning: expecting prototype for 
kvmppc_gsm_init(). Prototype was for kvmppc_gsm_new() instead
arch/powerpc/kvm/guest-state-buffer.c:565: warning: expecting prototype for 
kvmppc_gsm_fill_info(). Prototype was for kvmppc_gsm_refresh_info() instead

Error/Warning ids grouped by kconfigs:

gcc_recent_errors
`-- powerpc-ppc64_defconfig
|-- 
arch-powerpc-kvm-book3s_hv_nestedv2.c:error:variable-amor-set-but-not-used
|-- 
arch-powerpc-kvm-guest-state-buffer.c:warning:expecting-prototype-for-kvmppc_gsm_fill_info().-Prototype-was-for-kvmppc_gsm_refresh_info()-instead
`-- 
arch-powerpc-kvm-guest-state-buffer.c:warning:expecting-prototype-for-kvmppc_gsm_init().-Prototype-was-for-kvmppc_gsm_new()-instead

elapsed time: 887m

configs tested: 220
configs skipped: 2

tested configs:
alpha allnoconfig   gcc  
alphaallyesconfig   gcc  
alpha   defconfig   gcc  
alpharandconfig-r021-20230913   gcc  
alpharandconfig-r023-20230913   gcc  
arc  allmodconfig   gcc  
arc   allnoconfig   gcc  
arc  allyesconfig   gcc  
arc  axs103_defconfig   gcc  
arc defconfig   gcc  
arc nsimosci_hs_defconfig   gcc  
arm  allmodconfig   gcc  
arm   allnoconfig   gcc  
arm  allyesconfig   gcc  
arm defconfig   gcc  
arm lpc18xx_defconfig   gcc  
arm   omap1_defconfig   clang
arm  randconfig-r016-20230913   gcc  
arm64allmodconfig   gcc  
arm64 allnoconfig   gcc  
arm64allyesconfig   gcc  
arm64   defconfig   gcc  
arm64randconfig-r012-20230913   clang
csky allmodconfig   gcc  
csky  allnoconfig   gcc  
csky allyesconfig   gcc  
cskydefconfig   gcc  
csky randconfig-r006-20230913   gcc  
csky randconfig-r013-20230912   gcc  
csky randconfig-r025-20230913   gcc  
hexagon   randconfig-001-20230913   clang
hexagon   randconfig-002-20230913   clang
hexagon  randconfig-r003-20230913   clang
hexagon  randconfig-r036-20230912   clang
i386 allmodconfig   gcc  
i386  allnoconfig   gcc  
i386 allyesconfig   gcc  
i386 buildonly-randconfig-001-20230913   gcc  
i386 buildonly-randconfig-002-20230913   gcc  
i386 buildonly-randconfig-003-20230913   gcc  
i386 buildonly-randconfig-004-20230913   gcc  
i386 buildonly-randconfig-005-20230913   gcc  
i386 buildonly-randconfig-006-20230913   gcc  
i386  debian-10.3   gcc  
i386defconfig   gcc  
i386  randconfig-001-20230913   gcc  
i386  randconfig-002-20230913   gcc  
i386  randconfig-003-20230913   gcc  
i386  randconfig-004-20230913   gcc  
i386  randconfig-005-20230913   gcc  
i386  randconfig-006-20230913   gcc  
i386  randconfig-011-20230913   clang
i386  randconfig-012-20230913   clang
i386  randconfig-013-20230913   clang
i386  randconfig-014-20230913   clang
i386  randconfig-015-20230913   clang
i386  randconfig-016-20230913   clang
i386 randconfig-r004-20230913   gcc  
i386 randconfig-r006-20230913   gcc  
i386 randconfig-r031-20230912   clang
loongarchallmodconfig   gcc  
loongarch allnoconfig   gcc  
loongarchallyesconfig   gcc  
loongarch   defconfig   gcc  
loongarch randconfig-001-20230912   gcc  
loongarch randconfig-001-20230913   gcc  
loongarchrandconfig-r002

Re: [PATCH] ASoC: imx-rpmsg: Set ignore_pmdown_time for dai_link

2023-09-12 Thread Shengjiu Wang

On Tue, Sep 12, 2023 at 2:34 PM Chancel Liu  wrote:
>
> i.MX rpmsg sound cards work on codec slave mode. MCLK will be disabled
> by CPU DAI driver in hw_free(). Some codec requires MCLK present at
> power up/down sequence. So need to set ignore_pmdown_time to power down
> codec immediately before MCLK is turned off.
>
> Take WM8962 as an example, if MCLK is disabled before DAPM power down
> playback stream, FIFO error will arise in WM8962 which will have bad
> impact on playback next.
>
> Signed-off-by: Chancel Liu 
> ---
>  sound/soc/fsl/imx-rpmsg.c | 7 +++
>  1 file changed, 7 insertions(+)
>
> diff --git a/sound/soc/fsl/imx-rpmsg.c b/sound/soc/fsl/imx-rpmsg.c
> index 3c7b95db2eac..d2ecd5e821b1 100644
> --- a/sound/soc/fsl/imx-rpmsg.c
> +++ b/sound/soc/fsl/imx-rpmsg.c
> @@ -89,6 +89,13 @@ static int imx_rpmsg_probe(struct platform_device *pdev)
> SND_SOC_DAIFMT_NB_NF |
> SND_SOC_DAIFMT_CBC_CFC;
>
> +   /* i.MX rpmsg sound cards work on codec slave mode. MCLK will be

Comments for multi line start from empty line with "/* "

Best regards
wang Shengjiu
> +* disabled by CPU DAI driver in hw_free(). Some codec requires MCLK
> +* present at power up/down sequence. So need to set 
> ignore_pmdown_time
> +* to power down codec immediately before MCLK is turned off.
> +*/
> +   data->dai.ignore_pmdown_time = 1;
> +
> /* Optional codec node */
> ret = of_parse_phandle_with_fixed_args(np, "audio-codec", 0, 0, 
> );
> if (ret) {
> --
> 2.25.1
>

[powerpc:topic/ppc-kvm 10/11] arch/powerpc/kvm/book3s_hv_nestedv2.c:465:29: error: variable 'amor' set but not used

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git 
topic/ppc-kvm
head:   5af8497e01ed97410b2f19ca8320a3bcdcfe267b
commit: da467d188ec7dd17770d813226cd92329e9b5b3b [10/11] KVM: PPC: Add support 
for nestedv2 guests
config: powerpc-ppc64_defconfig 
(https://download.01.org/0day-ci/archive/20230913/202309130935.bj7eusw4-...@intel.com/config)
compiler: powerpc64-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): 
(https://download.01.org/0day-ci/archive/20230913/202309130935.bj7eusw4-...@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot 
| Closes: 
https://lore.kernel.org/oe-kbuild-all/202309130935.bj7eusw4-...@intel.com/

All errors (new ones prefixed by >>):

   arch/powerpc/kvm/book3s_hv_nestedv2.c: In function 
'gs_msg_ops_vcpu_refresh_info':
>> arch/powerpc/kvm/book3s_hv_nestedv2.c:465:29: error: variable 'amor' set but 
>> not used [-Werror=unused-but-set-variable]
 465 | u64 amor;
 | ^~~~
   cc1: all warnings being treated as errors


vim +/amor +465 arch/powerpc/kvm/book3s_hv_nestedv2.c

   361  
   362  static int gs_msg_ops_vcpu_refresh_info(struct kvmppc_gs_msg *gsm,
   363  struct kvmppc_gs_buff *gsb)
   364  {
   365  struct kvmppc_gs_parser gsp = { 0 };
   366  struct kvmhv_nestedv2_io *io;
   367  struct kvmppc_gs_bitmap *valids;
   368  struct kvm_vcpu *vcpu;
   369  struct kvmppc_gs_elem *gse;
   370  vector128 v;
   371  int rc, i;
   372  u16 iden;
   373  
   374  vcpu = gsm->data;
   375  
   376  rc = kvmppc_gse_parse(, gsb);
   377  if (rc < 0)
   378  return rc;
   379  
   380  io = >arch.nestedv2_io;
   381  valids = >valids;
   382  
   383  kvmppc_gsp_for_each(, iden, gse)
   384  {
   385  switch (iden) {
   386  case KVMPPC_GSID_DSCR:
   387  vcpu->arch.dscr = kvmppc_gse_get_u64(gse);
   388  break;
   389  case KVMPPC_GSID_MMCRA:
   390  vcpu->arch.mmcra = kvmppc_gse_get_u64(gse);
   391  break;
   392  case KVMPPC_GSID_HFSCR:
   393  vcpu->arch.hfscr = kvmppc_gse_get_u64(gse);
   394  break;
   395  case KVMPPC_GSID_PURR:
   396  vcpu->arch.purr = kvmppc_gse_get_u64(gse);
   397  break;
   398  case KVMPPC_GSID_SPURR:
   399  vcpu->arch.spurr = kvmppc_gse_get_u64(gse);
   400  break;
   401  case KVMPPC_GSID_AMR:
   402  vcpu->arch.amr = kvmppc_gse_get_u64(gse);
   403  break;
   404  case KVMPPC_GSID_UAMOR:
   405  vcpu->arch.uamor = kvmppc_gse_get_u64(gse);
   406  break;
   407  case KVMPPC_GSID_SIAR:
   408  vcpu->arch.siar = kvmppc_gse_get_u64(gse);
   409  break;
   410  case KVMPPC_GSID_SDAR:
   411  vcpu->arch.sdar = kvmppc_gse_get_u64(gse);
   412  break;
   413  case KVMPPC_GSID_IAMR:
   414  vcpu->arch.iamr = kvmppc_gse_get_u64(gse);
   415  break;
   416  case KVMPPC_GSID_DAWR0:
   417  vcpu->arch.dawr0 = kvmppc_gse_get_u64(gse);
   418  break;
   419  case KVMPPC_GSID_DAWR1:
   420  vcpu->arch.dawr1 = kvmppc_gse_get_u64(gse);
   421  break;
   422  case KVMPPC_GSID_DAWRX0:
   423  vcpu->arch.dawrx0 = kvmppc_gse_get_u32(gse);
   424  break;
   425  case KVMPPC_GSID_DAWRX1:
   426  vcpu->arch.dawrx1 = kvmppc_gse_get_u32(gse);
   427  break;
   428  case KVMPPC_GSID_CIABR:
   429  vcpu->arch.ciabr = kvmppc_gse_get_u64(gse);
   430  break;
   431  case KVMPPC_GSID_WORT:
   432  vcpu->arch.wort = kvmppc_gse_get_u32(gse);
   433  break;
   434  case KVMPPC_GSID_PPR:
   435  vcpu->arch.ppr = kvmppc_gse_get_u64(gse);
   436  break;
   437  case KVMPPC_GSID_PSPB:
   438  vcpu->arch.pspb = kvmppc_gse_get_u32(gse);
   439  break;

Re: [PATCH bpf-next 5/6] bpf, arm32: Always zero extend for LDX with B/H/W

2023-09-12 Thread Alexei Starovoitov

On Tue, Sep 12, 2023 at 4:17 PM Puranjay Mohan  wrote:
>
> On Wed, Sep 13, 2023 at 1:04 AM Russell King (Oracle)
>  wrote:
> >
> > On Tue, Sep 12, 2023 at 10:46:53PM +, Puranjay Mohan wrote:
> > > The JITs should not depend on the verifier for zero extending the upper
> > > 32 bits of the destination register when loading a byte, half-word, or
> > > word.
> > >
> > > A following patch will make the verifier stop patching zext instructions
> > > after LDX.
> >
> > This was introduced by:
> >
> > 163541e6ba34 ("arm: bpf: eliminate zero extension code-gen")
> >
> > along with an additional function. So three points:
> >
> > 1) the commit should probably explain why it has now become undesirable
> > to access this verifier state, whereas it appears it was explicitly
> > added to permit this optimisation.
>
> I added some details in the cover letter.
>
> For the complete discussion see: [1]
>
> > 2) you state that jits should not depend on this state, but the above
> > commit adds more references than you're removing, so aren't there still
> > references to the verifier remaining after this patch? I count a total
> > of 10, and the patch below removes three.
>
> The JITs should not depend on this state for LDX (loading
> a B/H/W.
> This patch removes the usage only for LDX.
>
> > 3) what about the bpf_jit_needs_zext() function that was added to
> > support the export of this zext state?
>
> That is still applicable, The verifier will still emit zext
> instructions for other
> instructions like BPF_ALU / BPF_ALU64
>
> >
> > Essentially, the logic stated in the commit message doesn't seem to be
> > reflected by the proposed code change.
>
> I will try to provide more information.
> Currently I have asked Alexei if we really need this in [2].
> I still think this optimization is useful and we should keep it.

Right. subreg tracking is indeed functional for narrow loads.
Let's drop this patch set.

Re: [PATCH bpf-next 5/6] bpf, arm32: Always zero extend for LDX with B/H/W

On Wed, Sep 13, 2023 at 1:04 AM Russell King (Oracle)
 wrote:
>
> On Tue, Sep 12, 2023 at 10:46:53PM +, Puranjay Mohan wrote:
> > The JITs should not depend on the verifier for zero extending the upper
> > 32 bits of the destination register when loading a byte, half-word, or
> > word.
> >
> > A following patch will make the verifier stop patching zext instructions
> > after LDX.
>
> This was introduced by:
>
> 163541e6ba34 ("arm: bpf: eliminate zero extension code-gen")
>
> along with an additional function. So three points:
>
> 1) the commit should probably explain why it has now become undesirable
> to access this verifier state, whereas it appears it was explicitly
> added to permit this optimisation.

I added some details in the cover letter.

For the complete discussion see: [1]

> 2) you state that jits should not depend on this state, but the above
> commit adds more references than you're removing, so aren't there still
> references to the verifier remaining after this patch? I count a total
> of 10, and the patch below removes three.

The JITs should not depend on this state for LDX (loading
a B/H/W.
This patch removes the usage only for LDX.

> 3) what about the bpf_jit_needs_zext() function that was added to
> support the export of this zext state?

That is still applicable, The verifier will still emit zext
instructions for other
instructions like BPF_ALU / BPF_ALU64

>
> Essentially, the logic stated in the commit message doesn't seem to be
> reflected by the proposed code change.

I will try to provide more information.
Currently I have asked Alexei if we really need this in [2].
I still think this optimization is useful and we should keep it.

Thanks,
Puranjay

[1] 
https://lore.kernel.org/all/CANk7y0j2f-gPgZwd+YfTL71-6wfvky+f=kbc_ccqss0ehay...@mail.gmail.com/
[2] 
https://lore.kernel.org/bpf/CANk7y0hK9sQJ-kRx3nQpVJSxpP=NzzFaLitOYq8=pb6dvk9...@mail.gmail.com/

[powerpc:topic/ppc-kvm 8/11] arch/powerpc/kvm/guest-state-buffer.c:505: warning: expecting prototype for kvmppc_gsm_init(). Prototype was for kvmppc_gsm_new() instead

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git 
topic/ppc-kvm
head:   5af8497e01ed97410b2f19ca8320a3bcdcfe267b
commit: c531e958f40241e921456e7b77574a25f713a2e5 [8/11] KVM: PPC: Add helper 
library for Guest State Buffers
config: powerpc-ppc64_defconfig 
(https://download.01.org/0day-ci/archive/20230913/202309130700.eru2idwo-...@intel.com/config)
compiler: powerpc64-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): 
(https://download.01.org/0day-ci/archive/20230913/202309130700.eru2idwo-...@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot 
| Closes: 
https://lore.kernel.org/oe-kbuild-all/202309130700.eru2idwo-...@intel.com/

All warnings (new ones prefixed by >>):

>> arch/powerpc/kvm/guest-state-buffer.c:505: warning: expecting prototype for 
>> kvmppc_gsm_init(). Prototype was for kvmppc_gsm_new() instead
>> arch/powerpc/kvm/guest-state-buffer.c:565: warning: expecting prototype for 
>> kvmppc_gsm_fill_info(). Prototype was for kvmppc_gsm_refresh_info() instead


vim +505 arch/powerpc/kvm/guest-state-buffer.c

   493  
   494  /**
   495   * kvmppc_gsm_init() - creates a new guest state message
   496   * @ops: callbacks
   497   * @data: private data
   498   * @flags: guest wide or thread wide
   499   * @gfp_flags: GFP allocation flags
   500   *
   501   * Returns an initialized guest state message.
   502   */
   503  struct kvmppc_gs_msg *kvmppc_gsm_new(struct kvmppc_gs_msg_ops *ops, 
void *data,
   504   unsigned long flags, gfp_t 
gfp_flags)
 > 505  {
   506  struct kvmppc_gs_msg *gsm;
   507  
   508  gsm = kzalloc(sizeof(*gsm), gfp_flags);
   509  if (!gsm)
   510  return NULL;
   511  
   512  kvmppc_gsm_init(gsm, ops, data, flags);
   513  
   514  return gsm;
   515  }
   516  EXPORT_SYMBOL_GPL(kvmppc_gsm_new);
   517  
   518  /**
   519   * kvmppc_gsm_size() - creates a new guest state message
   520   * @gsm: self
   521   *
   522   * Returns the size required for the message.
   523   */
   524  size_t kvmppc_gsm_size(struct kvmppc_gs_msg *gsm)
   525  {
   526  if (gsm->ops->get_size)
   527  return gsm->ops->get_size(gsm);
   528  return 0;
   529  }
   530  EXPORT_SYMBOL_GPL(kvmppc_gsm_size);
   531  
   532  /**
   533   * kvmppc_gsm_free() - free guest state message
   534   * @gsm: guest state message
   535   *
   536   * Returns the size required for the message.
   537   */
   538  void kvmppc_gsm_free(struct kvmppc_gs_msg *gsm)
   539  {
   540  kfree(gsm);
   541  }
   542  EXPORT_SYMBOL_GPL(kvmppc_gsm_free);
   543  
   544  /**
   545   * kvmppc_gsm_fill_info() - serialises message to guest state buffer 
format
   546   * @gsm: self
   547   * @gsb: buffer to serialise into
   548   */
   549  int kvmppc_gsm_fill_info(struct kvmppc_gs_msg *gsm, struct 
kvmppc_gs_buff *gsb)
   550  {
   551  if (!gsm->ops->fill_info)
   552  return -EINVAL;
   553  
   554  return gsm->ops->fill_info(gsb, gsm);
   555  }
   556  EXPORT_SYMBOL_GPL(kvmppc_gsm_fill_info);
   557  
   558  /**
   559   * kvmppc_gsm_fill_info() - deserialises from guest state buffer
   560   * @gsm: self
   561   * @gsb: buffer to serialise from
   562   */
   563  int kvmppc_gsm_refresh_info(struct kvmppc_gs_msg *gsm,
   564  struct kvmppc_gs_buff *gsb)
 > 565  {

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH bpf-next 5/6] bpf, arm32: Always zero extend for LDX with B/H/W

2023-09-12 Thread Russell King (Oracle)

On Tue, Sep 12, 2023 at 10:46:53PM +, Puranjay Mohan wrote:
> The JITs should not depend on the verifier for zero extending the upper
> 32 bits of the destination register when loading a byte, half-word, or
> word.
> 
> A following patch will make the verifier stop patching zext instructions
> after LDX.

This was introduced by:

163541e6ba34 ("arm: bpf: eliminate zero extension code-gen")

along with an additional function. So three points:

1) the commit should probably explain why it has now become undesirable
to access this verifier state, whereas it appears it was explicitly
added to permit this optimisation.
2) you state that jits should not depend on this state, but the above
commit adds more references than you're removing, so aren't there still
references to the verifier remaining after this patch? I count a total
of 10, and the patch below removes three.
3) what about the bpf_jit_needs_zext() function that was added to
support the export of this zext state?

Essentially, the logic stated in the commit message doesn't seem to be
reflected by the proposed code change.

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Re: [RFC v3 1/2] powerpc/cpuidle: cpuidle wakeup latency based on IPI and timer events

2023-09-12 Thread Michael Ellerman

Aboorva Devarajan  writes:
> From: Pratik R. Sampat 
>
> Introduce a mechanism to fire directed IPIs from a source CPU to a
> specified target CPU and measure the time incurred on waking up the
> target CPU in response.
>
> Also, introduce a mechanism to queue a hrtimer on a specified CPU and
> subsequently measure the time taken to wakeup the CPU.
>
> Define a simple debugfs interface that allows for adjusting the
> settings to trigger IPI and timer events on a designated CPU, and to
> observe the resulting cpuidle wakeup latencies.
>
> Reviewed-by: Srikar Dronamraju 
> Signed-off-by: Pratik R. Sampat 
> Signed-off-by: Aboorva Devarajan 
> ---
>  arch/powerpc/Kconfig.debug |  10 ++
>  arch/powerpc/kernel/Makefile   |   1 +
>  arch/powerpc/kernel/test_cpuidle_latency.c | 154 +
  
I don't see anything here that's powerpc specific?

Which makes me wonder 1) could this be done with some existing generic
mechanism?, and 2) if not can this test code be made generic.

At the very least this should be Cc'ed to the cpuidle lists &
maintainers given it's a test for cpuidle latency :)

cheers

[PATCH bpf-next 5/6] bpf, arm32: Always zero extend for LDX with B/H/W

The JITs should not depend on the verifier for zero extending the upper
32 bits of the destination register when loading a byte, half-word, or
word.

A following patch will make the verifier stop patching zext instructions
after LDX.

Signed-off-by: Puranjay Mohan 
---
 arch/arm/net/bpf_jit_32.c | 9 +++--
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
index 6a1c9fca5260..757a99febba5 100644
--- a/arch/arm/net/bpf_jit_32.c
+++ b/arch/arm/net/bpf_jit_32.c
@@ -1081,20 +1081,17 @@ static inline void emit_ldx_r(const s8 dst[], const s8 
src,
case BPF_B:
/* Load a Byte */
emit(ARM_LDRB_I(rd[1], rm, off), ctx);
-   if (!ctx->prog->aux->verifier_zext)
-   emit_a32_mov_i(rd[0], 0, ctx);
+   emit_a32_mov_i(rd[0], 0, ctx);
break;
case BPF_H:
/* Load a HalfWord */
emit(ARM_LDRH_I(rd[1], rm, off), ctx);
-   if (!ctx->prog->aux->verifier_zext)
-   emit_a32_mov_i(rd[0], 0, ctx);
+   emit_a32_mov_i(rd[0], 0, ctx);
break;
case BPF_W:
/* Load a Word */
emit(ARM_LDR_I(rd[1], rm, off), ctx);
-   if (!ctx->prog->aux->verifier_zext)
-   emit_a32_mov_i(rd[0], 0, ctx);
+   emit_a32_mov_i(rd[0], 0, ctx);
break;
case BPF_DW:
/* Load a Double Word */
-- 
2.39.2

[PATCH bpf-next 6/6] bpf, verifier: always mark destination of LDX as 64-bit

All 64-bit JITs utilize a single instruction to load + zero-extend a
byte, word, or a half-word. The optimisation of emitting zext for LDX is
not useful for most of the JITs.

All the JITs that relied on the verifier for zero extension of LDX
desitination registers have been modified to always zero extend the
destination.

Now the verifier can safely mark LDX destination as 64-bit and stop
emitting zero-extension instructions for it.

Signed-off-by: Puranjay Mohan 
---
 kernel/bpf/verifier.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c
index dbba2b806017..02a1ac1a1327 100644
--- a/kernel/bpf/verifier.c
+++ b/kernel/bpf/verifier.c
@@ -3028,9 +3028,7 @@ static bool is_reg64(struct bpf_verifier_env *env, struct 
bpf_insn *insn,
return false;
 
if (class == BPF_LDX) {
-   if (t != SRC_OP)
-   return BPF_SIZE(code) == BPF_DW;
-   /* LDX source must be ptr. */
+   /* LDX source must be a ptr. and LDX destination is always 
zero-extended. */
return true;
}
 
-- 
2.39.2

[PATCH bpf-next 4/6] bpf, powerpc32: Always zero extend for LDX

The JITs should not depend on the verifier for zero extending the upper
32 bits of the destination register when loading a byte, half-word, or
word.

A following patch will make the verifier stop patching zext instructions
after LDX.

Signed-off-by: Puranjay Mohan 
---
 arch/powerpc/net/bpf_jit_comp32.c | 25 -
 1 file changed, 8 insertions(+), 17 deletions(-)

diff --git a/arch/powerpc/net/bpf_jit_comp32.c 
b/arch/powerpc/net/bpf_jit_comp32.c
index 7f91ea064c08..0a952a2cfaac 100644
--- a/arch/powerpc/net/bpf_jit_comp32.c
+++ b/arch/powerpc/net/bpf_jit_comp32.c
@@ -936,14 +936,13 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, 
struct codegen_context *
PPC_BCC_SHORT(COND_GT, (ctx->idx + 4) * 4);
EMIT(PPC_RAW_LI(dst_reg, 0));
/*
-* For BPF_DW case, "li reg_h,0" would be 
needed when
-* !fp->aux->verifier_zext. Emit NOP otherwise.
+* For BPF_DW case, "li reg_h,0" would be 
needed emit NOP otherwise.
 *
 * Note that "li reg_h,0" is emitted for 
BPF_B/H/W case,
 * if necessary. So, jump there insted of 
emitting an
 * additional "li reg_h,0" instruction.
 */
-   if (size == BPF_DW && !fp->aux->verifier_zext)
+   if (size == BPF_DW)
EMIT(PPC_RAW_LI(dst_reg_h, 0));
else
EMIT(PPC_RAW_NOP());
@@ -974,7 +973,7 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, 
struct codegen_context *
break;
}
 
-   if (size != BPF_DW && !fp->aux->verifier_zext)
+   if (size != BPF_DW)
EMIT(PPC_RAW_LI(dst_reg_h, 0));
 
if (BPF_MODE(code) == BPF_PROBE_MEM) {
@@ -982,20 +981,12 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, 
struct codegen_context *
int jmp_off = 4;
 
/*
-* In case of BPF_DW, two lwz instructions are 
emitted, one
-* for higher 32-bit and another for lower 
32-bit. So, set
-* ex->insn to the first of the two and jump 
over both
-* instructions in fixup.
-*
-* Similarly, with !verifier_zext, two 
instructions are
-* emitted for BPF_B/H/W case. So, set ex->insn 
to the
-* instruction that could fault and skip over 
both
-* instructions.
+* Two instructions are emitted for LDX.
+* So, set ex->insn to the instruction that 
could fault and skip
+* over both instructions.
 */
-   if (size == BPF_DW || !fp->aux->verifier_zext) {
-   insn_idx -= 1;
-   jmp_off += 4;
-   }
+   insn_idx -= 1;
+   jmp_off += 4;
 
ret = bpf_add_extable_entry(fp, image, pass, 
ctx, insn_idx,
jmp_off, dst_reg);
-- 
2.39.2

[PATCH bpf-next 3/6] bpf, parisc32: Always zero extend for LDX with B/W/H

The JITs should not depend on the verifier for zero extending the upper
32 bits of the destination register when loading a byte, half-word, or
word.

A following patch will make the verifier stop patching zext instructions
after LDX.

Signed-off-by: Puranjay Mohan 
---
 arch/parisc/net/bpf_jit_comp32.c | 9 +++--
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/parisc/net/bpf_jit_comp32.c b/arch/parisc/net/bpf_jit_comp32.c
index 5ff0cf925fe9..cc3972d6c971 100644
--- a/arch/parisc/net/bpf_jit_comp32.c
+++ b/arch/parisc/net/bpf_jit_comp32.c
@@ -1026,18 +1026,15 @@ static int emit_load_r64(const s8 *dst, const s8 *src, 
s16 off,
switch (size) {
case BPF_B:
emit(hppa_ldb(off + 0, srcreg, lo(rd)), ctx);
-   if (!ctx->prog->aux->verifier_zext)
-   emit_hppa_copy(HPPA_REG_ZERO, hi(rd), ctx);
+   emit_hppa_copy(HPPA_REG_ZERO, hi(rd), ctx);
break;
case BPF_H:
emit(hppa_ldh(off + 0, srcreg, lo(rd)), ctx);
-   if (!ctx->prog->aux->verifier_zext)
-   emit_hppa_copy(HPPA_REG_ZERO, hi(rd), ctx);
+   emit_hppa_copy(HPPA_REG_ZERO, hi(rd), ctx);
break;
case BPF_W:
emit(hppa_ldw(off + 0, srcreg, lo(rd)), ctx);
-   if (!ctx->prog->aux->verifier_zext)
-   emit_hppa_copy(HPPA_REG_ZERO, hi(rd), ctx);
+   emit_hppa_copy(HPPA_REG_ZERO, hi(rd), ctx);
break;
case BPF_DW:
emit(hppa_ldw(off + 0, srcreg, hi(rd)), ctx);
-- 
2.39.2

[PATCH bpf-next 0/6] bpf: verifier: stop emitting zext for LDX

All 64-bit architectures that support the BPF JIT do LDX + zero extension
with a single CPU instruction. Some 64-bit architectures like riscv64,
s390, mips64, etc. have bpf_jit_needs_zext() -> true. This means although
these architectures do LDX + zero extension with a single CPU instruction,
the verifier emits extra zero extension instructions after LDX | B/H/W.

After a discussion about this in [1], it was decided that the verifier
should not emit zext instructions for LDX and all JITs that can't do a LDX
+ zero extension with a single instruction should emit two instructions by
default for LDX.

All 32 bit JITs checked for ctx->prog->aux->verifier_zext and did not do
explicit zero extension after LDX if this is set by the verifier.

This patch series changes all applicable 32-bit JITs to always do a zero
extension after LDX without checking ctx->prog->aux->verifier_zext.

The last patch modifies the verifier to always mark the destination of LDX
as 64 bit which in turn stops the verifier from emitting zext after LDX.

These changes have not been tested because I don't have the hardware to do
so, I would request the JIT maintainers to help me test this. Especially,
the powerpc32 JTI where amount of code change is more.

[1]
https://lore.kernel.org/all/CANk7y0j2f-gPgZwd+YfTL71-6wfvky+f=kbc_ccqss0ehay...@mail.gmail.com/

Puranjay Mohan (6):
bpf, riscv32: Always zero extend for LDX with B/W/H
bpf, x86-32: Always zero extend for LDX with B/W/H
bpf, parisc32: Always zero extend for LDX with B/W/H
bpf, powerpc32: Always zero extend for LDX
bpf, arm32: Always zero extend for LDX with B/H/W
bpf, verifier: always mark destination of LDX as 64-bit

--
2.39.2

[PATCH bpf-next 1/6] bpf, riscv32: Always zero extend for LDX with B/W/H

The JITs should not depend on the verifier for zero extending the upper
32 bits of the destination register when loading a byte, half-word, or
word.

A following patch will make the verifier stop patching zext instructions
after LDX.

Signed-off-by: Puranjay Mohan 
---
 arch/riscv/net/bpf_jit_comp32.c | 9 +++--
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/riscv/net/bpf_jit_comp32.c b/arch/riscv/net/bpf_jit_comp32.c
index 529a83b85c1c..8f8255519ba1 100644
--- a/arch/riscv/net/bpf_jit_comp32.c
+++ b/arch/riscv/net/bpf_jit_comp32.c
@@ -847,18 +847,15 @@ static int emit_load_r64(const s8 *dst, const s8 *src, 
s16 off,
switch (size) {
case BPF_B:
emit(rv_lbu(lo(rd), 0, RV_REG_T0), ctx);
-   if (!ctx->prog->aux->verifier_zext)
-   emit(rv_addi(hi(rd), RV_REG_ZERO, 0), ctx);
+   emit(rv_addi(hi(rd), RV_REG_ZERO, 0), ctx);
break;
case BPF_H:
emit(rv_lhu(lo(rd), 0, RV_REG_T0), ctx);
-   if (!ctx->prog->aux->verifier_zext)
-   emit(rv_addi(hi(rd), RV_REG_ZERO, 0), ctx);
+   emit(rv_addi(hi(rd), RV_REG_ZERO, 0), ctx);
break;
case BPF_W:
emit(rv_lw(lo(rd), 0, RV_REG_T0), ctx);
-   if (!ctx->prog->aux->verifier_zext)
-   emit(rv_addi(hi(rd), RV_REG_ZERO, 0), ctx);
+   emit(rv_addi(hi(rd), RV_REG_ZERO, 0), ctx);
break;
case BPF_DW:
emit(rv_lw(lo(rd), 0, RV_REG_T0), ctx);
-- 
2.39.2

[PATCH bpf-next 2/6] bpf, x86-32: Always zero extend for LDX with B/W/H

The JITs should not depend on the verifier for zero extending the upper
32 bits of the destination register when loading a byte, half-word, or
word.

A following patch will make the verifier stop patching zext instructions
after LDX.

Signed-off-by: Puranjay Mohan 
---
 arch/x86/net/bpf_jit_comp32.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/x86/net/bpf_jit_comp32.c b/arch/x86/net/bpf_jit_comp32.c
index 429a89c5468b..aef9183ff107 100644
--- a/arch/x86/net/bpf_jit_comp32.c
+++ b/arch/x86/net/bpf_jit_comp32.c
@@ -2050,8 +2050,6 @@ static int do_jit(struct bpf_prog *bpf_prog, int *addrs, 
u8 *image,
case BPF_B:
case BPF_H:
case BPF_W:
-   if (bpf_prog->aux->verifier_zext)
-   break;
if (dstk) {
EMIT3(0xC7, add_1reg(0x40, IA32_EBP),
  STACK_VAR(dst_hi));
-- 
2.39.2

[PATCH v2 3/3] doc: trusted-encrypted: add DCP as new trust source

Update the documentation for trusted and encrypted KEYS with DCP as new
trust source:

- Describe security properties of DCP trust source
- Describe key usage
- Document blob format

Co-developed-by: Richard Weinberger 
Signed-off-by: Richard Weinberger 
Co-developed-by: David Oberhollenzer 
Signed-off-by: David Oberhollenzer 
Signed-off-by: David Gstir 
---
 .../security/keys/trusted-encrypted.rst   | 85 +++
 1 file changed, 85 insertions(+)

diff --git a/Documentation/security/keys/trusted-encrypted.rst 
b/Documentation/security/keys/trusted-encrypted.rst
index 9bc9db8ec651..4452070afbe9 100644
--- a/Documentation/security/keys/trusted-encrypted.rst
+++ b/Documentation/security/keys/trusted-encrypted.rst
@@ -42,6 +42,14 @@ safe.
  randomly generated and fused into each SoC at manufacturing time.
  Otherwise, a common fixed test key is used instead.
 
+ (4) DCP (Data Co-Processor: crypto accelerator of various i.MX SoCs)
+
+ Rooted to a one-time programmable key (OTP) that is generally burnt
+ in the on-chip fuses and is accessible to the DCP encryption engine 
only.
+ DCP provides two keys that can be used as root of trust: the OTP key
+ and the UNIQUE key. Default is to use the UNIQUE key, but selecting
+ the OTP key can be done via a module parameter (dcp_use_otp_key).
+
   *  Execution isolation
 
  (1) TPM
@@ -57,6 +65,12 @@ safe.
 
  Fixed set of operations running in isolated execution environment.
 
+ (4) DCP
+
+ Fixed set of cryptographic operations running in isolated execution
+ environment. Only basic blob key encryption is executed there.
+ The actual key sealing/unsealing is done on main processor/kernel 
space.
+
   * Optional binding to platform integrity state
 
  (1) TPM
@@ -79,6 +93,11 @@ safe.
  Relies on the High Assurance Boot (HAB) mechanism of NXP SoCs
  for platform integrity.
 
+ (4) DCP
+
+ Relies on Secure/Trusted boot process (called HAB by vendor) for
+ platform integrity.
+
   *  Interfaces and APIs
 
  (1) TPM
@@ -94,6 +113,11 @@ safe.
 
  Interface is specific to silicon vendor.
 
+ (4) DCP
+
+ Vendor-specific API that is implemented as part of the DCP crypto 
driver in
+ ``drivers/crypto/mxs-dcp.c``.
+
   *  Threat model
 
  The strength and appropriateness of a particular trust source for a given
@@ -129,6 +153,13 @@ selected trust source:
  CAAM HWRNG, enable CRYPTO_DEV_FSL_CAAM_RNG_API and ensure the device
  is probed.
 
+  *  DCP (Data Co-Processor: crypto accelerator of various i.MX SoCs)
+
+ The DCP hardware device itself does not provide a dedicated RNG interface,
+ so the kernel default RNG is used. SoCs with DCP like the i.MX6ULL do have
+ a dedicated hardware RNG that is independent from DCP which can be enabled
+ to back the kernel RNG.
+
 Users may override this by specifying ``trusted.rng=kernel`` on the kernel
 command-line to override the used RNG with the kernel's random number pool.
 
@@ -231,6 +262,19 @@ Usage::
 CAAM-specific format.  The key length for new keys is always in bytes.
 Trusted Keys can be 32 - 128 bytes (256 - 1024 bits).
 
+Trusted Keys usage: DCP
+---
+
+Usage::
+
+keyctl add trusted name "new keylen" ring
+keyctl add trusted name "load hex_blob" ring
+keyctl print keyid
+
+"keyctl print" returns an ASCII hex copy of the sealed key, which is in format
+specific to this DCP key-blob implementation.  The key length for new keys is
+always in bytes. Trusted Keys can be 32 - 128 bytes (256 - 1024 bits).
+
 Encrypted Keys usage
 
 
@@ -426,3 +470,44 @@ string length.
 privkey is the binary representation of TPM2B_PUBLIC excluding the
 initial TPM2B header which can be reconstructed from the ASN.1 octed
 string length.
+
+DCP Blob Format
+---
+
+The Data Co-Processor (DCP) provides hardware-bound AES keys using its
+AES encryption engine only. It does not provide direct key sealing/unsealing.
+To make DCP hardware encryption keys usable as trust source, we define
+our own custom format that uses a hardware-bound key to secure the sealing
+key stored in the key blob.
+
+Whenever a new trusted key using DCP is generated, we generate a random 128-bit
+blob encryption key (BEK) and 128-bit nonce. The BEK and nonce are used to
+encrypt the trusted key payload using AES-128-GCM.
+
+The BEK itself is encrypted using the hardware-bound key using the DCP's AES
+encryption engine with AES-128-ECB. The encrypted BEK, generated nonce,
+BEK-encrypted payload and authentication tag make up the blob format together
+with a version number, payload length and authentication tag::
+
+/*
+ * struct dcp_blob_fmt - DCP BLOB format.
+ *
+ * @fmt_version: Format version, currently being %1
+ * @blob_key: Random AES 128 key which is used to encrypt @payload,
+ *

[PATCH v2 2/3] KEYS: trusted: Introduce support for NXP DCP-based trusted keys

DCP (Data Co-Processor) is the little brother of NXP's CAAM IP.

Beside of accelerated crypto operations, it also offers support for
hardware-bound keys. Using this feature it is possible to implement a blob
mechanism just like CAAM offers. Unlike on CAAM, constructing and
parsing the blob has to happen in software.

We chose the following format for the blob:
/*
 * struct dcp_blob_fmt - DCP BLOB format.
 *
 * @fmt_version: Format version, currently being %1
 * @blob_key: Random AES 128 key which is used to encrypt @payload,
 *@blob_key itself is encrypted with OTP or UNIQUE device key in
 *AES-128-ECB mode by DCP.
 * @nonce: Random nonce used for @payload encryption.
 * @payload_len: Length of the plain text @payload.
 * @payload: The payload itself, encrypted using AES-128-GCM and @blob_key,
 *   GCM auth tag of size AES_BLOCK_SIZE is attached at the end of it.
 *
 * The total size of a DCP BLOB is sizeof(struct dcp_blob_fmt) + @payload_len +
 * AES_BLOCK_SIZE.
 */
struct dcp_blob_fmt {
__u8 fmt_version;
__u8 blob_key[AES_KEYSIZE_128];
__u8 nonce[AES_KEYSIZE_128];
__le32 payload_len;
__u8 payload[];
} __packed;

@payload is the key provided by trusted_key_ops->seal().

By default the UNIQUE device key is used, it is also possible to use
the OTP key. While the UNIQUE device key should be unique it is not
entirely clear whether this is the case due to unclear documentation.
If someone wants to be sure they can burn their own unique key
into the OTP fuse and set the use_otp_key module parameter.

Co-developed-by: Richard Weinberger 
Signed-off-by: Richard Weinberger 
Co-developed-by: David Oberhollenzer 
Signed-off-by: David Oberhollenzer 
Signed-off-by: David Gstir 
---
 .../admin-guide/kernel-parameters.txt |  13 +
 MAINTAINERS   |   9 +
 include/keys/trusted_dcp.h|  13 +
 security/keys/trusted-keys/Kconfig|   9 +-
 security/keys/trusted-keys/Makefile   |   2 +
 security/keys/trusted-keys/trusted_core.c |   6 +-
 security/keys/trusted-keys/trusted_dcp.c  | 313 ++
 7 files changed, 363 insertions(+), 2 deletions(-)
 create mode 100644 include/keys/trusted_dcp.h
 create mode 100644 security/keys/trusted-keys/trusted_dcp.c

diff --git a/Documentation/admin-guide/kernel-parameters.txt 
b/Documentation/admin-guide/kernel-parameters.txt
index 0a1731a0f0ef..c11eda8b38e0 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -6566,6 +6566,7 @@
- "tpm"
- "tee"
- "caam"
+   - "dcp"
If not specified then it defaults to iterating through
the trust source list starting with TPM and assigns the
first trust source as a backend which is initialized
@@ -6581,6 +6582,18 @@
If not specified, "default" is used. In this case,
the RNG's choice is left to each individual trust 
source.
 
+   trusted.dcp_use_otp_key
+   This is intended to be used in combination with
+   trusted.source=dcp and will select the DCP OTP key
+   instead of the DCP UNIQUE key blob encryption.
+
+   trusted.dcp_skip_zk_test
+   This is intended to be used in combination with
+   trusted.source=dcp and will disable the check if all
+   the blob key is zero'ed. This is helpful for situations 
where
+   having this key zero'ed is acceptable. E.g. in testing
+   scenarios.
+
tsc=Disable clocksource stability checks for TSC.
Format: 
[x86] reliable: mark tsc clocksource as reliable, this
diff --git a/MAINTAINERS b/MAINTAINERS
index 90f13281d297..988d01226131 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11647,6 +11647,15 @@ S: Maintained
 F: include/keys/trusted_caam.h
 F: security/keys/trusted-keys/trusted_caam.c
 
+KEYS-TRUSTED-DCP
+M: David Gstir 
+R: sigma star Kernel Team 
+L: linux-integr...@vger.kernel.org
+L: keyri...@vger.kernel.org
+S: Supported
+F: include/keys/trusted_dcp.h
+F: security/keys/trusted-keys/trusted_dcp.c
+
 KEYS-TRUSTED-TEE
 M: Sumit Garg 
 L: linux-integr...@vger.kernel.org
diff --git a/include/keys/trusted_dcp.h b/include/keys/trusted_dcp.h
new file mode 100644
index ..7b2a1275c527
--- /dev/null
+++ b/include/keys/trusted_dcp.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2021 sigma star gmbh
+ * Authors: David Gstir 
+ *  Richard Weinberger 
+ */
+
+#ifndef TRUSTED_DCP_H
+#define TRUSTED_DCP_H
+
+extern struct trusted_key_ops dcp_trusted_key_ops;

[PATCH v2 1/3] crypto: mxs-dcp: Add support for hardware provided keys

DCP is capable to performing AES with hardware-bound keys.
These keys are not stored in main memory and are therefore not directly
accessible by the operating system.

So instead of feeding the key into DCP, we need to place a
reference to such a key before initiating the crypto operation.
Keys are referenced by a one byte identifiers.

DCP supports 6 different keys: 4 slots in the secure memory area,
a one time programmable key which can be burnt via on-chip fuses
and an unique device key.

Using these keys is restricted to in-kernel users that use them as building
block for other crypto tools such as trusted keys. Allowing userspace
(e.g. via AF_ALG) to use these keys to crypt or decrypt data is a security
risk, because there is no access control mechanism.

Co-developed-by: Richard Weinberger 
Signed-off-by: Richard Weinberger 
Co-developed-by: David Oberhollenzer 
Signed-off-by: David Oberhollenzer 
Signed-off-by: David Gstir 
---
 drivers/crypto/mxs-dcp.c | 107 +++
 include/soc/fsl/dcp.h|  19 +++
 2 files changed, 115 insertions(+), 11 deletions(-)
 create mode 100644 include/soc/fsl/dcp.h

diff --git a/drivers/crypto/mxs-dcp.c b/drivers/crypto/mxs-dcp.c
index f6b7bce0e656..d525cb41f2ca 100644
--- a/drivers/crypto/mxs-dcp.c
+++ b/drivers/crypto/mxs-dcp.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -101,6 +102,7 @@ struct dcp_async_ctx {
struct crypto_skcipher  *fallback;
unsigned intkey_len;
uint8_t key[AES_KEYSIZE_128];
+   boolrefkey;
 };
 
 struct dcp_aes_req_ctx {
@@ -155,6 +157,7 @@ static struct dcp *global_sdcp;
 #define MXS_DCP_CONTROL0_HASH_TERM (1 << 13)
 #define MXS_DCP_CONTROL0_HASH_INIT (1 << 12)
 #define MXS_DCP_CONTROL0_PAYLOAD_KEY   (1 << 11)
+#define MXS_DCP_CONTROL0_OTP_KEY   (1 << 10)
 #define MXS_DCP_CONTROL0_CIPHER_ENCRYPT(1 << 8)
 #define MXS_DCP_CONTROL0_CIPHER_INIT   (1 << 9)
 #define MXS_DCP_CONTROL0_ENABLE_HASH   (1 << 6)
@@ -168,6 +171,8 @@ static struct dcp *global_sdcp;
 #define MXS_DCP_CONTROL1_CIPHER_MODE_ECB   (0 << 4)
 #define MXS_DCP_CONTROL1_CIPHER_SELECT_AES128  (0 << 0)
 
+#define MXS_DCP_CONTROL1_KEY_SELECT_SHIFT  8
+
 static int mxs_dcp_start_dma(struct dcp_async_ctx *actx)
 {
int dma_err;
@@ -224,13 +229,16 @@ static int mxs_dcp_run_aes(struct dcp_async_ctx *actx,
struct dcp *sdcp = global_sdcp;
struct dcp_dma_desc *desc = >coh->desc[actx->chan];
struct dcp_aes_req_ctx *rctx = skcipher_request_ctx(req);
+   bool key_referenced = actx->refkey;
int ret;
 
-   key_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_key,
- 2 * AES_KEYSIZE_128, DMA_TO_DEVICE);
-   ret = dma_mapping_error(sdcp->dev, key_phys);
-   if (ret)
-   return ret;
+   if (!key_referenced) {
+   key_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_key,
+ 2 * AES_KEYSIZE_128, DMA_TO_DEVICE);
+   ret = dma_mapping_error(sdcp->dev, key_phys);
+   if (ret)
+   return ret;
+   }
 
src_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_in_buf,
  DCP_BUF_SZ, DMA_TO_DEVICE);
@@ -255,8 +263,13 @@ static int mxs_dcp_run_aes(struct dcp_async_ctx *actx,
MXS_DCP_CONTROL0_INTERRUPT |
MXS_DCP_CONTROL0_ENABLE_CIPHER;
 
-   /* Payload contains the key. */
-   desc->control0 |= MXS_DCP_CONTROL0_PAYLOAD_KEY;
+   if (key_referenced) {
+   /* Set OTP key bit to select the key via KEY_SELECT. */
+   desc->control0 |= MXS_DCP_CONTROL0_OTP_KEY;
+   } else {
+   /* Payload contains the key. */
+   desc->control0 |= MXS_DCP_CONTROL0_PAYLOAD_KEY;
+   }
 
if (rctx->enc)
desc->control0 |= MXS_DCP_CONTROL0_CIPHER_ENCRYPT;
@@ -270,6 +283,9 @@ static int mxs_dcp_run_aes(struct dcp_async_ctx *actx,
else
desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_CBC;
 
+   if (key_referenced)
+   desc->control1 |= sdcp->coh->aes_key[0] << 
MXS_DCP_CONTROL1_KEY_SELECT_SHIFT;
+
desc->next_cmd_addr = 0;
desc->source = src_phys;
desc->destination = dst_phys;
@@ -284,9 +300,10 @@ static int mxs_dcp_run_aes(struct dcp_async_ctx *actx,
 err_dst:
dma_unmap_single(sdcp->dev, src_phys, DCP_BUF_SZ, DMA_TO_DEVICE);
 err_src:
-   dma_unmap_single(sdcp->dev, key_phys, 2 * AES_KEYSIZE_128,
-DMA_TO_DEVICE);
-
+   if (!key_referenced) {
+   dma_unmap_single(sdcp->dev, key_phys, 2 * AES_KEYSIZE_128,
+DMA_TO_DEVICE);
+   }
return ret;
 }
 
@@ -453,7 +470,7 @@

[PATCH v2 0/3] DCP as trusted keys backend

This is a revival of the previous patch set submitted by Richard Weinberger:
https://lore.kernel.org/linux-integrity/20210614201620.30451-1-rich...@nod.at/

v1 -> v2:
- Revive and rebase to latest version
- Include review comments from Ahmad Fatoum

The Data CoProcessor (DCP) is an IP core built into many NXP SoCs such
as i.mx6ull.

Similar to the CAAM engine used in more powerful SoCs, DCP can AES-
encrypt/decrypt user data using a unique, never-disclosed,
device-specific key. Unlike CAAM though, it cannot directly wrap and
unwrap blobs in hardware. As DCP offers only the bare minimum feature
set and a blob mechanism needs aid from software. A blob in this case
is a piece of sensitive data (e.g. a key) that is encrypted and
authenticated using the device-specific key so that unwrapping can only
be done on the hardware where the blob was wrapped.

This patch series adds a DCP based, trusted-key backend and is similar
in spirit to the one by Ahmad Fatoum [0] that does the same for CAAM.
It is of interest for similar use cases as the CAAM patch set, but for
lower end devices, where CAAM is not available.

Because constructing and parsing the blob has to happen in software,
we needed to decide on a blob format and chose the following:

struct dcp_blob_fmt {
__u8 fmt_version;
__u8 blob_key[AES_KEYSIZE_128];
__u8 nonce[AES_KEYSIZE_128];
__le32 payload_len;
__u8 payload[];
} __packed;

The `fmt_version` is currently 1.

The encrypted key is stored in the payload area. It is AES-128-GCM
encrypted using `blob_key` and `nonce`, GCM auth tag is attached at
the end of the payload (`payload_len` does not include the size of
the auth tag).

The `blob_key` itself is encrypted in AES-128-ECB mode by DCP using
the OTP or UNIQUE device key. A new `blob_key` and `nonce` are generated
randomly, when sealing/exporting the DCP blob.

This patchset was tested with dm-crypt on an i.MX6ULL board.

[0] 
https://lore.kernel.org/keyrings/20220513145705.2080323-1-a.fat...@pengutronix.de/

David Gstir (3):
  crypto: mxs-dcp: Add support for hardware provided keys
  KEYS: trusted: Introduce support for NXP DCP-based trusted keys
  doc: trusted-encrypted: add DCP as new trust source

 .../admin-guide/kernel-parameters.txt |  13 +
 .../security/keys/trusted-encrypted.rst   |  85 +
 MAINTAINERS   |   9 +
 drivers/crypto/mxs-dcp.c  | 107 +-
 include/keys/trusted_dcp.h|  13 +
 include/soc/fsl/dcp.h |  19 ++
 security/keys/trusted-keys/Kconfig|   9 +-
 security/keys/trusted-keys/Makefile   |   2 +
 security/keys/trusted-keys/trusted_core.c |   6 +-
 security/keys/trusted-keys/trusted_dcp.c  | 313 ++
 10 files changed, 563 insertions(+), 13 deletions(-)
 create mode 100644 include/keys/trusted_dcp.h
 create mode 100644 include/soc/fsl/dcp.h
 create mode 100644 security/keys/trusted-keys/trusted_dcp.c

-- 
2.35.3

Re: [PATCH 2/2] arch: Reserve map_shadow_stack() syscall number for all architectures

2023-09-12 Thread Edgecombe, Rick P

On Mon, 2023-09-11 at 18:02 +, Sohil Mehta wrote:
> diff --git a/arch/powerpc/kernel/syscalls/syscall.tbl
> b/arch/powerpc/kernel/syscalls/syscall.tbl
> index 20e50586e8a2..2767b8a42636 100644
> --- a/arch/powerpc/kernel/syscalls/syscall.tbl
> +++ b/arch/powerpc/kernel/syscalls/syscall.tbl
> @@ -539,3 +539,4 @@
>  450nospu   set_mempolicy_home_node sys_set_mempolicy_hom
> e_node
>  451common  cachestat   sys_cachestat
>  452common  fchmodat2   sys_fchmodat2
> +453common  map_shadow_stacksys_map_shadow_stack

I noticed in powerpc, the not implemented syscalls are manually mapped
to sys_ni_syscall. It also has some special extra sys_ni_syscall()
implementation bits to handle both ARCH_HAS_SYSCALL_WRAPPER and
!ARCH_HAS_SYSCALL_WRAPPER. So wondering if it might need special
treatment. Did you see those parts?

[PATCH 2/2] arch: Reserve map_shadow_stack() syscall number for all architectures

2023-09-12 Thread Sohil Mehta

Support for map_shadow_stack() was recently added but it is an x86
only system call for now. There is a possibility that other
architectures (namely, arm64 and Risc-V) that are implementing support
for shadow stacks, might need to add support for it.

Independent of that, reserving arch-specific syscall numbers in the
syscall tables of all architectures is good practice and would help
avoid future conflicts.

Note, map_shadow_stack() was assigned #453 since #452 was taken by
fchmodat2().

Link:https://lore.kernel.org/lkml/20230830234752.19858-1-dave.han...@linux.intel.com/

Signed-off-by: Sohil Mehta 
---
 arch/alpha/kernel/syscalls/syscall.tbl  | 1 +
 arch/arm/tools/syscall.tbl  | 1 +
 arch/arm64/include/asm/unistd.h | 2 +-
 arch/arm64/include/asm/unistd32.h   | 2 ++
 arch/ia64/kernel/syscalls/syscall.tbl   | 1 +
 arch/m68k/kernel/syscalls/syscall.tbl   | 1 +
 arch/microblaze/kernel/syscalls/syscall.tbl | 1 +
 arch/mips/kernel/syscalls/syscall_n32.tbl   | 1 +
 arch/mips/kernel/syscalls/syscall_n64.tbl   | 1 +
 arch/mips/kernel/syscalls/syscall_o32.tbl   | 1 +
 arch/parisc/kernel/syscalls/syscall.tbl | 1 +
 arch/powerpc/kernel/syscalls/syscall.tbl| 1 +
 arch/s390/kernel/syscalls/syscall.tbl   | 1 +
 arch/sh/kernel/syscalls/syscall.tbl | 1 +
 arch/sparc/kernel/syscalls/syscall.tbl  | 1 +
 arch/x86/entry/syscalls/syscall_32.tbl  | 1 +
 arch/xtensa/kernel/syscalls/syscall.tbl | 1 +
 include/uapi/asm-generic/unistd.h   | 5 -
 tools/include/uapi/asm-generic/unistd.h | 5 -
 tools/perf/arch/mips/entry/syscalls/syscall_n64.tbl | 1 +
 tools/perf/arch/powerpc/entry/syscalls/syscall.tbl  | 1 +
 tools/perf/arch/s390/entry/syscalls/syscall.tbl | 1 +
 tools/perf/arch/x86/entry/syscalls/syscall_64.tbl   | 1 +
 23 files changed, 30 insertions(+), 3 deletions(-)

diff --git a/arch/alpha/kernel/syscalls/syscall.tbl 
b/arch/alpha/kernel/syscalls/syscall.tbl
index ad37569d0507..6e8479c96e65 100644
--- a/arch/alpha/kernel/syscalls/syscall.tbl
+++ b/arch/alpha/kernel/syscalls/syscall.tbl
@@ -492,3 +492,4 @@
 560common  set_mempolicy_home_node sys_ni_syscall
 561common  cachestat   sys_cachestat
 562common  fchmodat2   sys_fchmodat2
+563common  map_shadow_stacksys_map_shadow_stack
diff --git a/arch/arm/tools/syscall.tbl b/arch/arm/tools/syscall.tbl
index c572d6c3dee0..6d494dfbf5e4 100644
--- a/arch/arm/tools/syscall.tbl
+++ b/arch/arm/tools/syscall.tbl
@@ -466,3 +466,4 @@
 450common  set_mempolicy_home_node sys_set_mempolicy_home_node
 451common  cachestat   sys_cachestat
 452common  fchmodat2   sys_fchmodat2
+453common  map_shadow_stacksys_map_shadow_stack
diff --git a/arch/arm64/include/asm/unistd.h b/arch/arm64/include/asm/unistd.h
index bd77253b62e0..6a28fb91b85d 100644
--- a/arch/arm64/include/asm/unistd.h
+++ b/arch/arm64/include/asm/unistd.h
@@ -39,7 +39,7 @@
 #define __ARM_NR_compat_set_tls(__ARM_NR_COMPAT_BASE + 5)
 #define __ARM_NR_COMPAT_END(__ARM_NR_COMPAT_BASE + 0x800)
 
-#define __NR_compat_syscalls   453
+#define __NR_compat_syscalls   454
 #endif
 
 #define __ARCH_WANT_SYS_CLONE
diff --git a/arch/arm64/include/asm/unistd32.h 
b/arch/arm64/include/asm/unistd32.h
index 78b68311ec81..a201d842ec82 100644
--- a/arch/arm64/include/asm/unistd32.h
+++ b/arch/arm64/include/asm/unistd32.h
@@ -911,6 +911,8 @@ __SYSCALL(__NR_set_mempolicy_home_node, 
sys_set_mempolicy_home_node)
 __SYSCALL(__NR_cachestat, sys_cachestat)
 #define __NR_fchmodat2 452
 __SYSCALL(__NR_fchmodat2, sys_fchmodat2)
+#define __NR_map_shadow_stack 453
+__SYSCALL(__NR_map_shadow_stack, sys_map_shadow_stack)
 
 /*
  * Please add new compat syscalls above this comment and update
diff --git a/arch/ia64/kernel/syscalls/syscall.tbl 
b/arch/ia64/kernel/syscalls/syscall.tbl
index 83d8609aec03..be02ce9d376f 100644
--- a/arch/ia64/kernel/syscalls/syscall.tbl
+++ b/arch/ia64/kernel/syscalls/syscall.tbl
@@ -373,3 +373,4 @@
 450common  set_mempolicy_home_node sys_set_mempolicy_home_node
 451common  cachestat   sys_cachestat
 452common  fchmodat2   sys_fchmodat2
+453common  map_shadow_stacksys_map_shadow_stack
diff --git a/arch/m68k/kernel/syscalls/syscall.tbl 
b/arch/m68k/kernel/syscalls/syscall.tbl
index 259ceb125367..bee2d2f7f82c 100644
--- a/arch/m68k/kernel/syscalls/syscall.tbl
+++ b/arch/m68k/kernel/syscalls/syscall.tbl
@@ -452,3 +452,4 @@
 450common  set_mempolicy_home_node sys_set_mempolicy_home_node
 451common  cachestat   sys_cachestat
 452common  fchmodat2

[PATCH 1/2] tools headers UAPI: Sync fchmodat2() syscall table entries

2023-09-12 Thread Sohil Mehta

The syscall table entries in the core kernel and perf are expected to be
in sync. This would fix perf build warnings and also add support for
fchmodat2 in 'perf trace'.

Signed-off-by: Sohil Mehta 
---
 tools/include/uapi/asm-generic/unistd.h | 5 -
 tools/perf/arch/mips/entry/syscalls/syscall_n64.tbl | 1 +
 tools/perf/arch/powerpc/entry/syscalls/syscall.tbl  | 1 +
 tools/perf/arch/s390/entry/syscalls/syscall.tbl | 1 +
 tools/perf/arch/x86/entry/syscalls/syscall_64.tbl   | 1 +
 5 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/tools/include/uapi/asm-generic/unistd.h 
b/tools/include/uapi/asm-generic/unistd.h
index fd6c1cb585db..abe087c53b4b 100644
--- a/tools/include/uapi/asm-generic/unistd.h
+++ b/tools/include/uapi/asm-generic/unistd.h
@@ -820,8 +820,11 @@ __SYSCALL(__NR_set_mempolicy_home_node, 
sys_set_mempolicy_home_node)
 #define __NR_cachestat 451
 __SYSCALL(__NR_cachestat, sys_cachestat)
 
+#define __NR_fchmodat2 452
+__SYSCALL(__NR_fchmodat2, sys_fchmodat2)
+
 #undef __NR_syscalls
-#define __NR_syscalls 452
+#define __NR_syscalls 453
 
 /*
  * 32 bit systems traditionally used different
diff --git a/tools/perf/arch/mips/entry/syscalls/syscall_n64.tbl 
b/tools/perf/arch/mips/entry/syscalls/syscall_n64.tbl
index cfda2511badf..cb5e757f6621 100644
--- a/tools/perf/arch/mips/entry/syscalls/syscall_n64.tbl
+++ b/tools/perf/arch/mips/entry/syscalls/syscall_n64.tbl
@@ -366,3 +366,4 @@
 449n64 futex_waitv sys_futex_waitv
 450common  set_mempolicy_home_node sys_set_mempolicy_home_node
 451n64 cachestat   sys_cachestat
+452n64 fchmodat2   sys_fchmodat2
diff --git a/tools/perf/arch/powerpc/entry/syscalls/syscall.tbl 
b/tools/perf/arch/powerpc/entry/syscalls/syscall.tbl
index 8c0b08b7a80e..20e50586e8a2 100644
--- a/tools/perf/arch/powerpc/entry/syscalls/syscall.tbl
+++ b/tools/perf/arch/powerpc/entry/syscalls/syscall.tbl
@@ -538,3 +538,4 @@
 449common  futex_waitv sys_futex_waitv
 450nospu   set_mempolicy_home_node sys_set_mempolicy_home_node
 451common  cachestat   sys_cachestat
+452common  fchmodat2   sys_fchmodat2
diff --git a/tools/perf/arch/s390/entry/syscalls/syscall.tbl 
b/tools/perf/arch/s390/entry/syscalls/syscall.tbl
index a6935af2235c..0122cc156952 100644
--- a/tools/perf/arch/s390/entry/syscalls/syscall.tbl
+++ b/tools/perf/arch/s390/entry/syscalls/syscall.tbl
@@ -454,3 +454,4 @@
 449  commonfutex_waitv sys_futex_waitv 
sys_futex_waitv
 450  commonset_mempolicy_home_node sys_set_mempolicy_home_node 
sys_set_mempolicy_home_node
 451  commoncachestat   sys_cachestat   
sys_cachestat
+452  commonfchmodat2   sys_fchmodat2   
sys_fchmodat2
diff --git a/tools/perf/arch/x86/entry/syscalls/syscall_64.tbl 
b/tools/perf/arch/x86/entry/syscalls/syscall_64.tbl
index 227538b0ce80..a5db10ddf540 100644
--- a/tools/perf/arch/x86/entry/syscalls/syscall_64.tbl
+++ b/tools/perf/arch/x86/entry/syscalls/syscall_64.tbl
@@ -373,6 +373,7 @@
 449common  futex_waitv sys_futex_waitv
 450common  set_mempolicy_home_node sys_set_mempolicy_home_node
 451common  cachestat   sys_cachestat
+452common  fchmodat2   sys_fchmodat2
 
 #
 # Due to a historical design error, certain syscalls are numbered differently
-- 
2.34.1

[PATCH 0/2] arch: Sync all syscall tables with 2 newly added system calls

2023-09-12 Thread Sohil Mehta

6.6-rc1 has added support for 2 new system calls:
[1] fchmodat2()
[2] x86-specific map_shadow_stack()

This series mainly synchronizes the syscall tables arcoss the core kernel and
tools to reflect the recent updates.

For fchmodat2(), it fixes the missing entries in the tools directory.

For map_shadow_stack(), it reserves the syscall across the board. Since
map_shadow_stack() is x86 specific for now, it is marked as a conditional
syscall in sys_ni.c. Adding it to the syscall tables of other architectures is
harmless and would return ENOSYS when exercised.

Reserving arch-specific syscall numbers in the tables of all architectures is
good practice and would help avoid future conflicts.

[1]: 
https://lore.kernel.org/lkml/20230824-frohlocken-vorabend-725f6fdaad50@brauner/
[2]: 
https://lore.kernel.org/lkml/20230830234752.19858-1-dave.han...@linux.intel.com/

Sohil Mehta (2):
  tools headers UAPI: Sync fchmodat2() syscall table entries
  arch: Reserve map_shadow_stack() syscall number for all architectures

 arch/alpha/kernel/syscalls/syscall.tbl  | 1 +
 arch/arm/tools/syscall.tbl  | 1 +
 arch/arm64/include/asm/unistd.h | 2 +-
 arch/arm64/include/asm/unistd32.h   | 2 ++
 arch/ia64/kernel/syscalls/syscall.tbl   | 1 +
 arch/m68k/kernel/syscalls/syscall.tbl   | 1 +
 arch/microblaze/kernel/syscalls/syscall.tbl | 1 +
 arch/mips/kernel/syscalls/syscall_n32.tbl   | 1 +
 arch/mips/kernel/syscalls/syscall_n64.tbl   | 1 +
 arch/mips/kernel/syscalls/syscall_o32.tbl   | 1 +
 arch/parisc/kernel/syscalls/syscall.tbl | 1 +
 arch/powerpc/kernel/syscalls/syscall.tbl| 1 +
 arch/s390/kernel/syscalls/syscall.tbl   | 1 +
 arch/sh/kernel/syscalls/syscall.tbl | 1 +
 arch/sparc/kernel/syscalls/syscall.tbl  | 1 +
 arch/x86/entry/syscalls/syscall_32.tbl  | 1 +
 arch/xtensa/kernel/syscalls/syscall.tbl | 1 +
 include/uapi/asm-generic/unistd.h   | 5 -
 tools/include/uapi/asm-generic/unistd.h | 8 +++-
 tools/perf/arch/mips/entry/syscalls/syscall_n64.tbl | 2 ++
 tools/perf/arch/powerpc/entry/syscalls/syscall.tbl  | 2 ++
 tools/perf/arch/s390/entry/syscalls/syscall.tbl | 2 ++
 tools/perf/arch/x86/entry/syscalls/syscall_64.tbl   | 2 ++
 23 files changed, 37 insertions(+), 3 deletions(-)


base-commit: 0bb80ecc33a8fb5a682236443c1e740d5c917d1d
-- 
2.34.1

Re: [PATCH v5 28/31] pinctrl: Add support for the Lantic PEF2256 pinmux

On Tue, Sep 12, 2023 at 4:31 PM Mark Brown  wrote:
> On Tue, Sep 12, 2023 at 01:04:56PM +0200, Linus Walleij wrote:
> > On Tue, Sep 12, 2023 at 12:15 PM Herve Codina  
> > wrote:
>
> > > +/* SPDX-License-Identifier: GPL-2.0 */
> > > +/*
>
> > I think SPDX mandates that you start the tag with C99 comments
>
> > // SPDX-License-Identifier: GPL-2.0-only
>
> Not for headers, they should use C style since they might be included in
> contexts where C++ isn't supported.

Oh right. Thanks Mark!

Yours,
Linus Walleij

Re: KASAN debug kernel fails to boot at early stage when CONFIG_SMP=y is set (kernel 6.5-rc5, PowerMac G4 3,6)

2023-09-12 Thread Erhard Furtner

On Tue, 12 Sep 2023 17:39:10 +
Christophe Leroy  wrote:

> Ah ok, maybe your CPU only has 4 BATs and they are all used, following 
> change would tell us.
> 
> diff --git a/arch/powerpc/mm/book3s32/mmu.c b/arch/powerpc/mm/book3s32/mmu.c
> index 850783cfa9c7..bd26767edce7 100644
> --- a/arch/powerpc/mm/book3s32/mmu.c
> +++ b/arch/powerpc/mm/book3s32/mmu.c
> @@ -86,6 +86,7 @@ int __init find_free_bat(void)
>   if (!(bat[1].batu & 3))
>   return b;
>   }
> + pr_err("NO FREE BAT (%d)\n", n);
>   return -1;
>   }
> 
> Or you have 8 BATs in which case it's an alignment problem, you need to 
> increase CONFIG_DATA_SHIFT to 23, for that you need CONFIG_ADVANCED and 
> CONFIG_DATA_SHIFT_BOOL

Applied all your patches. According to the output my G4 DP seems to have 8 
BATs. Now I get the following output on screen before the freeze:

printk: bootconsole [udbg0] enabled
Total memory = 2048MB; using 4096kB for hash table
mapin_ram:125
mmu_mapin_ram:170 0 3000 140 200
__mmu_mapin_ram:147 0 140
__mmu_mapin_ram:156 140
__mmu_mapin_ram:147 140 3000
NO FREE BAT (8)
__mmu_mapin_ram:156 2000
__mapin_ram_chunk:107 2000 3000
__mapin_ram_chunk:117
mapin_ram:134
kasan_mmu_init:132
kasan_mmu_init:135 0
kasan_mmu_init:140
ioremap() called early from btext_map+0x64/0xdc. Use early_ioremap() instead
Linux version 6.6.0-rc1-PMacG4-dirty (root@T1000) (gcc (Gentoo 12.3.1_p20230526 
p2) 12.3.1 20230526, GNU ld (Gentoo 2.40 p7) 2.40.0) #5 SMP Tue Sep 12 16:50:47 
CEST 2023
kasan_init_region: c000 3000 f800 fe00
NO FREE BAT (8)
kasan_init_region: loop f800 fe00


So I set CONFIG_DATA_SHIFT=23 as suggested but then I only get:

printk: bootconsole [udbg0] enabled
Total memory = 2048MB; using 4096kB for hash table
mapin_ram:125
mmu_mapin_ram:170 0 3000 140 200
__mmu_mapin_ram:147 0 140
__mmu_mapin_ram:156 140
__mmu_mapin_ram:147 140 3000
NO FREE BAT (8)
__mmu_mapin_ram:156 2000
__mapin_ram_chunk:107 2000 3000
__mapin_ram_chunk:117
mapin_ram:134
kasan_mmu_init:132
kasan_mmu_init:135 0
kasan_mmu_init:140


With btext_unmap() left in place in init_32.c I only get:

printk: bootconsole [udbg0] enabled
Total memory = 2048MB; using 4096kB for hash table
mapin_ram:125
mmu_mapin_ram:170 0 3000 140 200
__mmu_mapin_ram:147 0 140
__mmu_mapin_ram:156 140
__mmu_mapin_ram:147 140 3000
NO FREE BAT (8)
__mmu_mapin_ram:156 2000
__mapin_ram_chunk:107 2000 3000
__mapin_ram_chunk:117
mapin_ram:134
btext_unmap:129

Hope the output sheds at least some light on what's going wrong!

Regards,
Erhard

Re: [PATCH v2 1/2] maple_tree: Disable mas_wr_append() when other readers are possible

2023-09-12 Thread Andreas Schwab

On Sep 12 2023, Liam R. Howlett wrote:

> * Andreas Schwab  [230912 14:15]:
>> Any news?  This is still broken.
>
> I have a proposed fix.  I seem to have caused a pre-existing problem to
> show up.  Please see if the attached works for you, and I'll send it
> to a lot of people.

Thanks, it fixes the issue for me (tested both 6.5 and 6.6-rc1).

-- 
Andreas Schwab, sch...@linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510  2552 DF73 E780 A9DA AEC1
"And now for something completely different."

Re: [PATCH] integrity: powerpc: Do not select CA_MACHINE_KEYRING

2023-09-12 Thread Mimi Zohar

On Tue, 2023-09-12 at 22:32 +0300, Jarkko Sakkinen wrote:
> On Tue Sep 12, 2023 at 10:22 PM EEST, Mimi Zohar wrote:
> > On Tue, 2023-09-12 at 12:49 +0300, Jarkko Sakkinen wrote:
> > > On Tue Sep 12, 2023 at 10:41 AM EEST, Michal Suchánek wrote:
> > > > On Mon, Sep 11, 2023 at 11:39:38PM -0400, Nayna wrote:
> > > > > 
> > > > > On 9/7/23 13:32, Michal Suchánek wrote:
> > > > > > Adding more CC's from the original patch, looks like 
> > > > > > get_maintainers is
> > > > > > not that great for this file.
> > > > > > 
> > > > > > On Thu, Sep 07, 2023 at 06:52:19PM +0200, Michal Suchanek wrote:
> > > > > > > No other platform needs CA_MACHINE_KEYRING, either.
> > > > > > > 
> > > > > > > This is policy that should be decided by the administrator, not 
> > > > > > > Kconfig
> > > > > > > dependencies.
> > > > > 
> > > > > We certainly agree that flexibility is important. However, in this 
> > > > > case,
> > > > > this also implies that we are expecting system admins to be security
> > > > > experts. As per our understanding, CA based infrastructure(PKI) is the
> > > > > standard to be followed and not the policy decision. And we can only 
> > > > > speak
> > > > > for Power.
> > > > > 
> > > > > INTEGRITY_CA_MACHINE_KEYRING ensures that we always have CA signed 
> > > > > leaf
> > > > > certs.
> > > >
> > > > And that's the problem.
> > > >
> > > > From a distribution point of view there are two types of leaf certs:
> > > >
> > > >  - leaf certs signed by the distribution CA which need not be imported
> > > >because the distribution CA cert is enrolled one way or another
> > > >  - user generated ad-hoc certificates that are not signed in any way,
> > > >and enrolled by the user
> > > >
> > > > The latter are vouched for by the user by enrolling the certificate, and
> > > > confirming that they really want to trust this certificate. Enrolling
> > > > user certificates is vital for usability or secure boot. Adding extra
> > > > step of creating a CA certificate stored on the same system only
> > > > complicates things with no added benefit.
> > > 
> > > This all comes down to the generic fact that kernel should not
> > > proactively define what it *expects* sysadmins.
> > > 
> > > CA based infrastructure like anything is a policy decision not
> > > a decision to be enforced by kernel.
> >
> > Secure boot requires a signature chain of trust.  IMA extends the
> > secure and trusted boot concepts to the kernel. Missing from that
> > signature chain of trust is the ability of allowing the end
> > machine/system owner to load other certificates without recompiling the
> > kernel. The introduction of the machine keyring was to address this.
> >
> > I'm not questioning the end user's intent on loading local or third
> > party keys via the normal mechanisms. If the existing mechanism(s) for
> > loading local or third party keys were full-proof, then loading a
> > single certificate, self-signed or not, would be fine. However, that
> > isn't the reality.  The security of the two-stage approach is simply
> > not equivalent to loading a single certificate.  Documentation could
> > help the end user/system owner to safely create (and manage) separate
> > certificate signing and code signing certs.
> >
> > Unlike UEFI based systems, PowerVM defines two variables trustedcadb
> > and moduledb, for storing certificate signing and code signing
> > certificates respectively.  First the certs on the trustedcadb are
> > loaded and then the ones on moduledb are loaded.
> 
> There's pragmatic reasons to make things more open than they should be
> in production. As a hardware example I still possess Raspberry Pi 3B for
> test workloads because it has a broken TZ implementation. The world is
> really bigger than production workloads.
> 
> It would be better to document what you said rather than enforce the
> right choice IMHO (e.g. extend Kconfig documentation).

PowerVM LPARs are more about production workloads than a Raspberry Pi. 
:)

-- 
thanks,

Mimi

Re: [PATCH V3] tools/perf: Add includes for detected configs in Makefile.perf

2023-09-12 Thread Arnaldo Carvalho de Melo

Em Tue, Sep 12, 2023 at 07:00:00AM -0700, Ian Rogers escreveu:
> On Mon, Sep 11, 2023 at 11:38 PM Athira Rajeev
>  wrote:
> >
> > Makefile.perf uses "CONFIG_*" checks in the code. Example the config
> > for libtraceevent is used to set PYTHON_EXT_SRCS
> >
> > ifeq ($(CONFIG_LIBTRACEEVENT),y)
> >   PYTHON_EXT_SRCS := $(shell grep -v ^\# util/python-ext-sources)
> > else
> >   PYTHON_EXT_SRCS := $(shell grep -v '^\#\|util/trace-event.c' 
> > util/python-ext-sources)
> > endif
> >
> > But this is not picking the value for CONFIG_LIBTRACEEVENT that is
> > set using the settings in Makefile.config. Include the file
> > ".config-detected" so that make will use the system detected
> > configuration in the CONFIG checks. This will fix isues that
> > could arise when other "CONFIG_*" checks are added to Makefile.perf
> > in future as well.
> >
> > Signed-off-by: Athira Rajeev 
> 
> Reviewed-by: Ian Rogers 

Thanks, applied.

- Arnaldo

 
> Thanks,
> Ian
> 
> > ---
> > Changelog:
> > v2 -> v3:
> > Added -include since in some cases make clean or make
> > will fail when config is not included and if config-detected
> > file is not present.
> >
> > v1 -> v2:
> > Added $(OUTPUT) prefix to config-detected as pointed
> > out by Ian
> >
> >  tools/perf/Makefile.perf | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf
> > index 37af6df7b978..f6fdc2d5a92f 100644
> > --- a/tools/perf/Makefile.perf
> > +++ b/tools/perf/Makefile.perf
> > @@ -351,6 +351,9 @@ export PYTHON_EXTBUILD_LIB PYTHON_EXTBUILD_TMP
> >
> >  python-clean := $(call QUIET_CLEAN, python) $(RM) -r $(PYTHON_EXTBUILD) 
> > $(OUTPUT)python/perf*.so
> >
> > +# Use the detected configuration
> > +-include $(OUTPUT).config-detected
> > +
> >  ifeq ($(CONFIG_LIBTRACEEVENT),y)
> >PYTHON_EXT_SRCS := $(shell grep -v ^\# util/python-ext-sources)
> >  else
> > --
> > 2.31.1
> >

-- 

- Arnaldo

Re: [PATCH] integrity: powerpc: Do not select CA_MACHINE_KEYRING

On Tue Sep 12, 2023 at 10:22 PM EEST, Mimi Zohar wrote:
> On Tue, 2023-09-12 at 12:49 +0300, Jarkko Sakkinen wrote:
> > On Tue Sep 12, 2023 at 10:41 AM EEST, Michal Suchánek wrote:
> > > On Mon, Sep 11, 2023 at 11:39:38PM -0400, Nayna wrote:
> > > > 
> > > > On 9/7/23 13:32, Michal Suchánek wrote:
> > > > > Adding more CC's from the original patch, looks like get_maintainers 
> > > > > is
> > > > > not that great for this file.
> > > > > 
> > > > > On Thu, Sep 07, 2023 at 06:52:19PM +0200, Michal Suchanek wrote:
> > > > > > No other platform needs CA_MACHINE_KEYRING, either.
> > > > > > 
> > > > > > This is policy that should be decided by the administrator, not 
> > > > > > Kconfig
> > > > > > dependencies.
> > > > 
> > > > We certainly agree that flexibility is important. However, in this case,
> > > > this also implies that we are expecting system admins to be security
> > > > experts. As per our understanding, CA based infrastructure(PKI) is the
> > > > standard to be followed and not the policy decision. And we can only 
> > > > speak
> > > > for Power.
> > > > 
> > > > INTEGRITY_CA_MACHINE_KEYRING ensures that we always have CA signed leaf
> > > > certs.
> > >
> > > And that's the problem.
> > >
> > > From a distribution point of view there are two types of leaf certs:
> > >
> > >  - leaf certs signed by the distribution CA which need not be imported
> > >because the distribution CA cert is enrolled one way or another
> > >  - user generated ad-hoc certificates that are not signed in any way,
> > >and enrolled by the user
> > >
> > > The latter are vouched for by the user by enrolling the certificate, and
> > > confirming that they really want to trust this certificate. Enrolling
> > > user certificates is vital for usability or secure boot. Adding extra
> > > step of creating a CA certificate stored on the same system only
> > > complicates things with no added benefit.
> > 
> > This all comes down to the generic fact that kernel should not
> > proactively define what it *expects* sysadmins.
> > 
> > CA based infrastructure like anything is a policy decision not
> > a decision to be enforced by kernel.
>
> Secure boot requires a signature chain of trust.  IMA extends the
> secure and trusted boot concepts to the kernel. Missing from that
> signature chain of trust is the ability of allowing the end
> machine/system owner to load other certificates without recompiling the
> kernel. The introduction of the machine keyring was to address this.
>
> I'm not questioning the end user's intent on loading local or third
> party keys via the normal mechanisms. If the existing mechanism(s) for
> loading local or third party keys were full-proof, then loading a
> single certificate, self-signed or not, would be fine. However, that
> isn't the reality.  The security of the two-stage approach is simply
> not equivalent to loading a single certificate.  Documentation could
> help the end user/system owner to safely create (and manage) separate
> certificate signing and code signing certs.
>
> Unlike UEFI based systems, PowerVM defines two variables trustedcadb
> and moduledb, for storing certificate signing and code signing
> certificates respectively.  First the certs on the trustedcadb are
> loaded and then the ones on moduledb are loaded.

There's pragmatic reasons to make things more open than they should be
in production. As a hardware example I still possess Raspberry Pi 3B for
test workloads because it has a broken TZ implementation. The world is
really bigger than production workloads.

It would be better to document what you said rather than enforce the
right choice IMHO (e.g. extend Kconfig documentation).

BR, Jarkko

Re: [PATCH v2 1/2] maple_tree: Disable mas_wr_append() when other readers are possible

2023-09-12 Thread Liam R. Howlett

* Andreas Schwab  [230912 14:15]:
> Any news?  This is still broken.

I have a proposed fix.  I seem to have caused a pre-existing problem to
show up.  Please see if the attached works for you, and I'll send it
to a lot of people.

Thanks,
Liam
>From 9ef8f834bb0342dc26464b9dd0165929d3e6a7e5 Mon Sep 17 00:00:00 2001
From: "Liam R. Howlett" 
Date: Tue, 12 Sep 2023 13:45:29 -0400
Subject: [PATCH] init/main: Clear boot task idle flag

Initial booting was setting the task flag to idle (PF_IDLE) by the call
path sched_init() -> init_idle().  Having the task idle and calling
call_rcu() in kernel/rcu/tiny.c means that TIF_NEED_RESCHED will be
enabled.  Subsequent calls to any cond_resched() will enable IRQs,
potentially earlier than the enabling of IRQs.

This causes a warning later in start_kernel() as interrupts are enabled
before the are fully set up.

Fix this issue by clearing the PF_IDLE flag on return from sched_init()
and restore the flag in rest_init().

Signed-off-by: Liam R. Howlett 
---
 init/main.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/init/main.c b/init/main.c
index ad920fac325c..46b35be8f00a 100644
--- a/init/main.c
+++ b/init/main.c
@@ -696,7 +696,7 @@ noinline void __ref __noreturn rest_init(void)
 	 */
 	rcu_read_lock();
 	tsk = find_task_by_pid_ns(pid, _pid_ns);
-	tsk->flags |= PF_NO_SETAFFINITY;
+	tsk->flags |= PF_NO_SETAFFINITY | PF_IDLE;
 	set_cpus_allowed_ptr(tsk, cpumask_of(smp_processor_id()));
 	rcu_read_unlock();
 
@@ -938,6 +938,7 @@ void start_kernel(void)
 	 * time - but meanwhile we still have a functioning scheduler.
 	 */
 	sched_init();
+	current->flags &= ~PF_IDLE;
 
 	if (WARN(!irqs_disabled(),
 		 "Interrupts were enabled *very* early, fixing it\n"))
-- 
2.39.2

Re: [PATCH] integrity: powerpc: Do not select CA_MACHINE_KEYRING

2023-09-12 Thread Mimi Zohar

On Tue, 2023-09-12 at 12:49 +0300, Jarkko Sakkinen wrote:
> On Tue Sep 12, 2023 at 10:41 AM EEST, Michal Suchánek wrote:
> > On Mon, Sep 11, 2023 at 11:39:38PM -0400, Nayna wrote:
> > > 
> > > On 9/7/23 13:32, Michal Suchánek wrote:
> > > > Adding more CC's from the original patch, looks like get_maintainers is
> > > > not that great for this file.
> > > > 
> > > > On Thu, Sep 07, 2023 at 06:52:19PM +0200, Michal Suchanek wrote:
> > > > > No other platform needs CA_MACHINE_KEYRING, either.
> > > > > 
> > > > > This is policy that should be decided by the administrator, not 
> > > > > Kconfig
> > > > > dependencies.
> > > 
> > > We certainly agree that flexibility is important. However, in this case,
> > > this also implies that we are expecting system admins to be security
> > > experts. As per our understanding, CA based infrastructure(PKI) is the
> > > standard to be followed and not the policy decision. And we can only speak
> > > for Power.
> > > 
> > > INTEGRITY_CA_MACHINE_KEYRING ensures that we always have CA signed leaf
> > > certs.
> >
> > And that's the problem.
> >
> > From a distribution point of view there are two types of leaf certs:
> >
> >  - leaf certs signed by the distribution CA which need not be imported
> >because the distribution CA cert is enrolled one way or another
> >  - user generated ad-hoc certificates that are not signed in any way,
> >and enrolled by the user
> >
> > The latter are vouched for by the user by enrolling the certificate, and
> > confirming that they really want to trust this certificate. Enrolling
> > user certificates is vital for usability or secure boot. Adding extra
> > step of creating a CA certificate stored on the same system only
> > complicates things with no added benefit.
> 
> This all comes down to the generic fact that kernel should not
> proactively define what it *expects* sysadmins.
> 
> CA based infrastructure like anything is a policy decision not
> a decision to be enforced by kernel.

Secure boot requires a signature chain of trust.  IMA extends the
secure and trusted boot concepts to the kernel. Missing from that
signature chain of trust is the ability of allowing the end
machine/system owner to load other certificates without recompiling the
kernel. The introduction of the machine keyring was to address this.

I'm not questioning the end user's intent on loading local or third
party keys via the normal mechanisms. If the existing mechanism(s) for
loading local or third party keys were full-proof, then loading a
single certificate, self-signed or not, would be fine. However, that
isn't the reality.  The security of the two-stage approach is simply
not equivalent to loading a single certificate.  Documentation could
help the end user/system owner to safely create (and manage) separate
certificate signing and code signing certs.

Unlike UEFI based systems, PowerVM defines two variables trustedcadb
and moduledb, for storing certificate signing and code signing
certificates respectively.  First the certs on the trustedcadb are
loaded and then the ones on moduledb are loaded.

-- 
thanks,

Mimi

Re: [PATCH v5 25/31] dt-bindings: net: Add the Lantiq PEF2256 E1/T1/J1 framer

On Tue, Sep 12, 2023 at 07:13:32PM +0100, Conor Dooley wrote:
> Yo,
> 
> I'm not au fait enough with this to leave particularly meaningful
> comments, so just some minor ones for you.
> 
> On Tue, Sep 12, 2023 at 12:14:44PM +0200, Herve Codina wrote:
> > The Lantiq PEF2256 is a framer and line interface component designed to
> > fulfill all required interfacing between an analog E1/T1/J1 line and the
> > digital PCM system highway/H.100 bus.
> > 
> > Signed-off-by: Herve Codina 
> > Signed-off-by: Christophe Leroy 
> 
> Missing a co-developed-by?

Whomever sends the patch should have the last Sob.

> 
> > ---
> >  .../bindings/net/lantiq,pef2256.yaml  | 214 ++
> >  1 file changed, 214 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/net/lantiq,pef2256.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/net/lantiq,pef2256.yaml 
> > b/Documentation/devicetree/bindings/net/lantiq,pef2256.yaml
> > new file mode 100644
> > index ..c4f21678bf6a
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/net/lantiq,pef2256.yaml
> > @@ -0,0 +1,214 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/net/lantiq,pef2256.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Lantiq PEF2256
> > +
> > +maintainers:
> > +  - Herve Codina 
> > +
> > +description:
> > +  The Lantiq PEF2256, also known as Infineon PEF2256 or FALC56, is a 
> > framer and
> > +  line interface component designed to fulfill all required interfacing 
> > between
> > +  an analog E1/T1/J1 line and the digital PCM system highway/H.100 bus.
> > +
> > +properties:
> > +  compatible:
> > +items:
> > +  - const: lantiq,pef2256
> > +
> > +  reg:
> > +maxItems: 1
> > +
> > +  clocks:
> > +items:
> > +  - description: Master clock
> 
> My OCD is rather upset by the inconsistent capitalisation used here :/
> 
> > +  - description: System Clock Receive
> > +  - description: System Clock Transmit
> > +
> > +  clock-names:
> > +items:
> > +  - const: mclk
> > +  - const: sclkr
> > +  - const: sclkx
> > +
> > +  interrupts:
> > +maxItems: 1
> > +
> > +  reset-gpios:
> > +description:
> > +  GPIO used to reset the device.
> > +maxItems: 1
> > +
> > +  pinctrl:
> > +$ref: /schemas/pinctrl/pinctrl.yaml#
> > +additionalProperties: false
> > +
> > +patternProperties:
> > +  '-pins$':
> > +type: object
> > +$ref: /schemas/pinctrl/pinmux-node.yaml#
> > +additionalProperties: false
> > +
> > +properties:
> > +  pins:
> > +enum: [ RPA, RPB, RPC, RPD, XPA, XPB, XPC, XPD ]
> > +
> > +  function:
> > +enum: [ SYPR, RFM, RFMB, RSIGM, RSIG, DLR, FREEZE, RFSP, LOS,
> > +SYPX, XFMS, XSIG, TCLK, XMFB, XSIGM, DLX, XCLK, XLT,
> > +GPI, GPOH, GPOL ]
> > +
> > +required:
> > +  - pins
> > +  - function
> > +
> > +  lantiq,data-rate-bps:
> > +$ref: /schemas/types.yaml#/definitions/uint32
> > +enum: [2048000, 4096000, 8192000, 16384000]
> 
> -kBps is a standard suffix, would it be worth using that instead here?
> What you have would fit as even multiples.
> Otherwise Rob, should dt-schema grow -bps as a standard suffix?

Yeah, I think that makes sense. I've added it now.

Rob

Re: [PATCHv6 1/3] powerpc/setup: Loosen the mapping between cpu logical id and its seq in dt

Hi Pingfan,

kernel test robot noticed the following build errors:

[auto build test ERROR on powerpc/fixes]
[also build test ERROR on linus/master v6.6-rc1 next-20230912]
[cannot apply to powerpc/next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:
https://github.com/intel-lab-lkp/linux/commits/Pingfan-Liu/powerpc-setup-Loosen-the-mapping-between-cpu-logical-id-and-its-seq-in-dt/20230911-213042
base:   https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git fixes
patch link:
https://lore.kernel.org/r/20230911131855.40738-2-piliu%40redhat.com
patch subject: [PATCHv6 1/3] powerpc/setup: Loosen the mapping between cpu 
logical id and its seq in dt
config: powerpc-randconfig-r032-20230912 
(https://download.01.org/0day-ci/archive/20230913/202309130232.n2rewhbv-...@intel.com/config)
compiler: clang version 17.0.0 (https://github.com/llvm/llvm-project.git 
4a5ac14ee968ff0ad5d2cc1ffa0299048db4c88a)
reproduce (this is a W=1 build): 
(https://download.01.org/0day-ci/archive/20230913/202309130232.n2rewhbv-...@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot 
| Closes: 
https://lore.kernel.org/oe-kbuild-all/202309130232.n2rewhbv-...@intel.com/

All errors (new ones prefixed by >>):

>> ld.lld: error: undefined symbol: boot_cpu_hwid
   >>> referenced by setup-common.c:0 (arch/powerpc/kernel/setup-common.c:0)
   >>>   arch/powerpc/kernel/setup-common.o:(smp_setup_cpu_maps) in 
archive vmlinux.a
   >>> referenced by setup-common.c:0 (arch/powerpc/kernel/setup-common.c:0)
   >>>   arch/powerpc/kernel/setup-common.o:(smp_setup_cpu_maps) in 
archive vmlinux.a

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH v5 25/31] dt-bindings: net: Add the Lantiq PEF2256 E1/T1/J1 framer



Le 12/09/2023 à 20:13, Conor Dooley a écrit :
> Yo,
> 
> I'm not au fait enough with this to leave particularly meaningful
> comments, so just some minor ones for you.
> 
> On Tue, Sep 12, 2023 at 12:14:44PM +0200, Herve Codina wrote:
>> The Lantiq PEF2256 is a framer and line interface component designed to
>> fulfill all required interfacing between an analog E1/T1/J1 line and the
>> digital PCM system highway/H.100 bus.
>>
>> Signed-off-by: Herve Codina 
>> Signed-off-by: Christophe Leroy 
> 
> Missing a co-developed-by?

No, I guess it's a left-over of version v4 that I sent-out while Hervé 
was AFK.

If a v6 is sent I think this line can be removed.

Christophe

Re: [PATCH v5 07/31] dt-bindings: soc: fsl: cpm_qe: cpm1-scc-qmc: Add 'additionalProperties: false' in child nodes



On Tue, 12 Sep 2023 10:14:58 +0200, Herve Codina wrote:
> Additional properties in child node should not be allowed.
> 
> Prevent them adding 'additionalProperties: false'
> 
> Signed-off-by: Herve Codina 
> ---
>  .../devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring

Re: [PATCH v5 06/31] dt-bindings: soc: fsl: cpm_qe: cpm1-scc-qmc: Fix example property name

On Tue, Sep 12, 2023 at 12:58:32PM -0500, Rob Herring wrote:
> On Tue, Sep 12, 2023 at 10:14:57AM +0200, Herve Codina wrote:
> > The given example mentions the 'fsl,mode' property whereas the
> > correct property name, the one described, is 'fsl,operational-mode'.
> > 
> > Fix the example to use the correct property name.
> > 
> > Fixes: a9b121327c93 ("dt-bindings: soc: fsl: cpm_qe: Add QMC controller")
> > Signed-off-by: Herve Codina 
> > ---
> >  .../bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml   | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> I have this same fix in my tree, but you missed something. Please add 
> additionalProperties or unevaluatedProperties to the child node schema 
> so that this error is flagged.

NM, I see the next patch now.

Acked-by: Rob Herring

Re: [PATCH v2 1/2] maple_tree: Disable mas_wr_append() when other readers are possible

2023-09-12 Thread Andreas Schwab

Any news?  This is still broken.

-- 
Andreas Schwab, sch...@linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510  2552 DF73 E780 A9DA AEC1
"And now for something completely different."

Re: [PATCH v5 25/31] dt-bindings: net: Add the Lantiq PEF2256 E1/T1/J1 framer

Yo,

I'm not au fait enough with this to leave particularly meaningful
comments, so just some minor ones for you.

On Tue, Sep 12, 2023 at 12:14:44PM +0200, Herve Codina wrote:
> The Lantiq PEF2256 is a framer and line interface component designed to
> fulfill all required interfacing between an analog E1/T1/J1 line and the
> digital PCM system highway/H.100 bus.
> 
> Signed-off-by: Herve Codina 
> Signed-off-by: Christophe Leroy 

Missing a co-developed-by?

> ---
>  .../bindings/net/lantiq,pef2256.yaml  | 214 ++
>  1 file changed, 214 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/net/lantiq,pef2256.yaml
> 
> diff --git a/Documentation/devicetree/bindings/net/lantiq,pef2256.yaml 
> b/Documentation/devicetree/bindings/net/lantiq,pef2256.yaml
> new file mode 100644
> index ..c4f21678bf6a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/lantiq,pef2256.yaml
> @@ -0,0 +1,214 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/lantiq,pef2256.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Lantiq PEF2256
> +
> +maintainers:
> +  - Herve Codina 
> +
> +description:
> +  The Lantiq PEF2256, also known as Infineon PEF2256 or FALC56, is a framer 
> and
> +  line interface component designed to fulfill all required interfacing 
> between
> +  an analog E1/T1/J1 line and the digital PCM system highway/H.100 bus.
> +
> +properties:
> +  compatible:
> +items:
> +  - const: lantiq,pef2256
> +
> +  reg:
> +maxItems: 1
> +
> +  clocks:
> +items:
> +  - description: Master clock

My OCD is rather upset by the inconsistent capitalisation used here :/

> +  - description: System Clock Receive
> +  - description: System Clock Transmit
> +
> +  clock-names:
> +items:
> +  - const: mclk
> +  - const: sclkr
> +  - const: sclkx
> +
> +  interrupts:
> +maxItems: 1
> +
> +  reset-gpios:
> +description:
> +  GPIO used to reset the device.
> +maxItems: 1
> +
> +  pinctrl:
> +$ref: /schemas/pinctrl/pinctrl.yaml#
> +additionalProperties: false
> +
> +patternProperties:
> +  '-pins$':
> +type: object
> +$ref: /schemas/pinctrl/pinmux-node.yaml#
> +additionalProperties: false
> +
> +properties:
> +  pins:
> +enum: [ RPA, RPB, RPC, RPD, XPA, XPB, XPC, XPD ]
> +
> +  function:
> +enum: [ SYPR, RFM, RFMB, RSIGM, RSIG, DLR, FREEZE, RFSP, LOS,
> +SYPX, XFMS, XSIG, TCLK, XMFB, XSIGM, DLX, XCLK, XLT,
> +GPI, GPOH, GPOL ]
> +
> +required:
> +  - pins
> +  - function
> +
> +  lantiq,data-rate-bps:
> +$ref: /schemas/types.yaml#/definitions/uint32
> +enum: [2048000, 4096000, 8192000, 16384000]

-kBps is a standard suffix, would it be worth using that instead here?
What you have would fit as even multiples.
Otherwise Rob, should dt-schema grow -bps as a standard suffix?

> +default: 2048000
> +description:
> +  Data rate (bit per seconds) on the system highway.
> +
> +  lantiq,clock-falling-edge:
> +$ref: /schemas/types.yaml#/definitions/flag
> +description:
> +  Data is sent on falling edge of the clock (and received on the rising
> +  edge). If 'clock-falling-edge' is not present, data is sent on the
> +  rising edge (and received on the falling edge).
> +
> +  lantiq,channel-phase:
> +$ref: /schemas/types.yaml#/definitions/uint32
> +enum: [0, 1, 2, 3, 4, 5, 6, 7]
> +default: 0
> +description: |
> +  The pef2256 delivers a full frame (32 8bit time-slots in E1 and 24 8bit

Just a wee nit, s/8bit/8-bit/ :)

Rest of this I don't really feel like I can really review.

Thanks,
Conor.

> +  time-slots 8 8bit signaling in E1/J1) every 125us. This lead to a data
> +  rate of 2048000 bit/s. When lantiq,data-rate-bps is more than 2048000
> +  bit/s, the data (all 32 8bit) present in the frame are interleave with
> +  unused time-slots. The lantiq,channel-phase property allows to set the
> +  correct alignment of the interleave mechanism.
> +  For instance, suppose lantiq,data-rate-bps = 8192000 (ie 4*2048000), 
> and
> +  lantiq,channel-phase = 2, the interleave schema with unused time-slots
> +  (nu) and used time-slots (XX) for TSi is
> +nu nu XX nu nu nu XX nu nu nu XX nu
> +<-- TSi --> <- TSi+1 -> <- TSi+2 ->
> +  With lantiq,data-rate-bps = 8192000, and lantiq,channel-phase = 1, the
> +  interleave schema is
> +nu XX nu nu nu XX nu nu nu XX nu nu
> +<-- TSi --> <- TSi+1 -> <- TSi+2 ->
> +  With lantiq,data-rate-bps = 4096000 (ie 2*2048000), and
> +  lantiq,channel-phase = 1, the interleave schema is
> +nuXXnuXXnuXX
> +<-- TSi --> <- TSi+1 -> <- TSi+2 ->
> +
> +patternProperties:
> +

Re: [PATCH v5 06/31] dt-bindings: soc: fsl: cpm_qe: cpm1-scc-qmc: Fix example property name

On Tue, Sep 12, 2023 at 10:14:57AM +0200, Herve Codina wrote:
> The given example mentions the 'fsl,mode' property whereas the
> correct property name, the one described, is 'fsl,operational-mode'.
> 
> Fix the example to use the correct property name.
> 
> Fixes: a9b121327c93 ("dt-bindings: soc: fsl: cpm_qe: Add QMC controller")
> Signed-off-by: Herve Codina 
> ---
>  .../bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml   | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)

I have this same fix in my tree, but you missed something. Please add 
additionalProperties or unevaluatedProperties to the child node schema 
so that this error is flagged.

> 
> diff --git 
> a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml 
> b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
> index ec888f48cac8..450a0354cb1d 100644
> --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
> +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
> @@ -137,7 +137,7 @@ examples:
>  channel@16 {
>  /* Ch16 : First 4 even TS from all routed from TSA */
>  reg = <16>;
> -fsl,mode = "transparent";
> +fsl,operational-mode = "transparent";
>  fsl,reverse-data;
>  fsl,tx-ts-mask = <0x 0x00aa>;
>  fsl,rx-ts-mask = <0x 0x00aa>;
> @@ -146,7 +146,7 @@ examples:
>  channel@17 {
>  /* Ch17 : First 4 odd TS from all routed from TSA */
>  reg = <17>;
> -fsl,mode = "transparent";
> +fsl,operational-mode = "transparent";
>  fsl,reverse-data;
>  fsl,tx-ts-mask = <0x 0x0055>;
>  fsl,rx-ts-mask = <0x 0x0055>;
> @@ -155,7 +155,7 @@ examples:
>  channel@19 {
>  /* Ch19 : 8 TS (TS 8..15) from all routed from TSA */
>  reg = <19>;
> -fsl,mode = "hdlc";
> +fsl,operational-mode = "hdlc";
>  fsl,tx-ts-mask = <0x 0xff00>;
>  fsl,rx-ts-mask = <0x 0xff00>;
>  };
> -- 
> 2.41.0
>

Re: KASAN debug kernel fails to boot at early stage when CONFIG_SMP=y is set (kernel 6.5-rc5, PowerMac G4 3,6)



Le 12/09/2023 à 17:59, Erhard Furtner a écrit :
> 
> printk: bootconsole [udbg0] enabled
> Total memory = 2048MB; using 4096kB for hash table
> mapin_ram:125
> mmu_mapin_ram:169 0 3000 140 200
> __mmu_mapin_ram:146 0 140
> __mmu_mapin_ram:155 140
> __mmu_mapin_ram:146 140 3000
> __mmu_mapin_ram:155 2000
> __mapin_ram_chunk:107 2000 3000
> __mapin_ram_chunk:117
> mapin_ram:134
> kasan_mmu_init:129
> kasan_mmu_init:132 0
> kasan_mmu_init:137
> ioremap() called early from btext_map+0x64/0xdc. Use early_ioremap() instead
> Linux version 6.6.0-rc1-PMacG4-dirty (root@T1000) (gcc (Gentoo 
> 12.3.1_p20230526 p2) 12.3.1 20230526, GNU ld (Gentoo 2.40 p7) 2.40.0) #5 SMP 
> Tue Sep 12 16:50:47 CEST 2023
> kasan_init_region: c000 3000 f800 fe00
> kasan_init_region: loop f800 fe00
> 
> 
> So I get no "kasan_init_region: setbat" line and don't reach "KASAN init 
> done".

Ah ok, maybe your CPU only has 4 BATs and they are all used, following 
change would tell us.

diff --git a/arch/powerpc/mm/book3s32/mmu.c b/arch/powerpc/mm/book3s32/mmu.c
index 850783cfa9c7..bd26767edce7 100644
--- a/arch/powerpc/mm/book3s32/mmu.c
+++ b/arch/powerpc/mm/book3s32/mmu.c
@@ -86,6 +86,7 @@ int __init find_free_bat(void)
if (!(bat[1].batu & 3))
return b;
}
+   pr_err("NO FREE BAT (%d)\n", n);
return -1;
  }


Or you have 8 BATs in which case it's an alignment problem, you need to 
increase CONFIG_DATA_SHIFT to 23, for that you need CONFIG_ADVANCED and 
CONFIG_DATA_SHIFT_BOOL

But regardless of that there is a problem we need to find out, because 
it should work without BATs.

As the BATs allocation fails, it falls back to :

phys = memblock_phys_alloc_range(k_end - k_start, PAGE_SIZE, 0,
 MEMBLOCK_ALLOC_ANYWHERE);
if (!phys)
return -ENOMEM;
}

ret = kasan_init_shadow_page_tables(k_start, k_end);
if (ret)
return ret;

for (k_cur = k_start; k_cur < k_end; k_cur += PAGE_SIZE) {
pmd_t *pmd = pmd_off_k(k_cur);
pte_t pte = pfn_pte(PHYS_PFN(phys + k_cur - k_start), 
PAGE_KERNEL);

__set_pte_at(_mm, k_cur, pte_offset_kernel(pmd, k_cur), 
pte, 0);
}
flush_tlb_kernel_range(k_start, k_end);
memset(kasan_mem_to_shadow(start), 0, k_end - k_start);


While the __weak function that you confirmed working is:

ret = kasan_init_shadow_page_tables(k_start, k_end);
if (ret)
return ret;

block = memblock_alloc(k_end - k_start, PAGE_SIZE);
if (!block)
return -ENOMEM;

for (k_cur = k_start & PAGE_MASK; k_cur < k_end; k_cur += PAGE_SIZE) {
pmd_t *pmd = pmd_off_k(k_cur);
void *va = block + k_cur - k_start;
pte_t pte = pfn_pte(PHYS_PFN(__pa(va)), PAGE_KERNEL);

__set_pte_at(_mm, k_cur, pte_offset_kernel(pmd, k_cur), 
pte, 0);
}
flush_tlb_kernel_range(k_start, k_end);


I'm having hard time to understand what's could be wrong at the first place.

Could you try following change:

diff --git a/arch/powerpc/mm/kasan/book3s_32.c 
b/arch/powerpc/mm/kasan/book3s_32.c
index 9954b7a3b7ae..e04f21908c6a 100644
--- a/arch/powerpc/mm/kasan/book3s_32.c
+++ b/arch/powerpc/mm/kasan/book3s_32.c
@@ -38,7 +38,7 @@ int __init kasan_init_region(void *start, size_t size)

if (k_nobat < k_end) {
phys = memblock_phys_alloc_range(k_end - k_nobat, PAGE_SIZE, 0,
-MEMBLOCK_ALLOC_ANYWHERE);
+MEMBLOCK_ALLOC_ACCESSIBLE);
if (!phys)
return -ENOMEM;
}

And also that one:


diff --git a/arch/powerpc/mm/kasan/init_32.c 
b/arch/powerpc/mm/kasan/init_32.c
index a70828a6d935..bc1c075489f4 100644
--- a/arch/powerpc/mm/kasan/init_32.c
+++ b/arch/powerpc/mm/kasan/init_32.c
@@ -84,6 +84,9 @@ kasan_update_early_region(unsigned long k_start, 
unsigned long k_end, pte_t pte)
  {
unsigned long k_cur;

+   if (k_start == k_end)
+   return;
+
for (k_cur = k_start; k_cur != k_end; k_cur += PAGE_SIZE) {
pmd_t *pmd = pmd_off_k(k_cur);
pte_t *ptep = pte_offset_kernel(pmd, k_cur);



Thanks
Christophe

Re: [PATCH v2 2/3] KEYS: trusted: Introduce support for NXP DCP-based trusted keys

On Tue Sep 12, 2023 at 2:11 PM EEST, David Gstir wrote:
> DCP (Data Co-Processor) is the little brother of NXP's CAAM IP.
>
> Beside of accelerated crypto operations, it also offers support for
> hardware-bound keys. Using this feature it is possible to implement a blob
> mechanism just like CAAM offers. Unlike on CAAM, constructing and
> parsing the blob has to happen in software.
>
> We chose the following format for the blob:
> /*
>  * struct dcp_blob_fmt - DCP BLOB format.
>  *
>  * @fmt_version: Format version, currently being %1
>  * @blob_key: Random AES 128 key which is used to encrypt @payload,
>  *@blob_key itself is encrypted with OTP or UNIQUE device key in
>  *AES-128-ECB mode by DCP.
>  * @nonce: Random nonce used for @payload encryption.
>  * @payload_len: Length of the plain text @payload.
>  * @payload: The payload itself, encrypted using AES-128-GCM and @blob_key,
>  *   GCM auth tag of size AES_BLOCK_SIZE is attached at the end of it.
>  *
>  * The total size of a DCP BLOB is sizeof(struct dcp_blob_fmt) + @payload_len 
> +
>  * AES_BLOCK_SIZE.
>  */
> struct dcp_blob_fmt {
>   __u8 fmt_version;
>   __u8 blob_key[AES_KEYSIZE_128];
>   __u8 nonce[AES_KEYSIZE_128];
>   __le32 payload_len;
>   __u8 payload[];
> } __packed;
>
> @payload is the key provided by trusted_key_ops->seal().
>
> By default the UNIQUE device key is used, it is also possible to use
> the OTP key. While the UNIQUE device key should be unique it is not
> entirely clear whether this is the case due to unclear documentation.
> If someone wants to be sure they can burn their own unique key
> into the OTP fuse and set the use_otp_key module parameter.
>
> Co-developed-by: Richard Weinberger 
> Signed-off-by: Richard Weinberger 
> Co-developed-by: David Oberhollenzer 
> Signed-off-by: David Oberhollenzer 
> Signed-off-by: David Gstir 
> ---
>  .../admin-guide/kernel-parameters.txt |  13 +
>  MAINTAINERS   |   9 +
>  include/keys/trusted_dcp.h|  13 +
>  security/keys/trusted-keys/Kconfig|   9 +-
>  security/keys/trusted-keys/Makefile   |   2 +
>  security/keys/trusted-keys/trusted_core.c |   6 +-
>  security/keys/trusted-keys/trusted_dcp.c  | 313 ++
>  7 files changed, 363 insertions(+), 2 deletions(-)
>  create mode 100644 include/keys/trusted_dcp.h
>  create mode 100644 security/keys/trusted-keys/trusted_dcp.c
>
> diff --git a/Documentation/admin-guide/kernel-parameters.txt 
> b/Documentation/admin-guide/kernel-parameters.txt
> index 0a1731a0f0ef..c11eda8b38e0 100644
> --- a/Documentation/admin-guide/kernel-parameters.txt
> +++ b/Documentation/admin-guide/kernel-parameters.txt
> @@ -6566,6 +6566,7 @@
>   - "tpm"
>   - "tee"
>   - "caam"
> + - "dcp"
>   If not specified then it defaults to iterating through
>   the trust source list starting with TPM and assigns the
>   first trust source as a backend which is initialized
> @@ -6581,6 +6582,18 @@
>   If not specified, "default" is used. In this case,
>   the RNG's choice is left to each individual trust 
> source.
>  
> + trusted.dcp_use_otp_key
> + This is intended to be used in combination with
> + trusted.source=dcp and will select the DCP OTP key
> + instead of the DCP UNIQUE key blob encryption.
> +
> + trusted.dcp_skip_zk_test
> + This is intended to be used in combination with
> + trusted.source=dcp and will disable the check if all
> + the blob key is zero'ed. This is helpful for situations 
> where
> + having this key zero'ed is acceptable. E.g. in testing
> + scenarios.
> +
>   tsc=Disable clocksource stability checks for TSC.
>   Format: 
>   [x86] reliable: mark tsc clocksource as reliable, this
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 90f13281d297..988d01226131 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -11647,6 +11647,15 @@ S:   Maintained
>  F:   include/keys/trusted_caam.h
>  F:   security/keys/trusted-keys/trusted_caam.c
>  
> +KEYS-TRUSTED-DCP
> +M:   David Gstir 
> +R:   sigma star Kernel Team 
> +L:   linux-integr...@vger.kernel.org
> +L:   keyri...@vger.kernel.org
> +S:   Supported
> +F:   include/keys/trusted_dcp.h
> +F:   security/keys/trusted-keys/trusted_dcp.c
> +
>  KEYS-TRUSTED-TEE
>  M:   Sumit Garg 
>  L:   linux-integr...@vger.kernel.org
> diff --git a/include/keys/trusted_dcp.h b/include/keys/trusted_dcp.h
> new file mode 100644
> index ..7b2a1275c527
> --- /dev/null
> +++ b/include/keys/trusted_dcp.h
> @@ -0,0 +1,13 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */

Re: [PATCH v2 1/3] crypto: mxs-dcp: Add support for hardware provided keys

On Tue Sep 12, 2023 at 2:11 PM EEST, David Gstir wrote:
> @@ -101,6 +102,7 @@ struct dcp_async_ctx {
>   struct crypto_skcipher  *fallback;
>   unsigned intkey_len;
>   uint8_t key[AES_KEYSIZE_128];
> + boolrefkey;
>  };

s/refkey/key_referenced/

No reason to obfuscate it, especially since there is no supporting
documentation.

BR, Jarkko

Re: [PATCH v2 1/3] crypto: mxs-dcp: Add support for hardware provided keys

On Tue Sep 12, 2023 at 2:11 PM EEST, David Gstir wrote:
> DCP is capable to performing AES with hardware-bound keys.
> These keys are not stored in main memory and are therefore not directly
> accessible by the operating system.
>
> So instead of feeding the key into DCP, we need to place a
> reference to such a key before initiating the crypto operation.
> Keys are referenced by a one byte identifiers.
>
> DCP supports 6 different keys: 4 slots in the secure memory area,
> a one time programmable key which can be burnt via on-chip fuses
> and an unique device key.
>
> Using these keys is restricted to in-kernel users that use them as building
> block for other crypto tools such as trusted keys. Allowing userspace
> (e.g. via AF_ALG) to use these keys to crypt or decrypt data is a security
> risk, because there is no access control mechanism.
>
> Co-developed-by: Richard Weinberger 
> Signed-off-by: Richard Weinberger 
> Co-developed-by: David Oberhollenzer 
> Signed-off-by: David Oberhollenzer 
> Signed-off-by: David Gstir 
> ---
>  drivers/crypto/mxs-dcp.c | 107 +++
>  include/soc/fsl/dcp.h|  19 +++
>  2 files changed, 115 insertions(+), 11 deletions(-)
>  create mode 100644 include/soc/fsl/dcp.h
>
> diff --git a/drivers/crypto/mxs-dcp.c b/drivers/crypto/mxs-dcp.c
> index f6b7bce0e656..d525cb41f2ca 100644
> --- a/drivers/crypto/mxs-dcp.c
> +++ b/drivers/crypto/mxs-dcp.c
> @@ -15,6 +15,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  
>  #include 
>  #include 
> @@ -101,6 +102,7 @@ struct dcp_async_ctx {
>   struct crypto_skcipher  *fallback;
>   unsigned intkey_len;
>   uint8_t key[AES_KEYSIZE_128];
> + boolrefkey;
>  };
>  
>  struct dcp_aes_req_ctx {
> @@ -155,6 +157,7 @@ static struct dcp *global_sdcp;
>  #define MXS_DCP_CONTROL0_HASH_TERM   (1 << 13)
>  #define MXS_DCP_CONTROL0_HASH_INIT   (1 << 12)
>  #define MXS_DCP_CONTROL0_PAYLOAD_KEY (1 << 11)
> +#define MXS_DCP_CONTROL0_OTP_KEY (1 << 10)
>  #define MXS_DCP_CONTROL0_CIPHER_ENCRYPT  (1 << 8)
>  #define MXS_DCP_CONTROL0_CIPHER_INIT (1 << 9)
>  #define MXS_DCP_CONTROL0_ENABLE_HASH (1 << 6)
> @@ -168,6 +171,8 @@ static struct dcp *global_sdcp;
>  #define MXS_DCP_CONTROL1_CIPHER_MODE_ECB (0 << 4)
>  #define MXS_DCP_CONTROL1_CIPHER_SELECT_AES128(0 << 0)
>  
> +#define MXS_DCP_CONTROL1_KEY_SELECT_SHIFT8
> +
>  static int mxs_dcp_start_dma(struct dcp_async_ctx *actx)
>  {
>   int dma_err;
> @@ -224,13 +229,16 @@ static int mxs_dcp_run_aes(struct dcp_async_ctx *actx,
>   struct dcp *sdcp = global_sdcp;
>   struct dcp_dma_desc *desc = >coh->desc[actx->chan];
>   struct dcp_aes_req_ctx *rctx = skcipher_request_ctx(req);
> + bool key_referenced = actx->refkey;
>   int ret;
>  
> - key_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_key,
> -   2 * AES_KEYSIZE_128, DMA_TO_DEVICE);
> - ret = dma_mapping_error(sdcp->dev, key_phys);
> - if (ret)
> - return ret;
> + if (!key_referenced) {
> + key_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_key,
> +   2 * AES_KEYSIZE_128, DMA_TO_DEVICE);
> + ret = dma_mapping_error(sdcp->dev, key_phys);
> + if (ret)
> + return ret;
> + }
>  
>   src_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_in_buf,
> DCP_BUF_SZ, DMA_TO_DEVICE);
> @@ -255,8 +263,13 @@ static int mxs_dcp_run_aes(struct dcp_async_ctx *actx,
>   MXS_DCP_CONTROL0_INTERRUPT |
>   MXS_DCP_CONTROL0_ENABLE_CIPHER;
>  
> - /* Payload contains the key. */
> - desc->control0 |= MXS_DCP_CONTROL0_PAYLOAD_KEY;
> + if (key_referenced) {
> + /* Set OTP key bit to select the key via KEY_SELECT. */
> + desc->control0 |= MXS_DCP_CONTROL0_OTP_KEY;
> + } else {
> + /* Payload contains the key. */
> + desc->control0 |= MXS_DCP_CONTROL0_PAYLOAD_KEY;
> + }

Remove curly braces (coding style).

>  
>   if (rctx->enc)
>   desc->control0 |= MXS_DCP_CONTROL0_CIPHER_ENCRYPT;
> @@ -270,6 +283,9 @@ static int mxs_dcp_run_aes(struct dcp_async_ctx *actx,
>   else
>   desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_CBC;
>  
> + if (key_referenced)
> + desc->control1 |= sdcp->coh->aes_key[0] << 
> MXS_DCP_CONTROL1_KEY_SELECT_SHIFT;
> +
>   desc->next_cmd_addr = 0;
>   desc->source = src_phys;
>   desc->destination = dst_phys;
> @@ -284,9 +300,10 @@ static int mxs_dcp_run_aes(struct dcp_async_ctx *actx,
>  err_dst:
>   dma_unmap_single(sdcp->dev, src_phys, DCP_BUF_SZ, DMA_TO_DEVICE);
>  err_src:
> - dma_unmap_single(sdcp->dev, key_phys, 2 * AES_KEYSIZE_128,
> -

Re: [PATCH v5 08/31] dt-bindings: soc: fsl: cpm_qe: cpm1-scc-qmc: Add support for QMC HDLC

On Tue, Sep 12, 2023 at 12:10:18PM +0200, Herve Codina wrote:
> The QMC (QUICC mutichannel controller) is a controller present in some
> PowerQUICC SoC such as MPC885.
> The QMC HDLC uses the QMC controller to transfer HDLC data.
> 
> Additionally, a framer can be connected to the QMC HDLC.
> If present, this framer is the interface between the TDM bus used by the
> QMC HDLC and the E1/T1 line.
> The QMC HDLC can use this framer to get information about the E1/T1 line
> and configure the E1/T1 line.
> 
> Signed-off-by: Herve Codina 
> ---
>  .../bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml   | 13 +
>  1 file changed, 13 insertions(+)
> 
> diff --git 
> a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml 
> b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
> index 82d9beb48e00..b5073531f3f1 100644
> --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
> +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
> @@ -101,6 +101,16 @@ patternProperties:
>Channel assigned Rx time-slots within the Rx time-slots routed by 
> the
>TSA to this cell.
>  
> +  compatible:
> +const: fsl,qmc-hdlc
> +
> +  fsl,framer:
> +$ref: /schemas/types.yaml#/definitions/phandle
> +description:
> +  phandle to the framer node. The framer is in charge of an E1/T1 
> line
> +  interface connected to the TDM bus. It can be used to get the 
> E1/T1 line
> +  status such as link up/down.

Sounds like this fsl,framer property should depend on the compatible
being present, no?

Thanks,
Conor.

> +
>  required:
>- reg
>- fsl,tx-ts-mask
> @@ -159,5 +169,8 @@ examples:
>  fsl,operational-mode = "hdlc";
>  fsl,tx-ts-mask = <0x 0xff00>;
>  fsl,rx-ts-mask = <0x 0xff00>;
> +
> +compatible = "fsl,qmc-hdlc";
> +fsl,framer = <>;
>  };
>  };
> -- 
> 2.41.0
> 


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Re: [PATCH] integrity: powerpc: Do not select CA_MACHINE_KEYRING

On Tue Sep 12, 2023 at 6:39 AM EEST, Nayna wrote:
>
> On 9/7/23 13:32, Michal Suchánek wrote:
> > Adding more CC's from the original patch, looks like get_maintainers is
> > not that great for this file.
> >
> > On Thu, Sep 07, 2023 at 06:52:19PM +0200, Michal Suchanek wrote:
> >> No other platform needs CA_MACHINE_KEYRING, either.
> >>
> >> This is policy that should be decided by the administrator, not Kconfig
> >> dependencies.
>
> We certainly agree that flexibility is important. However, in this case, 
> this also implies that we are expecting system admins to be security 
> experts. As per our understanding, CA based infrastructure(PKI) is the 
> standard to be followed and not the policy decision. And we can only 
> speak for Power.

In the end this is dictating policy for no compelling reason, and
that is the bottom line here, not playing a mind game what type of
expertise a sysadmin might or might not have.

BR, Jarkko

Re: [PATCH v5 07/31] dt-bindings: soc: fsl: cpm_qe: cpm1-scc-qmc: Add 'additionalProperties: false' in child nodes

On Tue, Sep 12, 2023 at 10:14:58AM +0200, Herve Codina wrote:
> Additional properties in child node should not be allowed.
> 
> Prevent them adding 'additionalProperties: false'
> 
> Signed-off-by: Herve Codina 

Acked-by: Conor Dooley 

Thanks,
Conor.

> ---
>  .../devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git 
> a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml 
> b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
> index 450a0354cb1d..82d9beb48e00 100644
> --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
> +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
> @@ -64,6 +64,7 @@ patternProperties:
>  description:
>A channel managed by this controller
>  type: object
> +additionalProperties: false
>  
>  properties:
>reg:
> -- 
> 2.41.0
> 


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Re: [PATCH v5 06/31] dt-bindings: soc: fsl: cpm_qe: cpm1-scc-qmc: Fix example property name

On Tue, Sep 12, 2023 at 10:14:57AM +0200, Herve Codina wrote:
> The given example mentions the 'fsl,mode' property whereas the
> correct property name, the one described, is 'fsl,operational-mode'.
> 
> Fix the example to use the correct property name.
> 
> Fixes: a9b121327c93 ("dt-bindings: soc: fsl: cpm_qe: Add QMC controller")
> Signed-off-by: Herve Codina 

Acked-by: Conor Dooley 

Thanks,
Conor.

> ---
>  .../bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml   | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git 
> a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml 
> b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
> index ec888f48cac8..450a0354cb1d 100644
> --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
> +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
> @@ -137,7 +137,7 @@ examples:
>  channel@16 {
>  /* Ch16 : First 4 even TS from all routed from TSA */
>  reg = <16>;
> -fsl,mode = "transparent";
> +fsl,operational-mode = "transparent";
>  fsl,reverse-data;
>  fsl,tx-ts-mask = <0x 0x00aa>;
>  fsl,rx-ts-mask = <0x 0x00aa>;
> @@ -146,7 +146,7 @@ examples:
>  channel@17 {
>  /* Ch17 : First 4 odd TS from all routed from TSA */
>  reg = <17>;
> -fsl,mode = "transparent";
> +fsl,operational-mode = "transparent";
>  fsl,reverse-data;
>  fsl,tx-ts-mask = <0x 0x0055>;
>  fsl,rx-ts-mask = <0x 0x0055>;
> @@ -155,7 +155,7 @@ examples:
>  channel@19 {
>  /* Ch19 : 8 TS (TS 8..15) from all routed from TSA */
>  reg = <19>;
> -fsl,mode = "hdlc";
> +fsl,operational-mode = "hdlc";
>  fsl,tx-ts-mask = <0x 0xff00>;
>  fsl,rx-ts-mask = <0x 0xff00>;
>  };
> -- 
> 2.41.0
> 


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Re: KASAN debug kernel fails to boot at early stage when CONFIG_SMP=y is set (kernel 6.5-rc5, PowerMac G4 3,6)

2023-09-12 Thread Erhard Furtner

On Tue, 12 Sep 2023 07:47:50 +
Christophe Leroy  wrote:

> I suspect something wrong when we set the BATs.
> 
> Can you try with the following additional traces:
> 
> diff --git a/arch/powerpc/mm/kasan/book3s_32.c 
> b/arch/powerpc/mm/kasan/book3s_32.c
> index 450a67ef0bbe..9954b7a3b7ae 100644
> --- a/arch/powerpc/mm/kasan/book3s_32.c
> +++ b/arch/powerpc/mm/kasan/book3s_32.c
> @@ -15,6 +15,7 @@ int __init kasan_init_region(void *start, size_t size)
>   phys_addr_t phys;
>   int ret;
> 
> + pr_err("%s: %px %x %lx %lx\n", __func__, start, size, k_start, k_end);
>   while (k_nobat < k_end) {
>   unsigned int k_size = bat_block_size(k_nobat, k_end);
>   int idx = find_free_bat();
> @@ -28,6 +29,7 @@ int __init kasan_init_region(void *start, size_t size)
>   if (!phys)
>   break;
> 
> + pr_err("%s: setbat %d %lx %x %x\n", __func__, idx, k_nobat, 
> phys, 
> k_size);
>   setbat(idx, k_nobat, phys, k_size, PAGE_KERNEL);
>   k_nobat += k_size;
>   }
> @@ -47,6 +49,7 @@ int __init kasan_init_region(void *start, size_t size)
> 
>   kasan_update_early_region(k_start, k_nobat, __pte(0));
> 
> + pr_err("%s: loop %lx %lx\n", __func__, k_nobat, k_end);
>   for (k_cur = k_nobat; k_cur < k_end; k_cur += PAGE_SIZE) {
>   pmd_t *pmd = pmd_off_k(k_cur);
>   pte_t pte = pfn_pte(PHYS_PFN(phys + k_cur - k_nobat), 
> PAGE_KERNEL);
> 
> 
> You'd then get something like:
> 
> Total memory = 2048MB; using 4096kB for hash table
> Activating Kernel Userspace Access Protection
> Activating Kernel Userspace Execution Prevention
> Linux version 6.6.0-rc1+ (chle...@po20335.idsi0.si.c-s.fr) 
> (powerpc64-linux-gcc (GCC) 12.2.0, GNU ld (GNU Binutils) 2.39) #461 Tue 
> Sep 12 09:37:11 CEST 2023
> kasan_init_region: c000 3000 f800 fe00
> kasan_init_region: setbat 3 f800 7c00 400
> kasan_init_region: loop fc00 fe00
> KASAN init done

Applied this patch on top of 6.6-rc1, your old pr_info() patch and Michaels 
patch.

This way booting gets stuck at:
printk: bootconsole [udbg0] enabled
Total memory = 2048MB; using 4096kB for hash table
mapin_ram:125
mmu_mapin_ram:169 0 3000 140 200
__mmu_mapin_ram:146 0 140
__mmu_mapin_ram:155 140
__mmu_mapin_ram:146 140 3000
__mmu_mapin_ram:155 2000
__mapin_ram_chunk:107 2000 3000
__mapin_ram_chunk:117
mapin_ram:134
btext_unmap:129

Having moved btext_unmap() after memblock_set_current_limit(lowmem_end_addr) in 
init_32.c I get:

printk: bootconsole [udbg0] enabled
Total memory = 2048MB; using 4096kB for hash table
mapin_ram:125
mmu_mapin_ram:169 0 3000 140 200
__mmu_mapin_ram:146 0 140
__mmu_mapin_ram:155 140
__mmu_mapin_ram:146 140 3000
__mmu_mapin_ram:155 2000
__mapin_ram_chunk:107 2000 3000
__mapin_ram_chunk:117
mapin_ram:134
kasan_mmu_init:129
kasan_mmu_init:132 0
kasan_mmu_init:137
btext_unmap:129

Changing the already moved btext_unmap() to btext_map() I get:

printk: bootconsole [udbg0] enabled
Total memory = 2048MB; using 4096kB for hash table
mapin_ram:125
mmu_mapin_ram:169 0 3000 140 200
__mmu_mapin_ram:146 0 140
__mmu_mapin_ram:155 140
__mmu_mapin_ram:146 140 3000
__mmu_mapin_ram:155 2000
__mapin_ram_chunk:107 2000 3000
__mapin_ram_chunk:117
mapin_ram:134
kasan_mmu_init:129
kasan_mmu_init:132 0
kasan_mmu_init:137
ioremap() called early from btext_map+0x64/0xdc. Use early_ioremap() instead
Linux version 6.6.0-rc1-PMacG4-dirty (root@T1000) (gcc (Gentoo 12.3.1_p20230526 
p2) 12.3.1 20230526, GNU ld (Gentoo 2.40 p7) 2.40.0) #5 SMP Tue Sep 12 16:50:47 
CEST 2023
kasan_init_region: c000 3000 f800 fe00
kasan_init_region: loop f800 fe00


So I get no "kasan_init_region: setbat" line and don't reach "KASAN init done".

Regards,
Erhard

Re: [PATCH v5 28/31] pinctrl: Add support for the Lantic PEF2256 pinmux

2023-09-12 Thread Mark Brown

On Tue, Sep 12, 2023 at 01:04:56PM +0200, Linus Walleij wrote:
> On Tue, Sep 12, 2023 at 12:15 PM Herve Codina  
> wrote:

> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*

> I think SPDX mandates that you start the tag with C99 comments

> // SPDX-License-Identifier: GPL-2.0-only

Not for headers, they should use C style since they might be included in
contexts where C++ isn't supported.


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Re: [PATCH V3] tools/perf: Add includes for detected configs in Makefile.perf

2023-09-12 Thread Ian Rogers

On Mon, Sep 11, 2023 at 11:38 PM Athira Rajeev
 wrote:
>
> Makefile.perf uses "CONFIG_*" checks in the code. Example the config
> for libtraceevent is used to set PYTHON_EXT_SRCS
>
> ifeq ($(CONFIG_LIBTRACEEVENT),y)
>   PYTHON_EXT_SRCS := $(shell grep -v ^\# util/python-ext-sources)
> else
>   PYTHON_EXT_SRCS := $(shell grep -v '^\#\|util/trace-event.c' 
> util/python-ext-sources)
> endif
>
> But this is not picking the value for CONFIG_LIBTRACEEVENT that is
> set using the settings in Makefile.config. Include the file
> ".config-detected" so that make will use the system detected
> configuration in the CONFIG checks. This will fix isues that
> could arise when other "CONFIG_*" checks are added to Makefile.perf
> in future as well.
>
> Signed-off-by: Athira Rajeev 

Reviewed-by: Ian Rogers 

Thanks,
Ian

> ---
> Changelog:
> v2 -> v3:
> Added -include since in some cases make clean or make
> will fail when config is not included and if config-detected
> file is not present.
>
> v1 -> v2:
> Added $(OUTPUT) prefix to config-detected as pointed
> out by Ian
>
>  tools/perf/Makefile.perf | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf
> index 37af6df7b978..f6fdc2d5a92f 100644
> --- a/tools/perf/Makefile.perf
> +++ b/tools/perf/Makefile.perf
> @@ -351,6 +351,9 @@ export PYTHON_EXTBUILD_LIB PYTHON_EXTBUILD_TMP
>
>  python-clean := $(call QUIET_CLEAN, python) $(RM) -r $(PYTHON_EXTBUILD) 
> $(OUTPUT)python/perf*.so
>
> +# Use the detected configuration
> +-include $(OUTPUT).config-detected
> +
>  ifeq ($(CONFIG_LIBTRACEEVENT),y)
>PYTHON_EXT_SRCS := $(shell grep -v ^\# util/python-ext-sources)
>  else
> --
> 2.31.1
>

Re: WARN: Interrupts were enabled early [bisected cfeb6ae8bcb9 ("maple_tree: disable mas_wr_append() when other readers are possible")]

2023-09-12 Thread Liam R. Howlett

* Christophe Leroy  [230912 06:56]:
> Hi,
> 
> With pmac32_defconfig on QEMU I get the following WARN with 6.6-rc1
> 
> Bisected to cfeb6ae8bcb9 ("maple_tree: disable mas_wr_append() when 
> other readers are possible")
> 
> I have absolutely no idea what it can be, do you ?

Please see the discussion on the mailing list [1].  We are looking at it
there and would appreciate anything you can add.

[1]. 
https://lore.kernel.org/linux-mm/3f86d58e-7f36-c6b4-c43a-2a7bcffd...@linux-m68k.org/

Thanks,
Liam

> 
> [ cut here ]
> Interrupts were enabled early
> WARNING: CPU: 0 PID: 0 at init/main.c:992 start_kernel+0x4d8/0x5c0
> Modules linked in:
> CPU: 0 PID: 0 Comm: swapper Not tainted 6.6.0-rc1 #480
> Hardware name: PowerMac3,1 7400 0xc0209 PowerMac
> NIP:  c0a6052c LR: c0a6052c CTR: 
> REGS: c0c4dee0 TRAP: 0700   Not tainted  (6.6.0-rc1)
> MSR:  00029032   CR: 24000282  XER: 2000
> 
> GPR00: c0a6052c c0c4dfa0 c0b92580 001d c0b9d128 0001 c0b9d148 
> 3dff
> GPR08: c0ba80f0   3e00 44000282   
> 0199abf8
> GPR16: 0199b0a0 7fde7fa4 7fc5ac0c 00bb 4100 01c690c8 c0b92014 
> c09b4bcc
> GPR24: c0c55220 c0ac  efff9109 efff9100 000a c0c6d000 
> c0b920a0
> NIP [c0a6052c] start_kernel+0x4d8/0x5c0
> LR [c0a6052c] start_kernel+0x4d8/0x5c0
> Call Trace:
> [c0c4dfa0] [c0a6052c] start_kernel+0x4d8/0x5c0 (unreliable)
> [c0c4dff0] [3540] 0x3540
> Code: 480037b1 48023c05 4bab88cd 90620260 480139e9 4b657ccd 7d2000a6 
> 71298000 41a20014 3c60c09a 3863b788 4b5e9ccd <0fe0> 3920 
> 99380008 7d2000a6
> ---[ end trace  ]---
> 
> Christophe

[PATCH v4 4/5] arch/powerpc: Remove file parameter from phys_mem_access_prot code

Remove 'file' parameter from struct machdep_calls.phys_mem_access_prot
and its implementation in pci_phys_mem_access_prot(). The file is not
used on PowerPC. By removing it, a later patch can simplify fbdev's
mmap code, which uses phys_mem_access_prot() on PowerPC.

Signed-off-by: Thomas Zimmermann 
---
 arch/powerpc/include/asm/book3s/pgtable.h | 10 --
 arch/powerpc/include/asm/machdep.h|  3 +--
 arch/powerpc/include/asm/nohash/pgtable.h | 10 --
 arch/powerpc/include/asm/pci.h|  4 +---
 arch/powerpc/kernel/pci-common.c  |  3 +--
 arch/powerpc/mm/mem.c |  8 
 6 files changed, 23 insertions(+), 15 deletions(-)

diff --git a/arch/powerpc/include/asm/book3s/pgtable.h 
b/arch/powerpc/include/asm/book3s/pgtable.h
index d18b748ea3ae0..84e36a5726417 100644
--- a/arch/powerpc/include/asm/book3s/pgtable.h
+++ b/arch/powerpc/include/asm/book3s/pgtable.h
@@ -20,9 +20,15 @@ extern void set_pte_at(struct mm_struct *mm, unsigned long 
addr, pte_t *ptep,
 extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long 
address,
 pte_t *ptep, pte_t entry, int dirty);
 
+extern pgprot_t __phys_mem_access_prot(unsigned long pfn, unsigned long size,
+  pgprot_t vma_prot);
+
 struct file;
-extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
-unsigned long size, pgprot_t vma_prot);
+static inline pgprot_t phys_mem_access_prot(struct file *file, unsigned long 
pfn,
+   unsigned long size, pgprot_t 
vma_prot)
+{
+   return __phys_mem_access_prot(pfn, size, vma_prot);
+}
 #define __HAVE_PHYS_MEM_ACCESS_PROT
 
 void __update_mmu_cache(struct vm_area_struct *vma, unsigned long address, 
pte_t *ptep);
diff --git a/arch/powerpc/include/asm/machdep.h 
b/arch/powerpc/include/asm/machdep.h
index 933465ed4c432..d31a5ec1550d4 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -106,8 +106,7 @@ struct machdep_calls {
int (*pci_get_legacy_ide_irq)(struct pci_dev *dev, int 
channel);
 
/* Get access protection for /dev/mem */
-   pgprot_t(*phys_mem_access_prot)(struct file *file,
-   unsigned long pfn,
+   pgprot_t(*phys_mem_access_prot)(unsigned long pfn,
unsigned long size,
pgprot_t vma_prot);
 
diff --git a/arch/powerpc/include/asm/nohash/pgtable.h 
b/arch/powerpc/include/asm/nohash/pgtable.h
index a6cb6f922..90366b0b3ad9a 100644
--- a/arch/powerpc/include/asm/nohash/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/pgtable.h
@@ -246,9 +246,15 @@ extern int ptep_set_access_flags(struct vm_area_struct 
*vma, unsigned long addre
 
 #define pgprot_writecombine pgprot_noncached_wc
 
+extern pgprot_t __phys_mem_access_prot(unsigned long pfn, unsigned long size,
+  pgprot_t vma_prot);
+
 struct file;
-extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
-unsigned long size, pgprot_t vma_prot);
+static inline pgprot_t phys_mem_access_prot(struct file *file, unsigned long 
pfn,
+   unsigned long size, pgprot_t 
vma_prot)
+{
+   return __phys_mem_access_prot(pfn, size, vma_prot);
+}
 #define __HAVE_PHYS_MEM_ACCESS_PROT
 
 #ifdef CONFIG_HUGETLB_PAGE
diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h
index 289f1ec85bc54..34ed4d51c546b 100644
--- a/arch/powerpc/include/asm/pci.h
+++ b/arch/powerpc/include/asm/pci.h
@@ -104,9 +104,7 @@ extern void of_scan_pci_bridge(struct pci_dev *dev);
 extern void of_scan_bus(struct device_node *node, struct pci_bus *bus);
 extern void of_rescan_bus(struct device_node *node, struct pci_bus *bus);
 
-struct file;
-extern pgprot_tpci_phys_mem_access_prot(struct file *file,
-unsigned long pfn,
+extern pgprot_tpci_phys_mem_access_prot(unsigned long pfn,
 unsigned long size,
 pgprot_t prot);
 
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index e88d7c9feeec3..73f12a17e572e 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -521,8 +521,7 @@ int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct 
vm_area_struct *vma)
  * PCI device, it tries to find the PCI device first and calls the
  * above routine
  */
-pgprot_t pci_phys_mem_access_prot(struct file *file,
- unsigned long pfn,
+pgprot_t pci_phys_mem_access_prot(unsigned long pfn,
  unsigned long size,
  pgprot_t prot)
 {
diff

[PATCH v4 5/5] arch/powerpc: Call internal __phys_mem_access_prot() in fbdev code

Call __phys_mem_access_prot() from the fbdev mmap helper
pgprot_framebuffer(). Allows to avoid the file argument of NULL.

Signed-off-by: Thomas Zimmermann 
---
 arch/powerpc/include/asm/fb.h | 7 +--
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/arch/powerpc/include/asm/fb.h b/arch/powerpc/include/asm/fb.h
index 3cecf14d51de8..c0c5d1df7ad1e 100644
--- a/arch/powerpc/include/asm/fb.h
+++ b/arch/powerpc/include/asm/fb.h
@@ -8,12 +8,7 @@ static inline pgprot_t pgprot_framebuffer(pgprot_t prot,
  unsigned long vm_start, unsigned long 
vm_end,
  unsigned long offset)
 {
-   /*
-* PowerPC's implementation of phys_mem_access_prot() does
-* not use the file argument. Set it to NULL in preparation
-* of later updates to the interface.
-*/
-   return phys_mem_access_prot(NULL, PHYS_PFN(offset), vm_end - vm_start, 
prot);
+   return __phys_mem_access_prot(PHYS_PFN(offset), vm_end - vm_start, 
prot);
 }
 #define pgprot_framebuffer pgprot_framebuffer
 
-- 
2.42.0

[PATCH v4 0/5] ppc, fbdev: Clean up fbdev mmap helper

Clean up and rename fb_pgprotect() to work without struct file. Then
refactor the implementation for PowerPC. This change has been discussed
at [1] in the context of refactoring fbdev's mmap code.

The first two patches update fbdev and replace fbdev's fb_pgprotect()
with pgprot_framebuffer() on all architectures. The new helper's stream-
lined interface enables more refactoring within fbdev's mmap
implementation.

Patches 3 to 5 adapt PowerPC's internal interfaces to provide
phys_mem_access_prot() that works without struct file. Neither the
architecture code or fbdev helpers need the parameter.

v4:
* fix commit message (Christophe)
v3:
* rename fb_pgrotect() to pgprot_framebuffer() (Arnd)
v2:
* reorder patches to simplify merging (Michael)

[1] 
https://lore.kernel.org/linuxppc-dev/5501ba80-bdb0-6344-16b0-0466a950f...@suse.com/

Thomas Zimmermann (5):
  fbdev: Avoid file argument in fb_pgprotect()
  fbdev: Replace fb_pgprotect() with pgprot_framebuffer()
  arch/powerpc: Remove trailing whitespaces
  arch/powerpc: Remove file parameter from phys_mem_access_prot code
  arch/powerpc: Call internal __phys_mem_access_prot() in fbdev code

 arch/ia64/include/asm/fb.h| 15 +++
 arch/m68k/include/asm/fb.h| 19 ++-
 arch/mips/include/asm/fb.h| 11 +--
 arch/powerpc/include/asm/book3s/pgtable.h | 10 --
 arch/powerpc/include/asm/fb.h | 13 +
 arch/powerpc/include/asm/machdep.h| 13 ++---
 arch/powerpc/include/asm/nohash/pgtable.h | 10 --
 arch/powerpc/include/asm/pci.h|  4 +---
 arch/powerpc/kernel/pci-common.c  |  3 +--
 arch/powerpc/mm/mem.c |  8 
 arch/sparc/include/asm/fb.h   | 15 +--
 arch/x86/include/asm/fb.h | 10 ++
 arch/x86/video/fbdev.c| 15 ---
 drivers/video/fbdev/core/fb_chrdev.c  |  3 ++-
 include/asm-generic/fb.h  | 12 ++--
 15 files changed, 86 insertions(+), 75 deletions(-)

-- 
2.42.0

[PATCH v4 1/5] fbdev: Avoid file argument in fb_pgprotect()

Only PowerPC's fb_pgprotect() needs the file argument, although
the implementation does not use it. Pass NULL to the internal
helper in preparation of further updates. A later patch will remove
the file parameter from fb_pgprotect().

While at it, replace the shift operation with PHYS_PFN().

Suggested-by: Christophe Leroy 
Signed-off-by: Thomas Zimmermann 
---
 arch/powerpc/include/asm/fb.h | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/include/asm/fb.h b/arch/powerpc/include/asm/fb.h
index 5f1a2e5f76548..61e3b8806db69 100644
--- a/arch/powerpc/include/asm/fb.h
+++ b/arch/powerpc/include/asm/fb.h
@@ -9,7 +9,12 @@
 static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
unsigned long off)
 {
-   vma->vm_page_prot = phys_mem_access_prot(file, off >> PAGE_SHIFT,
+   /*
+* PowerPC's implementation of phys_mem_access_prot() does
+* not use the file argument. Set it to NULL in preparation
+* of later updates to the interface.
+*/
+   vma->vm_page_prot = phys_mem_access_prot(NULL, PHYS_PFN(off),
 vma->vm_end - vma->vm_start,
 vma->vm_page_prot);
 }
-- 
2.42.0

[PATCH v4 2/5] fbdev: Replace fb_pgprotect() with pgprot_framebuffer()

Rename the fbdev mmap helper fb_pgprotect() to pgprot_framebuffer().
The helper sets VMA page-access flags for framebuffers in device I/O
memory.

Also clean up the helper's parameters and return value. Instead of
the VMA instance, pass the individial parameters separately: existing
page-access flags, the VMAs start and end addresses and the offset
in the underlying device memory rsp file. Return the new page-access
flags. These changes align pgprot_framebuffer() with other pgprot_()
functions.

v4:
* fix commit message (Christophe)
v3:
* rename fb_pgprotect() to pgprot_framebuffer() (Arnd)

Signed-off-by: Thomas Zimmermann 
---
 arch/ia64/include/asm/fb.h   | 15 +++
 arch/m68k/include/asm/fb.h   | 19 ++-
 arch/mips/include/asm/fb.h   | 11 +--
 arch/powerpc/include/asm/fb.h| 13 +
 arch/sparc/include/asm/fb.h  | 15 +--
 arch/x86/include/asm/fb.h| 10 ++
 arch/x86/video/fbdev.c   | 15 ---
 drivers/video/fbdev/core/fb_chrdev.c |  3 ++-
 include/asm-generic/fb.h | 12 ++--
 9 files changed, 58 insertions(+), 55 deletions(-)

diff --git a/arch/ia64/include/asm/fb.h b/arch/ia64/include/asm/fb.h
index 1717b26fd423f..7fce0d5423590 100644
--- a/arch/ia64/include/asm/fb.h
+++ b/arch/ia64/include/asm/fb.h
@@ -8,17 +8,16 @@
 
 #include 
 
-struct file;
-
-static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
-   unsigned long off)
+static inline pgprot_t pgprot_framebuffer(pgprot_t prot,
+ unsigned long vm_start, unsigned long 
vm_end,
+ unsigned long offset)
 {
-   if (efi_range_is_wc(vma->vm_start, vma->vm_end - vma->vm_start))
-   vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+   if (efi_range_is_wc(vm_start, vm_end - vm_start))
+   return pgprot_writecombine(prot);
else
-   vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+   return pgprot_noncached(prot);
 }
-#define fb_pgprotect fb_pgprotect
+#define pgprot_framebuffer pgprot_framebuffer
 
 static inline void fb_memcpy_fromio(void *to, const volatile void __iomem 
*from, size_t n)
 {
diff --git a/arch/m68k/include/asm/fb.h b/arch/m68k/include/asm/fb.h
index 24273fc7ad917..9941b7434b696 100644
--- a/arch/m68k/include/asm/fb.h
+++ b/arch/m68k/include/asm/fb.h
@@ -5,26 +5,27 @@
 #include 
 #include 
 
-struct file;
-
-static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
-   unsigned long off)
+static inline pgprot_t pgprot_framebuffer(pgprot_t prot,
+ unsigned long vm_start, unsigned long 
vm_end,
+ unsigned long offset)
 {
 #ifdef CONFIG_MMU
 #ifdef CONFIG_SUN3
-   pgprot_val(vma->vm_page_prot) |= SUN3_PAGE_NOCACHE;
+   pgprot_val(prot) |= SUN3_PAGE_NOCACHE;
 #else
if (CPU_IS_020_OR_030)
-   pgprot_val(vma->vm_page_prot) |= _PAGE_NOCACHE030;
+   pgprot_val(prot) |= _PAGE_NOCACHE030;
if (CPU_IS_040_OR_060) {
-   pgprot_val(vma->vm_page_prot) &= _CACHEMASK040;
+   pgprot_val(prot) &= _CACHEMASK040;
/* Use no-cache mode, serialized */
-   pgprot_val(vma->vm_page_prot) |= _PAGE_NOCACHE_S;
+   pgprot_val(prot) |= _PAGE_NOCACHE_S;
}
 #endif /* CONFIG_SUN3 */
 #endif /* CONFIG_MMU */
+
+   return prot;
 }
-#define fb_pgprotect fb_pgprotect
+#define pgprot_framebuffer pgprot_framebuffer
 
 #include 
 
diff --git a/arch/mips/include/asm/fb.h b/arch/mips/include/asm/fb.h
index 18b7226403bad..d98d6681d64ec 100644
--- a/arch/mips/include/asm/fb.h
+++ b/arch/mips/include/asm/fb.h
@@ -3,14 +3,13 @@
 
 #include 
 
-struct file;
-
-static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
-   unsigned long off)
+static inline pgprot_t pgprot_framebuffer(pgprot_t prot,
+ unsigned long vm_start, unsigned long 
vm_end,
+ unsigned long offset)
 {
-   vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+   return pgprot_noncached(prot);
 }
-#define fb_pgprotect fb_pgprotect
+#define pgprot_framebuffer pgprot_framebuffer
 
 /*
  * MIPS doesn't define __raw_ I/O macros, so the helpers
diff --git a/arch/powerpc/include/asm/fb.h b/arch/powerpc/include/asm/fb.h
index 61e3b8806db69..3cecf14d51de8 100644
--- a/arch/powerpc/include/asm/fb.h
+++ b/arch/powerpc/include/asm/fb.h
@@ -2,23 +2,20 @@
 #ifndef _ASM_FB_H_
 #define _ASM_FB_H_
 
-#include 
-
 #include 
 
-static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
-   unsigned long off)
+static inline

[PATCH v4 3/5] arch/powerpc: Remove trailing whitespaces

Fix coding style. No functional changes.

Signed-off-by: Thomas Zimmermann 
---
 arch/powerpc/include/asm/machdep.h | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/powerpc/include/asm/machdep.h 
b/arch/powerpc/include/asm/machdep.h
index 4f6e7d7ee3883..933465ed4c432 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -10,7 +10,7 @@
 #include 
 
 struct pt_regs;
-struct pci_bus;
+struct pci_bus;
 struct device_node;
 struct iommu_table;
 struct rtc_time;
@@ -78,8 +78,8 @@ struct machdep_calls {
unsigned char   (*nvram_read_val)(int addr);
void(*nvram_write_val)(int addr, unsigned char val);
ssize_t (*nvram_write)(char *buf, size_t count, loff_t *index);
-   ssize_t (*nvram_read)(char *buf, size_t count, loff_t *index);  
-   ssize_t (*nvram_size)(void);
+   ssize_t (*nvram_read)(char *buf, size_t count, loff_t *index);
+   ssize_t (*nvram_size)(void);
void(*nvram_sync)(void);
 
/* Exception handlers */
@@ -102,9 +102,9 @@ struct machdep_calls {
 */
long(*feature_call)(unsigned int feature, ...);
 
-   /* Get legacy PCI/IDE interrupt mapping */ 
+   /* Get legacy PCI/IDE interrupt mapping */
int (*pci_get_legacy_ide_irq)(struct pci_dev *dev, int 
channel);
-   
+
/* Get access protection for /dev/mem */
pgprot_t(*phys_mem_access_prot)(struct file *file,
unsigned long pfn,
-- 
2.42.0

Re: [RFC PATCH] powerpc: Make crashing cpu to be discovered first in kdump kernel.

2023-09-12 Thread Mahesh J Salgaonkar

On 2023-09-11 21:23:42 Mon, Pingfan Liu wrote:
> Hi Mahesh,
> 
> I am not quite sure about fdt, so I skip that part, and leave some
> comments from the kexec view.
> 
> On Thu, Sep 7, 2023 at 1:59 AM Mahesh Salgaonkar  wrote:
> >
> > The kernel boot parameter 'nr_cpus=' allows one to specify number of
> > possible cpus in the system. In the normal scenario the first cpu (cpu0)
> > that shows up is the boot cpu and hence it gets covered under nr_cpus
> > limit.
> >
> > But this assumption is broken in kdump scenario where kdump kernel after a
> > crash can boot up on an non-zero boot cpu. The paca structure allocation
> > depends on value of nr_cpus and is indexed using logical cpu ids. The cpu
> > discovery code brings up the cpus as they appear sequentially on device
> > tree and assigns logical cpu ids starting from 0. This definitely becomes
> > an issue if boot cpu id > nr_cpus. When this occurs it results into
> >
> > In past there were proposals to fix this by making changes to cpu discovery
> > code to identify non-zero boot cpu and map it to logical cpu 0. However,
> > the changes were very invasive, making discovery code more complicated and
> > risky.
> >
> > Considering that the non-zero boot cpu scenario is more specific to kdump
> > kernel, limiting the changes in panic/crash kexec path would probably be a
> > best approach to have.
> >
> > Hence proposed change is, in crash kexec path, move the crashing cpu's
> > device node to the first position under '/cpus' node, which will make the
> > crashing cpu to be discovered as part of the first core in kdump kernel.
> >
> > In order to accommodate boot cpu for the case where boot_cpuid > nr_cpu_ids,
> > align up the nr_cpu_ids to SMT threads in early_init_dt_scan_cpus(). This
> > will allow kdump kernel to work with nr_cpus=X where X will be aligned up
> > in multiple of SMT threads per core.
> >
> > Signed-off-by: Mahesh Salgaonkar 
> > ---
> >  arch/powerpc/include/asm/kexec.h  |1
> >  arch/powerpc/kernel/prom.c|   13 
> >  arch/powerpc/kexec/core_64.c  |  128 
> > +
> >  arch/powerpc/kexec/file_load_64.c |2 -
> >  4 files changed, 143 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/powerpc/include/asm/kexec.h 
> > b/arch/powerpc/include/asm/kexec.h
> > index a1ddba01e7d13..f5a6f4a1b8eb0 100644
> > --- a/arch/powerpc/include/asm/kexec.h
> > +++ b/arch/powerpc/include/asm/kexec.h
> > @@ -144,6 +144,7 @@ unsigned int kexec_extra_fdt_size_ppc64(struct kimage 
> > *image);
> >  int setup_new_fdt_ppc64(const struct kimage *image, void *fdt,
> > unsigned long initrd_load_addr,
> > unsigned long initrd_len, const char *cmdline);
> > +int add_node_props(void *fdt, int node_offset, const struct device_node 
> > *dn);
> >  #endif /* CONFIG_PPC64 */
> >
> >  #endif /* CONFIG_KEXEC_FILE */
> > diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
> > index 0b5878c3125b1..c2d4f55042d72 100644
> > --- a/arch/powerpc/kernel/prom.c
> > +++ b/arch/powerpc/kernel/prom.c
> > @@ -322,6 +322,9 @@ static void __init 
> > check_cpu_feature_properties(unsigned long node)
> > }
> >  }
> >
> > +/* align addr on a size boundary - adjust address up */
> > +#define _ALIGN_UP(addr, size)   
> > (((addr)+((size)-1))&(~((typeof(addr))(size)-1)))
> > +
> >  static int __init early_init_dt_scan_cpus(unsigned long node,
> >   const char *uname, int depth,
> >   void *data)
> > @@ -348,6 +351,16 @@ static int __init early_init_dt_scan_cpus(unsigned 
> > long node,
> >
> > nthreads = len / sizeof(int);
> >
> > +   /*
> > +* Align nr_cpu_ids to correct SMT value. This will help us to 
> > allocate
> > +* pacas correctly to accomodate boot_cpu != 0 scenario e.g. in 
> > kdump
> > +* kernel the boot cpu can be any cpu between 0 through nthreads.
> > +*/
> > +   if (nr_cpu_ids % nthreads) {
> > +   nr_cpu_ids = _ALIGN_UP(nr_cpu_ids, nthreads);
> 
> It is better to use set_nr_cpu_ids(), which can hide the difference of
> nr_cpus_ids under different kernel configuration.

Yup, I have fixed that in RFC v2 at 
https://lore.kernel.org/linuxppc-dev/169426331903.1523857.16489366285648613217.stgit@jupiter/

> 
> > +   pr_info("Aligned nr_cpus to SMT=%d, nr_cpu_ids = %d\n", 
> > nthreads, nr_cpu_ids);
> > +   }
> > +
> > /*
> >  * Now see if any of these threads match our boot cpu.
> >  * NOTE: This must match the parsing done in smp_setup_cpu_maps.
> > +
[...]
> >  /* too late to fail here */
> >  void default_machine_kexec(struct kimage *image)
> >  {
> > @@ -341,6 +455,20 @@ void default_machine_kexec(struct kimage *image)
> > printk("kexec: Unshared all shared pages.\n");
> > }
> >
> > +   /*
> > +* Move the crashing cpus FDT node as the

Re: [PATCH v5 29/31] MAINTAINERS: Add the Lantiq PEF2256 driver entry

On Tue, Sep 12, 2023 at 12:15 PM Herve Codina  wrote:

> After contributing the driver, add myself as the maintainer for the
> Lantiq PEF2256 driver.
>
> Signed-off-by: Herve Codina 
> Reviewed-by: Christophe Leroy 
> Signed-off-by: Christophe Leroy 
> ---
>  MAINTAINERS | 9 +
>  1 file changed, 9 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 8b987f2c8633..dbc5867016bc 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -11876,6 +11876,15 @@ S: Maintained
>  F: arch/mips/lantiq
>  F: drivers/soc/lantiq
>
> +LANTIQ PEF2256 DRIVER
> +M: Herve Codina 
> +S: Maintained
> +F: Documentation/devicetree/bindings/net/lantiq,pef2256.yaml
> +F: drivers/net/wan/framer/pef2256/
> +F: drivers/pinctrl/pinctrl-pef2256-regs.h
> +F: drivers/pinctrl/pinctrl-pef2256.c

Just use a glob expression:
F: drivers/pinctrl/pinctrl-pef2256-*

Yours,
Linus Walleij

Re: [PATCH v5 28/31] pinctrl: Add support for the Lantic PEF2256 pinmux

Hi Herve,

thanks for your patch!

On Tue, Sep 12, 2023 at 12:15 PM Herve Codina  wrote:

> The Lantiq PEF2256 is a framer and line interface component designed to
> fulfill all required interfacing between an analog E1/T1/J1 line and the
> digital PCM system highway/H.100 bus.
>
> This kind of component can be found in old telecommunication system.
> It was used to digital transmission of many simultaneous telephone calls
> by time-division multiplexing. Also using HDLC protocol, WAN networks
> can be reached through the framer.
>
> This pinmux support handles the pin muxing part (pins RP(A..D) and pins
> XP(A..D)) of the PEF2256.
>
> Signed-off-by: Herve Codina 
> Reviewed-by: Christophe Leroy 
> Signed-off-by: Christophe Leroy 

Nice to see this as a proper pin control driver!

>  drivers/pinctrl/pinctrl-pef2256-regs.h |  65 ++
>  drivers/pinctrl/pinctrl-pef2256.c  | 308 +

Do you really need a separate header just for some registers?
But it's a matter of taste so I'm not gonna complain if you want
it this way.

> +config PINCTRL_PEF2256
> +   tristate "Lantiq PEF2256 (FALC56) pin controller driver"
> +   depends on OF && FRAMER_PEF2256
> +   select PINMUX

select PINCONF

> +   select GENERIC_PINCONF

This brings it in implicitly but I prefer that you just select it.

> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*

I think SPDX mandates that you start the tag with C99 comments

// SPDX-License-Identifier: GPL-2.0-only

> +   /* We map 1 group <-> 1 pin */

Also known as "the qualcomm trick", but hey: it's fine.

> +static int pef2256_register_pinctrl(struct pef2256_pinctrl *pef2256)
> +{
> +   struct pinctrl_dev  *pctrl;
> +
> +   pef2256->pctrl_desc.name= dev_name(pef2256->dev);
> +   pef2256->pctrl_desc.owner   = THIS_MODULE;
> +   pef2256->pctrl_desc.pctlops = _pctlops;
> +   pef2256->pctrl_desc.pmxops  = _pmxops;
> +   if (pef2256->version == PEF2256_VERSION_1_2) {
> +   pef2256->pctrl_desc.pins  = pef2256_v12_pins;
> +   pef2256->pctrl_desc.npins = ARRAY_SIZE(pef2256_v12_pins);
> +   pef2256->functions  = pef2256_v12_functions;
> +   pef2256->nfunctions = ARRAY_SIZE(pef2256_v12_functions);
> +   } else {
> +   pef2256->pctrl_desc.pins  = pef2256_v2x_pins;
> +   pef2256->pctrl_desc.npins = ARRAY_SIZE(pef2256_v2x_pins);
> +   pef2256->functions  = pef2256_v2x_functions;
> +   pef2256->nfunctions = ARRAY_SIZE(pef2256_v2x_functions);
> +   }
> +
> +   pctrl = devm_pinctrl_register(pef2256->dev, >pctrl_desc, 
> pef2256);
> +   if (IS_ERR(pctrl)) {
> +   dev_err(pef2256->dev, "pinctrl driver registration failed\n");
> +   return PTR_ERR(pctrl);
> +   }
> +
> +   return 0;

You could use
return dev_err_probe(...);

> +   pef2256_reset_pinmux(pef2256_pinctrl);
> +   ret = pef2256_register_pinctrl(pef2256_pinctrl);
> +   if (ret)
> +   return ret;

Or you could use it down here.

With or without these changes (because they are nitpicks)
Reviewed-by: Linus Walleij 

Yours,
Linus Walleij

WARN: Interrupts were enabled early [bisected cfeb6ae8bcb9 ("maple_tree: disable mas_wr_append() when other readers are possible")]

Hi,

With pmac32_defconfig on QEMU I get the following WARN with 6.6-rc1

Bisected to cfeb6ae8bcb9 ("maple_tree: disable mas_wr_append() when 
other readers are possible")

I have absolutely no idea what it can be, do you ?

[ cut here ]
Interrupts were enabled early
WARNING: CPU: 0 PID: 0 at init/main.c:992 start_kernel+0x4d8/0x5c0
Modules linked in:
CPU: 0 PID: 0 Comm: swapper Not tainted 6.6.0-rc1 #480
Hardware name: PowerMac3,1 7400 0xc0209 PowerMac
NIP:  c0a6052c LR: c0a6052c CTR: 
REGS: c0c4dee0 TRAP: 0700   Not tainted  (6.6.0-rc1)
MSR:  00029032   CR: 24000282  XER: 2000

GPR00: c0a6052c c0c4dfa0 c0b92580 001d c0b9d128 0001 c0b9d148 
3dff
GPR08: c0ba80f0   3e00 44000282   
0199abf8
GPR16: 0199b0a0 7fde7fa4 7fc5ac0c 00bb 4100 01c690c8 c0b92014 
c09b4bcc
GPR24: c0c55220 c0ac  efff9109 efff9100 000a c0c6d000 
c0b920a0
NIP [c0a6052c] start_kernel+0x4d8/0x5c0
LR [c0a6052c] start_kernel+0x4d8/0x5c0
Call Trace:
[c0c4dfa0] [c0a6052c] start_kernel+0x4d8/0x5c0 (unreliable)
[c0c4dff0] [3540] 0x3540
Code: 480037b1 48023c05 4bab88cd 90620260 480139e9 4b657ccd 7d2000a6 
71298000 41a20014 3c60c09a 3863b788 4b5e9ccd <0fe0> 3920 
99380008 7d2000a6
---[ end trace  ]---

Christophe

Re: [PATCH v5 27/31] net: wan: framer: Add support for the Lantiq PEF2256 framer

On Tue, Sep 12, 2023 at 12:15 PM Herve Codina  wrote:

> The Lantiq PEF2256 is a framer and line interface component designed to
> fulfill all required interfacing between an analog E1/T1/J1 line and the
> digital PCM system highway/H.100 bus.
>
> Signed-off-by: Herve Codina 
> Reviewed-by: Christophe Leroy 
> Signed-off-by: Christophe Leroy 

Reviewed-by: Linus Walleij 

Yours,
Linus Walleij

[PATCH v5 31/31] net: wan: fsl_qmc_hdlc: Add framer support

Add framer support in the fsl_qmc_hdlc driver in order to be able to
signal carrier changes to the network stack based on the framer status
Also use this framer to provide information related to the E1/T1 line
interface on IF_GET_IFACE and configure the line interface according to
IF_IFACE_{E1,T1} information.

Signed-off-by: Herve Codina 
Reviewed-by: Christophe Leroy 
Signed-off-by: Christophe Leroy 
---
 drivers/net/wan/fsl_qmc_hdlc.c | 239 -
 1 file changed, 235 insertions(+), 4 deletions(-)

diff --git a/drivers/net/wan/fsl_qmc_hdlc.c b/drivers/net/wan/fsl_qmc_hdlc.c
index 24f466fa48b1..e5982766ff71 100644
--- a/drivers/net/wan/fsl_qmc_hdlc.c
+++ b/drivers/net/wan/fsl_qmc_hdlc.c
@@ -8,6 +8,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -27,6 +28,9 @@ struct qmc_hdlc {
struct device *dev;
struct qmc_chan *qmc_chan;
struct net_device *netdev;
+   struct framer *framer;
+   spinlock_t carrier_lock; /* Protect carrier detection */
+   struct notifier_block nb;
bool is_crc32;
spinlock_t tx_lock; /* Protect tx descriptors */
struct qmc_hdlc_desc tx_descs[8];
@@ -40,6 +44,195 @@ static inline struct qmc_hdlc *netdev_to_qmc_hdlc(struct 
net_device *netdev)
return dev_to_hdlc(netdev)->priv;
 }
 
+static int qmc_hdlc_framer_set_carrier(struct qmc_hdlc *qmc_hdlc)
+{
+   struct framer_status framer_status;
+   unsigned long flags;
+   int ret;
+
+   if (!qmc_hdlc->framer)
+   return 0;
+
+   spin_lock_irqsave(_hdlc->carrier_lock, flags);
+
+   ret = framer_get_status(qmc_hdlc->framer, _status);
+   if (ret) {
+   dev_err(qmc_hdlc->dev, "get framer status failed (%d)\n", ret);
+   goto end;
+   }
+   if (framer_status.link_is_on)
+   netif_carrier_on(qmc_hdlc->netdev);
+   else
+   netif_carrier_off(qmc_hdlc->netdev);
+
+end:
+   spin_unlock_irqrestore(_hdlc->carrier_lock, flags);
+   return ret;
+}
+
+static int qmc_hdlc_framer_notifier(struct notifier_block *nb, unsigned long 
action,
+   void *data)
+{
+   struct qmc_hdlc *qmc_hdlc = container_of(nb, struct qmc_hdlc, nb);
+   int ret;
+
+   if (action != FRAMER_EVENT_STATUS)
+   return NOTIFY_DONE;
+
+   ret = qmc_hdlc_framer_set_carrier(qmc_hdlc);
+   return ret ? NOTIFY_DONE : NOTIFY_OK;
+}
+
+static int qmc_hdlc_framer_start(struct qmc_hdlc *qmc_hdlc)
+{
+   struct framer_status framer_status;
+   int ret;
+
+   if (!qmc_hdlc->framer)
+   return 0;
+
+   ret = framer_power_on(qmc_hdlc->framer);
+   if (ret) {
+   dev_err(qmc_hdlc->dev, "framer power-on failed (%d)\n", ret);
+   return ret;
+   }
+
+   /* Be sure that get_status is supported */
+   ret = framer_get_status(qmc_hdlc->framer, _status);
+   if (ret) {
+   dev_err(qmc_hdlc->dev, "get framer status failed (%d)\n", ret);
+   goto framer_power_off;
+   }
+
+   qmc_hdlc->nb.notifier_call = qmc_hdlc_framer_notifier;
+   ret = framer_notifier_register(qmc_hdlc->framer, _hdlc->nb);
+   if (ret) {
+   dev_err(qmc_hdlc->dev, "framer notifier register failed 
(%d)\n", ret);
+   goto framer_power_off;
+   }
+
+   return 0;
+
+framer_power_off:
+   framer_power_off(qmc_hdlc->framer);
+   return ret;
+}
+
+static void qmc_hdlc_framer_stop(struct qmc_hdlc *qmc_hdlc)
+{
+   if (!qmc_hdlc->framer)
+   return;
+
+   framer_notifier_unregister(qmc_hdlc->framer, _hdlc->nb);
+   framer_power_off(qmc_hdlc->framer);
+}
+
+static int qmc_hdlc_framer_set_iface(struct qmc_hdlc *qmc_hdlc, int if_iface,
+const te1_settings *te1)
+{
+   struct framer_config config;
+   int ret;
+
+   if (!qmc_hdlc->framer)
+   return 0;
+
+   ret = framer_get_config(qmc_hdlc->framer, );
+   if (ret)
+   return ret;
+
+   switch (if_iface) {
+   case IF_IFACE_E1:
+   config.iface = FRAMER_IFACE_E1;
+   break;
+   case IF_IFACE_T1:
+   config.iface = FRAMER_IFACE_T1;
+   break;
+   default:
+   return -EINVAL;
+   }
+
+   switch (te1->clock_type) {
+   case CLOCK_DEFAULT:
+   /* Keep current value */
+   break;
+   case CLOCK_EXT:
+   config.clock_type = FRAMER_CLOCK_EXT;
+   break;
+   case CLOCK_INT:
+   config.clock_type = FRAMER_CLOCK_INT;
+   break;
+   default:
+   return -EINVAL;
+   }
+   config.line_clock_rate = te1->clock_rate;
+
+   return framer_set_config(qmc_hdlc->framer, );
+}
+
+static int qmc_hdlc_framer_get_iface(struct qmc_hdlc *qmc_hdlc, int *if_iface, 
te1_settings *te1)
+{
+   struct

[PATCH v5 30/31] ASoC: codecs: Add support for the framer codec

The framer codec interacts with a framer.
It allows to use some of the framer timeslots as audio channels to
transport audio data over the framer E1/T1/J1 lines.
It also reports line carrier detection events through the ALSA jack
detection feature.

Signed-off-by: Herve Codina 
Reviewed-by: Christophe Leroy 
Signed-off-by: Christophe Leroy 
---
 sound/soc/codecs/Kconfig|  15 ++
 sound/soc/codecs/Makefile   |   2 +
 sound/soc/codecs/framer-codec.c | 413 
 3 files changed, 430 insertions(+)
 create mode 100644 sound/soc/codecs/framer-codec.c

diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index f1e1dbc509f6..abb89796fd45 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -112,6 +112,7 @@ config SND_SOC_ALL_CODECS
imply SND_SOC_ES8328_I2C
imply SND_SOC_ES7134
imply SND_SOC_ES7241
+   imply SND_SOC_FRAMER
imply SND_SOC_GTM601
imply SND_SOC_HDAC_HDMI
imply SND_SOC_HDAC_HDA
@@ -1071,6 +1072,20 @@ config SND_SOC_ES8328_SPI
depends on SPI_MASTER
select SND_SOC_ES8328
 
+config SND_SOC_FRAMER
+   tristate "Framer codec"
+   depends on GENERIC_FRAMER
+   help
+ Enable support for the framer codec.
+ The framer codec uses the generic framer infrastructure to transport
+ some audio data over an analog E1/T1/J1 line.
+ This codec allows to use some of the time slots available on the TDM
+ bus on which the framer is connected to transport the audio data.
+
+ To compile this driver as a module, choose M here: the module
+ will be called snd-soc-framer.
+
+
 config SND_SOC_GTM601
tristate 'GTM601 UMTS modem audio codec'
 
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index a87e56938ce5..c6bb88cd687a 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -119,6 +119,7 @@ snd-soc-es8326-objs := es8326.o
 snd-soc-es8328-objs := es8328.o
 snd-soc-es8328-i2c-objs := es8328-i2c.o
 snd-soc-es8328-spi-objs := es8328-spi.o
+snd-soc-framer-objs := framer-codec.o
 snd-soc-gtm601-objs := gtm601.o
 snd-soc-hdac-hdmi-objs := hdac_hdmi.o
 snd-soc-hdac-hda-objs := hdac_hda.o
@@ -505,6 +506,7 @@ obj-$(CONFIG_SND_SOC_ES8326)+= snd-soc-es8326.o
 obj-$(CONFIG_SND_SOC_ES8328)   += snd-soc-es8328.o
 obj-$(CONFIG_SND_SOC_ES8328_I2C)+= snd-soc-es8328-i2c.o
 obj-$(CONFIG_SND_SOC_ES8328_SPI)+= snd-soc-es8328-spi.o
+obj-$(CONFIG_SND_SOC_FRAMER)   += snd-soc-framer.o
 obj-$(CONFIG_SND_SOC_GTM601)+= snd-soc-gtm601.o
 obj-$(CONFIG_SND_SOC_HDAC_HDMI) += snd-soc-hdac-hdmi.o
 obj-$(CONFIG_SND_SOC_HDAC_HDA) += snd-soc-hdac-hda.o
diff --git a/sound/soc/codecs/framer-codec.c b/sound/soc/codecs/framer-codec.c
new file mode 100644
index ..e5fcde9ee308
--- /dev/null
+++ b/sound/soc/codecs/framer-codec.c
@@ -0,0 +1,413 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Framer ALSA SoC driver
+//
+// Copyright 2023 CS GROUP France
+//
+// Author: Herve Codina 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define FRAMER_NB_CHANNEL  32
+#define FRAMER_JACK_MASK (SND_JACK_LINEIN | SND_JACK_LINEOUT)
+
+struct framer_codec {
+   struct framer *framer;
+   struct device *dev;
+   struct snd_soc_jack jack;
+   struct notifier_block nb;
+   struct work_struct carrier_work;
+   int max_chan_playback;
+   int max_chan_capture;
+};
+
+static int framer_dai_set_tdm_slot(struct snd_soc_dai *dai, unsigned int 
tx_mask,
+  unsigned int rx_mask, int slots, int width)
+{
+   struct framer_codec *framer = 
snd_soc_component_get_drvdata(dai->component);
+
+   switch (width) {
+   case 0:
+   /* Not set -> default 8 */
+   case 8:
+   break;
+   default:
+   dev_err(dai->dev, "tdm slot width %d not supported\n", width);
+   return -EINVAL;
+   }
+
+   framer->max_chan_playback = hweight32(tx_mask);
+   if (framer->max_chan_playback > FRAMER_NB_CHANNEL) {
+   dev_err(dai->dev, "too many tx slots defined (mask = 0x%x) 
supported max %d\n",
+   tx_mask, FRAMER_NB_CHANNEL);
+   return -EINVAL;
+   }
+
+   framer->max_chan_capture = hweight32(rx_mask);
+   if (framer->max_chan_capture > FRAMER_NB_CHANNEL) {
+   dev_err(dai->dev, "too many rx slots defined (mask = 0x%x) 
supported max %d\n",
+   rx_mask, FRAMER_NB_CHANNEL);
+   return -EINVAL;
+   }
+
+   return 0;
+}
+
+/*
+ * The constraints for format/channel is to match with the number of 8bit
+ * time-slots available.
+ */
+static int framer_dai_hw_rule_channels_by_format(struct snd_soc_dai *dai,
+struct snd_pcm_hw_params 
*params,
+unsigned

[PATCH v5 29/31] MAINTAINERS: Add the Lantiq PEF2256 driver entry

After contributing the driver, add myself as the maintainer for the
Lantiq PEF2256 driver.

Signed-off-by: Herve Codina 
Reviewed-by: Christophe Leroy 
Signed-off-by: Christophe Leroy 
---
 MAINTAINERS | 9 +
 1 file changed, 9 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 8b987f2c8633..dbc5867016bc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11876,6 +11876,15 @@ S: Maintained
 F: arch/mips/lantiq
 F: drivers/soc/lantiq
 
+LANTIQ PEF2256 DRIVER
+M: Herve Codina 
+S: Maintained
+F: Documentation/devicetree/bindings/net/lantiq,pef2256.yaml
+F: drivers/net/wan/framer/pef2256/
+F: drivers/pinctrl/pinctrl-pef2256-regs.h
+F: drivers/pinctrl/pinctrl-pef2256.c
+F: include/linux/framer/pef2256.h
+
 LASI 53c700 driver for PARISC
 M: "James E.J. Bottomley" 
 L: linux-s...@vger.kernel.org
-- 
2.41.0

[PATCH v5 28/31] pinctrl: Add support for the Lantic PEF2256 pinmux

The Lantiq PEF2256 is a framer and line interface component designed to
fulfill all required interfacing between an analog E1/T1/J1 line and the
digital PCM system highway/H.100 bus.

This kind of component can be found in old telecommunication system.
It was used to digital transmission of many simultaneous telephone calls
by time-division multiplexing. Also using HDLC protocol, WAN networks
can be reached through the framer.

This pinmux support handles the pin muxing part (pins RP(A..D) and pins
XP(A..D)) of the PEF2256.

Signed-off-by: Herve Codina 
Reviewed-by: Christophe Leroy 
Signed-off-by: Christophe Leroy 
---
 drivers/pinctrl/Kconfig|  14 ++
 drivers/pinctrl/Makefile   |   1 +
 drivers/pinctrl/pinctrl-pef2256-regs.h |  65 ++
 drivers/pinctrl/pinctrl-pef2256.c  | 308 +
 4 files changed, 388 insertions(+)
 create mode 100644 drivers/pinctrl/pinctrl-pef2256-regs.h
 create mode 100644 drivers/pinctrl/pinctrl-pef2256.c

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 7dfb7190580e..2e8687310c61 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -366,6 +366,20 @@ config PINCTRL_PALMAS
  open drain configuration for the Palmas series devices like
  TPS65913, TPS80036 etc.
 
+config PINCTRL_PEF2256
+   tristate "Lantiq PEF2256 (FALC56) pin controller driver"
+   depends on OF && FRAMER_PEF2256
+   select PINMUX
+   select GENERIC_PINCONF
+   help
+ This option enables the pin controller support for the Lantiq PEF2256
+ framer, also known as FALC56.
+
+ If unsure, say N.
+
+ To compile this driver as a module, choose M here: the
+ module will be called pinctrl-pef2256.
+
 config PINCTRL_PIC32
bool "Microchip PIC32 pin controller driver"
depends on OF
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index dd6cda270294..800c4219fcc1 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_PINCTRL_MICROCHIP_SGPIO) += 
pinctrl-microchip-sgpio.o
 obj-$(CONFIG_PINCTRL_MLXBF3)   += pinctrl-mlxbf3.o
 obj-$(CONFIG_PINCTRL_OCELOT)   += pinctrl-ocelot.o
 obj-$(CONFIG_PINCTRL_PALMAS)   += pinctrl-palmas.o
+obj-$(CONFIG_PINCTRL_PEF2256)  += pinctrl-pef2256.o
 obj-$(CONFIG_PINCTRL_PIC32)+= pinctrl-pic32.o
 obj-$(CONFIG_PINCTRL_PISTACHIO)+= pinctrl-pistachio.o
 obj-$(CONFIG_PINCTRL_RK805)+= pinctrl-rk805.o
diff --git a/drivers/pinctrl/pinctrl-pef2256-regs.h 
b/drivers/pinctrl/pinctrl-pef2256-regs.h
new file mode 100644
index ..cacc492a1623
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-pef2256-regs.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * PEF2256 pinctrl registers definition
+ *
+ * Copyright 2023 CS GROUP France
+ *
+ * Author: Herve Codina 
+ */
+#ifndef __PEF2256_PINCTRL_REGS_H__
+#define __PEF2256_PINCTRL_REGS_H__
+
+#include 
+
+/* Port Configuration 1..4 */
+#define PEF2256_PC1  0x80
+#define PEF2256_PC2  0x81
+#define PEF2256_PC3  0x82
+#define PEF2256_PC4  0x83
+#define PEF2256_12_PC_RPC_MASK   GENMASK(6, 4)
+#define PEF2256_12_PC_RPC_SYPR   FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x0)
+#define PEF2256_12_PC_RPC_RFMFIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x1)
+#define PEF2256_12_PC_RPC_RFMB   FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x2)
+#define PEF2256_12_PC_RPC_RSIGM  
FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x3)
+#define PEF2256_12_PC_RPC_RSIG   FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x4)
+#define PEF2256_12_PC_RPC_DLRFIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x5)
+#define PEF2256_12_PC_RPC_FREEZE  FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x6)
+#define PEF2256_12_PC_RPC_RFSP   FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x7)
+#define PEF2256_12_PC_XPC_MASKGENMASK(4, 0)
+#define PEF2256_12_PC_XPC_SYPX   FIELD_PREP_CONST(PEF2256_12_PC_XPC_MASK, 0x0)
+#define PEF2256_12_PC_XPC_XFMS   FIELD_PREP_CONST(PEF2256_12_PC_XPC_MASK, 0x1)
+#define PEF2256_12_PC_XPC_XSIG   FIELD_PREP_CONST(PEF2256_12_PC_XPC_MASK, 0x2)
+#define PEF2256_12_PC_XPC_TCLK   FIELD_PREP_CONST(PEF2256_12_PC_XPC_MASK, 0x3)
+#define PEF2256_12_PC_XPC_XMFB   FIELD_PREP_CONST(PEF2256_12_PC_XPC_MASK, 0x4)
+#define PEF2256_12_PC_XPC_XSIGM  
FIELD_PREP_CONST(PEF2256_12_PC_XPC_MASK, 0x5)
+#define PEF2256_12_PC_XPC_DLXFIELD_PREP_CONST(PEF2256_12_PC_XPC_MASK, 0x6)
+#define PEF2256_12_PC_XPC_XCLK   FIELD_PREP_CONST(PEF2256_12_PC_XPC_MASK, 0x7)
+#define PEF2256_12_PC_XPC_XLTFIELD_PREP_CONST(PEF2256_12_PC_XPC_MASK, 0x8)
+#define PEF2256_2X_PC_RPC_MASK   GENMASK(7, 4)
+#define PEF2256_2X_PC_RPC_SYPR   FIELD_PREP_CONST(PEF2256_2X_PC_RPC_MASK, 0x0)
+#define PEF2256_2X_PC_RPC_RFMFIELD_PREP_CONST(PEF2256_2X_PC_RPC_MASK, 0x1)
+#define PEF2256_2X_PC_RPC_RFMB   FIELD_PREP_CONST(PEF2256_2X_PC_RPC_MASK, 0x2)
+#define PEF2256_2X_PC_RPC_RSIGM

[PATCH v5 27/31] net: wan: framer: Add support for the Lantiq PEF2256 framer

The Lantiq PEF2256 is a framer and line interface component designed to
fulfill all required interfacing between an analog E1/T1/J1 line and the
digital PCM system highway/H.100 bus.

Signed-off-by: Herve Codina 
Reviewed-by: Christophe Leroy 
Signed-off-by: Christophe Leroy 
---
 drivers/net/wan/framer/Kconfig|  16 +
 drivers/net/wan/framer/Makefile   |   1 +
 drivers/net/wan/framer/pef2256/Makefile   |   8 +
 drivers/net/wan/framer/pef2256/pef2256-regs.h | 250 +
 drivers/net/wan/framer/pef2256/pef2256.c  | 880 ++
 include/linux/framer/pef2256.h|  31 +
 6 files changed, 1186 insertions(+)
 create mode 100644 drivers/net/wan/framer/pef2256/Makefile
 create mode 100644 drivers/net/wan/framer/pef2256/pef2256-regs.h
 create mode 100644 drivers/net/wan/framer/pef2256/pef2256.c
 create mode 100644 include/linux/framer/pef2256.h

diff --git a/drivers/net/wan/framer/Kconfig b/drivers/net/wan/framer/Kconfig
index 37df9a96ab42..482761d280fb 100644
--- a/drivers/net/wan/framer/Kconfig
+++ b/drivers/net/wan/framer/Kconfig
@@ -20,4 +20,20 @@ config GENERIC_FRAMER
  framework and framer users can obtain reference to the framer.
  All the users of this framework should select this config.
 
+config FRAMER_PEF2256
+   tristate "Lantiq PEF2256"
+   depends on OF
+   select GENERIC_FRAMER
+   select MFD_CORE
+   select REGMAP_MMIO
+   help
+ Enable support for the Lantiq PEF2256 (FALC56) framer.
+ The PEF2256 is a framer and line interface between analog E1/T1/J1
+ line and a digital PCM bus.
+
+ If unsure, say N.
+
+ To compile this driver as a module, choose M here: the
+ module will be called framer-pef2256.
+
 endmenu
diff --git a/drivers/net/wan/framer/Makefile b/drivers/net/wan/framer/Makefile
index 78dbd8e563d0..3403f2b14534 100644
--- a/drivers/net/wan/framer/Makefile
+++ b/drivers/net/wan/framer/Makefile
@@ -4,3 +4,4 @@
 #
 
 obj-$(CONFIG_GENERIC_FRAMER)   += framer-core.o
+obj-$(CONFIG_FRAMER_PEF2256)   += pef2256/
diff --git a/drivers/net/wan/framer/pef2256/Makefile 
b/drivers/net/wan/framer/pef2256/Makefile
new file mode 100644
index ..f4d1208dd8a4
--- /dev/null
+++ b/drivers/net/wan/framer/pef2256/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for the pef2256 driver.
+#
+
+obj-$(CONFIG_FRAMER_PEF2256)   += framer-pef2256.o
+
+framer-pef2256-objs:= pef2256.o
diff --git a/drivers/net/wan/framer/pef2256/pef2256-regs.h 
b/drivers/net/wan/framer/pef2256/pef2256-regs.h
new file mode 100644
index ..5d3183c91714
--- /dev/null
+++ b/drivers/net/wan/framer/pef2256/pef2256-regs.h
@@ -0,0 +1,250 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * PEF2256 registers definition
+ *
+ * Copyright 2023 CS GROUP France
+ *
+ * Author: Herve Codina 
+ */
+#ifndef __PEF2256_REGS_H__
+#define __PEF2256_REGS_H__
+
+#include "linux/bitfield.h"
+
+/* Command Register */
+#define PEF2256_CMDR   0x02
+#define PEF2256_CMDR_RRES  BIT(6)
+#define PEF2256_CMDR_XRES  BIT(4)
+#define PEF2256_CMDR_SRES  BIT(0)
+
+/* Interrupt Mask Register 0..5 */
+#define PEF2256_IMR0   0x14
+#define PEF2256_IMR1   0x15
+#define PEF2256_IMR2   0x16
+#define PEF2256_IMR3   0x17
+#define PEF2256_IMR4   0x18
+#define PEF2256_IMR5   0x19
+
+/* Framer Mode Register 0 */
+#define PEF2256_FMR0   0x1C
+#define PEF2256_FMR0_XC_MASK   GENMASK(7, 6)
+#define PEF2256_FMR0_XC_NRZFIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x0)
+#define PEF2256_FMR0_XC_CMIFIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x1)
+#define PEF2256_FMR0_XC_AMIFIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x2)
+#define PEF2256_FMR0_XC_HDB3   FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x3)
+#define PEF2256_FMR0_RC_MASK   GENMASK(5, 4)
+#define PEF2256_FMR0_RC_NRZFIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x0)
+#define PEF2256_FMR0_RC_CMIFIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x1)
+#define PEF2256_FMR0_RC_AMIFIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x2)
+#define PEF2256_FMR0_RC_HDB3   FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x3)
+
+/* Framer Mode Register 1 */
+#define PEF2256_FMR1   0x1D
+#define PEF2256_FMR1_XFS   BIT(3)
+#define PEF2256_FMR1_ECM   BIT(2)
+/* SSD is defined on 2 bits. The other bit is on SIC1 register */
+#define PEF2256_FMR1_SSD_MASK  GENMASK(1, 1)
+#define PEF2256_FMR1_SSD_2048  FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x0)
+#define PEF2256_FMR1_SSD_4096  FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x1)
+#define PEF2256_FMR1_SSD_8192  FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x0)
+#define PEF2256_FMR1_SSD_16384 FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x1)
+
+/* Framer Mode Register 2 */
+#define PEF2256_FMR2 0x1E
+#define PEF2256_FMR2_RFS_MASKGENMASK(7, 6)
+#define PEF2256_FMR2_RFS_DOUBLEFRAME

[PATCH v5 26/31] mfd: core: Ensure disabled devices are skipped without aborting

The loop searching for a matching device based on its compatible
string is aborted when a matching disabled device is found.
This abort prevents to add devices as soon as one disabled device
is found.

Continue searching for an other device instead of aborting on the
first disabled one fixes the issue.

Fixes: 22380b65dc70 ("mfd: mfd-core: Ensure disabled devices are ignored 
without error")
Signed-off-by: Herve Codina 
Reviewed-by: Christophe Leroy 
Signed-off-by: Christophe Leroy 
---
 drivers/mfd/mfd-core.c | 17 -
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/mfd/mfd-core.c b/drivers/mfd/mfd-core.c
index 0ed7c0d7784e..2b85509a90fc 100644
--- a/drivers/mfd/mfd-core.c
+++ b/drivers/mfd/mfd-core.c
@@ -146,6 +146,7 @@ static int mfd_add_device(struct device *parent, int id,
struct platform_device *pdev;
struct device_node *np = NULL;
struct mfd_of_node_entry *of_entry, *tmp;
+   bool disabled = false;
int ret = -ENOMEM;
int platform_id;
int r;
@@ -183,11 +184,10 @@ static int mfd_add_device(struct device *parent, int id,
if (IS_ENABLED(CONFIG_OF) && parent->of_node && cell->of_compatible) {
for_each_child_of_node(parent->of_node, np) {
if (of_device_is_compatible(np, cell->of_compatible)) {
-   /* Ignore 'disabled' devices error free */
+   /* Skip 'disabled' devices */
if (!of_device_is_available(np)) {
-   of_node_put(np);
-   ret = 0;
-   goto fail_alias;
+   disabled = true;
+   continue;
}
 
ret = mfd_match_of_node_to_dev(pdev, np, cell);
@@ -197,10 +197,17 @@ static int mfd_add_device(struct device *parent, int id,
if (ret)
goto fail_alias;
 
-   break;
+   goto match;
}
}
 
+   if (disabled) {
+   /* Ignore 'disabled' devices error free */
+   ret = 0;
+   goto fail_alias;
+   }
+
+match:
if (!pdev->dev.of_node)
pr_warn("%s: Failed to locate of_node [id: %d]\n",
cell->name, platform_id);
-- 
2.41.0

[PATCH v5 25/31] dt-bindings: net: Add the Lantiq PEF2256 E1/T1/J1 framer

The Lantiq PEF2256 is a framer and line interface component designed to
fulfill all required interfacing between an analog E1/T1/J1 line and the
digital PCM system highway/H.100 bus.

Signed-off-by: Herve Codina 
Signed-off-by: Christophe Leroy 
---
 .../bindings/net/lantiq,pef2256.yaml  | 214 ++
 1 file changed, 214 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/lantiq,pef2256.yaml

diff --git a/Documentation/devicetree/bindings/net/lantiq,pef2256.yaml 
b/Documentation/devicetree/bindings/net/lantiq,pef2256.yaml
new file mode 100644
index ..c4f21678bf6a
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/lantiq,pef2256.yaml
@@ -0,0 +1,214 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/lantiq,pef2256.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Lantiq PEF2256
+
+maintainers:
+  - Herve Codina 
+
+description:
+  The Lantiq PEF2256, also known as Infineon PEF2256 or FALC56, is a framer and
+  line interface component designed to fulfill all required interfacing between
+  an analog E1/T1/J1 line and the digital PCM system highway/H.100 bus.
+
+properties:
+  compatible:
+items:
+  - const: lantiq,pef2256
+
+  reg:
+maxItems: 1
+
+  clocks:
+items:
+  - description: Master clock
+  - description: System Clock Receive
+  - description: System Clock Transmit
+
+  clock-names:
+items:
+  - const: mclk
+  - const: sclkr
+  - const: sclkx
+
+  interrupts:
+maxItems: 1
+
+  reset-gpios:
+description:
+  GPIO used to reset the device.
+maxItems: 1
+
+  pinctrl:
+$ref: /schemas/pinctrl/pinctrl.yaml#
+additionalProperties: false
+
+patternProperties:
+  '-pins$':
+type: object
+$ref: /schemas/pinctrl/pinmux-node.yaml#
+additionalProperties: false
+
+properties:
+  pins:
+enum: [ RPA, RPB, RPC, RPD, XPA, XPB, XPC, XPD ]
+
+  function:
+enum: [ SYPR, RFM, RFMB, RSIGM, RSIG, DLR, FREEZE, RFSP, LOS,
+SYPX, XFMS, XSIG, TCLK, XMFB, XSIGM, DLX, XCLK, XLT,
+GPI, GPOH, GPOL ]
+
+required:
+  - pins
+  - function
+
+  lantiq,data-rate-bps:
+$ref: /schemas/types.yaml#/definitions/uint32
+enum: [2048000, 4096000, 8192000, 16384000]
+default: 2048000
+description:
+  Data rate (bit per seconds) on the system highway.
+
+  lantiq,clock-falling-edge:
+$ref: /schemas/types.yaml#/definitions/flag
+description:
+  Data is sent on falling edge of the clock (and received on the rising
+  edge). If 'clock-falling-edge' is not present, data is sent on the
+  rising edge (and received on the falling edge).
+
+  lantiq,channel-phase:
+$ref: /schemas/types.yaml#/definitions/uint32
+enum: [0, 1, 2, 3, 4, 5, 6, 7]
+default: 0
+description: |
+  The pef2256 delivers a full frame (32 8bit time-slots in E1 and 24 8bit
+  time-slots 8 8bit signaling in E1/J1) every 125us. This lead to a data
+  rate of 2048000 bit/s. When lantiq,data-rate-bps is more than 2048000
+  bit/s, the data (all 32 8bit) present in the frame are interleave with
+  unused time-slots. The lantiq,channel-phase property allows to set the
+  correct alignment of the interleave mechanism.
+  For instance, suppose lantiq,data-rate-bps = 8192000 (ie 4*2048000), and
+  lantiq,channel-phase = 2, the interleave schema with unused time-slots
+  (nu) and used time-slots (XX) for TSi is
+nu nu XX nu nu nu XX nu nu nu XX nu
+<-- TSi --> <- TSi+1 -> <- TSi+2 ->
+  With lantiq,data-rate-bps = 8192000, and lantiq,channel-phase = 1, the
+  interleave schema is
+nu XX nu nu nu XX nu nu nu XX nu nu
+<-- TSi --> <- TSi+1 -> <- TSi+2 ->
+  With lantiq,data-rate-bps = 4096000 (ie 2*2048000), and
+  lantiq,channel-phase = 1, the interleave schema is
+nuXXnuXXnuXX
+<-- TSi --> <- TSi+1 -> <- TSi+2 ->
+
+patternProperties:
+  '^codec(-([0-9]|[1-2][0-9]|3[0-1]))?$':
+type: object
+$ref: /schemas/sound/dai-common.yaml
+unevaluatedProperties: false
+description:
+  Codec provided by the pef2256. This codec allows to use some of the PCM
+  system highway time-slots as audio channels to transport audio data over
+  the E1/T1/J1 lines.
+  The time-slots used by the codec must be set and so, the properties
+  'dai-tdm-slot-num', 'dai-tdm-slot-width', 'dai-tdm-slot-tx-mask' and
+  'dai-tdm-slot-rx-mask' must be present in the sound card node for
+  sub-nodes that involve the codec. The codec uses 8bit time-slots.
+  'dai-tdm-tdm-slot-with' must be set to 8.
+  The tx and rx masks define the pef2256 time-slots assigned to the codec.
+
+properties:
+  compatible:
+const: lantiq,pef2256-codec
+
+

[PATCH v5 24/31] net: wan: Add framer framework support

A framer is a component in charge of an E1/T1 line interface.
Connected usually to a TDM bus, it converts TDM frames to/from E1/T1
frames. It also provides information related to the E1/T1 line.

The framer framework provides a set of APIs for the framer drivers
(framer provider) to create/destroy a framer and APIs for the framer
users (framer consumer) to obtain a reference to the framer, and
use the framer.

This basic implementation provides a framer abstraction for:
 - power on/off the framer
 - get the framer status (line state)
 - be notified on framer status changes
 - get/set the framer configuration

Signed-off-by: Herve Codina 
Reviewed-by: Christophe Leroy 
Signed-off-by: Christophe Leroy 
---
 drivers/net/wan/Kconfig|   2 +
 drivers/net/wan/Makefile   |   2 +
 drivers/net/wan/framer/Kconfig |  23 +
 drivers/net/wan/framer/Makefile|   6 +
 drivers/net/wan/framer/framer-core.c   | 887 +
 include/linux/framer/framer-provider.h | 194 ++
 include/linux/framer/framer.h  | 205 ++
 7 files changed, 1319 insertions(+)
 create mode 100644 drivers/net/wan/framer/Kconfig
 create mode 100644 drivers/net/wan/framer/Makefile
 create mode 100644 drivers/net/wan/framer/framer-core.c
 create mode 100644 include/linux/framer/framer-provider.h
 create mode 100644 include/linux/framer/framer.h

diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig
index 8de99f4b647b..31ab2136cdf1 100644
--- a/drivers/net/wan/Kconfig
+++ b/drivers/net/wan/Kconfig
@@ -95,6 +95,8 @@ config HDLC_X25
 comment "X.25/LAPB support is disabled"
depends on HDLC && (LAPB!=m || HDLC!=m) && LAPB!=y
 
+source "drivers/net/wan/framer/Kconfig"
+
 config PCI200SYN
tristate "Goramo PCI200SYN support"
depends on HDLC && PCI
diff --git a/drivers/net/wan/Makefile b/drivers/net/wan/Makefile
index f338f4830626..00e9b7ee1e01 100644
--- a/drivers/net/wan/Makefile
+++ b/drivers/net/wan/Makefile
@@ -14,6 +14,8 @@ obj-$(CONFIG_HDLC_FR) += hdlc_fr.o
 obj-$(CONFIG_HDLC_PPP) += hdlc_ppp.o
 obj-$(CONFIG_HDLC_X25) += hdlc_x25.o
 
+obj-y  += framer/
+
 obj-$(CONFIG_FARSYNC)  += farsync.o
 
 obj-$(CONFIG_LAPBETHER)+= lapbether.o
diff --git a/drivers/net/wan/framer/Kconfig b/drivers/net/wan/framer/Kconfig
new file mode 100644
index ..37df9a96ab42
--- /dev/null
+++ b/drivers/net/wan/framer/Kconfig
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# FRAMER
+#
+
+menu "Framer Subsystem"
+
+config GENERIC_FRAMER
+   bool "Framer Core"
+   help
+ Generic Framer support.
+ A framer is a component in charge of an E1/T1 line interface.
+ Connected usually to a TDM bus, it converts TDM frames to/from E1/T1
+ frames. It also provides information related to the E1/T1 line.
+ Used with HDLC, the network can be reached through the E1/T1 line.
+
+ This framework is designed to provide a generic interface for framer
+ devices present in the kernel. This layer will have the generic
+ API by which framer drivers can create framer using the framer
+ framework and framer users can obtain reference to the framer.
+ All the users of this framework should select this config.
+
+endmenu
diff --git a/drivers/net/wan/framer/Makefile b/drivers/net/wan/framer/Makefile
new file mode 100644
index ..78dbd8e563d0
--- /dev/null
+++ b/drivers/net/wan/framer/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for the framer drivers.
+#
+
+obj-$(CONFIG_GENERIC_FRAMER)   += framer-core.o
diff --git a/drivers/net/wan/framer/framer-core.c 
b/drivers/net/wan/framer/framer-core.c
new file mode 100644
index ..a8f34ba993e4
--- /dev/null
+++ b/drivers/net/wan/framer/framer-core.c
@@ -0,0 +1,887 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Generic Framer framework.
+ *
+ * Copyright 2023 CS GROUP France
+ *
+ * Author: Herve Codina 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static struct class *framer_class;
+static DEFINE_MUTEX(framer_provider_mutex);
+static LIST_HEAD(framer_provider_list);
+static DEFINE_IDA(framer_ida);
+
+#define dev_to_framer(a)   (container_of((a), struct framer, dev))
+
+int framer_pm_runtime_get(struct framer *framer)
+{
+   int ret;
+
+   if (!pm_runtime_enabled(>dev))
+   return -EOPNOTSUPP;
+
+   ret = pm_runtime_get(>dev);
+   if (ret < 0 && ret != -EINPROGRESS)
+   pm_runtime_put_noidle(>dev);
+
+   return ret;
+}
+EXPORT_SYMBOL_GPL(framer_pm_runtime_get);
+
+int framer_pm_runtime_get_sync(struct framer *framer)
+{
+   int ret;
+
+   if (!pm_runtime_enabled(>dev))
+   return -EOPNOTSUPP;
+
+   ret = pm_runtime_get_sync(>dev);
+   if (ret < 0)
+

[PATCH v5 23/31] wan: qmc_hdlc: Add runtime timeslots changes support

QMC channels support runtime timeslots changes but nothing is done at
the QMC HDLC driver to handle these changes.

Use existing IFACE ioctl in order to configure the timeslots to use.

Signed-off-by: Herve Codina 
Reviewed-by: Christophe Leroy 
Signed-off-by: Christophe Leroy 
---
 drivers/net/wan/fsl_qmc_hdlc.c | 169 -
 1 file changed, 168 insertions(+), 1 deletion(-)

diff --git a/drivers/net/wan/fsl_qmc_hdlc.c b/drivers/net/wan/fsl_qmc_hdlc.c
index 15e102547ff2..24f466fa48b1 100644
--- a/drivers/net/wan/fsl_qmc_hdlc.c
+++ b/drivers/net/wan/fsl_qmc_hdlc.c
@@ -32,6 +32,7 @@ struct qmc_hdlc {
struct qmc_hdlc_desc tx_descs[8];
unsigned int tx_out;
struct qmc_hdlc_desc rx_descs[4];
+   u32 slot_map;
 };
 
 static inline struct qmc_hdlc *netdev_to_qmc_hdlc(struct net_device *netdev)
@@ -202,6 +203,162 @@ static netdev_tx_t qmc_hdlc_xmit(struct sk_buff *skb, 
struct net_device *netdev)
return NETDEV_TX_OK;
 }
 
+static int qmc_hdlc_xlate_slot_map(struct qmc_hdlc *qmc_hdlc,
+  u32 slot_map, struct qmc_chan_ts_info 
*ts_info)
+{
+   u64 ts_mask_avail;
+   unsigned int bit;
+   unsigned int i;
+   u64 ts_mask;
+   u64 map;
+
+   /* Tx and Rx masks must be identical */
+   if (ts_info->rx_ts_mask_avail != ts_info->tx_ts_mask_avail) {
+   dev_err(qmc_hdlc->dev, "tx and rx available timeslots mismatch 
(0x%llx, 0x%llx)\n",
+   ts_info->rx_ts_mask_avail, ts_info->tx_ts_mask_avail);
+   return -EINVAL;
+   }
+
+   ts_mask_avail = ts_info->rx_ts_mask_avail;
+   ts_mask = 0;
+   map = slot_map;
+   bit = 0;
+   for (i = 0; i < 64; i++) {
+   if (ts_mask_avail & BIT_ULL(i)) {
+   if (map & BIT_ULL(bit))
+   ts_mask |= BIT_ULL(i);
+   bit++;
+   }
+   }
+
+   if (hweight64(ts_mask) != hweight64(map)) {
+   dev_err(qmc_hdlc->dev, "Cannot translate timeslots 0x%llx -> 
(0x%llx,0x%llx)\n",
+   map, ts_mask_avail, ts_mask);
+   return -EINVAL;
+   }
+
+   ts_info->tx_ts_mask = ts_mask;
+   ts_info->rx_ts_mask = ts_mask;
+   return 0;
+}
+
+static int qmc_hdlc_xlate_ts_info(struct qmc_hdlc *qmc_hdlc,
+ const struct qmc_chan_ts_info *ts_info, u32 
*slot_map)
+{
+   u64 ts_mask_avail;
+   unsigned int bit;
+   unsigned int i;
+   u64 ts_mask;
+   u64 map;
+
+   /* Tx and Rx masks must be identical */
+   if (ts_info->rx_ts_mask_avail != ts_info->tx_ts_mask_avail) {
+   dev_err(qmc_hdlc->dev, "tx and rx available timeslots mismatch 
(0x%llx, 0x%llx)\n",
+   ts_info->rx_ts_mask_avail, ts_info->tx_ts_mask_avail);
+   return -EINVAL;
+   }
+   if (ts_info->rx_ts_mask != ts_info->tx_ts_mask) {
+   dev_err(qmc_hdlc->dev, "tx and rx timeslots mismatch (0x%llx, 
0x%llx)\n",
+   ts_info->rx_ts_mask, ts_info->tx_ts_mask);
+   return -EINVAL;
+   }
+
+   ts_mask_avail = ts_info->rx_ts_mask_avail;
+   ts_mask = ts_info->rx_ts_mask;
+   map = 0;
+   bit = 0;
+   for (i = 0; i < 64; i++) {
+   if (ts_mask_avail & BIT_ULL(i)) {
+   if (ts_mask & BIT_ULL(i))
+   map |= BIT_ULL(bit);
+   bit++;
+   }
+   }
+
+   if (hweight64(ts_mask) != hweight64(map)) {
+   dev_err(qmc_hdlc->dev, "Cannot translate timeslots 
(0x%llx,0x%llx) -> 0x%llx\n",
+   ts_mask_avail, ts_mask, map);
+   return -EINVAL;
+   }
+
+   if (map >= BIT_ULL(32)) {
+   dev_err(qmc_hdlc->dev, "Slot map out of 32bit (0x%llx,0x%llx) 
-> 0x%llx\n",
+   ts_mask_avail, ts_mask, map);
+   return -EINVAL;
+   }
+
+   *slot_map = map;
+   return 0;
+}
+
+static int qmc_hdlc_set_iface(struct qmc_hdlc *qmc_hdlc, int if_iface, const 
te1_settings *te1)
+{
+   struct qmc_chan_ts_info ts_info;
+   int ret;
+
+   ret = qmc_chan_get_ts_info(qmc_hdlc->qmc_chan, _info);
+   if (ret) {
+   dev_err(qmc_hdlc->dev, "get QMC channel ts info failed %d\n", 
ret);
+   return ret;
+   }
+   ret = qmc_hdlc_xlate_slot_map(qmc_hdlc, te1->slot_map, _info);
+   if (ret)
+   return ret;
+
+   ret = qmc_chan_set_ts_info(qmc_hdlc->qmc_chan, _info);
+   if (ret) {
+   dev_err(qmc_hdlc->dev, "set QMC channel ts info failed %d\n", 
ret);
+   return ret;
+   }
+
+   qmc_hdlc->slot_map = te1->slot_map;
+
+   return 0;
+}
+
+static int qmc_hdlc_ioctl(struct net_device *netdev, struct if_settings *ifs)
+{
+   struct qmc_hdlc *qmc_hdlc = netdev_to_qmc_hdlc(netdev);
+

[PATCH v5 22/31] soc: fsl: cpm1: qmc: Introduce functions to change timeslots at runtime

Introduce qmc_chan_{get,set}_ts_info() function to allow timeslots
modification at runtime.

The modification is provided using qmc_chan_set_ts_info() and will be
applied on next qmc_chan_start().
qmc_chan_set_ts_info() must be called with the channel rx and/or tx
stopped.

Signed-off-by: Herve Codina 
Reviewed-by: Christophe Leroy 
Signed-off-by: Christophe Leroy 
---
 drivers/soc/fsl/qe/qmc.c | 51 
 include/soc/fsl/qe/qmc.h | 10 
 2 files changed, 61 insertions(+)

diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
index b63b54ec0a3a..6e22b96b4e7a 100644
--- a/drivers/soc/fsl/qe/qmc.c
+++ b/drivers/soc/fsl/qe/qmc.c
@@ -290,6 +290,57 @@ int qmc_chan_get_info(struct qmc_chan *chan, struct 
qmc_chan_info *info)
 }
 EXPORT_SYMBOL(qmc_chan_get_info);
 
+int qmc_chan_get_ts_info(struct qmc_chan *chan, struct qmc_chan_ts_info 
*ts_info)
+{
+   unsigned long flags;
+
+   spin_lock_irqsave(>ts_lock, flags);
+
+   ts_info->rx_ts_mask_avail = chan->rx_ts_mask_avail;
+   ts_info->tx_ts_mask_avail = chan->tx_ts_mask_avail;
+   ts_info->rx_ts_mask = chan->rx_ts_mask;
+   ts_info->tx_ts_mask = chan->tx_ts_mask;
+
+   spin_unlock_irqrestore(>ts_lock, flags);
+
+   return 0;
+}
+EXPORT_SYMBOL(qmc_chan_get_ts_info);
+
+int qmc_chan_set_ts_info(struct qmc_chan *chan, const struct qmc_chan_ts_info 
*ts_info)
+{
+   unsigned long flags;
+   int ret;
+
+   /* Only a subset of available timeslots is allowed */
+   if ((ts_info->rx_ts_mask & chan->rx_ts_mask_avail) != 
ts_info->rx_ts_mask)
+   return -EINVAL;
+   if ((ts_info->tx_ts_mask & chan->tx_ts_mask_avail) != 
ts_info->tx_ts_mask)
+   return -EINVAL;
+
+   /* In case of common rx/tx table, rx/tx masks must be identical */
+   if (chan->qmc->is_tsa_64rxtx) {
+   if (ts_info->rx_ts_mask != ts_info->tx_ts_mask)
+   return -EINVAL;
+   }
+
+   spin_lock_irqsave(>ts_lock, flags);
+
+   if ((chan->tx_ts_mask != ts_info->tx_ts_mask && !chan->is_tx_stopped) ||
+   (chan->rx_ts_mask != ts_info->rx_ts_mask && !chan->is_rx_stopped)) {
+   dev_err(chan->qmc->dev, "Channel rx and/or tx not stopped\n");
+   ret = -EBUSY;
+   } else {
+   chan->tx_ts_mask = ts_info->tx_ts_mask;
+   chan->rx_ts_mask = ts_info->rx_ts_mask;
+   ret = 0;
+   }
+   spin_unlock_irqrestore(>ts_lock, flags);
+
+   return ret;
+}
+EXPORT_SYMBOL(qmc_chan_set_ts_info);
+
 int qmc_chan_set_param(struct qmc_chan *chan, const struct qmc_chan_param 
*param)
 {
if (param->mode != chan->mode)
diff --git a/include/soc/fsl/qe/qmc.h b/include/soc/fsl/qe/qmc.h
index 166484bb4294..2a333fc1ea81 100644
--- a/include/soc/fsl/qe/qmc.h
+++ b/include/soc/fsl/qe/qmc.h
@@ -40,6 +40,16 @@ struct qmc_chan_info {
 
 int qmc_chan_get_info(struct qmc_chan *chan, struct qmc_chan_info *info);
 
+struct qmc_chan_ts_info {
+   u64 rx_ts_mask_avail;
+   u64 tx_ts_mask_avail;
+   u64 rx_ts_mask;
+   u64 tx_ts_mask;
+};
+
+int qmc_chan_get_ts_info(struct qmc_chan *chan, struct qmc_chan_ts_info 
*ts_info);
+int qmc_chan_set_ts_info(struct qmc_chan *chan, const struct qmc_chan_ts_info 
*ts_info);
+
 struct qmc_chan_param {
enum qmc_mode mode;
union {
-- 
2.41.0

[PATCH v5 21/31] soc: fsl: cpm1: qmc: Remove timeslots handling from setup_chan()

Timeslots setting is done at channel start() and stop().
There is no more need to do that during setup_chan().

Simply remove timeslot setting from setup_chan().

Signed-off-by: Herve Codina 
Reviewed-by: Christophe Leroy 
Signed-off-by: Christophe Leroy 
---
 drivers/soc/fsl/qe/qmc.c | 28 
 1 file changed, 28 deletions(-)

diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
index 185e6e87a83f..b63b54ec0a3a 100644
--- a/drivers/soc/fsl/qe/qmc.c
+++ b/drivers/soc/fsl/qe/qmc.c
@@ -723,30 +723,6 @@ static int qmc_chan_setup_tsa_rx(struct qmc_chan *chan, 
bool enable)
return qmc_chan_setup_tsa_32rx(chan, , enable);
 }
 
-static int qmc_chan_setup_tsa(struct qmc_chan *chan, bool enable)
-{
-   struct tsa_serial_info info;
-   int ret;
-
-   /* Retrieve info from the TSA related serial */
-   ret = tsa_serial_get_info(chan->qmc->tsa_serial, );
-   if (ret)
-   return ret;
-
-   /*
-* Setup one common 64 entries table or two 32 entries (one for Tx
-* and one for Tx) according to assigned TS numbers.
-*/
-   if (chan->qmc->is_tsa_64rxtx)
-   return qmc_chan_setup_tsa_64rxtx(chan, , enable);
-
-   ret = qmc_chan_setup_tsa_32rx(chan, , enable);
-   if (ret)
-   return ret;
-
-   return qmc_chan_setup_tsa_32tx(chan, , enable);
-}
-
 static int qmc_chan_command(struct qmc_chan *chan, u8 qmc_opcode)
 {
return cpm_command(chan->id << 2, (qmc_opcode << 4) | 0x0E);
@@ -1323,10 +1299,6 @@ static int qmc_setup_chan(struct qmc *qmc, struct 
qmc_chan *chan)
 
chan->qmc = qmc;
 
-   ret = qmc_chan_setup_tsa(chan, true);
-   if (ret)
-   return ret;
-
/* Set channel specific parameter base address */
chan->s_param = qmc->dpram + (chan->id * 64);
/* 16 bd per channel (8 rx and 8 tx) */
-- 
2.41.0

[PATCH v5 20/31] soc: fsl: cpm1: qmc: Handle timeslot entries at channel start() and stop()

In order to support runtime timeslot route changes, enable the
channel timeslot entries at channel start() and disable them at
channel stop().

Signed-off-by: Herve Codina 
Reviewed-by: Christophe Leroy 
Signed-off-by: Christophe Leroy 
---
 drivers/soc/fsl/qe/qmc.c | 175 ---
 1 file changed, 163 insertions(+), 12 deletions(-)

diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
index 19acfcded9bc..185e6e87a83f 100644
--- a/drivers/soc/fsl/qe/qmc.c
+++ b/drivers/soc/fsl/qe/qmc.c
@@ -177,6 +177,7 @@ struct qmc_chan {
struct qmc *qmc;
void __iomem *s_param;
enum qmc_mode mode;
+   spinlock_t  ts_lock; /* Protect timeslots */
u64 tx_ts_mask_avail;
u64 tx_ts_mask;
u64 rx_ts_mask_avail;
@@ -265,6 +266,7 @@ static void qmc_setbits32(void __iomem *addr, u32 set)
 int qmc_chan_get_info(struct qmc_chan *chan, struct qmc_chan_info *info)
 {
struct tsa_serial_info tsa_info;
+   unsigned long flags;
int ret;
 
/* Retrieve info from the TSA related serial */
@@ -272,6 +274,8 @@ int qmc_chan_get_info(struct qmc_chan *chan, struct 
qmc_chan_info *info)
if (ret)
return ret;
 
+   spin_lock_irqsave(>ts_lock, flags);
+
info->mode = chan->mode;
info->rx_fs_rate = tsa_info.rx_fs_rate;
info->rx_bit_rate = tsa_info.rx_bit_rate;
@@ -280,6 +284,8 @@ int qmc_chan_get_info(struct qmc_chan *chan, struct 
qmc_chan_info *info)
info->tx_bit_rate = tsa_info.tx_bit_rate;
info->nb_rx_ts = hweight64(chan->rx_ts_mask);
 
+   spin_unlock_irqrestore(>ts_lock, flags);
+
return 0;
 }
 EXPORT_SYMBOL(qmc_chan_get_info);
@@ -683,6 +689,40 @@ static int qmc_chan_setup_tsa_32tx(struct qmc_chan *chan, 
const struct tsa_seria
return 0;
 }
 
+static int qmc_chan_setup_tsa_tx(struct qmc_chan *chan, bool enable)
+{
+   struct tsa_serial_info info;
+   int ret;
+
+   /* Retrieve info from the TSA related serial */
+   ret = tsa_serial_get_info(chan->qmc->tsa_serial, );
+   if (ret)
+   return ret;
+
+   /* Setup entries */
+   if (chan->qmc->is_tsa_64rxtx)
+   return qmc_chan_setup_tsa_64rxtx(chan, , enable);
+
+   return qmc_chan_setup_tsa_32tx(chan, , enable);
+}
+
+static int qmc_chan_setup_tsa_rx(struct qmc_chan *chan, bool enable)
+{
+   struct tsa_serial_info info;
+   int ret;
+
+   /* Retrieve info from the TSA related serial */
+   ret = tsa_serial_get_info(chan->qmc->tsa_serial, );
+   if (ret)
+   return ret;
+
+   /* Setup entries */
+   if (chan->qmc->is_tsa_64rxtx)
+   return qmc_chan_setup_tsa_64rxtx(chan, , enable);
+
+   return qmc_chan_setup_tsa_32rx(chan, , enable);
+}
+
 static int qmc_chan_setup_tsa(struct qmc_chan *chan, bool enable)
 {
struct tsa_serial_info info;
@@ -719,6 +759,12 @@ static int qmc_chan_stop_rx(struct qmc_chan *chan)
 
spin_lock_irqsave(>rx_lock, flags);
 
+   if (chan->is_rx_stopped) {
+   /* The channel is already stopped -> simply return ok */
+   ret = 0;
+   goto end;
+   }
+
/* Send STOP RECEIVE command */
ret = qmc_chan_command(chan, 0x0);
if (ret) {
@@ -729,6 +775,15 @@ static int qmc_chan_stop_rx(struct qmc_chan *chan)
 
chan->is_rx_stopped = true;
 
+   if (!chan->qmc->is_tsa_64rxtx || chan->is_tx_stopped) {
+   ret = qmc_chan_setup_tsa_rx(chan, false);
+   if (ret) {
+   dev_err(chan->qmc->dev, "chan %u: Disable tsa entries 
failed (%d)\n",
+   chan->id, ret);
+   goto end;
+   }
+   }
+
 end:
spin_unlock_irqrestore(>rx_lock, flags);
return ret;
@@ -741,6 +796,12 @@ static int qmc_chan_stop_tx(struct qmc_chan *chan)
 
spin_lock_irqsave(>tx_lock, flags);
 
+   if (chan->is_tx_stopped) {
+   /* The channel is already stopped -> simply return ok */
+   ret = 0;
+   goto end;
+   }
+
/* Send STOP TRANSMIT command */
ret = qmc_chan_command(chan, 0x1);
if (ret) {
@@ -751,37 +812,82 @@ static int qmc_chan_stop_tx(struct qmc_chan *chan)
 
chan->is_tx_stopped = true;
 
+   if (!chan->qmc->is_tsa_64rxtx || chan->is_rx_stopped) {
+   ret = qmc_chan_setup_tsa_tx(chan, false);
+   if (ret) {
+   dev_err(chan->qmc->dev, "chan %u: Disable tsa entries 
failed (%d)\n",
+   chan->id, ret);
+   goto end;
+   }
+   }
+
 end:
spin_unlock_irqrestore(>tx_lock, flags);
return ret;
 }
 
+static int qmc_chan_start_rx(struct qmc_chan *chan);
+
 int qmc_chan_stop(struct qmc_chan *chan, int direction)
 {
-   int ret;
+   bool is_rx_rollback_needed = false;
+

[PATCH v5 19/31] soc: fsl: cpm1: qmc: Introduce is_tsa_64rxtx flag

In order to support runtime timeslot route changes, some operations will
be different according the routing table used (common Rx and Tx table or
one table for Rx and one for Tx).

The is_tsa_64rxtx flag is introduced to avoid extra computation to
determine the table format each time we need it.
It is set once at initialization.

Signed-off-by: Herve Codina 
Reviewed-by: Christophe Leroy 
Signed-off-by: Christophe Leroy 
---
 drivers/soc/fsl/qe/qmc.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
index eeceb81bf107..19acfcded9bc 100644
--- a/drivers/soc/fsl/qe/qmc.c
+++ b/drivers/soc/fsl/qe/qmc.c
@@ -216,6 +216,7 @@ struct qmc {
u16 __iomem *int_curr;
dma_addr_t int_dma_addr;
size_t int_size;
+   bool is_tsa_64rxtx;
struct list_head chan_head;
struct qmc_chan *chans[64];
 };
@@ -696,7 +697,7 @@ static int qmc_chan_setup_tsa(struct qmc_chan *chan, bool 
enable)
 * Setup one common 64 entries table or two 32 entries (one for Tx
 * and one for Tx) according to assigned TS numbers.
 */
-   if (info.nb_tx_ts > 32 || info.nb_rx_ts > 32)
+   if (chan->qmc->is_tsa_64rxtx)
return qmc_chan_setup_tsa_64rxtx(chan, , enable);
 
ret = qmc_chan_setup_tsa_32rx(chan, , enable);
@@ -1053,6 +1054,7 @@ static int qmc_init_tsa_64rxtx(struct qmc *qmc, const 
struct tsa_serial_info *in
 * Everything was previously checked, Tx and Rx related stuffs are
 * identical -> Used Rx related stuff to build the table
 */
+   qmc->is_tsa_64rxtx = true;
 
/* Invalidate all entries */
for (i = 0; i < 64; i++)
@@ -1081,6 +1083,7 @@ static int qmc_init_tsa_32rx_32tx(struct qmc *qmc, const 
struct tsa_serial_info
 * Use a Tx 32 entries table and a Rx 32 entries table.
 * Everything was previously checked.
 */
+   qmc->is_tsa_64rxtx = false;
 
/* Invalidate all entries */
for (i = 0; i < 32; i++) {
-- 
2.41.0

[PATCH v5 18/31] soc: fsl: cpm1: qmc: Split Tx and Rx TSA entries setup

The Tx and Rx entries for a given channel are set in one function.

In order to modify Rx entries and Tx entries independently of one other,
split this function in one for the Rx part and one for the Tx part.

Signed-off-by: Herve Codina 
Reviewed-by: Christophe Leroy 
Signed-off-by: Christophe Leroy 
---
 drivers/soc/fsl/qe/qmc.c | 49 
 1 file changed, 35 insertions(+), 14 deletions(-)

diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
index 26cd7e1ccafc..eeceb81bf107 100644
--- a/drivers/soc/fsl/qe/qmc.c
+++ b/drivers/soc/fsl/qe/qmc.c
@@ -610,14 +610,14 @@ static int qmc_chan_setup_tsa_64rxtx(struct qmc_chan 
*chan, const struct tsa_ser
return 0;
 }
 
-static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_chan *chan, const struct 
tsa_serial_info *info,
-   bool enable)
+static int qmc_chan_setup_tsa_32rx(struct qmc_chan *chan, const struct 
tsa_serial_info *info,
+  bool enable)
 {
unsigned int i;
u16 curr;
u16 val;
 
-   /* Use a Tx 32 entries table and a Rx 32 entries table */
+   /* Use a Rx 32 entries table */
 
val = QMC_TSA_VALID | QMC_TSA_MASK | QMC_TSA_CHANNEL(chan->id);
 
@@ -633,6 +633,30 @@ static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_chan 
*chan, const struct tsa_
return -EBUSY;
}
}
+
+   /* Set entries based on Rx stuff */
+   for (i = 0; i < info->nb_rx_ts; i++) {
+   if (!(chan->rx_ts_mask & (((u64)1) << i)))
+   continue;
+
+   qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2),
+~QMC_TSA_WRAP, enable ? val : 0x);
+   }
+
+   return 0;
+}
+
+static int qmc_chan_setup_tsa_32tx(struct qmc_chan *chan, const struct 
tsa_serial_info *info,
+  bool enable)
+{
+   unsigned int i;
+   u16 curr;
+   u16 val;
+
+   /* Use a Tx 32 entries table */
+
+   val = QMC_TSA_VALID | QMC_TSA_MASK | QMC_TSA_CHANNEL(chan->id);
+
/* Check entries based on Tx stuff */
for (i = 0; i < info->nb_tx_ts; i++) {
if (!(chan->tx_ts_mask & (((u64)1) << i)))
@@ -646,14 +670,6 @@ static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_chan 
*chan, const struct tsa_
}
}
 
-   /* Set entries based on Rx stuff */
-   for (i = 0; i < info->nb_rx_ts; i++) {
-   if (!(chan->rx_ts_mask & (((u64)1) << i)))
-   continue;
-
-   qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2),
-~QMC_TSA_WRAP, enable ? val : 0x);
-   }
/* Set entries based on Tx stuff */
for (i = 0; i < info->nb_tx_ts; i++) {
if (!(chan->tx_ts_mask & (((u64)1) << i)))
@@ -680,9 +696,14 @@ static int qmc_chan_setup_tsa(struct qmc_chan *chan, bool 
enable)
 * Setup one common 64 entries table or two 32 entries (one for Tx
 * and one for Tx) according to assigned TS numbers.
 */
-   return ((info.nb_tx_ts > 32) || (info.nb_rx_ts > 32)) ?
-   qmc_chan_setup_tsa_64rxtx(chan, , enable) :
-   qmc_chan_setup_tsa_32rx_32tx(chan, , enable);
+   if (info.nb_tx_ts > 32 || info.nb_rx_ts > 32)
+   return qmc_chan_setup_tsa_64rxtx(chan, , enable);
+
+   ret = qmc_chan_setup_tsa_32rx(chan, , enable);
+   if (ret)
+   return ret;
+
+   return qmc_chan_setup_tsa_32tx(chan, , enable);
 }
 
 static int qmc_chan_command(struct qmc_chan *chan, u8 qmc_opcode)
-- 
2.41.0

[PATCH v5 17/31] soc: fsl: cpm1: qmc: Add support for disabling channel TSA entries

In order to allow runtime timeslot route changes, disabling channel TSA
entries needs to be supported.

Add support for this new feature.

Signed-off-by: Herve Codina 
Reviewed-by: Christophe Leroy 
Signed-off-by: Christophe Leroy 
---
 drivers/soc/fsl/qe/qmc.c | 20 +++-
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
index 269d10cd3c7a..26cd7e1ccafc 100644
--- a/drivers/soc/fsl/qe/qmc.c
+++ b/drivers/soc/fsl/qe/qmc.c
@@ -567,7 +567,8 @@ static void qmc_chan_read_done(struct qmc_chan *chan)
spin_unlock_irqrestore(>rx_lock, flags);
 }
 
-static int qmc_chan_setup_tsa_64rxtx(struct qmc_chan *chan, const struct 
tsa_serial_info *info)
+static int qmc_chan_setup_tsa_64rxtx(struct qmc_chan *chan, const struct 
tsa_serial_info *info,
+bool enable)
 {
unsigned int i;
u16 curr;
@@ -603,13 +604,14 @@ static int qmc_chan_setup_tsa_64rxtx(struct qmc_chan 
*chan, const struct tsa_ser
continue;
 
qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2),
-~QMC_TSA_WRAP, val);
+~QMC_TSA_WRAP, enable ? val : 0x);
}
 
return 0;
 }
 
-static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_chan *chan, const struct 
tsa_serial_info *info)
+static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_chan *chan, const struct 
tsa_serial_info *info,
+   bool enable)
 {
unsigned int i;
u16 curr;
@@ -650,7 +652,7 @@ static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_chan 
*chan, const struct tsa_
continue;
 
qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2),
-~QMC_TSA_WRAP, val);
+~QMC_TSA_WRAP, enable ? val : 0x);
}
/* Set entries based on Tx stuff */
for (i = 0; i < info->nb_tx_ts; i++) {
@@ -658,13 +660,13 @@ static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_chan 
*chan, const struct tsa_
continue;
 
qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATTX + (i * 2),
-~QMC_TSA_WRAP, val);
+~QMC_TSA_WRAP, enable ? val : 0x);
}
 
return 0;
 }
 
-static int qmc_chan_setup_tsa(struct qmc_chan *chan)
+static int qmc_chan_setup_tsa(struct qmc_chan *chan, bool enable)
 {
struct tsa_serial_info info;
int ret;
@@ -679,8 +681,8 @@ static int qmc_chan_setup_tsa(struct qmc_chan *chan)
 * and one for Tx) according to assigned TS numbers.
 */
return ((info.nb_tx_ts > 32) || (info.nb_rx_ts > 32)) ?
-   qmc_chan_setup_tsa_64rxtx(chan, ) :
-   qmc_chan_setup_tsa_32rx_32tx(chan, );
+   qmc_chan_setup_tsa_64rxtx(chan, , enable) :
+   qmc_chan_setup_tsa_32rx_32tx(chan, , enable);
 }
 
 static int qmc_chan_command(struct qmc_chan *chan, u8 qmc_opcode)
@@ -1146,7 +1148,7 @@ static int qmc_setup_chan(struct qmc *qmc, struct 
qmc_chan *chan)
 
chan->qmc = qmc;
 
-   ret = qmc_chan_setup_tsa(chan);
+   ret = qmc_chan_setup_tsa(chan, true);
if (ret)
return ret;
 
-- 
2.41.0

[PATCH v5 16/31] soc: fsl: cpm1: qmc: Check available timeslots in qmc_check_chans()

The timeslots checked in qmc_check_chans() are the timeslots used.
With the introduction of the available timeslots, the used timeslots
are a subset of the available timeslots. The timeslots checked during
the qmc_check_chans() call should be the available ones.

Simply update and check the available timeslots instead of the used
timeslots in qmc_check_chans().

Signed-off-by: Herve Codina 
Reviewed-by: Christophe Leroy 
Signed-off-by: Christophe Leroy 
---
 drivers/soc/fsl/qe/qmc.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
index 1189e6076e37..269d10cd3c7a 100644
--- a/drivers/soc/fsl/qe/qmc.c
+++ b/drivers/soc/fsl/qe/qmc.c
@@ -914,13 +914,13 @@ static int qmc_check_chans(struct qmc *qmc)
rx_ts_assigned_mask = info.nb_rx_ts == 64 ? U64_MAX : (((u64)1) << 
info.nb_rx_ts) - 1;
 
list_for_each_entry(chan, >chan_head, list) {
-   if (chan->tx_ts_mask > tx_ts_assigned_mask) {
-   dev_err(qmc->dev, "chan %u uses TSA unassigned Tx 
TS\n", chan->id);
+   if (chan->tx_ts_mask_avail > tx_ts_assigned_mask) {
+   dev_err(qmc->dev, "chan %u can use TSA unassigned Tx 
TS\n", chan->id);
return -EINVAL;
}
 
-   if (chan->rx_ts_mask > rx_ts_assigned_mask) {
-   dev_err(qmc->dev, "chan %u uses TSA unassigned Rx 
TS\n", chan->id);
+   if (chan->rx_ts_mask_avail > rx_ts_assigned_mask) {
+   dev_err(qmc->dev, "chan %u can use TSA unassigned Rx 
TS\n", chan->id);
return -EINVAL;
}
}
-- 
2.41.0

[PATCH v5 15/31] soc: fsl: cpm1: qmc: Remove no more needed checks from qmc_check_chans()

The newly introduced qmc_chan_setup_tsa* functions check that the
channel entries are not already used.
These checks are also performed by qmc_check_chans() and are no more
needed.

Remove them from qmc_check_chans().

Signed-off-by: Herve Codina 
Reviewed-by: Christophe Leroy 
Signed-off-by: Christophe Leroy 
---
 drivers/soc/fsl/qe/qmc.c | 20 
 1 file changed, 20 deletions(-)

diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
index 8e8bd1942c08..1189e6076e37 100644
--- a/drivers/soc/fsl/qe/qmc.c
+++ b/drivers/soc/fsl/qe/qmc.c
@@ -884,10 +884,7 @@ EXPORT_SYMBOL(qmc_chan_reset);
 static int qmc_check_chans(struct qmc *qmc)
 {
struct tsa_serial_info info;
-   bool is_one_table = false;
struct qmc_chan *chan;
-   u64 tx_ts_mask = 0;
-   u64 rx_ts_mask = 0;
u64 tx_ts_assigned_mask;
u64 rx_ts_assigned_mask;
int ret;
@@ -911,7 +908,6 @@ static int qmc_check_chans(struct qmc *qmc)
dev_err(qmc->dev, "Number of TSA Tx/Rx TS assigned are 
not equal\n");
return -EINVAL;
}
-   is_one_table = true;
}
 
tx_ts_assigned_mask = info.nb_tx_ts == 64 ? U64_MAX : (((u64)1) << 
info.nb_tx_ts) - 1;
@@ -922,27 +918,11 @@ static int qmc_check_chans(struct qmc *qmc)
dev_err(qmc->dev, "chan %u uses TSA unassigned Tx 
TS\n", chan->id);
return -EINVAL;
}
-   if (tx_ts_mask & chan->tx_ts_mask) {
-   dev_err(qmc->dev, "chan %u uses an already used Tx 
TS\n", chan->id);
-   return -EINVAL;
-   }
 
if (chan->rx_ts_mask > rx_ts_assigned_mask) {
dev_err(qmc->dev, "chan %u uses TSA unassigned Rx 
TS\n", chan->id);
return -EINVAL;
}
-   if (rx_ts_mask & chan->rx_ts_mask) {
-   dev_err(qmc->dev, "chan %u uses an already used Rx 
TS\n", chan->id);
-   return -EINVAL;
-   }
-
-   if (is_one_table && (chan->tx_ts_mask != chan->rx_ts_mask)) {
-   dev_err(qmc->dev, "chan %u uses different Rx and Tx 
TS\n", chan->id);
-   return -EINVAL;
-   }
-
-   tx_ts_mask |= chan->tx_ts_mask;
-   rx_ts_mask |= chan->rx_ts_mask;
}
 
return 0;
-- 
2.41.0

[PATCH v5 14/31] soc: fsl: cpm1: qmc: Introduce qmc_chan_setup_tsa*

Introduce the qmc_chan_setup_tsa* functions to setup entries related
to the given channel.
Use them during QMC channels setup.

Signed-off-by: Herve Codina 
Reviewed-by: Christophe Leroy 
Signed-off-by: Christophe Leroy 
---
 drivers/soc/fsl/qe/qmc.c | 161 ++-
 1 file changed, 125 insertions(+), 36 deletions(-)

diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
index 28acf4c8a141..8e8bd1942c08 100644
--- a/drivers/soc/fsl/qe/qmc.c
+++ b/drivers/soc/fsl/qe/qmc.c
@@ -240,6 +240,11 @@ static void qmc_clrbits16(void __iomem *addr, u16 clr)
qmc_write16(addr, qmc_read16(addr) & ~clr);
 }
 
+static void qmc_clrsetbits16(void __iomem *addr, u16 clr, u16 set)
+{
+   qmc_write16(addr, (qmc_read16(addr) & ~clr) | set);
+}
+
 static void qmc_write32(void __iomem *addr, u32 val)
 {
iowrite32be(val, addr);
@@ -562,6 +567,122 @@ static void qmc_chan_read_done(struct qmc_chan *chan)
spin_unlock_irqrestore(>rx_lock, flags);
 }
 
+static int qmc_chan_setup_tsa_64rxtx(struct qmc_chan *chan, const struct 
tsa_serial_info *info)
+{
+   unsigned int i;
+   u16 curr;
+   u16 val;
+
+   /*
+* Use a common Tx/Rx 64 entries table.
+* Tx and Rx related stuffs must be identical
+*/
+   if (chan->tx_ts_mask != chan->rx_ts_mask) {
+   dev_err(chan->qmc->dev, "chan %u uses different Rx and Tx 
TS\n", chan->id);
+   return -EINVAL;
+   }
+
+   val = QMC_TSA_VALID | QMC_TSA_MASK | QMC_TSA_CHANNEL(chan->id);
+
+   /* Check entries based on Rx stuff*/
+   for (i = 0; i < info->nb_rx_ts; i++) {
+   if (!(chan->rx_ts_mask & (((u64)1) << i)))
+   continue;
+
+   curr = qmc_read16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 
2));
+   if (curr & QMC_TSA_VALID && (curr & ~QMC_TSA_WRAP) != val) {
+   dev_err(chan->qmc->dev, "chan %u TxRx entry %d already 
used\n",
+   chan->id, i);
+   return -EBUSY;
+   }
+   }
+
+   /* Set entries based on Rx stuff*/
+   for (i = 0; i < info->nb_rx_ts; i++) {
+   if (!(chan->rx_ts_mask & (((u64)1) << i)))
+   continue;
+
+   qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2),
+~QMC_TSA_WRAP, val);
+   }
+
+   return 0;
+}
+
+static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_chan *chan, const struct 
tsa_serial_info *info)
+{
+   unsigned int i;
+   u16 curr;
+   u16 val;
+
+   /* Use a Tx 32 entries table and a Rx 32 entries table */
+
+   val = QMC_TSA_VALID | QMC_TSA_MASK | QMC_TSA_CHANNEL(chan->id);
+
+   /* Check entries based on Rx stuff */
+   for (i = 0; i < info->nb_rx_ts; i++) {
+   if (!(chan->rx_ts_mask & (((u64)1) << i)))
+   continue;
+
+   curr = qmc_read16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 
2));
+   if (curr & QMC_TSA_VALID && (curr & ~QMC_TSA_WRAP) != val) {
+   dev_err(chan->qmc->dev, "chan %u Rx entry %d already 
used\n",
+   chan->id, i);
+   return -EBUSY;
+   }
+   }
+   /* Check entries based on Tx stuff */
+   for (i = 0; i < info->nb_tx_ts; i++) {
+   if (!(chan->tx_ts_mask & (((u64)1) << i)))
+   continue;
+
+   curr = qmc_read16(chan->qmc->scc_pram + QMC_GBL_TSATTX + (i * 
2));
+   if (curr & QMC_TSA_VALID && (curr & ~QMC_TSA_WRAP) != val) {
+   dev_err(chan->qmc->dev, "chan %u Tx entry %d already 
used\n",
+   chan->id, i);
+   return -EBUSY;
+   }
+   }
+
+   /* Set entries based on Rx stuff */
+   for (i = 0; i < info->nb_rx_ts; i++) {
+   if (!(chan->rx_ts_mask & (((u64)1) << i)))
+   continue;
+
+   qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2),
+~QMC_TSA_WRAP, val);
+   }
+   /* Set entries based on Tx stuff */
+   for (i = 0; i < info->nb_tx_ts; i++) {
+   if (!(chan->tx_ts_mask & (((u64)1) << i)))
+   continue;
+
+   qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATTX + (i * 2),
+~QMC_TSA_WRAP, val);
+   }
+
+   return 0;
+}
+
+static int qmc_chan_setup_tsa(struct qmc_chan *chan)
+{
+   struct tsa_serial_info info;
+   int ret;
+
+   /* Retrieve info from the TSA related serial */
+   ret = tsa_serial_get_info(chan->qmc->tsa_serial, );
+   if (ret)
+   return ret;
+
+   /*
+* Setup one common 64 entries table or two 32 entries (one for Tx
+* and one for Tx) according to assigned TS numbers.
+*/
+

[PATCH v5 13/31] soc: fsl: cpm1: qmc: Rename qmc_setup_tsa* to qmc_init_tsa*

qmc_setup_tsa* are called once at initialisation.
They initialize the QMC TSA table.
In order to introduce setup function later on for dynamic timeslots
management, rename the function to avoid later confusion.

Signed-off-by: Herve Codina 
Reviewed-by: Christophe Leroy 
Signed-off-by: Christophe Leroy 
---
 drivers/soc/fsl/qe/qmc.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
index 653d458b84b6..28acf4c8a141 100644
--- a/drivers/soc/fsl/qe/qmc.c
+++ b/drivers/soc/fsl/qe/qmc.c
@@ -919,7 +919,7 @@ static int qmc_of_parse_chans(struct qmc *qmc, struct 
device_node *np)
return qmc_check_chans(qmc);
 }
 
-static int qmc_setup_tsa_64rxtx(struct qmc *qmc, const struct tsa_serial_info 
*info)
+static int qmc_init_tsa_64rxtx(struct qmc *qmc, const struct tsa_serial_info 
*info)
 {
struct qmc_chan *chan;
unsigned int i;
@@ -961,7 +961,7 @@ static int qmc_setup_tsa_64rxtx(struct qmc *qmc, const 
struct tsa_serial_info *i
return 0;
 }
 
-static int qmc_setup_tsa_32rx_32tx(struct qmc *qmc, const struct 
tsa_serial_info *info)
+static int qmc_init_tsa_32rx_32tx(struct qmc *qmc, const struct 
tsa_serial_info *info)
 {
struct qmc_chan *chan;
unsigned int i;
@@ -1019,7 +1019,7 @@ static int qmc_setup_tsa_32rx_32tx(struct qmc *qmc, const 
struct tsa_serial_info
return 0;
 }
 
-static int qmc_setup_tsa(struct qmc *qmc)
+static int qmc_init_tsa(struct qmc *qmc)
 {
struct tsa_serial_info info;
int ret;
@@ -1030,12 +1030,12 @@ static int qmc_setup_tsa(struct qmc *qmc)
return ret;
 
/*
-* Setup one common 64 entries table or two 32 entries (one for Tx and
-* one for Tx) according to assigned TS numbers.
+* Initialize one common 64 entries table or two 32 entries (one for Tx
+* and one for Tx) according to assigned TS numbers.
 */
return ((info.nb_tx_ts > 32) || (info.nb_rx_ts > 32)) ?
-   qmc_setup_tsa_64rxtx(qmc, ) :
-   qmc_setup_tsa_32rx_32tx(qmc, );
+   qmc_init_tsa_64rxtx(qmc, ) :
+   qmc_init_tsa_32rx_32tx(qmc, );
 }
 
 static int qmc_setup_chan_trnsync(struct qmc *qmc, struct qmc_chan *chan)
@@ -1391,7 +1391,7 @@ static int qmc_probe(struct platform_device *pdev)
qmc_write32(qmc->scc_pram + QMC_GBL_C_MASK32, 0xDEBB20E3);
qmc_write16(qmc->scc_pram + QMC_GBL_C_MASK16, 0xF0B8);
 
-   ret = qmc_setup_tsa(qmc);
+   ret = qmc_init_tsa(qmc);
if (ret)
goto err_tsa_serial_disconnect;
 
-- 
2.41.0

[PATCH v5 12/31] soc: fsl: cpm1: qmc: Introduce available timeslots masks

Available timeslots masks define timeslots available for the related
channel. These timeslots are defined by the QMC binding.

Timeslots used are initialized to available timeslots but can be a
subset of available timeslots.
This prepares the dynamic timeslots management (ie. changing timeslots
at runtime).

Signed-off-by: Herve Codina 
Reviewed-by: Christophe Leroy 
Signed-off-by: Christophe Leroy 
---
 drivers/soc/fsl/qe/qmc.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
index 5da15a25600e..653d458b84b6 100644
--- a/drivers/soc/fsl/qe/qmc.c
+++ b/drivers/soc/fsl/qe/qmc.c
@@ -177,7 +177,9 @@ struct qmc_chan {
struct qmc *qmc;
void __iomem *s_param;
enum qmc_mode mode;
+   u64 tx_ts_mask_avail;
u64 tx_ts_mask;
+   u64 rx_ts_mask_avail;
u64 rx_ts_mask;
bool is_reverse_data;
 
@@ -875,7 +877,8 @@ static int qmc_of_parse_chans(struct qmc *qmc, struct 
device_node *np)
of_node_put(chan_np);
return ret;
}
-   chan->tx_ts_mask = ts_mask;
+   chan->tx_ts_mask_avail = ts_mask;
+   chan->tx_ts_mask = chan->tx_ts_mask_avail;
 
ret = of_property_read_u64(chan_np, "fsl,rx-ts-mask", _mask);
if (ret) {
@@ -884,7 +887,8 @@ static int qmc_of_parse_chans(struct qmc *qmc, struct 
device_node *np)
of_node_put(chan_np);
return ret;
}
-   chan->rx_ts_mask = ts_mask;
+   chan->rx_ts_mask_avail = ts_mask;
+   chan->rx_ts_mask = chan->rx_ts_mask_avail;
 
mode = "transparent";
ret = of_property_read_string(chan_np, "fsl,operational-mode", 
);
-- 
2.41.0

[PATCH v5 11/31] MAINTAINERS: Add the Freescale QMC HDLC driver entry

After contributing the driver, add myself as the maintainer for the
Freescale QMC HDLC driver.

Signed-off-by: Herve Codina 
Signed-off-by: Christophe Leroy 
---
 MAINTAINERS | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 90f13281d297..8b987f2c8633 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8364,6 +8364,13 @@ F:   
Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
 F: drivers/soc/fsl/qe/qmc.c
 F: include/soc/fsl/qe/qmc.h
 
+FREESCALE QUICC ENGINE QMC HDLC DRIVER
+M: Herve Codina 
+L: net...@vger.kernel.org
+L: linuxppc-dev@lists.ozlabs.org
+S: Maintained
+F: drivers/net/wan/fsl_qmc_hdlc.c
+
 FREESCALE QUICC ENGINE TSA DRIVER
 M: Herve Codina 
 L: linuxppc-dev@lists.ozlabs.org
-- 
2.41.0

[PATCH v5 10/31] net: wan: Add support for QMC HDLC

The QMC HDLC driver provides support for HDLC using the QMC (QUICC
Multichannel Controller) to transfer the HDLC data.

Signed-off-by: Herve Codina 
Reviewed-by: Christophe Leroy 
Signed-off-by: Christophe Leroy 
---
 drivers/net/wan/Kconfig|  12 +
 drivers/net/wan/Makefile   |   1 +
 drivers/net/wan/fsl_qmc_hdlc.c | 422 +
 3 files changed, 435 insertions(+)
 create mode 100644 drivers/net/wan/fsl_qmc_hdlc.c

diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig
index dcb069dde66b..8de99f4b647b 100644
--- a/drivers/net/wan/Kconfig
+++ b/drivers/net/wan/Kconfig
@@ -195,6 +195,18 @@ config FARSYNC
  To compile this driver as a module, choose M here: the
  module will be called farsync.
 
+config FSL_QMC_HDLC
+   tristate "Freescale QMC HDLC support"
+   depends on HDLC
+   depends on CPM_QMC
+   help
+ HDLC support using the Freescale QUICC Multichannel Controller (QMC).
+
+ To compile this driver as a module, choose M here: the
+ module will be called fsl_qmc_hdlc.
+
+ If unsure, say N.
+
 config FSL_UCC_HDLC
tristate "Freescale QUICC Engine HDLC support"
depends on HDLC
diff --git a/drivers/net/wan/Makefile b/drivers/net/wan/Makefile
index 5bec8fae47f8..f338f4830626 100644
--- a/drivers/net/wan/Makefile
+++ b/drivers/net/wan/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_WANXL)   += wanxl.o
 obj-$(CONFIG_PCI200SYN)+= pci200syn.o
 obj-$(CONFIG_PC300TOO) += pc300too.o
 obj-$(CONFIG_IXP4XX_HSS)   += ixp4xx_hss.o
+obj-$(CONFIG_FSL_QMC_HDLC) += fsl_qmc_hdlc.o
 obj-$(CONFIG_FSL_UCC_HDLC) += fsl_ucc_hdlc.o
 obj-$(CONFIG_SLIC_DS26522) += slic_ds26522.o
 
diff --git a/drivers/net/wan/fsl_qmc_hdlc.c b/drivers/net/wan/fsl_qmc_hdlc.c
new file mode 100644
index ..15e102547ff2
--- /dev/null
+++ b/drivers/net/wan/fsl_qmc_hdlc.c
@@ -0,0 +1,422 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Freescale QMC HDLC Device Driver
+ *
+ * Copyright 2023 CS GROUP France
+ *
+ * Author: Herve Codina 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct qmc_hdlc_desc {
+   struct net_device *netdev;
+   struct sk_buff *skb; /* NULL if the descriptor is not in use */
+   dma_addr_t dma_addr;
+   size_t dma_size;
+};
+
+struct qmc_hdlc {
+   struct device *dev;
+   struct qmc_chan *qmc_chan;
+   struct net_device *netdev;
+   bool is_crc32;
+   spinlock_t tx_lock; /* Protect tx descriptors */
+   struct qmc_hdlc_desc tx_descs[8];
+   unsigned int tx_out;
+   struct qmc_hdlc_desc rx_descs[4];
+};
+
+static inline struct qmc_hdlc *netdev_to_qmc_hdlc(struct net_device *netdev)
+{
+   return dev_to_hdlc(netdev)->priv;
+}
+
+static int qmc_hdlc_recv_queue(struct qmc_hdlc *qmc_hdlc, struct qmc_hdlc_desc 
*desc, size_t size);
+
+#define QMC_HDLC_RX_ERROR_FLAGS (QMC_RX_FLAG_HDLC_OVF | \
+QMC_RX_FLAG_HDLC_UNA | \
+QMC_RX_FLAG_HDLC_ABORT | \
+QMC_RX_FLAG_HDLC_CRC)
+
+static void qmc_hcld_recv_complete(void *context, size_t length, unsigned int 
flags)
+{
+   struct qmc_hdlc_desc *desc = context;
+   struct net_device *netdev = desc->netdev;
+   struct qmc_hdlc *qmc_hdlc = netdev_to_qmc_hdlc(desc->netdev);
+   int ret;
+
+   dma_unmap_single(qmc_hdlc->dev, desc->dma_addr, desc->dma_size, 
DMA_FROM_DEVICE);
+
+   if (flags & QMC_HDLC_RX_ERROR_FLAGS) {
+   netdev->stats.rx_errors++;
+   if (flags & QMC_RX_FLAG_HDLC_OVF) /* Data overflow */
+   netdev->stats.rx_over_errors++;
+   if (flags & QMC_RX_FLAG_HDLC_UNA) /* bits received not multiple 
of 8 */
+   netdev->stats.rx_frame_errors++;
+   if (flags & QMC_RX_FLAG_HDLC_ABORT) /* Received an abort 
sequence */
+   netdev->stats.rx_frame_errors++;
+   if (flags & QMC_RX_FLAG_HDLC_CRC) /* CRC error */
+   netdev->stats.rx_crc_errors++;
+   kfree_skb(desc->skb);
+   } else {
+   netdev->stats.rx_packets++;
+   netdev->stats.rx_bytes += length;
+
+   skb_put(desc->skb, length);
+   desc->skb->protocol = hdlc_type_trans(desc->skb, netdev);
+   netif_rx(desc->skb);
+   }
+
+   /* Re-queue a transfer using the same descriptor */
+   ret = qmc_hdlc_recv_queue(qmc_hdlc, desc, desc->dma_size);
+   if (ret) {
+   dev_err(qmc_hdlc->dev, "queue recv desc failed (%d)\n", ret);
+   netdev->stats.rx_errors++;
+   }
+}
+
+static int qmc_hdlc_recv_queue(struct qmc_hdlc *qmc_hdlc, struct qmc_hdlc_desc 
*desc, size_t size)
+{
+   int ret;
+
+   desc->skb = dev_alloc_skb(size);
+   if (!desc->skb)
+   return -ENOMEM;
+
+

[PATCH v5 09/31] soc: fsl: cpm1: qmc: Add support for child devices

QMC child devices support is needed to avoid orphan DT nodes that use a
simple DT phandle to reference a QMC channel.

Allow to instantiate child devices and also extend the API to get the
qmc_chan using a child device.

Signed-off-by: Herve Codina 
---
 drivers/soc/fsl/qe/qmc.c | 91 +++-
 include/soc/fsl/qe/qmc.h |  2 +
 2 files changed, 73 insertions(+), 20 deletions(-)

diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
index 459e0bbd723d..5da15a25600e 100644
--- a/drivers/soc/fsl/qe/qmc.c
+++ b/drivers/soc/fsl/qe/qmc.c
@@ -1425,8 +1425,16 @@ static int qmc_probe(struct platform_device *pdev)
 
platform_set_drvdata(pdev, qmc);
 
+   /* Populate channel related devices */
+   ret = devm_of_platform_populate(qmc->dev);
+   if (ret)
+   goto err_disable_txrx;
+
return 0;
 
+err_disable_txrx:
+   qmc_setbits32(qmc->scc_regs + SCC_GSMRL, 0);
+
 err_disable_intr:
qmc_write16(qmc->scc_regs + SCC_SCCM, 0);
 
@@ -1467,26 +1475,16 @@ static struct platform_driver qmc_driver = {
 };
 module_platform_driver(qmc_driver);
 
-struct qmc_chan *qmc_chan_get_byphandle(struct device_node *np, const char 
*phandle_name)
+static struct qmc_chan *qmc_chan_get_from_qmc(struct device_node *qmc_np, 
unsigned int chan_index)
 {
-   struct of_phandle_args out_args;
struct platform_device *pdev;
struct qmc_chan *qmc_chan;
struct qmc *qmc;
-   int ret;
 
-   ret = of_parse_phandle_with_fixed_args(np, phandle_name, 1, 0,
-  _args);
-   if (ret < 0)
-   return ERR_PTR(ret);
-
-   if (!of_match_node(qmc_driver.driver.of_match_table, out_args.np)) {
-   of_node_put(out_args.np);
+   if (!of_match_node(qmc_driver.driver.of_match_table, qmc_np))
return ERR_PTR(-EINVAL);
-   }
 
-   pdev = of_find_device_by_node(out_args.np);
-   of_node_put(out_args.np);
+   pdev = of_find_device_by_node(qmc_np);
if (!pdev)
return ERR_PTR(-ENODEV);
 
@@ -1496,17 +1494,12 @@ struct qmc_chan *qmc_chan_get_byphandle(struct 
device_node *np, const char *phan
return ERR_PTR(-EPROBE_DEFER);
}
 
-   if (out_args.args_count != 1) {
+   if (chan_index >= ARRAY_SIZE(qmc->chans)) {
platform_device_put(pdev);
return ERR_PTR(-EINVAL);
}
 
-   if (out_args.args[0] >= ARRAY_SIZE(qmc->chans)) {
-   platform_device_put(pdev);
-   return ERR_PTR(-EINVAL);
-   }
-
-   qmc_chan = qmc->chans[out_args.args[0]];
+   qmc_chan = qmc->chans[chan_index];
if (!qmc_chan) {
platform_device_put(pdev);
return ERR_PTR(-ENOENT);
@@ -1514,8 +1507,44 @@ struct qmc_chan *qmc_chan_get_byphandle(struct 
device_node *np, const char *phan
 
return qmc_chan;
 }
+
+struct qmc_chan *qmc_chan_get_byphandle(struct device_node *np, const char 
*phandle_name)
+{
+   struct of_phandle_args out_args;
+   struct qmc_chan *qmc_chan;
+   int ret;
+
+   ret = of_parse_phandle_with_fixed_args(np, phandle_name, 1, 0,
+  _args);
+   if (ret < 0)
+   return ERR_PTR(ret);
+
+   if (out_args.args_count != 1) {
+   of_node_put(out_args.np);
+   return ERR_PTR(-EINVAL);
+   }
+
+   qmc_chan = qmc_chan_get_from_qmc(out_args.np, out_args.args[0]);
+   of_node_put(out_args.np);
+   return qmc_chan;
+}
 EXPORT_SYMBOL(qmc_chan_get_byphandle);
 
+struct qmc_chan *qmc_chan_get_bychild(struct device_node *np)
+{
+   struct device_node *qmc_np;
+   u32 chan_index;
+   int ret;
+
+   qmc_np = np->parent;
+   ret = of_property_read_u32(np, "reg", _index);
+   if (ret)
+   return ERR_PTR(-EINVAL);
+
+   return qmc_chan_get_from_qmc(qmc_np, chan_index);
+}
+EXPORT_SYMBOL(qmc_chan_get_bychild);
+
 void qmc_chan_put(struct qmc_chan *chan)
 {
put_device(chan->qmc->dev);
@@ -1552,6 +1581,28 @@ struct qmc_chan *devm_qmc_chan_get_byphandle(struct 
device *dev,
 }
 EXPORT_SYMBOL(devm_qmc_chan_get_byphandle);
 
+struct qmc_chan *devm_qmc_chan_get_bychild(struct device *dev,
+  struct device_node *np)
+{
+   struct qmc_chan *qmc_chan;
+   struct qmc_chan **dr;
+
+   dr = devres_alloc(devm_qmc_chan_release, sizeof(*dr), GFP_KERNEL);
+   if (!dr)
+   return ERR_PTR(-ENOMEM);
+
+   qmc_chan = qmc_chan_get_bychild(np);
+   if (!IS_ERR(qmc_chan)) {
+   *dr = qmc_chan;
+   devres_add(dev, dr);
+   } else {
+   devres_free(dr);
+   }
+
+   return qmc_chan;
+}
+EXPORT_SYMBOL(devm_qmc_chan_get_bychild);
+
 MODULE_AUTHOR("Herve Codina ");
 MODULE_DESCRIPTION("CPM QMC driver");
 MODULE_LICENSE("GPL");
diff --git

[PATCH v5 08/31] dt-bindings: soc: fsl: cpm_qe: cpm1-scc-qmc: Add support for QMC HDLC

The QMC (QUICC mutichannel controller) is a controller present in some
PowerQUICC SoC such as MPC885.
The QMC HDLC uses the QMC controller to transfer HDLC data.

Additionally, a framer can be connected to the QMC HDLC.
If present, this framer is the interface between the TDM bus used by the
QMC HDLC and the E1/T1 line.
The QMC HDLC can use this framer to get information about the E1/T1 line
and configure the E1/T1 line.

Signed-off-by: Herve Codina 
---
 .../bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml   | 13 +
 1 file changed, 13 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml 
b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
index 82d9beb48e00..b5073531f3f1 100644
--- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
+++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
@@ -101,6 +101,16 @@ patternProperties:
   Channel assigned Rx time-slots within the Rx time-slots routed by the
   TSA to this cell.
 
+  compatible:
+const: fsl,qmc-hdlc
+
+  fsl,framer:
+$ref: /schemas/types.yaml#/definitions/phandle
+description:
+  phandle to the framer node. The framer is in charge of an E1/T1 line
+  interface connected to the TDM bus. It can be used to get the E1/T1 
line
+  status such as link up/down.
+
 required:
   - reg
   - fsl,tx-ts-mask
@@ -159,5 +169,8 @@ examples:
 fsl,operational-mode = "hdlc";
 fsl,tx-ts-mask = <0x 0xff00>;
 fsl,rx-ts-mask = <0x 0xff00>;
+
+compatible = "fsl,qmc-hdlc";
+fsl,framer = <>;
 };
 };
-- 
2.41.0

[PATCH v5 07/31] dt-bindings: soc: fsl: cpm_qe: cpm1-scc-qmc: Add 'additionalProperties: false' in child nodes

Additional properties in child node should not be allowed.

Prevent them adding 'additionalProperties: false'

Signed-off-by: Herve Codina 
---
 .../devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git 
a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml 
b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
index 450a0354cb1d..82d9beb48e00 100644
--- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
+++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
@@ -64,6 +64,7 @@ patternProperties:
 description:
   A channel managed by this controller
 type: object
+additionalProperties: false
 
 properties:
   reg:
-- 
2.41.0

Re: [PATCH] integrity: powerpc: Do not select CA_MACHINE_KEYRING

On Tue Sep 12, 2023 at 10:41 AM EEST, Michal Suchánek wrote:
> On Mon, Sep 11, 2023 at 11:39:38PM -0400, Nayna wrote:
> > 
> > On 9/7/23 13:32, Michal Suchánek wrote:
> > > Adding more CC's from the original patch, looks like get_maintainers is
> > > not that great for this file.
> > > 
> > > On Thu, Sep 07, 2023 at 06:52:19PM +0200, Michal Suchanek wrote:
> > > > No other platform needs CA_MACHINE_KEYRING, either.
> > > > 
> > > > This is policy that should be decided by the administrator, not Kconfig
> > > > dependencies.
> > 
> > We certainly agree that flexibility is important. However, in this case,
> > this also implies that we are expecting system admins to be security
> > experts. As per our understanding, CA based infrastructure(PKI) is the
> > standard to be followed and not the policy decision. And we can only speak
> > for Power.
> > 
> > INTEGRITY_CA_MACHINE_KEYRING ensures that we always have CA signed leaf
> > certs.
>
> And that's the problem.
>
> From a distribution point of view there are two types of leaf certs:
>
>  - leaf certs signed by the distribution CA which need not be imported
>because the distribution CA cert is enrolled one way or another
>  - user generated ad-hoc certificates that are not signed in any way,
>and enrolled by the user
>
> The latter are vouched for by the user by enrolling the certificate, and
> confirming that they really want to trust this certificate. Enrolling
> user certificates is vital for usability or secure boot. Adding extra
> step of creating a CA certificate stored on the same system only
> complicates things with no added benefit.

This all comes down to the generic fact that kernel should not
proactively define what it *expects* sysadmins.

CA based infrastructure like anything is a policy decision not
a decision to be enforced by kernel.

BR, Jarkko

[PATCH v5 06/31] dt-bindings: soc: fsl: cpm_qe: cpm1-scc-qmc: Fix example property name

The given example mentions the 'fsl,mode' property whereas the
correct property name, the one described, is 'fsl,operational-mode'.

Fix the example to use the correct property name.

Fixes: a9b121327c93 ("dt-bindings: soc: fsl: cpm_qe: Add QMC controller")
Signed-off-by: Herve Codina 
---
 .../bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml   | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git 
a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml 
b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
index ec888f48cac8..450a0354cb1d 100644
--- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
+++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml
@@ -137,7 +137,7 @@ examples:
 channel@16 {
 /* Ch16 : First 4 even TS from all routed from TSA */
 reg = <16>;
-fsl,mode = "transparent";
+fsl,operational-mode = "transparent";
 fsl,reverse-data;
 fsl,tx-ts-mask = <0x 0x00aa>;
 fsl,rx-ts-mask = <0x 0x00aa>;
@@ -146,7 +146,7 @@ examples:
 channel@17 {
 /* Ch17 : First 4 odd TS from all routed from TSA */
 reg = <17>;
-fsl,mode = "transparent";
+fsl,operational-mode = "transparent";
 fsl,reverse-data;
 fsl,tx-ts-mask = <0x 0x0055>;
 fsl,rx-ts-mask = <0x 0x0055>;
@@ -155,7 +155,7 @@ examples:
 channel@19 {
 /* Ch19 : 8 TS (TS 8..15) from all routed from TSA */
 reg = <19>;
-fsl,mode = "hdlc";
+fsl,operational-mode = "hdlc";
 fsl,tx-ts-mask = <0x 0xff00>;
 fsl,rx-ts-mask = <0x 0xff00>;
 };
-- 
2.41.0

[PATCH v5 05/31] soc: fsl: cpm1: qmc: Remove inline function specifiers

The inline function specifier is present on some functions but it is
better to let the compiler decide inlining or not these functions.

Remove inline specifiers.

Fixes: 3178d58e0b97 ("soc: fsl: cpm1: Add support for QMC")
Signed-off-by: Herve Codina 
Suggested-by: Andrew Lunn 
Reviewed-by: Christophe Leroy 
Signed-off-by: Christophe Leroy 
---
 drivers/soc/fsl/qe/qmc.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
index 2d2a9d88ba6c..459e0bbd723d 100644
--- a/drivers/soc/fsl/qe/qmc.c
+++ b/drivers/soc/fsl/qe/qmc.c
@@ -218,37 +218,37 @@ struct qmc {
struct qmc_chan *chans[64];
 };
 
-static inline void qmc_write16(void __iomem *addr, u16 val)
+static void qmc_write16(void __iomem *addr, u16 val)
 {
iowrite16be(val, addr);
 }
 
-static inline u16 qmc_read16(void __iomem *addr)
+static u16 qmc_read16(void __iomem *addr)
 {
return ioread16be(addr);
 }
 
-static inline void qmc_setbits16(void __iomem *addr, u16 set)
+static void qmc_setbits16(void __iomem *addr, u16 set)
 {
qmc_write16(addr, qmc_read16(addr) | set);
 }
 
-static inline void qmc_clrbits16(void __iomem *addr, u16 clr)
+static void qmc_clrbits16(void __iomem *addr, u16 clr)
 {
qmc_write16(addr, qmc_read16(addr) & ~clr);
 }
 
-static inline void qmc_write32(void __iomem *addr, u32 val)
+static void qmc_write32(void __iomem *addr, u32 val)
 {
iowrite32be(val, addr);
 }
 
-static inline u32 qmc_read32(void __iomem *addr)
+static u32 qmc_read32(void __iomem *addr)
 {
return ioread32be(addr);
 }
 
-static inline void qmc_setbits32(void __iomem *addr, u32 set)
+static void qmc_setbits32(void __iomem *addr, u32 set)
 {
qmc_write32(addr, qmc_read32(addr) | set);
 }
-- 
2.41.0

[PATCH v5 04/31] soc: fsl: cpm1: qmc: Extend the API to provide Rx status

In HDLC mode, some status flags related to the data read transfer can be
set by the hardware and need to be known by a QMC consumer for further
analysis.

Extend the API in order to provide these transfer status flags at the
read complete() call.

In TRANSPARENT mode, these flags have no meaning. Keep only one read
complete() API and update the consumers working in transparent mode.
In this case, the newly introduced flags parameter is simply unused.

Signed-off-by: Herve Codina 
Reviewed-by: Christophe Leroy 
Signed-off-by: Christophe Leroy 
---
 drivers/soc/fsl/qe/qmc.c  | 29 +
 include/soc/fsl/qe/qmc.h  | 15 ++-
 sound/soc/fsl/fsl_qmc_audio.c |  2 +-
 3 files changed, 40 insertions(+), 6 deletions(-)

diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
index 8dc73cc1a83b..2d2a9d88ba6c 100644
--- a/drivers/soc/fsl/qe/qmc.c
+++ b/drivers/soc/fsl/qe/qmc.c
@@ -166,7 +166,7 @@
 struct qmc_xfer_desc {
union {
void (*tx_complete)(void *context);
-   void (*rx_complete)(void *context, size_t length);
+   void (*rx_complete)(void *context, size_t length, unsigned int 
flags);
};
void *context;
 };
@@ -421,7 +421,8 @@ static void qmc_chan_write_done(struct qmc_chan *chan)
 }
 
 int qmc_chan_read_submit(struct qmc_chan *chan, dma_addr_t addr, size_t length,
-void (*complete)(void *context, size_t length), void 
*context)
+void (*complete)(void *context, size_t length, 
unsigned int flags),
+void *context)
 {
struct qmc_xfer_desc *xfer_desc;
unsigned long flags;
@@ -454,6 +455,10 @@ int qmc_chan_read_submit(struct qmc_chan *chan, dma_addr_t 
addr, size_t length,
xfer_desc->rx_complete = complete;
xfer_desc->context = context;
 
+   /* Clear previous status flags */
+   ctrl &= ~(QMC_BD_RX_L | QMC_BD_RX_F | QMC_BD_RX_LG | QMC_BD_RX_NO |
+ QMC_BD_RX_AB | QMC_BD_RX_CR);
+
/* Activate the descriptor */
ctrl |= (QMC_BD_RX_E | QMC_BD_RX_UB);
wmb(); /* Be sure to flush data before descriptor activation */
@@ -485,7 +490,7 @@ EXPORT_SYMBOL(qmc_chan_read_submit);
 
 static void qmc_chan_read_done(struct qmc_chan *chan)
 {
-   void (*complete)(void *context, size_t size);
+   void (*complete)(void *context, size_t size, unsigned int flags);
struct qmc_xfer_desc *xfer_desc;
unsigned long flags;
cbd_t __iomem *bd;
@@ -527,7 +532,23 @@ static void qmc_chan_read_done(struct qmc_chan *chan)
 
if (complete) {
spin_unlock_irqrestore(>rx_lock, flags);
-   complete(context, datalen);
+
+   /*
+* Avoid conversion between internal hardware flags and
+* the software API flags.
+* -> Be sure that the software API flags are consistent
+*with the hardware flags
+*/
+   BUILD_BUG_ON(QMC_RX_FLAG_HDLC_LAST  != QMC_BD_RX_L);
+   BUILD_BUG_ON(QMC_RX_FLAG_HDLC_FIRST != QMC_BD_RX_F);
+   BUILD_BUG_ON(QMC_RX_FLAG_HDLC_OVF   != QMC_BD_RX_LG);
+   BUILD_BUG_ON(QMC_RX_FLAG_HDLC_UNA   != QMC_BD_RX_NO);
+   BUILD_BUG_ON(QMC_RX_FLAG_HDLC_ABORT != QMC_BD_RX_AB);
+   BUILD_BUG_ON(QMC_RX_FLAG_HDLC_CRC   != QMC_BD_RX_CR);
+
+   complete(context, datalen,
+ctrl & (QMC_BD_RX_L | QMC_BD_RX_F | 
QMC_BD_RX_LG |
+QMC_BD_RX_NO | QMC_BD_RX_AB | 
QMC_BD_RX_CR));
spin_lock_irqsave(>rx_lock, flags);
}
 
diff --git a/include/soc/fsl/qe/qmc.h b/include/soc/fsl/qe/qmc.h
index 3c61a50d2ae2..6f1d6cebc9fe 100644
--- a/include/soc/fsl/qe/qmc.h
+++ b/include/soc/fsl/qe/qmc.h
@@ -9,6 +9,7 @@
 #ifndef __SOC_FSL_QMC_H__
 #define __SOC_FSL_QMC_H__
 
+#include 
 #include 
 
 struct device_node;
@@ -56,8 +57,20 @@ int qmc_chan_set_param(struct qmc_chan *chan, const struct 
qmc_chan_param *param
 int qmc_chan_write_submit(struct qmc_chan *chan, dma_addr_t addr, size_t 
length,
  void (*complete)(void *context), void *context);
 
+/* Flags available (ORed) for read complete() flags parameter in HDLC mode.
+ * No flags are available in transparent mode and the read complete() flags
+ * parameter has no meaning in transparent mode.
+ */
+#define QMC_RX_FLAG_HDLC_LAST  BIT(11) /* Last in frame */
+#define QMC_RX_FLAG_HDLC_FIRST BIT(10) /* First in frame */
+#define QMC_RX_FLAG_HDLC_OVF   BIT(5)  /* Data overflow */
+#define QMC_RX_FLAG_HDLC_UNA   BIT(4)  /* Unaligned (ie. bits received not 
multiple of 8) */
+#define QMC_RX_FLAG_HDLC_ABORT BIT(3)  /* Received an abort sequence (seven 
consecutive ones) */

Re: [PATCH v2 2/3] vmcore: allow fadump to export vmcore even if is_kdump_kernel() is false

2023-09-12 Thread Hari Bathini





On 11/09/23 4:01 pm, Baoquan He wrote:

On 09/11/23 at 05:13pm, Michael Ellerman wrote:

Hari Bathini  writes:

Currently, is_kdump_kernel() returns true when elfcorehdr_addr is set.
While elfcorehdr_addr is set for kexec based kernel dump mechanism,
alternate dump capturing methods like fadump [1] also set it to export
the vmcore. Since, is_kdump_kernel() is used to restrict resources in
crash dump capture kernel and such restrictions are not desirable for
fadump, allow is_kdump_kernel() to be defined differently for fadump
case. With that change, include is_fadump_active() check in functions
is_vmcore_usable() & vmcore_unusable() to be able to export vmcore for
fadump case too.

...

diff --git a/include/linux/crash_dump.h b/include/linux/crash_dump.h
index 0f3a656293b0..de8a9fabfb6f 100644
--- a/include/linux/crash_dump.h
+++ b/include/linux/crash_dump.h
@@ -50,6 +50,7 @@ void vmcore_cleanup(void);
  #define vmcore_elf64_check_arch(x) (elf_check_arch(x) || 
vmcore_elf_check_arch_cross(x))
  #endif
  
+#ifndef is_kdump_kernel

  /*
   * is_kdump_kernel() checks whether this kernel is booting after a panic of
   * previous kernel or not. This is determined by checking if previous kernel
@@ -64,6 +65,19 @@ static inline bool is_kdump_kernel(void)
  {
return elfcorehdr_addr != ELFCORE_ADDR_MAX;
  }
+#endif
+
+#ifndef is_fadump_active
+/*
+ * If f/w assisted dump capturing mechanism (fadump), instead of kexec based
+ * dump capturing mechanism (kdump) is exporting the vmcore, then this function
+ * will be defined in arch specific code to return true, when appropriate.
+ */
+static inline bool is_fadump_active(void)
+{
+   return false;
+}
+#endif
  
  /* is_vmcore_usable() checks if the kernel is booting after a panic and

   * the vmcore region is usable.
@@ -75,7 +89,8 @@ static inline bool is_kdump_kernel(void)
  
  static inline int is_vmcore_usable(void)

  {
-   return is_kdump_kernel() && elfcorehdr_addr != ELFCORE_ADDR_ERR ? 1 : 0;
+   return (is_kdump_kernel() || is_fadump_active())
+   && elfcorehdr_addr != ELFCORE_ADDR_ERR ? 1 : 0;
  }
  
  /* vmcore_unusable() marks the vmcore as unusable,

@@ -84,7 +99,7 @@ static inline int is_vmcore_usable(void)
  
  static inline void vmcore_unusable(void)

  {
-   if (is_kdump_kernel())
+   if (is_kdump_kernel() || is_fadump_active())
elfcorehdr_addr = ELFCORE_ADDR_ERR;
  }


I think it would be cleaner to decouple is_vmcore_usable() and
vmcore_usable() from is_kdump_kernel().

ie, make them operate solely based on the value of elforehdr_addr:

static inline int is_vmcore_usable(void)
{
elfcorehdr_addr != ELFCORE_ADDR_ERR && \
elfcorehdr_addr != ELFCORE_ADDR_MAX;


Agree. I fell into the blind corner of thinking earlier. Above change
is better.


Thanks for the reviews.
Posted v3.

- Hari

[PATCH v5 03/31] soc: fsl: cpm1: qmc: Fix rx channel reset

The qmc_chan_reset_rx() set the is_rx_stopped flag. This leads to an
inconsistent state in the following sequence.
qmc_chan_stop()
qmc_chan_reset()
Indeed, after the qmc_chan_reset() call, the channel must still be
stopped. Only a qmc_chan_start() call can move the channel from stopped
state to started state.

Fix the issue removing the is_rx_stopped flag setting from
qmc_chan_reset()

Fixes: 3178d58e0b97 ("soc: fsl: cpm1: Add support for QMC")
Signed-off-by: Herve Codina 
Reviewed-by: Christophe Leroy 
Signed-off-by: Christophe Leroy 
---
 drivers/soc/fsl/qe/qmc.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
index 7ad0d77f1740..8dc73cc1a83b 100644
--- a/drivers/soc/fsl/qe/qmc.c
+++ b/drivers/soc/fsl/qe/qmc.c
@@ -685,7 +685,6 @@ static void qmc_chan_reset_rx(struct qmc_chan *chan)
qmc_read16(chan->s_param + QMC_SPE_RBASE));
 
chan->rx_pending = 0;
-   chan->is_rx_stopped = false;
 
spin_unlock_irqrestore(>rx_lock, flags);
 }
-- 
2.41.0

[PATCH v5 02/31] soc: fsl: cpm1: qmc: Fix __iomem addresses declaration

Running sparse (make C=1) on qmc.c raises a lot of warning such as:
  ...
  warning: incorrect type in assignment (different address spaces)
 expected struct cpm_buf_desc [usertype] *[noderef] __iomem bd
 got struct cpm_buf_desc [noderef] [usertype] __iomem *txbd_free
  ...

Indeed, some variable were declared 'type *__iomem var' instead of
'type __iomem *var'.

Use the correct declaration to remove these warnings.

Fixes: 3178d58e0b97 ("soc: fsl: cpm1: Add support for QMC")
Signed-off-by: Herve Codina 
Reviewed-by: Christophe Leroy 
Signed-off-by: Christophe Leroy 
---
 drivers/soc/fsl/qe/qmc.c | 34 +-
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
index b3c292c9a14e..7ad0d77f1740 100644
--- a/drivers/soc/fsl/qe/qmc.c
+++ b/drivers/soc/fsl/qe/qmc.c
@@ -175,7 +175,7 @@ struct qmc_chan {
struct list_head list;
unsigned int id;
struct qmc *qmc;
-   void *__iomem s_param;
+   void __iomem *s_param;
enum qmc_mode mode;
u64 tx_ts_mask;
u64 rx_ts_mask;
@@ -203,9 +203,9 @@ struct qmc_chan {
 struct qmc {
struct device *dev;
struct tsa_serial *tsa_serial;
-   void *__iomem scc_regs;
-   void *__iomem scc_pram;
-   void *__iomem dpram;
+   void __iomem *scc_regs;
+   void __iomem *scc_pram;
+   void __iomem *dpram;
u16 scc_pram_offset;
cbd_t __iomem *bd_table;
dma_addr_t bd_dma_addr;
@@ -218,37 +218,37 @@ struct qmc {
struct qmc_chan *chans[64];
 };
 
-static inline void qmc_write16(void *__iomem addr, u16 val)
+static inline void qmc_write16(void __iomem *addr, u16 val)
 {
iowrite16be(val, addr);
 }
 
-static inline u16 qmc_read16(void *__iomem addr)
+static inline u16 qmc_read16(void __iomem *addr)
 {
return ioread16be(addr);
 }
 
-static inline void qmc_setbits16(void *__iomem addr, u16 set)
+static inline void qmc_setbits16(void __iomem *addr, u16 set)
 {
qmc_write16(addr, qmc_read16(addr) | set);
 }
 
-static inline void qmc_clrbits16(void *__iomem addr, u16 clr)
+static inline void qmc_clrbits16(void __iomem *addr, u16 clr)
 {
qmc_write16(addr, qmc_read16(addr) & ~clr);
 }
 
-static inline void qmc_write32(void *__iomem addr, u32 val)
+static inline void qmc_write32(void __iomem *addr, u32 val)
 {
iowrite32be(val, addr);
 }
 
-static inline u32 qmc_read32(void *__iomem addr)
+static inline u32 qmc_read32(void __iomem *addr)
 {
return ioread32be(addr);
 }
 
-static inline void qmc_setbits32(void *__iomem addr, u32 set)
+static inline void qmc_setbits32(void __iomem *addr, u32 set)
 {
qmc_write32(addr, qmc_read32(addr) | set);
 }
@@ -318,7 +318,7 @@ int qmc_chan_write_submit(struct qmc_chan *chan, dma_addr_t 
addr, size_t length,
 {
struct qmc_xfer_desc *xfer_desc;
unsigned long flags;
-   cbd_t *__iomem bd;
+   cbd_t __iomem *bd;
u16 ctrl;
int ret;
 
@@ -374,7 +374,7 @@ static void qmc_chan_write_done(struct qmc_chan *chan)
void (*complete)(void *context);
unsigned long flags;
void *context;
-   cbd_t *__iomem bd;
+   cbd_t __iomem *bd;
u16 ctrl;
 
/*
@@ -425,7 +425,7 @@ int qmc_chan_read_submit(struct qmc_chan *chan, dma_addr_t 
addr, size_t length,
 {
struct qmc_xfer_desc *xfer_desc;
unsigned long flags;
-   cbd_t *__iomem bd;
+   cbd_t __iomem *bd;
u16 ctrl;
int ret;
 
@@ -488,7 +488,7 @@ static void qmc_chan_read_done(struct qmc_chan *chan)
void (*complete)(void *context, size_t size);
struct qmc_xfer_desc *xfer_desc;
unsigned long flags;
-   cbd_t *__iomem bd;
+   cbd_t __iomem *bd;
void *context;
u16 datalen;
u16 ctrl;
@@ -663,7 +663,7 @@ static void qmc_chan_reset_rx(struct qmc_chan *chan)
 {
struct qmc_xfer_desc *xfer_desc;
unsigned long flags;
-   cbd_t *__iomem bd;
+   cbd_t __iomem *bd;
u16 ctrl;
 
spin_lock_irqsave(>rx_lock, flags);
@@ -694,7 +694,7 @@ static void qmc_chan_reset_tx(struct qmc_chan *chan)
 {
struct qmc_xfer_desc *xfer_desc;
unsigned long flags;
-   cbd_t *__iomem bd;
+   cbd_t __iomem *bd;
u16 ctrl;
 
spin_lock_irqsave(>tx_lock, flags);
-- 
2.41.0

[PATCH v5 01/31] soc: fsl: cpm1: tsa: Fix __iomem addresses declaration