[PATCH V3 2/2] powerpc/mpc85xx: Update TMU device tree node for T1023/T1024
From: Hongtao Jia <hongtao@nxp.com>
Update #thermal-sensor-cells from 0 to 1 according to the new binding. The
sensor specifier added is the monitoring site ID, and represents the "n" in
TRITSRn and TRATSRn.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
Changes for V3:
* Update the commit log to a better description.
Changes for V2:
* Rebase on latest linux-next tree (next-20161006).
arch/powerpc/boot/dts/fsl/t1023si-post.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
index 6e0b489..bce762a 100644
--- a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
@@ -321,7 +321,7 @@
0x00030001 0x000d
0x00030002 0x0019
0x00030003 0x0024>;
- #thermal-sensor-cells = <0>;
+ #thermal-sensor-cells = <1>;
};
thermal-zones {
@@ -329,7 +329,7 @@
polling-delay-passive = <1000>;
polling-delay = <5000>;
- thermal-sensors = <>;
+ thermal-sensors = < 0>;
trips {
cpu_alert: cpu-alert {
--
2.1.0.27.g96db324
[PATCH V3 1/2] powerpc/mpc85xx: Update TMU device tree node for T1040/T1042
From: Hongtao Jia <hongtao@nxp.com>
Update #thermal-sensor-cells from 0 to 1 according to the new binding. The
sensor specifier added is the monitoring site ID, and represents the "n" in
TRITSRn and TRATSRn.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
Changes for V3:
* Update the commit log to a better description.
Changes for V2:
* Rebase on latest linux-next tree (next-20161006).
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
index 44e399b..145c7f4 100644
--- a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -526,7 +526,7 @@
0x0003 0x0012
0x00030001 0x001d>;
- #thermal-sensor-cells = <0>;
+ #thermal-sensor-cells = <1>;
};
thermal-zones {
@@ -534,7 +534,7 @@
polling-delay-passive = <1000>;
polling-delay = <5000>;
- thermal-sensors = <>;
+ thermal-sensors = < 2>;
trips {
cpu_alert: cpu-alert {
--
2.1.0.27.g96db324
[PATCH V2 5/5] arm64:dt:ls2080a: Add TMU device tree support for LS2080A
From: Hongtao Jia <hongtao@nxp.com>
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
Changes for V2:
* Rebase on latest linux-next tree (next-20161006).
arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 116 +++--
4 files changed, 111 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
index b0dd010..8bc1f8f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
@@ -46,7 +46,7 @@
/dts-v1/;
-/include/ "fsl-ls2080a.dtsi"
+#include "fsl-ls2080a.dtsi"
/ {
model = "Freescale Layerscape 2080a QDS Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
index ad0ebb8..265e0a8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
@@ -46,7 +46,7 @@
/dts-v1/;
-/include/ "fsl-ls2080a.dtsi"
+#include "fsl-ls2080a.dtsi"
/ {
model = "Freescale Layerscape 2080a RDB Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
index 505d038..290604b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
@@ -46,7 +46,7 @@
/dts-v1/;
-/include/ "fsl-ls2080a.dtsi"
+#include "fsl-ls2080a.dtsi"
/ {
model = "Freescale Layerscape 2080a software Simulator model";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 337da90..723185e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -44,6 +44,8 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
+#include
+
/ {
compatible = "fsl,ls2080a";
interrupt-parent = <>;
@@ -62,15 +64,16 @@
*/
/* We have 4 clusters having 2 Cortex-A57 cores each */
- cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0>;
clocks = < 1 0>;
next-level-cache = <_l2>;
+ #cooling-cells = <2>;
};
- cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x1>;
@@ -78,15 +81,16 @@
next-level-cache = <_l2>;
};
- cpu@100 {
+ cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x100>;
clocks = < 1 1>;
next-level-cache = <_l2>;
+ #cooling-cells = <2>;
};
- cpu@101 {
+ cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x101>;
@@ -94,15 +98,16 @@
next-level-cache = <_l2>;
};
- cpu@200 {
+ cpu4: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x200>;
clocks = < 1 2>;
next-level-cache = <_l2>;
+ #cooling-cells = <2>;
};
- cpu@201 {
+ cpu5: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x201>;
@@ -110,15 +115,16 @@
next-level-cache = <_l2>;
};
- cpu@300 {
+ cpu6: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x300>;
clocks = < 1 3>;
next-level-cache = <_l2>;
+ #cooling-cells = <2>;
};
- cpu@
[PATCH V2 4/5] arm64:dt:ls1043a: Add TMU device tree support for LS1043A
From: Hongtao Jia <hongtao@nxp.com>
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
Changes for V2:
* Rebase on latest linux-next tree (next-20161006).
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi| 78 +++
3 files changed, 80 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
index dd9e919..0989d63 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
@@ -45,7 +45,7 @@
*/
/dts-v1/;
-/include/ "fsl-ls1043a.dtsi"
+#include "fsl-ls1043a.dtsi"
/ {
model = "LS1043A QDS Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
index d2313e0..c37110b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
@@ -45,7 +45,7 @@
*/
/dts-v1/;
-/include/ "fsl-ls1043a.dtsi"
+#include "fsl-ls1043a.dtsi"
/ {
model = "LS1043A RDB Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 220ac70..41e5dc1 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -44,6 +44,8 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
+#include
+
/ {
compatible = "fsl,ls1043a";
interrupt-parent = <>;
@@ -66,6 +68,7 @@
reg = <0x0>;
clocks = < 1 0>;
next-level-cache = <>;
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
@@ -254,6 +257,81 @@
big-endian;
};
+ tmu: tmu@1f0 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f0 0x0 0x1>;
+ interrupts = <0 33 0x4>;
+ fsl,tmu-range = <0xb 0x9002a 0x6004c 0x30062>;
+ fsl,tmu-calibration = <0x 0x0026
+ 0x0001 0x002d
+ 0x0002 0x0032
+ 0x0003 0x0039
+ 0x0004 0x003f
+ 0x0005 0x0046
+ 0x0006 0x004d
+ 0x0007 0x0054
+ 0x0008 0x005a
+ 0x0009 0x0061
+ 0x000a 0x006a
+ 0x000b 0x0071
+
+ 0x0001 0x0025
+ 0x00010001 0x002c
+ 0x00010002 0x0035
+ 0x00010003 0x003d
+ 0x00010004 0x0045
+ 0x00010005 0x004e
+ 0x00010006 0x0057
+ 0x00010007 0x0061
+ 0x00010008 0x006b
+ 0x00010009 0x0076
+
+ 0x0002 0x0029
+ 0x00020001 0x0033
+ 0x00020002 0x003d
+ 0x00020003 0x0049
+ 0x00020004 0x0056
+ 0x00020005 0x0061
+ 0x00020006 0x006d
+
+ 0x0003 0x0021
+ 0x00030001 0x002a
+ 0x00030002 0x003c
+ 0x00030003 0x004e>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000&g
[PATCH V2 3/5] arm:dt:ls1021a: Add TMU device tree support for LS1021A
From: Hongtao Jia <hongtao@nxp.com>
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
Changes for V2:
* Rebase on latest linux-next tree (next-20161006).
arch/arm/boot/dts/ls1021a.dtsi | 84 +-
1 file changed, 82 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 368e219..282d854 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -47,6 +47,7 @@
#include "skeleton64.dtsi"
#include
+#include
/ {
compatible = "fsl,ls1021a";
@@ -70,14 +71,15 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu@f00 {
+ cpu0: cpu@f00 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf00>;
clocks = <_clk>;
+ #cooling-cells = <2>;
};
- cpu@f01 {
+ cpu1: cpu@f01 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf01>;
@@ -251,6 +253,84 @@
};
};
+ tmu: tmu@1f0 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f0 0x0 0x1>;
+ interrupts = ;
+ fsl,tmu-range = <0xb 0xa0026 0x80048 0x30061>;
+ fsl,tmu-calibration = <0x 0x000f
+ 0x0001 0x0017
+ 0x0002 0x001e
+ 0x0003 0x0026
+ 0x0004 0x002e
+ 0x0005 0x0035
+ 0x0006 0x003d
+ 0x0007 0x0044
+ 0x0008 0x004c
+ 0x0009 0x0053
+ 0x000a 0x005b
+ 0x000b 0x0064
+
+ 0x0001 0x0011
+ 0x00010001 0x001c
+ 0x00010002 0x0024
+ 0x00010003 0x002b
+ 0x00010004 0x0034
+ 0x00010005 0x0039
+ 0x00010006 0x0042
+ 0x00010007 0x004c
+ 0x00010008 0x0051
+ 0x00010009 0x005a
+ 0x0001000a 0x0063
+
+ 0x0002 0x0013
+ 0x00020001 0x0019
+ 0x00020002 0x0024
+ 0x00020003 0x002c
+ 0x00020004 0x0035
+ 0x00020005 0x003d
+ 0x00020006 0x0046
+ 0x00020007 0x0050
+ 0x00020008 0x0059
+
+ 0x0003 0x0002
+ 0x00030001 0x000d
+ 0x00030002 0x0019
+ 0x00030003 0x0024>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = < 0>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
[PATCH V2 2/5] powerpc/mpc85xx: Update TMU device tree node for T1023/T1024
From: Hongtao Jia <hongtao@nxp.com>
SoC compatible string and endianness property are added according to the
new bindings.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
Changes for V2:
* Rebase on latest linux-next tree (next-20161006).
arch/powerpc/boot/dts/fsl/t1023si-post.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
index 6e0b489..bce762a 100644
--- a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
@@ -321,7 +321,7 @@
0x00030001 0x000d
0x00030002 0x0019
0x00030003 0x0024>;
- #thermal-sensor-cells = <0>;
+ #thermal-sensor-cells = <1>;
};
thermal-zones {
@@ -329,7 +329,7 @@
polling-delay-passive = <1000>;
polling-delay = <5000>;
- thermal-sensors = <>;
+ thermal-sensors = < 0>;
trips {
cpu_alert: cpu-alert {
--
2.1.0.27.g96db324
[PATCH V2 1/5] powerpc/mpc85xx: Update TMU device tree node for T1040/T1042
From: Hongtao Jia <hongtao@nxp.com>
SoC compatible string and endianness property are added according to the
new bindings.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
Changes for V2:
* Rebase on latest linux-next tree (next-20161006).
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
index 44e399b..145c7f4 100644
--- a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -526,7 +526,7 @@
0x0003 0x0012
0x00030001 0x001d>;
- #thermal-sensor-cells = <0>;
+ #thermal-sensor-cells = <1>;
};
thermal-zones {
@@ -534,7 +534,7 @@
polling-delay-passive = <1000>;
polling-delay = <5000>;
- thermal-sensors = <>;
+ thermal-sensors = < 2>;
trips {
cpu_alert: cpu-alert {
--
2.1.0.27.g96db324
[PATCH V2 7/7] thermal: qoriq: Add thermal management support
This driver add thermal management support by enabling TMU (Thermal
Monitoring Unit) on QorIQ platform.
It's based on thermal of framework:
- Trip points defined in device tree.
- Cpufreq as cooling device registered in qoriq cpufreq driver.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
Changes of V2:
* Add HAS_IOMEM dependency to fix build error on UM
drivers/thermal/Kconfig | 10 ++
drivers/thermal/Makefile| 1 +
drivers/thermal/qoriq_thermal.c | 328
3 files changed, 339 insertions(+)
create mode 100644 drivers/thermal/qoriq_thermal.c
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 2d702ca..56ef30d 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -195,6 +195,16 @@ config IMX_THERMAL
cpufreq is used as the cooling device to throttle CPUs when the
passive trip is crossed.
+config QORIQ_THERMAL
+ tristate "QorIQ Thermal Monitoring Unit"
+ depends on THERMAL_OF
+ depends on HAS_IOMEM
+ help
+ Support for Thermal Monitoring Unit (TMU) found on QorIQ platforms.
+ It supports one critical trip point and one passive trip point. The
+ cpufreq is used as the cooling device to throttle CPUs when the
+ passive trip is crossed.
+
config SPEAR_THERMAL
tristate "SPEAr thermal sensor driver"
depends on PLAT_SPEAR || COMPILE_TEST
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index 10b07c1..6662232 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_DB8500_THERMAL) += db8500_thermal.o
obj-$(CONFIG_ARMADA_THERMAL) += armada_thermal.o
obj-$(CONFIG_TANGO_THERMAL)+= tango_thermal.o
obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
+obj-$(CONFIG_QORIQ_THERMAL)+= qoriq_thermal.o
obj-$(CONFIG_DB8500_CPUFREQ_COOLING) += db8500_cpufreq_cooling.o
obj-$(CONFIG_INTEL_POWERCLAMP) += intel_powerclamp.o
obj-$(CONFIG_X86_PKG_TEMP_THERMAL) += x86_pkg_temp_thermal.o
diff --git a/drivers/thermal/qoriq_thermal.c b/drivers/thermal/qoriq_thermal.c
new file mode 100644
index 000..644ba52
--- /dev/null
+++ b/drivers/thermal/qoriq_thermal.c
@@ -0,0 +1,328 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "thermal_core.h"
+
+#define SITES_MAX 16
+
+/*
+ * QorIQ TMU Registers
+ */
+struct qoriq_tmu_site_regs {
+ u32 tritsr; /* Immediate Temperature Site Register */
+ u32 tratsr; /* Average Temperature Site Register */
+ u8 res0[0x8];
+};
+
+struct qoriq_tmu_regs {
+ u32 tmr;/* Mode Register */
+#define TMR_DISABLE0x0
+#define TMR_ME 0x8000
+#define TMR_ALPF 0x0c00
+ u32 tsr;/* Status Register */
+ u32 tmtmir; /* Temperature measurement interval Register */
+#define TMTMIR_DEFAULT 0x000f
+ u8 res0[0x14];
+ u32 tier; /* Interrupt Enable Register */
+#define TIER_DISABLE 0x0
+ u32 tidr; /* Interrupt Detect Register */
+ u32 tiscr; /* Interrupt Site Capture Register */
+ u32 ticscr; /* Interrupt Critical Site Capture Register */
+ u8 res1[0x10];
+ u32 tmhtcrh;/* High Temperature Capture Register */
+ u32 tmhtcrl;/* Low Temperature Capture Register */
+ u8 res2[0x8];
+ u32 tmhtitr;/* High Temperature Immediate Threshold */
+ u32 tmhtatr;/* High Temperature Average Threshold */
+ u32 tmhtactr; /* High Temperature Average Crit Threshold */
+ u8 res3[0x24];
+ u32 ttcfgr; /* Temperature Configuration Register */
+ u32 tscfgr; /* Sensor Configuration Register */
+ u8 res4[0x78];
+ struct qoriq_tmu_site_regs site[SITES_MAX];
+ u8 res5[0x9f8];
+ u32 ipbrr0; /* IP Block Revision Register 0 */
+ u32 ipbrr1; /* IP Block Revision Register 1 */
+ u8 res6[0x310];
+ u32 ttr0cr; /* Temperature Range 0 Control Register */
+ u32 ttr1cr; /* Temperature Range 1 Control Register */
+ u32 ttr2cr; /* Temperature Range 2 Control Register */
+ u32 ttr3cr; /* Temperature Range 3 Control Register */
+};
+
+/
[PATCH V2 1/7] dt-bindings: Update QorIQ TMU thermal bindings
For different types of SoC the sensor id and endianness may vary.
"#thermal-sensor-cells" is used to provide sensor id information.
"little-endian" property is to tell the endianness of TMU.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
Changes for V2:
* Remove formatting chnages.
Documentation/devicetree/bindings/thermal/qoriq-thermal.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
index 66223d5..20ca4ef 100644
--- a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
@@ -17,6 +17,12 @@ Required properties:
calibration data, as specified by the SoC reference manual.
The first cell of each pair is the value to be written to TTCFGR,
and the second is the value to be written to TSCFGR.
+- #thermal-sensor-cells : Must be 1. The sensor specifier is the monitoring
+ site ID, and represents the "n" in TRITSRn and TRATSRn.
+
+Optional property:
+- little-endian : If present, the TMU registers are little endian. If absent,
+ the default is big endian.
Example:
@@ -60,4 +66,5 @@ tmu@f {
0x0003 0x0012
0x00030001 0x001d>;
+ #thermal-sensor-cells = <1>;
};
--
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[PATCH 2/7] powerpc/mpc85xx: Update TMU device tree node for T1040/T1042
SoC compatible string and endianness property are added according to the
new bindings.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
index 507649e..089eb56 100644
--- a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -526,7 +526,7 @@
0x0003 0x0012
0x00030001 0x001d>;
- #thermal-sensor-cells = <0>;
+ #thermal-sensor-cells = <1>;
};
thermal-zones {
@@ -534,7 +534,7 @@
polling-delay-passive = <1000>;
polling-delay = <5000>;
- thermal-sensors = <>;
+ thermal-sensors = < 2>;
trips {
cpu_alert: cpu-alert {
--
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[PATCH 5/7] arm64:dt:ls1043a: Add TMU device tree support for LS1043A
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi| 78 +++
3 files changed, 80 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
index 9d3e9fe..fa447b6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
@@ -45,7 +45,7 @@
*/
/dts-v1/;
-/include/ "fsl-ls1043a.dtsi"
+#include "fsl-ls1043a.dtsi"
/ {
model = "LS1043A QDS Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
index f895fc0..6015d88 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
@@ -45,7 +45,7 @@
*/
/dts-v1/;
-/include/ "fsl-ls1043a.dtsi"
+#include "fsl-ls1043a.dtsi"
/ {
model = "LS1043A RDB Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index de0323b..4004273 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -44,6 +44,8 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
+#include
+
/ {
compatible = "fsl,ls1043a";
interrupt-parent = <>;
@@ -65,6 +67,7 @@
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
clocks = < 1 0>;
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
@@ -196,6 +199,81 @@
bus-width = <4>;
};
+ tmu: tmu@1f0 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f0 0x0 0x1>;
+ interrupts = <0 33 0x4>;
+ fsl,tmu-range = <0xb 0x9002a 0x6004c 0x30062>;
+ fsl,tmu-calibration = <0x 0x0026
+ 0x0001 0x002d
+ 0x0002 0x0032
+ 0x0003 0x0039
+ 0x0004 0x003f
+ 0x0005 0x0046
+ 0x0006 0x004d
+ 0x0007 0x0054
+ 0x0008 0x005a
+ 0x0009 0x0061
+ 0x000a 0x006a
+ 0x000b 0x0071
+
+ 0x0001 0x0025
+ 0x00010001 0x002c
+ 0x00010002 0x0035
+ 0x00010003 0x003d
+ 0x00010004 0x0045
+ 0x00010005 0x004e
+ 0x00010006 0x0057
+ 0x00010007 0x0061
+ 0x00010008 0x006b
+ 0x00010009 0x0076
+
+ 0x0002 0x0029
+ 0x00020001 0x0033
+ 0x00020002 0x003d
+ 0x00020003 0x0049
+ 0x00020004 0x0056
+ 0x00020005 0x0061
+ 0x00020006 0x006d
+
+ 0x0003 0x0021
+ 0x00030001 0x002a
+ 0x00030002 0x003c
+ 0x00030003 0x004e>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = < 3>;
[PATCH 7/7] thermal: qoriq: Add thermal management support
This driver add thermal management support by enabling TMU (Thermal
Monitoring Unit) on QorIQ platform.
It's based on thermal of framework:
- Trip points defined in device tree.
- Cpufreq as cooling device registered in qoriq cpufreq driver.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
drivers/thermal/Kconfig | 9 ++
drivers/thermal/Makefile| 1 +
drivers/thermal/qoriq_thermal.c | 328
3 files changed, 338 insertions(+)
create mode 100644 drivers/thermal/qoriq_thermal.c
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 2d702ca..bef26cd 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -195,6 +195,15 @@ config IMX_THERMAL
cpufreq is used as the cooling device to throttle CPUs when the
passive trip is crossed.
+config QORIQ_THERMAL
+ tristate "QorIQ Thermal Monitoring Unit"
+ depends on THERMAL_OF
+ help
+ Support for Thermal Monitoring Unit (TMU) found on QorIQ platforms.
+ It supports one critical trip point and one passive trip point. The
+ cpufreq is used as the cooling device to throttle CPUs when the
+ passive trip is crossed.
+
config SPEAR_THERMAL
tristate "SPEAr thermal sensor driver"
depends on PLAT_SPEAR || COMPILE_TEST
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index 10b07c1..6662232 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_DB8500_THERMAL) += db8500_thermal.o
obj-$(CONFIG_ARMADA_THERMAL) += armada_thermal.o
obj-$(CONFIG_TANGO_THERMAL)+= tango_thermal.o
obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
+obj-$(CONFIG_QORIQ_THERMAL)+= qoriq_thermal.o
obj-$(CONFIG_DB8500_CPUFREQ_COOLING) += db8500_cpufreq_cooling.o
obj-$(CONFIG_INTEL_POWERCLAMP) += intel_powerclamp.o
obj-$(CONFIG_X86_PKG_TEMP_THERMAL) += x86_pkg_temp_thermal.o
diff --git a/drivers/thermal/qoriq_thermal.c b/drivers/thermal/qoriq_thermal.c
new file mode 100644
index 000..644ba52
--- /dev/null
+++ b/drivers/thermal/qoriq_thermal.c
@@ -0,0 +1,328 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "thermal_core.h"
+
+#define SITES_MAX 16
+
+/*
+ * QorIQ TMU Registers
+ */
+struct qoriq_tmu_site_regs {
+ u32 tritsr; /* Immediate Temperature Site Register */
+ u32 tratsr; /* Average Temperature Site Register */
+ u8 res0[0x8];
+};
+
+struct qoriq_tmu_regs {
+ u32 tmr;/* Mode Register */
+#define TMR_DISABLE0x0
+#define TMR_ME 0x8000
+#define TMR_ALPF 0x0c00
+ u32 tsr;/* Status Register */
+ u32 tmtmir; /* Temperature measurement interval Register */
+#define TMTMIR_DEFAULT 0x000f
+ u8 res0[0x14];
+ u32 tier; /* Interrupt Enable Register */
+#define TIER_DISABLE 0x0
+ u32 tidr; /* Interrupt Detect Register */
+ u32 tiscr; /* Interrupt Site Capture Register */
+ u32 ticscr; /* Interrupt Critical Site Capture Register */
+ u8 res1[0x10];
+ u32 tmhtcrh;/* High Temperature Capture Register */
+ u32 tmhtcrl;/* Low Temperature Capture Register */
+ u8 res2[0x8];
+ u32 tmhtitr;/* High Temperature Immediate Threshold */
+ u32 tmhtatr;/* High Temperature Average Threshold */
+ u32 tmhtactr; /* High Temperature Average Crit Threshold */
+ u8 res3[0x24];
+ u32 ttcfgr; /* Temperature Configuration Register */
+ u32 tscfgr; /* Sensor Configuration Register */
+ u8 res4[0x78];
+ struct qoriq_tmu_site_regs site[SITES_MAX];
+ u8 res5[0x9f8];
+ u32 ipbrr0; /* IP Block Revision Register 0 */
+ u32 ipbrr1; /* IP Block Revision Register 1 */
+ u8 res6[0x310];
+ u32 ttr0cr; /* Temperature Range 0 Control Register */
+ u32 ttr1cr; /* Temperature Range 1 Control Register */
+ u32 ttr2cr; /* Temperature Range 2 Control Register */
+ u32 ttr3cr; /* Temperature Range 3 Control Register */
+};
+
+/*
+ * Thermal zone data
+ */
+struct qoriq_tmu_data {
+ struct thermal_zone_device *tz;
+
[PATCH 6/7] arm64:dt:ls2080a: Add TMU device tree support for LS2080A
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts | 2 +-
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 116 +++--
4 files changed, 111 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
index e8801fa..18e99f4 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
@@ -46,7 +46,7 @@
/dts-v1/;
-/include/ "fsl-ls2080a.dtsi"
+#include "fsl-ls2080a.dtsi"
/ {
model = "Freescale Layerscape 2080a QDS Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
index e127f0b..f1c8115 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
@@ -46,7 +46,7 @@
/dts-v1/;
-/include/ "fsl-ls2080a.dtsi"
+#include "fsl-ls2080a.dtsi"
/ {
model = "Freescale Layerscape 2080a RDB Board";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
index 505d038..290604b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
@@ -46,7 +46,7 @@
/dts-v1/;
-/include/ "fsl-ls2080a.dtsi"
+#include "fsl-ls2080a.dtsi"
/ {
model = "Freescale Layerscape 2080a software Simulator model";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 3187c82..5cc27df 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -44,6 +44,8 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
+#include
+
/ {
compatible = "fsl,ls2080a";
interrupt-parent = <>;
@@ -62,56 +64,60 @@
*/
/* We have 4 clusters having 2 Cortex-A57 cores each */
- cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x0>;
clocks = < 1 0>;
+ #cooling-cells = <2>;
};
- cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x1>;
clocks = < 1 0>;
};
- cpu@100 {
+ cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x100>;
clocks = < 1 1>;
+ #cooling-cells = <2>;
};
- cpu@101 {
+ cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x101>;
clocks = < 1 1>;
};
- cpu@200 {
+ cpu4: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x200>;
clocks = < 1 2>;
+ #cooling-cells = <2>;
};
- cpu@201 {
+ cpu5: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x201>;
clocks = < 1 2>;
};
- cpu@300 {
+ cpu6: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x300>;
clocks = < 1 3>;
+ #cooling-cells = <2>;
};
- cpu@301 {
+ cpu7: cpu@301 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x301>;
@@ -191,6 +197,100 @@
clocks = <>;
};
+ tmu: tmu@1f8 {
+ compatible = "fsl,qori
[PATCH 3/7] powerpc/mpc85xx: Update TMU device tree node for T1023/T1024
SoC compatible string and endianness property are added according to the
new bindings.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
arch/powerpc/boot/dts/fsl/t1023si-post.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
index 6e0b489..bce762a 100644
--- a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
@@ -321,7 +321,7 @@
0x00030001 0x000d
0x00030002 0x0019
0x00030003 0x0024>;
- #thermal-sensor-cells = <0>;
+ #thermal-sensor-cells = <1>;
};
thermal-zones {
@@ -329,7 +329,7 @@
polling-delay-passive = <1000>;
polling-delay = <5000>;
- thermal-sensors = <>;
+ thermal-sensors = < 0>;
trips {
cpu_alert: cpu-alert {
--
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[PATCH 1/7] dt-bindings: Update QorIQ TMU thermal bindings
For different types of SoC the sensor id and endianness may vary.
"#thermal-sensor-cells" is used to provide sensor id information.
"little-endian" property is to tell the endianness of TMU.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
.../devicetree/bindings/thermal/qoriq-thermal.txt | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
index 66223d5..8eeef80 100644
--- a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
@@ -1,22 +1,28 @@
* Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs
Required properties:
-- compatible : Must include "fsl,qoriq-tmu". The version of the device is
+- compatible: Must include "fsl,qoriq-tmu". The version of the device is
determined by the TMU IP Block Revision Register (IPBRR0) at
offset 0x0BF8.
- Table of correspondences between IPBRR0 values and example chips:
+ Table of correspondences between IPBRR0 values and example chips:
Value Device
-- -
0x01900102 T1040
-- reg : Address range of TMU registers.
-- interrupts : Contains the interrupt for TMU.
-- fsl,tmu-range : The values to be programmed into TTRnCR, as specified by
+- reg: Address range of TMU registers.
+- interrupts: Contains the interrupt for TMU.
+- fsl,tmu-range: The values to be programmed into TTRnCR, as specified by
the SoC reference manual. The first cell is TTR0CR, the second is
TTR1CR, etc.
-- fsl,tmu-calibration : A list of cell pairs containing temperature
+- fsl,tmu-calibration: A list of cell pairs containing temperature
calibration data, as specified by the SoC reference manual.
The first cell of each pair is the value to be written to TTCFGR,
and the second is the value to be written to TSCFGR.
+- #thermal-sensor-cells: Must be 1. The sensor specifier is the monitoring
+ site ID, and represents the "n" in TRITSRn and TRATSRn.
+
+Optional property:
+- little-endian: If present, the TMU registers are little endian. If absent,
+ the default is big endian.
Example:
@@ -60,4 +66,5 @@ tmu@f {
0x0003 0x0012
0x00030001 0x001d>;
+ #thermal-sensor-cells = <1>;
};
--
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[PATCH 4/7] arm:dt:ls1021a: Add TMU device tree support for LS1021A
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
arch/arm/boot/dts/ls1021a.dtsi | 84 +-
1 file changed, 82 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 5ae8e92..1bac9d8 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -47,6 +47,7 @@
#include "skeleton64.dtsi"
#include
+#include
/ {
compatible = "fsl,ls1021a";
@@ -70,14 +71,15 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu@f00 {
+ cpu0: cpu@f00 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf00>;
clocks = <_clk>;
+ #cooling-cells = <2>;
};
- cpu@f01 {
+ cpu1: cpu@f01 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf01>;
@@ -251,6 +253,84 @@
};
};
+ tmu: tmu@1f0 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f0 0x0 0x1>;
+ interrupts = ;
+ fsl,tmu-range = <0xb 0xa0026 0x80048 0x30061>;
+ fsl,tmu-calibration = <0x 0x000f
+ 0x0001 0x0017
+ 0x0002 0x001e
+ 0x0003 0x0026
+ 0x0004 0x002e
+ 0x0005 0x0035
+ 0x0006 0x003d
+ 0x0007 0x0044
+ 0x0008 0x004c
+ 0x0009 0x0053
+ 0x000a 0x005b
+ 0x000b 0x0064
+
+ 0x0001 0x0011
+ 0x00010001 0x001c
+ 0x00010002 0x0024
+ 0x00010003 0x002b
+ 0x00010004 0x0034
+ 0x00010005 0x0039
+ 0x00010006 0x0042
+ 0x00010007 0x004c
+ 0x00010008 0x0051
+ 0x00010009 0x005a
+ 0x0001000a 0x0063
+
+ 0x0002 0x0013
+ 0x00020001 0x0019
+ 0x00020002 0x0024
+ 0x00020003 0x002c
+ 0x00020004 0x0035
+ 0x00020005 0x003d
+ 0x00020006 0x0046
+ 0x00020007 0x0050
+ 0x00020008 0x0059
+
+ 0x0003 0x0002
+ 0x00030001 0x000d
+ 0x00030002 0x0019
+ 0x00030003 0x0024>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = < 0>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit: cpu-crit {
+
[PATCH V3 1/2] cpufreq: qoriq: Remove __exit macro from .exit callback
.exit callback (qoriq_cpufreq_cpu_exit()) is also used during suspend.
So __exit macro should be removed or the function will be discarded.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
drivers/cpufreq/qoriq-cpufreq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/cpufreq/qoriq-cpufreq.c b/drivers/cpufreq/qoriq-cpufreq.c
index b23e525..3a3fe39 100644
--- a/drivers/cpufreq/qoriq-cpufreq.c
+++ b/drivers/cpufreq/qoriq-cpufreq.c
@@ -301,7 +301,7 @@ err_np:
return -ENODEV;
}
-static int __exit qoriq_cpufreq_cpu_exit(struct cpufreq_policy *policy)
+static int qoriq_cpufreq_cpu_exit(struct cpufreq_policy *policy)
{
struct cpu_data *data = policy->driver_data;
@@ -348,7 +348,7 @@ static struct cpufreq_driver qoriq_cpufreq_driver = {
.name = "qoriq_cpufreq",
.flags = CPUFREQ_CONST_LOOPS,
.init = qoriq_cpufreq_cpu_init,
- .exit = __exit_p(qoriq_cpufreq_cpu_exit),
+ .exit = qoriq_cpufreq_cpu_exit,
.verify = cpufreq_generic_frequency_table_verify,
.target_index = qoriq_cpufreq_target,
.get= cpufreq_generic_get,
--
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[PATCH V2] cpufreq: qoriq: Fix cooling device registration issue during suspend
Cooling device is registered by ready callback. It's also invoked while
system resuming from sleep (Enabling non-boot cpus). Thus cooling device
may be multiple registered. Matchable unregistration is added to exit
callback to fix this issue.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
Changes for V2:
* Using qoriq_cpufreq_cpu_exit() callback instead of adding stop_cpu().
drivers/cpufreq/qoriq-cpufreq.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/cpufreq/qoriq-cpufreq.c b/drivers/cpufreq/qoriq-cpufreq.c
index b23e525..0b85f90 100644
--- a/drivers/cpufreq/qoriq-cpufreq.c
+++ b/drivers/cpufreq/qoriq-cpufreq.c
@@ -301,10 +301,11 @@ err_np:
return -ENODEV;
}
-static int __exit qoriq_cpufreq_cpu_exit(struct cpufreq_policy *policy)
+static int qoriq_cpufreq_cpu_exit(struct cpufreq_policy *policy)
{
struct cpu_data *data = policy->driver_data;
+ cpufreq_cooling_unregister(data->cdev);
kfree(data->pclk);
kfree(data->table);
kfree(data);
@@ -348,7 +349,7 @@ static struct cpufreq_driver qoriq_cpufreq_driver = {
.name = "qoriq_cpufreq",
.flags = CPUFREQ_CONST_LOOPS,
.init = qoriq_cpufreq_cpu_init,
- .exit = __exit_p(qoriq_cpufreq_cpu_exit),
+ .exit = qoriq_cpufreq_cpu_exit,
.verify = cpufreq_generic_frequency_table_verify,
.target_index = qoriq_cpufreq_target,
.get= cpufreq_generic_get,
--
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[PATCH 1/2] cpufreq: qoriq: Fix cooling device registration issue during suspend
Cooling device is registered by ready callback. It's also invoked while
system resuming from sleep (Enabling non-boot cpus). Thus cooling device
may be multiple registered. Stop_cpu callback is invoked during suspend
(Disabling non-boot cpus). So matchable unregistration is added to fix
this issue.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
drivers/cpufreq/qoriq-cpufreq.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/cpufreq/qoriq-cpufreq.c b/drivers/cpufreq/qoriq-cpufreq.c
index b23e525..1c2fdc1 100644
--- a/drivers/cpufreq/qoriq-cpufreq.c
+++ b/drivers/cpufreq/qoriq-cpufreq.c
@@ -305,6 +305,7 @@ static int __exit qoriq_cpufreq_cpu_exit(struct
cpufreq_policy *policy)
{
struct cpu_data *data = policy->driver_data;
+ cpufreq_cooling_unregister(data->cdev);
kfree(data->pclk);
kfree(data->table);
kfree(data);
@@ -323,6 +324,12 @@ static int qoriq_cpufreq_target(struct cpufreq_policy
*policy,
return clk_set_parent(policy->clk, parent);
}
+static void qoriq_cpufreq_stop_cpu(struct cpufreq_policy *policy)
+{
+ struct cpu_data *cpud = policy->driver_data;
+
+ cpufreq_cooling_unregister(cpud->cdev);
+}
static void qoriq_cpufreq_ready(struct cpufreq_policy *policy)
{
@@ -352,6 +359,7 @@ static struct cpufreq_driver qoriq_cpufreq_driver = {
.verify = cpufreq_generic_frequency_table_verify,
.target_index = qoriq_cpufreq_target,
.get= cpufreq_generic_get,
+ .stop_cpu = qoriq_cpufreq_stop_cpu,
.ready = qoriq_cpufreq_ready,
.attr = cpufreq_generic_attr,
};
--
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[PATCH 2/2] cpufreq: qoriq: Don't show cooling device messages if THERMAL_OF undefined
When THERMAL_OF is undefined the cooling device messages should not be
shown. -ENOSYS is returned from of_cpufreq_cooling_register() when
THERMAL_OF is undefined.
Signed-off-by: Jia Hongtao <hongtao@nxp.com>
---
drivers/cpufreq/qoriq-cpufreq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/cpufreq/qoriq-cpufreq.c b/drivers/cpufreq/qoriq-cpufreq.c
index 1c2fdc1..ff8da83 100644
--- a/drivers/cpufreq/qoriq-cpufreq.c
+++ b/drivers/cpufreq/qoriq-cpufreq.c
@@ -340,8 +340,8 @@ static void qoriq_cpufreq_ready(struct cpufreq_policy
*policy)
cpud->cdev = of_cpufreq_cooling_register(np,
policy->related_cpus);
- if (IS_ERR(cpud->cdev)) {
- pr_err("Failed to register cooling device cpu%d: %ld\n",
+ if (IS_ERR(cpud->cdev) && PTR_ERR(cpud->cdev) != -ENOSYS) {
+ pr_err("cpu%d is not running as cooling device: %ld\n",
policy->cpu, PTR_ERR(cpud->cdev));
cpud->cdev = NULL;
--
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[PATCH V3] cpufreq: qoriq: Register cooling device based on device tree
Register the qoriq cpufreq driver as a cooling device, based on the
thermal device tree framework. When temperature crosses the passive trip
point cpufreq is used to throttle CPUs.
Signed-off-by: Jia Hongtao <hongtao@freescale.com>
Reviewed-by: Viresh Kumar <viresh.ku...@linaro.org>
---
Changes for V3:
* Removed unnecessary cpu node NULL check.
Changes for V2:
* Using ->ready callback for cpu cooling device registering.
drivers/cpufreq/qoriq-cpufreq.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/cpufreq/qoriq-cpufreq.c b/drivers/cpufreq/qoriq-cpufreq.c
index 4f53fa2..cb6a62c 100644
--- a/drivers/cpufreq/qoriq-cpufreq.c
+++ b/drivers/cpufreq/qoriq-cpufreq.c
@@ -12,6 +12,7 @@
#include
#include
+#include
#include
#include
#include
@@ -33,6 +34,7 @@
struct cpu_data {
struct clk **pclk;
struct cpufreq_frequency_table *table;
+ struct thermal_cooling_device *cdev;
};
/*
@@ -260,6 +262,27 @@ static int qoriq_cpufreq_target(struct cpufreq_policy
*policy,
return clk_set_parent(policy->clk, parent);
}
+
+static void qoriq_cpufreq_ready(struct cpufreq_policy *policy)
+{
+ struct cpu_data *cpud = policy->driver_data;
+ struct device_node *np = of_get_cpu_node(policy->cpu, NULL);
+
+ if (of_find_property(np, "#cooling-cells", NULL)) {
+ cpud->cdev = of_cpufreq_cooling_register(np,
+policy->related_cpus);
+
+ if (IS_ERR(cpud->cdev)) {
+ pr_err("Failed to register cooling device cpu%d: %ld\n",
+ policy->cpu, PTR_ERR(cpud->cdev));
+
+ cpud->cdev = NULL;
+ }
+ }
+
+ of_node_put(np);
+}
+
static struct cpufreq_driver qoriq_cpufreq_driver = {
.name = "qoriq_cpufreq",
.flags = CPUFREQ_CONST_LOOPS,
@@ -268,6 +291,7 @@ static struct cpufreq_driver qoriq_cpufreq_driver = {
.verify = cpufreq_generic_frequency_table_verify,
.target_index = qoriq_cpufreq_target,
.get= cpufreq_generic_get,
+ .ready = qoriq_cpufreq_ready,
.attr = cpufreq_generic_attr,
};
--
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[PATCH V2] cpufreq: qoriq: Register cooling device based on device tree
Register the qoriq cpufreq driver as a cooling device, based on the
thermal device tree framework. When temperature crosses the passive trip
point cpufreq is used to throttle CPUs.
Signed-off-by: Jia Hongtao <hongtao@freescale.com>
---
Changes for V2:
* Using ->ready callback for cpu cooling device registering.
drivers/cpufreq/qoriq-cpufreq.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/cpufreq/qoriq-cpufreq.c b/drivers/cpufreq/qoriq-cpufreq.c
index 4f53fa2..a39f868 100644
--- a/drivers/cpufreq/qoriq-cpufreq.c
+++ b/drivers/cpufreq/qoriq-cpufreq.c
@@ -12,6 +12,7 @@
#include
#include
+#include
#include
#include
#include
@@ -33,6 +34,7 @@
struct cpu_data {
struct clk **pclk;
struct cpufreq_frequency_table *table;
+ struct thermal_cooling_device *cdev;
};
/*
@@ -260,6 +262,30 @@ static int qoriq_cpufreq_target(struct cpufreq_policy
*policy,
return clk_set_parent(policy->clk, parent);
}
+
+static void qoriq_cpufreq_ready(struct cpufreq_policy *policy)
+{
+ struct cpu_data *cpud = policy->driver_data;
+ struct device_node *np = of_get_cpu_node(policy->cpu, NULL);
+
+ if (WARN_ON(!np))
+ return;
+
+ if (of_find_property(np, "#cooling-cells", NULL)) {
+ cpud->cdev = of_cpufreq_cooling_register(np,
+policy->related_cpus);
+
+ if (IS_ERR(cpud->cdev)) {
+ pr_err("Failed to register cooling device cpu%d: %ld\n",
+ policy->cpu, PTR_ERR(cpud->cdev));
+
+ cpud->cdev = NULL;
+ }
+ }
+
+ of_node_put(np);
+}
+
static struct cpufreq_driver qoriq_cpufreq_driver = {
.name = "qoriq_cpufreq",
.flags = CPUFREQ_CONST_LOOPS,
@@ -268,6 +294,7 @@ static struct cpufreq_driver qoriq_cpufreq_driver = {
.verify = cpufreq_generic_frequency_table_verify,
.target_index = qoriq_cpufreq_target,
.get= cpufreq_generic_get,
+ .ready = qoriq_cpufreq_ready,
.attr = cpufreq_generic_attr,
};
--
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[PATCH V4 4/5] powerpc/mpc85xx: Add TMU device tree support for T1023/T1024
Also add nodes and properties for thermal management support. Meanwhile
preprocessor support is needed using thermal of framework.
Signed-off-by: Jia Hongtao <hongtao@freescale.com>
Reviewed-by: Scott Wood <scottw...@freescale.com>
---
arch/powerpc/boot/dts/fsl/t1023rdb.dts | 2 +-
arch/powerpc/boot/dts/fsl/t1023si-post.dtsi | 86 +
arch/powerpc/boot/dts/fsl/t1024qds.dts | 2 +-
arch/powerpc/boot/dts/fsl/t1024rdb.dts | 2 +-
arch/powerpc/boot/dts/fsl/t1024si-post.dtsi | 2 +-
arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi | 2 +
6 files changed, 92 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t1023rdb.dts
b/arch/powerpc/boot/dts/fsl/t1023rdb.dts
index 2b2fff4..6bd842b 100644
--- a/arch/powerpc/boot/dts/fsl/t1023rdb.dts
+++ b/arch/powerpc/boot/dts/fsl/t1023rdb.dts
@@ -159,4 +159,4 @@
};
};
-/include/ "t1023si-post.dtsi"
+#include "t1023si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
index 518ddaa..99e421d 100644
--- a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
@@ -32,6 +32,8 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#include
+
{
#address-cells = <2>;
#size-cells = <1>;
@@ -275,6 +277,90 @@
reg = <0xea000 0x4000>;
};
+ tmu: tmu@f {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0xf 0x1000>;
+ interrupts = <18 2 0 0>;
+ fsl,tmu-range = <0xb 0xa0026 0x80048 0x30061>;
+ fsl,tmu-calibration = <0x 0x000f
+ 0x0001 0x0017
+ 0x0002 0x001e
+ 0x0003 0x0026
+ 0x0004 0x002e
+ 0x0005 0x0035
+ 0x0006 0x003d
+ 0x0007 0x0044
+ 0x0008 0x004c
+ 0x0009 0x0053
+ 0x000a 0x005b
+ 0x000b 0x0064
+
+ 0x0001 0x0011
+ 0x00010001 0x001c
+ 0x00010002 0x0024
+ 0x00010003 0x002b
+ 0x00010004 0x0034
+ 0x00010005 0x0039
+ 0x00010006 0x0042
+ 0x00010007 0x004c
+ 0x00010008 0x0051
+ 0x00010009 0x005a
+ 0x0001000a 0x0063
+
+ 0x0002 0x0013
+ 0x00020001 0x0019
+ 0x00020002 0x0024
+ 0x00020003 0x002c
+ 0x00020004 0x0035
+ 0x00020005 0x003d
+ 0x00020006 0x0046
+ 0x00020007 0x0050
+ 0x00020008 0x0059
+
+ 0x0003 0x0002
+ 0x00030001 0x000d
+ 0x00030002 0x0019
+ 0x00030003 0x0024>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = <>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit: cpu-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+
[PATCH V4 3/5] powerpc/mpc85xx: Add TMU device tree support for T1040/T1042
Also add nodes and properties for thermal management support. Meanwhile
preprocessor support is needed using thermal of framework.
Signed-off-by: Jia Hongtao <hongtao@freescale.com>
Reviewed-by: Scott Wood <scottw...@freescale.com>
---
arch/powerpc/boot/dts/fsl/t1040d4rdb.dts| 2 +-
arch/powerpc/boot/dts/fsl/t1040qds.dts | 2 +-
arch/powerpc/boot/dts/fsl/t1040rdb.dts | 2 +-
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 94 +
arch/powerpc/boot/dts/fsl/t1042d4rdb.dts| 2 +-
arch/powerpc/boot/dts/fsl/t1042qds.dts | 2 +-
arch/powerpc/boot/dts/fsl/t1042rdb.dts | 2 +-
arch/powerpc/boot/dts/fsl/t1042rdb_pi.dts | 2 +-
arch/powerpc/boot/dts/fsl/t1042si-post.dtsi | 2 +-
arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi | 4 ++
10 files changed, 106 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t1040d4rdb.dts
b/arch/powerpc/boot/dts/fsl/t1040d4rdb.dts
index 681746e..fb6bc02 100644
--- a/arch/powerpc/boot/dts/fsl/t1040d4rdb.dts
+++ b/arch/powerpc/boot/dts/fsl/t1040d4rdb.dts
@@ -43,4 +43,4 @@
interrupt-parent = <>;
};
-/include/ "t1040si-post.dtsi"
+#include "t1040si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/t1040qds.dts
b/arch/powerpc/boot/dts/fsl/t1040qds.dts
index 4d29865..5f76edc 100644
--- a/arch/powerpc/boot/dts/fsl/t1040qds.dts
+++ b/arch/powerpc/boot/dts/fsl/t1040qds.dts
@@ -43,4 +43,4 @@
interrupt-parent = <>;
};
-/include/ "t1040si-post.dtsi"
+#include "t1040si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/t1040rdb.dts
b/arch/powerpc/boot/dts/fsl/t1040rdb.dts
index 8f9e65b..cf19415 100644
--- a/arch/powerpc/boot/dts/fsl/t1040rdb.dts
+++ b/arch/powerpc/boot/dts/fsl/t1040rdb.dts
@@ -45,4 +45,4 @@
};
};
-/include/ "t1040si-post.dtsi"
+#include "t1040si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
index d30b3de..e0f4da5 100644
--- a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -32,6 +32,8 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#include
+
_fbpr {
compatible = "fsl,bman-fbpr";
alloc-ranges = <0 0 0x1 0>;
@@ -484,6 +486,98 @@
reg= <0xea000 0x4000>;
};
+ tmu: tmu@f {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0xf 0x1000>;
+ interrupts = <18 2 0 0>;
+ fsl,tmu-range = <0xa 0x90026 0x8004a 0x1006a>;
+ fsl,tmu-calibration = <0x 0x0025
+ 0x0001 0x0028
+ 0x0002 0x002d
+ 0x0003 0x0031
+ 0x0004 0x0036
+ 0x0005 0x003a
+ 0x0006 0x0040
+ 0x0007 0x0044
+ 0x0008 0x004a
+ 0x0009 0x004f
+ 0x000a 0x0054
+
+ 0x0001 0x000d
+ 0x00010001 0x0013
+ 0x00010002 0x0019
+ 0x00010003 0x001f
+ 0x00010004 0x0025
+ 0x00010005 0x002d
+ 0x00010006 0x0033
+ 0x00010007 0x0043
+ 0x00010008 0x004b
+ 0x00010009 0x0053
+
+ 0x0002 0x0010
+ 0x00020001 0x0017
+ 0x00020002 0x001f
+ 0x00020003 0x0029
+ 0x00020004 0x0031
+ 0x00020005 0x003c
+ 0x00020006 0x0042
+ 0x00020007 0x004d
+ 0x00020008 0x0056
+
+ 0x0003 0x0012
+ 0x00030001 0x001d>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = <>;
+
+ trips {
+
[PATCH V4 2/5] thermal: qoriq: Add thermal management support
This driver add thermal management support by enabling TMU (Thermal
Monitoring Unit) on QorIQ platform.
It's based on thermal of framework:
- Trip points defined in device tree.
- Cpufreq as cooling device registered in qoriq cpufreq driver.
Signed-off-by: Jia Hongtao <hongtao@freescale.com>
Reviewed-by: Scott Wood <scottw...@freescale.com>
---
V4 changes:
- Code cleanup:
* Remove unnecessary comments.
* Remove unnecessary cpufreq.h inclusion.
* Remove unnecessary ENABLE mode setting in probe function.
* Redefine tmu_get_temp function.
V3 changes:
- Using thermal of framework.
drivers/thermal/Kconfig | 10 ++
drivers/thermal/Makefile| 1 +
drivers/thermal/qoriq_thermal.c | 262
3 files changed, 273 insertions(+)
create mode 100644 drivers/thermal/qoriq_thermal.c
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index c463c89..43a925c 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -194,6 +194,16 @@ config IMX_THERMAL
cpufreq is used as the cooling device to throttle CPUs when the
passive trip is crossed.
+config QORIQ_THERMAL
+ tristate "Freescale QorIQ Thermal Monitoring Unit"
+ depends on CPU_THERMAL
+ depends on THERMAL_OF
+ help
+ Enable thermal management based on Freescale QorIQ Thermal Monitoring
+ Unit (TMU). It supports one critical trip point and one passive trip
+ point. The cpufreq is used as the cooling device to throttle CPUs when
+ the passive trip is crossed.
+
config SPEAR_THERMAL
bool "SPEAr thermal sensor driver"
depends on PLAT_SPEAR || COMPILE_TEST
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index cfae6a6..e269979 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_DOVE_THERMAL)+= dove_thermal.o
obj-$(CONFIG_DB8500_THERMAL) += db8500_thermal.o
obj-$(CONFIG_ARMADA_THERMAL) += armada_thermal.o
obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
+obj-$(CONFIG_QORIQ_THERMAL)+= qoriq_thermal.o
obj-$(CONFIG_DB8500_CPUFREQ_COOLING) += db8500_cpufreq_cooling.o
obj-$(CONFIG_INTEL_POWERCLAMP) += intel_powerclamp.o
obj-$(CONFIG_X86_PKG_TEMP_THERMAL) += x86_pkg_temp_thermal.o
diff --git a/drivers/thermal/qoriq_thermal.c b/drivers/thermal/qoriq_thermal.c
new file mode 100644
index 000..2a563f9
--- /dev/null
+++ b/drivers/thermal/qoriq_thermal.c
@@ -0,0 +1,262 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "thermal_core.h"
+
+#define SITES_MAX 16
+
+/*
+ * QorIQ TMU Registers
+ */
+struct qoriq_tmu_site_regs {
+ __be32 tritsr; /* Immediate Temperature Site Register */
+ __be32 tratsr; /* Average Temperature Site Register */
+ u8 res0[0x8];
+} __packed;
+
+struct qoriq_tmu_regs {
+ __be32 tmr; /* Mode Register */
+#define TMR_DISABLE0x0
+#define TMR_ME 0x8000
+#define TMR_ALPF 0x0c00
+#define TMR_MSITE 0x8000 /* Core temperature site */
+#define TMR_ALL(TMR_ME | TMR_ALPF | TMR_MSITE)
+ __be32 tsr; /* Status Register */
+ __be32 tmtmir; /* Temperature measurement interval Register */
+#define TMTMIR_DEFAULT 0x000f
+ u8 res0[0x14];
+ __be32 tier;/* Interrupt Enable Register */
+#define TIER_DISABLE 0x0
+ __be32 tidr;/* Interrupt Detect Register */
+ __be32 tiscr; /* Interrupt Site Capture Register */
+ __be32 ticscr; /* Interrupt Critical Site Capture Register */
+ u8 res1[0x10];
+ __be32 tmhtcrh; /* High Temperature Capture Register */
+ __be32 tmhtcrl; /* Low Temperature Capture Register */
+ u8 res2[0x8];
+ __be32 tmhtitr; /* High Temperature Immediate Threshold */
+ __be32 tmhtatr; /* High Temperature Average Threshold */
+ __be32 tmhtactr;/* High Temperature Average Crit Threshold */
+ u8 res3[0x24];
+ __be32 ttcfgr; /* Temperature Configuration Register */
+ __be32 tscfgr; /* Sensor Configuration Register */
+ u8 res4[0x78];
+ struct qoriq_tmu_site_regs site[SITES_MAX];
+ u8 res5[0x9f8];
+ __be32 ipbrr0; /* IP Block Re
[PATCH V4 5/5] arm/ls1021a: Add TMU device tree support for LS1021A
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao <hongtao@freescale.com>
Reviewed-by: Scott Wood <scottw...@freescale.com>
---
arch/arm/boot/dts/ls1021a.dtsi | 84 +-
1 file changed, 82 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 9430a99..d31a811 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -47,6 +47,7 @@
#include "skeleton64.dtsi"
#include
+#include
/ {
compatible = "fsl,ls1021a";
@@ -70,14 +71,15 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu@f00 {
+ cpu0: cpu@f00 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf00>;
clocks = <_clk>;
+ #cooling-cells = <2>;
};
- cpu@f01 {
+ cpu1: cpu@f01 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf01>;
@@ -226,6 +228,84 @@
};
};
+ tmu: tmu@1f0 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f0 0x0 0x1>;
+ interrupts = ;
+ fsl,tmu-range = <0xb 0xa0026 0x80048 0x30061>;
+ fsl,tmu-calibration = <0x 0x000f
+ 0x0001 0x0017
+ 0x0002 0x001e
+ 0x0003 0x0026
+ 0x0004 0x002e
+ 0x0005 0x0035
+ 0x0006 0x003d
+ 0x0007 0x0044
+ 0x0008 0x004c
+ 0x0009 0x0053
+ 0x000a 0x005b
+ 0x000b 0x0064
+
+ 0x0001 0x0011
+ 0x00010001 0x001c
+ 0x00010002 0x0024
+ 0x00010003 0x002b
+ 0x00010004 0x0034
+ 0x00010005 0x0039
+ 0x00010006 0x0042
+ 0x00010007 0x004c
+ 0x00010008 0x0051
+ 0x00010009 0x005a
+ 0x0001000a 0x0063
+
+ 0x0002 0x0013
+ 0x00020001 0x0019
+ 0x00020002 0x0024
+ 0x00020003 0x002c
+ 0x00020004 0x0035
+ 0x00020005 0x003d
+ 0x00020006 0x0046
+ 0x00020007 0x0050
+ 0x00020008 0x0059
+
+ 0x0003 0x0002
+ 0x00030001 0x000d
+ 0x00030002 0x0019
+ 0x00030003 0x0024>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = <>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit: cpu-crit {
+
[PATCH] cpufreq: qoriq: Register cooling device based on device tree
Register the qoriq cpufreq driver as a cooling device, based on the
thermal device tree framework. When temperature crosses the passive trip
point cpufreq is used to throttle CPUs.
Signed-off-by: Jia Hongtao <hongtao@freescale.com>
Reviewed-by: Scott Wood <scottw...@freescale.com>
---
This patch depends on following patches from Scott Wood:
http://patchwork.ozlabs.org/patch/519803/
http://patchwork.ozlabs.org/patch/519804/
drivers/cpufreq/qoriq-cpufreq.c | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/cpufreq/qoriq-cpufreq.c b/drivers/cpufreq/qoriq-cpufreq.c
index 4f53fa2..cb1bc3c 100644
--- a/drivers/cpufreq/qoriq-cpufreq.c
+++ b/drivers/cpufreq/qoriq-cpufreq.c
@@ -12,6 +12,7 @@
#include
#include
+#include
#include
#include
#include
@@ -33,6 +34,7 @@
struct cpu_data {
struct clk **pclk;
struct cpufreq_frequency_table *table;
+ struct thermal_cooling_device *cdev;
};
/*
@@ -292,7 +294,11 @@ static const struct of_device_id node_matches[]
__initconst = {
static int __init qoriq_cpufreq_init(void)
{
int ret;
- struct device_node *np;
+ struct device_node *np;
+ struct device_node *cpu_np;
+ unsigned int cpu_id;
+ struct cpufreq_policy cpu_policy;
+ struct cpu_data *cpud;
const struct of_device_id *match;
const struct soc_data *data;
@@ -309,6 +315,22 @@ static int __init qoriq_cpufreq_init(void)
return -ENODEV;
ret = cpufreq_register_driver(_cpufreq_driver);
+
+ /* Register CPU cooling device for QorIQ platform */
+ for_each_node_with_property(cpu_np, "#cooling-cells") {
+ of_property_read_u32(cpu_np, "reg", _id);
+ cpufreq_get_policy(_policy, cpu_id);
+
+ cpud = cpu_policy.driver_data;
+ cpud->cdev = of_cpufreq_cooling_register(cpu_np,
+ cpu_policy.related_cpus);
+ if (IS_ERR(cpud->cdev) && ERR_PTR(cpud->cdev) != -ENOSYS)
+ pr_err("Failed to register cooling device cpu%d: %ld\n",
+ cpu_id, PTR_ERR(cpud->cdev));
+ }
+
+ of_node_put(cpu_np);
+
if (!ret)
pr_info("Freescale QorIQ CPU frequency scaling driver\n");
--
2.1.0.27.g96db324
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[PATCH V4 0/5] TMU support for QorIQ platform
This patchset add thermal management support to QorIQ platform including: - T1040/T1042. - T1023/T1024. - LS1021A. The thermal driver is updated to V4 based on Linux v4.4-rc2. CPU Cooling device registration is done by another patch which will send to both thermal and cpufreq maintainers. The patchset is reviewed by Scott Wood <scottw...@freescale.com>. Jia Hongtao (5): dt-bindings: Add QorIQ TMU thermal bindings thermal: qoriq: Add thermal management support powerpc/mpc85xx: Add TMU device tree support for T1040/T1042 powerpc/mpc85xx: Add TMU device tree support for T1023/T1024 arm/ls1021a: Add TMU device tree support for LS1021A .../devicetree/bindings/thermal/qoriq-thermal.txt | 63 + arch/arm/boot/dts/ls1021a.dtsi | 84 ++- arch/powerpc/boot/dts/fsl/t1023rdb.dts | 2 +- arch/powerpc/boot/dts/fsl/t1023si-post.dtsi| 86 +++ arch/powerpc/boot/dts/fsl/t1024qds.dts | 2 +- arch/powerpc/boot/dts/fsl/t1024rdb.dts | 2 +- arch/powerpc/boot/dts/fsl/t1024si-post.dtsi| 2 +- arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi | 2 + arch/powerpc/boot/dts/fsl/t1040d4rdb.dts | 2 +- arch/powerpc/boot/dts/fsl/t1040qds.dts | 2 +- arch/powerpc/boot/dts/fsl/t1040rdb.dts | 2 +- arch/powerpc/boot/dts/fsl/t1040si-post.dtsi| 94 arch/powerpc/boot/dts/fsl/t1042d4rdb.dts | 2 +- arch/powerpc/boot/dts/fsl/t1042qds.dts | 2 +- arch/powerpc/boot/dts/fsl/t1042rdb.dts | 2 +- arch/powerpc/boot/dts/fsl/t1042rdb_pi.dts | 2 +- arch/powerpc/boot/dts/fsl/t1042si-post.dtsi| 2 +- arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi | 4 + drivers/thermal/Kconfig| 10 + drivers/thermal/Makefile | 1 + drivers/thermal/qoriq_thermal.c| 262 + 21 files changed, 616 insertions(+), 14 deletions(-) create mode 100644 Documentation/devicetree/bindings/thermal/qoriq-thermal.txt create mode 100644 drivers/thermal/qoriq_thermal.c -- 2.1.0.27.g96db324 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V4 1/5] dt-bindings: Add QorIQ TMU thermal bindings
Add bindings documentation for TMU (Thermal Monitoring Unit) on QorIQ
platform.
Signed-off-by: Jia Hongtao <hongtao@freescale.com>
Reviewed-by: Scott Wood <scottw...@freescale.com>
---
.../devicetree/bindings/thermal/qoriq-thermal.txt | 63 ++
1 file changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
new file mode 100644
index 000..66223d5
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
@@ -0,0 +1,63 @@
+* Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs
+
+Required properties:
+- compatible : Must include "fsl,qoriq-tmu". The version of the device is
+ determined by the TMU IP Block Revision Register (IPBRR0) at
+ offset 0x0BF8.
+ Table of correspondences between IPBRR0 values and example chips:
+ Value Device
+ -- -
+ 0x01900102 T1040
+- reg : Address range of TMU registers.
+- interrupts : Contains the interrupt for TMU.
+- fsl,tmu-range : The values to be programmed into TTRnCR, as specified by
+ the SoC reference manual. The first cell is TTR0CR, the second is
+ TTR1CR, etc.
+- fsl,tmu-calibration : A list of cell pairs containing temperature
+ calibration data, as specified by the SoC reference manual.
+ The first cell of each pair is the value to be written to TTCFGR,
+ and the second is the value to be written to TSCFGR.
+
+Example:
+
+tmu@f {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0xf 0x1000>;
+ interrupts = <18 2 0 0>;
+ fsl,tmu-range = <0x000a 0x00090026 0x0008004a 0x0001006a>;
+ fsl,tmu-calibration = <0x 0x0025
+ 0x0001 0x0028
+ 0x0002 0x002d
+ 0x0003 0x0031
+ 0x0004 0x0036
+ 0x0005 0x003a
+ 0x0006 0x0040
+ 0x0007 0x0044
+ 0x0008 0x004a
+ 0x0009 0x004f
+ 0x000a 0x0054
+
+ 0x0001 0x000d
+ 0x00010001 0x0013
+ 0x00010002 0x0019
+ 0x00010003 0x001f
+ 0x00010004 0x0025
+ 0x00010005 0x002d
+ 0x00010006 0x0033
+ 0x00010007 0x0043
+ 0x00010008 0x004b
+ 0x00010009 0x0053
+
+ 0x0002 0x0010
+ 0x00020001 0x0017
+ 0x00020002 0x001f
+ 0x00020003 0x0029
+ 0x00020004 0x0031
+ 0x00020005 0x003c
+ 0x00020006 0x0042
+ 0x00020007 0x004d
+ 0x00020008 0x0056
+
+ 0x0003 0x0012
+ 0x00030001 0x001d>;
+};
--
2.1.0.27.g96db324
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[PATCH V3] thermal: qoriq: Add thermal management support
This driver add thermal management support by enabling TMU (Thermal
Monitoring Unit) on QorIQ platform.
It's based on thermal of framework:
- Trip points defined in device tree.
- Cpufreq as cooling device registered in qoriq cpufreq driver.
Signed-off-by: Jia Hongtao <hongtao@freescale.com>
---
V3: Using thermal of framework.
drivers/thermal/Kconfig | 11 ++
drivers/thermal/Makefile| 1 +
drivers/thermal/qoriq_thermal.c | 267
3 files changed, 279 insertions(+)
create mode 100644 drivers/thermal/qoriq_thermal.c
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 0390044..c91041b 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -180,6 +180,17 @@ config IMX_THERMAL
cpufreq is used as the cooling device to throttle CPUs when the
passive trip is crossed.
+config QORIQ_THERMAL
+ tristate "Freescale QorIQ Thermal Monitoring Unit"
+ depends on CPU_THERMAL
+ depends on THERMAL_OF
+ default n
+ help
+ Enable thermal management based on Freescale QorIQ Thermal Monitoring
+ Unit (TMU). It supports one critical trip point and one passive trip
+ point. The cpufreq is used as the cooling device to throttle CPUs when
+ the passive trip is crossed.
+
config SPEAR_THERMAL
bool "SPEAr thermal sensor driver"
depends on PLAT_SPEAR
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index 26f1608..e55d703 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_DOVE_THERMAL)+= dove_thermal.o
obj-$(CONFIG_DB8500_THERMAL) += db8500_thermal.o
obj-$(CONFIG_ARMADA_THERMAL) += armada_thermal.o
obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
+obj-$(CONFIG_QORIQ_THERMAL)+= qoriq_thermal.o
obj-$(CONFIG_DB8500_CPUFREQ_COOLING) += db8500_cpufreq_cooling.o
obj-$(CONFIG_INTEL_POWERCLAMP) += intel_powerclamp.o
obj-$(CONFIG_X86_PKG_TEMP_THERMAL) += x86_pkg_temp_thermal.o
diff --git a/drivers/thermal/qoriq_thermal.c b/drivers/thermal/qoriq_thermal.c
new file mode 100644
index 000..7c2a3261
--- /dev/null
+++ b/drivers/thermal/qoriq_thermal.c
@@ -0,0 +1,267 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+/*
+ * Based on Freescale QorIQ Thermal Monitoring Unit (TMU)
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "thermal_core.h"
+
+#define SITES_MAX 16
+
+/*
+ * QorIQ TMU Registers
+ */
+struct qoriq_tmu_site_regs {
+ __be32 tritsr; /* Immediate Temperature Site Register */
+ __be32 tratsr; /* Average Temperature Site Register */
+ u8 res0[0x8];
+} __packed;
+
+struct qoriq_tmu_regs {
+ __be32 tmr; /* Mode Register */
+#define TMR_DISABLE0x0
+#define TMR_ME 0x8000
+#define TMR_ALPF 0x0c00
+#define TMR_MSITE 0x8000 /* Core temperature site */
+#define TMR_ALL(TMR_ME | TMR_ALPF | TMR_MSITE)
+ __be32 tsr; /* Status Register */
+ __be32 tmtmir; /* Temperature measurement interval Register */
+#define TMTMIR_DEFAULT 0x0007
+ u8 res0[0x14];
+ __be32 tier;/* Interrupt Enable Register */
+#define TIER_DISABLE 0x0
+ __be32 tidr;/* Interrupt Detect Register */
+ __be32 tiscr; /* Interrupt Site Capture Register */
+ __be32 ticscr; /* Interrupt Critical Site Capture Register */
+ u8 res1[0x10];
+ __be32 tmhtcrh; /* High Temperature Capture Register */
+ __be32 tmhtcrl; /* Low Temperature Capture Register */
+ u8 res2[0x8];
+ __be32 tmhtitr; /* High Temperature Immediate Threshold */
+ __be32 tmhtatr; /* High Temperature Average Threshold */
+ __be32 tmhtactr;/* High Temperature Average Crit Threshold */
+ u8 res3[0x24];
+ __be32 ttcfgr; /* Temperature Configuration Register */
+ __be32 tscfgr; /* Sensor Configuration Register */
+ u8 res4[0x78];
+ struct qoriq_tmu_site_regs site[SITES_MAX];
+ u8 res5[0x9f8];
+ __be32 ipbrr0; /* IP Block Revision Register 0 */
+ __be32 ipbrr1; /* IP Block Revision Register 1 */
+ u8 res6[0x310];
+ __be32 ttr0cr; /* Temperature Range 0 Control Register */
+ __
[PATCH] PowerPC: Move Freescale device tree files into fsl folder
It makes no sense that some Freescale device tree files are in fsl
directory while some others not. This patch move Freescale device tree
files into fsl folder. To do that the following two steps are made:
- Move Freescale device tree files into fsl folder.
- Update the include path in these files from "fsl/*.dtsi" to "*.dtsi".
Plese add "fsl/" prefix when you make dtb using Makefile.
Signed-off-by: Jia Hongtao <hongtao@freescale.com>
---
arch/powerpc/boot/dts/{ => fsl}/b4420qds.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/b4860qds.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/b4qds.dtsi | 2 +-
arch/powerpc/boot/dts/{ => fsl}/bsc9131rdb.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/bsc9131rdb.dtsi| 0
arch/powerpc/boot/dts/{ => fsl}/bsc9132qds.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/bsc9132qds.dtsi| 0
arch/powerpc/boot/dts/{ => fsl}/c293pcie.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/ge_imp3a.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/kmcoge4.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/mpc8536ds.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/mpc8536ds.dtsi | 0
arch/powerpc/boot/dts/{ => fsl}/mpc8536ds_36b.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/mpc8540ads.dts | 2 +-
arch/powerpc/boot/dts/{ => fsl}/mpc8541cds.dts | 2 +-
arch/powerpc/boot/dts/{ => fsl}/mpc8544ds.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/mpc8544ds.dtsi | 0
arch/powerpc/boot/dts/{ => fsl}/mpc8548cds.dtsi| 0
arch/powerpc/boot/dts/{ => fsl}/mpc8548cds_32b.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/mpc8548cds_36b.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/mpc8555cds.dts | 2 +-
arch/powerpc/boot/dts/{ => fsl}/mpc8560ads.dts | 2 +-
arch/powerpc/boot/dts/{ => fsl}/mpc8568mds.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/mpc8569mds.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/mpc8572ds.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/mpc8572ds.dtsi | 0
arch/powerpc/boot/dts/{ => fsl}/mpc8572ds_36b.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/mpc8572ds_camp_core0.dts | 0
arch/powerpc/boot/dts/{ => fsl}/mpc8572ds_camp_core1.dts | 0
arch/powerpc/boot/dts/{ => fsl}/mvme2500.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/oca4080.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1010rdb-pa.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1010rdb-pa.dtsi | 0
arch/powerpc/boot/dts/{ => fsl}/p1010rdb-pa_36b.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1010rdb-pb.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1010rdb-pb_36b.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1010rdb.dtsi | 0
arch/powerpc/boot/dts/{ => fsl}/p1010rdb_32b.dtsi | 0
arch/powerpc/boot/dts/{ => fsl}/p1010rdb_36b.dtsi | 0
arch/powerpc/boot/dts/{ => fsl}/p1020mbg-pc.dtsi | 0
arch/powerpc/boot/dts/{ => fsl}/p1020mbg-pc_32b.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1020mbg-pc_36b.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1020rdb-pc.dtsi | 0
arch/powerpc/boot/dts/{ => fsl}/p1020rdb-pc_32b.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1020rdb-pc_36b.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1020rdb-pc_camp_core0.dts | 0
arch/powerpc/boot/dts/{ => fsl}/p1020rdb-pc_camp_core1.dts | 0
arch/powerpc/boot/dts/{ => fsl}/p1020rdb-pd.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1020rdb.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1020rdb.dtsi | 0
arch/powerpc/boot/dts/{ => fsl}/p1020rdb_36b.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1020utm-pc.dtsi | 0
arch/powerpc/boot/dts/{ => fsl}/p1020utm-pc_32b.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1020utm-pc_36b.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1021mds.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1021rdb-pc.dtsi | 0
arch/powerpc/boot/dts/{ => fsl}/p1021rdb-pc_32b.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1021rdb-pc_36b.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1022ds.dtsi | 0
arch/powerpc/boot/dts/{ => fsl}/p1022ds_32b.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1022ds_36b.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1022rdk.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1023rdb.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1024rdb.dtsi | 0
arch
[PATCH] PowerPC: Move Freescale device tree files into fsl folder
It makes no sense that some Freescale device tree files are in fsl
directory while some others not. This patch move Freescale device tree
files into fsl folder. To do that the following two steps are made:
- Move Freescale device tree files into fsl folder.
- Update the include path in these files from "fsl/*.dtsi" to "*.dtsi".
Please add "fsl/" prefix when you make dtb using Makefile.
Signed-off-by: Jia Hongtao <hongtao@freescale.com>
---
arch/powerpc/boot/dts/{ => fsl}/b4420qds.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/b4860qds.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/b4qds.dtsi | 2 +-
arch/powerpc/boot/dts/{ => fsl}/bsc9131rdb.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/bsc9131rdb.dtsi| 0
arch/powerpc/boot/dts/{ => fsl}/bsc9132qds.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/bsc9132qds.dtsi| 0
arch/powerpc/boot/dts/{ => fsl}/c293pcie.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/ge_imp3a.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/kmcoge4.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/mpc8536ds.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/mpc8536ds.dtsi | 0
arch/powerpc/boot/dts/{ => fsl}/mpc8536ds_36b.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/mpc8540ads.dts | 2 +-
arch/powerpc/boot/dts/{ => fsl}/mpc8541cds.dts | 2 +-
arch/powerpc/boot/dts/{ => fsl}/mpc8544ds.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/mpc8544ds.dtsi | 0
arch/powerpc/boot/dts/{ => fsl}/mpc8548cds.dtsi| 0
arch/powerpc/boot/dts/{ => fsl}/mpc8548cds_32b.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/mpc8548cds_36b.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/mpc8555cds.dts | 2 +-
arch/powerpc/boot/dts/{ => fsl}/mpc8560ads.dts | 2 +-
arch/powerpc/boot/dts/{ => fsl}/mpc8568mds.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/mpc8569mds.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/mpc8572ds.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/mpc8572ds.dtsi | 0
arch/powerpc/boot/dts/{ => fsl}/mpc8572ds_36b.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/mpc8572ds_camp_core0.dts | 0
arch/powerpc/boot/dts/{ => fsl}/mpc8572ds_camp_core1.dts | 0
arch/powerpc/boot/dts/{ => fsl}/mvme2500.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/oca4080.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1010rdb-pa.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1010rdb-pa.dtsi | 0
arch/powerpc/boot/dts/{ => fsl}/p1010rdb-pa_36b.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1010rdb-pb.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1010rdb-pb_36b.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1010rdb.dtsi | 0
arch/powerpc/boot/dts/{ => fsl}/p1010rdb_32b.dtsi | 0
arch/powerpc/boot/dts/{ => fsl}/p1010rdb_36b.dtsi | 0
arch/powerpc/boot/dts/{ => fsl}/p1020mbg-pc.dtsi | 0
arch/powerpc/boot/dts/{ => fsl}/p1020mbg-pc_32b.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1020mbg-pc_36b.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1020rdb-pc.dtsi | 0
arch/powerpc/boot/dts/{ => fsl}/p1020rdb-pc_32b.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1020rdb-pc_36b.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1020rdb-pc_camp_core0.dts | 0
arch/powerpc/boot/dts/{ => fsl}/p1020rdb-pc_camp_core1.dts | 0
arch/powerpc/boot/dts/{ => fsl}/p1020rdb-pd.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1020rdb.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1020rdb.dtsi | 0
arch/powerpc/boot/dts/{ => fsl}/p1020rdb_36b.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1020utm-pc.dtsi | 0
arch/powerpc/boot/dts/{ => fsl}/p1020utm-pc_32b.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1020utm-pc_36b.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1021mds.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1021rdb-pc.dtsi | 0
arch/powerpc/boot/dts/{ => fsl}/p1021rdb-pc_32b.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1021rdb-pc_36b.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1022ds.dtsi | 0
arch/powerpc/boot/dts/{ => fsl}/p1022ds_32b.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1022ds_36b.dts| 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1022rdk.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1023rdb.dts | 4 ++--
arch/powerpc/boot/dts/{ => fsl}/p1024rdb.dtsi | 0
arch
[PATCH V2] QorIQ/TMU: add thermal management support based on TMU
It supports one critical trip point and one passive trip point.
The cpufreq is used as the cooling device to throttle CPUs when
the passive trip is crossed.
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
This patch based on:
http://patchwork.ozlabs.org/patch/482987/
Changes for V2:
* Add tmu-range parse.
* Use default trend hook.
* Using latest thermal_zone_bind_cooling_device API.
* Add calibration check during initialization.
* Disable/enalbe device when suspend/resume.
drivers/thermal/Kconfig | 11 ++
drivers/thermal/Makefile| 1 +
drivers/thermal/qoriq_thermal.c | 406
3 files changed, 418 insertions(+)
create mode 100644 drivers/thermal/qoriq_thermal.c
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 118938e..a200745 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -180,6 +180,17 @@ config IMX_THERMAL
cpufreq is used as the cooling device to throttle CPUs when the
passive trip is crossed.
+config QORIQ_THERMAL
+ tristate Freescale QorIQ Thermal Monitoring Unit
+ depends on CPU_THERMAL
+ depends on OF
+ default n
+ help
+ Enable thermal management based on Freescale QorIQ Thermal Monitoring
+ Unit (TMU). It supports one critical trip point and one passive trip
+ point. The cpufreq is used as the cooling device to throttle CPUs when
+ the passive trip is crossed.
+
config SPEAR_THERMAL
bool SPEAr thermal sensor driver
depends on PLAT_SPEAR
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index 535dfee..8c25859 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_DOVE_THERMAL)+= dove_thermal.o
obj-$(CONFIG_DB8500_THERMAL) += db8500_thermal.o
obj-$(CONFIG_ARMADA_THERMAL) += armada_thermal.o
obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
+obj-$(CONFIG_QORIQ_THERMAL)+= qoriq_thermal.o
obj-$(CONFIG_DB8500_CPUFREQ_COOLING) += db8500_cpufreq_cooling.o
obj-$(CONFIG_INTEL_POWERCLAMP) += intel_powerclamp.o
obj-$(CONFIG_X86_PKG_TEMP_THERMAL) += x86_pkg_temp_thermal.o
diff --git a/drivers/thermal/qoriq_thermal.c b/drivers/thermal/qoriq_thermal.c
new file mode 100644
index 000..0694f42
--- /dev/null
+++ b/drivers/thermal/qoriq_thermal.c
@@ -0,0 +1,406 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+/*
+ * Based on Freescale QorIQ Thermal Monitoring Unit (TMU)
+ */
+#include linux/cpufreq.h
+#include linux/cpu_cooling.h
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/err.h
+#include linux/io.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/thermal.h
+
+#define SITES_MAX 16
+
+#define TMU_TEMP_PASSIVE 85000
+#define TMU_TEMP_CRITICAL 95000
+
+#define TMU_PASSIVE_DELAY 1000/* Milliseconds */
+#define TMU_POLLING_DELAY 5000
+
+/* The driver supports 1 passive trip point and 1 critical trip point */
+enum tmu_thermal_trip {
+ TMU_TRIP_PASSIVE,
+ TMU_TRIP_CRITICAL,
+ TMU_TRIP_NUM,
+};
+
+/*
+ * QorIQ TMU Registers
+ */
+struct qoriq_tmu_site_regs {
+ __be32 tritsr; /* Immediate Temperature Site Register */
+ __be32 tratsr; /* Average Temperature Site Register */
+ u8 res0[0x8];
+} __packed;
+
+struct qoriq_tmu_regs {
+ __be32 tmr; /* Mode Register */
+#define TMR_DISABLE0x0
+#define TMR_ME 0x8000
+#define TMR_ALPF 0x0c00
+#define TMR_MSITE 0x8000
+#define TMR_ALL(TMR_ME | TMR_ALPF | TMR_MSITE)
+ __be32 tsr; /* Status Register */
+ __be32 tmtmir; /* Temperature measurement interval Register */
+#define TMTMIR_DEFAULT 0x0007
+ u8 res0[0x14];
+ __be32 tier;/* Interrupt Enable Register */
+#define TIER_DISABLE 0x0
+ __be32 tidr;/* Interrupt Detect Register */
+ __be32 tiscr; /* Interrupt Site Capture Register */
+ __be32 ticscr; /* Interrupt Critical Site Capture Register */
+ u8 res1[0x10];
+ __be32 tmhtcrh; /* High Temperature Capture Register */
+ __be32 tmhtcrl; /* Low Temperature Capture Register */
+ u8 res2[0x8];
+ __be32 tmhtitr; /* High Temperature Immediate Threshold */
+ __be32 tmhtatr; /* High Temperature Average Threshold */
+ __be32 tmhtactr
[PATCH V3] QorIQ/TMU: add TMU node to device tree for QorIQ T1040
This is Thermal Monitoring Unit for QorIQ platform.
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
Changes of V3:
* Put TMU node directly into t1040si-post.dtsi file.
* Add fsl,tmu-range property.
* Change calibration property to fsl,tmu-calibration.
* Update the calibration data.
Changes of V2:
* Provide more details on compatible and calibration properties.
.../devicetree/bindings/thermal/qoriq-thermal.txt | 63 ++
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi| 42 +++
2 files changed, 105 insertions(+)
create mode 100644 Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
new file mode 100644
index 000..2bc9cb3
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
@@ -0,0 +1,63 @@
+* Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs
+
+Required properties:
+- compatible : Must include fsl,qoriq-tmu. The version of the device is
+ determined by the TMU IP Block Revision Register (IPBRR0) at
+ offset 0x0BF8.
+ Table of correspondences between IPBRR0 values and example chips:
+ Value Device
+ -- -
+ 0x01900102 T1040
+- reg : Address range of TMU registers.
+- interrupts : Contains the interrupt for TMU.
+- fsl,tmu-range : Temperature range for TMU. Including the starting
+ temperature and number of calibration points for each range.
+- fsl,tmu-calibration : Calibration table for TMU. This is required to
+ determine what a specific sensor reading translates to in degrees
+ Celsius. There are four calibration ranges, for each range we need
+ a couple of calibration data formatted like TTCFGR, TSCFGR.
+ Freescale provides the data required.
+
+Example:
+
+tmu@f {
+ compatible = fsl,qoriq-tmu;
+ reg = 0xf 0x1000;
+ interrupts = 18 2 0 0;
+ fsl,tmu-range = 0x000a 0x00090026 0x0008004a 0x0001006a;
+ fsl,tmu-calibration = 0x 0x0025
+ 0x0001 0x0028
+ 0x0002 0x002d
+ 0x0003 0x0031
+ 0x0004 0x0036
+ 0x0005 0x003a
+ 0x0006 0x0040
+ 0x0007 0x0044
+ 0x0008 0x004a
+ 0x0009 0x004f
+ 0x000a 0x0054
+
+ 0x0001 0x000d
+ 0x00010001 0x0013
+ 0x00010002 0x0019
+ 0x00010003 0x001f
+ 0x00010004 0x0025
+ 0x00010005 0x002d
+ 0x00010006 0x0033
+ 0x00010007 0x0043
+ 0x00010008 0x004b
+ 0x00010009 0x0053
+
+ 0x0002 0x0010
+ 0x00020001 0x0017
+ 0x00020002 0x001f
+ 0x00020003 0x0029
+ 0x00020004 0x0031
+ 0x00020005 0x003c
+ 0x00020006 0x0042
+ 0x00020007 0x004d
+ 0x00020008 0x0056
+
+ 0x0003 0x0012
+ 0x00030001 0x001d;
+};
diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
index 5cc01be..6d9ca4d 100644
--- a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -407,6 +407,48 @@
reg= 0xea000 0x4000;
};
+ tmu@f {
+ compatible = fsl,qoriq-tmu;
+ reg = 0xf 0x1000;
+ interrupts = 18 2 0 0;
+ fsl,tmu-range = 0x000a 0x00090026 0x0008004a 0x0001006a;
+ fsl,tmu-calibration = 0x 0x0025
+ 0x0001 0x0028
+ 0x0002 0x002d
+ 0x0003 0x0031
+ 0x0004 0x0036
+ 0x0005 0x003a
+ 0x0006 0x0040
+ 0x0007 0x0044
+ 0x0008 0x004a
+ 0x0009 0x004f
[PATCH V2] QorIQ/TMU: add TMU node to device tree for QorIQ T104x
This is Thermal Monitoring Unit for QorIQ platform.
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
Changes from V1:
* Provide more details on compatible and calibration properties.
.../devicetree/bindings/thermal/qoriq-thermal.txt | 68 ++
arch/powerpc/boot/dts/fsl/qoriq-tmu-t104xsi.dtsi | 82 ++
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi| 1 +
3 files changed, 151 insertions(+)
create mode 100644 Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-tmu-t104xsi.dtsi
diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
new file mode 100644
index 000..48e7fff
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
@@ -0,0 +1,68 @@
+* Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs
+
+Required properties:
+- compatible : Must include fsl,qoriq-tmu. The version of the device is
+ determined by the TMU IP Block Revision Register (IPBRR0) at
+ offset 0x0BF8.
+ Table of correspondences between IPBRR0 values and example chips:
+ Value Device
+ -- -
+ 0x01900102 T1040
+- reg : Address range of TMU registers.
+- interrupts : Contains the interrupt for TMU.
+- calibration : Calibration table for TMU. This is required to determine
+ what a specific sensor reading translates to in degrees Celsius.
+ There are four calibration config ranges, for each range we need
+ a couple of calibration data formatted like TTCFGR, TSCFGR.
+ Freescale provides the data required.
+
+Example:
+
+tmu@f {
+ compatible = fsl,qoriq-tmu;
+ reg = 0xf 0x1000;
+ interrupts = 18 2 0 0;
+ calibration = 0x 0x000f
+ 0x0001 0x0017
+ 0x0002 0x001e
+ 0x0003 0x0026
+ 0x0004 0x002e
+ 0x0005 0x0035
+ 0x0006 0x003d
+ 0x0007 0x0044
+ 0x0008 0x004c
+ 0x0009 0x0053
+ 0x000a 0x005b
+ 0x000b 0x0062
+
+ 0x0001 0x0011
+ 0x00010001 0x0019
+ 0x00010002 0x0021
+ 0x00010003 0x002a
+ 0x00010004 0x0032
+ 0x00010005 0x003a
+ 0x00010006 0x0042
+ 0x00010007 0x004b
+ 0x00010008 0x0053
+ 0x00010009 0x005b
+ 0x0001000a 0x0063
+
+ 0x0002 0x0012
+ 0x00020001 0x001b
+ 0x00020002 0x0024
+ 0x00020003 0x002c
+ 0x00020004 0x0035
+ 0x00020005 0x003d
+ 0x00020006 0x0046
+ 0x00020007 0x004e
+ 0x00020008 0x0057
+
+ 0x0003 0x0009
+ 0x00030001 0x0011
+ 0x00030002 0x0019
+ 0x00030003 0x0021
+ 0x00030004 0x0029
+ 0x00030005 0x0031
+ 0x00030006 0x0039
+ 0x00030007 0x0041;
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-tmu-t104xsi.dtsi
b/arch/powerpc/boot/dts/fsl/qoriq-tmu-t104xsi.dtsi
new file mode 100644
index 000..d85c77d
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-tmu-t104xsi.dtsi
@@ -0,0 +1,82 @@
+/*
+ * QorIQ TMU device tree stub [ controller @ offset 0xf ]
+ *
+ * Copyright 2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your
[PATCH] QorIQ/TMU: add thermal management support based on TMU
It supports one critical trip point and one passive trip point.
The cpufreq is used as the cooling device to throttle CPUs when
the passive trip is crossed.
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
drivers/thermal/Kconfig | 11 ++
drivers/thermal/Makefile| 1 +
drivers/thermal/qoriq_thermal.c | 405
3 files changed, 417 insertions(+)
create mode 100644 drivers/thermal/qoriq_thermal.c
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index af40db0..c0a8bd1 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -147,6 +147,17 @@ config IMX_THERMAL
cpufreq is used as the cooling device to throttle CPUs when the
passive trip is crossed.
+config QORIQ_THERMAL
+ tristate Freescale QorIQ Thermal Monitoring Unit
+ depends on CPU_THERMAL
+ depends on OF
+ default n
+ help
+ Enable thermal management based on Freescale QorIQ Thermal Monitoring
+ Unit (TMU). It supports one critical trip point and one passive trip
+ point. The cpufreq is used as the cooling device to throttle CPUs when
+ the passive trip is crossed.
+
config SPEAR_THERMAL
bool SPEAr thermal sensor driver
depends on PLAT_SPEAR
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index fa0dc48..7de4847 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_DOVE_THERMAL)+= dove_thermal.o
obj-$(CONFIG_DB8500_THERMAL) += db8500_thermal.o
obj-$(CONFIG_ARMADA_THERMAL) += armada_thermal.o
obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
+obj-$(CONFIG_QORIQ_THERMAL)+= qoriq_thermal.o
obj-$(CONFIG_DB8500_CPUFREQ_COOLING) += db8500_cpufreq_cooling.o
obj-$(CONFIG_INTEL_POWERCLAMP) += intel_powerclamp.o
obj-$(CONFIG_X86_PKG_TEMP_THERMAL) += x86_pkg_temp_thermal.o
diff --git a/drivers/thermal/qoriq_thermal.c b/drivers/thermal/qoriq_thermal.c
new file mode 100644
index 000..f5d3a2c
--- /dev/null
+++ b/drivers/thermal/qoriq_thermal.c
@@ -0,0 +1,405 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+/*
+ * Based on Freescale QorIQ Thermal Monitoring Unit (TMU)
+ */
+#include linux/cpufreq.h
+#include linux/cpu_cooling.h
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/err.h
+#include linux/io.h
+#include linux/of.h
+#include linux/thermal.h
+
+#define SITES_MAX 16
+
+#define TMU_TEMP_PASSIVE 85000
+#define TMU_TEMP_CRITICAL 95000
+
+#define TMU_PASSIVE_DELAY 1000/* Milliseconds */
+#define TMU_POLLING_DELAY 5000
+
+/* The driver supports 1 passive trip point and 1 critical trip point */
+enum tmu_thermal_trip {
+ TMU_TRIP_PASSIVE,
+ TMU_TRIP_CRITICAL,
+ TMU_TRIP_NUM,
+};
+
+/*
+ * QorIQ TMU Registers
+ */
+struct qoriq_tmu_site_regs {
+ __be32 tritsr; /* Immediate Temperature Site Register */
+ __be32 tratsr; /* Average Temperature Site Register */
+ u8 res0[0x8];
+} __packed;
+
+struct qoriq_tmu_regs {
+ __be32 tmr; /* Mode Register */
+#define TMR_DISABLE0x0
+#define TMR_ME 0x8000
+#define TMR_ALPF 0x0c00
+#define TMR_MSITE 0x8000
+#define TMR_ALL(TMR_ME | TMR_ALPF | TMR_MSITE)
+ __be32 tsr; /* Status Register */
+ __be32 tmtmir; /* Temperature measurement interval Register */
+#define TMTMIR_DEFAULT 0x0007
+ u8 res0[0x14];
+ __be32 tier;/* Interrupt Enable Register */
+#define TIER_DISABLE 0x0
+ __be32 tidr;/* Interrupt Detect Register */
+ __be32 tiscr; /* Interrupt Site Capture Register */
+ __be32 ticscr; /* Interrupt Critical Site Capture Register */
+ u8 res1[0x10];
+ __be32 tmhtcrh; /* High Temperature Capture Register */
+ __be32 tmhtcrl; /* Low Temperature Capture Register */
+ u8 res2[0x8];
+ __be32 tmhtitr; /* High Temperature Immediate Threshold */
+ __be32 tmhtatr; /* High Temperature Average Threshold */
+ __be32 tmhtactr;/* High Temperature Average Crit Threshold */
+ u8 res3[0x24];
+ __be32 ttcfgr; /* Temperature Configuration Register */
+ __be32 tscfgr; /* Sensor Configuration Register */
+ u8 res4[0x78];
+ struct qoriq_tmu_site_regs site[SITES_MAX];
+ u8 res5
[PATCH] QorIQ/TMU: add TMU node to device tree for QorIQ T104x
This is Thermal Monitoring Unit for QorIQ platform.
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
.../devicetree/bindings/thermal/qoriq-thermal.txt | 58 +++
arch/powerpc/boot/dts/fsl/qoriq-tmu-t104xsi.dtsi | 82 ++
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi| 1 +
3 files changed, 141 insertions(+)
create mode 100644 Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-tmu-t104xsi.dtsi
diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
new file mode 100644
index 000..dfc17fa
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
@@ -0,0 +1,58 @@
+* Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs
+
+Required properties:
+- compatible : fsl,qoriq-tmu.
+- reg : address range of TMU registers.
+- interrupts : should contain the interrupt for TMU.
+- calibration : calibration table for TMU.
+
+Example:
+
+tmu@f {
+ compatible = fsl,qoriq-tmu;
+ reg = 0xf 0x1000;
+ interrupts = 18 2 0 0;
+ calibration = 0x 0x000f
+ 0x0001 0x0017
+ 0x0002 0x001e
+ 0x0003 0x0026
+ 0x0004 0x002e
+ 0x0005 0x0035
+ 0x0006 0x003d
+ 0x0007 0x0044
+ 0x0008 0x004c
+ 0x0009 0x0053
+ 0x000a 0x005b
+ 0x000b 0x0062
+
+ 0x0001 0x0011
+ 0x00010001 0x0019
+ 0x00010002 0x0021
+ 0x00010003 0x002a
+ 0x00010004 0x0032
+ 0x00010005 0x003a
+ 0x00010006 0x0042
+ 0x00010007 0x004b
+ 0x00010008 0x0053
+ 0x00010009 0x005b
+ 0x0001000a 0x0063
+
+ 0x0002 0x0012
+ 0x00020001 0x001b
+ 0x00020002 0x0024
+ 0x00020003 0x002c
+ 0x00020004 0x0035
+ 0x00020005 0x003d
+ 0x00020006 0x0046
+ 0x00020007 0x004e
+ 0x00020008 0x0057
+
+ 0x0003 0x0009
+ 0x00030001 0x0011
+ 0x00030002 0x0019
+ 0x00030003 0x0021
+ 0x00030004 0x0029
+ 0x00030005 0x0031
+ 0x00030006 0x0039
+ 0x00030007 0x0041;
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-tmu-t104xsi.dtsi
b/arch/powerpc/boot/dts/fsl/qoriq-tmu-t104xsi.dtsi
new file mode 100644
index 000..d85c77d
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-tmu-t104xsi.dtsi
@@ -0,0 +1,82 @@
+/*
+ * QorIQ TMU device tree stub [ controller @ offset 0xf ]
+ *
+ * Copyright 2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE
[PATCH 2/2] powerpc: Enable power monitor feature in defconfig for supported platforms
Signed-off-by: Jia Hongtao hongtao@freescale.com --- arch/powerpc/configs/corenet32_smp_defconfig | 1 + arch/powerpc/configs/corenet64_smp_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig index 7370990..36970c8 100644 --- a/arch/powerpc/configs/corenet32_smp_defconfig +++ b/arch/powerpc/configs/corenet32_smp_defconfig @@ -119,6 +119,7 @@ CONFIG_SPI_GPIO=y CONFIG_SPI_FSL_SPI=y CONFIG_SPI_FSL_ESPI=y CONFIG_SENSORS_LM90=y +CONFIG_SENSORS_INA2XX=y CONFIG_USB_HID=m CONFIG_USB=y CONFIG_USB_MON=y diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig index 4cfc3e8..6194a11 100644 --- a/arch/powerpc/configs/corenet64_smp_defconfig +++ b/arch/powerpc/configs/corenet64_smp_defconfig @@ -104,6 +104,7 @@ CONFIG_SPI_GPIO=y CONFIG_SPI_FSL_SPI=y CONFIG_SPI_FSL_ESPI=y CONFIG_SENSORS_LM90=y +CONFIG_SENSORS_INA2XX=y CONFIG_USB_HID=m CONFIG_USB=y CONFIG_USB_MON=y -- 2.1.0.27.g96db324 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/2] powerpc: Enable thermal monitor feature in defconfig for supported platforms
Signed-off-by: Jia Hongtao hongtao@freescale.com --- arch/powerpc/configs/corenet32_smp_defconfig | 2 +- arch/powerpc/configs/corenet64_smp_defconfig | 2 +- arch/powerpc/configs/mpc85xx_defconfig | 3 +-- arch/powerpc/configs/mpc85xx_smp_defconfig | 2 +- 4 files changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig index ca7957b..7370990 100644 --- a/arch/powerpc/configs/corenet32_smp_defconfig +++ b/arch/powerpc/configs/corenet32_smp_defconfig @@ -118,7 +118,7 @@ CONFIG_SPI=y CONFIG_SPI_GPIO=y CONFIG_SPI_FSL_SPI=y CONFIG_SPI_FSL_ESPI=y -# CONFIG_HWMON is not set +CONFIG_SENSORS_LM90=y CONFIG_USB_HID=m CONFIG_USB=y CONFIG_USB_MON=y diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig index 04737aa..4cfc3e8 100644 --- a/arch/powerpc/configs/corenet64_smp_defconfig +++ b/arch/powerpc/configs/corenet64_smp_defconfig @@ -103,7 +103,7 @@ CONFIG_SPI=y CONFIG_SPI_GPIO=y CONFIG_SPI_FSL_SPI=y CONFIG_SPI_FSL_ESPI=y -# CONFIG_HWMON is not set +CONFIG_SENSORS_LM90=y CONFIG_USB_HID=m CONFIG_USB=y CONFIG_USB_MON=y diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig index 8535c34..6ecf7bd 100644 --- a/arch/powerpc/configs/mpc85xx_defconfig +++ b/arch/powerpc/configs/mpc85xx_defconfig @@ -150,8 +150,7 @@ CONFIG_SPI=y CONFIG_SPI_FSL_SPI=y CONFIG_SPI_FSL_ESPI=y CONFIG_GPIO_MPC8XXX=y -CONFIG_HWMON=m -CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_LM90=y CONFIG_FB=y CONFIG_FB_FSL_DIU=y # CONFIG_VGA_CONSOLE is not set diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig index c45ad2e..b6c7111 100644 --- a/arch/powerpc/configs/mpc85xx_smp_defconfig +++ b/arch/powerpc/configs/mpc85xx_smp_defconfig @@ -143,7 +143,7 @@ CONFIG_SPI=y CONFIG_SPI_FSL_SPI=y CONFIG_SPI_FSL_ESPI=y CONFIG_GPIO_MPC8XXX=y -# CONFIG_HWMON is not set +CONFIG_SENSORS_LM90=y CONFIG_FB=y CONFIG_FB_FSL_DIU=y # CONFIG_VGA_CONSOLE is not set -- 2.1.0.27.g96db324 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V3] powerpc/85xx: workaround for chips with MSI hardware errata
From: Hongtao Jia hongtao@freescale.com
The MPIC version 2.0 has a MSI errata (errata PIC1 of mpc8544), It causes
that neither MSI nor MSI-X can work fine. This is a workaround to allow
MSI-X to function properly.
Signed-off-by: Liu Shuo soniccat@gmail.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
Changes for V3:
* remove mpic_has_erratum_pic1() function. Test erratum directly.
* rebase on latest kernel update.
Changes for V2:
* change the name of function mpic_has_errata() to mpic_has_erratum_pic1().
* move MSI_HW_ERRATA_ENDIAN define to fsl_msi.h with all other defines.
arch/powerpc/sysdev/fsl_msi.c | 29 ++---
arch/powerpc/sysdev/fsl_msi.h | 2 ++
2 files changed, 28 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index 4bbb4b8..f086c6f 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -162,7 +162,17 @@ static void fsl_compose_msi_msg(struct pci_dev *pdev, int
hwirq,
msg-address_lo = lower_32_bits(address);
msg-address_hi = upper_32_bits(address);
- msg-data = hwirq;
+ /*
+* MPIC version 2.0 has erratum PIC1. It causes
+* that neither MSI nor MSI-X can work fine.
+* This is a workaround to allow MSI-X to function
+* properly. It only works for MSI-X, we prevent
+* MSI on buggy chips in fsl_setup_msi_irqs().
+*/
+ if (msi_data-feature MSI_HW_ERRATA_ENDIAN)
+ msg-data = __swab32(hwirq);
+ else
+ msg-data = hwirq;
pr_debug(%s: allocated srs: %d, ibs: %d\n, __func__,
(hwirq msi_data-srs_shift) MSI_SRS_MASK,
@@ -180,8 +190,16 @@ static int fsl_setup_msi_irqs(struct pci_dev *pdev, int
nvec, int type)
struct msi_msg msg;
struct fsl_msi *msi_data;
- if (type == PCI_CAP_ID_MSIX)
- pr_debug(fslmsi: MSI-X untested, trying anyway.\n);
+ if (type == PCI_CAP_ID_MSI) {
+ /*
+* MPIC version 2.0 has erratum PIC1. For now MSI
+* could not work. So check to prevent MSI from
+* being used on the board with this erratum.
+*/
+ list_for_each_entry(msi_data, msi_head, list)
+ if (msi_data-feature MSI_HW_ERRATA_ENDIAN)
+ return -EINVAL;
+ }
/*
* If the PCI node has an fsl,msi property, then we need to use it
@@ -446,6 +464,11 @@ static int fsl_of_msi_probe(struct platform_device *dev)
msi-feature = features-fsl_pic_ip;
+ /* For erratum PIC1 on MPIC version 2.0*/
+ if ((features-fsl_pic_ip FSL_PIC_IP_MASK) == FSL_PIC_IP_MPIC
+(fsl_mpic_primary_get_version() == 0x0200))
+ msi-feature |= MSI_HW_ERRATA_ENDIAN;
+
/*
* Remember the phandle, so that we can match with any PCI nodes
* that have an fsl,msi property.
diff --git a/arch/powerpc/sysdev/fsl_msi.h b/arch/powerpc/sysdev/fsl_msi.h
index 420cfcb..a67359d 100644
--- a/arch/powerpc/sysdev/fsl_msi.h
+++ b/arch/powerpc/sysdev/fsl_msi.h
@@ -27,6 +27,8 @@
#define FSL_PIC_IP_IPIC 0x0002
#define FSL_PIC_IP_VMPIC 0x0003
+#define MSI_HW_ERRATA_ENDIAN 0x0010
+
struct fsl_msi_cascade_data;
struct fsl_msi {
--
2.1.0.27.g96db324
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[PATCH 2/2] powerpc: Add INA220 to device tree for supported boards
Including: P3041DS P5020DS P5040DS B4QDS
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
arch/powerpc/boot/dts/b4qds.dtsi | 12
arch/powerpc/boot/dts/p3041ds.dts | 20
arch/powerpc/boot/dts/p5020ds.dts | 20
arch/powerpc/boot/dts/p5040ds.dts | 20
4 files changed, 72 insertions(+)
diff --git a/arch/powerpc/boot/dts/b4qds.dtsi b/arch/powerpc/boot/dts/b4qds.dtsi
index bccc986..e5bde0b 100644
--- a/arch/powerpc/boot/dts/b4qds.dtsi
+++ b/arch/powerpc/boot/dts/b4qds.dtsi
@@ -153,6 +153,18 @@
};
};
+ i2c@2 {
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x2;
+
+ ina220@40 {
+ compatible = ti,ina220;
+ reg = 0x40;
+ shunt-resistor = 1000;
+ };
+ };
+
i2c@3 {
#address-cells = 1;
#size-cells = 0;
diff --git a/arch/powerpc/boot/dts/p3041ds.dts
b/arch/powerpc/boot/dts/p3041ds.dts
index 2fed3bc..394ea9c 100644
--- a/arch/powerpc/boot/dts/p3041ds.dts
+++ b/arch/powerpc/boot/dts/p3041ds.dts
@@ -98,6 +98,26 @@
reg = 0x68;
interrupts = 0x1 0x1 0 0;
};
+ ina220@40 {
+ compatible = ti,ina220;
+ reg = 0x40;
+ shunt-resistor = 1000;
+ };
+ ina220@41 {
+ compatible = ti,ina220;
+ reg = 0x41;
+ shunt-resistor = 1000;
+ };
+ ina220@44 {
+ compatible = ti,ina220;
+ reg = 0x44;
+ shunt-resistor = 1000;
+ };
+ ina220@45 {
+ compatible = ti,ina220;
+ reg = 0x45;
+ shunt-resistor = 1000;
+ };
adt7461@4c {
compatible = adi,adt7461;
reg = 0x4c;
diff --git a/arch/powerpc/boot/dts/p5020ds.dts
b/arch/powerpc/boot/dts/p5020ds.dts
index 2869fea..b7f3057 100644
--- a/arch/powerpc/boot/dts/p5020ds.dts
+++ b/arch/powerpc/boot/dts/p5020ds.dts
@@ -98,6 +98,26 @@
reg = 0x68;
interrupts = 0x1 0x1 0 0;
};
+ ina220@40 {
+ compatible = ti,ina220;
+ reg = 0x40;
+ shunt-resistor = 1000;
+ };
+ ina220@41 {
+ compatible = ti,ina220;
+ reg = 0x41;
+ shunt-resistor = 1000;
+ };
+ ina220@44 {
+ compatible = ti,ina220;
+ reg = 0x44;
+ shunt-resistor = 1000;
+ };
+ ina220@45 {
+ compatible = ti,ina220;
+ reg = 0x45;
+ shunt-resistor = 1000;
+ };
adt7461@4c {
compatible = adi,adt7461;
reg = 0x4c;
diff --git a/arch/powerpc/boot/dts/p5040ds.dts
b/arch/powerpc/boot/dts/p5040ds.dts
index 860b5cc..7e04bf4 100644
--- a/arch/powerpc/boot/dts/p5040ds.dts
+++ b/arch/powerpc/boot/dts/p5040ds.dts
@@ -95,6 +95,26 @@
reg = 0x68;
interrupts = 0x1 0x1 0 0;
};
+ ina220@40 {
+ compatible = ti,ina220;
+ reg = 0x40;
+ shunt-resistor = 1000;
+ };
+ ina220@41 {
+ compatible = ti,ina220;
+ reg = 0x41;
+ shunt-resistor = 1000;
+ };
+ ina220@44 {
+ compatible = ti,ina220;
+ reg = 0x44
[PATCH 1/2] powerpc: Add ADT7461 to device tree for supported boards
Including: T104xRDB T208xQDS B4QDS
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
arch/powerpc/boot/dts/b4qds.dtsi| 11 +++
arch/powerpc/boot/dts/t104xrdb.dtsi | 7 +++
arch/powerpc/boot/dts/t208xqds.dtsi | 11 +++
3 files changed, 29 insertions(+)
diff --git a/arch/powerpc/boot/dts/b4qds.dtsi b/arch/powerpc/boot/dts/b4qds.dtsi
index 8b47edc..bccc986 100644
--- a/arch/powerpc/boot/dts/b4qds.dtsi
+++ b/arch/powerpc/boot/dts/b4qds.dtsi
@@ -152,6 +152,17 @@
reg = 0x68;
};
};
+
+ i2c@3 {
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x3;
+
+ adt7461@4c {
+ compatible = adi,adt7461;
+ reg = 0x4c;
+ };
+ };
};
};
diff --git a/arch/powerpc/boot/dts/t104xrdb.dtsi
b/arch/powerpc/boot/dts/t104xrdb.dtsi
index 1cf0f3c..187add8 100644
--- a/arch/powerpc/boot/dts/t104xrdb.dtsi
+++ b/arch/powerpc/boot/dts/t104xrdb.dtsi
@@ -83,6 +83,13 @@
};
};
+ i2c@118000 {
+ adt7461@4c {
+ compatible = adi,adt7461;
+ reg = 0x4c;
+ };
+ };
+
i2c@118100 {
pca9546@77 {
compatible = nxp,pca9546;
diff --git a/arch/powerpc/boot/dts/t208xqds.dtsi
b/arch/powerpc/boot/dts/t208xqds.dtsi
index 555dc6e..5906183 100644
--- a/arch/powerpc/boot/dts/t208xqds.dtsi
+++ b/arch/powerpc/boot/dts/t208xqds.dtsi
@@ -169,6 +169,17 @@
shunt-resistor = 1000;
};
};
+
+ i2c@3 {
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x3;
+
+ adt7461@4c {
+ compatible = adi,adt7461;
+ reg = 0x4c;
+ };
+ };
};
};
--
2.1.0.27.g96db324
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[PATCH V3] powerpc: Add I2C bus multiplexer node for B4 and T4240QDS
In both B4 and T4240QDS platform PCA9547 I2C bus multiplexer is used.
The sub-nodes are also reorganized according to right I2C topology.
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
V3 change log:
* Change channel to i2c based on i2c-mux binding.
* Update vendor from philips to nxp.
V2 change log:
* Reorganized the sub-nodes under I2C multiplexer to represent right topology.
arch/powerpc/boot/dts/b4qds.dtsi | 51 +---
arch/powerpc/boot/dts/t4240qds.dts | 69 ++
2 files changed, 73 insertions(+), 47 deletions(-)
diff --git a/arch/powerpc/boot/dts/b4qds.dtsi b/arch/powerpc/boot/dts/b4qds.dtsi
index e6d2f8f..8b47edc 100644
--- a/arch/powerpc/boot/dts/b4qds.dtsi
+++ b/arch/powerpc/boot/dts/b4qds.dtsi
@@ -120,25 +120,38 @@
};
i2c@118000 {
- eeprom@50 {
- compatible = at24,24c64;
- reg = 0x50;
- };
- eeprom@51 {
- compatible = at24,24c256;
- reg = 0x51;
- };
- eeprom@53 {
- compatible = at24,24c256;
- reg = 0x53;
- };
- eeprom@57 {
- compatible = at24,24c256;
- reg = 0x57;
- };
- rtc@68 {
- compatible = dallas,ds3232;
- reg = 0x68;
+ mux@77 {
+ compatible = nxp,pca9547;
+ reg = 0x77;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ i2c@0 {
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0;
+
+ eeprom@50 {
+ compatible = at24,24c64;
+ reg = 0x50;
+ };
+ eeprom@51 {
+ compatible = at24,24c256;
+ reg = 0x51;
+ };
+ eeprom@53 {
+ compatible = at24,24c256;
+ reg = 0x53;
+ };
+ eeprom@57 {
+ compatible = at24,24c256;
+ reg = 0x57;
+ };
+ rtc@68 {
+ compatible = dallas,ds3232;
+ reg = 0x68;
+ };
+ };
};
};
diff --git a/arch/powerpc/boot/dts/t4240qds.dts
b/arch/powerpc/boot/dts/t4240qds.dts
index 0555976..a35508f 100644
--- a/arch/powerpc/boot/dts/t4240qds.dts
+++ b/arch/powerpc/boot/dts/t4240qds.dts
@@ -118,34 +118,47 @@
};
i2c@118000 {
- eeprom@51 {
- compatible = at24,24c256;
- reg = 0x51;
- };
- eeprom@52 {
- compatible = at24,24c256;
- reg = 0x52;
- };
- eeprom@53 {
- compatible = at24,24c256;
- reg = 0x53;
- };
- eeprom@54 {
- compatible = at24,24c256;
- reg = 0x54;
- };
- eeprom@55 {
- compatible = at24,24c256;
- reg = 0x55;
- };
- eeprom@56 {
- compatible = at24,24c256;
- reg = 0x56;
- };
- rtc@68 {
- compatible = dallas,ds3232;
- reg = 0x68;
- interrupts = 0x1 0x1 0 0;
+ mux@77 {
+ compatible = nxp,pca9547;
+ reg = 0x77;
+ #address-cells = 1
RE: [PATCH V2] powerpc: Add I2C bus multiplexer node for B4 and T4240QDS
Great thanks.
I will update the patch and send it soon.
-Hongtao
-Original Message-
From: Linuxppc-dev [mailto:linuxppc-dev-
bounces+b38951=freescale@lists.ozlabs.org] On Behalf Of Kumar Gala
Sent: Saturday, September 07, 2013 12:10 AM
To: Jia Hongtao-B38951
Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org;
wei.y...@windriver.com
Subject: Re: [PATCH V2] powerpc: Add I2C bus multiplexer node for B4 and
T4240QDS
On Sep 5, 2013, at 10:33 PM, Jia Hongtao-B38951 wrote:
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Friday, September 06, 2013 2:41 AM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421;
wei.y...@windriver.com
Subject: Re: [PATCH V2] powerpc: Add I2C bus multiplexer node for B4
and T4240QDS
On Sep 4, 2013, at 9:41 PM, Jia Hongtao wrote:
In both B4 and T4240QDS platform PCA9547 I2C bus multiplexer is used.
The sub-nodes are also reorganized according to right I2C topology.
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
V2 change log:
Reorganized the sub-nodes under I2C multiplexer to represent right
topology.
arch/powerpc/boot/dts/b4qds.dtsi | 49 +---
arch/powerpc/boot/dts/t4240qds.dts | 67
++-
---
2 files changed, 69 insertions(+), 47 deletions(-)
diff --git a/arch/powerpc/boot/dts/b4qds.dtsi
b/arch/powerpc/boot/dts/b4qds.dtsi
index e6d2f8f..de8cb38 100644
--- a/arch/powerpc/boot/dts/b4qds.dtsi
+++ b/arch/powerpc/boot/dts/b4qds.dtsi
@@ -120,25 +120,36 @@
};
i2c@118000 {
- eeprom@50 {
- compatible = at24,24c64;
- reg = 0x50;
- };
- eeprom@51 {
- compatible = at24,24c256;
- reg = 0x51;
- };
- eeprom@53 {
- compatible = at24,24c256;
- reg = 0x53;
- };
- eeprom@57 {
- compatible = at24,24c256;
- reg = 0x57;
- };
- rtc@68 {
- compatible = dallas,ds3232;
- reg = 0x68;
+ pca9547@77 {
+ compatible = philips,pca9547;
We seem to be using nxp instead of philips now.
This is based on Documentation/devicetree/bindings/vendor-prefixes.txt
+ reg = 0x77;
+ #address-cells = 1;
+ #size-cells = 0;
+ channel@0 {
channel should probably be i2c
Is there any standard for the name?
i2c is ok but I think channel is more intuitional.
Hi Scott,
What do you think of it.
Basing my comments on Documentation/devicetree/bindings/i2c/i2c-mux.txt
Thanks.
-Hongtao
[same comments below]
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0;
+ eeprom@50 {
+ compatible = at24,24c64;
+ reg = 0x50;
+ };
+ eeprom@51 {
+ compatible = at24,24c256;
+ reg = 0x51;
+ };
+ eeprom@53 {
+ compatible = at24,24c256;
+ reg = 0x53;
+ };
+ eeprom@57 {
+ compatible = at24,24c256;
+ reg = 0x57;
+ };
+ rtc@68 {
+ compatible = dallas,ds3232;
+ reg = 0x68;
+ };
+ };
};
};
diff --git a/arch/powerpc/boot/dts/t4240qds.dts
b/arch/powerpc/boot/dts/t4240qds.dts
index 0555976..ae68595 100644
--- a/arch/powerpc/boot/dts/t4240qds.dts
+++ b/arch/powerpc/boot/dts/t4240qds.dts
@@ -118,34 +118,45 @@
};
i2c@118000 {
- eeprom@51 {
- compatible = at24,24c256;
- reg = 0x51;
- };
- eeprom@52 {
- compatible = at24,24c256;
- reg = 0x52;
- };
- eeprom@53
[PATCH V3] powerpc: Add I2C bus multiplexer node for B4 and T4240QDS
In both B4 and T4240QDS platform PCA9547 I2C bus multiplexer is used.
The sub-nodes are also reorganized according to right I2C topology.
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
V3 change log:
* change channel to i2c based on i2c-mux binding.
V2 change log:
* Reorganized the sub-nodes under I2C multiplexer to represent right topology.
arch/powerpc/boot/dts/b4qds.dtsi | 51 +---
arch/powerpc/boot/dts/t4240qds.dts | 69 ++
2 files changed, 73 insertions(+), 47 deletions(-)
diff --git a/arch/powerpc/boot/dts/b4qds.dtsi b/arch/powerpc/boot/dts/b4qds.dtsi
index e6d2f8f..e2ab6cb 100644
--- a/arch/powerpc/boot/dts/b4qds.dtsi
+++ b/arch/powerpc/boot/dts/b4qds.dtsi
@@ -120,25 +120,38 @@
};
i2c@118000 {
- eeprom@50 {
- compatible = at24,24c64;
- reg = 0x50;
- };
- eeprom@51 {
- compatible = at24,24c256;
- reg = 0x51;
- };
- eeprom@53 {
- compatible = at24,24c256;
- reg = 0x53;
- };
- eeprom@57 {
- compatible = at24,24c256;
- reg = 0x57;
- };
- rtc@68 {
- compatible = dallas,ds3232;
- reg = 0x68;
+ mux@77 {
+ compatible = philips,pca9547;
+ reg = 0x77;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ i2c@0 {
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0;
+
+ eeprom@50 {
+ compatible = at24,24c64;
+ reg = 0x50;
+ };
+ eeprom@51 {
+ compatible = at24,24c256;
+ reg = 0x51;
+ };
+ eeprom@53 {
+ compatible = at24,24c256;
+ reg = 0x53;
+ };
+ eeprom@57 {
+ compatible = at24,24c256;
+ reg = 0x57;
+ };
+ rtc@68 {
+ compatible = dallas,ds3232;
+ reg = 0x68;
+ };
+ };
};
};
diff --git a/arch/powerpc/boot/dts/t4240qds.dts
b/arch/powerpc/boot/dts/t4240qds.dts
index 0555976..b354af5 100644
--- a/arch/powerpc/boot/dts/t4240qds.dts
+++ b/arch/powerpc/boot/dts/t4240qds.dts
@@ -118,34 +118,47 @@
};
i2c@118000 {
- eeprom@51 {
- compatible = at24,24c256;
- reg = 0x51;
- };
- eeprom@52 {
- compatible = at24,24c256;
- reg = 0x52;
- };
- eeprom@53 {
- compatible = at24,24c256;
- reg = 0x53;
- };
- eeprom@54 {
- compatible = at24,24c256;
- reg = 0x54;
- };
- eeprom@55 {
- compatible = at24,24c256;
- reg = 0x55;
- };
- eeprom@56 {
- compatible = at24,24c256;
- reg = 0x56;
- };
- rtc@68 {
- compatible = dallas,ds3232;
- reg = 0x68;
- interrupts = 0x1 0x1 0 0;
+ mux@77 {
+ compatible = philips,pca9547;
+ reg = 0x77;
+ #address-cells = 1;
+ #size-cells = 0
RE: [V2,2/2] powerpc/85xx: workaround for chips with MSI hardware errata
-Original Message- From: Wood Scott-B07421 Sent: Friday, September 06, 2013 1:57 AM To: Jia Hongtao-B38951 Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org Subject: Re: [V2,2/2] powerpc/85xx: workaround for chips with MSI hardware errata On Wed, 2013-09-04 at 23:00 -0500, Jia Hongtao-B38951 wrote: -Original Message- From: Jia Hongtao-B38951 Sent: Monday, July 01, 2013 5:36 PM To: Wood Scott-B07421 Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org Subject: RE: [V2,2/2] powerpc/85xx: workaround for chips with MSI hardware errata -Original Message- From: Wood Scott-B07421 Sent: Friday, June 28, 2013 10:29 AM To: Jia Hongtao-B38951 Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org; Wood Scott- B07421 Subject: Re: [V2,2/2] powerpc/85xx: workaround for chips with MSI hardware errata On Wed, Apr 03, 2013 at 10:03:18AM +0800, Hongtao Jia wrote: The MPIC version 2.0 has a MSI errata (errata PIC1 of mpc8544), It causes that neither MSI nor MSI-X can work fine. This is a workaround to allow MSI-X to function properly. Signed-off-by: Liu Shuo soniccat@gmail.com Signed-off-by: Li Yang le...@freescale.com Signed-off-by: Jia Hongtao hongtao@freescale.com Building on 83xx: arch/powerpc/sysdev/built-in.o: In function `fsl_of_msi_probe': fsl_msi.c:(.text+0x1464): undefined reference to `fsl_mpic_primary_get_version' make[1]: *** [vmlinux] Error 1 make: *** [sub-make] Error 2 fsl_msi.c supports IPIC as well. -Scott Hi Scott, I updated the patch to fix this compile error just now. please refer to: http://patchwork.ozlabs.org/patch/256018/ Thanks. -Hongtao Hi Scott, The 83xx compile issue has already been fixed. Please have a review on this patch. Oh, sorry -- I missed it because it was marked Changes Requested. I've changed the status and will consider it for the next batch of next patches. In the future, if a patch is miscategorized in patchwork (e.g. says changes requested when there is no longer a need to submit a new patch) please mention that specifically and provide the patchwork URL. -Scott Ok, got it. Sorry for your inconvenient. -Hongtao ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH V2] powerpc: Add I2C bus multiplexer node for B4 and T4240QDS
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Friday, September 06, 2013 2:41 AM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421;
wei.y...@windriver.com
Subject: Re: [PATCH V2] powerpc: Add I2C bus multiplexer node for B4 and
T4240QDS
On Sep 4, 2013, at 9:41 PM, Jia Hongtao wrote:
In both B4 and T4240QDS platform PCA9547 I2C bus multiplexer is used.
The sub-nodes are also reorganized according to right I2C topology.
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
V2 change log:
Reorganized the sub-nodes under I2C multiplexer to represent right
topology.
arch/powerpc/boot/dts/b4qds.dtsi | 49 +---
arch/powerpc/boot/dts/t4240qds.dts | 67 ++-
---
2 files changed, 69 insertions(+), 47 deletions(-)
diff --git a/arch/powerpc/boot/dts/b4qds.dtsi
b/arch/powerpc/boot/dts/b4qds.dtsi
index e6d2f8f..de8cb38 100644
--- a/arch/powerpc/boot/dts/b4qds.dtsi
+++ b/arch/powerpc/boot/dts/b4qds.dtsi
@@ -120,25 +120,36 @@
};
i2c@118000 {
- eeprom@50 {
- compatible = at24,24c64;
- reg = 0x50;
- };
- eeprom@51 {
- compatible = at24,24c256;
- reg = 0x51;
- };
- eeprom@53 {
- compatible = at24,24c256;
- reg = 0x53;
- };
- eeprom@57 {
- compatible = at24,24c256;
- reg = 0x57;
- };
- rtc@68 {
- compatible = dallas,ds3232;
- reg = 0x68;
+ pca9547@77 {
+ compatible = philips,pca9547;
We seem to be using nxp instead of philips now.
+ reg = 0x77;
+ #address-cells = 1;
+ #size-cells = 0;
+ channel@0 {
channel should probably be i2c
Is there any standard for the name?
i2c is ok but I think channel is more intuitional.
Hi Scott,
What do you think of it.
Thanks.
-Hongtao
[same comments below]
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0;
+ eeprom@50 {
+ compatible = at24,24c64;
+ reg = 0x50;
+ };
+ eeprom@51 {
+ compatible = at24,24c256;
+ reg = 0x51;
+ };
+ eeprom@53 {
+ compatible = at24,24c256;
+ reg = 0x53;
+ };
+ eeprom@57 {
+ compatible = at24,24c256;
+ reg = 0x57;
+ };
+ rtc@68 {
+ compatible = dallas,ds3232;
+ reg = 0x68;
+ };
+ };
};
};
diff --git a/arch/powerpc/boot/dts/t4240qds.dts
b/arch/powerpc/boot/dts/t4240qds.dts
index 0555976..ae68595 100644
--- a/arch/powerpc/boot/dts/t4240qds.dts
+++ b/arch/powerpc/boot/dts/t4240qds.dts
@@ -118,34 +118,45 @@
};
i2c@118000 {
- eeprom@51 {
- compatible = at24,24c256;
- reg = 0x51;
- };
- eeprom@52 {
- compatible = at24,24c256;
- reg = 0x52;
- };
- eeprom@53 {
- compatible = at24,24c256;
- reg = 0x53;
- };
- eeprom@54 {
- compatible = at24,24c256;
- reg = 0x54;
- };
- eeprom@55 {
- compatible = at24,24c256;
- reg = 0x55;
- };
- eeprom@56 {
- compatible = at24,24c256;
- reg = 0x56
[PATCH V2] powerpc: Add I2C bus multiplexer node for B4 and T4240QDS
In both B4 and T4240QDS platform PCA9547 I2C bus multiplexer is used.
The sub-nodes are also reorganized according to right I2C topology.
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
V2 change log:
Reorganized the sub-nodes under I2C multiplexer to represent right topology.
arch/powerpc/boot/dts/b4qds.dtsi | 49 +---
arch/powerpc/boot/dts/t4240qds.dts | 67 ++
2 files changed, 69 insertions(+), 47 deletions(-)
diff --git a/arch/powerpc/boot/dts/b4qds.dtsi b/arch/powerpc/boot/dts/b4qds.dtsi
index e6d2f8f..de8cb38 100644
--- a/arch/powerpc/boot/dts/b4qds.dtsi
+++ b/arch/powerpc/boot/dts/b4qds.dtsi
@@ -120,25 +120,36 @@
};
i2c@118000 {
- eeprom@50 {
- compatible = at24,24c64;
- reg = 0x50;
- };
- eeprom@51 {
- compatible = at24,24c256;
- reg = 0x51;
- };
- eeprom@53 {
- compatible = at24,24c256;
- reg = 0x53;
- };
- eeprom@57 {
- compatible = at24,24c256;
- reg = 0x57;
- };
- rtc@68 {
- compatible = dallas,ds3232;
- reg = 0x68;
+ pca9547@77 {
+ compatible = philips,pca9547;
+ reg = 0x77;
+ #address-cells = 1;
+ #size-cells = 0;
+ channel@0 {
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0;
+ eeprom@50 {
+ compatible = at24,24c64;
+ reg = 0x50;
+ };
+ eeprom@51 {
+ compatible = at24,24c256;
+ reg = 0x51;
+ };
+ eeprom@53 {
+ compatible = at24,24c256;
+ reg = 0x53;
+ };
+ eeprom@57 {
+ compatible = at24,24c256;
+ reg = 0x57;
+ };
+ rtc@68 {
+ compatible = dallas,ds3232;
+ reg = 0x68;
+ };
+ };
};
};
diff --git a/arch/powerpc/boot/dts/t4240qds.dts
b/arch/powerpc/boot/dts/t4240qds.dts
index 0555976..ae68595 100644
--- a/arch/powerpc/boot/dts/t4240qds.dts
+++ b/arch/powerpc/boot/dts/t4240qds.dts
@@ -118,34 +118,45 @@
};
i2c@118000 {
- eeprom@51 {
- compatible = at24,24c256;
- reg = 0x51;
- };
- eeprom@52 {
- compatible = at24,24c256;
- reg = 0x52;
- };
- eeprom@53 {
- compatible = at24,24c256;
- reg = 0x53;
- };
- eeprom@54 {
- compatible = at24,24c256;
- reg = 0x54;
- };
- eeprom@55 {
- compatible = at24,24c256;
- reg = 0x55;
- };
- eeprom@56 {
- compatible = at24,24c256;
- reg = 0x56;
- };
- rtc@68 {
- compatible = dallas,ds3232;
- reg = 0x68;
- interrupts = 0x1 0x1 0 0;
+ pca9547@77 {
+ compatible = philips,pca9547;
+ reg = 0x77;
+ #address-cells = 1;
+ #size-cells = 0;
+ channel@0
RE: [V2,2/2] powerpc/85xx: workaround for chips with MSI hardware errata
-Original Message- From: Jia Hongtao-B38951 Sent: Monday, July 01, 2013 5:36 PM To: Wood Scott-B07421 Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org Subject: RE: [V2,2/2] powerpc/85xx: workaround for chips with MSI hardware errata -Original Message- From: Wood Scott-B07421 Sent: Friday, June 28, 2013 10:29 AM To: Jia Hongtao-B38951 Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org; Wood Scott- B07421 Subject: Re: [V2,2/2] powerpc/85xx: workaround for chips with MSI hardware errata On Wed, Apr 03, 2013 at 10:03:18AM +0800, Hongtao Jia wrote: The MPIC version 2.0 has a MSI errata (errata PIC1 of mpc8544), It causes that neither MSI nor MSI-X can work fine. This is a workaround to allow MSI-X to function properly. Signed-off-by: Liu Shuo soniccat@gmail.com Signed-off-by: Li Yang le...@freescale.com Signed-off-by: Jia Hongtao hongtao@freescale.com Building on 83xx: arch/powerpc/sysdev/built-in.o: In function `fsl_of_msi_probe': fsl_msi.c:(.text+0x1464): undefined reference to `fsl_mpic_primary_get_version' make[1]: *** [vmlinux] Error 1 make: *** [sub-make] Error 2 fsl_msi.c supports IPIC as well. -Scott Hi Scott, I updated the patch to fix this compile error just now. please refer to: http://patchwork.ozlabs.org/patch/256018/ Thanks. -Hongtao Hi Scott, The 83xx compile issue has already been fixed. Please have a review on this patch. Thanks. -Hongtao ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH] powerpc: Add I2C bus multiplexer node for B4 and T4240QDS
Hi Wei,
I totally agree that the i2c nodes topology should end up like you said.
But I think adding sub-nodes should step by step.
Actually the hardware i2c topology are huge like on T4.
So I'd like to adding nodes when we needed.
If you think the sub-nodes are needed please send another patch based on mine.
I think this is the more reasonable way.
Thanks.
-Hongtao
-Original Message-
From: Yang,Wei [mailto:wei.y...@windriver.com]
Sent: Wednesday, September 04, 2013 9:27 AM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Jia Hongtao-B38951
Subject: Re: [PATCH] powerpc: Add I2C bus multiplexer node for B4 and
T4240QDS
On 09/03/2013 03:51 PM, Jia Hongtao wrote:
In both B4 and T4240QDS platform PCA9547 I2C bus multiplexer is used.
Hi Hongtao,
If you want to support I2C bus multiplexer, for T4 and B4QDS platform,
since some eeprom devices is connected to PCA9574 I2C bus multiplexer, so
these devices should be connected to pca9547 node. Just like the
following, what do you think of it?
+ pca9547@77 {
+ compatible = philips,pca9547;
+ reg = 0x77;
+ #address-cells = 1;
+ #size-cells = 0;
+ channel@0 {
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0;
+ eeprom@51 {
+ compatible =
at24,24c256;
+ reg = 0x51;
+ };
+ eeprom@52 {
+ compatible =
at24,24c256;
+ reg = 0x52;
+ };
+ eeprom@53 {
+ compatible =
at24,24c256;
+ reg = 0x53;
+ };
+ eeprom@54 {
+ compatible =
at24,24c256;
+ reg = 0x54;
+ };
+ eeprom@55 {
+ compatible =
at24,24c256;
+ reg = 0x55;
+ };
+ eeprom@56 {
+ compatible =
at24,24c256;
+ reg = 0x56;
+ };
+ rtc@68 {
+ compatible =
dallas,ds3232;
+ reg = 0x68;
+ interrupts =
0x1 0x1 0 0;
+ };
+ };
Wei
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
arch/powerpc/boot/dts/b4qds.dtsi | 4
arch/powerpc/boot/dts/t4240qds.dts | 4
2 files changed, 8 insertions(+)
diff --git a/arch/powerpc/boot/dts/b4qds.dtsi
b/arch/powerpc/boot/dts/b4qds.dtsi
index e6d2f8f..2aa3399 100644
--- a/arch/powerpc/boot/dts/b4qds.dtsi
+++ b/arch/powerpc/boot/dts/b4qds.dtsi
@@ -120,6 +120,10 @@
};
i2c@118000 {
+ pca9547@77 {
+ compatible = philips,pca9547;
+ reg = 0x77;
+ };
eeprom@50 {
compatible = at24,24c64;
reg = 0x50;
diff --git a/arch/powerpc/boot/dts/t4240qds.dts
b/arch/powerpc/boot/dts/t4240qds.dts
index 0555976..084db57 100644
--- a/arch/powerpc/boot/dts/t4240qds.dts
+++ b/arch/powerpc/boot/dts/t4240qds.dts
@@ -118,6 +118,10 @@
};
i2c@118000 {
+ pca9547@77 {
+ compatible = philips,pca9547;
+ reg = 0x77;
+ };
eeprom@51 {
compatible = at24,24c256;
reg = 0x51;
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo
RE: [PATCH] powerpc: Add I2C bus multiplexer node for B4 and T4240QDS
Hi Yuantian,
Yes, you are right.
Hi Wei,
I misunderstood your idea.
I agree it and I will submit V2 patch to update it soon.
Thanks.
-Hongtao
-Original Message-
From: Tang Yuantian-B29983
Sent: Wednesday, September 04, 2013 12:04 PM
To: Jia Hongtao-B38951; Yang,Wei
Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org
Subject: RE: [PATCH] powerpc: Add I2C bus multiplexer node for B4 and
T4240QDS
Hi,
I noticed that there are already some nodes in i2c bus.
You should at least move the existing node into PCA9547.
Thanks,
Yuantian
-Original Message-
From: Linuxppc-dev [mailto:linuxppc-dev-
bounces+b29983=freescale@lists.ozlabs.org] On Behalf Of Jia
bounces+Hongtao-
B38951
Sent: 2013年9月4日 星期三 11:38
To: Yang,Wei
Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org
Subject: RE: [PATCH] powerpc: Add I2C bus multiplexer node for B4 and
T4240QDS
Hi Wei,
I totally agree that the i2c nodes topology should end up like you said.
But I think adding sub-nodes should step by step.
Actually the hardware i2c topology are huge like on T4.
So I'd like to adding nodes when we needed.
If you think the sub-nodes are needed please send another patch based
on mine.
I think this is the more reasonable way.
Thanks.
-Hongtao
-Original Message-
From: Yang,Wei [mailto:wei.y...@windriver.com]
Sent: Wednesday, September 04, 2013 9:27 AM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Jia
Hongtao-B38951
Subject: Re: [PATCH] powerpc: Add I2C bus multiplexer node for B4
and T4240QDS
On 09/03/2013 03:51 PM, Jia Hongtao wrote:
In both B4 and T4240QDS platform PCA9547 I2C bus multiplexer is
used.
Hi Hongtao,
If you want to support I2C bus multiplexer, for T4 and B4QDS
platform, since some eeprom devices is connected to PCA9574 I2C bus
multiplexer, so these devices should be connected to pca9547 node.
Just like the following, what do you think of it?
+ pca9547@77 {
+ compatible = philips,pca9547;
+ reg = 0x77;
+ #address-cells = 1;
+ #size-cells = 0;
+ channel@0 {
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0;
+ eeprom@51 {
+ compatible =
at24,24c256;
+ reg = 0x51;
+ };
+ eeprom@52 {
+ compatible =
at24,24c256;
+ reg = 0x52;
+ };
+ eeprom@53 {
+ compatible =
at24,24c256;
+ reg = 0x53;
+ };
+ eeprom@54 {
+ compatible =
at24,24c256;
+ reg = 0x54;
+ };
+ eeprom@55 {
+ compatible =
at24,24c256;
+ reg = 0x55;
+ };
+ eeprom@56 {
+ compatible =
at24,24c256;
+ reg = 0x56;
+ };
+ rtc@68 {
+ compatible =
dallas,ds3232;
+ reg = 0x68;
+ interrupts =
0x1 0x1 0 0;
+ };
+ };
Wei
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
arch/powerpc/boot/dts/b4qds.dtsi | 4
arch/powerpc/boot/dts/t4240qds.dts | 4
2 files changed, 8 insertions(+)
diff --git a/arch/powerpc/boot/dts/b4qds.dtsi
b/arch/powerpc/boot/dts/b4qds.dtsi
index e6d2f8f..2aa3399 100644
--- a/arch/powerpc/boot/dts/b4qds.dtsi
+++ b/arch/powerpc/boot
RE: [PATCH] powerpc/msi: Fix compile error on mpc83xx
-Original Message- From: Wood Scott-B07421 Sent: Tuesday, July 23, 2013 1:19 AM To: Jia Hongtao-B38951 Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org; Li Yang-R58472; Jia Hongtao-B38951 Subject: Re: [PATCH] powerpc/msi: Fix compile error on mpc83xx On 07/21/2013 09:00:51 PM, Jia Hongtao-B38951 wrote: Hi Scott, The fsl_msi.c build error on MPC83xx platform is fixed by this patch. Could you please have a review? Thanks. -Hongtao I will apply it when I apply the patch that depends on it. I hope to resume applying patches soon. -Scott Thanks. - Hongtao ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH] powerpc/msi: Fix compile error on mpc83xx
Hi Scott,
The fsl_msi.c build error on MPC83xx platform is fixed by this patch.
Could you please have a review?
Thanks.
-Hongtao
-Original Message-
From: Jia Hongtao-B38951
Sent: Wednesday, July 10, 2013 10:04 AM
To: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org
Cc: ga...@kernel.crashing.org; Li Yang-R58472; Jia Hongtao-B38951
Subject: RE: [PATCH] powerpc/msi: Fix compile error on mpc83xx
Hi Scott,
I made this patch to fix msi compile error on mpc83xx.
Could you please have a review.
Thanks.
-Hongtao
-Original Message-
From: Jia Hongtao-B38951
Sent: Tuesday, July 02, 2013 9:37 AM
To: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421
Cc: ga...@kernel.crashing.org; Li Yang-R58472; Jia Hongtao-B38951
Subject: [PATCH] powerpc/msi: Fix compile error on mpc83xx
mpic_get_primary_version() is not defined when not using MPIC.
The compile error log like:
arch/powerpc/sysdev/built-in.o: In function `fsl_of_msi_probe':
fsl_msi.c:(.text+0x150c): undefined reference to
`fsl_mpic_primary_get_version'
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
arch/powerpc/include/asm/mpic.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/include/asm/mpic.h
b/arch/powerpc/include/asm/mpic.h index ea6bf72..97b5a63 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -394,7 +394,14 @@ struct mpic
#defineMPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109
PIC */
/* Get the version of primary MPIC */
+#ifdef CONFIG_MPIC
extern u32 fsl_mpic_primary_get_version(void);
+#else
+static inline u32 fsl_mpic_primary_get_version(void)
+{
+ return 0;
+}
+#endif
/* Allocate the controller structure and setup the linux irq descs
* for the range if interrupts passed in. No HW initialization is
--
1.8.0
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RE: [PATCH] powerpc/msi: Fix compile error on mpc83xx
Hi Scott,
I made this patch to fix msi compile error on mpc83xx.
Could you please have a review.
Thanks.
-Hongtao
-Original Message-
From: Jia Hongtao-B38951
Sent: Tuesday, July 02, 2013 9:37 AM
To: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421
Cc: ga...@kernel.crashing.org; Li Yang-R58472; Jia Hongtao-B38951
Subject: [PATCH] powerpc/msi: Fix compile error on mpc83xx
mpic_get_primary_version() is not defined when not using MPIC.
The compile error log like:
arch/powerpc/sysdev/built-in.o: In function `fsl_of_msi_probe':
fsl_msi.c:(.text+0x150c): undefined reference to
`fsl_mpic_primary_get_version'
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
arch/powerpc/include/asm/mpic.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/include/asm/mpic.h
b/arch/powerpc/include/asm/mpic.h index ea6bf72..97b5a63 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -394,7 +394,14 @@ struct mpic
#define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109
PIC */
/* Get the version of primary MPIC */
+#ifdef CONFIG_MPIC
extern u32 fsl_mpic_primary_get_version(void);
+#else
+static inline u32 fsl_mpic_primary_get_version(void)
+{
+ return 0;
+}
+#endif
/* Allocate the controller structure and setup the linux irq descs
* for the range if interrupts passed in. No HW initialization is
--
1.8.0
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[PATCH V6] powerpc/MPIC: Add get_version API both for internal and external use
From: Hongtao Jia hongtao@freescale.com
MPIC version is useful information for both mpic_alloc() and mpic_init().
The patch provide an API to get MPIC version for reusing the code.
Also, some other IP block may need MPIC version for their own use.
The API for external use is also provided.
Signed-off-by: Jia Hongtao hongtao@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
V6:
* Fix compile error on mpc83xx.
V5:
* add MPIC_FSL check for fsl_mpic_get_version().
V4:
* change the name of function from mpic_get_version() to
fsl_mpic_get_version().
V3:
* change the name of function from mpic_primary_get_version() to
fsl_mpic_primary_get_version().
* return 0 if mpic_primary is null.
V2:
* Using mpic_get_version() to implement mpic_primary_get_version()
arch/powerpc/include/asm/mpic.h | 10 ++
arch/powerpc/sysdev/mpic.c | 32 +---
2 files changed, 35 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index c0f9ef9..9d55671 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -393,6 +393,16 @@ struct mpic
#defineMPIC_REGSET_STANDARDMPIC_REGSET(0) /* Original
MPIC */
#defineMPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109
PIC */
+/* Get the version of primary MPIC */
+#ifdef CONFIG_MPIC
+extern u32 fsl_mpic_primary_get_version(void);
+#else
+static inline u32 fsl_mpic_primary_get_version(void)
+{
+ return -ENOTSUPP;
+}
+#endif
+
/* Allocate the controller structure and setup the linux irq descs
* for the range if interrupts passed in. No HW initialization is
* actually performed.
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 3cc2f91..1a4e19c 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1173,10 +1173,33 @@ static struct irq_domain_ops mpic_host_ops = {
.xlate = mpic_host_xlate,
};
+static u32 fsl_mpic_get_version(struct mpic *mpic)
+{
+ u32 brr1;
+
+ if (!(mpic-flags MPIC_FSL))
+ return 0;
+
+ brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
+ MPIC_FSL_BRR1);
+
+ return brr1 MPIC_FSL_BRR1_VER;
+}
+
/*
* Exported functions
*/
+u32 fsl_mpic_primary_get_version(void)
+{
+ struct mpic *mpic = mpic_primary;
+
+ if (mpic)
+ return fsl_mpic_get_version(mpic);
+
+ return 0;
+}
+
struct mpic * __init mpic_alloc(struct device_node *node,
phys_addr_t phys_addr,
unsigned int flags,
@@ -1323,7 +1346,6 @@ struct mpic * __init mpic_alloc(struct device_node *node,
mpic_map(mpic, mpic-paddr, mpic-tmregs, MPIC_INFO(TIMER_BASE),
0x1000);
if (mpic-flags MPIC_FSL) {
- u32 brr1;
int ret;
/*
@@ -1334,9 +1356,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
mpic_map(mpic, mpic-paddr, mpic-thiscpuregs,
MPIC_CPU_THISBASE, 0x1000);
- brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
- MPIC_FSL_BRR1);
- fsl_version = brr1 MPIC_FSL_BRR1_VER;
+ fsl_version = fsl_mpic_get_version(mpic);
/* Error interrupt mask register (EIMR) is required for
* handling individual device error interrupts. EIMR
@@ -1526,9 +1546,7 @@ void __init mpic_init(struct mpic *mpic)
mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
if (mpic-flags MPIC_FSL) {
- u32 brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
- MPIC_FSL_BRR1);
- u32 version = brr1 MPIC_FSL_BRR1_VER;
+ u32 version = fsl_mpic_get_version(mpic);
/*
* Timer group B is present at the latest in MPIC 3.1 (e.g.
--
1.8.0
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RE: [V2,2/2] powerpc/85xx: workaround for chips with MSI hardware errata
-Original Message- From: Wood Scott-B07421 Sent: Friday, June 28, 2013 10:29 AM To: Jia Hongtao-B38951 Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org; Wood Scott- B07421 Subject: Re: [V2,2/2] powerpc/85xx: workaround for chips with MSI hardware errata On Wed, Apr 03, 2013 at 10:03:18AM +0800, Hongtao Jia wrote: The MPIC version 2.0 has a MSI errata (errata PIC1 of mpc8544), It causes that neither MSI nor MSI-X can work fine. This is a workaround to allow MSI-X to function properly. Signed-off-by: Liu Shuo soniccat@gmail.com Signed-off-by: Li Yang le...@freescale.com Signed-off-by: Jia Hongtao hongtao@freescale.com Building on 83xx: arch/powerpc/sysdev/built-in.o: In function `fsl_of_msi_probe': fsl_msi.c:(.text+0x1464): undefined reference to `fsl_mpic_primary_get_version' make[1]: *** [vmlinux] Error 1 make: *** [sub-make] Error 2 fsl_msi.c supports IPIC as well. -Scott Hi Scott, I updated the patch to fix this compile error just now. please refer to: http://patchwork.ozlabs.org/patch/256018/ Thanks. -Hongtao ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH V6] powerpc/MPIC: Add get_version API both for internal and external use
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, July 02, 2013 7:59 AM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421;
ga...@kernel.crashing.org; Li Yang-R58472; Jia Hongtao-B38951
Subject: Re: [PATCH V6] powerpc/MPIC: Add get_version API both for
internal and external use
On 07/01/2013 12:26:06 AM, Jia Hongtao wrote:
From: Hongtao Jia hongtao@freescale.com
MPIC version is useful information for both mpic_alloc() and
mpic_init().
The patch provide an API to get MPIC version for reusing the code.
Also, some other IP block may need MPIC version for their own use.
The API for external use is also provided.
Signed-off-by: Jia Hongtao hongtao@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
V6:
* Fix compile error on mpc83xx.
I already applied V5 before realizing that it was this patch that you
updated, rather than the MSI patch that depends on it. There is no
compile error until the MSI patch that starts using this (which I haven't
yet applied, due to the error). Could you send a followup patch that
just adds the stub?
Yep, sure.
+/* Get the version of primary MPIC */ #ifdef CONFIG_MPIC extern u32
+fsl_mpic_primary_get_version(void);
+#else
+static inline u32 fsl_mpic_primary_get_version(void)
+{
+ return -ENOTSUPP;
+}
+#endif
[snip]
+static u32 fsl_mpic_get_version(struct mpic *mpic) {
+ u32 brr1;
+
+ if (!(mpic-flags MPIC_FSL))
+ return 0;
In one case, calling this without having an FSL MPIC returns -ENOTSUPP,
and in another case it returns 0... Shouldn't it be consistent?
Also returning a negative number as a u32 is not very nice.
-Scott
My mistake.
Will be fixed.
Thanks.
-Hongtao
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[PATCH] powerpc/msi: Fix compile error on mpc83xx
mpic_get_primary_version() is not defined when not using MPIC.
The compile error log like:
arch/powerpc/sysdev/built-in.o: In function `fsl_of_msi_probe':
fsl_msi.c:(.text+0x150c): undefined reference to `fsl_mpic_primary_get_version'
Signed-off-by: Jia Hongtao b38...@freescale.com
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
arch/powerpc/include/asm/mpic.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index ea6bf72..97b5a63 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -394,7 +394,14 @@ struct mpic
#defineMPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109
PIC */
/* Get the version of primary MPIC */
+#ifdef CONFIG_MPIC
extern u32 fsl_mpic_primary_get_version(void);
+#else
+static inline u32 fsl_mpic_primary_get_version(void)
+{
+ return 0;
+}
+#endif
/* Allocate the controller structure and setup the linux irq descs
* for the range if interrupts passed in. No HW initialization is
--
1.8.0
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[PATCH] powerpc/msi: Fix compile error on mpc83xx
mpic_get_primary_version() is not defined when not using MPIC.
The compile error log like:
arch/powerpc/sysdev/built-in.o: In function `fsl_of_msi_probe':
fsl_msi.c:(.text+0x150c): undefined reference to `fsl_mpic_primary_get_version'
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
arch/powerpc/include/asm/mpic.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index ea6bf72..97b5a63 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -394,7 +394,14 @@ struct mpic
#defineMPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109
PIC */
/* Get the version of primary MPIC */
+#ifdef CONFIG_MPIC
extern u32 fsl_mpic_primary_get_version(void);
+#else
+static inline u32 fsl_mpic_primary_get_version(void)
+{
+ return 0;
+}
+#endif
/* Allocate the controller structure and setup the linux irq descs
* for the range if interrupts passed in. No HW initialization is
--
1.8.0
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RE: [PATCH] powerpc/msi: Fix compile error on mpc83xx
Please ignore this patch.
-Hongtao
-Original Message-
From: Jia Hongtao-B38951
Sent: Tuesday, July 02, 2013 9:35 AM
To: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421
Cc: ga...@kernel.crashing.org; Li Yang-R58472; Jia Hongtao-B38951
Subject: [PATCH] powerpc/msi: Fix compile error on mpc83xx
mpic_get_primary_version() is not defined when not using MPIC.
The compile error log like:
arch/powerpc/sysdev/built-in.o: In function `fsl_of_msi_probe':
fsl_msi.c:(.text+0x150c): undefined reference to
`fsl_mpic_primary_get_version'
Signed-off-by: Jia Hongtao b38...@freescale.com
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
arch/powerpc/include/asm/mpic.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/include/asm/mpic.h
b/arch/powerpc/include/asm/mpic.h
index ea6bf72..97b5a63 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -394,7 +394,14 @@ struct mpic
#define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109
PIC */
/* Get the version of primary MPIC */
+#ifdef CONFIG_MPIC
extern u32 fsl_mpic_primary_get_version(void);
+#else
+static inline u32 fsl_mpic_primary_get_version(void)
+{
+ return 0;
+}
+#endif
/* Allocate the controller structure and setup the linux irq descs
* for the range if interrupts passed in. No HW initialization is
--
1.8.0
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RE: [PATCH 2/2 V8] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx
Hi Ben and Kumar, I'm really appreciate if you could help me to review this patches for these patches were pending nearly a month. Thanks. -Hongtao -Original Message- From: Jia Hongtao-B38951 Sent: Monday, May 13, 2013 2:20 PM To: 'Benjamin Herrenschmidt' Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org; Wood Scott- B07421; Li Yang-R58472; Jia Hongtao-B38951 Subject: RE: [PATCH 2/2 V8] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx Hi Ben, These four patches have been reviewed for a long time and look good to Scott Wood. It seems Kumar have no enough time for further review. Could you please help me to review them? http://patchwork.ozlabs.org/patch/233211/ http://patchwork.ozlabs.org/patch/235276/ http://patchwork.ozlabs.org/patch/240238/ http://patchwork.ozlabs.org/patch/240239/ Thanks. -Hongtao -Original Message- From: Jia Hongtao-B38951 Sent: Friday, May 10, 2013 12:01 PM To: ga...@kernel.crashing.org Cc: linuxppc-dev@lists.ozlabs.org; Li Yang-R58472; Jia Hongtao-B38951 Subject: RE: [PATCH 2/2 V8] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx -Original Message- From: Wood Scott-B07421 Sent: Friday, May 03, 2013 1:04 AM To: Jia Hongtao-B38951 Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org; Wood Scott- B07421; seg...@kernel.crashing.org; Li Yang-R58472; Jia Hongtao-B38951 Subject: Re: [PATCH 2/2 V8] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx On 04/28/2013 12:20:08 AM, Jia Hongtao wrote: A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe goes down. when the link goes down, Non-posted transactions issued via the ATMU requiring completion result in an instruction stall. At the same time a machine-check exception is generated to the core to allow further processing by the handler. We implements the handler which skips the instruction caused the stall. This patch depends on patch: powerpc/85xx: Add platform_device declaration to fsl_pci.h Signed-off-by: Zhao Chenhui b35...@freescale.com Signed-off-by: Li Yang le...@freescale.com Signed-off-by: Liu Shuo soniccat@gmail.com Signed-off-by: Jia Hongtao hongtao@freescale.com --- V8: * Add A variant load instruction emulation. ACK -Scott Thanks for the review. Hi Kumar, Could you please review these MSI and PCI hang errata patches? http://patchwork.ozlabs.org/patch/233211/ http://patchwork.ozlabs.org/patch/235276/ http://patchwork.ozlabs.org/patch/240238/ http://patchwork.ozlabs.org/patch/240239/ (This patch) Thanks. -Hongtao Hi Kumar, I'm really appreciated if you have time to review these patches? Thanks. -Hongtao ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH 2/2 V8] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx
Hi Ben, These four patches have been reviewed for a long time and look good to Scott Wood. It seems Kumar have no enough time for further review. Could you please help me to review them? http://patchwork.ozlabs.org/patch/233211/ http://patchwork.ozlabs.org/patch/235276/ http://patchwork.ozlabs.org/patch/240238/ http://patchwork.ozlabs.org/patch/240239/ Thanks. -Hongtao -Original Message- From: Jia Hongtao-B38951 Sent: Friday, May 10, 2013 12:01 PM To: ga...@kernel.crashing.org Cc: linuxppc-dev@lists.ozlabs.org; Li Yang-R58472; Jia Hongtao-B38951 Subject: RE: [PATCH 2/2 V8] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx -Original Message- From: Wood Scott-B07421 Sent: Friday, May 03, 2013 1:04 AM To: Jia Hongtao-B38951 Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org; Wood Scott- B07421; seg...@kernel.crashing.org; Li Yang-R58472; Jia Hongtao-B38951 Subject: Re: [PATCH 2/2 V8] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx On 04/28/2013 12:20:08 AM, Jia Hongtao wrote: A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe goes down. when the link goes down, Non-posted transactions issued via the ATMU requiring completion result in an instruction stall. At the same time a machine-check exception is generated to the core to allow further processing by the handler. We implements the handler which skips the instruction caused the stall. This patch depends on patch: powerpc/85xx: Add platform_device declaration to fsl_pci.h Signed-off-by: Zhao Chenhui b35...@freescale.com Signed-off-by: Li Yang le...@freescale.com Signed-off-by: Liu Shuo soniccat@gmail.com Signed-off-by: Jia Hongtao hongtao@freescale.com --- V8: * Add A variant load instruction emulation. ACK -Scott Thanks for the review. Hi Kumar, Could you please review these MSI and PCI hang errata patches? http://patchwork.ozlabs.org/patch/233211/ http://patchwork.ozlabs.org/patch/235276/ http://patchwork.ozlabs.org/patch/240238/ http://patchwork.ozlabs.org/patch/240239/ (This patch) Thanks. -Hongtao Hi Kumar, I'm really appreciated if you have time to review these patches? Thanks. -Hongtao ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH 2/2 V8] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx
-Original Message- From: Wood Scott-B07421 Sent: Friday, May 03, 2013 1:04 AM To: Jia Hongtao-B38951 Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org; Wood Scott- B07421; seg...@kernel.crashing.org; Li Yang-R58472; Jia Hongtao-B38951 Subject: Re: [PATCH 2/2 V8] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx On 04/28/2013 12:20:08 AM, Jia Hongtao wrote: A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe goes down. when the link goes down, Non-posted transactions issued via the ATMU requiring completion result in an instruction stall. At the same time a machine-check exception is generated to the core to allow further processing by the handler. We implements the handler which skips the instruction caused the stall. This patch depends on patch: powerpc/85xx: Add platform_device declaration to fsl_pci.h Signed-off-by: Zhao Chenhui b35...@freescale.com Signed-off-by: Li Yang le...@freescale.com Signed-off-by: Liu Shuo soniccat@gmail.com Signed-off-by: Jia Hongtao hongtao@freescale.com --- V8: * Add A variant load instruction emulation. ACK -Scott Thanks for the review. Hi Kumar, Could you please review these MSI and PCI hang errata patches? http://patchwork.ozlabs.org/patch/233211/ http://patchwork.ozlabs.org/patch/235276/ http://patchwork.ozlabs.org/patch/240238/ http://patchwork.ozlabs.org/patch/240239/ (This patch) Thanks. -Hongtao Hi Kumar, I'm really appreciated if you have time to review these patches? Thanks. -Hongtao ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH 2/2 V7] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx
-Original Message- From: Wood Scott-B07421 Sent: Tuesday, April 30, 2013 4:30 AM To: Jia Hongtao-B38951 Cc: Wood Scott-B07421; Segher Boessenkool; linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org Subject: Re: [PATCH 2/2 V7] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx On 04/26/2013 09:26:26 PM, Jia Hongtao-B38951 wrote: -Original Message- From: Wood Scott-B07421 Sent: Friday, April 26, 2013 12:58 AM To: Segher Boessenkool Cc: Jia Hongtao-B38951; linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org; Wood Scott-B07421 Subject: Re: [PATCH 2/2 V7] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx On 04/25/2013 10:31:51 AM, Segher Boessenkool wrote: * Remove A variant of load instruction emulation Why is this? You handle all other simple load insns, there is nothing special about LHA. (I reviewed the V4 email thread, no reason for the chance is given there). The LHA implementation in V5 was incorrect (didn't sign-extend). -Scott In former email you doubt whether we need A variant or not. Any particular reason for that? If not should I emulate all the A ARX AU AUX and AX variant? I was just noting that the variants you left out from the earlier revisions (e.g. BRX) were much more likely to be used for I/O than some of the ones you included (e.g. A). Implementing all the normal load/store instructions would be better, if they're done correctly. -Scott All right. I have submitted a new version and please have a review. http://patchwork.ozlabs.org/patch/240238/ http://patchwork.ozlabs.org/patch/240239/ Thanks. -Hongtao ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH 2/2 V8] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx
-Original Message- From: Wood Scott-B07421 Sent: Friday, May 03, 2013 1:04 AM To: Jia Hongtao-B38951 Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org; Wood Scott- B07421; seg...@kernel.crashing.org; Li Yang-R58472; Jia Hongtao-B38951 Subject: Re: [PATCH 2/2 V8] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx On 04/28/2013 12:20:08 AM, Jia Hongtao wrote: A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe goes down. when the link goes down, Non-posted transactions issued via the ATMU requiring completion result in an instruction stall. At the same time a machine-check exception is generated to the core to allow further processing by the handler. We implements the handler which skips the instruction caused the stall. This patch depends on patch: powerpc/85xx: Add platform_device declaration to fsl_pci.h Signed-off-by: Zhao Chenhui b35...@freescale.com Signed-off-by: Li Yang le...@freescale.com Signed-off-by: Liu Shuo soniccat@gmail.com Signed-off-by: Jia Hongtao hongtao@freescale.com --- V8: * Add A variant load instruction emulation. ACK -Scott Thanks for the review. Hi Kumar, Could you please review these MSI and PCI hang errata patches? http://patchwork.ozlabs.org/patch/233211/ http://patchwork.ozlabs.org/patch/235276/ http://patchwork.ozlabs.org/patch/240238/ http://patchwork.ozlabs.org/patch/240239/ (This patch) Thanks. -Hongtao ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/2 V2] powerpc: Move opcode definitions from kvm/emulate.c to asm/ppc-opcode.h
Opcode and xopcode are useful definitions not just for KVM. Move these
definitions to asm/ppc-opcode.h for public use.
Signed-off-by: Jia Hongtao hongtao@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
V2:
* Add LHAUX definition.
arch/powerpc/include/asm/ppc-opcode.h | 46 +++
arch/powerpc/kvm/emulate.c| 44 +
2 files changed, 47 insertions(+), 43 deletions(-)
diff --git a/arch/powerpc/include/asm/ppc-opcode.h
b/arch/powerpc/include/asm/ppc-opcode.h
index 8752bc8..79057f7 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -81,6 +81,52 @@
#define__REGA0_R30 30
#define__REGA0_R31 31
+/* opcode and xopcode for instructions */
+#define OP_TRAP 3
+#define OP_TRAP_64 2
+
+#define OP_31_XOP_TRAP 4
+#define OP_31_XOP_LWZX 23
+#define OP_31_XOP_LWZUX 55
+#define OP_31_XOP_TRAP_64 68
+#define OP_31_XOP_DCBF 86
+#define OP_31_XOP_LBZX 87
+#define OP_31_XOP_STWX 151
+#define OP_31_XOP_STBX 215
+#define OP_31_XOP_LBZUX 119
+#define OP_31_XOP_STBUX 247
+#define OP_31_XOP_LHZX 279
+#define OP_31_XOP_LHZUX 311
+#define OP_31_XOP_MFSPR 339
+#define OP_31_XOP_LHAX 343
+#define OP_31_XOP_LHAUX 375
+#define OP_31_XOP_STHX 407
+#define OP_31_XOP_STHUX 439
+#define OP_31_XOP_MTSPR 467
+#define OP_31_XOP_DCBI 470
+#define OP_31_XOP_LWBRX 534
+#define OP_31_XOP_TLBSYNC 566
+#define OP_31_XOP_STWBRX662
+#define OP_31_XOP_LHBRX 790
+#define OP_31_XOP_STHBRX918
+
+#define OP_LWZ 32
+#define OP_LD 58
+#define OP_LWZU 33
+#define OP_LBZ 34
+#define OP_LBZU 35
+#define OP_STW 36
+#define OP_STWU 37
+#define OP_STD 62
+#define OP_STB 38
+#define OP_STBU 39
+#define OP_LHZ 40
+#define OP_LHZU 41
+#define OP_LHA 42
+#define OP_LHAU 43
+#define OP_STH 44
+#define OP_STHU 45
+
/* sorted alphabetically */
#define PPC_INST_DCBA 0x7c0005ec
#define PPC_INST_DCBA_MASK 0xfc0007fe
diff --git a/arch/powerpc/kvm/emulate.c b/arch/powerpc/kvm/emulate.c
index 7a73b6f..426d3f5 100644
--- a/arch/powerpc/kvm/emulate.c
+++ b/arch/powerpc/kvm/emulate.c
@@ -30,52 +30,10 @@
#include asm/byteorder.h
#include asm/kvm_ppc.h
#include asm/disassemble.h
+#include asm/ppc-opcode.h
#include timing.h
#include trace.h
-#define OP_TRAP 3
-#define OP_TRAP_64 2
-
-#define OP_31_XOP_TRAP 4
-#define OP_31_XOP_LWZX 23
-#define OP_31_XOP_TRAP_64 68
-#define OP_31_XOP_DCBF 86
-#define OP_31_XOP_LBZX 87
-#define OP_31_XOP_STWX 151
-#define OP_31_XOP_STBX 215
-#define OP_31_XOP_LBZUX 119
-#define OP_31_XOP_STBUX 247
-#define OP_31_XOP_LHZX 279
-#define OP_31_XOP_LHZUX 311
-#define OP_31_XOP_MFSPR 339
-#define OP_31_XOP_LHAX 343
-#define OP_31_XOP_STHX 407
-#define OP_31_XOP_STHUX 439
-#define OP_31_XOP_MTSPR 467
-#define OP_31_XOP_DCBI 470
-#define OP_31_XOP_LWBRX 534
-#define OP_31_XOP_TLBSYNC 566
-#define OP_31_XOP_STWBRX662
-#define OP_31_XOP_LHBRX 790
-#define OP_31_XOP_STHBRX918
-
-#define OP_LWZ 32
-#define OP_LD 58
-#define OP_LWZU 33
-#define OP_LBZ 34
-#define OP_LBZU 35
-#define OP_STW 36
-#define OP_STWU 37
-#define OP_STD 62
-#define OP_STB 38
-#define OP_STBU 39
-#define OP_LHZ 40
-#define OP_LHZU 41
-#define OP_LHA 42
-#define OP_LHAU 43
-#define OP_STH 44
-#define OP_STHU 45
-
void kvmppc_emulate_dec(struct kvm_vcpu *vcpu)
{
unsigned long dec_nsec;
--
1.8.0
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[PATCH 2/2 V8] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx
A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe
goes down. when the link goes down, Non-posted transactions issued
via the ATMU requiring completion result in an instruction stall.
At the same time a machine-check exception is generated to the core
to allow further processing by the handler. We implements the handler
which skips the instruction caused the stall.
This patch depends on patch:
powerpc/85xx: Add platform_device declaration to fsl_pci.h
Signed-off-by: Zhao Chenhui b35...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Liu Shuo soniccat@gmail.com
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
V8:
* Add A variant load instruction emulation.
V7:
* Correct PCIe checking method (Using indirect_type member of pci_controller
stucture).
V6:
* Move OP and XOP defines to a new header file: asm/ppc-disassemble.h
* Add X UX BRX variant of load instruction emulation
* Remove A variant of load instruction emulation
V5:
* Fill rd with all-Fs if the skipped instruction is load and emulate the
instruction.
* Let KVM/QEMU deal with the exception if the machine check comes from KVM.
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 2 +-
arch/powerpc/kernel/traps.c | 3 +
arch/powerpc/sysdev/fsl_pci.c | 158 ++
arch/powerpc/sysdev/fsl_pci.h | 6 ++
4 files changed, 168 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index 0b9af01..bfb18c7 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -75,7 +75,7 @@ _GLOBAL(__setup_cpu_e500v2)
bl __e500_icache_setup
bl __e500_dcache_setup
bl __setup_e500_ivors
-#ifdef CONFIG_FSL_RIO
+#if defined(CONFIG_FSL_RIO) || defined(CONFIG_FSL_PCI)
/* Ensure that RFXE is set */
mfspr r3,SPRN_HID1
orisr3,r3,HID1_RFXE@h
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 37cc40e..d15cfb5 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -60,6 +60,7 @@
#include asm/switch_to.h
#include asm/tm.h
#include asm/debug.h
+#include sysdev/fsl_pci.h
#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
int (*__debugger)(struct pt_regs *regs) __read_mostly;
@@ -565,6 +566,8 @@ int machine_check_e500(struct pt_regs *regs)
if (reason MCSR_BUS_RBERR) {
if (fsl_rio_mcheck_exception(regs))
return 1;
+ if (fsl_pci_mcheck_exception(regs))
+ return 1;
}
printk(Machine check in kernel mode.\n);
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 40ffe29..5fa851a 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -26,11 +26,15 @@
#include linux/memblock.h
#include linux/log2.h
#include linux/slab.h
+#include linux/uaccess.h
#include asm/io.h
#include asm/prom.h
#include asm/pci-bridge.h
+#include asm/ppc-pci.h
#include asm/machdep.h
+#include asm/disassemble.h
+#include asm/ppc-opcode.h
#include sysdev/fsl_soc.h
#include sysdev/fsl_pci.h
@@ -876,6 +880,160 @@ u64 fsl_pci_immrbar_base(struct pci_controller *hose)
return 0;
}
+#ifdef CONFIG_E500
+static int mcheck_handle_load(struct pt_regs *regs, u32 inst)
+{
+ unsigned int rd, ra, rb, d;
+
+ rd = get_rt(inst);
+ ra = get_ra(inst);
+ rb = get_rb(inst);
+ d = get_d(inst);
+
+ switch (get_op(inst)) {
+ case 31:
+ switch (get_xop(inst)) {
+ case OP_31_XOP_LWZX:
+ case OP_31_XOP_LWBRX:
+ regs-gpr[rd] = 0x;
+ break;
+
+ case OP_31_XOP_LWZUX:
+ regs-gpr[rd] = 0x;
+ regs-gpr[ra] += regs-gpr[rb];
+ break;
+
+ case OP_31_XOP_LBZX:
+ regs-gpr[rd] = 0xff;
+ break;
+
+ case OP_31_XOP_LBZUX:
+ regs-gpr[rd] = 0xff;
+ regs-gpr[ra] += regs-gpr[rb];
+ break;
+
+ case OP_31_XOP_LHZX:
+ case OP_31_XOP_LHBRX:
+ regs-gpr[rd] = 0x;
+ break;
+
+ case OP_31_XOP_LHZUX:
+ regs-gpr[rd] = 0x;
+ regs-gpr[ra] += regs-gpr[rb];
+ break;
+
+ case OP_31_XOP_LHAX:
+ regs-gpr[rd] = ~0UL;
+ break;
+
+ case OP_31_XOP_LHAUX:
+ regs-gpr[rd] = ~0UL;
+ regs-gpr[ra] += regs-gpr[rb];
+ break;
+
+ default:
+ return 0
RE: [PATCH 2/2 V7] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx
-Original Message- From: Segher Boessenkool [mailto:seg...@kernel.crashing.org] Sent: Saturday, April 27, 2013 9:32 PM To: Jia Hongtao-B38951 Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org Subject: Re: [PATCH 2/2 V7] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx In former email you doubt whether we need A variant or not. Any particular reason for that? If not should I emulate all the A ARX AU AUX and AX variant? A/AU/AX/AUX are just normal loads, sign-extended instead of zero-extended (so assign -1 to the register loaded). The ARX thing is load-locked, you do not want that one. Segher Thanks, very helpful. -Hongtao ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH 2/2 V7] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx
-Original Message- From: Wood Scott-B07421 Sent: Friday, April 26, 2013 12:58 AM To: Segher Boessenkool Cc: Jia Hongtao-B38951; linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org; Wood Scott-B07421 Subject: Re: [PATCH 2/2 V7] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx On 04/25/2013 10:31:51 AM, Segher Boessenkool wrote: * Remove A variant of load instruction emulation Why is this? You handle all other simple load insns, there is nothing special about LHA. (I reviewed the V4 email thread, no reason for the chance is given there). The LHA implementation in V5 was incorrect (didn't sign-extend). -Scott In former email you doubt whether we need A variant or not. Any particular reason for that? If not should I emulate all the A ARX AU AUX and AX variant? Thanks. -Hongtao. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH 1/2] powerpc: Move opcode definitions from kvm/emulate.c to asm/ppc-opcode.h
-Original Message- From: Benjamin Herrenschmidt [mailto:b...@kernel.crashing.org] Sent: Wednesday, April 24, 2013 12:19 PM To: Jia Hongtao-B38951 Cc: Michael Ellerman; Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH 1/2] powerpc: Move opcode definitions from kvm/emulate.c to asm/ppc-opcode.h On Tue, 2013-04-23 at 06:36 +, Jia Hongtao-B38951 wrote: These definitions are firstly used by KVM defined like OP_31_XOP_TRAP. Two ways to extract these definitions for public use: 1. Like this patch did. For keeping the KVM code that using these definitions unchanged we do not update them to match. 2. Move these definitions to another .h file like my last patch did: http://patchwork.ozlabs.org/patch/235646/ You can see the comments there. There's a better way ... but it's more work. All opcodes are based on a primary opcode and a potential secondary opcode. You could/should rework ppc-opcodes.h to in fact define them all that way as well, which would reconcile the KVM way and the existing stuff. Cheers, Ben. Agree. But I'm afraid to say that I'm too busy to do this more work right now. Could we defer this work for some time? Thanks. - Hongtao ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH 1/2] powerpc: Move opcode definitions from kvm/emulate.c to asm/ppc-opcode.h
-Original Message- From: Linuxppc-dev [mailto:linuxppc-dev- bounces+b38951=freescale@lists.ozlabs.org] On Behalf Of Michael Ellerman Sent: Tuesday, April 23, 2013 1:30 PM To: Jia Hongtao-B38951 Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH 1/2] powerpc: Move opcode definitions from kvm/emulate.c to asm/ppc-opcode.h On Tue, Apr 23, 2013 at 10:39:35AM +0800, Jia Hongtao wrote: Opcode and xopcode are useful definitions not just for KVM. Move these definitions to asm/ppc-opcode.h for public use. Agreed. Though nearly everything else in ppc-opcode.h uses PPC_INST_FOO, or at least PPC_FOO, any reason not to update these to match? cheers These definitions are firstly used by KVM defined like OP_31_XOP_TRAP. Two ways to extract these definitions for public use: 1. Like this patch did. For keeping the KVM code that using these definitions unchanged we do not update them to match. 2. Move these definitions to another .h file like my last patch did: http://patchwork.ozlabs.org/patch/235646/ You can see the comments there. Thanks. -Hongtao ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/2] powerpc: Move opcode definitions from kvm/emulate.c to asm/ppc-opcode.h
Opcode and xopcode are useful definitions not just for KVM. Move these
definitions to asm/ppc-opcode.h for public use.
Signed-off-by: Jia Hongtao hongtao@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
arch/powerpc/include/asm/ppc-opcode.h | 45 +++
arch/powerpc/kvm/emulate.c| 44 +-
2 files changed, 46 insertions(+), 43 deletions(-)
diff --git a/arch/powerpc/include/asm/ppc-opcode.h
b/arch/powerpc/include/asm/ppc-opcode.h
index 8752bc8..18de83a 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -81,6 +81,51 @@
#define__REGA0_R30 30
#define__REGA0_R31 31
+/* opcode and xopcode for instructions */
+#define OP_TRAP 3
+#define OP_TRAP_64 2
+
+#define OP_31_XOP_TRAP 4
+#define OP_31_XOP_LWZX 23
+#define OP_31_XOP_LWZUX 55
+#define OP_31_XOP_TRAP_64 68
+#define OP_31_XOP_DCBF 86
+#define OP_31_XOP_LBZX 87
+#define OP_31_XOP_STWX 151
+#define OP_31_XOP_STBX 215
+#define OP_31_XOP_LBZUX 119
+#define OP_31_XOP_STBUX 247
+#define OP_31_XOP_LHZX 279
+#define OP_31_XOP_LHZUX 311
+#define OP_31_XOP_MFSPR 339
+#define OP_31_XOP_LHAX 343
+#define OP_31_XOP_STHX 407
+#define OP_31_XOP_STHUX 439
+#define OP_31_XOP_MTSPR 467
+#define OP_31_XOP_DCBI 470
+#define OP_31_XOP_LWBRX 534
+#define OP_31_XOP_TLBSYNC 566
+#define OP_31_XOP_STWBRX662
+#define OP_31_XOP_LHBRX 790
+#define OP_31_XOP_STHBRX918
+
+#define OP_LWZ 32
+#define OP_LD 58
+#define OP_LWZU 33
+#define OP_LBZ 34
+#define OP_LBZU 35
+#define OP_STW 36
+#define OP_STWU 37
+#define OP_STD 62
+#define OP_STB 38
+#define OP_STBU 39
+#define OP_LHZ 40
+#define OP_LHZU 41
+#define OP_LHA 42
+#define OP_LHAU 43
+#define OP_STH 44
+#define OP_STHU 45
+
/* sorted alphabetically */
#define PPC_INST_DCBA 0x7c0005ec
#define PPC_INST_DCBA_MASK 0xfc0007fe
diff --git a/arch/powerpc/kvm/emulate.c b/arch/powerpc/kvm/emulate.c
index 7a73b6f..426d3f5 100644
--- a/arch/powerpc/kvm/emulate.c
+++ b/arch/powerpc/kvm/emulate.c
@@ -30,52 +30,10 @@
#include asm/byteorder.h
#include asm/kvm_ppc.h
#include asm/disassemble.h
+#include asm/ppc-opcode.h
#include timing.h
#include trace.h
-#define OP_TRAP 3
-#define OP_TRAP_64 2
-
-#define OP_31_XOP_TRAP 4
-#define OP_31_XOP_LWZX 23
-#define OP_31_XOP_TRAP_64 68
-#define OP_31_XOP_DCBF 86
-#define OP_31_XOP_LBZX 87
-#define OP_31_XOP_STWX 151
-#define OP_31_XOP_STBX 215
-#define OP_31_XOP_LBZUX 119
-#define OP_31_XOP_STBUX 247
-#define OP_31_XOP_LHZX 279
-#define OP_31_XOP_LHZUX 311
-#define OP_31_XOP_MFSPR 339
-#define OP_31_XOP_LHAX 343
-#define OP_31_XOP_STHX 407
-#define OP_31_XOP_STHUX 439
-#define OP_31_XOP_MTSPR 467
-#define OP_31_XOP_DCBI 470
-#define OP_31_XOP_LWBRX 534
-#define OP_31_XOP_TLBSYNC 566
-#define OP_31_XOP_STWBRX662
-#define OP_31_XOP_LHBRX 790
-#define OP_31_XOP_STHBRX918
-
-#define OP_LWZ 32
-#define OP_LD 58
-#define OP_LWZU 33
-#define OP_LBZ 34
-#define OP_LBZU 35
-#define OP_STW 36
-#define OP_STWU 37
-#define OP_STD 62
-#define OP_STB 38
-#define OP_STBU 39
-#define OP_LHZ 40
-#define OP_LHZU 41
-#define OP_LHA 42
-#define OP_LHAU 43
-#define OP_STH 44
-#define OP_STHU 45
-
void kvmppc_emulate_dec(struct kvm_vcpu *vcpu)
{
unsigned long dec_nsec;
--
1.8.0
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[PATCH 2/2 V7] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx
A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe
goes down. when the link goes down, Non-posted transactions issued
via the ATMU requiring completion result in an instruction stall.
At the same time a machine-check exception is generated to the core
to allow further processing by the handler. We implements the handler
which skips the instruction caused the stall.
This patch depends on patch:
powerpc/85xx: Add platform_device declaration to fsl_pci.h
Signed-off-by: Zhao Chenhui b35...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Liu Shuo soniccat@gmail.com
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
V6:
* Correct PCIe checking method (Using indirect_type member of pci_controller
stucture).
V5:
* Move OP and XOP defines to a new header file: asm/ppc-disassemble.h
* Add X UX BRX variant of load instruction emulation
* Remove A variant of load instruction emulation
V4:
* Fill rd with all-Fs if the skipped instruction is load and emulate the
instruction.
* Let KVM/QEMU deal with the exception if the machine check comes from KVM.
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 2 +-
arch/powerpc/kernel/traps.c | 3 +
arch/powerpc/sysdev/fsl_pci.c | 140 ++
arch/powerpc/sysdev/fsl_pci.h | 6 ++
4 files changed, 150 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index 0b9af01..bfb18c7 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -75,7 +75,7 @@ _GLOBAL(__setup_cpu_e500v2)
bl __e500_icache_setup
bl __e500_dcache_setup
bl __setup_e500_ivors
-#ifdef CONFIG_FSL_RIO
+#if defined(CONFIG_FSL_RIO) || defined(CONFIG_FSL_PCI)
/* Ensure that RFXE is set */
mfspr r3,SPRN_HID1
orisr3,r3,HID1_RFXE@h
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 37cc40e..d15cfb5 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -60,6 +60,7 @@
#include asm/switch_to.h
#include asm/tm.h
#include asm/debug.h
+#include sysdev/fsl_pci.h
#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
int (*__debugger)(struct pt_regs *regs) __read_mostly;
@@ -565,6 +566,8 @@ int machine_check_e500(struct pt_regs *regs)
if (reason MCSR_BUS_RBERR) {
if (fsl_rio_mcheck_exception(regs))
return 1;
+ if (fsl_pci_mcheck_exception(regs))
+ return 1;
}
printk(Machine check in kernel mode.\n);
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 40ffe29..6bddf0f 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -26,11 +26,15 @@
#include linux/memblock.h
#include linux/log2.h
#include linux/slab.h
+#include linux/uaccess.h
#include asm/io.h
#include asm/prom.h
#include asm/pci-bridge.h
+#include asm/ppc-pci.h
#include asm/machdep.h
+#include asm/disassemble.h
+#include asm/ppc-opcode.h
#include sysdev/fsl_soc.h
#include sysdev/fsl_pci.h
@@ -876,6 +880,142 @@ u64 fsl_pci_immrbar_base(struct pci_controller *hose)
return 0;
}
+#ifdef CONFIG_E500
+static int mcheck_handle_load(struct pt_regs *regs, u32 inst)
+{
+ unsigned int rd, ra, rb, d;
+
+ rd = get_rt(inst);
+ ra = get_ra(inst);
+ rb = get_rb(inst);
+ d = get_d(inst);
+
+ switch (get_op(inst)) {
+ case 31:
+ switch (get_xop(inst)) {
+ case OP_31_XOP_LWZX:
+ case OP_31_XOP_LWBRX:
+ regs-gpr[rd] = 0x;
+ break;
+
+ case OP_31_XOP_LWZUX:
+ regs-gpr[rd] = 0x;
+ regs-gpr[ra] += regs-gpr[rb];
+ break;
+
+ case OP_31_XOP_LBZX:
+ regs-gpr[rd] = 0xff;
+ break;
+
+ case OP_31_XOP_LBZUX:
+ regs-gpr[rd] = 0xff;
+ regs-gpr[ra] += regs-gpr[rb];
+ break;
+
+ case OP_31_XOP_LHZX:
+ case OP_31_XOP_LHBRX:
+ regs-gpr[rd] = 0x;
+ break;
+
+ case OP_31_XOP_LHZUX:
+ regs-gpr[rd] = 0x;
+ regs-gpr[ra] += regs-gpr[rb];
+ break;
+
+ default:
+ return 0;
+ }
+ break;
+
+ case OP_LWZ:
+ regs-gpr[rd] = 0x;
+ break;
+
+ case OP_LWZU:
+ regs-gpr[rd] = 0x;
+ regs-gpr[ra] += (s16)d;
+ break;
+
+ case OP_LBZ:
+ regs-gpr[rd] = 0xff;
+ break;
+
+ case
RE: [PATCH V5] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, April 11, 2013 5:52 AM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org; Wood Scott-
B07421; Li Yang-R58472; Jia Hongtao-B38951
Subject: Re: [PATCH V5] powerpc/85xx: Add machine check handler to fix
PCIe erratum on mpc85xx
On 04/08/2013 03:26:54 AM, Jia Hongtao wrote:
@@ -826,6 +829,124 @@ u64 fsl_pci_immrbar_base(struct pci_controller
*hose)
return 0;
}
+#ifdef CONFIG_E500
+
+#define OP_LWZ 32
+#define OP_LWZU 33
+#define OP_LBZ 34
+#define OP_LBZU 35
+#define OP_LHZ 40
+#define OP_LHZU 41
+#define OP_LHA 42
+#define OP_LHAU 43
Can you move these to asm/ppc-opcode.h (or possibly
asm/ppc-disassemble.h if we don't want to mix the two methods of
describing instructions)?
Yes, mix the two methods is not appropriate.
asm/ppc-disassemble.h is a nice choice.
+static int mcheck_handle_load(struct pt_regs *regs, u32 inst)
+{
+ unsigned int rd, ra, d;
+
+ rd = get_rt(inst);
+ ra = get_ra(inst);
+ d = get_d(inst);
+
+ switch (get_op(inst)) {
+ case OP_LWZ:
+ regs-gpr[rd] = 0x;
+ break;
+
+ case OP_LWZU:
+ regs-gpr[rd] = 0x;
+ regs-gpr[ra] += (s16)d;
+ break;
+
+ case OP_LBZ:
+ regs-gpr[rd] = 0xff;
+ break;
+
+ case OP_LBZU:
+ regs-gpr[rd] = 0xff;
+ regs-gpr[ra] += (s16)d;
+ break;
+
+ case OP_LHZ:
+ regs-gpr[rd] = 0x;
+ break;
+
+ case OP_LHZU:
+ regs-gpr[rd] = 0x;
+ regs-gpr[ra] += (s16)d;
+ break;
+
+ case OP_LHA:
+ regs-gpr[rd] = 0x;
+ break;
+
+ case OP_LHAU:
+ regs-gpr[rd] = 0x;
+ regs-gpr[ra] += (s16)d;
+ break;
The X and (especially for PCI) BRX versions are important -- probably
more so than the U versions. I doubt we need the A variant.
Then I will add X and BRX variant and remove A variant.
If you do support the A variant, why are you not sign-extending the
value?
Just curious, sign-extending the value means fill rd with 0x?
Is this erratum present on any 64-bit chips?
No. This erratum only happened in e500 core chips.
-Scott
Thanks.
-Hongtao
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[PATCH V6] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx
A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe
goes down. when the link goes down, Non-posted transactions issued
via the ATMU requiring completion result in an instruction stall.
At the same time a machine-check exception is generated to the core
to allow further processing by the handler. We implements the handler
which skips the instruction caused the stall.
This patch depends on patch:
powerpc/85xx: Add platform_device declaration to fsl_pci.h
Signed-off-by: Zhao Chenhui b35...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Liu Shuo soniccat@gmail.com
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
V5:
* Move OP and XOP defines to a new header file: asm/ppc-disassemble.h
* Add X UX BRX variant of load instruction emulation
* Remove A variant of load instruction emulation
V4:
* Fill rd with all-Fs if the skipped instruction is load and emulate the
instruction.
* Let KVM/QEMU deal with the exception if the machine check comes from KVM.
arch/powerpc/include/asm/ppc-disassemble.h | 31 +++
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 2 +-
arch/powerpc/kernel/traps.c| 3 +
arch/powerpc/sysdev/fsl_pci.c | 140 +
arch/powerpc/sysdev/fsl_pci.h | 6 ++
5 files changed, 181 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/include/asm/ppc-disassemble.h
diff --git a/arch/powerpc/include/asm/ppc-disassemble.h
b/arch/powerpc/include/asm/ppc-disassemble.h
new file mode 100644
index 000..f9782b8
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc-disassemble.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * provides opcode and xopcode images for use by emulating
+ * instructions
+ */
+#ifndef _ASM_POWERPC_PPC_DISASSEMBLE_H
+#define _ASM_POWERPC_PPC_DISASSEMBLE_H
+
+#define OP_LWZ 32
+#define OP_LWZU 33
+#define OP_LBZ 34
+#define OP_LBZU 35
+#define OP_LHZ 40
+#define OP_LHZU 41
+
+#define OP_31_XOP_LWZX 23
+#define OP_31_XOP_LWZUX 55
+#define OP_31_XOP_LBZX 87
+#define OP_31_XOP_LBZUX 119
+#define OP_31_XOP_LHZX 279
+#define OP_31_XOP_LHZUX 311
+#define OP_31_XOP_LWBRX 534
+#define OP_31_XOP_LHBRX 790
+
+#endif
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index dcd8819..f1bde90 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -66,7 +66,7 @@ _GLOBAL(__setup_cpu_e500v2)
bl __e500_icache_setup
bl __e500_dcache_setup
bl __setup_e500_ivors
-#ifdef CONFIG_FSL_RIO
+#if defined(CONFIG_FSL_RIO) || defined(CONFIG_FSL_PCI)
/* Ensure that RFXE is set */
mfspr r3,SPRN_HID1
orisr3,r3,HID1_RFXE@h
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index a008cf5..dd275a4 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -59,6 +59,7 @@
#include asm/fadump.h
#include asm/switch_to.h
#include asm/debug.h
+#include sysdev/fsl_pci.h
#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
int (*__debugger)(struct pt_regs *regs) __read_mostly;
@@ -556,6 +557,8 @@ int machine_check_e500(struct pt_regs *regs)
if (reason MCSR_BUS_RBERR) {
if (fsl_rio_mcheck_exception(regs))
return 1;
+ if (fsl_pci_mcheck_exception(regs))
+ return 1;
}
printk(Machine check in kernel mode.\n);
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 682084d..aaa54c5 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -26,11 +26,15 @@
#include linux/memblock.h
#include linux/log2.h
#include linux/slab.h
+#include linux/uaccess.h
#include asm/io.h
#include asm/prom.h
#include asm/pci-bridge.h
+#include asm/ppc-pci.h
#include asm/machdep.h
+#include asm/disassemble.h
+#include asm/ppc-disassemble.h
#include sysdev/fsl_soc.h
#include sysdev/fsl_pci.h
@@ -826,6 +830,142 @@ u64 fsl_pci_immrbar_base(struct pci_controller *hose)
return 0;
}
+#ifdef CONFIG_E500
+static int mcheck_handle_load(struct pt_regs *regs, u32 inst)
+{
+ unsigned int rd, ra, rb, d;
+
+ rd = get_rt(inst);
+ ra = get_ra(inst);
+ rb = get_rb(inst);
+ d = get_d(inst);
+
+ switch (get_op(inst)) {
+ case 31:
+ switch (get_xop(inst)) {
+ case OP_31_XOP_LWZX:
+ case OP_31_XOP_LWBRX:
+ regs-gpr[rd] = 0x;
+ break;
+
+ case OP_31_XOP_LWZUX
RE: [PATCH V6] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Thursday, April 11, 2013 9:47 PM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Li Yang-R58472
Subject: Re: [PATCH V6] powerpc/85xx: Add machine check handler to fix
PCIe erratum on mpc85xx
On Apr 11, 2013, at 3:36 AM, Jia Hongtao wrote:
A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe
goes down. when the link goes down, Non-posted transactions issued via
the ATMU requiring completion result in an instruction stall.
At the same time a machine-check exception is generated to the core to
allow further processing by the handler. We implements the handler
which skips the instruction caused the stall.
This patch depends on patch:
powerpc/85xx: Add platform_device declaration to fsl_pci.h
Signed-off-by: Zhao Chenhui b35...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Liu Shuo soniccat@gmail.com
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
V5:
* Move OP and XOP defines to a new header file: asm/ppc-disassemble.h
* Add X UX BRX variant of load instruction emulation
* Remove A variant of load instruction emulation
V4:
* Fill rd with all-Fs if the skipped instruction is load and emulate
the instruction.
* Let KVM/QEMU deal with the exception if the machine check comes from
KVM.
arch/powerpc/include/asm/ppc-disassemble.h | 31 +++
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 2 +-
arch/powerpc/kernel/traps.c| 3 +
arch/powerpc/sysdev/fsl_pci.c | 140
+
arch/powerpc/sysdev/fsl_pci.h | 6 ++
5 files changed, 181 insertions(+), 1 deletion(-) create mode 100644
arch/powerpc/include/asm/ppc-disassemble.h
diff --git a/arch/powerpc/include/asm/ppc-disassemble.h
b/arch/powerpc/include/asm/ppc-disassemble.h
new file mode 100644
index 000..f9782b8
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc-disassemble.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * provides opcode and xopcode images for use by emulating
+ * instructions
+ */
+#ifndef _ASM_POWERPC_PPC_DISASSEMBLE_H #define
+_ASM_POWERPC_PPC_DISASSEMBLE_H
+
This should really just be in asm/ppc-opcode.h
Hi Kumar and Scott,
This is the different method of describing instructions so I put them
in a new file.
But I agree that a patch to extract these from existing code is more
well-organized.
Is that OK if I extract these definitions from arch/powerpc/kvm/emulate.c
to asm/ppc-opcode.h? Even though These definitions are different.
Scott,
What's your opinion on this?
+#define OP_LWZ 32
+#define OP_LWZU 33
+#define OP_LBZ 34
+#define OP_LBZU 35
+#define OP_LHZ 40
+#define OP_LHZU 41
+
+#define OP_31_XOP_LWZX 23
+#define OP_31_XOP_LWZUX 55
+#define OP_31_XOP_LBZX 87
+#define OP_31_XOP_LBZUX 119
+#define OP_31_XOP_LHZX 279
+#define OP_31_XOP_LHZUX 311
+#define OP_31_XOP_LWBRX 534
+#define OP_31_XOP_LHBRX 790
+
Also, submit a patch to extract these from existing code so we stop
duplicating them everywhere.
+#endif
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index dcd8819..f1bde90 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -66,7 +66,7 @@ _GLOBAL(__setup_cpu_e500v2)
bl __e500_icache_setup
bl __e500_dcache_setup
bl __setup_e500_ivors
-#ifdef CONFIG_FSL_RIO
+#if defined(CONFIG_FSL_RIO) || defined(CONFIG_FSL_PCI)
/* Ensure that RFXE is set */
mfspr r3,SPRN_HID1
orisr3,r3,HID1_RFXE@h
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index a008cf5..dd275a4 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -59,6 +59,7 @@
#include asm/fadump.h
#include asm/switch_to.h
#include asm/debug.h
+#include sysdev/fsl_pci.h
#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) int
(*__debugger)(struct pt_regs *regs) __read_mostly; @@ -556,6 +557,8 @@
int machine_check_e500(struct pt_regs *regs)
if (reason MCSR_BUS_RBERR) {
if (fsl_rio_mcheck_exception(regs))
return 1;
+ if (fsl_pci_mcheck_exception(regs))
+ return 1;
}
printk(Machine check in kernel mode.\n); diff --git
a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index
682084d..aaa54c5 100644
--- a/arch/powerpc/sysdev
RE: [PATCH V5] powerpc/MPIC: Add get_version API both for internal and external use
Hi Kumar,
Scott reviewed this patch and MSI errata patch for weeks.
Here is the link for MSI errata patch:
http://patchwork.ozlabs.org/patch/233211/
Could you please have a review and ACK them if they
look good to you too?
Thanks.
- Hongtao
-Original Message-
From: Jia Hongtao-B38951
Sent: Wednesday, April 10, 2013 10:53 AM
To: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org
Cc: Wood Scott-B07421; Li Yang-R58472; Jia Hongtao-B38951
Subject: [PATCH V5] powerpc/MPIC: Add get_version API both for internal
and external use
MPIC version is useful information for both mpic_alloc() and mpic_init().
The patch provide an API to get MPIC version for reusing the code.
Also, some other IP block may need MPIC version for their own use.
The API for external use is also provided.
Signed-off-by: Jia Hongtao hongtao@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
V5:
* add MPIC_FSL check for fsl_mpic_get_version().
V4:
* change the name of function from mpic_get_version() to
fsl_mpic_get_version().
V3:
* change the name of function from mpic_primary_get_version() to
fsl_mpic_primary_get_version().
* return 0 if mpic_primary is null.
V2:
* Using mpic_get_version() to implement mpic_primary_get_version()
arch/powerpc/include/asm/mpic.h | 3 +++
arch/powerpc/sysdev/mpic.c | 32 +---
2 files changed, 28 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/include/asm/mpic.h
b/arch/powerpc/include/asm/mpic.h index c0f9ef9..ea6bf72 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -393,6 +393,9 @@ struct mpic
#define MPIC_REGSET_STANDARDMPIC_REGSET(0) /* Original
MPIC */
#define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109
PIC */
+/* Get the version of primary MPIC */
+extern u32 fsl_mpic_primary_get_version(void);
+
/* Allocate the controller structure and setup the linux irq descs
* for the range if interrupts passed in. No HW initialization is
* actually performed.
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index d30e6a6..47ef4ba 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1165,10 +1165,33 @@ static struct irq_domain_ops mpic_host_ops = {
.xlate = mpic_host_xlate,
};
+static u32 fsl_mpic_get_version(struct mpic *mpic) {
+ u32 brr1;
+
+ if (!(mpic-flags MPIC_FSL))
+ return 0;
+
+ brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
+ MPIC_FSL_BRR1);
+
+ return brr1 MPIC_FSL_BRR1_VER;
+}
+
/*
* Exported functions
*/
+u32 fsl_mpic_primary_get_version(void)
+{
+ struct mpic *mpic = mpic_primary;
+
+ if (mpic)
+ return fsl_mpic_get_version(mpic);
+
+ return 0;
+}
+
struct mpic * __init mpic_alloc(struct device_node *node,
phys_addr_t phys_addr,
unsigned int flags,
@@ -1315,7 +1338,6 @@ struct mpic * __init mpic_alloc(struct device_node
*node,
mpic_map(mpic, mpic-paddr, mpic-tmregs, MPIC_INFO(TIMER_BASE),
0x1000);
if (mpic-flags MPIC_FSL) {
- u32 brr1;
int ret;
/*
@@ -1326,9 +1348,7 @@ struct mpic * __init mpic_alloc(struct device_node
*node,
mpic_map(mpic, mpic-paddr, mpic-thiscpuregs,
MPIC_CPU_THISBASE, 0x1000);
- brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
- MPIC_FSL_BRR1);
- fsl_version = brr1 MPIC_FSL_BRR1_VER;
+ fsl_version = fsl_mpic_get_version(mpic);
/* Error interrupt mask register (EIMR) is required for
* handling individual device error interrupts. EIMR @@ -
1518,9 +1538,7 @@ void __init mpic_init(struct mpic *mpic)
mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
if (mpic-flags MPIC_FSL) {
- u32 brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
- MPIC_FSL_BRR1);
- u32 version = brr1 MPIC_FSL_BRR1_VER;
+ u32 version = fsl_mpic_get_version(mpic);
/*
* Timer group B is present at the latest in MPIC 3.1 (e.g.
--
1.8.0
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RE: [PATCH V4] powerpc/MPIC: Add get_version API both for internal and external use
Hi Kumar and Scott,
Any more comments for this patch and MSI-X erratum patch?
Thanks.
-Hongtao.
-Original Message-
From: Jia Hongtao-B38951
Sent: Monday, April 08, 2013 10:02 AM
To: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org
Cc: Wood Scott-B07421; Li Yang-R58472; Jia Hongtao-B38951
Subject: [PATCH V4] powerpc/MPIC: Add get_version API both for internal
and external use
MPIC version is useful information for both mpic_alloc() and mpic_init().
The patch provide an API to get MPIC version for reusing the code.
Also, some other IP block may need MPIC version for their own use.
The API for external use is also provided.
Signed-off-by: Jia Hongtao hongtao@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
Changes for V4:
* change the name of function from mpic_get_version() to
fsl_mpic_get_version().
Changes for V3:
* change the name of function from mpic_primary_get_version() to
fsl_mpic_primary_get_version().
* return 0 if mpic_primary is null.
Changes for V2:
* Using mpic_get_version() to implement mpic_primary_get_version()
arch/powerpc/include/asm/mpic.h | 3 +++
arch/powerpc/sysdev/mpic.c | 29 ++---
2 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/include/asm/mpic.h
b/arch/powerpc/include/asm/mpic.h index c0f9ef9..ea6bf72 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -393,6 +393,9 @@ struct mpic
#define MPIC_REGSET_STANDARDMPIC_REGSET(0) /* Original
MPIC */
#define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109
PIC */
+/* Get the version of primary MPIC */
+extern u32 fsl_mpic_primary_get_version(void);
+
/* Allocate the controller structure and setup the linux irq descs
* for the range if interrupts passed in. No HW initialization is
* actually performed.
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index d30e6a6..48c8fae 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1165,10 +1165,30 @@ static struct irq_domain_ops mpic_host_ops = {
.xlate = mpic_host_xlate,
};
+static u32 fsl_mpic_get_version(struct mpic *mpic) {
+ u32 brr1;
+
+ brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
+ MPIC_FSL_BRR1);
+
+ return brr1 MPIC_FSL_BRR1_VER;
+}
+
/*
* Exported functions
*/
+u32 fsl_mpic_primary_get_version(void)
+{
+ struct mpic *mpic = mpic_primary;
+
+ if (mpic)
+ return fsl_mpic_get_version(mpic);
+
+ return 0;
+}
+
struct mpic * __init mpic_alloc(struct device_node *node,
phys_addr_t phys_addr,
unsigned int flags,
@@ -1315,7 +1335,6 @@ struct mpic * __init mpic_alloc(struct device_node
*node,
mpic_map(mpic, mpic-paddr, mpic-tmregs, MPIC_INFO(TIMER_BASE),
0x1000);
if (mpic-flags MPIC_FSL) {
- u32 brr1;
int ret;
/*
@@ -1326,9 +1345,7 @@ struct mpic * __init mpic_alloc(struct device_node
*node,
mpic_map(mpic, mpic-paddr, mpic-thiscpuregs,
MPIC_CPU_THISBASE, 0x1000);
- brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
- MPIC_FSL_BRR1);
- fsl_version = brr1 MPIC_FSL_BRR1_VER;
+ fsl_version = fsl_mpic_get_version(mpic);
/* Error interrupt mask register (EIMR) is required for
* handling individual device error interrupts. EIMR @@ -
1518,9 +1535,7 @@ void __init mpic_init(struct mpic *mpic)
mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
if (mpic-flags MPIC_FSL) {
- u32 brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
- MPIC_FSL_BRR1);
- u32 version = brr1 MPIC_FSL_BRR1_VER;
+ u32 version = fsl_mpic_get_version(mpic);
/*
* Timer group B is present at the latest in MPIC 3.1 (e.g.
--
1.8.0
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RE: [PATCH V4] powerpc/MPIC: Add get_version API both for internal and external use
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, April 10, 2013 10:32 AM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org; Wood Scott-
B07421; Li Yang-R58472; Jia Hongtao-B38951
Subject: Re: [PATCH V4] powerpc/MPIC: Add get_version API both for
internal and external use
On 04/07/2013 09:01:54 PM, Jia Hongtao wrote:
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index d30e6a6..48c8fae 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1165,10 +1165,30 @@ static struct irq_domain_ops mpic_host_ops = {
.xlate = mpic_host_xlate,
};
+static u32 fsl_mpic_get_version(struct mpic *mpic) {
+ u32 brr1;
+
+ brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
+ MPIC_FSL_BRR1);
+
+ return brr1 MPIC_FSL_BRR1_VER;
+}
If it's not an FSL mpic, thiscpuregs-base will be NULL. Please check
mpic-flags for MPIC_FSL.
I will add the check soon.
+
/*
* Exported functions
*/
+u32 fsl_mpic_primary_get_version(void)
+{
+ struct mpic *mpic = mpic_primary;
+
+ if (mpic)
+ return fsl_mpic_get_version(mpic);
+
+ return 0;
+}
...especially since the external version doesn't check for it either.
Otherwise, this and the MSI-X patch look OK to me.
-Scott
Thanks.
-Hongtao.
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RE: [PATCH V4] powerpc/MPIC: Add get_version API both for internal and external use
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, April 10, 2013 10:32 AM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org; Wood Scott-
B07421; Li Yang-R58472; Jia Hongtao-B38951
Subject: Re: [PATCH V4] powerpc/MPIC: Add get_version API both for
internal and external use
On 04/07/2013 09:01:54 PM, Jia Hongtao wrote:
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index d30e6a6..48c8fae 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1165,10 +1165,30 @@ static struct irq_domain_ops mpic_host_ops = {
.xlate = mpic_host_xlate,
};
+static u32 fsl_mpic_get_version(struct mpic *mpic) {
+ u32 brr1;
+
+ brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
+ MPIC_FSL_BRR1);
+
+ return brr1 MPIC_FSL_BRR1_VER;
+}
If it's not an FSL mpic, thiscpuregs-base will be NULL. Please check
mpic-flags for MPIC_FSL.
+
/*
* Exported functions
*/
+u32 fsl_mpic_primary_get_version(void)
+{
+ struct mpic *mpic = mpic_primary;
+
+ if (mpic)
+ return fsl_mpic_get_version(mpic);
+
+ return 0;
+}
...especially since the external version doesn't check for it either.
Otherwise, this and the MSI-X patch look OK to me.
-Scott
Since all the functions including mpic_alloc() and mpic_init() do the
check for MPIC_FSL before using fsl_mpic_get_version() I'd like to add
check just for fsl_mpic_primary_get_version().
It will be like this:
u32 fsl_mpic_primary_get_version(void)
{
struct mpic *mpic = mpic_primary;
if (mpic (mpic-flags MPIC_FSL))
return fsl_mpic_get_version(mpic);
return 0;
}
Could we reach an agreement here?
Thanks.
-Hongtao.
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RE: [PATCH V4] powerpc/MPIC: Add get_version API both for internal and external use
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, April 10, 2013 11:08 AM
To: Jia Hongtao-B38951
Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org;
ga...@kernel.crashing.org; Li Yang-R58472
Subject: Re: [PATCH V4] powerpc/MPIC: Add get_version API both for
internal and external use
On 04/09/2013 10:04:44 PM, Jia Hongtao-B38951 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, April 10, 2013 10:32 AM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org; Wood
Scott-
B07421; Li Yang-R58472; Jia Hongtao-B38951
Subject: Re: [PATCH V4] powerpc/MPIC: Add get_version API both for
internal and external use
On 04/07/2013 09:01:54 PM, Jia Hongtao wrote:
diff --git a/arch/powerpc/sysdev/mpic.c
b/arch/powerpc/sysdev/mpic.c
index d30e6a6..48c8fae 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1165,10 +1165,30 @@ static struct irq_domain_ops
mpic_host_ops = {
.xlate = mpic_host_xlate,
};
+static u32 fsl_mpic_get_version(struct mpic *mpic) {
+ u32 brr1;
+
+ brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
+ MPIC_FSL_BRR1);
+
+ return brr1 MPIC_FSL_BRR1_VER;
+}
If it's not an FSL mpic, thiscpuregs-base will be NULL. Please
check
mpic-flags for MPIC_FSL.
+
/*
* Exported functions
*/
+u32 fsl_mpic_primary_get_version(void)
+{
+ struct mpic *mpic = mpic_primary;
+
+ if (mpic)
+ return fsl_mpic_get_version(mpic);
+
+ return 0;
+}
...especially since the external version doesn't check for it
either.
Otherwise, this and the MSI-X patch look OK to me.
-Scott
Since all the functions including mpic_alloc() and mpic_init() do the
check for MPIC_FSL before using fsl_mpic_get_version() I'd like to add
check just for fsl_mpic_primary_get_version().
It will be like this:
u32 fsl_mpic_primary_get_version(void)
{
struct mpic *mpic = mpic_primary;
if (mpic (mpic-flags MPIC_FSL))
return fsl_mpic_get_version(mpic);
return 0;
}
Could we reach an agreement here?
Is there any particular reason? It would be more robust and more
consistent if the check were done in fsl_mpic_get_version().
-Scott
I found out that all the functions using fsl_mpic_get_version() have
already done the check. Adding the check in fsl_mpic_get_version() will
cause duplicate check there. This is my consideration.
-Hongtao.
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RE: [PATCH V4] powerpc/MPIC: Add get_version API both for internal and external use
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, April 10, 2013 11:12 AM
To: Jia Hongtao-B38951
Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org;
ga...@kernel.crashing.org; Li Yang-R58472
Subject: Re: [PATCH V4] powerpc/MPIC: Add get_version API both for
internal and external use
On 04/09/2013 10:10:37 PM, Jia Hongtao-B38951 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, April 10, 2013 11:08 AM
To: Jia Hongtao-B38951
Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org;
ga...@kernel.crashing.org; Li Yang-R58472
Subject: Re: [PATCH V4] powerpc/MPIC: Add get_version API both for
internal and external use
On 04/09/2013 10:04:44 PM, Jia Hongtao-B38951 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, April 10, 2013 10:32 AM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org;
Wood
Scott-
B07421; Li Yang-R58472; Jia Hongtao-B38951
Subject: Re: [PATCH V4] powerpc/MPIC: Add get_version API both
for
internal and external use
On 04/07/2013 09:01:54 PM, Jia Hongtao wrote:
diff --git a/arch/powerpc/sysdev/mpic.c
b/arch/powerpc/sysdev/mpic.c
index d30e6a6..48c8fae 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1165,10 +1165,30 @@ static struct irq_domain_ops
mpic_host_ops = {
.xlate = mpic_host_xlate,
};
+static u32 fsl_mpic_get_version(struct mpic *mpic) {
+ u32 brr1;
+
+ brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
+ MPIC_FSL_BRR1);
+
+ return brr1 MPIC_FSL_BRR1_VER; }
If it's not an FSL mpic, thiscpuregs-base will be NULL. Please
check
mpic-flags for MPIC_FSL.
+
/*
* Exported functions
*/
+u32 fsl_mpic_primary_get_version(void)
+{
+ struct mpic *mpic = mpic_primary;
+
+ if (mpic)
+ return fsl_mpic_get_version(mpic);
+
+ return 0;
+}
...especially since the external version doesn't check for it
either.
Otherwise, this and the MSI-X patch look OK to me.
-Scott
Since all the functions including mpic_alloc() and mpic_init() do
the
check for MPIC_FSL before using fsl_mpic_get_version() I'd like
to add
check just for fsl_mpic_primary_get_version().
It will be like this:
u32 fsl_mpic_primary_get_version(void)
{
struct mpic *mpic = mpic_primary;
if (mpic (mpic-flags MPIC_FSL))
return fsl_mpic_get_version(mpic);
return 0;
}
Could we reach an agreement here?
Is there any particular reason? It would be more robust and more
consistent if the check were done in fsl_mpic_get_version().
-Scott
I found out that all the functions using fsl_mpic_get_version() have
already done the check. Adding the check in fsl_mpic_get_version()
will cause duplicate check there. This is my consideration.
Does that duplicate check cause any harm?
-Scott
No harm at all just not necessary.
I wonder if I could add check in fsl_mpic_get_version() and remove all the
check from functions in which using fsl_mpic_get_version()?
-Hongtao.
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RE: [PATCH V4] powerpc/MPIC: Add get_version API both for internal and external use
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, April 10, 2013 11:20 AM
To: Jia Hongtao-B38951
Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org;
ga...@kernel.crashing.org; Li Yang-R58472
Subject: Re: [PATCH V4] powerpc/MPIC: Add get_version API both for
internal and external use
On 04/09/2013 10:14:06 PM, Jia Hongtao-B38951 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, April 10, 2013 11:12 AM
To: Jia Hongtao-B38951
Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org;
ga...@kernel.crashing.org; Li Yang-R58472
Subject: Re: [PATCH V4] powerpc/MPIC: Add get_version API both for
internal and external use
On 04/09/2013 10:10:37 PM, Jia Hongtao-B38951 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, April 10, 2013 11:08 AM
To: Jia Hongtao-B38951
Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org;
ga...@kernel.crashing.org; Li Yang-R58472
Subject: Re: [PATCH V4] powerpc/MPIC: Add get_version API both
for
internal and external use
On 04/09/2013 10:04:44 PM, Jia Hongtao-B38951 wrote:
Since all the functions including mpic_alloc() and
mpic_init() do
the
check for MPIC_FSL before using fsl_mpic_get_version() I'd
like
to add
check just for fsl_mpic_primary_get_version().
It will be like this:
u32 fsl_mpic_primary_get_version(void)
{
struct mpic *mpic = mpic_primary;
if (mpic (mpic-flags MPIC_FSL))
return fsl_mpic_get_version(mpic);
return 0;
}
Could we reach an agreement here?
Is there any particular reason? It would be more robust and
more
consistent if the check were done in fsl_mpic_get_version().
-Scott
I found out that all the functions using fsl_mpic_get_version()
have
already done the check. Adding the check in fsl_mpic_get_version()
will cause duplicate check there. This is my consideration.
Does that duplicate check cause any harm?
-Scott
No harm at all just not necessary.
Not *necessary*, but makes it more robust and more consistent.
I wonder if I could add check in fsl_mpic_get_version() and remove
all the
check from functions in which using fsl_mpic_get_version()?
One of the two places that calls it is the place that maps thiscpuregs
in the first place, so no. :-)
Reasonable enough.
I will just add check in fsl_mpic_get_version().
Thanks.
-Hongtao.
The check in mpic_init() for the number of timers could perhaps have
the check removed if we're comfortable equating a version of zero with
a non-FSL MPIC. This really isn't something that's worth worrying
about, though.
-Scott
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[PATCH V5] powerpc/MPIC: Add get_version API both for internal and external use
MPIC version is useful information for both mpic_alloc() and mpic_init().
The patch provide an API to get MPIC version for reusing the code.
Also, some other IP block may need MPIC version for their own use.
The API for external use is also provided.
Signed-off-by: Jia Hongtao hongtao@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
V5:
* add MPIC_FSL check for fsl_mpic_get_version().
V4:
* change the name of function from mpic_get_version() to
fsl_mpic_get_version().
V3:
* change the name of function from mpic_primary_get_version() to
fsl_mpic_primary_get_version().
* return 0 if mpic_primary is null.
V2:
* Using mpic_get_version() to implement mpic_primary_get_version()
arch/powerpc/include/asm/mpic.h | 3 +++
arch/powerpc/sysdev/mpic.c | 32 +---
2 files changed, 28 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index c0f9ef9..ea6bf72 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -393,6 +393,9 @@ struct mpic
#defineMPIC_REGSET_STANDARDMPIC_REGSET(0) /* Original
MPIC */
#defineMPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109
PIC */
+/* Get the version of primary MPIC */
+extern u32 fsl_mpic_primary_get_version(void);
+
/* Allocate the controller structure and setup the linux irq descs
* for the range if interrupts passed in. No HW initialization is
* actually performed.
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index d30e6a6..47ef4ba 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1165,10 +1165,33 @@ static struct irq_domain_ops mpic_host_ops = {
.xlate = mpic_host_xlate,
};
+static u32 fsl_mpic_get_version(struct mpic *mpic)
+{
+ u32 brr1;
+
+ if (!(mpic-flags MPIC_FSL))
+ return 0;
+
+ brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
+ MPIC_FSL_BRR1);
+
+ return brr1 MPIC_FSL_BRR1_VER;
+}
+
/*
* Exported functions
*/
+u32 fsl_mpic_primary_get_version(void)
+{
+ struct mpic *mpic = mpic_primary;
+
+ if (mpic)
+ return fsl_mpic_get_version(mpic);
+
+ return 0;
+}
+
struct mpic * __init mpic_alloc(struct device_node *node,
phys_addr_t phys_addr,
unsigned int flags,
@@ -1315,7 +1338,6 @@ struct mpic * __init mpic_alloc(struct device_node *node,
mpic_map(mpic, mpic-paddr, mpic-tmregs, MPIC_INFO(TIMER_BASE),
0x1000);
if (mpic-flags MPIC_FSL) {
- u32 brr1;
int ret;
/*
@@ -1326,9 +1348,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
mpic_map(mpic, mpic-paddr, mpic-thiscpuregs,
MPIC_CPU_THISBASE, 0x1000);
- brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
- MPIC_FSL_BRR1);
- fsl_version = brr1 MPIC_FSL_BRR1_VER;
+ fsl_version = fsl_mpic_get_version(mpic);
/* Error interrupt mask register (EIMR) is required for
* handling individual device error interrupts. EIMR
@@ -1518,9 +1538,7 @@ void __init mpic_init(struct mpic *mpic)
mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
if (mpic-flags MPIC_FSL) {
- u32 brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
- MPIC_FSL_BRR1);
- u32 version = brr1 MPIC_FSL_BRR1_VER;
+ u32 version = fsl_mpic_get_version(mpic);
/*
* Timer group B is present at the latest in MPIC 3.1 (e.g.
--
1.8.0
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[PATCH V5] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx
A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe
goes down. when the link goes down, Non-posted transactions issued
via the ATMU requiring completion result in an instruction stall.
At the same time a machine-check exception is generated to the core
to allow further processing by the handler. We implements the handler
which skips the instruction caused the stall.
This patch depends on patch:
powerpc/85xx: Add platform_device declaration to fsl_pci.h
Signed-off-by: Zhao Chenhui b35...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Liu Shuo soniccat@gmail.com
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
Changes for V4:
* Fill rd with all-Fs if the skipped instruction is load and emulate the
instruction.
* Let KVM/QEMU deal with the exception if the machine check comes from KVM.
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 2 +-
arch/powerpc/kernel/traps.c | 3 +
arch/powerpc/sysdev/fsl_pci.c | 121 ++
arch/powerpc/sysdev/fsl_pci.h | 6 ++
4 files changed, 131 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index dcd8819..f1bde90 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -66,7 +66,7 @@ _GLOBAL(__setup_cpu_e500v2)
bl __e500_icache_setup
bl __e500_dcache_setup
bl __setup_e500_ivors
-#ifdef CONFIG_FSL_RIO
+#if defined(CONFIG_FSL_RIO) || defined(CONFIG_FSL_PCI)
/* Ensure that RFXE is set */
mfspr r3,SPRN_HID1
orisr3,r3,HID1_RFXE@h
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index a008cf5..dd275a4 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -59,6 +59,7 @@
#include asm/fadump.h
#include asm/switch_to.h
#include asm/debug.h
+#include sysdev/fsl_pci.h
#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
int (*__debugger)(struct pt_regs *regs) __read_mostly;
@@ -556,6 +557,8 @@ int machine_check_e500(struct pt_regs *regs)
if (reason MCSR_BUS_RBERR) {
if (fsl_rio_mcheck_exception(regs))
return 1;
+ if (fsl_pci_mcheck_exception(regs))
+ return 1;
}
printk(Machine check in kernel mode.\n);
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 682084d..48326cd 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -26,11 +26,14 @@
#include linux/memblock.h
#include linux/log2.h
#include linux/slab.h
+#include linux/uaccess.h
#include asm/io.h
#include asm/prom.h
#include asm/pci-bridge.h
+#include asm/ppc-pci.h
#include asm/machdep.h
+#include asm/disassemble.h
#include sysdev/fsl_soc.h
#include sysdev/fsl_pci.h
@@ -826,6 +829,124 @@ u64 fsl_pci_immrbar_base(struct pci_controller *hose)
return 0;
}
+#ifdef CONFIG_E500
+
+#define OP_LWZ 32
+#define OP_LWZU 33
+#define OP_LBZ 34
+#define OP_LBZU 35
+#define OP_LHZ 40
+#define OP_LHZU 41
+#define OP_LHA 42
+#define OP_LHAU 43
+
+static int mcheck_handle_load(struct pt_regs *regs, u32 inst)
+{
+ unsigned int rd, ra, d;
+
+ rd = get_rt(inst);
+ ra = get_ra(inst);
+ d = get_d(inst);
+
+ switch (get_op(inst)) {
+ case OP_LWZ:
+ regs-gpr[rd] = 0x;
+ break;
+
+ case OP_LWZU:
+ regs-gpr[rd] = 0x;
+ regs-gpr[ra] += (s16)d;
+ break;
+
+ case OP_LBZ:
+ regs-gpr[rd] = 0xff;
+ break;
+
+ case OP_LBZU:
+ regs-gpr[rd] = 0xff;
+ regs-gpr[ra] += (s16)d;
+ break;
+
+ case OP_LHZ:
+ regs-gpr[rd] = 0x;
+ break;
+
+ case OP_LHZU:
+ regs-gpr[rd] = 0x;
+ regs-gpr[ra] += (s16)d;
+ break;
+
+ case OP_LHA:
+ regs-gpr[rd] = 0x;
+ break;
+
+ case OP_LHAU:
+ regs-gpr[rd] = 0x;
+ regs-gpr[ra] += (s16)d;
+ break;
+
+ default:
+ return 0;
+ }
+
+ return 1;
+}
+
+static int is_in_pci_mem_space(phys_addr_t addr)
+{
+ struct pci_controller *hose;
+ struct resource *res;
+ int i;
+
+ list_for_each_entry(hose, hose_list, list_node) {
+ if (!early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP))
+ continue;
+
+ for (i = 0; i 3; i++) {
+ res = hose-mem_resources[i];
+ if ((res-flags IORESOURCE_MEM)
+ addr = res-start addr = res-end)
+ return 1;
+ }
+ }
+ return 0;
+}
+
+int fsl_pci_mcheck_exception
[PATCH V4] powerpc/MPIC: Add get_version API both for internal and external use
MPIC version is useful information for both mpic_alloc() and mpic_init().
The patch provide an API to get MPIC version for reusing the code.
Also, some other IP block may need MPIC version for their own use.
The API for external use is also provided.
Signed-off-by: Jia Hongtao hongtao@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
Changes for V4:
* change the name of function from mpic_get_version() to
fsl_mpic_get_version().
Changes for V3:
* change the name of function from mpic_primary_get_version() to
fsl_mpic_primary_get_version().
* return 0 if mpic_primary is null.
Changes for V2:
* Using mpic_get_version() to implement mpic_primary_get_version()
arch/powerpc/include/asm/mpic.h | 3 +++
arch/powerpc/sysdev/mpic.c | 29 ++---
2 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index c0f9ef9..ea6bf72 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -393,6 +393,9 @@ struct mpic
#defineMPIC_REGSET_STANDARDMPIC_REGSET(0) /* Original
MPIC */
#defineMPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109
PIC */
+/* Get the version of primary MPIC */
+extern u32 fsl_mpic_primary_get_version(void);
+
/* Allocate the controller structure and setup the linux irq descs
* for the range if interrupts passed in. No HW initialization is
* actually performed.
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index d30e6a6..48c8fae 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1165,10 +1165,30 @@ static struct irq_domain_ops mpic_host_ops = {
.xlate = mpic_host_xlate,
};
+static u32 fsl_mpic_get_version(struct mpic *mpic)
+{
+ u32 brr1;
+
+ brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
+ MPIC_FSL_BRR1);
+
+ return brr1 MPIC_FSL_BRR1_VER;
+}
+
/*
* Exported functions
*/
+u32 fsl_mpic_primary_get_version(void)
+{
+ struct mpic *mpic = mpic_primary;
+
+ if (mpic)
+ return fsl_mpic_get_version(mpic);
+
+ return 0;
+}
+
struct mpic * __init mpic_alloc(struct device_node *node,
phys_addr_t phys_addr,
unsigned int flags,
@@ -1315,7 +1335,6 @@ struct mpic * __init mpic_alloc(struct device_node *node,
mpic_map(mpic, mpic-paddr, mpic-tmregs, MPIC_INFO(TIMER_BASE),
0x1000);
if (mpic-flags MPIC_FSL) {
- u32 brr1;
int ret;
/*
@@ -1326,9 +1345,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
mpic_map(mpic, mpic-paddr, mpic-thiscpuregs,
MPIC_CPU_THISBASE, 0x1000);
- brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
- MPIC_FSL_BRR1);
- fsl_version = brr1 MPIC_FSL_BRR1_VER;
+ fsl_version = fsl_mpic_get_version(mpic);
/* Error interrupt mask register (EIMR) is required for
* handling individual device error interrupts. EIMR
@@ -1518,9 +1535,7 @@ void __init mpic_init(struct mpic *mpic)
mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
if (mpic-flags MPIC_FSL) {
- u32 brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
- MPIC_FSL_BRR1);
- u32 version = brr1 MPIC_FSL_BRR1_VER;
+ u32 version = fsl_mpic_get_version(mpic);
/*
* Timer group B is present at the latest in MPIC 3.1 (e.g.
--
1.8.0
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RE: [PATCH V2] powerpc/MPIC: Add get_version API both for internal and external use
-Original Message-
From: Wood Scott-B07421
Sent: Saturday, March 30, 2013 5:55 AM
To: Wood Scott-B07421
Cc: Jia Hongtao-B38951; linuxppc-dev@lists.ozlabs.org;
ga...@kernel.crashing.org; Wood Scott-B07421; Li Yang-R58472; Jia
Hongtao-B38951
Subject: Re: [PATCH V2] powerpc/MPIC: Add get_version API both for
internal and external use
On 03/29/2013 04:51:59 PM, Scott Wood wrote:
On 03/26/2013 12:28:10 AM, Jia Hongtao wrote:
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index d30e6a6..c893a4b 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1165,10 +1165,27 @@ static struct irq_domain_ops mpic_host_ops =
{
.xlate = mpic_host_xlate,
};
+static u32 mpic_get_version(struct mpic *mpic) {
+ u32 brr1;
+
+ brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
+ MPIC_FSL_BRR1);
+
+ return brr1 MPIC_FSL_BRR1_VER;
+}
+
/*
* Exported functions
*/
+u32 mpic_primary_get_version(void)
+{
+ struct mpic *mpic = mpic_primary;
+
+ return mpic_get_version(mpic);
+}
So this just crashes if there is no mpic_primary or it's a non-FSL
MPIC?
...and since it's specifically checking for the FSL version, fsl
should be in the name.
-Scott
Right, I will update it with next version.
- Hongtao.
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RE: [PATCH 2/2] powerpc/85xx: workaround for chips with MSI hardware errata
-Original Message-
From: Wood Scott-B07421
Sent: Saturday, March 30, 2013 5:55 AM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org; Wood Scott-
B07421; Li Yang-R58472; Jia Hongtao-B38951
Subject: Re: [PATCH 2/2] powerpc/85xx: workaround for chips with MSI
hardware errata
On 03/25/2013 10:28:47 PM, Jia Hongtao wrote:
The MPIC version 2.0 has a MSI errata (errata PIC1 of mpc8544), It
causes that neither MSI nor MSI-X can work fine. This is a workaround
to allow MSI-X to function properly.
Signed-off-by: Liu Shuo soniccat@gmail.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
arch/powerpc/sysdev/fsl_msi.c | 47
---
1 file changed, 44 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_msi.c
b/arch/powerpc/sysdev/fsl_msi.c index 178c994..d2f8040 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -28,6 +28,8 @@
#include fsl_msi.h
#include fsl_pci.h
+#define MSI_HW_ERRATA_ENDIAN 0x0010
It seems Kumar like put this just in fsl_msi.c.
Here is the comments from Kumar few days ago:
Is there any reason to put this in fsl_msi.h rather than just in
fsl_msi.c itself?
I think the all the #defines should be together.
Ether all in .h or all in .c.
In this case I prefer your idea.
This should probably be kept in the same place as the other
msi-features definitions (e.g. FSL_PIC_IP_*).
+/* MPIC version 2.0 has erratum PIC1 */ static int
+mpic_has_errata(void) {
+ if (mpic_primary_get_version() == 0x0200)
+ return 1;
+
+ return 0;
+}
mpic_has_erratum_pic1()
You are right.
Good advice.
+ if ((features-fsl_pic_ip FSL_PIC_IP_MASK) ==
FSL_PIC_IP_MPIC) {
+ rc = mpic_has_errata();
+ if (rc 0) {
+ msi-feature |= MSI_HW_ERRATA_ENDIAN;
+ } else if (rc 0) {
+ err = rc;
+ goto error_out;
+ }
When would mpic_has_errata() ever return a negative value (maybe
mpic_primary_get_version could fail, but you don't allow for that in the
interface)?
If you're not going to add a way for errors to be returned back, just
do:
if (mpic_has_erratum_pic1())
msi-feature |= MSI_HW_ERRATA_ENDIAN;
-Scott
I will update the mpic_primary_get_version() and it will return 0 if failed.
Based on the new mpic_primary_get_version() I agree with this.
Thanks.
-Hongtao.
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RE: [PATCH V4] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx
-Original Message-
From: Wood Scott-B07421
Sent: Saturday, March 30, 2013 12:34 AM
To: Jia Hongtao-B38951
Cc: Wood Scott-B07421; David Laight; linuxppc-dev@lists.ozlabs.org;
Stuart Yoder
Subject: Re: [PATCH V4] powerpc/85xx: Add machine check handler to fix
PCIe erratum on mpc85xx
On 03/29/2013 03:03:51 AM, Jia Hongtao-B38951 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Saturday, March 16, 2013 12:35 AM
To: Jia Hongtao-B38951
Cc: Wood Scott-B07421; David Laight; linuxppc-dev@lists.ozlabs.org;
Stuart Yoder
Subject: Re: [PATCH V4] powerpc/85xx: Add machine check handler to
fix
PCIe erratum on mpc85xx
On 03/14/2013 09:47:58 PM, Jia Hongtao-B38951 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, March 14, 2013 12:38 AM
To: David Laight
Cc: Jia Hongtao-B38951; Wood Scott-B07421;
linuxppc-dev@lists.ozlabs.org;
Stuart Yoder
Subject: Re: [PATCH V4] powerpc/85xx: Add machine check handler
to
fix
PCIe erratum on mpc85xx
On 03/13/2013 04:40:40 AM, David Laight wrote:
Hmm, seems there's no probe_user_address() -- for userspace
we
basically want the same thing minus the KERNEL_DS. See
arch/powerpc/perf/callchain.c for an example.
Isn't that just copy_from_user() ?
Plus pagefault_disable/enable().
-Scott
pagefault_disable() is identical to preempt_disable(). So I think
this
could not avoid other cpu to swap out the instruction we want to
read
back.
probe_kernel_address() also have the same issue.
That's not the point -- the point is to let the page fault handler
know
that it should go directly to bad_page_fault(). Do not pass
handle_mm_fault(). Do not collect a page from disk.
Granted, we're already in atomic context which will have that effect
due to being in the machine check handler, but it's better to be
explicit about it and not depend on how pagefault_diasble() is
implemented.
-Scott
Based on the comments I updated the machine check handler.
Changes from last version:
* Check MSR_GS state
* Check if the instruction is LD
* Handle the user space issue
The updated machine check handler is as following:
int fsl_pci_mcheck_exception(struct pt_regs *regs) {
unsigned int op, rd;
u32 inst;
int ret;
phys_addr_t addr = 0;
/* Let KVM/QEMU deal with the exception */
if (regs-msr MSR_GS)
return 0;
#ifdef CONFIG_PHYS_64BIT
addr = mfspr(SPRN_MCARU);
addr = 32;
#endif
addr += mfspr(SPRN_MCAR);
if (is_in_pci_mem_space(addr)) {
if (user_mode(regs)) {
pagefault_disable();
ret = copy_from_user((inst), (u32 __user
*)regs-nip, sizeof(inst));
pagefault_enable();
You could use get_user() instead of copy_from_user().
Got it.
} else {
ret = probe_kernel_address(regs-nip, inst);
}
op = get_op(inst);
/* Check if the instruction is LD */
if (!ret (op == 111010)) {
rd = get_rt(inst);
regs-gpr[rd] = 0x;
}
regs-nip += 4;
return 1;
}
return 0;
}
BTW, I'm still not sure how to deal with LD instruction with update.
You would need to do the update yourself. Or just say that's a case you
don't handle, and return 0.
Again, please check for the size of the load operation.
-Scott
For informing error to the process that hold the stall instruction
we need to do:
1. Verify the instruction is load.
2. Fill the rd register with ~0UL.
3. Deal with the load instruction with update.
Here is the problems:
1. So many load instructions to handle. There are dozens of load instructions
and most of them with different op code. Like:
lbz: 1 0 0 0 1 0
lhz: 1 0 1 0 0 0
lwz: 1 0 0 0 0 0
ld : 1 1 1 0 1 0
...
Is there any available API for verifying the load instruction?
2. For different size of load operation could we just fill the rd register with
~0UL?
3. A load instruction with update could not just verified by op code. I'd like
to leave it along. I think we could not fix but just inform the error by
filling the rd with ~0UL. Could you explain why should we care about the
update?
The main problem is how to verifying the load instruction. I wonder if there is
an easy way to do it. If not the code here will be so complicated.
Thanks.
-Hongtao.
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[PATCH V3 1/2] powerpc/MPIC: Add get_version API both for internal and external use
MPIC version is useful information for both mpic_alloc() and mpic_init().
The patch provide an API to get MPIC version for reusing the code.
Also, some other IP block may need MPIC version for their own use.
The API for external use is also provided.
Signed-off-by: Jia Hongtao hongtao@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
Changes for V3:
* change the name of function from mpic_primary_get_version() to
fsl_mpic_primary_get_version().
* return 0 if mpic_primary is null.
arch/powerpc/include/asm/mpic.h | 3 +++
arch/powerpc/sysdev/mpic.c | 29 ++---
2 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index c0f9ef9..ea6bf72 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -393,6 +393,9 @@ struct mpic
#defineMPIC_REGSET_STANDARDMPIC_REGSET(0) /* Original
MPIC */
#defineMPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109
PIC */
+/* Get the version of primary MPIC */
+extern u32 fsl_mpic_primary_get_version(void);
+
/* Allocate the controller structure and setup the linux irq descs
* for the range if interrupts passed in. No HW initialization is
* actually performed.
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index d30e6a6..e793337 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1165,10 +1165,30 @@ static struct irq_domain_ops mpic_host_ops = {
.xlate = mpic_host_xlate,
};
+static u32 mpic_get_version(struct mpic *mpic)
+{
+ u32 brr1;
+
+ brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
+ MPIC_FSL_BRR1);
+
+ return brr1 MPIC_FSL_BRR1_VER;
+}
+
/*
* Exported functions
*/
+u32 fsl_mpic_primary_get_version(void)
+{
+ struct mpic *mpic = mpic_primary;
+
+ if (mpic)
+ return mpic_get_version(mpic);
+
+ return 0;
+}
+
struct mpic * __init mpic_alloc(struct device_node *node,
phys_addr_t phys_addr,
unsigned int flags,
@@ -1315,7 +1335,6 @@ struct mpic * __init mpic_alloc(struct device_node *node,
mpic_map(mpic, mpic-paddr, mpic-tmregs, MPIC_INFO(TIMER_BASE),
0x1000);
if (mpic-flags MPIC_FSL) {
- u32 brr1;
int ret;
/*
@@ -1326,9 +1345,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
mpic_map(mpic, mpic-paddr, mpic-thiscpuregs,
MPIC_CPU_THISBASE, 0x1000);
- brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
- MPIC_FSL_BRR1);
- fsl_version = brr1 MPIC_FSL_BRR1_VER;
+ fsl_version = mpic_get_version(mpic);
/* Error interrupt mask register (EIMR) is required for
* handling individual device error interrupts. EIMR
@@ -1518,9 +1535,7 @@ void __init mpic_init(struct mpic *mpic)
mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
if (mpic-flags MPIC_FSL) {
- u32 brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
- MPIC_FSL_BRR1);
- u32 version = brr1 MPIC_FSL_BRR1_VER;
+ u32 version = mpic_get_version(mpic);
/*
* Timer group B is present at the latest in MPIC 3.1 (e.g.
--
1.8.0
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[PATCH V2 2/2] powerpc/85xx: workaround for chips with MSI hardware errata
The MPIC version 2.0 has a MSI errata (errata PIC1 of mpc8544), It causes
that neither MSI nor MSI-X can work fine. This is a workaround to allow
MSI-X to function properly.
Signed-off-by: Liu Shuo soniccat@gmail.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
Changes for V2:
* change the name of function mpic_has_errata() to mpic_has_erratum_pic1().
* move MSI_HW_ERRATA_ENDIAN define to fsl_msi.h with all other defines.
arch/powerpc/sysdev/fsl_msi.c | 40 +---
arch/powerpc/sysdev/fsl_msi.h | 2 ++
2 files changed, 39 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index 178c994..ca1157a 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -98,8 +98,18 @@ static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type)
{
- if (type == PCI_CAP_ID_MSIX)
- pr_debug(fslmsi: MSI-X untested, trying anyway.\n);
+ struct fsl_msi *msi;
+
+ if (type == PCI_CAP_ID_MSI) {
+ /*
+* MPIC version 2.0 has erratum PIC1. For now MSI
+* could not work. So check to prevent MSI from
+* being used on the board with this erratum.
+*/
+ list_for_each_entry(msi, msi_head, list)
+ if (msi-feature MSI_HW_ERRATA_ENDIAN)
+ return -EINVAL;
+ }
return 0;
}
@@ -142,7 +152,17 @@ static void fsl_compose_msi_msg(struct pci_dev *pdev, int
hwirq,
msg-address_lo = lower_32_bits(address);
msg-address_hi = upper_32_bits(address);
- msg-data = hwirq;
+ /*
+* MPIC version 2.0 has erratum PIC1. It causes
+* that neither MSI nor MSI-X can work fine.
+* This is a workaround to allow MSI-X to function
+* properly. It only works for MSI-X, we prevent
+* MSI on buggy chips in fsl_msi_check_device().
+*/
+ if (msi_data-feature MSI_HW_ERRATA_ENDIAN)
+ msg-data = __swab32(hwirq);
+ else
+ msg-data = hwirq;
pr_debug(%s: allocated srs: %d, ibs: %d\n,
__func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG);
@@ -361,6 +381,15 @@ static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct
platform_device *dev,
return 0;
}
+/* MPIC version 2.0 has erratum PIC1 */
+static int mpic_has_erratum_pic1(void)
+{
+ if (fsl_mpic_primary_get_version() == 0x0200)
+ return 1;
+
+ return 0;
+}
+
static const struct of_device_id fsl_of_msi_ids[];
static int fsl_of_msi_probe(struct platform_device *dev)
{
@@ -423,6 +452,11 @@ static int fsl_of_msi_probe(struct platform_device *dev)
msi-feature = features-fsl_pic_ip;
+ if ((features-fsl_pic_ip FSL_PIC_IP_MASK) == FSL_PIC_IP_MPIC) {
+ if (mpic_has_erratum_pic1())
+ msi-feature |= MSI_HW_ERRATA_ENDIAN;
+ }
+
/*
* Remember the phandle, so that we can match with any PCI nodes
* that have an fsl,msi property.
diff --git a/arch/powerpc/sysdev/fsl_msi.h b/arch/powerpc/sysdev/fsl_msi.h
index 8225f86..7389e8e 100644
--- a/arch/powerpc/sysdev/fsl_msi.h
+++ b/arch/powerpc/sysdev/fsl_msi.h
@@ -25,6 +25,8 @@
#define FSL_PIC_IP_IPIC 0x0002
#define FSL_PIC_IP_VMPIC 0x0003
+#define MSI_HW_ERRATA_ENDIAN 0x0010
+
struct fsl_msi {
struct irq_domain *irqhost;
--
1.8.0
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RE: [PATCH V2] powerpc/MPIC: Add get_version API both for internal and external use
Hi Kumar and Scott,
Any comments on these two patches?
Thanks.
-Hongtao.
-Original Message-
From: Jia Hongtao-B38951
Sent: Tuesday, March 26, 2013 1:28 PM
To: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org
Cc: Wood Scott-B07421; Li Yang-R58472; Jia Hongtao-B38951
Subject: [PATCH V2] powerpc/MPIC: Add get_version API both for internal
and external use
MPIC version is useful information for both mpic_alloc() and mpic_init().
The patch provide an API to get MPIC version for reusing the code.
Also, some other IP block may need MPIC version for their own use.
The API for external use is also provided.
Signed-off-by: Jia Hongtao hongtao@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
Changes for V2:
* Using mpic_get_version() to implement mpic_primary_get_version()
arch/powerpc/include/asm/mpic.h | 3 +++
arch/powerpc/sysdev/mpic.c | 26 +++---
2 files changed, 22 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/include/asm/mpic.h
b/arch/powerpc/include/asm/mpic.h index c0f9ef9..7d1222d 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -393,6 +393,9 @@ struct mpic
#define MPIC_REGSET_STANDARDMPIC_REGSET(0) /* Original
MPIC */
#define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109
PIC */
+/* Get the version of primary MPIC */
+extern u32 mpic_primary_get_version(void);
+
/* Allocate the controller structure and setup the linux irq descs
* for the range if interrupts passed in. No HW initialization is
* actually performed.
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index d30e6a6..c893a4b 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1165,10 +1165,27 @@ static struct irq_domain_ops mpic_host_ops = {
.xlate = mpic_host_xlate,
};
+static u32 mpic_get_version(struct mpic *mpic) {
+ u32 brr1;
+
+ brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
+ MPIC_FSL_BRR1);
+
+ return brr1 MPIC_FSL_BRR1_VER;
+}
+
/*
* Exported functions
*/
+u32 mpic_primary_get_version(void)
+{
+ struct mpic *mpic = mpic_primary;
+
+ return mpic_get_version(mpic);
+}
+
struct mpic * __init mpic_alloc(struct device_node *node,
phys_addr_t phys_addr,
unsigned int flags,
@@ -1315,7 +1332,6 @@ struct mpic * __init mpic_alloc(struct device_node
*node,
mpic_map(mpic, mpic-paddr, mpic-tmregs, MPIC_INFO(TIMER_BASE),
0x1000);
if (mpic-flags MPIC_FSL) {
- u32 brr1;
int ret;
/*
@@ -1326,9 +1342,7 @@ struct mpic * __init mpic_alloc(struct device_node
*node,
mpic_map(mpic, mpic-paddr, mpic-thiscpuregs,
MPIC_CPU_THISBASE, 0x1000);
- brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
- MPIC_FSL_BRR1);
- fsl_version = brr1 MPIC_FSL_BRR1_VER;
+ fsl_version = mpic_get_version(mpic);
/* Error interrupt mask register (EIMR) is required for
* handling individual device error interrupts. EIMR @@ -
1518,9 +1532,7 @@ void __init mpic_init(struct mpic *mpic)
mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
if (mpic-flags MPIC_FSL) {
- u32 brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
- MPIC_FSL_BRR1);
- u32 version = brr1 MPIC_FSL_BRR1_VER;
+ u32 version = mpic_get_version(mpic);
/*
* Timer group B is present at the latest in MPIC 3.1 (e.g.
--
1.8.0
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RE: [PATCH V4] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx
-Original Message-
From: Wood Scott-B07421
Sent: Saturday, March 16, 2013 12:35 AM
To: Jia Hongtao-B38951
Cc: Wood Scott-B07421; David Laight; linuxppc-dev@lists.ozlabs.org;
Stuart Yoder
Subject: Re: [PATCH V4] powerpc/85xx: Add machine check handler to fix
PCIe erratum on mpc85xx
On 03/14/2013 09:47:58 PM, Jia Hongtao-B38951 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, March 14, 2013 12:38 AM
To: David Laight
Cc: Jia Hongtao-B38951; Wood Scott-B07421;
linuxppc-dev@lists.ozlabs.org;
Stuart Yoder
Subject: Re: [PATCH V4] powerpc/85xx: Add machine check handler to
fix
PCIe erratum on mpc85xx
On 03/13/2013 04:40:40 AM, David Laight wrote:
Hmm, seems there's no probe_user_address() -- for userspace we
basically want the same thing minus the KERNEL_DS. See
arch/powerpc/perf/callchain.c for an example.
Isn't that just copy_from_user() ?
Plus pagefault_disable/enable().
-Scott
pagefault_disable() is identical to preempt_disable(). So I think this
could not avoid other cpu to swap out the instruction we want to read
back.
probe_kernel_address() also have the same issue.
That's not the point -- the point is to let the page fault handler know
that it should go directly to bad_page_fault(). Do not pass
handle_mm_fault(). Do not collect a page from disk.
Granted, we're already in atomic context which will have that effect
due to being in the machine check handler, but it's better to be
explicit about it and not depend on how pagefault_diasble() is
implemented.
-Scott
Based on the comments I updated the machine check handler.
Changes from last version:
* Check MSR_GS state
* Check if the instruction is LD
* Handle the user space issue
The updated machine check handler is as following:
int fsl_pci_mcheck_exception(struct pt_regs *regs)
{
unsigned int op, rd;
u32 inst;
int ret;
phys_addr_t addr = 0;
/* Let KVM/QEMU deal with the exception */
if (regs-msr MSR_GS)
return 0;
#ifdef CONFIG_PHYS_64BIT
addr = mfspr(SPRN_MCARU);
addr = 32;
#endif
addr += mfspr(SPRN_MCAR);
if (is_in_pci_mem_space(addr)) {
if (user_mode(regs)) {
pagefault_disable();
ret = copy_from_user((inst), (u32 __user *)regs-nip,
sizeof(inst));
pagefault_enable();
} else {
ret = probe_kernel_address(regs-nip, inst);
}
op = get_op(inst);
/* Check if the instruction is LD */
if (!ret (op == 111010)) {
rd = get_rt(inst);
regs-gpr[rd] = 0x;
}
regs-nip += 4;
return 1;
}
return 0;
}
BTW, I'm still not sure how to deal with LD instruction with update.
Any comments and suggestions are welcomed.
Thanks.
-Hongtao.
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[PATCH V2] powerpc/MPIC: Add get_version API both for internal and external use
MPIC version is useful information for both mpic_alloc() and mpic_init().
The patch provide an API to get MPIC version for reusing the code.
Also, some other IP block may need MPIC version for their own use.
The API for external use is also provided.
Signed-off-by: Jia Hongtao hongtao@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
Changes for V2:
* Using mpic_get_version() to implement mpic_primary_get_version()
arch/powerpc/include/asm/mpic.h | 3 +++
arch/powerpc/sysdev/mpic.c | 26 +++---
2 files changed, 22 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index c0f9ef9..7d1222d 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -393,6 +393,9 @@ struct mpic
#defineMPIC_REGSET_STANDARDMPIC_REGSET(0) /* Original
MPIC */
#defineMPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109
PIC */
+/* Get the version of primary MPIC */
+extern u32 mpic_primary_get_version(void);
+
/* Allocate the controller structure and setup the linux irq descs
* for the range if interrupts passed in. No HW initialization is
* actually performed.
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index d30e6a6..c893a4b 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1165,10 +1165,27 @@ static struct irq_domain_ops mpic_host_ops = {
.xlate = mpic_host_xlate,
};
+static u32 mpic_get_version(struct mpic *mpic)
+{
+ u32 brr1;
+
+ brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
+ MPIC_FSL_BRR1);
+
+ return brr1 MPIC_FSL_BRR1_VER;
+}
+
/*
* Exported functions
*/
+u32 mpic_primary_get_version(void)
+{
+ struct mpic *mpic = mpic_primary;
+
+ return mpic_get_version(mpic);
+}
+
struct mpic * __init mpic_alloc(struct device_node *node,
phys_addr_t phys_addr,
unsigned int flags,
@@ -1315,7 +1332,6 @@ struct mpic * __init mpic_alloc(struct device_node *node,
mpic_map(mpic, mpic-paddr, mpic-tmregs, MPIC_INFO(TIMER_BASE),
0x1000);
if (mpic-flags MPIC_FSL) {
- u32 brr1;
int ret;
/*
@@ -1326,9 +1342,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
mpic_map(mpic, mpic-paddr, mpic-thiscpuregs,
MPIC_CPU_THISBASE, 0x1000);
- brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
- MPIC_FSL_BRR1);
- fsl_version = brr1 MPIC_FSL_BRR1_VER;
+ fsl_version = mpic_get_version(mpic);
/* Error interrupt mask register (EIMR) is required for
* handling individual device error interrupts. EIMR
@@ -1518,9 +1532,7 @@ void __init mpic_init(struct mpic *mpic)
mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
if (mpic-flags MPIC_FSL) {
- u32 brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
- MPIC_FSL_BRR1);
- u32 version = brr1 MPIC_FSL_BRR1_VER;
+ u32 version = mpic_get_version(mpic);
/*
* Timer group B is present at the latest in MPIC 3.1 (e.g.
--
1.8.0
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[PATCH 1/2] powerpc/MPIC: Add get_version API both for internal and external use
MPIC version is useful information for both mpic_alloc() and mpic_init().
The patch provide an API to get MPIC version for reusing the code.
Also, some other IP block may need MPIC version for their own use.
The API for external use is also provided.
Signed-off-by: Jia Hongtao hongtao@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
arch/powerpc/include/asm/mpic.h | 3 +++
arch/powerpc/sysdev/mpic.c | 30 +++---
2 files changed, 26 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index c0f9ef9..95053d6 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -393,6 +393,9 @@ struct mpic
#defineMPIC_REGSET_STANDARDMPIC_REGSET(0) /* Original
MPIC */
#defineMPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109
PIC */
+/* Get the mpic version */
+extern u32 mpic_primary_get_version(void);
+
/* Allocate the controller structure and setup the linux irq descs
* for the range if interrupts passed in. No HW initialization is
* actually performed.
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index d30e6a6..d6b6fb6 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1165,10 +1165,31 @@ static struct irq_domain_ops mpic_host_ops = {
.xlate = mpic_host_xlate,
};
+static u32 mpic_get_version(struct mpic *mpic)
+{
+ u32 brr1;
+
+ brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
+ MPIC_FSL_BRR1);
+
+ return brr1 MPIC_FSL_BRR1_VER;
+}
+
/*
* Exported functions
*/
+u32 mpic_primary_get_version(void)
+{
+ u32 brr1;
+ struct mpic *mpic = mpic_primary;
+
+ brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
+ MPIC_FSL_BRR1);
+
+ return brr1 MPIC_FSL_BRR1_VER;
+}
+
struct mpic * __init mpic_alloc(struct device_node *node,
phys_addr_t phys_addr,
unsigned int flags,
@@ -1315,7 +1336,6 @@ struct mpic * __init mpic_alloc(struct device_node *node,
mpic_map(mpic, mpic-paddr, mpic-tmregs, MPIC_INFO(TIMER_BASE),
0x1000);
if (mpic-flags MPIC_FSL) {
- u32 brr1;
int ret;
/*
@@ -1326,9 +1346,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
mpic_map(mpic, mpic-paddr, mpic-thiscpuregs,
MPIC_CPU_THISBASE, 0x1000);
- brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
- MPIC_FSL_BRR1);
- fsl_version = brr1 MPIC_FSL_BRR1_VER;
+ fsl_version = mpic_get_version(mpic);
/* Error interrupt mask register (EIMR) is required for
* handling individual device error interrupts. EIMR
@@ -1518,9 +1536,7 @@ void __init mpic_init(struct mpic *mpic)
mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
if (mpic-flags MPIC_FSL) {
- u32 brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
- MPIC_FSL_BRR1);
- u32 version = brr1 MPIC_FSL_BRR1_VER;
+ u32 version = mpic_get_version(mpic);
/*
* Timer group B is present at the latest in MPIC 3.1 (e.g.
--
1.8.0
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[PATCH 2/2] powerpc/85xx: workaround for chips with MSI hardware errata
The MPIC version 2.0 has a MSI errata (errata PIC1 of mpc8544), It causes
that neither MSI nor MSI-X can work fine. This is a workaround to allow
MSI-X to function properly.
Signed-off-by: Liu Shuo soniccat@gmail.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
arch/powerpc/sysdev/fsl_msi.c | 47 ---
1 file changed, 44 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index 178c994..d2f8040 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -28,6 +28,8 @@
#include fsl_msi.h
#include fsl_pci.h
+#define MSI_HW_ERRATA_ENDIAN 0x0010
+
static LIST_HEAD(msi_head);
struct fsl_msi_feature {
@@ -98,8 +100,18 @@ static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type)
{
- if (type == PCI_CAP_ID_MSIX)
- pr_debug(fslmsi: MSI-X untested, trying anyway.\n);
+ struct fsl_msi *msi;
+
+ if (type == PCI_CAP_ID_MSI) {
+ /*
+* MPIC version 2.0 has erratum PIC1. For now MSI
+* could not work. So check to prevent MSI from
+* being used on the board with this erratum.
+*/
+ list_for_each_entry(msi, msi_head, list)
+ if (msi-feature MSI_HW_ERRATA_ENDIAN)
+ return -EINVAL;
+ }
return 0;
}
@@ -142,7 +154,17 @@ static void fsl_compose_msi_msg(struct pci_dev *pdev, int
hwirq,
msg-address_lo = lower_32_bits(address);
msg-address_hi = upper_32_bits(address);
- msg-data = hwirq;
+ /*
+* MPIC version 2.0 has erratum PIC1. It causes
+* that neither MSI nor MSI-X can work fine.
+* This is a workaround to allow MSI-X to function
+* properly. It only works for MSI-X, we prevent
+* MSI on buggy chips in fsl_msi_check_device().
+*/
+ if (msi_data-feature MSI_HW_ERRATA_ENDIAN)
+ msg-data = __swab32(hwirq);
+ else
+ msg-data = hwirq;
pr_debug(%s: allocated srs: %d, ibs: %d\n,
__func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG);
@@ -361,6 +383,15 @@ static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct
platform_device *dev,
return 0;
}
+/* MPIC version 2.0 has erratum PIC1 */
+static int mpic_has_errata(void)
+{
+ if (mpic_primary_get_version() == 0x0200)
+ return 1;
+
+ return 0;
+}
+
static const struct of_device_id fsl_of_msi_ids[];
static int fsl_of_msi_probe(struct platform_device *dev)
{
@@ -423,6 +454,16 @@ static int fsl_of_msi_probe(struct platform_device *dev)
msi-feature = features-fsl_pic_ip;
+ if ((features-fsl_pic_ip FSL_PIC_IP_MASK) == FSL_PIC_IP_MPIC) {
+ rc = mpic_has_errata();
+ if (rc 0) {
+ msi-feature |= MSI_HW_ERRATA_ENDIAN;
+ } else if (rc 0) {
+ err = rc;
+ goto error_out;
+ }
+ }
+
/*
* Remember the phandle, so that we can match with any PCI nodes
* that have an fsl,msi property.
--
1.8.0
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RE: [PATCH 1/2] powerpc/MPIC: Add get_version API both for internal and external use
-Original Message-
From: Michael Ellerman [mailto:mich...@ellerman.id.au]
Sent: Tuesday, March 26, 2013 12:14 PM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org; Wood Scott-
B07421
Subject: Re: [PATCH 1/2] powerpc/MPIC: Add get_version API both for
internal and external use
On Tue, Mar 26, 2013 at 11:28:46AM +0800, Jia Hongtao wrote:
MPIC version is useful information for both mpic_alloc() and
mpic_init().
The patch provide an API to get MPIC version for reusing the code.
Also, some other IP block may need MPIC version for their own use.
The API for external use is also provided.
Signed-off-by: Jia Hongtao hongtao@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
arch/powerpc/include/asm/mpic.h | 3 +++
arch/powerpc/sysdev/mpic.c | 30 +++---
2 files changed, 26 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/include/asm/mpic.h
b/arch/powerpc/include/asm/mpic.h index c0f9ef9..95053d6 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -393,6 +393,9 @@ struct mpic
#defineMPIC_REGSET_STANDARDMPIC_REGSET(0) /* Original
MPIC */
#defineMPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109
PIC */
+/* Get the mpic version */
+extern u32 mpic_primary_get_version(void);
+
/* Allocate the controller structure and setup the linux irq descs
* for the range if interrupts passed in. No HW initialization is
* actually performed.
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index d30e6a6..d6b6fb6 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1165,10 +1165,31 @@ static struct irq_domain_ops mpic_host_ops = {
.xlate = mpic_host_xlate,
};
+static u32 mpic_get_version(struct mpic *mpic) {
+ u32 brr1;
+
+ brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
+ MPIC_FSL_BRR1);
+
+ return brr1 MPIC_FSL_BRR1_VER;
+}
+
/*
* Exported functions
*/
+u32 mpic_primary_get_version(void)
+{
+ u32 brr1;
+ struct mpic *mpic = mpic_primary;
+
+ brr1 = _mpic_read(mpic-reg_type, mpic-thiscpuregs,
+ MPIC_FSL_BRR1);
+
+ return brr1 MPIC_FSL_BRR1_VER;
+}
Why doesn't mpic_primary_get_version() call mpic_get_version() ?
cheers
Good idea.
Thanks.
-Hongtao.
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RE: [PATCH V2] powerpc/85xx: workaround for chips with MSI hardware errata
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, March 20, 2013 12:32 AM
To: Jia Hongtao-B38951
Cc: Kumar Gala; linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421;
mich...@ellerman.id.au; Li Yang-R58472
Subject: Re: [PATCH V2] powerpc/85xx: workaround for chips with MSI
hardware errata
;On 03/19/2013 03:03:13 AM, Jia Hongtao-B38951 wrote:
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Friday, March 15, 2013 11:53 PM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421;
mich...@ellerman.id.au; Li Yang-R58472
Subject: Re: [PATCH V2] powerpc/85xx: workaround for chips with MSI
hardware errata
On Mar 14, 2013, at 9:00 PM, Jia Hongtao-B38951 wrote:
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Friday, March 15, 2013 4:05 AM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421;
mich...@ellerman.id.au; Li Yang-R58472; Jia Hongtao-B38951
Subject: Re: [PATCH V2] powerpc/85xx: workaround for chips with
MSI
hardware errata
On Mar 14, 2013, at 5:35 AM, Jia Hongtao wrote:
The MPIC version 2.0 has a MSI errata (errata PIC1 of mpc8544),
It
causes that neither MSI nor MSI-X can work fine. This is a
workaround to allow MSI-X to function properly.
Signed-off-by: Liu Shuo soniccat@gmail.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
Changes for V2:
- Address almost all the comments from Michael Ellerman for V1.
Here is the link:
http://patchwork.ozlabs.org/patch/226833/
arch/powerpc/sysdev/fsl_msi.c | 65
+--
arch/powerpc/sysdev/fsl_msi.h | 2 ++
2 files changed, 64 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_msi.c
b/arch/powerpc/sysdev/fsl_msi.c index 178c994..54cb83e 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -98,8 +98,18 @@ static int fsl_msi_init_allocator(struct
fsl_msi
*msi_data)
static int fsl_msi_check_device(struct pci_dev *pdev, int nvec,
int
type) {
- if (type == PCI_CAP_ID_MSIX)
- pr_debug(fslmsi: MSI-X untested, trying
anyway.\n);
+ struct fsl_msi *msi;
+
+ if (type == PCI_CAP_ID_MSI) {
+ /*
+ * MPIC version 2.0 has erratum PIC1. For now
MSI
+ * could not work. So check to prevent MSI from
+ * being used on the board with this erratum.
+ */
+ list_for_each_entry(msi, msi_head, list)
+ if (msi-feature MSI_HW_ERRATA_ENDIAN)
+ return -EINVAL;
+ }
return 0;
}
@@ -142,7 +152,17 @@ static void fsl_compose_msi_msg(struct
pci_dev
*pdev, int hwirq,
msg-address_lo = lower_32_bits(address);
msg-address_hi = upper_32_bits(address);
- msg-data = hwirq;
+ /*
+ * MPIC version 2.0 has erratum PIC1. It causes
+ * that neither MSI nor MSI-X can work fine.
+ * This is a workaround to allow MSI-X to function
+ * properly. It only works for MSI-X, we prevent
+ * MSI on buggy chips in fsl_msi_check_device().
+ */
+ if (msi_data-feature MSI_HW_ERRATA_ENDIAN)
+ msg-data = __swab32(hwirq);
+ else
+ msg-data = hwirq;
pr_debug(%s: allocated srs: %d, ibs: %d\n,
__func__, hwirq / IRQS_PER_MSI_REG, hwirq %
IRQS_PER_MSI_REG);
@@
-361,6 +381,35 @@ static int fsl_msi_setup_hwirq(struct fsl_msi
*msi,
struct platform_device *dev,
return 0;
}
+/* MPIC version 2.0 has erratum PIC1 */ static int
+mpic_has_errata(struct platform_device *dev) {
+ struct device_node *mpic_node;
+
+ mpic_node = of_irq_find_parent(dev-dev.of_node);
+ if (mpic_node) {
+ u32 *reg_base, brr1 = 0;
+ /* Get the PIC reg base */
+ reg_base = of_iomap(mpic_node, 0);
+ of_node_put(mpic_node);
+ if (!reg_base) {
+ dev_err(dev-dev, ioremap problem
failed.\n);
+ return -EIO;
+ }
+
+ /* Get the mpic version from block revision
register 1 */
+ brr1 = in_be32(reg_base + MPIC_FSL_BRR1);
+ iounmap(reg_base);
+ if ((brr1 MPIC_FSL_BRR1_VER) == 0x0200)
+ return 1;
+ } else {
+ dev_err(dev-dev, MSI can't find his parent
mpic node.\n);
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
static
RE: [PATCH V2] powerpc/85xx: workaround for chips with MSI hardware errata
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Friday, March 15, 2013 11:53 PM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421;
mich...@ellerman.id.au; Li Yang-R58472
Subject: Re: [PATCH V2] powerpc/85xx: workaround for chips with MSI
hardware errata
On Mar 14, 2013, at 9:00 PM, Jia Hongtao-B38951 wrote:
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Friday, March 15, 2013 4:05 AM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421;
mich...@ellerman.id.au; Li Yang-R58472; Jia Hongtao-B38951
Subject: Re: [PATCH V2] powerpc/85xx: workaround for chips with MSI
hardware errata
On Mar 14, 2013, at 5:35 AM, Jia Hongtao wrote:
The MPIC version 2.0 has a MSI errata (errata PIC1 of mpc8544), It
causes that neither MSI nor MSI-X can work fine. This is a
workaround to allow MSI-X to function properly.
Signed-off-by: Liu Shuo soniccat@gmail.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jia Hongtao hongtao@freescale.com
---
Changes for V2:
- Address almost all the comments from Michael Ellerman for V1.
Here is the link:
http://patchwork.ozlabs.org/patch/226833/
arch/powerpc/sysdev/fsl_msi.c | 65
+--
arch/powerpc/sysdev/fsl_msi.h | 2 ++
2 files changed, 64 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_msi.c
b/arch/powerpc/sysdev/fsl_msi.c index 178c994..54cb83e 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -98,8 +98,18 @@ static int fsl_msi_init_allocator(struct fsl_msi
*msi_data)
static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int
type) {
- if (type == PCI_CAP_ID_MSIX)
- pr_debug(fslmsi: MSI-X untested, trying anyway.\n);
+ struct fsl_msi *msi;
+
+ if (type == PCI_CAP_ID_MSI) {
+ /*
+ * MPIC version 2.0 has erratum PIC1. For now MSI
+ * could not work. So check to prevent MSI from
+ * being used on the board with this erratum.
+ */
+ list_for_each_entry(msi, msi_head, list)
+ if (msi-feature MSI_HW_ERRATA_ENDIAN)
+ return -EINVAL;
+ }
return 0;
}
@@ -142,7 +152,17 @@ static void fsl_compose_msi_msg(struct pci_dev
*pdev, int hwirq,
msg-address_lo = lower_32_bits(address);
msg-address_hi = upper_32_bits(address);
- msg-data = hwirq;
+ /*
+ * MPIC version 2.0 has erratum PIC1. It causes
+ * that neither MSI nor MSI-X can work fine.
+ * This is a workaround to allow MSI-X to function
+ * properly. It only works for MSI-X, we prevent
+ * MSI on buggy chips in fsl_msi_check_device().
+ */
+ if (msi_data-feature MSI_HW_ERRATA_ENDIAN)
+ msg-data = __swab32(hwirq);
+ else
+ msg-data = hwirq;
pr_debug(%s: allocated srs: %d, ibs: %d\n,
__func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG);
@@
-361,6 +381,35 @@ static int fsl_msi_setup_hwirq(struct fsl_msi
*msi,
struct platform_device *dev,
return 0;
}
+/* MPIC version 2.0 has erratum PIC1 */ static int
+mpic_has_errata(struct platform_device *dev) {
+ struct device_node *mpic_node;
+
+ mpic_node = of_irq_find_parent(dev-dev.of_node);
+ if (mpic_node) {
+ u32 *reg_base, brr1 = 0;
+ /* Get the PIC reg base */
+ reg_base = of_iomap(mpic_node, 0);
+ of_node_put(mpic_node);
+ if (!reg_base) {
+ dev_err(dev-dev, ioremap problem failed.\n);
+ return -EIO;
+ }
+
+ /* Get the mpic version from block revision register 1 */
+ brr1 = in_be32(reg_base + MPIC_FSL_BRR1);
+ iounmap(reg_base);
+ if ((brr1 MPIC_FSL_BRR1_VER) == 0x0200)
+ return 1;
+ } else {
+ dev_err(dev-dev, MSI can't find his parent mpic node.\n);
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
static const struct of_device_id fsl_of_msi_ids[]; static int
fsl_of_msi_probe(struct platform_device *dev) { @@ -423,6 +472,16 @@
static int fsl_of_msi_probe(struct platform_device *dev)
msi-feature = features-fsl_pic_ip;
+ if ((features-fsl_pic_ip FSL_PIC_IP_MASK) == FSL_PIC_IP_MPIC) {
+ rc = mpic_has_errata(dev);
+ if (rc 0) {
+ msi-feature |= MSI_HW_ERRATA_ENDIAN;
+ } else if (rc 0) {
+ err = rc;
+ goto error_out;
+ }
+ }
+
/*
* Remember the phandle, so that we can match with any PCI nodes
* that have an fsl,msi property.
diff --git a/arch/powerpc/sysdev/fsl_msi.h
b/arch/powerpc/sysdev/fsl_msi.h index 8225f86..7389e8e 100644
--- a/arch/powerpc/sysdev/fsl_msi.h
+++ b/arch/powerpc/sysdev/fsl_msi.h
@@ -25,6 +25,8
RE: [PATCH] powerpc/85xx: Add platform_device declaration to fsl_pci.h
-Original Message- From: Kumar Gala [mailto:ga...@kernel.crashing.org] Sent: Wednesday, March 13, 2013 4:46 AM To: Jia Hongtao-B38951 Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Li Yang-R58472 Subject: Re: [PATCH] powerpc/85xx: Add platform_device declaration to fsl_pci.h On Mar 10, 2013, at 9:36 PM, Jia Hongtao-B38951 wrote: -Original Message- From: Kumar Gala [mailto:ga...@kernel.crashing.org] Sent: Saturday, March 09, 2013 4:38 AM To: Jia Hongtao-B38951 Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Li Yang-R58472 Subject: Re: [PATCH] powerpc/85xx: Add platform_device declaration to fsl_pci.h On Mar 4, 2013, at 2:40 AM, Jia Hongtao wrote: mpc85xx_pci_err_probe(struct platform_device *op) need platform_device declaration for definition. Otherwise, it will cause compile error if any files including fsl_pci.h without declaration of platform_device. Signed-off-by: Jia Hongtao b38...@freescale.com --- arch/powerpc/sysdev/fsl_pci.h |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) Where does the compile error show up? - k The function mpc85xx_pci_err_probe(struct platform_device *op) need *platform_device* declaration so linux/platform_device.h must be included. For now there is no compile error occurred just because the file that need fsl_pci.h happened to include linux/platform_device.h already. If not the compile error log will be like this: In file included from arch/powerpc/kernel/traps.c:62:0: arch/powerpc/sysdev/fsl_pci.h:108:34: error: 'struct platform_device' declared inside parameter list arch/powerpc/sysdev/fsl_pci.h:108:34: error: its scope is only this definition or declaration, which is probably not what you want You mean I have to show the compile error log in patch description? Not necessarily, I'm just trying to decide if we should include linux/platform_device.h or just do: struct platform_device; near the top of fsl_pci.h. Actually just add struct platform_device; works too. Only mpc85xx_edac.c use mpc85xx_pci_err_probe(struct platform_device *op) and linux/platform_device.h has already included there. I will update and send the new patch. -Hongtao. Thanks. -Hongtao. diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h index c495c00..df66721 100644 --- a/arch/powerpc/sysdev/fsl_pci.h +++ b/arch/powerpc/sysdev/fsl_pci.h @@ -14,6 +14,8 @@ #ifndef __POWERPC_FSL_PCI_H #define __POWERPC_FSL_PCI_H +#include linux/platform_device.h + #define PCIE_LTSSM0x0404 /* PCIE Link Training and Status */ #define PCIE_LTSSM_L0 0x16/* L0 state */ #define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */ -- 1.7.5.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
