RE: [PATCH v5 4/4] PCI: layerscape: Add suspend/resume for ls1043a
> From: Frank Li > Subject: [PATCH v5 4/4] PCI: layerscape: Add suspend/resume for ls1043a > > Add suspend/resume support for Layerscape LS1043a. > > In the suspend path, PME_Turn_Off message is sent to the endpoint to > transition the link to L2/L3_Ready state. In this SoC, there is no way to > check if > the controller has received the PME_To_Ack from the endpoint or not. So to be > on the safer side, the driver just waits for PCIE_PME_TO_L2_TIMEOUT_US > before asserting the SoC specific PMXMTTURNOFF bit to complete the > PME_Turn_Off handshake. Then the link would enter L2/L3 state depending on > the VAUX supply. > > In the resume path, the link is brought back from L2 to L0 by doing a software > reset. > > Signed-off-by: Frank Li Acked-by: Roy Zang Roy
RE: [PATCH v5 3/4] PCI: layerscape(ep): Rename pf_* as pf_lut_*
> From: Frank Li > Subject: [PATCH v5 3/4] PCI: layerscape(ep): Rename pf_* as pf_lut_* > > 'pf' and 'lut' is just difference name in difference chips, but basic it is a > MMIO > base address plus an offset. > > Rename it to avoid duplicate pf_* and lut_* in driver. > > Signed-off-by: Frank Li Acked-by: Roy Zang Roy
RE: [PATCH v5 2/4] PCI: layerscape: Add suspend/resume for ls1021a
> From: Frank Li > Subject: [PATCH v5 2/4] PCI: layerscape: Add suspend/resume for ls1021a > > Add suspend/resume support for Layerscape LS1021a. > > In the suspend path, PME_Turn_Off message is sent to the endpoint to > transition the link to L2/L3_Ready state. In this SoC, there is no way to > check if > the controller has received the PME_To_Ack from the endpoint or not. So to be > on the safer side, the driver just waits for PCIE_PME_TO_L2_TIMEOUT_US > before asserting the SoC specific PMXMTTURNOFF bit to complete the > PME_Turn_Off handshake. Then the link would enter L2/L3 state depending on > the VAUX supply. > > In the resume path, the link is brought back from L2 to L0 by doing a software > reset. > > Signed-off-by: Frank Li Acked-by: Roy Zang Roy
RE: [PATCH v5 1/4] PCI: layerscape: Add function pointer for exit_from_l2()
> From: Frank Li > Subject: [PATCH v5 1/4] PCI: layerscape: Add function pointer for > exit_from_l2() > > Since difference SoCs require different sequence for exiting L2, let's add a > separate "exit_from_l2()" callback. This callback can be used to execute SoC > specific sequence. > > Change ls_pcie_exit_from_l2() return value from void to int. Return error if > exit_from_l2() failure at exit resume flow. > > Reviewed-by: Manivannan Sadhasivam > Signed-off-by: Frank Li Acked-by: Roy Zang Roy
RE: [PATCH v3 1/1] PCI: layerscape-ep: set 64-bit DMA mask
> -Original Message- > From: Frank Li > Sent: Tuesday, September 26, 2023 9:05 AM > From: Guanhua Gao > > Set DMA mask and coherent DMA mask to enable 64-bit addressing. > > Signed-off-by: Guanhua Gao > Signed-off-by: Hou Zhiqiang > Signed-off-by: Frank Li > --- > > Notes: > change from v2 to v3 > - remove check return value of dma_set_mask_and_coherent. 64bit mask > always > return success. > - remove redundate comments > change from v1 to v2 > - Remove 32bit DMA mask set. > > drivers/pci/controller/dwc/pci-layerscape-ep.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c > b/drivers/pci/controller/dwc/pci-layerscape-ep.c > index de4c1758a6c3..2c2c9aaa8700 100644 > --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c > +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c > @@ -249,6 +249,8 @@ static int __init ls_pcie_ep_probe(struct > platform_device *pdev) > > pcie->big_endian = of_property_read_bool(dev->of_node, "big- > endian"); > > + dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); > + Acked-by: Roy Zang -R
RE: [PATCH 1/1] PCI: layerscape: Add EP mode support for ls1028a
> -Original Message- > From: Frank Li > Subject: [PATCH 1/1] PCI: layerscape: Add EP mode support for ls1028a > > From: Xiaowei Bao > > Add PCIe EP mode support for ls1028a. > > Signed-off-by: Xiaowei Bao > Signed-off-by: Hou Zhiqiang > --- > > All other patches were already accepte by maintainer in > https://lore.kernel.org/lkml/2022223457.10599-1-leoyang...@nxp.com/ > > But missed this one. > > Re-post. > > drivers/pci/controller/dwc/pci-layerscape-ep.c | 1 + > 1 file changed, 1 insertion(+) Acked-by: Roy Zang R
RE: [PATCH v3 5/5] PCI: Remove unnecessary includes
> -Original Message- > From: Bjorn Helgaas > Subject: [PATCH v3 5/5] PCI: Remove unnecessary includes > > From: Bjorn Helgaas > > Many host controller drivers #include even though they > don't need it. Remove the unnecessary #includes. > > Signed-off-by: Bjorn Helgaas > --- > drivers/pci/controller/cadence/pci-j721e.c | 1 - > drivers/pci/controller/dwc/pci-layerscape.c | 1 - > drivers/pci/controller/dwc/pcie-armada8k.c | 1 - > drivers/pci/controller/dwc/pcie-tegra194.c | 1 - > drivers/pci/controller/pci-v3-semi.c | 1 - > drivers/pci/controller/pci-xgene-msi.c | 1 - > drivers/pci/controller/pci-xgene.c | 1 - > drivers/pci/controller/pcie-altera-msi.c | 1 - > drivers/pci/controller/pcie-iproc-platform.c | 1 - > drivers/pci/controller/pcie-iproc.c | 1 - > drivers/pci/controller/pcie-microchip-host.c | 1 - > drivers/pci/controller/pcie- > rockchip-host.c | 1 - > drivers/pci/controller/pcie-xilinx-cpm.c | 1 - > drivers/pci/controller/pcie-xilinx-nwl.c | 1 - > 14 files changed, 14 deletions(-) Acked-by: Roy Zang -R
RE: [PATCH] PCI: Remove unnecessary of_irq.h includes
> -Original Message- > From: Bjorn Helgaas > > From: Bjorn Helgaas > > Many host controller drivers #include even though they > don't need it. Remove the unnecessary #includes. > > Signed-off-by: Bjorn Helgaas > --- > drivers/pci/controller/cadence/pci-j721e.c | 1 - > drivers/pci/controller/dwc/pci-layerscape.c | 1 - > drivers/pci/controller/dwc/pcie-armada8k.c | 1 - > drivers/pci/controller/dwc/pcie-tegra194.c | 1 - > drivers/pci/controller/pci-v3-semi.c | 1 - > drivers/pci/controller/pci-xgene-msi.c | 1 - > drivers/pci/controller/pci-xgene.c | 1 - > drivers/pci/controller/pcie-altera-msi.c | 1 - > drivers/pci/controller/pcie-iproc-platform.c | 1 - > drivers/pci/controller/pcie-iproc.c | 1 - > drivers/pci/controller/pcie-microchip-host.c | 1 - > drivers/pci/controller/pcie- > rockchip-host.c | 1 - > drivers/pci/controller/pcie-xilinx-cpm.c | 1 - > drivers/pci/controller/pcie-xilinx-nwl.c | 1 - > 14 files changed, 14 deletions(-) Acked-by: Roy Zang Roy
RE: [PATCH -next] pci/controller/dwc: convert comma to semicolon
> From: Lorenzo Pieralisi > On Mon, Mar 22, 2021 at 01:40:16PM +0000, Roy Zang wrote: > > Yes. It is maintained. > > To be maintained you should review its code please. Sure. > > > I will send out a patch. > > Krzysztof already posted one for you, you just need to ack it: > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchw > ork.kernel.org%2Fproject%2Flinux- > pci%2Fpatch%2F20210311033745.1547044-1- > kw%40linux.comdata=04%7C01%7Croy.zang%40nxp.com%7Ced683ff5 > 093443cb9c1608d8ed41150e%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0 > %7C1%7C637520211070640953%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiM > C4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C2000 > sdata=IWTcj7Xs0AdVVIf%2BSFzge6is9D8o0h6SSi7MpibIYcY%3Dr > eserved=0 > > For the future email exchanges: don't top-post please. Acked. Roy
RE: [PATCH] PCI: layerscape: Correct syntax by changing comma to semicolon
Acked-by: Roy Zang Roy -Original Message- From: Krzysztof Wilczyński Sent: Wednesday, March 10, 2021 9:38 PM Replace command with a semicolon to correct syntax and to prevent potential unspecified behaviour and/or unintended side effects. Related: https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Flinux-pci%2F20201216131944.14990-1-zhengyongjun3%40huawei.com%2Fdata=04%7C01%7Croy.zang%40nxp.com%7C8bc03d11ee3f47753d7e08d8e43f0c15%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C637510306719022629%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C2000sdata=coDaErstzzBiGcJUykscD38ogbGXQyvrxt7ZI8cBk%2Fs%3Dreserved=0 Co-authored-by: Zheng Yongjun Signed-off-by: Krzysztof Wilczyński --- drivers/pci/controller/dwc/pci-layerscape-ep.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c index 39fe2ed5a6a2..39f4664bd84c 100644 --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c @@ -154,7 +154,7 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) pci->dev = dev; pci->ops = pcie->drvdata->dw_pcie_ops; - ls_epc->bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4), + ls_epc->bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4); pcie->pci = pci; pcie->ls_epc = ls_epc; -- 2.30.1
RE: [PATCH -next] pci/controller/dwc: convert comma to semicolon
Yes. It is maintained. I will send out a patch. Thanks. Roy -Original Message- From: Lorenzo Pieralisi On Sun, Mar 07, 2021 at 07:36:57PM +0100, Krzysztof Wilczyński wrote: > Hi, > > [...] > > I would request NXP maintainers to take this patch, rewrite it as > > Bjorn requested and resend it as fast as possible, this is a very > > relevant fix. > [...] > > Looking at the state of the pci-layerscape-ep.c file in Linus' tree, > this still hasn't been fixed, and it has been a while. > > NXP folks, are you intend to pick this up? Do let us know. Minghuan, Mingkai, Roy, either one of you reply and follow up this patch or I will have to update the MAINTAINERS entry and take action accordingly, you are not maintaining this driver and I won't maintain your code, sorry. Lorenzo > Krzysztof
Re: [PATCH v2 0/7] PCI: layerscape: Cleanups
On 10/12/2016 11:07 AM, Bjorn Helgaas wrote: > I applied these to pci/host-layerscape for v4.9. I hope to ask Linus to > pull them tomorrow, so if you see any issues, let me know soon. > good to me. Thanks. Roy
Re: [PATCH 1/7] PCI: layerscape: Name private struct pointer "ls" consistently
On 10/07/2016 11:42 AM, Bjorn Helgaas wrote: > Use a device-specific name, "ls", for struct ls_pcie pointers > to hint that this is device-specific information. No functional change > intended. how about ls_pcie instead of ls ? Roy
RE: [PATCH][v2] powerpc/pci: Fix IMMRBAR address
-Original Message- From: Minghuan Lian [mailto:minghuan.l...@freescale.com] Sent: Monday, January 20, 2014 4:54 AM To: linuxppc-dev@lists.ozlabs.org Cc: Zang Roy-R61911; Wood Scott-B07421; Kumar Gala; Lian Minghuan-B31939 Subject: [PATCH][v2] powerpc/pci: Fix IMMRBAR address For PEXCSRBAR, bit 3-0 indicate prefetchable and address type. So when getting base address, these bits should be masked, otherwise we may get incorrect base address. Signed-off-by: Minghuan Lian minghuan.l...@freescale.com Acked. Roy ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH V2] powerpc/85xx: Merge 85xx/p1023_defconfig into mpc85xx_smp_defconfig and mpc85xx_defconfig
-Original Message- From: Linuxppc-dev [mailto:linuxppc-dev-bounces+tie- fei.zang=freescale@lists.ozlabs.org] On Behalf Of Scott Wood Sent: Tuesday, November 12, 2013 4:05 PM To: Pan Lijun-B44306 Cc: linuxppc-...@ozlabs.org Subject: Re: [PATCH V2] powerpc/85xx: Merge 85xx/p1023_defconfig into mpc85xx_smp_defconfig and mpc85xx_defconfig On Mon, 2013-11-11 at 13:25 -0600, Lijun Pan wrote: mpc85xx_smp_defconfig and mpc85xx_defconfig already have CONFIG_P1023RDS=y. Merge CONFIG_P1023RDB=y and other relevant configurations into mpc85xx_smp_defconfig and mpc85_defconfig. Signed-off-by: Lijun Pan lijun@freescale.com --- arch/powerpc/configs/85xx/p1023_defconfig | 188 arch/powerpc/configs/mpc85xx_defconfig | 18 +++ arch/powerpc/configs/mpc85xx_smp_defconfig | 17 +++ 3 files changed, 35 insertions(+), 188 deletions(-) delete mode 100644 arch/powerpc/configs/85xx/p1023_defconfig Are we still going to want to have one defconfig if and when we finally get datapath support upstream? That's a lot of code to add to the 85xx config just for this one chip. P1023 has dpaa. Will mpc85xx_defconfig or mpc85xx_smp_defconfig support dpaa? Thanks. Roy ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH V2] powerpc/85xx: Merge 85xx/p1023_defconfig into mpc85xx_smp_defconfig and mpc85xx_defconfig
-Original Message- From: Wood Scott-B07421 Sent: Tuesday, November 12, 2013 4:52 PM To: Zang Roy-R61911 Cc: Pan Lijun-B44306; linuxppc-...@ozlabs.org Subject: Re: [PATCH V2] powerpc/85xx: Merge 85xx/p1023_defconfig into mpc85xx_smp_defconfig and mpc85xx_defconfig On Tue, 2013-11-12 at 16:49 -0600, Zang Roy-R61911 wrote: -Original Message- From: Linuxppc-dev [mailto:linuxppc-dev-bounces+tie- fei.zang=freescale@lists.ozlabs.org] On Behalf Of Scott Wood Sent: Tuesday, November 12, 2013 4:05 PM To: Pan Lijun-B44306 Cc: linuxppc-...@ozlabs.org Subject: Re: [PATCH V2] powerpc/85xx: Merge 85xx/p1023_defconfig into mpc85xx_smp_defconfig and mpc85xx_defconfig On Mon, 2013-11-11 at 13:25 -0600, Lijun Pan wrote: mpc85xx_smp_defconfig and mpc85xx_defconfig already have CONFIG_P1023RDS=y. Merge CONFIG_P1023RDB=y and other relevant configurations into mpc85xx_smp_defconfig and mpc85_defconfig. Signed-off-by: Lijun Pan lijun@freescale.com --- arch/powerpc/configs/85xx/p1023_defconfig | 188 arch/powerpc/configs/mpc85xx_defconfig | 18 +++ arch/powerpc/configs/mpc85xx_smp_defconfig | 17 +++ 3 files changed, 35 insertions(+), 188 deletions(-) delete mode 100644 arch/powerpc/configs/85xx/p1023_defconfig Are we still going to want to have one defconfig if and when we finally get datapath support upstream? That's a lot of code to add to the 85xx config just for this one chip. P1023 has dpaa. Will mpc85xx_defconfig or mpc85xx_smp_defconfig support dpaa? That's the question I'm asking. Though I suppose we could take a patch like this one for now, and then introduce mpc85xx_dpaa_defconfig when it becomes relevant (which would make clear why the defconfig is separate). p1023 would still work with the non-dpaa defconfigs, but without dpaa support. It will be hard to find a seat for P1023 in mpc85xx_dpaa_defconfig. P1023 does not have corenet. It has e500v2 core. All the other DPAA SOCs have corenet. I suggest leaving p1023 defconfig standalone. Roy ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v2] powerpc/fsl-pci:fix incorrect iounmap pci hose-private_data
pci hose-private_data will be used by other function, for example,
fsl_pcie_check_link(), so do not iounmap it.
fix the kerenl crash on T4240:
Unable to handle kernel paging request for data at address
0x880080060f14
Faulting instruction address: 0xc0032554
Oops: Kernel access of bad area, sig: 11 [#1]
SMP NR_CPUS=24 T4240 QDS
Modules linked in:
NIP: c0032554 LR: c003254c CTR: c001e5c0
REGS: c00179143440 TRAP: 0300 Not tainted
(3.8.8-rt2-00754-g951f064-dirt)
MSR: 80029000 CE,EE,ME CR: 24adbe22 XER:
SOFTE: 0
DEAR: 880080060f14, ESR:
TASK = c0017913d2c0[1] 'swapper/0' THREAD: c0017914 CPU: 2
GPR00: c003254c c001791436c0 c0ae2998
0027
GPR04: 05a5
0002
GPR08: 3030303038303038 c0a2d4d0 c0aebeb8
c0af2998
GPR12: 24adbe22 cfffa800 c0001be0
GPR16:
GPR20:
c09ddf70
GPR24: c09e8d40 c0af2998 c0b1529c
c00179143b40
GPR28: c001799b4000 c00179143c00 88008006
c0727ec8
NIP [c0032554] .fsl_pcie_check_link+0x104/0x150
LR [c003254c] .fsl_pcie_check_link+0xfc/0x150
Call Trace:
[c001791436c0] [c003254c] .fsl_pcie_check_link+0xfc/0x150
(unreliab)
[c00179143a30] [c00325d4]
.fsl_indirect_read_config+0x34/0xb0
[c00179143ad0] [c02c7ee8]
.pci_bus_read_config_byte+0x88/0xd0
[c00179143b90] [c09c0528] .pci_apply_final_quirks+0x9c/0x18c
[c00179143c40] [c000142c] .do_one_initcall+0x5c/0x1f0
[c00179143cf0] [c09a0bb4] .kernel_init_freeable+0x180/0x264
[c00179143db0] [c0001bfc] .kernel_init+0x1c/0x420
[c00179143e30] [c8b4] .ret_from_kernel_thread+0x64/0xb0
Instruction dump:
6000 4ba0 ebc301d0 3fe2ffc4 3c62ffe0 3bff5530 38638a78 7fe4fb78
7fc5f378 486ea77d 6000 7c0004ac 801e0f14 0c00 4c00012c
3c62ffe0
---[ end trace f841fbc03c9d2e1b ]---
Kernel panic - not syncing: Attempted to kill init! exitcode=0x000b
Rebooting in 180 seconds..
Signed-off-by: Yuanquan Chen yuanquan.c...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
based on Kumar's next branch
v2:v1, fix the exit issue
arch/powerpc/sysdev/fsl_pci.c |7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index f823304..cffe7ed 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -244,12 +244,12 @@ static void setup_pci_atmu(struct pci_controller *hose)
if (paddr_hi == paddr_lo) {
pr_err(%s: No outbound window space\n, name);
- goto out;
+ return;
}
if (paddr_lo == 0) {
pr_err(%s: No space for inbound window\n, name);
- goto out;
+ return;
}
/* setup PCSRBAR/PEXCSRBAR */
@@ -395,9 +395,6 @@ static void setup_pci_atmu(struct pci_controller *hose)
pr_info(%s: DMA window size is 0x%llx\n, name,
(u64)hose-dma_window_size);
}
-
-out:
- iounmap(pci);
}
static void __init setup_pci_cmd(struct pci_controller *hose)
--
1.7.9.5
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Re: [PATCH v2] powerpc/fsl-pci:fix incorrect iounmap pci hose-private_data
On 04/23/2013 05:13 PM, Kevin Hao wrote: On Tue, Apr 23, 2013 at 11:18:03PM +0800, Roy Zang wrote: pci hose-private_data will be used by other function, for example, fsl_pcie_check_link(), so do not iounmap it. I already sent out a same patch ten days ago. :-) http://patchwork.ozlabs.org/patch/236293/ Thanks, Kevin I do not notice it. That is good :-) Kumar, You can pick up the post from Kevin. Thanks. Roy ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/fsl-pci: don't unmap the PCI SoC controller registers in setup_pci_atmu
On 04/13/2013 03:14 PM, Kevin Hao wrote: In patch 34642bbb (powerpc/fsl-pci: Keep PCI SoC controller registers in pci_controller) we choose to keep the map of the PCI SoC controller registers. But we missed to delete the unmap in setup_pci_atmu function. This will cause the following call trace once we access the PCI SoC controller registers later. Unable to handle kernel paging request for data at address 0x880080040f14 Faulting instruction address: 0xc002ea58 Oops: Kernel access of bad area, sig: 11 [#1] SMP NR_CPUS=24 T4240 QDS Modules linked in: NIP: c002ea58 LR: c002eaf4 CTR: c002eac0 REGS: c0017e10b4a0 TRAP: 0300 Not tainted (3.9.0-rc1-00052-gfa3529f-dirty) MSR: 80029000 CE,EE,ME CR: 28adbe22 XER: SOFTE: 0 DEAR: 880080040f14, ESR: TASK = c0017e10[1] 'swapper/0' THREAD: c0017e108000 CPU: 2 GPR00: c0017e10b720 c09928d8 c0017e578e00 GPR04: 000c 0001 c0017e10bb40 GPR08: 88008004 0016 GPR12: 88adbe22 cfffa800 c0001ba0 GPR16: GPR20: c08a5b70 GPR24: c08af938 c09a28d8 c09bb5dc c0017e10bb40 GPR28: c0017e32a400 c0017e10bc00 c0017e32a400 c0017e578e00 NIP [c002ea58] .fsl_pcie_check_link+0x88/0xf0 LR [c002eaf4] .fsl_indirect_read_config+0x34/0xb0 Call Trace: [c0017e10b720] [c0017e10b7a0] 0xc0017e10b7a0 (unreliable) [c0017e10ba30] [c002eaf4] .fsl_indirect_read_config+0x34/0xb0 [c0017e10bad0] [c033aa08] .pci_bus_read_config_byte+0x88/0xd0 [c0017e10bb90] [c088d708] .pci_apply_final_quirks+0x9c/0x18c [c0017e10bc40] [c00013dc] .do_one_initcall+0x5c/0x1f0 [c0017e10bcf0] [c086ebac] .kernel_init_freeable+0x180/0x26c [c0017e10bdb0] [c0001bbc] .kernel_init+0x1c/0x460 [c0017e10be30] [c880] .ret_from_kernel_thread+0x64/0xe4 Instruction dump: 38210310 2b800015 4fdde842 7c600026 5463fffe e8010010 7c0803a6 4e800020 6000 6000 e92301d0 7c0004ac 80690f14 0c03 4c00012c 38210310 ---[ end trace 7a8fe0cbccb7d992 ]--- Kernel panic - not syncing: Attempted to kill init! exitcode=0x000b Signed-off-by: Kevin Hao haoke...@gmail.com --- acked. thanks. Roy ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/fsl-pci:fix incorrect iounmap pci hose-private_data
pci hose-private_data will be used by other function, for example,
fsl_pcie_check_link(), so do not iounmap it.
fix the kerenl crash on T4240:
Unable to handle kernel paging request for data at address
0x880080060f14
Faulting instruction address: 0xc0032554
Oops: Kernel access of bad area, sig: 11 [#1]
SMP NR_CPUS=24 T4240 QDS
Modules linked in:
NIP: c0032554 LR: c003254c CTR: c001e5c0
REGS: c00179143440 TRAP: 0300 Not tainted
(3.8.8-rt2-00754-g951f064-dirt)
MSR: 80029000 CE,EE,ME CR: 24adbe22 XER:
SOFTE: 0
DEAR: 880080060f14, ESR:
TASK = c0017913d2c0[1] 'swapper/0' THREAD: c0017914 CPU: 2
GPR00: c003254c c001791436c0 c0ae2998
0027
GPR04: 05a5
0002
GPR08: 3030303038303038 c0a2d4d0 c0aebeb8
c0af2998
GPR12: 24adbe22 cfffa800 c0001be0
GPR16:
GPR20:
c09ddf70
GPR24: c09e8d40 c0af2998 c0b1529c
c00179143b40
GPR28: c001799b4000 c00179143c00 88008006
c0727ec8
NIP [c0032554] .fsl_pcie_check_link+0x104/0x150
LR [c003254c] .fsl_pcie_check_link+0xfc/0x150
Call Trace:
[c001791436c0] [c003254c] .fsl_pcie_check_link+0xfc/0x150
(unreliab)
[c00179143a30] [c00325d4]
.fsl_indirect_read_config+0x34/0xb0
[c00179143ad0] [c02c7ee8]
.pci_bus_read_config_byte+0x88/0xd0
[c00179143b90] [c09c0528] .pci_apply_final_quirks+0x9c/0x18c
[c00179143c40] [c000142c] .do_one_initcall+0x5c/0x1f0
[c00179143cf0] [c09a0bb4] .kernel_init_freeable+0x180/0x264
[c00179143db0] [c0001bfc] .kernel_init+0x1c/0x420
[c00179143e30] [c8b4] .ret_from_kernel_thread+0x64/0xb0
Instruction dump:
6000 4ba0 ebc301d0 3fe2ffc4 3c62ffe0 3bff5530 38638a78 7fe4fb78
7fc5f378 486ea77d 6000 7c0004ac 801e0f14 0c00 4c00012c
3c62ffe0
---[ end trace f841fbc03c9d2e1b ]---
Kernel panic - not syncing: Attempted to kill init! exitcode=0x000b
Rebooting in 180 seconds..
Signed-off-by: Yuanquan Chen yuanquan.c...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
based on Kumar's next branch.
tested on P3041 and T4240.
arch/powerpc/sysdev/fsl_pci.c | 11 ++-
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index f823304..c343edc 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -242,15 +242,11 @@ static void setup_pci_atmu(struct pci_controller *hose)
paddr_hi -= hose-pci_mem_offset;
paddr_lo -= hose-pci_mem_offset;
- if (paddr_hi == paddr_lo) {
+ if (paddr_hi == paddr_lo)
pr_err(%s: No outbound window space\n, name);
- goto out;
- }
- if (paddr_lo == 0) {
+ if (paddr_lo == 0)
pr_err(%s: No space for inbound window\n, name);
- goto out;
- }
/* setup PCSRBAR/PEXCSRBAR */
early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0x);
@@ -395,9 +391,6 @@ static void setup_pci_atmu(struct pci_controller *hose)
pr_info(%s: DMA window size is 0x%llx\n, name,
(u64)hose-dma_window_size);
}
-
-out:
- iounmap(pci);
}
static void __init setup_pci_cmd(struct pci_controller *hose)
--
1.7.9.5
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[PATCH] powerpc/fsl-pci: fix setup_pci_atmu() parameter issue
setup_pci_atmu() only has one parameter and remove the extra one, or build will fail due to un-match. Signed-off-by: Roy Zang tie-fei.z...@freescale.com --- arch/powerpc/sysdev/fsl_pci.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 40ffe29..f823304 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -978,7 +978,7 @@ static int fsl_pci_resume(struct device *dev) return -ENODEV; } - setup_pci_atmu(hose, pci_rsrc); + setup_pci_atmu(hose); return 0; } -- 1.7.9.5 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/fsl-pci: fix setup_pci_atmu() parameter issue
On 04/20/2013 02:55 AM, Roy Zang wrote: setup_pci_atmu() only has one parameter and remove the extra one, or build will fail due to un-match. Signed-off-by: Roy Zang tie-fei.z...@freescale.com --- based on Kumar's next branch. Roy ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/pci: fix 64 bit pci size issue
The size might be 64 bit, so use ilog2() instead of __ilog2() or
__ilog2_u64().
ilog2() can select 32bit or 64bit funciton automatically.
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
arch/powerpc/sysdev/fsl_pci.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 682084d..a0a1b76 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -106,7 +106,7 @@ static int setup_one_atmu(struct ccsr_pci __iomem *pci,
flags |= 0x1000; /* enable relaxed ordering */
for (i = 0; size 0; i++) {
- unsigned int bits = min(__ilog2(size),
+ unsigned int bits = min(ilog2(size),
__ffs(pci_addr | phys_addr));
if (index + i = 5)
@@ -196,7 +196,7 @@ static void setup_pci_atmu(struct pci_controller *hose,
out_be32(pci-pow[j].powbar, (hose-io_base_phys
12));
/* Enable, IO R/W */
out_be32(pci-pow[j].powar, 0x80088000
- | (__ilog2(hose-io_resource.end
+ | (ilog2(hose-io_resource.end
- hose-io_resource.start + 1) - 1));
}
}
@@ -261,7 +261,7 @@ static void setup_pci_atmu(struct pci_controller *hose,
}
sz = min(mem, paddr_lo);
- mem_log = __ilog2_u64(sz);
+ mem_log = ilog2(sz);
/* PCIe can overmap inbound outbound since RX TX are separated */
if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
@@ -290,7 +290,7 @@ static void setup_pci_atmu(struct pci_controller *hose,
* SWIOTLB and access the full range of memory
*/
if (sz != mem) {
- mem_log = __ilog2_u64(mem);
+ mem_log = ilog2(mem);
/* Size window up if we dont fit in exact power-of-2 */
if ((1ull mem_log) != mem)
@@ -327,7 +327,7 @@ static void setup_pci_atmu(struct pci_controller *hose,
sz -= 1ull mem_log;
if (sz) {
- mem_log = __ilog2_u64(sz);
+ mem_log = ilog2(sz);
piwar |= (mem_log - 1);
out_be32(pci-piw[win_idx].pitar, paddr 12);
--
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[upstream] mtd/ifc: fix ifc driver memory release issue
memory is allocated by devm_kzalloc, so release it using
devm_kfree() instead kfree();
Signed-off-by: Li Hao b44...@freescale.com
Signed-off-by: Cao Yonghua b43...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
drivers/mtd/nand/fsl_ifc_nand.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index f1f7f12..b574ca4 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -908,7 +908,7 @@ static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv)
ifc_nand_ctrl-chips[priv-bank] = NULL;
dev_set_drvdata(priv-dev, NULL);
- kfree(priv);
+ devm_kfree(priv-dev, priv);
return 0;
}
@@ -974,6 +974,7 @@ static int fsl_ifc_nand_probe(struct platform_device *dev)
if (!ifc_nand_ctrl) {
dev_err(dev-dev, failed to allocate memory\n);
mutex_unlock(fsl_ifc_nand_mutex);
+ devm_kfree(dev-dev, priv);
return -ENOMEM;
}
--
1.7.9.5
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[PATCH] powerpc/85xx: enable E1000 NIC to mpc85xx_defconfig
E1000 NIC is a common used Ethernet card. Enable it as default for mpc85xx platform. other change is due to make savedefconfig Reported-by: Fu Jiwei b36...@freescale.com Signed-off-by: Roy Zang tie-fei.z...@freescale.com --- tested on P1010rdb board arch/powerpc/configs/mpc85xx_defconfig |8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig index cf815e8..e12146f 100644 --- a/arch/powerpc/configs/mpc85xx_defconfig +++ b/arch/powerpc/configs/mpc85xx_defconfig @@ -1,13 +1,12 @@ CONFIG_PPC_85xx=y CONFIG_PHYS_64BIT=y -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y -CONFIG_BSD_PROCESS_ACCT=y CONFIG_AUDIT=y CONFIG_IRQ_DOMAIN_DEBUG=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_BSD_PROCESS_ACCT=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 @@ -113,6 +112,9 @@ CONFIG_DUMMY=y CONFIG_FS_ENET=y CONFIG_UCC_GETH=y CONFIG_GIANFAR=y +CONFIG_E1000=y +CONFIG_E1000E=y +CONFIG_IGB=y CONFIG_MARVELL_PHY=y CONFIG_DAVICOM_PHY=y CONFIG_CICADA_PHY=y @@ -132,7 +134,6 @@ CONFIG_SERIAL_8250_DETECT_IRQ=y CONFIG_SERIAL_8250_RSA=y CONFIG_SERIAL_QE=m CONFIG_NVRAM=y -CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_CPM=m CONFIG_I2C_MPC=y @@ -230,7 +231,6 @@ CONFIG_DEBUG_INFO=y CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_AES=y # CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_DEV_FSL_CAAM=y CONFIG_CRYPTO_DEV_TALITOS=y -- 1.7.9.5 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 5/8] powerpc/fsl-booke: Add initial silicon device tree for
On 03/06/2013 07:15 AM, Kumar Gala wrote: * Thread support on e6500 * Proper PAMU topology information * DPAA related nodes (Qman, Bman, Fman, Rman, DCE) * Prefetch Manager * Thermal monitor unit * Interlaken Signed-off-by: Roy Zangtie-fei.z...@freescale.com Signed-off-by: Minghuan Lianminghuan.l...@freescale.com Signed-off-by: Haiying Wanghaiying.w...@freescale.com Signed-off-by: Andy Flemingaflem...@freescale.com Signed-off-by: Prabhakar Kushwahaprabha...@freescale.com Signed-off-by: York Sunyork...@freescale.com Signed-off-by: Vakul Gargva...@freescale.com Signed-off-by: Tang Yuantianyuantian.t...@freescale.com Signed-off-by: Zhao Chenhuichenhui.z...@freescale.com Signed-off-by: Li Yangle...@freescale.com Signed-off-by: Ramneek Mehreshramneek.mehr...@freescale.com Signed-off-by: Haiying Wanghaiying.w...@freescale.com Haiying is doubled. Roy ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/2] powerpc/pci: Add IP revision register define for Freescale PCIe controller
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
arch/powerpc/sysdev/fsl_pci.h |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index baa0fd1..7192932 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -16,6 +16,7 @@
#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
#define PCIE_LTSSM_L0 0x16/* L0 state */
+#define PCIE_IP_REV_2_20x02080202 /* PCIE IP block version
Rev2.2 */
#define PIWAR_EN 0x8000 /* Enable */
#define PIWAR_PF 0x2000 /* prefetch */
#define PIWAR_TGI_LOCAL0x00f0 /* target - local
memory */
@@ -57,7 +58,9 @@ struct ccsr_pci {
__be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message
disable register */
__be32 pex_pme_mes_ier;/* 0x.028 - PCIE PME and message
interrupt enable register */
__be32 pex_pmcr; /* 0x.02c - PCIE power management
command register */
- u8 res3[3024];
+ u8 res3[3016];
+ __be32 block_rev1; /* 0x.bf8 - PCIE Block Revision register 1 */
+ __be32 block_rev2; /* 0x.bfc - PCIE Block Revision register 2 */
/* PCI/PCI Express outbound window 0-4
* Window 0 is the default window and is the only window enabled upon reset.
--
1.7.8.1
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[PATCH 2/2] powerpc/pci: Use PCIe IP block revision register instead of compatible
Freescale PCIe IP block revision bigger than rev2.2 will also need
redefine the sequence of inbound windows. So change to use IP block
revision instead of compatible for the judgment.
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
arch/powerpc/sysdev/fsl_pci.c | 14 --
1 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index a7b2a60..bce48e6 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -143,18 +143,20 @@ static void __init setup_pci_atmu(struct pci_controller
*hose,
pr_debug(PCI memory map start 0x%016llx, size 0x%016llx\n,
(u64)rsrc-start, (u64)resource_size(rsrc));
- if (of_device_is_compatible(hose-dn, fsl,qoriq-pcie-v2.2)) {
- win_idx = 2;
- start_idx = 0;
- end_idx = 3;
- }
-
pci = ioremap(rsrc-start, resource_size(rsrc));
if (!pci) {
dev_err(hose-parent, Unable to map ATMU registers\n);
return;
}
+ if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
+ if (in_be32(pci-block_rev1) = PCIE_IP_REV_2_2) {
+ win_idx = 2;
+ start_idx = 0;
+ end_idx = 3;
+ }
+ }
+
/* Disable all windows (except powar0 since it's ignored) */
for(i = 1; i 5; i++)
out_be32(pci-pow[i].powar, 0);
--
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[PATCH] powerpc/p1023: set IRQ[4:6, 11] to high level sensitive for PCIe
P1023 external IRQ[4:6, 11] do not pin out, but the interrupts are shared with PCIe controller. The silicon internally ties the interrupts to L, so change the IRQ[4:6,11] to high level sensitive for PCIe. Signed-off-by: Roy Zang tie-fei.z...@freescale.com --- arch/powerpc/boot/dts/p1023rds.dts |8 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/boot/dts/p1023rds.dts b/arch/powerpc/boot/dts/p1023rds.dts index d9b7767..66bf804 100644 --- a/arch/powerpc/boot/dts/p1023rds.dts +++ b/arch/powerpc/boot/dts/p1023rds.dts @@ -490,9 +490,9 @@ interrupt-map-mask = 0xf800 0 0 7; interrupt-map = /* IDSEL 0x0 */ - 0 0 1 mpic 4 1 - 0 0 2 mpic 5 1 - 0 0 3 mpic 6 1 + 0 0 1 mpic 4 2 + 0 0 2 mpic 5 2 + 0 0 3 mpic 6 2 0 0 4 mpic 7 1 ; ranges = 0x200 0x0 0xa000 @@ -532,7 +532,7 @@ 0 0 1 mpic 8 1 0 0 2 mpic 9 1 0 0 3 mpic 10 1 - 0 0 4 mpic 11 1 + 0 0 4 mpic 11 2 ; ranges = 0x200 0x0 0x8000 0x200 0x0 0x8000 -- 1.6.0.6 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] eSDHC: Access Freescale eSDHC registers by 32-bit
From: Xu lei b33...@freescale.com
Freescale eSDHC registers only support 32-bit accesses,
this patch ensures that all Freescale eSDHC register accesses
are 32-bit.
Signed-off-by: Xu lei b33...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
This is a patch resend
http://patchwork.ozlabs.org/patch/106245/
based on latest Linus tree.
Andrew,
Could you help to pick up this patch first?
Thanks.
Roy
drivers/mmc/host/sdhci-of-esdhc.c | 18 ++
1 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c
b/drivers/mmc/host/sdhci-of-esdhc.c
index fe604df..40036f6 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -1,7 +1,7 @@
/*
* Freescale eSDHC controller driver.
*
- * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ * Copyright (c) 2007, 2010 Freescale Semiconductor, Inc.
* Copyright (c) 2009 MontaVista Software, Inc.
*
* Authors: Xiaobo Xie x@freescale.com
@@ -22,11 +22,21 @@
static u16 esdhc_readw(struct sdhci_host *host, int reg)
{
u16 ret;
+ int base = reg ~0x3;
+ int shift = (reg 0x2) * 8;
if (unlikely(reg == SDHCI_HOST_VERSION))
- ret = in_be16(host-ioaddr + reg);
+ ret = in_be32(host-ioaddr + base) 0x;
else
- ret = sdhci_be32bs_readw(host, reg);
+ ret = (in_be32(host-ioaddr + base) shift) 0x;
+ return ret;
+}
+
+static u8 esdhc_readb(struct sdhci_host *host, int reg)
+{
+ int base = reg ~0x3;
+ int shift = (reg 0x3) * 8;
+ u8 ret = (in_be32(host-ioaddr + base) shift) 0xff;
return ret;
}
@@ -74,7 +84,7 @@ static unsigned int esdhc_of_get_min_clock(struct sdhci_host
*host)
static struct sdhci_ops sdhci_esdhc_ops = {
.read_l = sdhci_be32bs_readl,
.read_w = esdhc_readw,
- .read_b = sdhci_be32bs_readb,
+ .read_b = esdhc_readb,
.write_l = sdhci_be32bs_writel,
.write_w = esdhc_writew,
.write_b = esdhc_writeb,
--
1.6.0.6
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[PATCH 1/2 v2] eSDHC: Access Freescale eSDHC registers by 32-bit
From: Xu lei b33...@freescale.com
For Freescale eSDHC registers only support 32-bit accesses,
this patch ensure that all Freescale eSDHC register accesses
are 32-bit.
Signed-off-by: Xu lei b33...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
this patch set replaces previous patches:
https://patchwork.kernel.org/patch/943332/
https://patchwork.kernel.org/patch/943342/
https://patchwork.kernel.org/patch/943322/
The last one is discarded according to the comment from Anton.
just resend with the new patch set. no change for this patch comparing
to previous version.
drivers/mmc/host/sdhci-of-esdhc.c | 18 ++
1 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c
b/drivers/mmc/host/sdhci-of-esdhc.c
index ba40d6d..c9a8519 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -1,7 +1,7 @@
/*
* Freescale eSDHC controller driver.
*
- * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ * Copyright (c) 2007, 2010 Freescale Semiconductor, Inc.
* Copyright (c) 2009 MontaVista Software, Inc.
*
* Authors: Xiaobo Xie x@freescale.com
@@ -23,11 +23,21 @@
static u16 esdhc_readw(struct sdhci_host *host, int reg)
{
u16 ret;
+ int base = reg ~0x3;
+ int shift = (reg 0x2) * 8;
if (unlikely(reg == SDHCI_HOST_VERSION))
- ret = in_be16(host-ioaddr + reg);
+ ret = in_be32(host-ioaddr + base) 0x;
else
- ret = sdhci_be32bs_readw(host, reg);
+ ret = (in_be32(host-ioaddr + base) shift) 0x;
+ return ret;
+}
+
+static u8 esdhc_readb(struct sdhci_host *host, int reg)
+{
+ int base = reg ~0x3;
+ int shift = (reg 0x3) * 8;
+ u8 ret = (in_be32(host-ioaddr + base) shift) 0xff;
return ret;
}
@@ -79,7 +89,7 @@ struct sdhci_of_data sdhci_esdhc = {
.ops = {
.read_l = sdhci_be32bs_readl,
.read_w = esdhc_readw,
- .read_b = sdhci_be32bs_readb,
+ .read_b = esdhc_readb,
.write_l = sdhci_be32bs_writel,
.write_w = esdhc_writew,
.write_b = esdhc_writeb,
--
1.6.0.6
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[PATCH 2/2 v2] eSDHC: Fix errors when booting kernel with fsl esdhc
From: Xu lei b33...@freescale.com
When esdhc module was enabled in p5020, there were following errors:
mmc0: Timeout waiting for hardware interrupt.
mmc0: error -110 whilst initialising SD card
mmc0: Unexpected interrupt 0x0200.
mmc0: Timeout waiting for hardware interrupt.
mmc0: error -110 whilst initialising SD card
mmc0: Unexpected interrupt 0x0200.
It is because ESDHC controller has different bit setting for PROCTL
register, when kernel sets Power Control Register by method for standard
SD Host Specification, it would overwritten FSL ESDHC PROCTL[DMAS];
when it set Host Control Registers[DMAS], it sets PROCTL[EMODE] and
PROCTL[D3CD]. These operations will set bad bits for PROCTL Register
on FSL ESDHC Controller and cause errors, so this patch will make esdhc
driver access FSL PROCTL Register according to block guide instead of
standard SD Host Specification.
For some FSL chips, such as MPC8536/P2020, PROCTL[VOLT_SEL] and PROCTL[DMAS]
bits are reserved and even if they are set to wrong bits there is no error.
But considering that all FSL ESDHC Controller register map is not fully
compliant to standard SD Host Specification, we put the patch to all of
FSL ESDHC Controllers.
Signed-off-by: Lei Xu b33...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
v2:v1 some minor code style fix according to Venkatraman's comment.
drivers/mmc/host/sdhci-of-core.c |3 ++
drivers/mmc/host/sdhci.c | 64 ++---
include/linux/mmc/sdhci.h|6 ++-
3 files changed, 59 insertions(+), 14 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-core.c b/drivers/mmc/host/sdhci-of-core.c
index 60e4186..fede43d 100644
--- a/drivers/mmc/host/sdhci-of-core.c
+++ b/drivers/mmc/host/sdhci-of-core.c
@@ -179,6 +179,9 @@ static int __devinit sdhci_of_probe(struct platform_device
*ofdev)
if (sdhci_of_wp_inverted(np))
host-quirks |= SDHCI_QUIRK_INVERTED_WRITE_PROTECT;
+ if (of_device_is_compatible(np, fsl,esdhc))
+ host-quirks |= SDHCI_QUIRK_QORIQ_PROCTL_WEIRD;
+
clk = of_get_property(np, clock-frequency, size);
if (clk size == sizeof(*clk) *clk)
of_host-clock = be32_to_cpup(clk);
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 58d5436..855fbe8 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -674,7 +674,7 @@ static void sdhci_set_transfer_irqs(struct sdhci_host *host)
static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command
*cmd)
{
u8 count;
- u8 ctrl;
+ u32 ctrl;
struct mmc_data *data = cmd-data;
int ret;
@@ -807,14 +807,28 @@ static void sdhci_prepare_data(struct sdhci_host *host,
struct mmc_command *cmd)
* is ADMA.
*/
if (host-version = SDHCI_SPEC_200) {
- ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
- ctrl = ~SDHCI_CTRL_DMA_MASK;
- if ((host-flags SDHCI_REQ_USE_DMA)
- (host-flags SDHCI_USE_ADMA))
- ctrl |= SDHCI_CTRL_ADMA32;
- else
- ctrl |= SDHCI_CTRL_SDMA;
- sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+ if (host-quirks SDHCI_QUIRK_QORIQ_PROCTL_WEIRD) {
+#define ESDHCI_PROCTL_DMAS_MASK0x0300
+#define ESDHCI_PROCTL_ADMA32 0x0200
+#define ESDHCI_PROCTL_SDMA 0x
+ ctrl = sdhci_readl(host, SDHCI_HOST_CONTROL);
+ ctrl = ~ESDHCI_PROCTL_DMAS_MASK;
+ if ((host-flags SDHCI_REQ_USE_DMA)
+ (host-flags SDHCI_USE_ADMA))
+ ctrl |= ESDHCI_PROCTL_ADMA32;
+ else
+ ctrl |= ESDHCI_PROCTL_SDMA;
+ sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL);
+ } else {
+ ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
+ ctrl = ~SDHCI_CTRL_DMA_MASK;
+ if ((host-flags SDHCI_REQ_USE_DMA)
+ (host-flags SDHCI_USE_ADMA))
+ ctrl |= SDHCI_CTRL_ADMA32;
+ else
+ ctrl |= SDHCI_CTRL_SDMA;
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+ }
}
if (!(host-flags SDHCI_REQ_USE_DMA)) {
@@ -1138,19 +1152,32 @@ out:
static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
{
u8 pwr = 0;
+ u8 volt = 0;
if (power != (unsigned short)-1) {
switch (1 power) {
+#defineESDHCI_FSL_POWER_MASK 0x40
+#defineESDHCI_FSL_POWER_1800x00
+#defineESDHCI_FSL_POWER_3000x40
case MMC_VDD_165_195
[PATCH 1/3] eSDHC: Access Freescale eSDHC registers by 32-bit
From: Xu lei b33...@freescale.com
For Freescale eSDHC registers only support 32-bit accesses,
this patch ensure that all Freescale eSDHC register accesses
are 32-bit.
Signed-off-by: Xu lei b33...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
drivers/mmc/host/sdhci-of-esdhc.c | 18 ++
1 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c
b/drivers/mmc/host/sdhci-of-esdhc.c
index ba40d6d..c9a8519 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -1,7 +1,7 @@
/*
* Freescale eSDHC controller driver.
*
- * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ * Copyright (c) 2007, 2010 Freescale Semiconductor, Inc.
* Copyright (c) 2009 MontaVista Software, Inc.
*
* Authors: Xiaobo Xie x@freescale.com
@@ -23,11 +23,21 @@
static u16 esdhc_readw(struct sdhci_host *host, int reg)
{
u16 ret;
+ int base = reg ~0x3;
+ int shift = (reg 0x2) * 8;
if (unlikely(reg == SDHCI_HOST_VERSION))
- ret = in_be16(host-ioaddr + reg);
+ ret = in_be32(host-ioaddr + base) 0x;
else
- ret = sdhci_be32bs_readw(host, reg);
+ ret = (in_be32(host-ioaddr + base) shift) 0x;
+ return ret;
+}
+
+static u8 esdhc_readb(struct sdhci_host *host, int reg)
+{
+ int base = reg ~0x3;
+ int shift = (reg 0x3) * 8;
+ u8 ret = (in_be32(host-ioaddr + base) shift) 0xff;
return ret;
}
@@ -79,7 +89,7 @@ struct sdhci_of_data sdhci_esdhc = {
.ops = {
.read_l = sdhci_be32bs_readl,
.read_w = esdhc_readw,
- .read_b = sdhci_be32bs_readb,
+ .read_b = esdhc_readb,
.write_l = sdhci_be32bs_writel,
.write_w = esdhc_writew,
.write_b = esdhc_writeb,
--
1.6.0.6
___
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[PATCH 3/3] eSDHC: fix incorrect default value of the capabilities register on P4080
P4080 eSDHC errata 12 describes incorrect default value of the
the host controller capabilities register.
The default value of the VS18 and VS30 fields in the host controller
capabilities register (HOSTCAPBLT) are incorrect. The default of these bits
should be zero instead of one in the eSDHC logic.
This patch adds the workaround for these errata.
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
drivers/mmc/host/sdhci-of-core.c |3 +++
drivers/mmc/host/sdhci.c |6 ++
include/linux/mmc/sdhci.h|4
3 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-core.c b/drivers/mmc/host/sdhci-of-core.c
index fede43d..9bdd30d 100644
--- a/drivers/mmc/host/sdhci-of-core.c
+++ b/drivers/mmc/host/sdhci-of-core.c
@@ -182,6 +182,9 @@ static int __devinit sdhci_of_probe(struct platform_device
*ofdev)
if (of_device_is_compatible(np, fsl,esdhc))
host-quirks |= SDHCI_QUIRK_QORIQ_PROCTL_WEIRD;
+ if (of_device_is_compatible(np, fsl,p4080-esdhc))
+ host-quirks |= SDHCI_QUIRK_QORIQ_HOSTCAPBLT_ONLY_VS33;
+
clk = of_get_property(np, clock-frequency, size);
if (clk size == sizeof(*clk) *clk)
of_host-clock = be32_to_cpup(clk);
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 77174e5..7e0b4cd 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -2396,6 +2396,12 @@ int sdhci_add_host(struct sdhci_host *host)
caps[1] = (host-version = SDHCI_SPEC_300) ?
sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
+/* Make sure clean the VS18 and VS30 bit. P4080 incorrectly
+ * set the voltage capability bits
+ */
+ if (host-quirks SDHCI_QUIRK_QORIQ_HOSTCAPBLT_ONLY_VS33)
+ caps[0] = ~(SDHCI_CAN_VDD_180 | SDHCI_CAN_VDD_300);
+
if (host-quirks SDHCI_QUIRK_FORCE_DMA)
host-flags |= SDHCI_USE_SDMA;
else if (!(caps[0] SDHCI_CAN_DO_SDMA))
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index d87abc7..7ffd458 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -89,6 +89,10 @@ struct sdhci_host {
#define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1U31)
/* Controller has weird bit setting for Protocol Control Register */
#define SDHCI_QUIRK_QORIQ_PROCTL_WEIRD (0x1U)
+/* Controller can only supports 3.3V, but the capabilities register
+ * has incorrect set 1.8V and 3.0V
+ */
+#define SDHCI_QUIRK_QORIQ_HOSTCAPBLT_ONLY_VS33 (0x2U)
int irq;/* Device IRQ */
void __iomem *ioaddr; /* Mapped address */
--
1.6.0.6
___
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[PATCH 2/3] eSDHC: Fix errors when booting kernel with fsl esdhc
From: Xu lei b33...@freescale.com
When esdhc module was enabled in p5020, there were following errors:
mmc0: Timeout waiting for hardware interrupt.
mmc0: error -110 whilst initialising SD card
mmc0: Unexpected interrupt 0x0200.
mmc0: Timeout waiting for hardware interrupt.
mmc0: error -110 whilst initialising SD card
mmc0: Unexpected interrupt 0x0200.
It is because ESDHC controller has different bit setting for PROCTL
register, when kernel sets Power Control Register by method for standard
SD Host Specification, it would overwritten FSL ESDHC PROCTL[DMAS];
when it set Host Control Registers[DMAS], it sets PROCTL[EMODE] and
PROCTL[D3CD]. These operations will set bad bits for PROCTL Register
on FSL ESDHC Controller and cause errors, so this patch will make esdhc
driver access FSL PROCTL Register according to block guide instead of
standard SD Host Specification.
For some FSL chips, such as MPC8536/P2020, PROCTL[VOLT_SEL] and PROCTL[DMAS]
bits are reserved and even if they are set to wrong bits there is no error.
But considering that all FSL ESDHC Controller register map is not fully
compliant to standard SD Host Specification, we put the patch to all of
FSL ESDHC Controllers.
Signed-off-by: Lei Xu b33...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
drivers/mmc/host/sdhci-of-core.c |3 ++
drivers/mmc/host/sdhci.c | 62 ++---
include/linux/mmc/sdhci.h|6 ++-
3 files changed, 57 insertions(+), 14 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-core.c b/drivers/mmc/host/sdhci-of-core.c
index 60e4186..fede43d 100644
--- a/drivers/mmc/host/sdhci-of-core.c
+++ b/drivers/mmc/host/sdhci-of-core.c
@@ -179,6 +179,9 @@ static int __devinit sdhci_of_probe(struct platform_device
*ofdev)
if (sdhci_of_wp_inverted(np))
host-quirks |= SDHCI_QUIRK_INVERTED_WRITE_PROTECT;
+ if (of_device_is_compatible(np, fsl,esdhc))
+ host-quirks |= SDHCI_QUIRK_QORIQ_PROCTL_WEIRD;
+
clk = of_get_property(np, clock-frequency, size);
if (clk size == sizeof(*clk) *clk)
of_host-clock = be32_to_cpup(clk);
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 58d5436..77174e5 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -674,7 +674,7 @@ static void sdhci_set_transfer_irqs(struct sdhci_host *host)
static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command
*cmd)
{
u8 count;
- u8 ctrl;
+ u32 ctrl;
struct mmc_data *data = cmd-data;
int ret;
@@ -807,14 +807,28 @@ static void sdhci_prepare_data(struct sdhci_host *host,
struct mmc_command *cmd)
* is ADMA.
*/
if (host-version = SDHCI_SPEC_200) {
- ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
- ctrl = ~SDHCI_CTRL_DMA_MASK;
- if ((host-flags SDHCI_REQ_USE_DMA)
- (host-flags SDHCI_USE_ADMA))
- ctrl |= SDHCI_CTRL_ADMA32;
- else
- ctrl |= SDHCI_CTRL_SDMA;
- sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+ if (host-quirks SDHCI_QUIRK_QORIQ_PROCTL_WEIRD) {
+#define ESDHCI_PROCTL_DMAS_MASK0x0300
+#define ESDHCI_PROCTL_ADMA32 0x0200
+#define ESDHCI_PROCTL_SDMA 0x
+ ctrl = sdhci_readl(host, SDHCI_HOST_CONTROL);
+ ctrl = ~ESDHCI_PROCTL_DMAS_MASK;
+ if ((host-flags SDHCI_REQ_USE_DMA)
+ (host-flags SDHCI_USE_ADMA))
+ ctrl |= ESDHCI_PROCTL_ADMA32;
+ else
+ ctrl |= ESDHCI_PROCTL_SDMA;
+ sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL);
+ } else {
+ ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
+ ctrl = ~SDHCI_CTRL_DMA_MASK;
+ if ((host-flags SDHCI_REQ_USE_DMA)
+ (host-flags SDHCI_USE_ADMA))
+ ctrl |= SDHCI_CTRL_ADMA32;
+ else
+ ctrl |= SDHCI_CTRL_SDMA;
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+ }
}
if (!(host-flags SDHCI_REQ_USE_DMA)) {
@@ -1138,19 +1152,32 @@ out:
static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
{
u8 pwr = 0;
+ u8 volt = 0;
if (power != (unsigned short)-1) {
switch (1 power) {
+#defineESDHCI_FSL_POWER_MASK 0x40
+#defineESDHCI_FSL_POWER_1800x00
+#defineESDHCI_FSL_POWER_3000x40
case MMC_VDD_165_195:
- pwr = SDHCI_POWER_180;
+ if (host
[PATCH] Add Freescale CodeWarrior debug support for kernel
CodeWarrior is popular embedded tools to support debugging Powerpc.
This patch adds Freescale CodeWarrior debug support for Linux kernel on
85xx/QorIQ platform.
Signed-off-by: Bogdan Adrin drian.bog...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
arch/powerpc/Kconfig.debug|8
arch/powerpc/Makefile |5 +
arch/powerpc/include/asm/reg_booke.h |4
arch/powerpc/kernel/fsl_booke_entry_mapping.S |3 +++
arch/powerpc/kernel/head_fsl_booke.S | 11 +--
arch/powerpc/kernel/idle.c|5 -
6 files changed, 33 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index 2d38a50..eedd2ac 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
@@ -153,6 +153,14 @@ config BDI_SWITCH
Unless you are intending to debug the kernel with one of these
machines, say N here.
+config DEBUG_CODEWARRIOR
+ bool Include CodeWarrior kernel debugging
+ depends on DEBUG_KERNEL PPC32
+ help
+ Say Y here to include CodeWarrior kernel debugging option
+ Unless you are intending to debug the kernel with one of these
+ machines, say N here.
+
config BOOTX_TEXT
bool Support for early boot text console (BootX or OpenFirmware only)
depends on PPC_OF PPC_BOOK3S
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
index b7212b6..d3050e6 100644
--- a/arch/powerpc/Makefile
+++ b/arch/powerpc/Makefile
@@ -121,6 +121,11 @@ KBUILD_CFLAGS += $(call cc-option,-fno-dwarf2-cfi-asm)
# often slow when they are implemented at all
KBUILD_CFLAGS += -mno-string
+ifeq ($(CONFIG_DEBUG_CODEWARRIOR),y)
+CFLAGS += -g2 -gdwarf-2
+AFLAGS_KERNEL += -Wa,-gdwarf2
+endif
+
ifeq ($(CONFIG_6xx),y)
KBUILD_CFLAGS += -mcpu=powerpc
endif
diff --git a/arch/powerpc/include/asm/reg_booke.h
b/arch/powerpc/include/asm/reg_booke.h
index 667a498..ac65fcd 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -35,7 +35,11 @@
#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
#else
+#if defined(CONFIG_DEBUG_CODEWARRIOR)
+#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE|MSR_DE)
+#else
#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE)
+#endif
#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
#endif
diff --git a/arch/powerpc/kernel/fsl_booke_entry_mapping.S
b/arch/powerpc/kernel/fsl_booke_entry_mapping.S
index a92c79b..9102aa7 100644
--- a/arch/powerpc/kernel/fsl_booke_entry_mapping.S
+++ b/arch/powerpc/kernel/fsl_booke_entry_mapping.S
@@ -116,6 +116,9 @@ skpinv: addir6,r6,1 /*
Increment */
xorir6,r4,1
slwir6,r6,5 /* setup new context with other address space */
+#if defined(CONFIG_DEBUG_CODEWARRIOR)
+ ori r6, r6, 0x200 /* enable DE bit for MSR */
+#endif
bl 1f /* Find our address */
1: mflrr9
rlwimi r7,r9,0,20,31
diff --git a/arch/powerpc/kernel/head_fsl_booke.S
b/arch/powerpc/kernel/head_fsl_booke.S
index 529b817..9962d09 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -21,7 +21,7 @@
* debbie_...@mvista.com
*Copyright 2002-2004 MontaVista Software, Inc.
* PowerPC 44x support, Matt Porter mpor...@kernel.crashing.org
- *Copyright 2004 Freescale Semiconductor, Inc
+ *Copyright 2004,2010 Freescale Semiconductor, Inc
* PowerPC e500 modifications, Kumar Gala ga...@kernel.crashing.org
*
* This program is free software; you can redistribute it and/or modify it
@@ -135,7 +135,7 @@ _ENTRY(__early_start)
mtspr SPRN_HID0, r2
#endif
-#if !defined(CONFIG_BDI_SWITCH)
+#if !defined(CONFIG_BDI_SWITCH) !defined(CONFIG_DEBUG_CODEWARRIOR)
/*
* The Abatron BDI JTAG debugger does not tolerate others
* mucking with the debug registers.
@@ -197,6 +197,13 @@ _ENTRY(__early_start)
/*
* Decide what sort of machine this is and initialize the MMU.
*/
+#if defined(CONFIG_DEBUG_CODEWARRIOR)
+ lis r10, 0x1008 /* clear the V bit from the L2MMU_CAM8 register */
+ mtspr SPRN_MAS0, r10
+ lis r10, 0x0
+ mtspr SPRN_MAS1, r10
+ tlbwe
+#endif
mr r3,r31
mr r4,r30
mr r5,r29
diff --git a/arch/powerpc/kernel/idle.c b/arch/powerpc/kernel/idle.c
index 39a2baa..83fb019 100644
--- a/arch/powerpc/kernel/idle.c
+++ b/arch/powerpc/kernel/idle.c
@@ -73,8 +73,11 @@ void cpu_idle(void)
stop_critical_timings();
/* check again after disabling irqs */
- if (!need_resched() !cpu_should_die())
+ if (!need_resched() !cpu_should_die()) {
+#if !defined
[PATCH 1/2] P4080/eLBC: Make Freescale elbc interrupt common to elbc devices
Move Freescale elbc interrupt from nand dirver to elbc driver.
Then all elbc devices can use the interrupt instead of ONLY nand.
For former nand driver, it had the two functions:
1. detecting nand flash partitions;
2. registering elbc interrupt.
Now, second function is removed to fsl_lbc.c.
Signed-off-by: Lan Chunhe-B25806 b25...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
Reviewed-by: Anton Vorontsov cbouatmai...@gmail.com
Cc: Wood Scott-B07421 b07...@freescale.com
---
These two patches are based on the following commits:
1.
http://lists.infradead.org/pipermail/linux-mtd/2010-September/032112.html
2.
http://lists.infradead.org/pipermail/linux-mtd/2010-September/032110.html
3.
http://lists.infradead.org/pipermail/linux-mtd/2010-September/032111.html
According to Anton's comment, I merge 1 2 together and start a new thread.
Comparing the provided link:
1. Merge 1 2 together.
2. Some code style updates
3. Add counter protect for elbc driver remove
4. Rebase to 2.6.36-rc7
Other histories from the links:
V2: Comparing with v1, according to the feedback, add some decorations.
V3: Comparing with v2:
1. according to the feedback, add some decorations.
2. change of_platform_driver to platform_driver
3. rebase to 2.6.36-rc4
V4: Comparing with v3
1. minor fix from type unsigned int to u32
2. fix platform_driver issue.
3. add mutex for nand probe
arch/powerpc/Kconfig |7 +-
arch/powerpc/include/asm/fsl_lbc.h | 33 +++-
arch/powerpc/sysdev/fsl_lbc.c | 229 ++---
drivers/mtd/nand/Kconfig |1 +
drivers/mtd/nand/fsl_elbc_nand.c | 482 +++-
5 files changed, 425 insertions(+), 327 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 631e5a0..44df1ba 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -687,9 +687,12 @@ config 4xx_SOC
bool
config FSL_LBC
- bool
+ bool Freescale Local Bus support
+ depends on FSL_SOC
help
- Freescale Localbus support
+ Enables reporting of errors from the Freescale local bus
+ controller. Also contains some common code used by
+ drivers for specific local bus peripherals.
config FSL_GTM
bool
diff --git a/arch/powerpc/include/asm/fsl_lbc.h
b/arch/powerpc/include/asm/fsl_lbc.h
index 1b5a210..0c40c05 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -1,9 +1,10 @@
/* Freescale Local Bus Controller
*
- * Copyright (c) 2006-2007 Freescale Semiconductor
+ * Copyright (c) 2006-2007, 2010 Freescale Semiconductor
*
* Authors: Nick Spence nick.spe...@freescale.com,
* Scott Wood scottw...@freescale.com
+ * Jack Lan jack@freescale.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -26,6 +27,8 @@
#include linux/compiler.h
#include linux/types.h
#include linux/io.h
+#include linux/device.h
+#include linux/spinlock.h
struct fsl_lbc_bank {
__be32 br; /** Base Register */
@@ -125,13 +128,23 @@ struct fsl_lbc_regs {
#define LTESR_ATMW 0x0080
#define LTESR_ATMR 0x0040
#define LTESR_CS 0x0008
+#define LTESR_UPM 0x0002
#define LTESR_CC 0x0001
#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
+#define LTESR_MASK (LTESR_BM | LTESR_FCT | LTESR_PAR | LTESR_WP \
+| LTESR_ATMW | LTESR_ATMR | LTESR_CS | LTESR_UPM \
+| LTESR_CC)
+#define LTESR_CLEAR0x
+#define LTECCR_CLEAR 0x
+#define LTESR_STATUS LTESR_MASK
+#define LTEIR_ENABLE LTESR_MASK
+#define LTEDR_ENABLE 0x
__be32 ltedr; /** Transfer Error Disable Register */
__be32 lteir; /** Transfer Error Interrupt Register */
__be32 lteatr; /** Transfer Error Attributes Register */
__be32 ltear; /** Transfer Error Address Register */
- u8 res6[0xC];
+ __be32 lteccr; /** Transfer Error ECC Register */
+ u8 res6[0x8];
__be32 lbcr;/** Configuration Register */
#define LBCR_LDIS 0x8000
#define LBCR_LDIS_SHIFT31
@@ -265,7 +278,23 @@ static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
cpu_relax();
}
+/* overview of the fsl lbc controller */
+
+struct fsl_lbc_ctrl {
+ /* device info */
+ struct device *dev;
+ struct fsl_lbc_regs __iomem *regs;
+ int irq;
+ wait_queue_head_t irq_wait;
+ spinlock_t lock;
+ void*nand;
+
+ /* status read from LTESR by irq handler */
+ unsigned intirq_status;
+};
+
extern int
[PATCH 2/2] P4080/mtd: Fix the freescale lbc issue with 36bit mode
From: Lan Chunhe-B25806 b25...@freescale.com
When system uses 36bit physical address, res.start is 36bit
physical address. But the function of in_be32 returns 32bit
physical address. Then both of them compared each other is
wrong. So by converting the address of res.start into
the right format fixes this issue.
Signed-off-by: Lan Chunhe-B25806 b25...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
Reviewed-by: Anton Vorontsov cbouatmai...@gmail.com
---
arch/powerpc/include/asm/fsl_lbc.h |1 +
arch/powerpc/sysdev/fsl_lbc.c | 23 ++-
drivers/mtd/nand/fsl_elbc_nand.c |2 +-
3 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_lbc.h
b/arch/powerpc/include/asm/fsl_lbc.h
index 0c40c05..7639cbd 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -248,6 +248,7 @@ struct fsl_upm {
int width;
};
+extern u32 fsl_lbc_addr(phys_addr_t addr_base);
extern int fsl_lbc_find(phys_addr_t addr_base);
extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm);
diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c
index 4bb0336..29ba867 100644
--- a/arch/powerpc/sysdev/fsl_lbc.c
+++ b/arch/powerpc/sysdev/fsl_lbc.c
@@ -34,6 +34,27 @@ struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
EXPORT_SYMBOL(fsl_lbc_ctrl_dev);
/**
+ * fsl_lbc_addr - convert the base address
+ * @addr_base: base address of the memory bank
+ *
+ * This function converts a base address of lbc into the right format for the
+ * BR register. If the SOC has eLBC then it returns 32bit physical address
+ * else it convers a 34bit local bus physical address to correct format of
+ * 32bit address for BR register (Example: MPC8641).
+ */
+u32 fsl_lbc_addr(phys_addr_t addr_base)
+{
+ struct device_node *np = fsl_lbc_ctrl_dev-dev-of_node;
+ u32 addr = addr_base 0x8000;
+
+ if (of_device_is_compatible(np, fsl,elbc))
+ return addr;
+
+ return addr | ((addr_base 0x3ull) 19);
+}
+EXPORT_SYMBOL(fsl_lbc_addr);
+
+/**
* fsl_lbc_find - find Localbus bank
* @addr_base: base address of the memory bank
*
@@ -55,7 +76,7 @@ int fsl_lbc_find(phys_addr_t addr_base)
__be32 br = in_be32(lbc-bank[i].br);
__be32 or = in_be32(lbc-bank[i].or);
- if (br BR_V (br or BR_BA) == addr_base)
+ if (br BR_V (br or BR_BA) == fsl_lbc_addr(addr_base))
return i;
}
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 400f01f..8785317 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -868,7 +868,7 @@ static int __devinit fsl_elbc_nand_probe(struct
platform_device *pdev)
(in_be32(lbc-bank[bank].br) BR_MSEL) == BR_MS_FCM
(in_be32(lbc-bank[bank].br)
in_be32(lbc-bank[bank].or) BR_BA)
-== res.start)
+== fsl_lbc_addr(res.start))
break;
if (bank = MAX_BANKS) {
--
1.5.6.5
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[PATCH 2/3 v4] P4080/mtd: Only make elbc nand driver detect nand flash partitions
From: Jack Lan jack@freescale.com
The former driver had the two functions:
1. detecting nand flash partitions;
2. registering elbc interrupt.
Now, second function is removed to fsl_lbc.c.
Signed-off-by: Lan Chunhe-B25806 b25...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
drivers/mtd/nand/Kconfig |1 +
drivers/mtd/nand/fsl_elbc_nand.c | 477 +++---
2 files changed, 193 insertions(+), 285 deletions(-)
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 8b4b67c..4132c46 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -458,6 +458,7 @@ config MTD_NAND_ORION
config MTD_NAND_FSL_ELBC
tristate NAND support for Freescale eLBC controllers
depends on PPC_OF
+ select FSL_LBC
help
Various Freescale chips, including the 8313, include a NAND Flash
Controller Module with built-in hardware ECC capabilities.
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 80de0bf..76ffd24 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -1,9 +1,11 @@
/* Freescale Enhanced Local Bus Controller NAND driver
*
- * Copyright (c) 2006-2007 Freescale Semiconductor
+ * Copyright (c) 2006-2007, 2010 Freescale Semiconductor
*
* Authors: Nick Spence nick.spe...@freescale.com,
* Scott Wood scottw...@freescale.com
+ * Jack Lan jack@freescale.com
+ * Roy Zang tie-fei.z...@freescale.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -27,6 +29,7 @@
#include linux/string.h
#include linux/ioport.h
#include linux/of_platform.h
+#include linux/platform_device.h
#include linux/slab.h
#include linux/interrupt.h
@@ -42,14 +45,12 @@
#define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
#define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
-struct fsl_elbc_ctrl;
-
/* mtd information per set */
struct fsl_elbc_mtd {
struct mtd_info mtd;
struct nand_chip chip;
- struct fsl_elbc_ctrl *ctrl;
+ struct fsl_lbc_ctrl *ctrl;
struct device *dev;
int bank; /* Chip select bank number */
@@ -58,18 +59,12 @@ struct fsl_elbc_mtd {
unsigned int fmr; /* FCM Flash Mode Register value */
};
-/* overview of the fsl elbc controller */
+/* Freescale eLBC FCM controller infomation */
-struct fsl_elbc_ctrl {
+struct fsl_elbc_fcm_ctrl {
struct nand_hw_control controller;
struct fsl_elbc_mtd *chips[MAX_BANKS];
- /* device info */
- struct device *dev;
- struct fsl_lbc_regs __iomem *regs;
- int irq;
- wait_queue_head_t irq_wait;
- unsigned int irq_status; /* status read from LTESR by irq handler */
u8 __iomem *addr;/* Address of assigned FCM buffer*/
unsigned int page; /* Last page written to / read from */
unsigned int read_bytes; /* Number of bytes read during command */
@@ -164,11 +159,12 @@ static void set_addr(struct mtd_info *mtd, int column,
int page_addr, int oob)
{
struct nand_chip *chip = mtd-priv;
struct fsl_elbc_mtd *priv = chip-priv;
- struct fsl_elbc_ctrl *ctrl = priv-ctrl;
+ struct fsl_lbc_ctrl *ctrl = priv-ctrl;
struct fsl_lbc_regs __iomem *lbc = ctrl-regs;
+ struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl-nand;
int buf_num;
- ctrl-page = page_addr;
+ elbc_fcm_ctrl-page = page_addr;
out_be32(lbc-fbar,
page_addr (chip-phys_erase_shift - chip-page_shift));
@@ -185,16 +181,18 @@ static void set_addr(struct mtd_info *mtd, int column,
int page_addr, int oob)
buf_num = page_addr 7;
}
- ctrl-addr = priv-vbase + buf_num * 1024;
- ctrl-index = column;
+ elbc_fcm_ctrl-addr = priv-vbase + buf_num * 1024;
+ elbc_fcm_ctrl-index = column;
/* for OOB data point to the second half of the buffer */
if (oob)
- ctrl-index += priv-page_size ? 2048 : 512;
+ elbc_fcm_ctrl-index += priv-page_size ? 2048 : 512;
- dev_vdbg(ctrl-dev, set_addr: bank=%d, ctrl-addr=0x%p (0x%p),
+ dev_vdbg(priv-dev, set_addr: bank=%d,
+ elbc_fcm_ctrl-addr=0x%p (0x%p),
index %x, pes %d ps %d\n,
-buf_num, ctrl-addr, priv-vbase, ctrl-index,
+buf_num, elbc_fcm_ctrl-addr, priv-vbase,
+elbc_fcm_ctrl-index,
chip-phys_erase_shift, chip-page_shift);
}
@@ -205,18 +203,19 @@ static int fsl_elbc_run_command(struct mtd_info *mtd)
{
struct nand_chip *chip = mtd-priv;
struct fsl_elbc_mtd *priv = chip-priv;
- struct fsl_elbc_ctrl *ctrl = priv-ctrl
[PATCH 1/3 v4] P4080/eLBC: Make Freescale elbc interrupt common to elbc devices
From: Lan Chunhe-B25806 b25...@freescale.com
Move Freescale elbc interrupt from nand dirver to elbc driver.
Then all elbc devices can use the interrupt instead of ONLY nand.
Signed-off-by: Lan Chunhe-B25806 b25...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
Comparing v3:
1. minor fix from type unsigned int to u32
2. fix platform_driver issue.
3. add mutex for nand probe
arch/powerpc/Kconfig |7 +-
arch/powerpc/include/asm/fsl_lbc.h | 31 +-
arch/powerpc/sysdev/fsl_lbc.c | 246 ++--
3 files changed, 242 insertions(+), 42 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 631e5a0..44df1ba 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -687,9 +687,12 @@ config 4xx_SOC
bool
config FSL_LBC
- bool
+ bool Freescale Local Bus support
+ depends on FSL_SOC
help
- Freescale Localbus support
+ Enables reporting of errors from the Freescale local bus
+ controller. Also contains some common code used by
+ drivers for specific local bus peripherals.
config FSL_GTM
bool
diff --git a/arch/powerpc/include/asm/fsl_lbc.h
b/arch/powerpc/include/asm/fsl_lbc.h
index 1b5a210..db94698 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -1,9 +1,10 @@
/* Freescale Local Bus Controller
*
- * Copyright (c) 2006-2007 Freescale Semiconductor
+ * Copyright (c) 2006-2007, 2010 Freescale Semiconductor
*
* Authors: Nick Spence nick.spe...@freescale.com,
* Scott Wood scottw...@freescale.com
+ * Jack Lan jack@freescale.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -125,13 +126,23 @@ struct fsl_lbc_regs {
#define LTESR_ATMW 0x0080
#define LTESR_ATMR 0x0040
#define LTESR_CS 0x0008
+#define LTESR_UPM 0x0002
#define LTESR_CC 0x0001
#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
+#define LTESR_MASK (LTESR_BM | LTESR_FCT | LTESR_PAR | LTESR_WP \
+| LTESR_ATMW | LTESR_ATMR | LTESR_CS | LTESR_UPM \
+| LTESR_CC)
+#define LTESR_CLEAR0x
+#define LTECCR_CLEAR 0x
+#define LTESR_STATUS LTESR_MASK
+#define LTEIR_ENABLE LTESR_MASK
+#define LTEDR_ENABLE 0x
__be32 ltedr; /** Transfer Error Disable Register */
__be32 lteir; /** Transfer Error Interrupt Register */
__be32 lteatr; /** Transfer Error Attributes Register */
__be32 ltear; /** Transfer Error Address Register */
- u8 res6[0xC];
+ __be32 lteccr; /** Transfer Error ECC Register */
+ u8 res6[0x8];
__be32 lbcr;/** Configuration Register */
#define LBCR_LDIS 0x8000
#define LBCR_LDIS_SHIFT31
@@ -265,7 +276,23 @@ static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
cpu_relax();
}
+/* overview of the fsl lbc controller */
+
+struct fsl_lbc_ctrl {
+ /* device info */
+ struct device *dev;
+ struct fsl_lbc_regs __iomem *regs;
+ int irq;
+ wait_queue_head_t irq_wait;
+ spinlock_t lock;
+ void*nand;
+
+ /* status read from LTESR by irq handler */
+ unsigned intirq_status;
+};
+
extern int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base,
u32 mar);
+extern struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
#endif /* __ASM_FSL_LBC_H */
diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c
index dceb8d1..4920cd3 100644
--- a/arch/powerpc/sysdev/fsl_lbc.c
+++ b/arch/powerpc/sysdev/fsl_lbc.c
@@ -2,8 +2,11 @@
* Freescale LBC and UPM routines.
*
* Copyright (c) 2007-2008 MontaVista Software, Inc.
+ * Copyright (c) 2010 Freescale Semiconductor
*
* Author: Anton Vorontsov avoront...@ru.mvista.com
+ * Author: Jack Lan jack@freescale.com
+ * Author: Roy Zang tie-fei.z...@freescale.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -21,37 +24,14 @@
#include linux/of.h
#include asm/prom.h
#include asm/fsl_lbc.h
+#include linux/slab.h
+#include linux/of_platform.h
+#include linux/platform_device.h
+#include linux/interrupt.h
static spinlock_t fsl_lbc_lock = __SPIN_LOCK_UNLOCKED(fsl_lbc_lock);
-static struct fsl_lbc_regs __iomem *fsl_lbc_regs;
-
-static char __initdata *compat_lbc[] = {
- fsl,pq2-localbus,
- fsl,pq2pro-localbus,
- fsl,pq3-localbus,
- fsl,elbc,
-};
-
-static int __init fsl_lbc_init(void)
-{
- struct device_node *lbus;
- int i
[PATCH 3/3 v4] P4080/mtd: Fix the freescale lbc issue with 36bit mode
From: Lan Chunhe-B25806 b25...@freescale.com
When system uses 36bit physical address, res.start is 36bit
physical address. But the function of in_be32 returns 32bit
physical address. Then both of them compared each other is
wrong. So by converting the address of res.start into
the right format fixes this issue.
Signed-off-by: Lan Chunhe-B25806 b25...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
Reviewed-by: Anton Vorontsov cbouatmai...@gmail.com
---
arch/powerpc/include/asm/fsl_lbc.h |1 +
arch/powerpc/sysdev/fsl_lbc.c | 23 ++-
drivers/mtd/nand/fsl_elbc_nand.c |2 +-
3 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_lbc.h
b/arch/powerpc/include/asm/fsl_lbc.h
index db94698..ad663e8 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -246,6 +246,7 @@ struct fsl_upm {
int width;
};
+extern u32 fsl_lbc_addr(phys_addr_t addr_base);
extern int fsl_lbc_find(phys_addr_t addr_base);
extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm);
diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c
index 4920cd3..32c2120 100644
--- a/arch/powerpc/sysdev/fsl_lbc.c
+++ b/arch/powerpc/sysdev/fsl_lbc.c
@@ -34,6 +34,27 @@ struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
EXPORT_SYMBOL(fsl_lbc_ctrl_dev);
/**
+ * fsl_lbc_addr - convert the base address
+ * @addr_base: base address of the memory bank
+ *
+ * This function converts a base address of lbc into the right format for the
+ * BR register. If the SOC has eLBC then it returns 32bit physical address
+ * else it convers a 34bit local bus physical address to correct format of
+ * 32bit address for BR register (Example: MPC8641).
+ */
+u32 fsl_lbc_addr(phys_addr_t addr_base)
+{
+ struct device_node *np = fsl_lbc_ctrl_dev-dev-of_node;
+ u32 addr = addr_base 0x8000;
+
+ if (of_device_is_compatible(np, fsl,elbc))
+ return addr;
+
+ return addr | ((addr_base 0x3ull) 19);
+}
+EXPORT_SYMBOL(fsl_lbc_addr);
+
+/**
* fsl_lbc_find - find Localbus bank
* @addr_base: base address of the memory bank
*
@@ -55,7 +76,7 @@ int fsl_lbc_find(phys_addr_t addr_base)
__be32 br = in_be32(lbc-bank[i].br);
__be32 or = in_be32(lbc-bank[i].or);
- if (br BR_V (br or BR_BA) == addr_base)
+ if (br BR_V (br or BR_BA) == fsl_lbc_addr(addr_base))
return i;
}
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 76ffd24..227618b 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -865,7 +865,7 @@ static int __devinit fsl_elbc_nand_probe(struct
platform_device *dev)
(in_be32(lbc-bank[bank].br) BR_MSEL) == BR_MS_FCM
(in_be32(lbc-bank[bank].br)
in_be32(lbc-bank[bank].or) BR_BA)
-== res.start)
+== fsl_lbc_addr(res.start))
break;
if (bank = MAX_BANKS) {
--
1.5.6.5
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[PATCH 2/3 v3] P4080/mtd: Only make elbc nand driver detect nand flash partitions
From: Jack Lan jack@freescale.com
The former driver had the two functions:
1. detecting nand flash partitions;
2. registering elbc interrupt.
Now, second function is removed to fsl_lbc.c.
Signed-off-by: Lan Chunhe-B25806 b25...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
drivers/mtd/nand/Kconfig |1 +
drivers/mtd/nand/fsl_elbc_nand.c | 474 +++---
2 files changed, 190 insertions(+), 285 deletions(-)
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 8b4b67c..4132c46 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -458,6 +458,7 @@ config MTD_NAND_ORION
config MTD_NAND_FSL_ELBC
tristate NAND support for Freescale eLBC controllers
depends on PPC_OF
+ select FSL_LBC
help
Various Freescale chips, including the 8313, include a NAND Flash
Controller Module with built-in hardware ECC capabilities.
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 80de0bf..91c5c05 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -1,9 +1,10 @@
/* Freescale Enhanced Local Bus Controller NAND driver
*
- * Copyright (c) 2006-2007 Freescale Semiconductor
+ * Copyright (c) 2006-2007, 2010 Freescale Semiconductor
*
* Authors: Nick Spence nick.spe...@freescale.com,
* Scott Wood scottw...@freescale.com
+ * Jack Lan jack@freescale.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -27,6 +28,7 @@
#include linux/string.h
#include linux/ioport.h
#include linux/of_platform.h
+#include linux/platform_device.h
#include linux/slab.h
#include linux/interrupt.h
@@ -42,14 +44,12 @@
#define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
#define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
-struct fsl_elbc_ctrl;
-
/* mtd information per set */
struct fsl_elbc_mtd {
struct mtd_info mtd;
struct nand_chip chip;
- struct fsl_elbc_ctrl *ctrl;
+ struct fsl_lbc_ctrl *ctrl;
struct device *dev;
int bank; /* Chip select bank number */
@@ -58,18 +58,12 @@ struct fsl_elbc_mtd {
unsigned int fmr; /* FCM Flash Mode Register value */
};
-/* overview of the fsl elbc controller */
+/* Freescale eLBC FCM controller infomation */
-struct fsl_elbc_ctrl {
+struct fsl_elbc_fcm_ctrl {
struct nand_hw_control controller;
struct fsl_elbc_mtd *chips[MAX_BANKS];
- /* device info */
- struct device *dev;
- struct fsl_lbc_regs __iomem *regs;
- int irq;
- wait_queue_head_t irq_wait;
- unsigned int irq_status; /* status read from LTESR by irq handler */
u8 __iomem *addr;/* Address of assigned FCM buffer*/
unsigned int page; /* Last page written to / read from */
unsigned int read_bytes; /* Number of bytes read during command */
@@ -164,11 +158,12 @@ static void set_addr(struct mtd_info *mtd, int column,
int page_addr, int oob)
{
struct nand_chip *chip = mtd-priv;
struct fsl_elbc_mtd *priv = chip-priv;
- struct fsl_elbc_ctrl *ctrl = priv-ctrl;
+ struct fsl_lbc_ctrl *ctrl = priv-ctrl;
struct fsl_lbc_regs __iomem *lbc = ctrl-regs;
+ struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl-nand;
int buf_num;
- ctrl-page = page_addr;
+ elbc_fcm_ctrl-page = page_addr;
out_be32(lbc-fbar,
page_addr (chip-phys_erase_shift - chip-page_shift));
@@ -185,16 +180,18 @@ static void set_addr(struct mtd_info *mtd, int column,
int page_addr, int oob)
buf_num = page_addr 7;
}
- ctrl-addr = priv-vbase + buf_num * 1024;
- ctrl-index = column;
+ elbc_fcm_ctrl-addr = priv-vbase + buf_num * 1024;
+ elbc_fcm_ctrl-index = column;
/* for OOB data point to the second half of the buffer */
if (oob)
- ctrl-index += priv-page_size ? 2048 : 512;
+ elbc_fcm_ctrl-index += priv-page_size ? 2048 : 512;
- dev_vdbg(ctrl-dev, set_addr: bank=%d, ctrl-addr=0x%p (0x%p),
+ dev_vdbg(priv-dev, set_addr: bank=%d,
+ elbc_fcm_ctrl-addr=0x%p (0x%p),
index %x, pes %d ps %d\n,
-buf_num, ctrl-addr, priv-vbase, ctrl-index,
+buf_num, elbc_fcm_ctrl-addr, priv-vbase,
+elbc_fcm_ctrl-index,
chip-phys_erase_shift, chip-page_shift);
}
@@ -205,18 +202,19 @@ static int fsl_elbc_run_command(struct mtd_info *mtd)
{
struct nand_chip *chip = mtd-priv;
struct fsl_elbc_mtd *priv = chip-priv;
- struct fsl_elbc_ctrl *ctrl = priv-ctrl;
+ struct fsl_lbc_ctrl *ctrl = priv-ctrl
[PATCH 1/3 v3] P4080/eLBC: Make Freescale elbc interrupt common to elbc devices
From: Lan Chunhe-B25806 b25...@freescale.com
Move Freescale elbc interrupt from nand dirver to elbc driver.
Then all elbc devices can use the interrupt instead of ONLY nand.
Signed-off-by: Lan Chunhe-B25806 b25...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
Comparing with v2:
1. according to the feedback, add some decorations.
2. change of_platform_driver to platform_driver
3. rebase to 2.6.36-rc4
arch/powerpc/Kconfig |7 +-
arch/powerpc/include/asm/fsl_lbc.h | 31 +-
arch/powerpc/sysdev/fsl_lbc.c | 246 ++--
3 files changed, 242 insertions(+), 42 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 631e5a0..44df1ba 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -687,9 +687,12 @@ config 4xx_SOC
bool
config FSL_LBC
- bool
+ bool Freescale Local Bus support
+ depends on FSL_SOC
help
- Freescale Localbus support
+ Enables reporting of errors from the Freescale local bus
+ controller. Also contains some common code used by
+ drivers for specific local bus peripherals.
config FSL_GTM
bool
diff --git a/arch/powerpc/include/asm/fsl_lbc.h
b/arch/powerpc/include/asm/fsl_lbc.h
index 1b5a210..db94698 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -1,9 +1,10 @@
/* Freescale Local Bus Controller
*
- * Copyright (c) 2006-2007 Freescale Semiconductor
+ * Copyright (c) 2006-2007, 2010 Freescale Semiconductor
*
* Authors: Nick Spence nick.spe...@freescale.com,
* Scott Wood scottw...@freescale.com
+ * Jack Lan jack@freescale.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -125,13 +126,23 @@ struct fsl_lbc_regs {
#define LTESR_ATMW 0x0080
#define LTESR_ATMR 0x0040
#define LTESR_CS 0x0008
+#define LTESR_UPM 0x0002
#define LTESR_CC 0x0001
#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
+#define LTESR_MASK (LTESR_BM | LTESR_FCT | LTESR_PAR | LTESR_WP \
+| LTESR_ATMW | LTESR_ATMR | LTESR_CS | LTESR_UPM \
+| LTESR_CC)
+#define LTESR_CLEAR0x
+#define LTECCR_CLEAR 0x
+#define LTESR_STATUS LTESR_MASK
+#define LTEIR_ENABLE LTESR_MASK
+#define LTEDR_ENABLE 0x
__be32 ltedr; /** Transfer Error Disable Register */
__be32 lteir; /** Transfer Error Interrupt Register */
__be32 lteatr; /** Transfer Error Attributes Register */
__be32 ltear; /** Transfer Error Address Register */
- u8 res6[0xC];
+ __be32 lteccr; /** Transfer Error ECC Register */
+ u8 res6[0x8];
__be32 lbcr;/** Configuration Register */
#define LBCR_LDIS 0x8000
#define LBCR_LDIS_SHIFT31
@@ -265,7 +276,23 @@ static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
cpu_relax();
}
+/* overview of the fsl lbc controller */
+
+struct fsl_lbc_ctrl {
+ /* device info */
+ struct device *dev;
+ struct fsl_lbc_regs __iomem *regs;
+ int irq;
+ wait_queue_head_t irq_wait;
+ spinlock_t lock;
+ void*nand;
+
+ /* status read from LTESR by irq handler */
+ unsigned intirq_status;
+};
+
extern int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base,
u32 mar);
+extern struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
#endif /* __ASM_FSL_LBC_H */
diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c
index dceb8d1..edd6d95 100644
--- a/arch/powerpc/sysdev/fsl_lbc.c
+++ b/arch/powerpc/sysdev/fsl_lbc.c
@@ -2,8 +2,11 @@
* Freescale LBC and UPM routines.
*
* Copyright (c) 2007-2008 MontaVista Software, Inc.
+ * Copyright (c) 2010 Freescale Semiconductor
*
* Author: Anton Vorontsov avoront...@ru.mvista.com
+ * Author: Jack Lan jack@freescale.com
+ * Author: Roy Zang tie-fei.z...@freescale.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -21,37 +24,14 @@
#include linux/of.h
#include asm/prom.h
#include asm/fsl_lbc.h
+#include linux/slab.h
+#include linux/of_platform.h
+#include linux/platform_device.h
+#include linux/interrupt.h
static spinlock_t fsl_lbc_lock = __SPIN_LOCK_UNLOCKED(fsl_lbc_lock);
-static struct fsl_lbc_regs __iomem *fsl_lbc_regs;
-
-static char __initdata *compat_lbc[] = {
- fsl,pq2-localbus,
- fsl,pq2pro-localbus,
- fsl,pq3-localbus,
- fsl,elbc,
-};
-
-static int __init fsl_lbc_init(void)
-{
- struct
[PATCH 3/3 v3] P4080/mtd: Fix the freescale lbc issue with 36bit mode
From: Lan Chunhe-B25806 b25...@freescale.com
When system uses 36bit physical address, res.start is 36bit
physical address. But the function of in_be32 returns 32bit
physical address. Then both of them compared each other is
wrong. So by converting the address of res.start into
the right format fixes this issue.
Signed-off-by: Lan Chunhe-B25806 b25...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
arch/powerpc/include/asm/fsl_lbc.h |1 +
arch/powerpc/sysdev/fsl_lbc.c | 23 ++-
drivers/mtd/nand/fsl_elbc_nand.c |2 +-
3 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_lbc.h
b/arch/powerpc/include/asm/fsl_lbc.h
index db94698..5638b1e 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -246,6 +246,7 @@ struct fsl_upm {
int width;
};
+extern unsigned int fsl_lbc_addr(phys_addr_t addr_base);
extern int fsl_lbc_find(phys_addr_t addr_base);
extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm);
diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c
index edd6d95..8a835ef 100644
--- a/arch/powerpc/sysdev/fsl_lbc.c
+++ b/arch/powerpc/sysdev/fsl_lbc.c
@@ -34,6 +34,27 @@ struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
EXPORT_SYMBOL(fsl_lbc_ctrl_dev);
/**
+ * fsl_lbc_addr - convert the base address
+ * @addr_base: base address of the memory bank
+ *
+ * This function converts a base address of lbc into the right format for the
+ * BR register. If the SOC has eLBC then it returns 32bit physical address
+ * else it convers a 34bit local bus physical address to correct format of
+ * 32bit address for BR register (Example: MPC8641).
+ */
+u32 fsl_lbc_addr(phys_addr_t addr_base)
+{
+ struct device_node *np = fsl_lbc_ctrl_dev-dev-of_node;
+ u32 addr = addr_base 0x8000;
+
+ if (of_device_is_compatible(np, fsl,elbc))
+ return addr;
+
+ return addr | ((addr_base 0x3ull) 19);
+}
+EXPORT_SYMBOL(fsl_lbc_addr);
+
+/**
* fsl_lbc_find - find Localbus bank
* @addr_base: base address of the memory bank
*
@@ -55,7 +76,7 @@ int fsl_lbc_find(phys_addr_t addr_base)
__be32 br = in_be32(lbc-bank[i].br);
__be32 or = in_be32(lbc-bank[i].or);
- if (br BR_V (br or BR_BA) == addr_base)
+ if (br BR_V (br or BR_BA) == fsl_lbc_addr(addr_base))
return i;
}
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 91c5c05..85858e3 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -865,7 +865,7 @@ static int __devinit fsl_elbc_nand_probe(struct
platform_device *dev)
(in_be32(lbc-bank[bank].br) BR_MSEL) == BR_MS_FCM
(in_be32(lbc-bank[bank].br)
in_be32(lbc-bank[bank].or) BR_BA)
-== res.start)
+== fsl_lbc_addr(res.start))
break;
if (bank = MAX_BANKS) {
--
1.5.6.5
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/dts: add interrupt parent for lbc node for p4080
Signed-off-by: Roy Zang tie-fei.z...@freescale.com --- arch/powerpc/boot/dts/p4080ds.dts |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/boot/dts/p4080ds.dts b/arch/powerpc/boot/dts/p4080ds.dts index 2f0de24..0a18138 100644 --- a/arch/powerpc/boot/dts/p4080ds.dts +++ b/arch/powerpc/boot/dts/p4080ds.dts @@ -431,6 +431,7 @@ compatible = fsl,p4080-elbc, fsl,elbc, simple-bus; reg = 0xf 0xfe124000 0 0x1000; interrupts = 25 2; + interrupt-parent = mpic; #address-cells = 2; #size-cells = 1; -- 1.5.6.5 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/3 v2][MTD] P4080/eLBC: Make Freescale elbc interrupt common to elbc devices
From: Lan Chunhe-B25806 b25...@freescale.com
Move Freescale elbc interrupt from nand dirver to elbc driver.
Then all elbc devices can use the interrupt instead of ONLY nand.
Signed-off-by: Lan Chunhe-B25806 b25...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
Comparing with v1, according to the feedback, add some decorations.
arch/powerpc/Kconfig |7 +-
arch/powerpc/include/asm/fsl_lbc.h | 34 +-
arch/powerpc/sysdev/fsl_lbc.c | 248 ++--
3 files changed, 247 insertions(+), 42 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 631e5a0..44df1ba 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -687,9 +687,12 @@ config 4xx_SOC
bool
config FSL_LBC
- bool
+ bool Freescale Local Bus support
+ depends on FSL_SOC
help
- Freescale Localbus support
+ Enables reporting of errors from the Freescale local bus
+ controller. Also contains some common code used by
+ drivers for specific local bus peripherals.
config FSL_GTM
bool
diff --git a/arch/powerpc/include/asm/fsl_lbc.h
b/arch/powerpc/include/asm/fsl_lbc.h
index 1b5a210..9b95eab 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -1,9 +1,10 @@
/* Freescale Local Bus Controller
*
- * Copyright (c) 2006-2007 Freescale Semiconductor
+ * Copyright (c) 2006-2007, 2010 Freescale Semiconductor
*
* Authors: Nick Spence nick.spe...@freescale.com,
* Scott Wood scottw...@freescale.com
+ * Jack Lan jack@freescale.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -27,6 +28,9 @@
#include linux/types.h
#include linux/io.h
+#include linux/of_platform.h
+#include linux/interrupt.h
+
struct fsl_lbc_bank {
__be32 br; /** Base Register */
#define BR_BA 0x8000
@@ -125,13 +129,23 @@ struct fsl_lbc_regs {
#define LTESR_ATMW 0x0080
#define LTESR_ATMR 0x0040
#define LTESR_CS 0x0008
+#define LTESR_UPM 0x0002
#define LTESR_CC 0x0001
#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
+#define LTESR_MASK (LTESR_BM | LTESR_FCT | LTESR_PAR | LTESR_WP \
+| LTESR_ATMW | LTESR_ATMR | LTESR_CS | LTESR_UPM \
+| LTESR_CC)
+#define LTESR_CLEAR0x
+#define LTECCR_CLEAR 0x
+#define LTESR_STATUS LTESR_MASK
+#define LTEIR_ENABLE LTESR_MASK
+#define LTEDR_ENABLE 0x
__be32 ltedr; /** Transfer Error Disable Register */
__be32 lteir; /** Transfer Error Interrupt Register */
__be32 lteatr; /** Transfer Error Attributes Register */
__be32 ltear; /** Transfer Error Address Register */
- u8 res6[0xC];
+ __be32 lteccr; /** Transfer Error ECC Register */
+ u8 res6[0x8];
__be32 lbcr;/** Configuration Register */
#define LBCR_LDIS 0x8000
#define LBCR_LDIS_SHIFT31
@@ -265,7 +279,23 @@ static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
cpu_relax();
}
+/* overview of the fsl lbc controller */
+
+struct fsl_lbc_ctrl {
+ /* device info */
+ struct device *dev;
+ struct fsl_lbc_regs __iomem *regs;
+ int irq;
+ wait_queue_head_t irq_wait;
+ spinlock_t lock;
+ void*nand;
+
+ /* status read from LTESR by irq handler */
+ unsigned intirq_status;
+};
+
extern int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base,
u32 mar);
+extern struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
#endif /* __ASM_FSL_LBC_H */
diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c
index dceb8d1..f4eca8d 100644
--- a/arch/powerpc/sysdev/fsl_lbc.c
+++ b/arch/powerpc/sysdev/fsl_lbc.c
@@ -2,8 +2,11 @@
* Freescale LBC and UPM routines.
*
* Copyright (c) 2007-2008 MontaVista Software, Inc.
+ * Copyright (c) 2010 Freescale Semiconductor
*
* Author: Anton Vorontsov avoront...@ru.mvista.com
+ * Author: Jack Lan jack@freescale.com
+ * Author: Roy Zang tie-fei.z...@freescale.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -21,37 +24,11 @@
#include linux/of.h
#include asm/prom.h
#include asm/fsl_lbc.h
+#include linux/slab.h
static spinlock_t fsl_lbc_lock = __SPIN_LOCK_UNLOCKED(fsl_lbc_lock);
-static struct fsl_lbc_regs __iomem *fsl_lbc_regs;
-
-static char __initdata *compat_lbc[] = {
- fsl,pq2-localbus,
- fsl,pq2pro-localbus,
- fsl,pq3-localbus,
- fsl,elbc
[PATCH 2/3 v2][MTD] P4080/mtd: Only make elbc nand driver detect nand flash partitions
From: Jack Lan jack@freescale.com
The former driver had the two functions:
1. detecting nand flash partitions;
2. registering elbc interrupt.
Now, second function is removed to fsl_lbc.c.
Signed-off-by: Lan Chunhe-B25806 b25...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
Comparing with v1, according to the feedback, remove global variables.
drivers/mtd/nand/Kconfig |1 +
drivers/mtd/nand/fsl_elbc_nand.c | 476 +++---
2 files changed, 183 insertions(+), 294 deletions(-)
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 8b4b67c..4132c46 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -458,6 +458,7 @@ config MTD_NAND_ORION
config MTD_NAND_FSL_ELBC
tristate NAND support for Freescale eLBC controllers
depends on PPC_OF
+ select FSL_LBC
help
Various Freescale chips, including the 8313, include a NAND Flash
Controller Module with built-in hardware ECC capabilities.
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 80de0bf..64c840f 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -1,9 +1,10 @@
/* Freescale Enhanced Local Bus Controller NAND driver
*
- * Copyright (c) 2006-2007 Freescale Semiconductor
+ * Copyright (c) 2006-2007, 2010 Freescale Semiconductor
*
* Authors: Nick Spence nick.spe...@freescale.com,
* Scott Wood scottw...@freescale.com
+ * Jack Lan jack@freescale.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -24,32 +25,22 @@
#include linux/types.h
#include linux/init.h
#include linux/kernel.h
-#include linux/string.h
-#include linux/ioport.h
-#include linux/of_platform.h
-#include linux/slab.h
-#include linux/interrupt.h
-#include linux/mtd/mtd.h
#include linux/mtd/nand.h
-#include linux/mtd/nand_ecc.h
#include linux/mtd/partitions.h
-
-#include asm/io.h
#include asm/fsl_lbc.h
+#include linux/slab.h
#define MAX_BANKS 8
#define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
#define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
-struct fsl_elbc_ctrl;
-
/* mtd information per set */
struct fsl_elbc_mtd {
struct mtd_info mtd;
struct nand_chip chip;
- struct fsl_elbc_ctrl *ctrl;
+ struct fsl_lbc_ctrl *ctrl;
struct device *dev;
int bank; /* Chip select bank number */
@@ -58,18 +49,12 @@ struct fsl_elbc_mtd {
unsigned int fmr; /* FCM Flash Mode Register value */
};
-/* overview of the fsl elbc controller */
+/* Freescale eLBC FCM controller infomation */
-struct fsl_elbc_ctrl {
+struct fsl_elbc_fcm_ctrl {
struct nand_hw_control controller;
struct fsl_elbc_mtd *chips[MAX_BANKS];
- /* device info */
- struct device *dev;
- struct fsl_lbc_regs __iomem *regs;
- int irq;
- wait_queue_head_t irq_wait;
- unsigned int irq_status; /* status read from LTESR by irq handler */
u8 __iomem *addr;/* Address of assigned FCM buffer*/
unsigned int page; /* Last page written to / read from */
unsigned int read_bytes; /* Number of bytes read during command */
@@ -164,11 +149,12 @@ static void set_addr(struct mtd_info *mtd, int column,
int page_addr, int oob)
{
struct nand_chip *chip = mtd-priv;
struct fsl_elbc_mtd *priv = chip-priv;
- struct fsl_elbc_ctrl *ctrl = priv-ctrl;
+ struct fsl_lbc_ctrl *ctrl = priv-ctrl;
struct fsl_lbc_regs __iomem *lbc = ctrl-regs;
+ struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl-nand;
int buf_num;
- ctrl-page = page_addr;
+ elbc_fcm_ctrl-page = page_addr;
out_be32(lbc-fbar,
page_addr (chip-phys_erase_shift - chip-page_shift));
@@ -185,16 +171,18 @@ static void set_addr(struct mtd_info *mtd, int column,
int page_addr, int oob)
buf_num = page_addr 7;
}
- ctrl-addr = priv-vbase + buf_num * 1024;
- ctrl-index = column;
+ elbc_fcm_ctrl-addr = priv-vbase + buf_num * 1024;
+ elbc_fcm_ctrl-index = column;
/* for OOB data point to the second half of the buffer */
if (oob)
- ctrl-index += priv-page_size ? 2048 : 512;
+ elbc_fcm_ctrl-index += priv-page_size ? 2048 : 512;
- dev_vdbg(ctrl-dev, set_addr: bank=%d, ctrl-addr=0x%p (0x%p),
+ dev_vdbg(priv-dev, set_addr: bank=%d,
+ elbc_fcm_ctrl-addr=0x%p (0x%p),
index %x, pes %d ps %d\n,
-buf_num, ctrl-addr, priv-vbase, ctrl-index,
+buf_num, elbc_fcm_ctrl-addr, priv-vbase,
+elbc_fcm_ctrl-index,
chip
[PATCH v2 3/3][MTD] P4080/mtd: Fix the freescale lbc issue with 36bit mode
From: Lan Chunhe-B25806 b25...@freescale.com
When system uses 36bit physical address, res.start is 36bit
physical address. But the function of in_be32 returns 32bit
physical address. Then both of them compared each other is
wrong. So by converting the address of res.start into
the right format fixes this issue.
Signed-off-by: Lan Chunhe-B25806 b25...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
Comparing with v1, according to the feedback, add some decorations.
arch/powerpc/include/asm/fsl_lbc.h |1 +
arch/powerpc/sysdev/fsl_lbc.c | 26 +-
drivers/mtd/nand/fsl_elbc_nand.c |2 +-
3 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_lbc.h
b/arch/powerpc/include/asm/fsl_lbc.h
index 9b95eab..bff85c8 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -249,6 +249,7 @@ struct fsl_upm {
int width;
};
+extern unsigned int fsl_lbc_addr(phys_addr_t addr_base);
extern int fsl_lbc_find(phys_addr_t addr_base);
extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm);
diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c
index f4eca8d..3a09e90 100644
--- a/arch/powerpc/sysdev/fsl_lbc.c
+++ b/arch/powerpc/sysdev/fsl_lbc.c
@@ -31,6 +31,30 @@ struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
EXPORT_SYMBOL(fsl_lbc_ctrl_dev);
/**
+ * fsl_lbc_addr - convert the base address
+ * @addr_base: base address of the memory bank
+ *
+ * This function converts a base address of lbc into the right format for the
BR
+ * registers. If the SOC has eLBC then it returns 32bit physical address else
+ * it returns 34bit physical address for local bus(Example: MPC8641).
+ */
+unsigned int fsl_lbc_addr(phys_addr_t addr_base)
+{
+ void *dev;
+ int compatible;
+
+ dev = fsl_lbc_ctrl_dev-dev-of_node;
+ compatible = of_device_is_compatible(dev, fsl,elbc);
+
+ if (compatible)
+ return addr_base 0x8000;
+ else
+ return (addr_base 0x08000ull)
+ | ((addr_base 0x3ull) 19);
+}
+EXPORT_SYMBOL(fsl_lbc_addr);
+
+/**
* fsl_lbc_find - find Localbus bank
* @addr_base: base address of the memory bank
*
@@ -52,7 +76,7 @@ int fsl_lbc_find(phys_addr_t addr_base)
__be32 br = in_be32(lbc-bank[i].br);
__be32 or = in_be32(lbc-bank[i].or);
- if (br BR_V (br or BR_BA) == addr_base)
+ if (br BR_V (br or BR_BA) == fsl_lbc_addr(addr_base))
return i;
}
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 64c840f..6dec268 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -851,7 +851,7 @@ static int __devinit fsl_elbc_nand_probe(struct
platform_device *dev,
(in_be32(lbc-bank[bank].br) BR_MSEL) == BR_MS_FCM
(in_be32(lbc-bank[bank].br)
in_be32(lbc-bank[bank].or) BR_BA)
-== res.start)
+== fsl_lbc_addr(res.start))
break;
if (bank = MAX_BANKS) {
--
1.5.6.5
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[PATCH 1/2] mmc: change ACMD12 to AUTO_CMD12 for more clear
Change ACMD12 to AUTO_CMD12 to reduce the confusion.
ACMD12 might be confused with MMC/SD App CMD 12 (CMD55+CMD12 combo).
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
drivers/mmc/host/sdhci-of-core.c |2 +-
drivers/mmc/host/sdhci.c |8
drivers/mmc/host/sdhci.h | 10 +-
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-core.c b/drivers/mmc/host/sdhci-of-core.c
index dd1bdd1..d059805 100644
--- a/drivers/mmc/host/sdhci-of-core.c
+++ b/drivers/mmc/host/sdhci-of-core.c
@@ -155,7 +155,7 @@ static int __devinit sdhci_of_probe(struct of_device *ofdev,
}
if (of_get_property(np, sdhci,auto-cmd12, NULL))
- host-quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
+ host-quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_AUTO_CMD12;
if (of_get_property(np, sdhci,1-bit-only, NULL))
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index a92566e..4b7b2d5 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -73,7 +73,7 @@ static void sdhci_dumpregs(struct sdhci_host *host)
sdhci_readl(host, SDHCI_INT_ENABLE),
sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
printk(KERN_DEBUG DRIVER_NAME : AC12 err: 0x%08x | Slot int: 0x%08x\n,
- sdhci_readw(host, SDHCI_ACMD12_ERR),
+ sdhci_readw(host, SDHCI_AUTO_CMD12_ERR),
sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
printk(KERN_DEBUG DRIVER_NAME : Caps: 0x%08x | Max curr: 0x%08x\n,
sdhci_readl(host, SDHCI_CAPABILITIES),
@@ -818,8 +818,8 @@ static void sdhci_set_transfer_mode(struct sdhci_host *host,
mode = SDHCI_TRNS_BLK_CNT_EN;
if (data-blocks 1) {
- if (host-quirks SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
- mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_ACMD12;
+ if (host-quirks SDHCI_QUIRK_MULTIBLOCK_READ_AUTO_CMD12)
+ mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_AUTO_CMD12;
else
mode |= SDHCI_TRNS_MULTI;
}
@@ -1112,7 +1112,7 @@ static void sdhci_request(struct mmc_host *mmc, struct
mmc_request *mrq)
#ifndef SDHCI_USE_LEDS_CLASS
sdhci_activate_led(host);
#endif
- if (host-quirks SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) {
+ if (host-quirks SDHCI_QUIRK_MULTIBLOCK_READ_AUTO_CMD12) {
if (mrq-stop) {
mrq-data-stop = NULL;
mrq-stop = NULL;
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 8fb088c..dfe1c4a 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -32,7 +32,7 @@
#define SDHCI_TRANSFER_MODE0x0C
#define SDHCI_TRNS_DMA0x01
#define SDHCI_TRNS_BLK_CNT_EN 0x02
-#define SDHCI_TRNS_ACMD12 0x04
+#define SDHCI_TRNS_AUTO_CMD12 0x04
#define SDHCI_TRNS_READ 0x10
#define SDHCI_TRNS_MULTI 0x20
@@ -116,7 +116,7 @@
#define SDHCI_INT_DATA_CRC0x0020
#define SDHCI_INT_DATA_END_BIT0x0040
#define SDHCI_INT_BUS_POWER 0x0080
-#define SDHCI_INT_ACMD12ERR 0x0100
+#define SDHCI_INT_AUTO_CMD12_ERR 0x0100
#define SDHCI_INT_ADMA_ERROR 0x0200
#define SDHCI_INT_NORMAL_MASK 0x7FFF
@@ -130,7 +130,7 @@
SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
-#define SDHCI_ACMD12_ERR 0x3C
+#define SDHCI_AUTO_CMD12_ERR 0x3C
/* 3E-3F reserved */
@@ -157,7 +157,7 @@
/* 4C-4F reserved for more max current */
-#define SDHCI_SET_ACMD12_ERROR 0x50
+#define SDHCI_SET_AUTO_CMD12_ERROR 0x50
#define SDHCI_SET_INT_ERROR0x52
#define SDHCI_ADMA_ERROR 0x54
@@ -241,7 +241,7 @@ struct sdhci_host {
/* Controller cannot support End Attribute in NOP ADMA descriptor */
#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (126)
/* Controller uses Auto CMD12 command to stop the transfer */
-#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (127)
+#define SDHCI_QUIRK_MULTIBLOCK_READ_AUTO_CMD12 (127)
int irq;/* Device IRQ */
void __iomem * ioaddr; /* Mapped address */
--
1.5.6.5
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[PATCH 2/2] mmc: some nip clean up for the sdhci driver
remove the extra line and rewrite the if condition line.
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
drivers/mmc/host/sdhci-of-core.c |1 -
drivers/mmc/host/sdhci.c |5 ++---
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-core.c b/drivers/mmc/host/sdhci-of-core.c
index d059805..732cffd 100644
--- a/drivers/mmc/host/sdhci-of-core.c
+++ b/drivers/mmc/host/sdhci-of-core.c
@@ -157,7 +157,6 @@ static int __devinit sdhci_of_probe(struct of_device *ofdev,
if (of_get_property(np, sdhci,auto-cmd12, NULL))
host-quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_AUTO_CMD12;
-
if (of_get_property(np, sdhci,1-bit-only, NULL))
host-quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 4b7b2d5..a1e6269 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -818,10 +818,9 @@ static void sdhci_set_transfer_mode(struct sdhci_host
*host,
mode = SDHCI_TRNS_BLK_CNT_EN;
if (data-blocks 1) {
+ mode |= SDHCI_TRNS_MULTI;
if (host-quirks SDHCI_QUIRK_MULTIBLOCK_READ_AUTO_CMD12)
- mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_AUTO_CMD12;
- else
- mode |= SDHCI_TRNS_MULTI;
+ mode |= SDHCI_TRNS_AUTO_CMD12;
}
if (data-flags MMC_DATA_READ)
mode |= SDHCI_TRNS_READ;
--
1.5.6.5
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[PATCH 3/3][MTD] P4080/nand: Fix the freescale lbc issue with 36bit mode
From: Lan Chunhe-B25806 b25...@freescale.com
When system uses 36bit physical address, res.start is 36bit
physical address. But the function of in_be32 returns 32bit
physical address. Then both of them compared each other is
wrong. So by converting the address of res.start into
the right format fixes this issue.
Signed-off-by: Lan Chunhe-B25806 b25...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
arch/powerpc/include/asm/fsl_lbc.h |1 +
arch/powerpc/sysdev/fsl_lbc.c | 33 -
drivers/mtd/nand/fsl_elbc_nand.c |2 +-
3 files changed, 34 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_lbc.h
b/arch/powerpc/include/asm/fsl_lbc.h
index 9b95eab..28dcf63 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -249,6 +249,7 @@ struct fsl_upm {
int width;
};
+extern unsigned int convert_lbc_address(phys_addr_t addr_base);
extern int fsl_lbc_find(phys_addr_t addr_base);
extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm);
diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c
index 9c9e44f..08f98d8 100644
--- a/arch/powerpc/sysdev/fsl_lbc.c
+++ b/arch/powerpc/sysdev/fsl_lbc.c
@@ -31,6 +31,36 @@ struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
EXPORT_SYMBOL(fsl_lbc_ctrl_dev);
/**
+ * convert_lbc_address - convert the base address
+ * @addr_base: base address of the memory bank
+ *
+ * This function converts a base address of lbc into the right format for the
BR
+ * registers. If the SOC has eLBC then it returns 32bit physical address else
+ * it returns 34bit physical address for local bus(Example: MPC8641).
+ */
+unsigned int convert_lbc_address(phys_addr_t addr_base)
+{
+ void *dev;
+ int compatible;
+
+ dev = of_find_node_by_name(NULL, localbus);
+ if (!dev) {
+ printk(KERN_INFO fsl-lbc: can't find localbus node\n);
+ of_node_put(dev);
+ return 0;
+ }
+
+ compatible = of_device_is_compatible(dev, fsl,elbc);
+ of_node_put(dev);
+ if (compatible)
+ return addr_base 0x8000;
+ else
+ return (addr_base 0x08000ull) \
+ | ((addr_base 0x3ull) 19);
+}
+EXPORT_SYMBOL(convert_lbc_address);
+
+/**
* fsl_lbc_find - find Localbus bank
* @addr_base: base address of the memory bank
*
@@ -50,7 +80,8 @@ int fsl_lbc_find(phys_addr_t addr_base)
__be32 br = in_be32(fsl_lbc_ctrl_dev-regs-bank[i].br);
__be32 or = in_be32(fsl_lbc_ctrl_dev-regs-bank[i].or);
- if (br BR_V (br or BR_BA) == addr_base)
+ if (br BR_V (br or BR_BA) \
+ == convert_lbc_address(addr_base))
return i;
}
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 7bbcb3f..0e8dc40 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -838,7 +838,7 @@ static int __devinit fsl_elbc_nand_probe(struct of_device
*dev,
(in_be32(lbc-bank[bank].br) BR_MSEL) == BR_MS_FCM
(in_be32(lbc-bank[bank].br)
in_be32(lbc-bank[bank].or) BR_BA)
-== res.start)
+== convert_lbc_address(res.start))
break;
if (bank = MAX_BANKS) {
--
1.5.6.5
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[PATCH 1/3][MTD] P4080/eLBC: Make Freescale elbc interrupt common to elbc devices
From: Lan Chunhe-B25806 b25...@freescale.com
Move Freescale elbc interrupt from nand dirver to elbc driver.
Then all elbc devices can use the interrupt instead of ONLY nand.
Signed-off-by: Lan Chunhe-B25806 b25...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
send the patch to linux-...@lists.infradead.org
it has been posted to linuxppc-...@ozlabs.org and do not get any comment.
arch/powerpc/Kconfig |7 +-
arch/powerpc/include/asm/fsl_lbc.h | 34 +-
arch/powerpc/sysdev/fsl_lbc.c | 254 ++--
3 files changed, 253 insertions(+), 42 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 2031a28..5155b53 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -703,9 +703,12 @@ config 4xx_SOC
bool
config FSL_LBC
- bool
+ bool Freescale Local Bus support
+ depends on FSL_SOC
help
- Freescale Localbus support
+ Enables reporting of errors from the Freescale local bus
+ controller. Also contains some common code used by
+ drivers for specific local bus peripherals.
config FSL_GTM
bool
diff --git a/arch/powerpc/include/asm/fsl_lbc.h
b/arch/powerpc/include/asm/fsl_lbc.h
index 1b5a210..9b95eab 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -1,9 +1,10 @@
/* Freescale Local Bus Controller
*
- * Copyright (c) 2006-2007 Freescale Semiconductor
+ * Copyright (c) 2006-2007, 2010 Freescale Semiconductor
*
* Authors: Nick Spence nick.spe...@freescale.com,
* Scott Wood scottw...@freescale.com
+ * Jack Lan jack@freescale.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -27,6 +28,9 @@
#include linux/types.h
#include linux/io.h
+#include linux/of_platform.h
+#include linux/interrupt.h
+
struct fsl_lbc_bank {
__be32 br; /** Base Register */
#define BR_BA 0x8000
@@ -125,13 +129,23 @@ struct fsl_lbc_regs {
#define LTESR_ATMW 0x0080
#define LTESR_ATMR 0x0040
#define LTESR_CS 0x0008
+#define LTESR_UPM 0x0002
#define LTESR_CC 0x0001
#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
+#define LTESR_MASK (LTESR_BM | LTESR_FCT | LTESR_PAR | LTESR_WP \
+| LTESR_ATMW | LTESR_ATMR | LTESR_CS | LTESR_UPM \
+| LTESR_CC)
+#define LTESR_CLEAR0x
+#define LTECCR_CLEAR 0x
+#define LTESR_STATUS LTESR_MASK
+#define LTEIR_ENABLE LTESR_MASK
+#define LTEDR_ENABLE 0x
__be32 ltedr; /** Transfer Error Disable Register */
__be32 lteir; /** Transfer Error Interrupt Register */
__be32 lteatr; /** Transfer Error Attributes Register */
__be32 ltear; /** Transfer Error Address Register */
- u8 res6[0xC];
+ __be32 lteccr; /** Transfer Error ECC Register */
+ u8 res6[0x8];
__be32 lbcr;/** Configuration Register */
#define LBCR_LDIS 0x8000
#define LBCR_LDIS_SHIFT31
@@ -265,7 +279,23 @@ static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
cpu_relax();
}
+/* overview of the fsl lbc controller */
+
+struct fsl_lbc_ctrl {
+ /* device info */
+ struct device *dev;
+ struct fsl_lbc_regs __iomem *regs;
+ int irq;
+ wait_queue_head_t irq_wait;
+ spinlock_t lock;
+ void*nand;
+
+ /* status read from LTESR by irq handler */
+ unsigned intirq_status;
+};
+
extern int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base,
u32 mar);
+extern struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
#endif /* __ASM_FSL_LBC_H */
diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c
index dceb8d1..9c9e44f 100644
--- a/arch/powerpc/sysdev/fsl_lbc.c
+++ b/arch/powerpc/sysdev/fsl_lbc.c
@@ -5,6 +5,10 @@
*
* Author: Anton Vorontsov avoront...@ru.mvista.com
*
+ * Copyright (c) 2010 Freescale Semiconductor
+ *
+ * Authors: Jack Lan jack@freescale.com
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@@ -23,35 +27,8 @@
#include asm/fsl_lbc.h
static spinlock_t fsl_lbc_lock = __SPIN_LOCK_UNLOCKED(fsl_lbc_lock);
-static struct fsl_lbc_regs __iomem *fsl_lbc_regs;
-
-static char __initdata *compat_lbc[] = {
- fsl,pq2-localbus,
- fsl,pq2pro-localbus,
- fsl,pq3-localbus,
- fsl,elbc,
-};
-
-static int __init fsl_lbc_init(void)
-{
- struct device_node *lbus
[PATCH 2/3][MTD] P4080/nand: Only make elbc nand driver detect nand flash partitions
From: Lan Chunhe-B25806 b25...@freescale.com
The former driver had the two functions:
1. detecting nand flash partitions;
2. registering elbc interrupt.
Now, second function is removed to fsl_lbc.c.
Signed-off-by: Lan Chunhe-B25806 b25...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
drivers/mtd/nand/Kconfig |1 +
drivers/mtd/nand/fsl_elbc_nand.c | 464 ++
2 files changed, 170 insertions(+), 295 deletions(-)
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index ffc3720..4b4c82e 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -459,6 +459,7 @@ config MTD_NAND_ORION
config MTD_NAND_FSL_ELBC
tristate NAND support for Freescale eLBC controllers
depends on MTD_NAND PPC_OF
+ select FSL_LBC
help
Various Freescale chips, including the 8313, include a NAND Flash
Controller Module with built-in hardware ECC capabilities.
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 5084cc5..7bbcb3f 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -1,9 +1,10 @@
/* Freescale Enhanced Local Bus Controller NAND driver
*
- * Copyright (c) 2006-2007 Freescale Semiconductor
+ * Copyright (c) 2006-2007, 2010 Freescale Semiconductor
*
* Authors: Nick Spence nick.spe...@freescale.com,
* Scott Wood scottw...@freescale.com
+ * Jack Lan jack@freescale.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -24,32 +25,21 @@
#include linux/types.h
#include linux/init.h
#include linux/kernel.h
-#include linux/string.h
-#include linux/ioport.h
-#include linux/of_platform.h
-#include linux/slab.h
-#include linux/interrupt.h
-#include linux/mtd/mtd.h
#include linux/mtd/nand.h
-#include linux/mtd/nand_ecc.h
#include linux/mtd/partitions.h
-
-#include asm/io.h
#include asm/fsl_lbc.h
#define MAX_BANKS 8
#define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
#define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
-struct fsl_elbc_ctrl;
-
/* mtd information per set */
struct fsl_elbc_mtd {
struct mtd_info mtd;
struct nand_chip chip;
- struct fsl_elbc_ctrl *ctrl;
+ struct fsl_lbc_ctrl *ctrl;
struct device *dev;
int bank; /* Chip select bank number */
@@ -58,18 +48,12 @@ struct fsl_elbc_mtd {
unsigned int fmr; /* FCM Flash Mode Register value */
};
-/* overview of the fsl elbc controller */
+/* Freescale eLBC FCM controller infomation */
-struct fsl_elbc_ctrl {
+struct fsl_elbc_fcm_ctrl {
struct nand_hw_control controller;
struct fsl_elbc_mtd *chips[MAX_BANKS];
- /* device info */
- struct device *dev;
- struct fsl_lbc_regs __iomem *regs;
- int irq;
- wait_queue_head_t irq_wait;
- unsigned int irq_status; /* status read from LTESR by irq handler */
u8 __iomem *addr;/* Address of assigned FCM buffer*/
unsigned int page; /* Last page written to / read from */
unsigned int read_bytes; /* Number of bytes read during command */
@@ -82,6 +66,8 @@ struct fsl_elbc_ctrl {
char *oob_poi; /* Place to write ECC after read back*/
};
+static struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl;
+
/* These map to the positions used by the FCM hardware ECC generator */
/* Small Page FLASH with FMR[ECCM] = 0 */
@@ -164,11 +150,11 @@ static void set_addr(struct mtd_info *mtd, int column,
int page_addr, int oob)
{
struct nand_chip *chip = mtd-priv;
struct fsl_elbc_mtd *priv = chip-priv;
- struct fsl_elbc_ctrl *ctrl = priv-ctrl;
+ struct fsl_lbc_ctrl *ctrl = priv-ctrl;
struct fsl_lbc_regs __iomem *lbc = ctrl-regs;
int buf_num;
- ctrl-page = page_addr;
+ elbc_fcm_ctrl-page = page_addr;
out_be32(lbc-fbar,
page_addr (chip-phys_erase_shift - chip-page_shift));
@@ -185,16 +171,18 @@ static void set_addr(struct mtd_info *mtd, int column,
int page_addr, int oob)
buf_num = page_addr 7;
}
- ctrl-addr = priv-vbase + buf_num * 1024;
- ctrl-index = column;
+ elbc_fcm_ctrl-addr = priv-vbase + buf_num * 1024;
+ elbc_fcm_ctrl-index = column;
/* for OOB data point to the second half of the buffer */
if (oob)
- ctrl-index += priv-page_size ? 2048 : 512;
+ elbc_fcm_ctrl-index += priv-page_size ? 2048 : 512;
- dev_vdbg(ctrl-dev, set_addr: bank=%d, ctrl-addr=0x%p (0x%p),
+ dev_vdbg(priv-dev, set_addr: bank=%d,
+ elbc_fcm_ctrl-addr=0x%p (0x%p),
index %x, pes %d ps %d\n,
-buf_num, ctrl
[PATCH 2/3 v2] dts: Add sdhci,auto-cmd12 field for p4080 device tree
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
Documentation/powerpc/dts-bindings/fsl/esdhc.txt |2 ++
arch/powerpc/boot/dts/p4080ds.dts|1 +
2 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/Documentation/powerpc/dts-bindings/fsl/esdhc.txt
b/Documentation/powerpc/dts-bindings/fsl/esdhc.txt
index 8a00407..64bcb8b 100644
--- a/Documentation/powerpc/dts-bindings/fsl/esdhc.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/esdhc.txt
@@ -14,6 +14,8 @@ Required properties:
reports inverted write-protect state;
- sdhci,1-bit-only : (optional) specifies that a controller can
only handle 1-bit data transfers.
+ - sdhci,auto-cmd12: (optional) specifies that a controller can
+only handle auto CMD12.
Example:
diff --git a/arch/powerpc/boot/dts/p4080ds.dts
b/arch/powerpc/boot/dts/p4080ds.dts
index 6b29eab..efa0091 100644
--- a/arch/powerpc/boot/dts/p4080ds.dts
+++ b/arch/powerpc/boot/dts/p4080ds.dts
@@ -280,6 +280,7 @@
reg = 0x114000 0x1000;
interrupts = 48 2;
interrupt-parent = mpic;
+ sdhci,auto-cmd12;
};
i...@118000 {
--
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[PATCH 3/3 v2] dts: Add ESDHC weird voltage bits workaround
P4080 ESDHC controller does not support 1.8V and 3.0V voltage. but the host controller capabilities register wrongly set the bits. This patch adds the workaround to correct the weird voltage setting bits. Only 3.3V voltage is supported for P4080 ESDHC controller. Signed-off-by: Roy Zang tie-fei.z...@freescale.com --- arch/powerpc/boot/dts/p4080ds.dts |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/boot/dts/p4080ds.dts b/arch/powerpc/boot/dts/p4080ds.dts index efa0091..2f0de24 100644 --- a/arch/powerpc/boot/dts/p4080ds.dts +++ b/arch/powerpc/boot/dts/p4080ds.dts @@ -280,6 +280,7 @@ reg = 0x114000 0x1000; interrupts = 48 2; interrupt-parent = mpic; + voltage-ranges = 3300 3300; sdhci,auto-cmd12; }; -- 1.5.6.5 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/3 v2] sdhci: Add auto CMD12 support for eSDHC driver
From: Jerry Huang chang-ming.hu...@freescale.com
Add auto CMD12 command support for eSDHC driver.
This is needed by P4080 and P1022 for block read/write.
Manual asynchronous CMD12 abort operation causes protocol violations on
these silicons.
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
drivers/mmc/host/sdhci-of-core.c |4
drivers/mmc/host/sdhci.c | 14 --
drivers/mmc/host/sdhci.h |2 ++
3 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-core.c b/drivers/mmc/host/sdhci-of-core.c
index a2e9820..dd1bdd1 100644
--- a/drivers/mmc/host/sdhci-of-core.c
+++ b/drivers/mmc/host/sdhci-of-core.c
@@ -154,6 +154,10 @@ static int __devinit sdhci_of_probe(struct of_device
*ofdev,
host-ops = sdhci_of_data-ops;
}
+ if (of_get_property(np, sdhci,auto-cmd12, NULL))
+ host-quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
+
+
if (of_get_property(np, sdhci,1-bit-only, NULL))
host-quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index c6d1bd8..a92566e 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -817,8 +817,12 @@ static void sdhci_set_transfer_mode(struct sdhci_host
*host,
WARN_ON(!host-data);
mode = SDHCI_TRNS_BLK_CNT_EN;
- if (data-blocks 1)
- mode |= SDHCI_TRNS_MULTI;
+ if (data-blocks 1) {
+ if (host-quirks SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
+ mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_ACMD12;
+ else
+ mode |= SDHCI_TRNS_MULTI;
+ }
if (data-flags MMC_DATA_READ)
mode |= SDHCI_TRNS_READ;
if (host-flags SDHCI_REQ_USE_DMA)
@@ -1108,6 +1112,12 @@ static void sdhci_request(struct mmc_host *mmc, struct
mmc_request *mrq)
#ifndef SDHCI_USE_LEDS_CLASS
sdhci_activate_led(host);
#endif
+ if (host-quirks SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) {
+ if (mrq-stop) {
+ mrq-data-stop = NULL;
+ mrq-stop = NULL;
+ }
+ }
host-mrq = mrq;
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index c846813..8fb088c 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -240,6 +240,8 @@ struct sdhci_host {
#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (125)
/* Controller cannot support End Attribute in NOP ADMA descriptor */
#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (126)
+/* Controller uses Auto CMD12 command to stop the transfer */
+#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (127)
int irq;/* Device IRQ */
void __iomem * ioaddr; /* Mapped address */
--
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[PATCH 3/3] P4080/mtd: Fix the freescale lbc issue with 36bit mode
From: Lan Chunhe-B25806 b25...@freescale.com
When system uses 36bit physical address, res.start is 36bit
physical address. But the function of in_be32 returns 32bit
physical address. Then both of them compared each other is
wrong. So by converting the address of res.start into
the right format fixes this issue.
Signed-off-by: Lan Chunhe-B25806 b25...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
arch/powerpc/include/asm/fsl_lbc.h |1 +
arch/powerpc/sysdev/fsl_lbc.c | 33 -
drivers/mtd/nand/fsl_elbc_nand.c |2 +-
3 files changed, 34 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_lbc.h
b/arch/powerpc/include/asm/fsl_lbc.h
index 9b95eab..28dcf63 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -249,6 +249,7 @@ struct fsl_upm {
int width;
};
+extern unsigned int convert_lbc_address(phys_addr_t addr_base);
extern int fsl_lbc_find(phys_addr_t addr_base);
extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm);
diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c
index 9c9e44f..08f98d8 100644
--- a/arch/powerpc/sysdev/fsl_lbc.c
+++ b/arch/powerpc/sysdev/fsl_lbc.c
@@ -31,6 +31,36 @@ struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
EXPORT_SYMBOL(fsl_lbc_ctrl_dev);
/**
+ * convert_lbc_address - convert the base address
+ * @addr_base: base address of the memory bank
+ *
+ * This function converts a base address of lbc into the right format for the
BR
+ * registers. If the SOC has eLBC then it returns 32bit physical address else
+ * it returns 34bit physical address for local bus(Example: MPC8641).
+ */
+unsigned int convert_lbc_address(phys_addr_t addr_base)
+{
+ void *dev;
+ int compatible;
+
+ dev = of_find_node_by_name(NULL, localbus);
+ if (!dev) {
+ printk(KERN_INFO fsl-lbc: can't find localbus node\n);
+ of_node_put(dev);
+ return 0;
+ }
+
+ compatible = of_device_is_compatible(dev, fsl,elbc);
+ of_node_put(dev);
+ if (compatible)
+ return addr_base 0x8000;
+ else
+ return (addr_base 0x08000ull) \
+ | ((addr_base 0x3ull) 19);
+}
+EXPORT_SYMBOL(convert_lbc_address);
+
+/**
* fsl_lbc_find - find Localbus bank
* @addr_base: base address of the memory bank
*
@@ -50,7 +80,8 @@ int fsl_lbc_find(phys_addr_t addr_base)
__be32 br = in_be32(fsl_lbc_ctrl_dev-regs-bank[i].br);
__be32 or = in_be32(fsl_lbc_ctrl_dev-regs-bank[i].or);
- if (br BR_V (br or BR_BA) == addr_base)
+ if (br BR_V (br or BR_BA) \
+ == convert_lbc_address(addr_base))
return i;
}
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 7bbcb3f..0e8dc40 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -838,7 +838,7 @@ static int __devinit fsl_elbc_nand_probe(struct of_device
*dev,
(in_be32(lbc-bank[bank].br) BR_MSEL) == BR_MS_FCM
(in_be32(lbc-bank[bank].br)
in_be32(lbc-bank[bank].or) BR_BA)
-== res.start)
+== convert_lbc_address(res.start))
break;
if (bank = MAX_BANKS) {
--
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[PATCH 3/3 v2] mmc: Add ESDHC weird voltage bits workaround
P4080 ESDHC controller does not support 1.8V and 3.0V voltage. but the
host controller capabilities register wrongly set the bits.
This patch adds the workaround to correct the weird voltage setting bits.
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
This is the second version of patch
http://patchwork.ozlabs.org/patch/60106/
According to the comment, remove some un-necessary setting.
Together with patch
http://patchwork.ozlabs.org/patch/60111/
http://patchwork.ozlabs.org/patch/60116/
This serial patches add mmc support for p4080 silicon
drivers/mmc/host/sdhci-of-core.c |4
drivers/mmc/host/sdhci.c |8
drivers/mmc/host/sdhci.h |4
3 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-core.c b/drivers/mmc/host/sdhci-of-core.c
index 0c30242..1f3913d 100644
--- a/drivers/mmc/host/sdhci-of-core.c
+++ b/drivers/mmc/host/sdhci-of-core.c
@@ -164,6 +164,10 @@ static int __devinit sdhci_of_probe(struct of_device
*ofdev,
if (sdhci_of_wp_inverted(np))
host-quirks |= SDHCI_QUIRK_INVERTED_WRITE_PROTECT;
+ if (of_device_is_compatible(np, fsl,p4080-esdhc))
+ host-quirks |= (SDHCI_QUIRK_QORIQ_NO_VDD_180
+ |SDHCI_QUIRK_QORIQ_NO_VDD_300);
+
clk = of_get_property(np, clock-frequency, size);
if (clk size == sizeof(*clk) *clk)
of_host-clock = *clk;
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 1424d08..a667790 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1699,6 +1699,14 @@ int sdhci_add_host(struct sdhci_host *host)
caps = sdhci_readl(host, SDHCI_CAPABILITIES);
+/* Workaround for P4080 host controller capabilities
+ * 1.8V and 3.0V do not supported*/
+ if (host-quirks SDHCI_QUIRK_QORIQ_NO_VDD_180)
+ caps = ~SDHCI_CAN_VDD_180;
+
+ if (host-quirks SDHCI_QUIRK_QORIQ_NO_VDD_300)
+ caps = ~SDHCI_CAN_VDD_300;
+
if (host-quirks SDHCI_QUIRK_FORCE_DMA)
host-flags |= SDHCI_USE_SDMA;
else if (!(caps SDHCI_CAN_DO_SDMA))
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index aa112aa..389b58c 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -243,6 +243,10 @@ struct sdhci_host {
#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (126)
/* Controller uses Auto CMD12 command to stop the transfer */
#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (127)
+/* Controller cannot support 1.8V */
+#define SDHCI_QUIRK_QORIQ_NO_VDD_180 (128)
+/* Controller cannot support 3.0V */
+#define SDHCI_QUIRK_QORIQ_NO_VDD_300 (129)
int irq;/* Device IRQ */
void __iomem * ioaddr; /* Mapped address */
--
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[PATCH 3/3] mmc: Add ESDHC weird register workaround
P4080 ESDHC controller induces weird register setting.
This patch adds the workaround to correct the weird register setting.
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
drivers/mmc/host/sdhci-of-core.c |5 +
drivers/mmc/host/sdhci.c | 13 +
drivers/mmc/host/sdhci.h |2 ++
3 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-core.c b/drivers/mmc/host/sdhci-of-core.c
index 0c30242..1b6945a 100644
--- a/drivers/mmc/host/sdhci-of-core.c
+++ b/drivers/mmc/host/sdhci-of-core.c
@@ -164,6 +164,11 @@ static int __devinit sdhci_of_probe(struct of_device
*ofdev,
if (sdhci_of_wp_inverted(np))
host-quirks |= SDHCI_QUIRK_INVERTED_WRITE_PROTECT;
+ if (of_device_is_compatible(np, fsl,p4080-esdhc)) {
+ host-quirks |= SDHCI_QUIRK_QORIQ_REG_WEIRD;
+ host-quirks = ~SDHCI_QUIRK_INVERTED_WRITE_PROTECT;
+ }
+
clk = of_get_property(np, clock-frequency, size);
if (clk size == sizeof(*clk) *clk)
of_host-clock = *clk;
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 1424d08..b5b3627 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -788,6 +788,15 @@ static void sdhci_prepare_data(struct sdhci_host *host,
struct mmc_data *data)
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
}
+ /* The default value of DMAS bits of Protocol Control Register is not
+* correct. clear these two bits to use simple DMA */
+#define ESDHCI_CTRL_DMAS_MASK 0xFCFF
+ if (host-quirks SDHCI_QUIRK_QORIQ_REG_WEIRD) {
+ ctrl = sdhci_readl(host, SDHCI_HOST_CONTROL);
+ ctrl = ctrl ESDHCI_CTRL_DMAS_MASK;
+ sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL);
+ }
+
if (!(host-flags SDHCI_REQ_USE_DMA)) {
int flags;
@@ -1699,6 +1708,10 @@ int sdhci_add_host(struct sdhci_host *host)
caps = sdhci_readl(host, SDHCI_CAPABILITIES);
+/* Workaround for P4080 host controller capabilities */
+ if (host-quirks SDHCI_QUIRK_QORIQ_REG_WEIRD)
+ caps = ~(SDHCI_CAN_VDD_180 | SDHCI_CAN_VDD_330);
+
if (host-quirks SDHCI_QUIRK_FORCE_DMA)
host-flags |= SDHCI_USE_SDMA;
else if (!(caps SDHCI_CAN_DO_SDMA))
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index aa112aa..33d5613 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -243,6 +243,8 @@ struct sdhci_host {
#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (126)
/* Controller uses Auto CMD12 command to stop the transfer */
#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (127)
+/* Controller has weird bit setting for some registers due to errata */
+#define SDHCI_QUIRK_QORIQ_REG_WEIRD(128)
int irq;/* Device IRQ */
void __iomem * ioaddr; /* Mapped address */
--
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[PATCH 1/3] mmc: Auto CMD12 support for eSDHC driver
From: Jerry Huang chang-ming.hu...@freescale.com
Add auto CMD12 command support for eSDHC driver.
This is needed by P4080 and P1022 for block read/write.
Manual asynchronous CMD12 abort operation causes protocol violations on
these silicons.
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
drivers/mmc/host/sdhci-of-core.c |4
drivers/mmc/host/sdhci.c | 14 --
drivers/mmc/host/sdhci.h |3 +++
3 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-core.c b/drivers/mmc/host/sdhci-of-core.c
index a2e9820..0c30242 100644
--- a/drivers/mmc/host/sdhci-of-core.c
+++ b/drivers/mmc/host/sdhci-of-core.c
@@ -154,6 +154,10 @@ static int __devinit sdhci_of_probe(struct of_device
*ofdev,
host-ops = sdhci_of_data-ops;
}
+ if (of_get_property(np, fsl,sdhci-auto-cmd12, NULL))
+ host-quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
+
+
if (of_get_property(np, sdhci,1-bit-only, NULL))
host-quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index c6d1bd8..1424d08 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -2,6 +2,7 @@
* linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface
driver
*
* Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
+ * Copyright 2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -817,8 +818,12 @@ static void sdhci_set_transfer_mode(struct sdhci_host
*host,
WARN_ON(!host-data);
mode = SDHCI_TRNS_BLK_CNT_EN;
- if (data-blocks 1)
- mode |= SDHCI_TRNS_MULTI;
+ if (data-blocks 1) {
+ if (host-quirks SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
+ mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_ACMD12;
+ else
+ mode |= SDHCI_TRNS_MULTI;
+ }
if (data-flags MMC_DATA_READ)
mode |= SDHCI_TRNS_READ;
if (host-flags SDHCI_REQ_USE_DMA)
@@ -1108,6 +1113,11 @@ static void sdhci_request(struct mmc_host *mmc, struct
mmc_request *mrq)
#ifndef SDHCI_USE_LEDS_CLASS
sdhci_activate_led(host);
#endif
+ if (host-quirks SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
+ if (mrq-stop) {
+ mrq-data-stop = NULL;
+ mrq-stop = NULL;
+ }
host-mrq = mrq;
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index c846813..aa112aa 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -2,6 +2,7 @@
* linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface
driver
*
* Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
+ * Copyright 2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -240,6 +241,8 @@ struct sdhci_host {
#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (125)
/* Controller cannot support End Attribute in NOP ADMA descriptor */
#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (126)
+/* Controller uses Auto CMD12 command to stop the transfer */
+#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (127)
int irq;/* Device IRQ */
void __iomem * ioaddr; /* Mapped address */
--
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[PATCH 2/3] dts: Add sdhci-auto-cmd12 field for p4080 device tree
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
arch/powerpc/boot/dts/p4080ds.dts |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/p4080ds.dts
b/arch/powerpc/boot/dts/p4080ds.dts
index 6b29eab..11c8884 100644
--- a/arch/powerpc/boot/dts/p4080ds.dts
+++ b/arch/powerpc/boot/dts/p4080ds.dts
@@ -280,6 +280,7 @@
reg = 0x114000 0x1000;
interrupts = 48 2;
interrupt-parent = mpic;
+ fsl,sdhci-auto-cmd12;
};
i...@118000 {
--
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[PATCH 0/3] mmc: Add mmc support for P4080 chip
This serial patch adds some workarounds to enable mmc card support for P4080 chip. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v2] rtc: add support for DS3232 RTC
This patch adds the driver for RTC chip DS3232 via I2C bus.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
Signed-off-by: Jingchang Lu b22...@freescale.com
Signed-off-by: Srikanth Srinivasan srikanth.sriniva...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
Tested on MPC8536DS and P4080DS board
drivers/rtc/Kconfig | 11 ++
drivers/rtc/Makefile |1 +
drivers/rtc/rtc-ds3232.c | 427 ++
3 files changed, 439 insertions(+), 0 deletions(-)
create mode 100644 drivers/rtc/rtc-ds3232.c
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 6a13037..13c2fdb 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -166,6 +166,17 @@ config RTC_DRV_DS1672
This driver can also be built as a module. If so, the module
will be called rtc-ds1672.
+config RTC_DRV_DS3232
+ tristate Dallas/Maxim DS3232
+ depends on RTC_CLASS I2C
+ help
+ If you say yes here you get support for Dallas Semiconductor
+ DS3232 real-time clock chips. If an interrupt is associated
+ with the device, the alarm functionality is supported.
+
+ This driver can also be built as a module. If so, the module
+ will be called rtc-ds3232.
+
config RTC_DRV_MAX6900
tristate Maxim MAX6900
help
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 44ef194..0af190c 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_RTC_DRV_DS1511) += rtc-ds1511.o
obj-$(CONFIG_RTC_DRV_DS1553) += rtc-ds1553.o
obj-$(CONFIG_RTC_DRV_DS1672) += rtc-ds1672.o
obj-$(CONFIG_RTC_DRV_DS1742) += rtc-ds1742.o
+obj-$(CONFIG_RTC_DRV_DS3232) += rtc-ds3232.o
obj-$(CONFIG_RTC_DRV_DS3234) += rtc-ds3234.o
obj-$(CONFIG_RTC_DRV_EFI) += rtc-efi.o
obj-$(CONFIG_RTC_DRV_EP93XX) += rtc-ep93xx.o
diff --git a/drivers/rtc/rtc-ds3232.c b/drivers/rtc/rtc-ds3232.c
new file mode 100644
index 000..e36ec1c
--- /dev/null
+++ b/drivers/rtc/rtc-ds3232.c
@@ -0,0 +1,427 @@
+/*
+ * RTC client/driver for the Maxim/Dallas DS3232 Real-Time Clock over I2C
+ *
+ * Copyright (C) 2009-2010 Freescale Semiconductor.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+/*
+ * It would be more efficient to use i2c msgs/i2c_transfer directly but, as
+ * recommened in .../Documentation/i2c/writing-clients section
+ * Sending and receiving, using SMBus level communication is preferred.
+ */
+
+#include linux/kernel.h
+#include linux/module.h
+#include linux/interrupt.h
+#include linux/i2c.h
+#include linux/rtc.h
+#include linux/bcd.h
+#include linux/workqueue.h
+#include linux/slab.h
+
+#define DS3232_REG_SECONDS 0x00
+#define DS3232_REG_MINUTES 0x01
+#define DS3232_REG_HOURS 0x02
+#define DS3232_REG_AMPM0x02
+#define DS3232_REG_DAY 0x03
+#define DS3232_REG_DATE0x04
+#define DS3232_REG_MONTH 0x05
+#define DS3232_REG_CENTURY 0x05
+#define DS3232_REG_YEAR0x06
+#define DS3232_REG_ALARM1 0x07 /* Alarm 1 BASE */
+#define DS3232_REG_ALARM2 0x0B /* Alarm 2 BASE */
+#define DS3232_REG_CR 0x0E/* Control register */
+# define DS3232_REG_CR_nEOSC0x80
+# define DS3232_REG_CR_INTCN0x04
+# define DS3232_REG_CR_A2IE0x02
+# define DS3232_REG_CR_A1IE0x01
+
+#define DS3232_REG_SR 0x0F/* control/status register */
+# define DS3232_REG_SR_OSF 0x80
+# define DS3232_REG_SR_BSY 0x04
+# define DS3232_REG_SR_A2F 0x02
+# define DS3232_REG_SR_A1F 0x01
+
+struct ds3232 {
+ struct i2c_client *client;
+ struct rtc_device *rtc;
+ struct work_struct work;
+
+ /* The mutex protects alarm operations, and prevents a race
+* between the enable_irq() in the workqueue and the free_irq()
+* in the remove function.
+*/
+ struct mutex mutex;
+ int exiting;
+};
+
+static struct i2c_driver ds3232_driver;
+
+static int ds3232_check_rtc_status(struct i2c_client *client)
+{
+ int ret = 0;
+ int control, stat;
+
+ stat = i2c_smbus_read_byte_data(client, DS3232_REG_SR);
+ if (stat 0)
+ return stat;
+
+ if (stat DS3232_REG_SR_OSF)
+ dev_warn(client-dev,
+ oscillator discontinuity flagged,
+ time unreliable\n);
+
+ stat = ~(DS3232_REG_SR_OSF | DS3232_REG_SR_A1F | DS3232_REG_SR_A2F);
+
+ ret = i2c_smbus_write_byte_data(client, DS3232_REG_SR, stat);
+ if (ret 0)
+ return ret;
+
+ /* If the alarm is pending, clear it before requesting
+* the interrupt, so an interrupt event
[PATCH] rtc: add support for DS3232 RTC
This patch adds the driver for RTC chip DS3232 via I2C bus
Signed-off-by: Mingkai Hu mingkai...@freescale.com
Signed-off-by: Jingchang Lu b22...@freescale.com
Signed-off-by: Srikanth Srinivasan srikanth.sriniva...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
Tested on MPC8536DS and P4080DS board
drivers/rtc/Kconfig | 11 +
drivers/rtc/Makefile |1 +
drivers/rtc/rtc-ds3232.c | 466 ++
3 files changed, 478 insertions(+), 0 deletions(-)
create mode 100644 drivers/rtc/rtc-ds3232.c
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 6a13037..13c2fdb 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -166,6 +166,17 @@ config RTC_DRV_DS1672
This driver can also be built as a module. If so, the module
will be called rtc-ds1672.
+config RTC_DRV_DS3232
+ tristate Dallas/Maxim DS3232
+ depends on RTC_CLASS I2C
+ help
+ If you say yes here you get support for Dallas Semiconductor
+ DS3232 real-time clock chips. If an interrupt is associated
+ with the device, the alarm functionality is supported.
+
+ This driver can also be built as a module. If so, the module
+ will be called rtc-ds3232.
+
config RTC_DRV_MAX6900
tristate Maxim MAX6900
help
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 44ef194..0af190c 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_RTC_DRV_DS1511) += rtc-ds1511.o
obj-$(CONFIG_RTC_DRV_DS1553) += rtc-ds1553.o
obj-$(CONFIG_RTC_DRV_DS1672) += rtc-ds1672.o
obj-$(CONFIG_RTC_DRV_DS1742) += rtc-ds1742.o
+obj-$(CONFIG_RTC_DRV_DS3232) += rtc-ds3232.o
obj-$(CONFIG_RTC_DRV_DS3234) += rtc-ds3234.o
obj-$(CONFIG_RTC_DRV_EFI) += rtc-efi.o
obj-$(CONFIG_RTC_DRV_EP93XX) += rtc-ep93xx.o
diff --git a/drivers/rtc/rtc-ds3232.c b/drivers/rtc/rtc-ds3232.c
new file mode 100644
index 000..21e1599
--- /dev/null
+++ b/drivers/rtc/rtc-ds3232.c
@@ -0,0 +1,466 @@
+/*
+ * RTC client/driver for the Maxim/Dallas DS3232 Real-Time Clock over I2C
+ *
+ * Copyright (C) 2009-2010 Freescale Semiconductor.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+/*
+ * It would be more efficient to use i2c msgs/i2c_transfer directly but, as
+ * recommened in .../Documentation/i2c/writing-clients section
+ * Sending and receiving, using SMBus level communication is preferred.
+ */
+
+#include linux/kernel.h
+#include linux/module.h
+#include linux/interrupt.h
+#include linux/i2c.h
+#include linux/rtc.h
+#include linux/bcd.h
+#include linux/workqueue.h
+#include linux/slab.h
+
+#define DS3232_REG_SECONDS 0x00
+#define DS3232_REG_MINUTES 0x01
+#define DS3232_REG_HOURS 0x02
+#define DS3232_REG_AMPM0x02
+#define DS3232_REG_DAY 0x03
+#define DS3232_REG_DATE0x04
+#define DS3232_REG_MONTH 0x05
+#define DS3232_REG_CENTURY 0x05
+#define DS3232_REG_YEAR0x06
+#define DS3232_REG_ALARM1 0x07 /* Alarm 1 BASE */
+#define DS3232_REG_ALARM2 0x0B /* Alarm 2 BASE */
+#define DS3232_REG_CR 0x0E/* Control register */
+# define DS3232_REG_CR_nEOSC0x80
+# define DS3232_REG_CR_INTCN0x04
+# define DS3232_REG_CR_A2IE0x02
+# define DS3232_REG_CR_A1IE0x01
+
+#define DS3232_REG_SR 0x0F/* control/status register */
+# define DS3232_REG_SR_OSF 0x80
+# define DS3232_REG_SR_BSY 0x04
+# define DS3232_REG_SR_A2F 0x02
+# define DS3232_REG_SR_A1F 0x01
+
+struct ds3232 {
+ struct i2c_client *client;
+ struct rtc_device *rtc;
+ struct work_struct work;
+
+ /* The mutex protects alarm operations, and prevents a race
+* between the enable_irq() in the workqueue and the free_irq()
+* in the remove function.
+*/
+ struct mutex mutex;
+ int exiting;
+};
+
+static struct i2c_driver ds3232_driver;
+
+static int ds3232_check_rtc_status(struct i2c_client *client)
+{
+ int ret = 0;
+ int control, stat;
+
+ stat = i2c_smbus_read_byte_data(client, DS3232_REG_SR);
+ if (stat 0)
+ return stat;
+
+ if (stat DS3232_REG_SR_OSF)
+ dev_warn(client-dev,
+ oscillator discontinuity flagged,
+ time unreliable\n);
+
+ stat = ~(DS3232_REG_SR_OSF | DS3232_REG_SR_A1F | DS3232_REG_SR_A2F);
+
+ ret = i2c_smbus_write_byte_data(client, DS3232_REG_SR, stat);
+ if (ret 0)
+ return ret;
+
+ /* If the alarm is pending, clear it before requesting
+* the interrupt, so an interrupt event isn't
[PATCH] rtc: add support for DS3232 RTC
This patch adds the driver for RTC chip DS3232 via I2C bus
Signed-off-by: Mingkai Hu mingkai...@freescale.com
Signed-off-by: Jingchang Lu b22...@freescale.com
Signed-off-by: Srikanth Srinivasan srikanth.sriniva...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
Tested on MPC8536DS and P4080DS board
drivers/rtc/Kconfig | 11 +
drivers/rtc/Makefile |1 +
drivers/rtc/rtc-ds3232.c | 466 ++
3 files changed, 478 insertions(+), 0 deletions(-)
create mode 100644 drivers/rtc/rtc-ds3232.c
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 6a13037..13c2fdb 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -166,6 +166,17 @@ config RTC_DRV_DS1672
This driver can also be built as a module. If so, the module
will be called rtc-ds1672.
+config RTC_DRV_DS3232
+ tristate Dallas/Maxim DS3232
+ depends on RTC_CLASS I2C
+ help
+ If you say yes here you get support for Dallas Semiconductor
+ DS3232 real-time clock chips. If an interrupt is associated
+ with the device, the alarm functionality is supported.
+
+ This driver can also be built as a module. If so, the module
+ will be called rtc-ds3232.
+
config RTC_DRV_MAX6900
tristate Maxim MAX6900
help
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 44ef194..0af190c 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_RTC_DRV_DS1511) += rtc-ds1511.o
obj-$(CONFIG_RTC_DRV_DS1553) += rtc-ds1553.o
obj-$(CONFIG_RTC_DRV_DS1672) += rtc-ds1672.o
obj-$(CONFIG_RTC_DRV_DS1742) += rtc-ds1742.o
+obj-$(CONFIG_RTC_DRV_DS3232) += rtc-ds3232.o
obj-$(CONFIG_RTC_DRV_DS3234) += rtc-ds3234.o
obj-$(CONFIG_RTC_DRV_EFI) += rtc-efi.o
obj-$(CONFIG_RTC_DRV_EP93XX) += rtc-ep93xx.o
diff --git a/drivers/rtc/rtc-ds3232.c b/drivers/rtc/rtc-ds3232.c
new file mode 100644
index 000..21e1599
--- /dev/null
+++ b/drivers/rtc/rtc-ds3232.c
@@ -0,0 +1,466 @@
+/*
+ * RTC client/driver for the Maxim/Dallas DS3232 Real-Time Clock over I2C
+ *
+ * Copyright (C) 2009-2010 Freescale Semiconductor.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+/*
+ * It would be more efficient to use i2c msgs/i2c_transfer directly but, as
+ * recommened in .../Documentation/i2c/writing-clients section
+ * Sending and receiving, using SMBus level communication is preferred.
+ */
+
+#include linux/kernel.h
+#include linux/module.h
+#include linux/interrupt.h
+#include linux/i2c.h
+#include linux/rtc.h
+#include linux/bcd.h
+#include linux/workqueue.h
+#include linux/slab.h
+
+#define DS3232_REG_SECONDS 0x00
+#define DS3232_REG_MINUTES 0x01
+#define DS3232_REG_HOURS 0x02
+#define DS3232_REG_AMPM0x02
+#define DS3232_REG_DAY 0x03
+#define DS3232_REG_DATE0x04
+#define DS3232_REG_MONTH 0x05
+#define DS3232_REG_CENTURY 0x05
+#define DS3232_REG_YEAR0x06
+#define DS3232_REG_ALARM1 0x07 /* Alarm 1 BASE */
+#define DS3232_REG_ALARM2 0x0B /* Alarm 2 BASE */
+#define DS3232_REG_CR 0x0E/* Control register */
+# define DS3232_REG_CR_nEOSC0x80
+# define DS3232_REG_CR_INTCN0x04
+# define DS3232_REG_CR_A2IE0x02
+# define DS3232_REG_CR_A1IE0x01
+
+#define DS3232_REG_SR 0x0F/* control/status register */
+# define DS3232_REG_SR_OSF 0x80
+# define DS3232_REG_SR_BSY 0x04
+# define DS3232_REG_SR_A2F 0x02
+# define DS3232_REG_SR_A1F 0x01
+
+struct ds3232 {
+ struct i2c_client *client;
+ struct rtc_device *rtc;
+ struct work_struct work;
+
+ /* The mutex protects alarm operations, and prevents a race
+* between the enable_irq() in the workqueue and the free_irq()
+* in the remove function.
+*/
+ struct mutex mutex;
+ int exiting;
+};
+
+static struct i2c_driver ds3232_driver;
+
+static int ds3232_check_rtc_status(struct i2c_client *client)
+{
+ int ret = 0;
+ int control, stat;
+
+ stat = i2c_smbus_read_byte_data(client, DS3232_REG_SR);
+ if (stat 0)
+ return stat;
+
+ if (stat DS3232_REG_SR_OSF)
+ dev_warn(client-dev,
+ oscillator discontinuity flagged,
+ time unreliable\n);
+
+ stat = ~(DS3232_REG_SR_OSF | DS3232_REG_SR_A1F | DS3232_REG_SR_A2F);
+
+ ret = i2c_smbus_write_byte_data(client, DS3232_REG_SR, stat);
+ if (ret 0)
+ return ret;
+
+ /* If the alarm is pending, clear it before requesting
+* the interrupt, so an interrupt event isn't
Re: [PATCH] mpc7448: add alias list to DTS, clean out old chosen node
On Fri, 2008-07-11 at 04:21 +0800, Paul Gortmaker wrote: The mpc7448hpc2 board doesn't have an alias block like most of the other modern eval boards have. We need this block in order to have u-boot be able to make use of the CONFIG_OF_STDOUT_VIA_ALIAS (vs. having a hard coded node) in the future. Also remove the old, redundant chosen node. Of all the modern Freescale eval boards (incl. 83xx, 85xx, 86xx) this is the only one which still has it. Its presence also breaks with some older versions of u-boot, like 1.3.1 -- which try and insert a second chosen node. Signed-off-by: Paul Gortmaker [EMAIL PROTECTED] --- Acked-by: Roy Zang [EMAIL PROTECTED] Roy ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
