Re: [PATCHv3 1/2] [POWERPC] CPM2: Implement GPIO LIB API on CPM2 Freescale SoC.
Hi Kumar,
On Friday 18 July 2008, Kumar Gala wrote:
On Jul 18, 2008, at 10:30 AM, Jochen Friedrich wrote:
On Jun 18, 2008, at 12:08 PM, Laurent Pinchart wrote:
+#if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
+
+struct cpm2_ioports {
+ u32 dir, par, sor, odr, dat;
+ u32 res[3];
+};
+
is this really common for both CPM2 and 8xx? if so why the name?
It is common to CPM2 and Port E of CPM1.
but ports a-d are different on cpm1? I guess I'd like to see both
patches to understand the commonality and differences.
As Jorgen mentionned, both patches are still in patchwork:
http://patchwork.ozlabs.org/linuxppc/patch?id=19045
http://patchwork.ozlabs.org/linuxppc/patch?id=19386
Would it be possible for you to review them in time for 2.6.27 ?
--
Laurent Pinchart
CSE Semaphore Belgium
Chaussee de Bruxelles, 732A
B-1410 Waterloo
Belgium
T +32 (2) 387 42 59
F +32 (2) 387 42 75
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Re: [PATCHv3 1/2] [POWERPC] CPM2: Implement GPIO LIB API on CPM2 Freescale SoC.
On Jul 24, 2008, at 9:46 AM, Laurent Pinchart wrote:
Hi Kumar,
On Friday 18 July 2008, Kumar Gala wrote:
On Jul 18, 2008, at 10:30 AM, Jochen Friedrich wrote:
On Jun 18, 2008, at 12:08 PM, Laurent Pinchart wrote:
+#if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
+
+struct cpm2_ioports {
+ u32 dir, par, sor, odr, dat;
+ u32 res[3];
+};
+
is this really common for both CPM2 and 8xx? if so why the name?
It is common to CPM2 and Port E of CPM1.
but ports a-d are different on cpm1? I guess I'd like to see both
patches to understand the commonality and differences.
As Jorgen mentionned, both patches are still in patchwork:
http://patchwork.ozlabs.org/linuxppc/patch?id=19045
http://patchwork.ozlabs.org/linuxppc/patch?id=19386
Would it be possible for you to review them in time for 2.6.27 ?
Yes. Can you resend the first patch and add some details in the
commit message about the fact we can also use this code for 8xx/CPM1
port E.
- k
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Re: [PATCHv3 1/2] [POWERPC] CPM2: Implement GPIO LIB API on CPM2 Freescale SoC.
On Friday 27 June 2008, Jochen Friedrich wrote: Hi Laurent, Is there any pending issue or can this be applied to powerpc-next ? Looks OK to me. Signed-off-by: Laurent Pinchart [EMAIL PROTECTED] Cc: Jochen Friedrich [EMAIL PROTECTED] Acked-by: Jochen Friedrich [EMAIL PROTECTED] Any news on this patch ? Kumar, could you apply it to your tree for 2.6.27 ? Best regards, -- Laurent Pinchart CSE Semaphore Belgium Chaussee de Bruxelles, 732A B-1410 Waterloo Belgium T +32 (2) 387 42 59 F +32 (2) 387 42 75 signature.asc Description: This is a digitally signed message part. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCHv3 1/2] [POWERPC] CPM2: Implement GPIO LIB API on CPM2 Freescale SoC.
On Jul 18, 2008, at 9:38 AM, Laurent Pinchart wrote: On Friday 27 June 2008, Jochen Friedrich wrote: Hi Laurent, Is there any pending issue or can this be applied to powerpc-next ? Looks OK to me. Signed-off-by: Laurent Pinchart [EMAIL PROTECTED] Cc: Jochen Friedrich [EMAIL PROTECTED] Acked-by: Jochen Friedrich [EMAIL PROTECTED] Any news on this patch ? Kumar, could you apply it to your tree for 2.6.27 ? Can you repost it. I not sure what patch 2/2 was and if I've already dealt with it. - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCHv3 1/2] [POWERPC] CPM2: Implement GPIO LIB API on CPM2 Freescale SoC.
On Friday 18 July 2008, Kumar Gala wrote: On Jul 18, 2008, at 9:38 AM, Laurent Pinchart wrote: On Friday 27 June 2008, Jochen Friedrich wrote: Hi Laurent, Is there any pending issue or can this be applied to powerpc-next ? Looks OK to me. Signed-off-by: Laurent Pinchart [EMAIL PROTECTED] Cc: Jochen Friedrich [EMAIL PROTECTED] Acked-by: Jochen Friedrich [EMAIL PROTECTED] Any news on this patch ? Kumar, could you apply it to your tree for 2.6.27 ? Can you repost it. I not sure what patch 2/2 was and if I've already dealt with it. 2/2 was [PATCH2/2] [POWERPC] CPM1: implement GPIO LIB API on CPM1 Freescale SoC. posted by Jochen Friedrich. You haven't dealt with it yet as far as I know, but it would be up to Jochen to resubmit. The PATCHv3 1/2 patch can be considered as-is, as it doesn't depend on 2/2. Should I resubmit a PATCHv4 that just changes the subject line ? -- Laurent Pinchart CSE Semaphore Belgium Chaussee de Bruxelles, 732A B-1410 Waterloo Belgium T +32 (2) 387 42 59 F +32 (2) 387 42 75 signature.asc Description: This is a digitally signed message part. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCHv3 1/2] [POWERPC] CPM2: Implement GPIO LIB API on CPM2 Freescale SoC.
On Jul 18, 2008, at 10:07 AM, Laurent Pinchart wrote: On Friday 18 July 2008, Kumar Gala wrote: On Jul 18, 2008, at 9:38 AM, Laurent Pinchart wrote: On Friday 27 June 2008, Jochen Friedrich wrote: Hi Laurent, Is there any pending issue or can this be applied to powerpc- next ? Looks OK to me. Signed-off-by: Laurent Pinchart [EMAIL PROTECTED] Cc: Jochen Friedrich [EMAIL PROTECTED] Acked-by: Jochen Friedrich [EMAIL PROTECTED] Any news on this patch ? Kumar, could you apply it to your tree for 2.6.27 ? Can you repost it. I not sure what patch 2/2 was and if I've already dealt with it. 2/2 was [PATCH2/2] [POWERPC] CPM1: implement GPIO LIB API on CPM1 Freescale SoC. posted by Jochen Friedrich. You haven't dealt with it yet as far as I know, but it would be up to Jochen to resubmit. Since it sounds like CPM1 and CPM2 gpio are different I'd like a new patch. I'll send comments on v3. The PATCHv3 1/2 patch can be considered as-is, as it doesn't depend on 2/2. Should I resubmit a PATCHv4 that just changes the subject line ? You can generate a v4 w/my desired changes. - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCHv3 1/2] [POWERPC] CPM2: Implement GPIO LIB API on CPM2 Freescale SoC.
On Jun 18, 2008, at 12:08 PM, Laurent Pinchart wrote:
+#if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
+
+struct cpm2_ioports {
+ u32 dir, par, sor, odr, dat;
+ u32 res[3];
+};
+
is this really common for both CPM2 and 8xx? if so why the name?
- k
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Re: [PATCHv3 1/2] [POWERPC] CPM2: Implement GPIO LIB API on CPM2 Freescale SoC.
Hi Kumar,
On Jun 18, 2008, at 12:08 PM, Laurent Pinchart wrote:
+#if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
+
+struct cpm2_ioports {
+u32 dir, par, sor, odr, dat;
+u32 res[3];
+};
+
is this really common for both CPM2 and 8xx? if so why the name?
It is common to CPM2 and Port E of CPM1.
Thanks,
Jochen
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Re: [PATCHv3 1/2] [POWERPC] CPM2: Implement GPIO LIB API on CPM2 Freescale SoC.
On Jul 18, 2008, at 10:30 AM, Jochen Friedrich wrote:
Hi Kumar,
On Jun 18, 2008, at 12:08 PM, Laurent Pinchart wrote:
+#if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
+
+struct cpm2_ioports {
+ u32 dir, par, sor, odr, dat;
+ u32 res[3];
+};
+
is this really common for both CPM2 and 8xx? if so why the name?
It is common to CPM2 and Port E of CPM1.
but ports a-d are different on cpm1? I guess I'd like to see both
patches to understand the commonality and differences.
- k
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Re: [PATCHv3 1/2] [POWERPC] CPM2: Implement GPIO LIB API on CPM2 Freescale SoC.
Hi Kumar, but ports a-d are different on cpm1? I guess I'd like to see both patches to understand the commonality and differences. Yes. Both patches are still in patchwork: http://patchwork.ozlabs.org/linuxppc/patch?id=19045 http://patchwork.ozlabs.org/linuxppc/patch?id=19386 Thanks, Jochen ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCHv3 1/2] [POWERPC] CPM2: Implement GPIO LIB API on CPM2 Freescale SoC.
Hi Laurent, Is there any pending issue or can this be applied to powerpc-next ? Looks OK to me. Signed-off-by: Laurent Pinchart [EMAIL PROTECTED] Cc: Jochen Friedrich [EMAIL PROTECTED] Acked-by: Jochen Friedrich [EMAIL PROTECTED] Thanks, Jochen ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCHv3 1/2] [POWERPC] CPM2: Implement GPIO LIB API on CPM2 Freescale SoC.
On Wednesday 18 June 2008 19:08, Laurent Pinchart wrote:
Based on earlier work by Jochen Friedrich.
This patch implement GPIO LIB support for the CPM2 GPIOs.
Is there any pending issue or can this be applied to powerpc-next ?
Signed-off-by: Laurent Pinchart [EMAIL PROTECTED]
Cc: Jochen Friedrich [EMAIL PROTECTED]
---
arch/powerpc/platforms/Kconfig |2 +
arch/powerpc/sysdev/cpm2.c | 11
arch/powerpc/sysdev/cpm_common.c | 123
++
include/asm-powerpc/cpm.h|3 +
4 files changed, 139 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 87454c5..7e67e26 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -280,6 +280,8 @@ config CPM2
depends on MPC85xx || 8260
select CPM
select PPC_LIB_RHEAP
+ select GENERIC_GPIO
+ select HAVE_GPIO_LIB
help
The CPM2 (Communications Processor Module) is a coprocessor on
embedded CPUs made by Freescale. Selecting this option means that
diff --git a/arch/powerpc/sysdev/cpm2.c b/arch/powerpc/sysdev/cpm2.c
index 5a6c5df..9311778 100644
--- a/arch/powerpc/sysdev/cpm2.c
+++ b/arch/powerpc/sysdev/cpm2.c
@@ -377,3 +377,14 @@ void cpm2_set_pin(int port, int pin, int flags)
else
clrbits32(iop[port].odr, pin);
}
+
+static int cpm_init_par_io(void)
+{
+ struct device_node *np;
+
+ for_each_compatible_node(np, NULL, fsl,cpm2-pario-bank)
+ cpm2_gpiochip_add32(np);
+ return 0;
+}
+arch_initcall(cpm_init_par_io);
+
diff --git a/arch/powerpc/sysdev/cpm_common.c
b/arch/powerpc/sysdev/cpm_common.c
index cb7df2d..b957a48 100644
--- a/arch/powerpc/sysdev/cpm_common.c
+++ b/arch/powerpc/sysdev/cpm_common.c
@@ -19,6 +19,8 @@
#include linux/init.h
#include linux/of_device.h
+#include linux/spinlock.h
+#include linux/of.h
#include asm/udbg.h
#include asm/io.h
@@ -28,6 +30,10 @@
#include mm/mmu_decl.h
+#if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
+#include linux/of_gpio.h
+#endif
+
#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
static u32 __iomem *cpm_udbg_txdesc =
(u32 __iomem __force *)CONFIG_PPC_EARLY_DEBUG_CPM_ADDR;
@@ -198,3 +204,120 @@ dma_addr_t cpm_muram_dma(void __iomem *addr)
return muram_pbase + ((u8 __iomem *)addr - muram_vbase);
}
EXPORT_SYMBOL(cpm_muram_dma);
+
+#if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
+
+struct cpm2_ioports {
+ u32 dir, par, sor, odr, dat;
+ u32 res[3];
+};
+
+struct cpm2_gpio32_chip {
+ struct of_mm_gpio_chip mm_gc;
+ spinlock_t lock;
+
+ /* shadowed data register to clear/set bits safely */
+ u32 cpdata;
+};
+
+static inline struct cpm2_gpio32_chip *
+to_cpm2_gpio32_chip(struct of_mm_gpio_chip *mm_gc)
+{
+ return container_of(mm_gc, struct cpm2_gpio32_chip, mm_gc);
+}
+
+static void cpm2_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
+{
+ struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
+ struct cpm2_ioports __iomem *iop = mm_gc-regs;
+
+ cpm2_gc-cpdata = in_be32(iop-dat);
+}
+
+static int cpm2_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+ struct cpm2_ioports __iomem *iop = mm_gc-regs;
+ u32 pin_mask;
+
+ pin_mask = 1 (31 - gpio);
+
+ return !!(in_be32(iop-dat) pin_mask);
+}
+
+static void cpm2_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int
value)
+{
+ struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+ struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
+ struct cpm2_ioports __iomem *iop = mm_gc-regs;
+ unsigned long flags;
+ u32 pin_mask = 1 (31 - gpio);
+
+ spin_lock_irqsave(cpm2_gc-lock, flags);
+
+ if (value)
+ cpm2_gc-cpdata |= pin_mask;
+ else
+ cpm2_gc-cpdata = ~pin_mask;
+
+ out_be32(iop-dat, cpm2_gc-cpdata);
+
+ spin_unlock_irqrestore(cpm2_gc-lock, flags);
+}
+
+static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int
val)
+{
+ struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+ struct cpm2_ioports __iomem *iop = mm_gc-regs;
+ u32 pin_mask;
+
+ pin_mask = 1 (31 - gpio);
+
+ setbits32(iop-dir, pin_mask);
+
+ cpm2_gpio32_set(gc, gpio, val);
+
+ return 0;
+}
+
+static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+ struct cpm2_ioports __iomem *iop = mm_gc-regs;
+ u32 pin_mask;
+
+ pin_mask = 1 (31 - gpio);
+
+ clrbits32(iop-dir, pin_mask);
+
+ return 0;
+}
+
+int cpm2_gpiochip_add32(struct device_node *np)
+{
+ struct cpm2_gpio32_chip *cpm2_gc;
+ struct of_mm_gpio_chip *mm_gc;
+ struct of_gpio_chip *of_gc;
[PATCHv3 1/2] [POWERPC] CPM2: Implement GPIO LIB API on CPM2 Freescale SoC.
Based on earlier work by Jochen Friedrich.
This patch implement GPIO LIB support for the CPM2 GPIOs.
Signed-off-by: Laurent Pinchart [EMAIL PROTECTED]
Cc: Jochen Friedrich [EMAIL PROTECTED]
---
arch/powerpc/platforms/Kconfig |2 +
arch/powerpc/sysdev/cpm2.c | 11
arch/powerpc/sysdev/cpm_common.c | 123 ++
include/asm-powerpc/cpm.h|3 +
4 files changed, 139 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 87454c5..7e67e26 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -280,6 +280,8 @@ config CPM2
depends on MPC85xx || 8260
select CPM
select PPC_LIB_RHEAP
+ select GENERIC_GPIO
+ select HAVE_GPIO_LIB
help
The CPM2 (Communications Processor Module) is a coprocessor on
embedded CPUs made by Freescale. Selecting this option means that
diff --git a/arch/powerpc/sysdev/cpm2.c b/arch/powerpc/sysdev/cpm2.c
index 5a6c5df..9311778 100644
--- a/arch/powerpc/sysdev/cpm2.c
+++ b/arch/powerpc/sysdev/cpm2.c
@@ -377,3 +377,14 @@ void cpm2_set_pin(int port, int pin, int flags)
else
clrbits32(iop[port].odr, pin);
}
+
+static int cpm_init_par_io(void)
+{
+ struct device_node *np;
+
+ for_each_compatible_node(np, NULL, fsl,cpm2-pario-bank)
+ cpm2_gpiochip_add32(np);
+ return 0;
+}
+arch_initcall(cpm_init_par_io);
+
diff --git a/arch/powerpc/sysdev/cpm_common.c b/arch/powerpc/sysdev/cpm_common.c
index cb7df2d..b957a48 100644
--- a/arch/powerpc/sysdev/cpm_common.c
+++ b/arch/powerpc/sysdev/cpm_common.c
@@ -19,6 +19,8 @@
#include linux/init.h
#include linux/of_device.h
+#include linux/spinlock.h
+#include linux/of.h
#include asm/udbg.h
#include asm/io.h
@@ -28,6 +30,10 @@
#include mm/mmu_decl.h
+#if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
+#include linux/of_gpio.h
+#endif
+
#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
static u32 __iomem *cpm_udbg_txdesc =
(u32 __iomem __force *)CONFIG_PPC_EARLY_DEBUG_CPM_ADDR;
@@ -198,3 +204,120 @@ dma_addr_t cpm_muram_dma(void __iomem *addr)
return muram_pbase + ((u8 __iomem *)addr - muram_vbase);
}
EXPORT_SYMBOL(cpm_muram_dma);
+
+#if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
+
+struct cpm2_ioports {
+ u32 dir, par, sor, odr, dat;
+ u32 res[3];
+};
+
+struct cpm2_gpio32_chip {
+ struct of_mm_gpio_chip mm_gc;
+ spinlock_t lock;
+
+ /* shadowed data register to clear/set bits safely */
+ u32 cpdata;
+};
+
+static inline struct cpm2_gpio32_chip *
+to_cpm2_gpio32_chip(struct of_mm_gpio_chip *mm_gc)
+{
+ return container_of(mm_gc, struct cpm2_gpio32_chip, mm_gc);
+}
+
+static void cpm2_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
+{
+ struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
+ struct cpm2_ioports __iomem *iop = mm_gc-regs;
+
+ cpm2_gc-cpdata = in_be32(iop-dat);
+}
+
+static int cpm2_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+ struct cpm2_ioports __iomem *iop = mm_gc-regs;
+ u32 pin_mask;
+
+ pin_mask = 1 (31 - gpio);
+
+ return !!(in_be32(iop-dat) pin_mask);
+}
+
+static void cpm2_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
+{
+ struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+ struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
+ struct cpm2_ioports __iomem *iop = mm_gc-regs;
+ unsigned long flags;
+ u32 pin_mask = 1 (31 - gpio);
+
+ spin_lock_irqsave(cpm2_gc-lock, flags);
+
+ if (value)
+ cpm2_gc-cpdata |= pin_mask;
+ else
+ cpm2_gc-cpdata = ~pin_mask;
+
+ out_be32(iop-dat, cpm2_gc-cpdata);
+
+ spin_unlock_irqrestore(cpm2_gc-lock, flags);
+}
+
+static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int
val)
+{
+ struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+ struct cpm2_ioports __iomem *iop = mm_gc-regs;
+ u32 pin_mask;
+
+ pin_mask = 1 (31 - gpio);
+
+ setbits32(iop-dir, pin_mask);
+
+ cpm2_gpio32_set(gc, gpio, val);
+
+ return 0;
+}
+
+static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+ struct cpm2_ioports __iomem *iop = mm_gc-regs;
+ u32 pin_mask;
+
+ pin_mask = 1 (31 - gpio);
+
+ clrbits32(iop-dir, pin_mask);
+
+ return 0;
+}
+
+int cpm2_gpiochip_add32(struct device_node *np)
+{
+ struct cpm2_gpio32_chip *cpm2_gc;
+ struct of_mm_gpio_chip *mm_gc;
+ struct of_gpio_chip *of_gc;
+ struct gpio_chip *gc;
+
+ cpm2_gc = kzalloc(sizeof(*cpm2_gc), GFP_KERNEL);
+ if (!cpm2_gc)
+ return -ENOMEM;
+
+
