Re: [PATCH v3 3/3] powerpc/fsl: 85xx: add cache-sram support
Mahajan Vivek-B08308 wrote: From: Wood Scott-B07421 Sent: Friday, November 20, 2009 11:09 PM Cache-sram does not have any device tree entry since it is not a hardware as such. Putting it under chosen can be another option. I think, Scott (cc'ed) was of the opinion that since 32b base address support is missing; so there is no point in moving this address to the command line and .config should be okay for now for it. I don't know what you mean by 32b base address support is missing. I have no objection to putting it on the command line. It was a typo, it should be missing 36b address support. Since the kernel did not run under different environment (i.e 32b / 36b base address); so it was decided that .config may be okay for this. The kernel *will* run with a 36-bit address map even if some of our drivers don't support it right at the moment -- so we should be planning for it. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v3 3/3] powerpc/fsl: 85xx: add cache-sram support
On Dec 1, 2009, at 11:04 AM, Scott Wood wrote: Mahajan Vivek-B08308 wrote: From: Wood Scott-B07421 Sent: Friday, November 20, 2009 11:09 PM Cache-sram does not have any device tree entry since it is not a hardware as such. Putting it under chosen can be another option. I think, Scott (cc'ed) was of the opinion that since 32b base address support is missing; so there is no point in moving this address to the command line and .config should be okay for now for it. I don't know what you mean by 32b base address support is missing. I have no objection to putting it on the command line. It was a typo, it should be missing 36b address support. Since the kernel did not run under different environment (i.e 32b / 36b base address); so it was decided that .config may be okay for this. The kernel *will* run with a 36-bit address map even if some of our drivers don't support it right at the moment -- so we should be planning for it. Not only that but I'd like to move any future parts to only support a 36-bit memory map. - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH v3 3/3] powerpc/fsl: 85xx: add cache-sram support
From: Wood Scott-B07421 Sent: Friday, November 20, 2009 11:09 PM Cache-sram does not have any device tree entry since it is not a hardware as such. Putting it under chosen can be another option. I think, Scott (cc'ed) was of the opinion that since 32b base address support is missing; so there is no point in moving this address to the command line and .config should be okay for now for it. I don't know what you mean by 32b base address support is missing. I have no objection to putting it on the command line. It was a typo, it should be missing 36b address support. Since the kernel did not run under different environment (i.e 32b / 36b base address); so it was decided that .config may be okay for this. -Scott Thanks, Vivek ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v3 3/3] powerpc/fsl: 85xx: add cache-sram support
On Thu, Nov 19, 2009 at 11:45:32PM -0700, Mahajan Vivek-B08308 wrote: I really don't like setting the physical address this way, can we not do this via the device tree? Cache-sram does not have any device tree entry since it is not a hardware as such. Putting it under chosen can be another option. I think, Scott (cc'ed) was of the opinion that since 32b base address support is missing; so there is no point in moving this address to the command line and .config should be okay for now for it. I don't know what you mean by 32b base address support is missing. I have no objection to putting it on the command line. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v3 3/3] powerpc/fsl: 85xx: add cache-sram support
On Oct 21, 2009, at 7:50 AM, Vivek Mahajan wrote:
This adds QorIQ based Cache-SRAM support as under:-
* A small abstraction over powerpc's remote heap allocator
* Exports mpc85xx_cache_sram_alloc()/free() APIs
* Supports only one contiguous SRAM window
* Defines FSL_85XX_CACHE_SRAM and its base address
Signed-off-by: Vivek Mahajan vivek.maha...@freescale.com
---
v2: mbar(1) - eieio() as per Kumar G.
v3: Fixed cache-sram ways computation
arch/powerpc/include/asm/fsl_85xx_cache_sram.h | 48 ++
arch/powerpc/platforms/85xx/Kconfig|9 ++
arch/powerpc/sysdev/Makefile |1 +
arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h | 95
arch/powerpc/sysdev/fsl_85xx_cache_sram.c | 141 +++
+++
arch/powerpc/sysdev/fsl_85xx_l2ctlr.c | 184 +++
+
6 files changed, 478 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/include/asm/fsl_85xx_cache_sram.h
create mode 100644 arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
create mode 100644 arch/powerpc/sysdev/fsl_85xx_cache_sram.c
create mode 100644 arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
diff --git a/arch/powerpc/include/asm/fsl_85xx_cache_sram.h b/arch/
powerpc/include/asm/fsl_85xx_cache_sram.h
new file mode 100644
index 000..2af2bdc
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_85xx_cache_sram.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * Cache SRAM handling for QorIQ platform
should say PQ3 some QorIQ platforms
+ *
+ * Author: Vivek Mahajan vivek.maha...@freescale.com
+
+ * This file is derived from the original work done
+ * by Sylvain Munaut for the Bestcomm SRAM allocator.
+ *
+ * This program is free software; you can redistribute it and/or
modify it
+ * under the terms of the GNU General Public License as
published by the
+ * Free Software Foundation; either version 2 of the License, or
(at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_POWERPC_FSL_85XX_CACHE_SRAM_H__
+#define __ASM_POWERPC_FSL_85XX_CACHE_SRAM_H__
+
+#include asm/rheap.h
+#include linux/spinlock.h
+
+/*
+ * Cache-SRAM
+ */
+
+struct mpc85xx_cache_sram {
+ phys_addr_t base_phys;
+ void *base_virt;
+ unsigned int size;
+ rh_info_t *rh;
+ spinlock_t lock;
+};
+
+extern void mpc85xx_cache_sram_free(void *ptr);
+extern void *mpc85xx_cache_sram_alloc(unsigned int size,
+ phys_addr_t *phys, unsigned int align);
+
+#endif /* __AMS_POWERPC_FSL_85XX_CACHE_SRAM_H__ */
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/
platforms/85xx/Kconfig
index d3a975e..b6f23c3 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -144,6 +144,15 @@ config SBC8560
help
This option enables support for the Wind River SBC8560 board
+config FSL_85XX_CACHE_SRAM
+ bool
+ select PPC_LIB_RHEAP
+
+config FSL_85XX_CACHE_SRAM_BASE
+ hex
+ depends on FSL_85XX_CACHE_SRAM
+ default 0xfff0
+
I really don't like setting the physical address this way, can we not
do this via the device tree?
endif # MPC85xx
config TQM85xx
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/
Makefile
index 9d4b174..745994c 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_FSL_PCI) += fsl_pci.o $(fsl-msi-obj-y)
obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
obj-$(CONFIG_FSL_GTM) += fsl_gtm.o
obj-$(CONFIG_MPC8xxx_GPIO) += mpc8xxx_gpio.o
+obj-$(CONFIG_FSL_85XX_CACHE_SRAM) += fsl_85xx_l2ctlr.o
fsl_85xx_cache_sram.o
obj-$(CONFIG_SIMPLE_GPIO) += simple_gpio.o
obj-$(CONFIG_RAPIDIO) += fsl_rio.o
obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
diff --git a/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h b/arch/
powerpc/sysdev/fsl_85xx_cache_ctlr.h
new file mode 100644
index 000..8c4a4ac
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc
+ *
+ * QorIQ based Cache Controller Memory Mapped Registers
PQ3 or some QorIQ
+ *
+ * Author: Vivek Mahajan vivek.maha...@freescale.com
+ *
+ * This program is free software; you can redistribute it and/or
modify it
+ * under the terms of the GNU General Public License as
published by the
+ * Free Software Foundation; either version 2 of the License, or
(at your
+ * option) any later version.
+ *
+ * This program is
Re: [PATCH v3 3/3] powerpc/fsl: 85xx: add cache-sram support
On Nov 19, 2009, at 8:21 AM, Kumar Gala wrote:
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/
platforms/85xx/Kconfig
index d3a975e..b6f23c3 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -144,6 +144,15 @@ config SBC8560
help
This option enables support for the Wind River SBC8560 board
+config FSL_85XX_CACHE_SRAM
+ bool
+ select PPC_LIB_RHEAP
+
+config FSL_85XX_CACHE_SRAM_BASE
+ hex
+ depends on FSL_85XX_CACHE_SRAM
+ default 0xfff0
+
I really don't like setting the physical address this way, can we
not do this via the device tree?
At a high level I think we should add something like the following in
the .dts:
s...@fff0 {
fsl,sram-ctrl-handle = L2;
reg = 0xfff0 0x;
compatible = fsl,mpc85xx-l2-sram;
}
the can be the size the sram is configured as.
- k
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Re: [PATCH v3 3/3] powerpc/fsl: 85xx: add cache-sram support
On Thu, Nov 19, 2009 at 08:29:19AM -0600, Kumar Gala wrote:
+config FSL_85XX_CACHE_SRAM_BASE
+ hex
+ depends on FSL_85XX_CACHE_SRAM
+ default 0xfff0
+
I really don't like setting the physical address this way, can we
not do this via the device tree?
At a high level I think we should add something like the following in
the .dts:
s...@fff0 {
fsl,sram-ctrl-handle = L2;
reg = 0xfff0 0x;
compatible = fsl,mpc85xx-l2-sram;
}
the can be the size the sram is configured as.
I don't see why this needs to go in the device tree, if it's the kernel
that is setting it up. The kernel can pick any address and size it
wants.
-Scott
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Re: [PATCH v3 3/3] powerpc/fsl: 85xx: add cache-sram support
On Nov 19, 2009, at 11:45 AM, Scott Wood wrote:
On Thu, Nov 19, 2009 at 08:29:19AM -0600, Kumar Gala wrote:
+config FSL_85XX_CACHE_SRAM_BASE
+ hex
+ depends on FSL_85XX_CACHE_SRAM
+ default 0xfff0
+
I really don't like setting the physical address this way, can we
not do this via the device tree?
At a high level I think we should add something like the following in
the .dts:
s...@fff0 {
fsl,sram-ctrl-handle = L2;
reg = 0xfff0 0x;
compatible = fsl,mpc85xx-l2-sram;
}
the can be the size the sram is configured as.
I don't see why this needs to go in the device tree, if it's the
kernel
that is setting it up. The kernel can pick any address and size it
wants.
It can, we just don't normally do physical address allocation in the
kernel. I just dont want it as a compile time thing. Either .dts or
make it runtime allocated by the kernel.
- k
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RE: [PATCH v3 3/3] powerpc/fsl: 85xx: add cache-sram support
From: Gala Kumar-B11780 Sent: Thursday, November 19, 2009 7:51 PM + * Cache SRAM handling for QorIQ platform should say PQ3 some QorIQ platforms Ok +config FSL_85XX_CACHE_SRAM_BASE + hex + depends on FSL_85XX_CACHE_SRAM + default 0xfff0 + I really don't like setting the physical address this way, can we not do this via the device tree? Cache-sram does not have any device tree entry since it is not a hardware as such. Putting it under chosen can be another option. I think, Scott (cc'ed) was of the opinion that since 32b base address support is missing; so there is no point in moving this address to the command line and .config should be okay for now for it. + * QorIQ based Cache Controller Memory Mapped Registers PQ3 or some QorIQ Ok + * Simple memory allocator abstraction for QorIQ (P1/P2) based Cache-SRAM PQ3 or some QorIQ Ok + + if (!param || (strict_strtoul(param, 0, val) 0)) + return -EINVAL; + we should use memparse() Ok Thanks, Vivek ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
