Re: How to use ramdisk on the ml300?
Hi Yanlong, On Thu, Aug 14, 2008 at 5:08 AM, yanlong wang [EMAIL PROTECTED] wrote: If i want use ramdisk on the ml300 , i must use u-boot in my system ? many thanks I suppose you want to use an initial ram filesystem as rootfs to boot your system? You have to point CONFIG_INITRAMFS_SOURCE= to a cpio archive or a directory which contains your rootfs. If you use a directory structure then you should set your uid/gid to make the build process convert the owner to root: # if your uid/gid is 500: CONFIG_INITRAMFS_ROOT_UID=500 CONFIG_INITRAMFS_ROOT_GID=500 Don't forget to set CONFIG_BLK_DEV_RAM=y to be able to use a ramdisk at all. I'm also using the ml300 board and I create my kernel with: make simpleImage.virtex405-ml300 My dts is arch/powerpc/boot/dts/virtex405-ml300.dts. There is no kernel boot command line needed to use the initramfs in my case (I only set up my console to the uart). Just download the image arch/powerpc/boot/simpleImage.virtex405-ml300.elf with xmd to your ml300 and run it. I hope this works for you. Regards Jens ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
Re: How to use ramdisk on the ml300?
Hi JensWirth, Thanks for your reply :). I have some questions here. (1)You told me make simpleImage.virtex405-ml300,i only know make zImage and make zImage.initrd ,what it is this command mean??? (2)What is dts ? I don't know what is this :( Regards, YanLong:) Jens Wirth wrote: Hi Yanlong, On Thu, Aug 14, 2008 at 5:08 AM, yanlong wang [EMAIL PROTECTED] wrote: If i want use ramdisk on the ml300 , i must use u-boot in my system ? many thanks I suppose you want to use an initial ram filesystem as rootfs to boot your system? You have to point CONFIG_INITRAMFS_SOURCE= to a cpio archive or a directory which contains your rootfs. If you use a directory structure then you should set your uid/gid to make the build process convert the owner to root: # if your uid/gid is 500: CONFIG_INITRAMFS_ROOT_UID=500 CONFIG_INITRAMFS_ROOT_GID=500 Don't forget to set CONFIG_BLK_DEV_RAM=y to be able to use a ramdisk at all. I'm also using the ml300 board and I create my kernel with: make simpleImage.virtex405-ml300 My dts is arch/powerpc/boot/dts/virtex405-ml300.dts. There is no kernel boot command line needed to use the initramfs in my case (I only set up my console to the uart). Just download the image arch/powerpc/boot/simpleImage.virtex405-ml300.elf with xmd to your ml300 and run it. I hope this works for you. Regards Jens ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded -- View this message in context: http://www.nabble.com/How-to-use-ramdisk-on-the-ml300--tp18975066p18979320.html Sent from the linuxppc-embedded mailing list archive at Nabble.com. ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
[PATCH] RE: Some memory (DDR2 ECC Dual Rank) just doesn't work! Can anyone pointme to how to debug this hang?
Vince Asbridge wrote: We have an 8548 design, which implements a DDR2 on a SODIMM We have an issue with dual rank memory (specific part number Viking VR5DR287218EBSS1), which is a 1G ECC Registered SODIMM part, with two ranks. Our platform wires CS0 and CS1 to the SODIMM slot. At uBoot, all is well. Memory is discovered as ECC 533, 1G DDR2 64Bit 4 beat bursts, and mtest can read and write all 1G of the SODIMM. [...] Other DDR2s (identical except for vendor and # of ranks), work perfectly! Anyone got a clue what I could look at to try to figure this out? We've tried enable / disable ECC at uboot We've tried enable / disable Interleaving at uboot uboot always works (and can read/write entire DDR), Linux always hangs on boot! U-Boot is too gentle when testing SDRAM. Make sure the caches are enabled under U-Boot, and put on heavy stress with DMA, pipelined prefetch's, etc. This is what your CPU is enduring under Linux. Your question is definitely a question for the U-Boot mailing list. BTW, what is the version of U-Boot in use? U-Boot is still missing the following patch: MPC85xx BA bits not set for 3-bit bank address DIMM of CS1 The current implementation set the number of bank address bits (BA) in the processor for CS0 but not for CS1. Signed-off-by: Stephane Fillod [EMAIL PROTECTED] --- u-boot/cpu/mpc85xx/spd_sdram.c +++ u-boot/cpu/mpc85xx/spd_sdram.c @@ -365,6 +365,7 @@ ddr-cs1_config = ( 131 | (odt_rd_cfg 20) | (odt_wr_cfg 16) + | (ba_bits 14) | (spd.nrow_addr - 12) 8 | (spd.ncol_addr - 8) ); debug(DDR: cs1_bnds = 0x%08x\n, ddr-cs1_bnds); Otherwise, recompile with -DDEBUG and CFG_CMD_SDRAM, grab the Viking datasheet and a scope, and a full cup of coffee/tea much needed during cross-checking :-) Cheers -- Stephane ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
Re: How to use ramdisk on the ml300?
Hi On Thu, Aug 14, 2008 at 12:44 PM, wangyanlong [EMAIL PROTECTED] wrote: Hi JensWirth, Thanks for your reply :). I have some questions here. (1)You told me make simpleImage.virtex405-ml300,i only know make zImage and make zImage.initrd ,what it is this command mean??? It's a relatively new target in the arch/powerpc/boot/Makefile which wraps your compressed kernel and bootcode together with a device tree blob. A device tree blob is created using a device tree source (dts). (2)What is dts ? I don't know what is this :( A device tree source is plain text. Look inside arch/powerpc/boot/dts. A device tree is essential if you want to boot an ARCH=powerpc Linux-Kernel. Read this: http://ols.fedoraproject.org/OLS/Reprints-2008/likely2-reprint.pdf I supposed you were using 2.6.26 or 2.6.27-rcX Regards Jens ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
RPC source code
Where in the heck does one find the source code for RPC? I need to cross compile it... ideas?? thanks. -stv -- /* * Steve Iribarne * Software Engineer * (aka Grunt) */ ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
RE: [PATCH] RE: Some memory (DDR2 ECC Dual Rank) just doesn't work! Can anyone pointme to how to debug this hang?
Stephane, Thanks so much for your prompt reply. We will pursue your suggestions, and let the forum know what we find. We're at 1.3.0 uboot version. Vince -Original Message- From: Fillod Stephane [mailto:[EMAIL PROTECTED] Sent: Thursday, August 14, 2008 8:06 AM To: Vince Asbridge; linuxppc-embedded Cc: [EMAIL PROTECTED] Subject: [PATCH] RE: Some memory (DDR2 ECC Dual Rank) just doesn't work! Can anyone pointme to how to debug this hang? Vince Asbridge wrote: We have an 8548 design, which implements a DDR2 on a SODIMM We have an issue with dual rank memory (specific part number Viking VR5DR287218EBSS1), which is a 1G ECC Registered SODIMM part, with two ranks. Our platform wires CS0 and CS1 to the SODIMM slot. At uBoot, all is well. Memory is discovered as ECC 533, 1G DDR2 64Bit 4 beat bursts, and mtest can read and write all 1G of the SODIMM. [...] Other DDR2s (identical except for vendor and # of ranks), work perfectly! Anyone got a clue what I could look at to try to figure this out? We've tried enable / disable ECC at uboot We've tried enable / disable Interleaving at uboot uboot always works (and can read/write entire DDR), Linux always hangs on boot! U-Boot is too gentle when testing SDRAM. Make sure the caches are enabled under U-Boot, and put on heavy stress with DMA, pipelined prefetch's, etc. This is what your CPU is enduring under Linux. Your question is definitely a question for the U-Boot mailing list. BTW, what is the version of U-Boot in use? U-Boot is still missing the following patch: MPC85xx BA bits not set for 3-bit bank address DIMM of CS1 The current implementation set the number of bank address bits (BA) in the processor for CS0 but not for CS1. Signed-off-by: Stephane Fillod [EMAIL PROTECTED] --- u-boot/cpu/mpc85xx/spd_sdram.c +++ u-boot/cpu/mpc85xx/spd_sdram.c @@ -365,6 +365,7 @@ ddr-cs1_config = ( 131 | (odt_rd_cfg 20) | (odt_wr_cfg 16) + | (ba_bits 14) | (spd.nrow_addr - 12) 8 | (spd.ncol_addr - 8) ); debug(DDR: cs1_bnds = 0x%08x\n, ddr-cs1_bnds); Otherwise, recompile with -DDEBUG and CFG_CMD_SDRAM, grab the Viking datasheet and a scope, and a full cup of coffee/tea much needed during cross-checking :-) Cheers -- Stephane ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
Re: [PATCH] RE: Some memory (DDR2 ECC Dual Rank) just doesn't work! Can anyone pointme to how to debug this hang?
Vince Asbridge wrote: Stephane, Thanks so much for your prompt reply. We will pursue your suggestions, and let the forum know what we find. We're at 1.3.0 uboot version. Vince -Original Message- From: Fillod Stephane [mailto:[EMAIL PROTECTED] Sent: Thursday, August 14, 2008 8:06 AM To: Vince Asbridge; linuxppc-embedded Cc: [EMAIL PROTECTED] Subject: [PATCH] RE: Some memory (DDR2 ECC Dual Rank) just doesn't work! Can anyone pointme to how to debug this hang? Vince Asbridge wrote: We have an 8548 design, which implements a DDR2 on a SODIMM We have an issue with dual rank memory (specific part number Viking VR5DR287218EBSS1), which is a 1G ECC Registered SODIMM part, with two ranks. Our platform wires CS0 and CS1 to the SODIMM slot. At uBoot, all is well. Memory is discovered as ECC 533, 1G DDR2 64Bit 4 beat bursts, and mtest can read and write all 1G of the SODIMM. [...] Other DDR2s (identical except for vendor and # of ranks), work perfectly! Anyone got a clue what I could look at to try to figure this out? We've tried enable / disable ECC at uboot We've tried enable / disable Interleaving at uboot uboot always works (and can read/write entire DDR), Linux always hangs on boot! U-Boot is too gentle when testing SDRAM. Make sure the caches are enabled under U-Boot, and put on heavy stress with DMA, pipelined prefetch's, etc. This is what your CPU is enduring under Linux. Your question is definitely a question for the U-Boot mailing list. BTW, what is the version of U-Boot in use? U-Boot is still missing the following patch: MPC85xx BA bits not set for 3-bit bank address DIMM of CS1 The current implementation set the number of bank address bits (BA) in the processor for CS0 but not for CS1. Signed-off-by: Stephane Fillod [EMAIL PROTECTED] --- u-boot/cpu/mpc85xx/spd_sdram.c +++ u-boot/cpu/mpc85xx/spd_sdram.c @@ -365,6 +365,7 @@ ddr-cs1_config = ( 131 | (odt_rd_cfg 20) | (odt_wr_cfg 16) + | (ba_bits 14) | (spd.nrow_addr - 12) 8 | (spd.ncol_addr - 8) ); debug(DDR: cs1_bnds = 0x%08x\n, ddr-cs1_bnds); Otherwise, recompile with -DDEBUG and CFG_CMD_SDRAM, grab the Viking datasheet and a scope, and a full cup of coffee/tea much needed during cross-checking :-) That bug fix, along with many, many others, as well as some new support for multiple controllers and such are all present in the DDR re-write patch set that Kumar just posted. You may want to try that code too. It will be replacing the entire 85xx/86xx and eventually the 83xx line of memory controller initialization. It also contains some support for a pretty useful interactive DDR configuration setup mechanism too. jdl ___ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
