Re: MPC8313 ERDB has proper interrupt mapping for TSEC?

2008-07-15 Thread Kumar Gala 


On Jul 14, 2008, at 7:14 AM, selvamuthukumar v wrote:


From, arch/powerpc/boot/dts/mpc8313erdb.dts,

212 enet0: [EMAIL PROTECTED] {
  .
  .
219 interrupts = 37 0x8 36 0x8 35 0x8;
  .
  .
222 };
223
224 enet1: [EMAIL PROTECTED] {
  .
  .
231 interrupts = 34 0x8 33 0x8 32 0x8;
  .
234 };
235

But as per 8313 Reference manual interrups 32, 33, 34 are for
[EMAIL PROTECTED] and 35, 36, 37 are for [EMAIL PROTECTED] Any idea why 
interrupt
numbers are swapped for enet0 and enet1?


I believe different revisions of the part had different mappings.

- k
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MPC8313 ERDB has proper interrupt mapping for TSEC?

2008-07-14 Thread selvamuthukumar v 
From, arch/powerpc/boot/dts/mpc8313erdb.dts,

212 enet0: [EMAIL PROTECTED] {
   .
   .
219 interrupts = 37 0x8 36 0x8 35 0x8;
   .
   .
222 };
223
224 enet1: [EMAIL PROTECTED] {
   .
   .
231 interrupts = 34 0x8 33 0x8 32 0x8;
   .
234 };
235

But as per 8313 Reference manual interrups 32, 33, 34 are for
[EMAIL PROTECTED] and 35, 36, 37 are for [EMAIL PROTECTED] Any idea why 
interrupt
numbers are swapped for enet0 and enet1?

-- 
Selva
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