from:"Nitesh Jain via lldb\-commits"

[Lldb-commits] [lldb] r310856 - [LLDB][MIPS] Fix process load/unload on android.

2017-08-14 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Mon Aug 14 09:39:16 2017
New Revision: 310856

URL: http://llvm.org/viewvc/llvm-project?rev=310856=rev
Log:
[LLDB][MIPS] Fix process load/unload on android.

To detect the correct function name based on the list of available symbols 
instead of the SDK version

Reviewers: tberghammer, clayborg

Subscribers: jaydeep, bhushan, lldb-commits

Differential Revision: https://reviews.llvm.org/D36445

Modified:
lldb/trunk/source/Plugins/Platform/Android/PlatformAndroid.cpp
lldb/trunk/source/Plugins/Platform/Android/PlatformAndroid.h
lldb/trunk/source/Plugins/Platform/POSIX/PlatformPOSIX.cpp
lldb/trunk/source/Plugins/Platform/POSIX/PlatformPOSIX.h

Modified: lldb/trunk/source/Plugins/Platform/Android/PlatformAndroid.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Platform/Android/PlatformAndroid.cpp?rev=310856=310855=310856=diff
==
--- lldb/trunk/source/Plugins/Platform/Android/PlatformAndroid.cpp (original)
+++ lldb/trunk/source/Plugins/Platform/Android/PlatformAndroid.cpp Mon Aug 14 
09:39:16 2017
@@ -21,6 +21,7 @@
 #include "AdbClient.h"
 #include "PlatformAndroid.h"
 #include "PlatformAndroidRemoteGDBServer.h"
+#include "lldb/Target/Target.h"
 
 using namespace lldb;
 using namespace lldb_private;
@@ -366,9 +367,22 @@ bool PlatformAndroid::GetRemoteOSVersion
   return m_major_os_version != 0;
 }
 
-llvm::StringRef PlatformAndroid::GetLibdlFunctionDeclarations() {
+llvm::StringRef
+PlatformAndroid::GetLibdlFunctionDeclarations(lldb_private::Process *process) {
+  SymbolContextList matching_symbols;
+  std::vector dl_open_names = { "__dl_dlopen", "dlopen" };
+  const char *dl_open_name = nullptr;
+  Target  = process->GetTarget();
+  for (auto name: dl_open_names) {
+if (target.GetImages().FindFunctionSymbols(ConstString(name),
+   eFunctionNameTypeFull,
+   matching_symbols)) {
+   dl_open_name = name;
+   break;
+}
+  }
   // Older platform versions have the dl function symbols mangled
-  if (GetSdkVersion() < 26)
+  if (dl_open_name == dl_open_names[0])
 return R"(
   extern "C" void* dlopen(const char*, int) asm("__dl_dlopen");
   extern "C" void* dlsym(void*, const char*) asm("__dl_dlsym");
@@ -376,7 +390,7 @@ llvm::StringRef PlatformAndroid::GetLibd
   extern "C" char* dlerror(void) asm("__dl_dlerror");
  )";
 
-  return PlatformPOSIX::GetLibdlFunctionDeclarations();
+  return PlatformPOSIX::GetLibdlFunctionDeclarations(process);
 }
 
 AdbClient::SyncService *PlatformAndroid::GetSyncService(Status ) {

Modified: lldb/trunk/source/Plugins/Platform/Android/PlatformAndroid.h
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Platform/Android/PlatformAndroid.h?rev=310856=310855=310856=diff
==
--- lldb/trunk/source/Plugins/Platform/Android/PlatformAndroid.h (original)
+++ lldb/trunk/source/Plugins/Platform/Android/PlatformAndroid.h Mon Aug 14 
09:39:16 2017
@@ -76,7 +76,8 @@ protected:
   Status DownloadSymbolFile(const lldb::ModuleSP _sp,
 const FileSpec _file_spec) override;
 
-  llvm::StringRef GetLibdlFunctionDeclarations() override;
+  llvm::StringRef
+  GetLibdlFunctionDeclarations(lldb_private::Process *process) override;
 
 private:
   AdbClient::SyncService *GetSyncService(Status );

Modified: lldb/trunk/source/Plugins/Platform/POSIX/PlatformPOSIX.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Platform/POSIX/PlatformPOSIX.cpp?rev=310856=310855=310856=diff
==
--- lldb/trunk/source/Plugins/Platform/POSIX/PlatformPOSIX.cpp (original)
+++ lldb/trunk/source/Plugins/Platform/POSIX/PlatformPOSIX.cpp Mon Aug 14 
09:39:16 2017
@@ -944,7 +944,7 @@ uint32_t PlatformPOSIX::DoLoadImage(lldb
the_result;
   )",
   path);
-  llvm::StringRef prefix = GetLibdlFunctionDeclarations();
+  llvm::StringRef prefix = GetLibdlFunctionDeclarations(process);
   lldb::ValueObjectSP result_valobj_sp;
   error = EvaluateLibdlExpression(process, expr.GetData(), prefix,
   result_valobj_sp);
@@ -992,7 +992,7 @@ Status PlatformPOSIX::UnloadImage(lldb_p
 
   StreamString expr;
   expr.Printf("dlclose((void *)0x%" PRIx64 ")", image_addr);
-  llvm::StringRef prefix = GetLibdlFunctionDeclarations();
+  llvm::StringRef prefix = GetLibdlFunctionDeclarations(process);
   lldb::ValueObjectSP result_valobj_sp;
   Status error = EvaluateLibdlExpression(process, expr.GetData(), prefix,
  result_valobj_sp);
@@ -1024,7 +1024,8 @@ lldb::ProcessSP PlatformPOSIX::ConnectPr
   error);
 }

[Lldb-commits] [lldb] r310855 - [LLDB][MIPS] Set the Section's file address for

2017-08-14 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Mon Aug 14 09:30:25 2017
New Revision: 310855

URL: http://llvm.org/viewvc/llvm-project?rev=310855=rev
Log:
[LLDB][MIPS] Set the Section's file address for
ELF section to LLDB_INVALID_ADDRESS if SHF_ALLOC is not set.

Reviewers: labath, clayborg

Subscribers: jaydeep, bhushan, lldb-commits

Differential Revision: https://reviews.llvm.org/D35784

Modified:
lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp

Modified: lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp?rev=310855=310854=310855=diff
==
--- lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp (original)
+++ lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp Mon Aug 14 
09:30:25 2017
@@ -1987,7 +1987,9 @@ void ObjectFileELF::CreateSections(Secti
   ? m_arch_spec.GetDataByteSize()
   : eSectionTypeCode == sect_type ? m_arch_spec.GetCodeByteSize()
   : 1;
-
+  const addr_t sect_file_addr = header.sh_flags & SHF_ALLOC
+? header.sh_addr
+: LLDB_INVALID_ADDRESS;
   elf::elf_xword log2align =
   (header.sh_addralign == 0) ? 0 : llvm::Log2_64(header.sh_addralign);
   SectionSP section_sp(new Section(
@@ -1997,7 +1999,7 @@ void ObjectFileELF::CreateSections(Secti
   SectionIndex(I), // Section ID.
   name,// Section name.
   sect_type,   // Section type.
-  header.sh_addr,  // VM address.
+  sect_file_addr,  // VM address.
   vm_size, // VM size in bytes of this section.
   header.sh_offset,// Offset of this section in the file.
   file_size,   // Size of the section as found in the file.


___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] r309250 - [LLDB][MIPS] Fix emulation of Instruction for MIPS64R6 target.

2017-07-26 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Wed Jul 26 22:34:33 2017
New Revision: 309250

URL: http://llvm.org/viewvc/llvm-project?rev=309250=rev
Log:
[LLDB][MIPS] Fix emulation of Instruction for MIPS64R6 target.

Subscribers: jaydeep, bhushan, lldb-commits, slthakur

Modified:
lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp

Modified: 
lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp?rev=309250=309249=309250=diff
==
--- lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp 
(original)
+++ lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp 
Wed Jul 26 22:34:33 2017
@@ -801,7 +801,9 @@ EmulateInstructionMIPS64::GetOpcodeForIn
   // Branch instructions
   //--
   {"BEQ", ::Emulate_BXX_3ops, "BEQ rs,rt,offset"},
+  {"BEQ64", ::Emulate_BXX_3ops, "BEQ 
rs,rt,offset"},
   {"BNE", ::Emulate_BXX_3ops, "BNE rs,rt,offset"},
+  {"BNE64", ::Emulate_BXX_3ops, "BNE 
rs,rt,offset"},
   {"BEQL", ::Emulate_BXX_3ops,
"BEQL rs,rt,offset"},
   {"BNEL", ::Emulate_BXX_3ops,
@@ -814,6 +816,7 @@ EmulateInstructionMIPS64::GetOpcodeForIn
   {"BALC", ::Emulate_BALC, "BALC offset"},
   {"BC", ::Emulate_BC, "BC offset"},
   {"BGEZ", ::Emulate_BXX_2ops, "BGEZ rs,offset"},
+  {"BGEZ64", ::Emulate_BXX_2ops, "BGEZ 
rs,offset"},
   {"BLEZALC", ::Emulate_Bcond_Link_C,
"BLEZALC rs,offset"},
   {"BGEZALC", ::Emulate_Bcond_Link_C,
@@ -828,34 +831,61 @@ EmulateInstructionMIPS64::GetOpcodeForIn
"BNEZALC rs,offset"},
   {"BEQC", ::Emulate_BXX_3ops_C,
"BEQC rs,rt,offset"},
+  {"BEQC64", ::Emulate_BXX_3ops_C,
+   "BEQC rs,rt,offset"},
   {"BNEC", ::Emulate_BXX_3ops_C,
"BNEC rs,rt,offset"},
+  {"BNEC64", ::Emulate_BXX_3ops_C,
+   "BNEC rs,rt,offset"},
   {"BLTC", ::Emulate_BXX_3ops_C,
"BLTC rs,rt,offset"},
+  {"BLTC64", ::Emulate_BXX_3ops_C,
+   "BLTC rs,rt,offset"},
   {"BGEC", ::Emulate_BXX_3ops_C,
"BGEC rs,rt,offset"},
+  {"BGEC64", ::Emulate_BXX_3ops_C,
+   "BGEC rs,rt,offset"},
   {"BLTUC", ::Emulate_BXX_3ops_C,
"BLTUC rs,rt,offset"},
+  {"BLTUC64", ::Emulate_BXX_3ops_C,
+   "BLTUC rs,rt,offset"},
   {"BGEUC", ::Emulate_BXX_3ops_C,
"BGEUC rs,rt,offset"},
+  {"BGEUC64", ::Emulate_BXX_3ops_C,
+   "BGEUC rs,rt,offset"},
   {"BLTZC", ::Emulate_BXX_2ops_C,
"BLTZC rt,offset"},
+  {"BLTZC64", ::Emulate_BXX_2ops_C,
+   "BLTZC rt,offset"},
   {"BLEZC", ::Emulate_BXX_2ops_C,
"BLEZC rt,offset"},
+  {"BLEZC64", ::Emulate_BXX_2ops_C,
+   "BLEZC rt,offset"},
   {"BGEZC", ::Emulate_BXX_2ops_C,
"BGEZC rt,offset"},
+  {"BGEZC64", ::Emulate_BXX_2ops_C,
+   "BGEZC rt,offset"},
   {"BGTZC", ::Emulate_BXX_2ops_C,
"BGTZC rt,offset"},
+  {"BGTZC64", ::Emulate_BXX_2ops_C,
+   "BGTZC rt,offset"},
   {"BEQZC", ::Emulate_BXX_2ops_C,
"BEQZC rt,offset"},
+  {"BEQZC64", ::Emulate_BXX_2ops_C,
+   "BEQZC rt,offset"},
   {"BNEZC", ::Emulate_BXX_2ops_C,
"BNEZC rt,offset"},
+  {"BNEZC64", ::Emulate_BXX_2ops_C,
+   "BNEZC rt,offset"},
   {"BGEZL", ::Emulate_BXX_2ops, "BGEZL 
rt,offset"},
   {"BGTZ", ::Emulate_BXX_2ops, "BGTZ rt,offset"},
+  {"BGTZ64", ::Emulate_BXX_2ops, "BGTZ 
rt,offset"},
   {"BGTZL", ::Emulate_BXX_2ops, "BGTZL 
rt,offset"},
   {"BLEZ", ::Emulate_BXX_2ops, "BLEZ rt,offset"},
+  {"BLEZ64", ::Emulate_BXX_2ops, "BLEZ 
rt,offset"},
   {"BLEZL", ::Emulate_BXX_2ops, "BLEZL 
rt,offset"},
   {"BLTZ", ::Emulate_BXX_2ops, "BLTZ rt,offset"},
+  {"BLTZ64", ::Emulate_BXX_2ops, "BLTZ 
rt,offset"},
   {"BLTZAL", ::Emulate_Bcond_Link,
"BLTZAL rt,offset"},
   {"BLTZALL", ::Emulate_Bcond_Link,
@@ -872,8 +902,11 @@ EmulateInstructionMIPS64::GetOpcodeForIn
   {"JALR64", ::Emulate_JALR, "JALR target"},
   {"JALR_HB", ::Emulate_JALR, "JALR.HB target"},
   {"JIALC", ::Emulate_JIALC, "JIALC rt,offset"},
+  {"JIALC64", ::Emulate_JIALC, "JIALC rt,offset"},
   {"JIC", ::Emulate_JIC, "JIC rt,offset"},
+  {"JIC64", ::Emulate_JIC, "JIC rt,offset"},
   {"JR", ::Emulate_JR, "JR target"},
+  {"JR64", ::Emulate_JR, "JR target"},
   {"JR_HB", ::Emulate_JR, "JR.HB target"},
   {"BC1F", ::Emulate_FP_branch, "BC1F cc, 
offset"},
   {"BC1T", ::Emulate_FP_branch, "BC1T cc, 
offset"},
@@ -1338,12 +1371,14 @@ bool EmulateInstructionMIPS64::Emulate_B
   if (!success)
 return false;
 
-  if (!strcasecmp(op_name, "BEQ") || !strcasecmp(op_name, "BEQL")) {
+  if (!strcasecmp(op_name, "BEQ") || !strcasecmp(op_name, "BEQL") 
+   || !strcasecmp(op_name,

[Lldb-commits] [lldb] r305383 - [LLDB][MIPS] Skip TestGdbRemoteSingleStep and TestGdbRemote_vCont.py.

2017-06-14 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Wed Jun 14 07:21:26 2017
New Revision: 305383

URL: http://llvm.org/viewvc/llvm-project?rev=305383=rev
Log:
[LLDB][MIPS] Skip TestGdbRemoteSingleStep and TestGdbRemote_vCont.py.

The step count depends on code generated by compiler (GCC/Clang).
It will also vary for different MIPS arch variant. Hence skipping these test 
for MIPS.

Subscribers: jaydeep, bhushan, lldb-commits, slthakur

Modified:

lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-server/TestGdbRemoteSingleStep.py

lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-server/TestGdbRemote_vCont.py

Modified: 
lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-server/TestGdbRemoteSingleStep.py
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-server/TestGdbRemoteSingleStep.py?rev=305383=305382=305383=diff
==
--- 
lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-server/TestGdbRemoteSingleStep.py
 (original)
+++ 
lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-server/TestGdbRemoteSingleStep.py
 Wed Jun 14 07:21:26 2017
@@ -31,6 +31,7 @@ class TestGdbRemoteSingleStep(gdbremote_
 "arm",
 "aarch64"],
 bugnumber="llvm.org/pr24739")
+@skipIf(triple='^mips')
 def test_single_step_only_steps_one_instruction_with_s_llgs(self):
 self.init_llgs_test()
 self.build()

Modified: 
lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-server/TestGdbRemote_vCont.py
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-server/TestGdbRemote_vCont.py?rev=305383=305382=305383=diff
==
--- 
lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-server/TestGdbRemote_vCont.py
 (original)
+++ 
lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-server/TestGdbRemote_vCont.py
 Wed Jun 14 07:21:26 2017
@@ -108,6 +108,7 @@ class TestGdbRemote_vCont(gdbremote_test
 "arm",
 "aarch64"],
 bugnumber="llvm.org/pr24739")
+@skipIf(triple='^mips')
 def test_single_step_only_steps_one_instruction_with_Hc_vCont_s_llgs(self):
 self.init_llgs_test()
 self.build()
@@ -136,6 +137,7 @@ class TestGdbRemote_vCont(gdbremote_test
 "arm",
 "aarch64"],
 bugnumber="llvm.org/pr24739")
+@skipIf(triple='^mips')
 def test_single_step_only_steps_one_instruction_with_vCont_s_thread_llgs(
 self):
 self.init_llgs_test()


___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] r305380 - [LLDB][MIPS] Fix TestNoreturnUnwind.py.

2017-06-14 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Wed Jun 14 05:47:25 2017
New Revision: 305380

URL: http://llvm.org/viewvc/llvm-project?rev=305380=rev
Log:
[LLDB][MIPS] Fix TestNoreturnUnwind.py.

bugnumber=llvm.org/pr33452

Subscribers: jaydeep, bhushan, lldb-commits, slthakur

Modified:

lldb/trunk/packages/Python/lldbsuite/test/functionalities/unwind/noreturn/TestNoreturnUnwind.py

Modified: 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/unwind/noreturn/TestNoreturnUnwind.py
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/functionalities/unwind/noreturn/TestNoreturnUnwind.py?rev=305380=305379=305380=diff
==
--- 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/unwind/noreturn/TestNoreturnUnwind.py
 (original)
+++ 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/unwind/noreturn/TestNoreturnUnwind.py
 Wed Jun 14 05:47:25 2017
@@ -19,6 +19,7 @@ class NoreturnUnwind(TestBase):
 @skipIfWindows  # clang-cl does not support gcc style attributes.
 # clang does not preserve LR in noreturn functions, making unwinding 
impossible
 @skipIf(compiler="clang", archs=['arm'], oslist=['linux'])
+@expectedFailureAll(bugnumber="llvm.org/pr33452", triple='^mips')
 def test(self):
 """Test that we can backtrace correctly with 'noreturn' functions on 
the stack"""
 self.build()


___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] r305378 - [LLDB][MIPS] Fix TestRegisterVariables.py.

2017-06-14 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Wed Jun 14 05:02:56 2017
New Revision: 305378

URL: http://llvm.org/viewvc/llvm-project?rev=305378=rev
Log:
[LLDB][MIPS] Fix TestRegisterVariables.py.

Clang does not accept regparm attribute on these platforms.
Fortunately, the default calling convention passes arguments
in registers any way

Subscribers: jaydeep, bhushan, lldb-commits, slthakur

Modified:
lldb/trunk/packages/Python/lldbsuite/test/lang/c/register_variables/test.c

Modified: 
lldb/trunk/packages/Python/lldbsuite/test/lang/c/register_variables/test.c
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/lang/c/register_variables/test.c?rev=305378=305377=305378=diff
==
--- lldb/trunk/packages/Python/lldbsuite/test/lang/c/register_variables/test.c 
(original)
+++ lldb/trunk/packages/Python/lldbsuite/test/lang/c/register_variables/test.c 
Wed Jun 14 05:02:56 2017
@@ -1,6 +1,6 @@
 #include 
 
-#if defined(__arm__) || defined(__aarch64__)
+#if defined(__arm__) || defined(__aarch64__) || defined (__mips__)
 // Clang does not accept regparm attribute on these platforms.
 // Fortunately, the default calling convention passes arguments in registers
 // anyway.


___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] r302139 - [LLDB][MIPS] Fix TestStepOverBreakpoint.py failure.

2017-05-04 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Thu May  4 06:34:42 2017
New Revision: 302139

URL: http://llvm.org/viewvc/llvm-project?rev=302139=rev
Log:
[LLDB][MIPS] Fix TestStepOverBreakpoint.py failure.

Reviewers: jingham, labath

Subscribers: jaydeep, bhushan, lldb-commits, slthakur

Differential Revision: https://reviews.llvm.org/D32168

Modified:
lldb/trunk/include/lldb/API/SBAddress.h
lldb/trunk/include/lldb/API/SBInstruction.h
lldb/trunk/include/lldb/API/SBInstructionList.h
lldb/trunk/include/lldb/Core/Disassembler.h

lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/step_over_breakpoint/TestStepOverBreakpoint.py
lldb/trunk/scripts/interface/SBInstruction.i
lldb/trunk/scripts/interface/SBInstructionList.i
lldb/trunk/source/API/SBAddress.cpp
lldb/trunk/source/API/SBInstruction.cpp
lldb/trunk/source/API/SBInstructionList.cpp
lldb/trunk/source/Core/Disassembler.cpp

Modified: lldb/trunk/include/lldb/API/SBAddress.h
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/include/lldb/API/SBAddress.h?rev=302139=302138=302139=diff
==
--- lldb/trunk/include/lldb/API/SBAddress.h (original)
+++ lldb/trunk/include/lldb/API/SBAddress.h Thu May  4 06:34:42 2017
@@ -103,6 +103,8 @@ protected:
 
   const lldb_private::Address *operator->() const;
 
+  friend bool operator==(const SBAddress , const SBAddress );
+
   lldb_private::Address *get();
 
   lldb_private::Address ();
@@ -117,6 +119,8 @@ private:
   std::unique_ptr m_opaque_ap;
 };
 
+bool operator==(const SBAddress , const SBAddress );
+
 } // namespace lldb
 
 #endif // LLDB_SBAddress_h_

Modified: lldb/trunk/include/lldb/API/SBInstruction.h
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/include/lldb/API/SBInstruction.h?rev=302139=302138=302139=diff
==
--- lldb/trunk/include/lldb/API/SBInstruction.h (original)
+++ lldb/trunk/include/lldb/API/SBInstruction.h Thu May  4 06:34:42 2017
@@ -53,6 +53,8 @@ public:
 
   bool HasDelaySlot();
 
+  bool CanSetBreakpoint();
+
   void Print(FILE *out);
 
   bool GetDescription(lldb::SBStream );

Modified: lldb/trunk/include/lldb/API/SBInstructionList.h
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/include/lldb/API/SBInstructionList.h?rev=302139=302138=302139=diff
==
--- lldb/trunk/include/lldb/API/SBInstructionList.h (original)
+++ lldb/trunk/include/lldb/API/SBInstructionList.h Thu May  4 06:34:42 2017
@@ -32,6 +32,15 @@ public:
 
   lldb::SBInstruction GetInstructionAtIndex(uint32_t idx);
 
+  // --
+  // Returns the number of instructions between the start and end address.
+  // If canSetBreakpoint is true then the count will be the number of 
+  // instructions on which a breakpoint can be set.
+  // --
+  size_t GetInstructionsCount(const SBAddress ,
+  const SBAddress ,
+  bool canSetBreakpoint = false);  
 
+
   void Clear();
 
   void AppendInstruction(lldb::SBInstruction inst);

Modified: lldb/trunk/include/lldb/Core/Disassembler.h
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/include/lldb/Core/Disassembler.h?rev=302139=302138=302139=diff
==
--- lldb/trunk/include/lldb/Core/Disassembler.h (original)
+++ lldb/trunk/include/lldb/Core/Disassembler.h Thu May  4 06:34:42 2017
@@ -173,6 +173,8 @@ public:
 
   virtual bool HasDelaySlot();
 
+  bool CanSetBreakpoint ();
+
   virtual size_t Decode(const Disassembler ,
 const DataExtractor ,
 lldb::offset_t data_offset) = 0;

Modified: 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/step_over_breakpoint/TestStepOverBreakpoint.py
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/step_over_breakpoint/TestStepOverBreakpoint.py?rev=302139=302138=302139=diff
==
--- 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/step_over_breakpoint/TestStepOverBreakpoint.py
 (original)
+++ 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/step_over_breakpoint/TestStepOverBreakpoint.py
 Thu May  4 06:34:42 2017
@@ -62,12 +62,11 @@ class StepOverBreakpointsTestCase(TestBa
 instructions = function.GetInstructions(self.target)
 addr_1 = self.breakpoint1.GetLocationAtIndex(0).GetAddress()
 addr_4 = self.breakpoint4.GetLocationAtIndex(0).GetAddress()
-for i in range(instructions.GetSize()) :
-addr =

[Lldb-commits] [lldb] r301537 - [LLDB][MIPS] Forgot to add check in commit rl301530

2017-04-27 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Thu Apr 27 07:27:42 2017
New Revision: 301537

URL: http://llvm.org/viewvc/llvm-project?rev=301537=rev
Log:
[LLDB][MIPS] Forgot to add check in commit rl301530
Reviewers: ki.stfu, labath
Subscribers: jaydeep, bhushan, lldb-commits, slthakur

Modified:

lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-mi/control/TestMiExec.py

Modified: 
lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-mi/control/TestMiExec.py
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-mi/control/TestMiExec.py?rev=301537=301536=301537=diff
==
--- 
lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-mi/control/TestMiExec.py 
(original)
+++ 
lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-mi/control/TestMiExec.py 
Thu Apr 27 07:27:42 2017
@@ -325,8 +325,10 @@ class MiExecTestCase(lldbmi_testcase.MiT
 if it == 1:
 # Call to s_MyFunction may not follow immediately after 
g_MyFunction.
 # There might be some instructions in between to restore 
caller-saved registers.
-# We need to get past these instructions with a step to reach call 
to s_MyFunction.
-self.runCmd("-exec-step --thread 1")
+# We need to get past these instructions with a next to reach call 
to s_MyFunction.
+self.runCmd("-exec-next --thread 1")
+self.expect("\^running")
+
self.expect("\*stopped,reason=\"end-stepping-range\".+?main\.cpp\",line=\"30\"")
 
 # Test that -exec-step steps into s_MyFunction
 # (and that --frame is optional)


___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] r301295 - [LLDB][MIPS] Fix typo in TestStepOverWatchpoint.py.

2017-04-25 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Tue Apr 25 01:12:59 2017
New Revision: 301295

URL: http://llvm.org/viewvc/llvm-project?rev=301295=rev
Log:
[LLDB][MIPS] Fix typo in TestStepOverWatchpoint.py.

Subscribers: jaydeep, bhushan, lldb-commits, slthakur

Modified:

lldb/trunk/packages/Python/lldbsuite/test/functionalities/watchpoint/step_over_watchpoint/TestStepOverWatchpoint.py

Modified: 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/watchpoint/step_over_watchpoint/TestStepOverWatchpoint.py
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/functionalities/watchpoint/step_over_watchpoint/TestStepOverWatchpoint.py?rev=301295=301294=301295=diff
==
--- 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/watchpoint/step_over_watchpoint/TestStepOverWatchpoint.py
 (original)
+++ 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/watchpoint/step_over_watchpoint/TestStepOverWatchpoint.py
 Tue Apr 25 01:12:59 2017
@@ -89,7 +89,7 @@ class TestStepOverWatchpoint(TestBase):
 
 # resolve_location=True, read=False, write=True
 write_watchpoint = write_value.Watch(True, False, True, error)
-self.assertTrue(read_watchpoint, "Failed to set write watchpoint.")
+self.assertTrue(write_watchpoint, "Failed to set write watchpoint.")
 self.assertTrue(error.Success(),
 "Error while setting watchpoint: %s" %
 error.GetCString())


___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] r301172 - [LLDB][MIPS] Move it into HandleLLVMOptions.cmake.

2017-04-24 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Mon Apr 24 05:56:01 2017
New Revision: 301172

URL: http://llvm.org/viewvc/llvm-project?rev=301172=rev
Log:
[LLDB][MIPS] Move it into HandleLLVMOptions.cmake.

The revison https://reviews.llvm.org/D32125 will fixed the off_t for GNU 
specific 32 bit platform. This fixed the difference in definition of off_t in 
LLDB and LLVM

Subscribers: jaydeep, bhushan, lldb-commits, slthakur, llvm-commits, 
krytarowski, emaste, zturner

Modified:
lldb/trunk/cmake/modules/LLDBConfig.cmake

Modified: lldb/trunk/cmake/modules/LLDBConfig.cmake
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/cmake/modules/LLDBConfig.cmake?rev=301172=301171=301172=diff
==
--- lldb/trunk/cmake/modules/LLDBConfig.cmake (original)
+++ lldb/trunk/cmake/modules/LLDBConfig.cmake Mon Apr 24 05:56:01 2017
@@ -250,12 +250,6 @@ endif()
 set(LLDB_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR})
 set(LLDB_BINARY_DIR ${CMAKE_CURRENT_BINARY_DIR})
 
-# If building on a 32-bit system, make sure off_t can store offsets > 2GB
-if( CMAKE_SIZEOF_VOID_P EQUAL 4 )
-  add_definitions( -D_LARGEFILE_SOURCE )
-  add_definitions( -D_FILE_OFFSET_BITS=64 )
-endif()
-
 if (CMAKE_SOURCE_DIR STREQUAL CMAKE_BINARY_DIR)
   message(FATAL_ERROR "In-source builds are not allowed. CMake would overwrite 
"
 "the makefiles distributed with LLDB. Please create a directory and run cmake "


___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] r299527 - Fix a typo introduce in r299200.

2017-04-05 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Wed Apr  5 04:31:43 2017
New Revision: 299527

URL: http://llvm.org/viewvc/llvm-project?rev=299527=rev
Log:
Fix a typo introduce in r299200.

Modified:

lldb/trunk/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_mips64.h

Modified: 
lldb/trunk/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_mips64.h
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_mips64.h?rev=299527=299526=299527=diff
==
--- 
lldb/trunk/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_mips64.h
 (original)
+++ 
lldb/trunk/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_mips64.h
 Wed Apr  5 04:31:43 2017
@@ -11,7 +11,7 @@
 #define liblldb_RegisterContextPOSIXProcessMonitor_mips64_H_
 
 #include "Plugins/Process/Utility/RegisterContextPOSIX_mips64.h"
-#include "Plugin/Process/Utility/lldb-mips-freebsd-register-enums.h"
+#include "Plugins/Process/Utility/lldb-mips-freebsd-register-enums.h"
 #include "RegisterContextPOSIX.h"
 
 class RegisterContextPOSIXProcessMonitor_mips64


___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] r299200 - [LLDB][MIPS] Core Dump Support.

2017-03-31 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Fri Mar 31 06:14:02 2017
New Revision: 299200

URL: http://llvm.org/viewvc/llvm-project?rev=299200=rev
Log:
[LLDB][MIPS] Core Dump Support.

Reviewers: labath, emaste

Subscribers: jaydeep, bhushan, lldb-commits, slthakur

Differential Revision: https://reviews.llvm.org/D30457

Modified:
lldb/trunk/source/Core/ArchSpec.cpp

lldb/trunk/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_mips64.h

lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
lldb/trunk/source/Plugins/Process/Utility/RegisterContextFreeBSD_mips64.cpp
lldb/trunk/source/Plugins/Process/Utility/RegisterContextFreeBSD_mips64.h
lldb/trunk/source/Plugins/Process/Utility/RegisterContextLinux_mips.cpp
lldb/trunk/source/Plugins/Process/Utility/RegisterContextLinux_mips.h
lldb/trunk/source/Plugins/Process/Utility/RegisterContextLinux_mips64.cpp
lldb/trunk/source/Plugins/Process/Utility/RegisterContextLinux_mips64.h
lldb/trunk/source/Plugins/Process/Utility/RegisterContextPOSIX_mips64.cpp
lldb/trunk/source/Plugins/Process/Utility/RegisterContextPOSIX_mips64.h

lldb/trunk/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_mips64.cpp
lldb/trunk/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_mips64.h
lldb/trunk/source/Plugins/Process/elf-core/ThreadElfCore.cpp
lldb/trunk/source/Plugins/Process/elf-core/ThreadElfCore.h

Modified: lldb/trunk/source/Core/ArchSpec.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Core/ArchSpec.cpp?rev=299200=299199=299200=diff
==
--- lldb/trunk/source/Core/ArchSpec.cpp (original)
+++ lldb/trunk/source/Core/ArchSpec.cpp Fri Mar 31 06:14:02 2017
@@ -1380,7 +1380,7 @@ static bool cores_match(const ArchSpec::
   if (core2 >= ArchSpec::kCore_mips32el_first &&
   core2 <= ArchSpec::kCore_mips32el_last)
 return true;
-  try_inverse = false;
+  try_inverse = true;
 }
 break;
 

Modified: 
lldb/trunk/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_mips64.h
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_mips64.h?rev=299200=299199=299200=diff
==
--- 
lldb/trunk/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_mips64.h
 (original)
+++ 
lldb/trunk/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_mips64.h
 Fri Mar 31 06:14:02 2017
@@ -11,6 +11,7 @@
 #define liblldb_RegisterContextPOSIXProcessMonitor_mips64_H_
 
 #include "Plugins/Process/Utility/RegisterContextPOSIX_mips64.h"
+#include "Plugin/Process/Utility/lldb-mips-freebsd-register-enums.h"
 #include "RegisterContextPOSIX.h"
 
 class RegisterContextPOSIXProcessMonitor_mips64
@@ -72,6 +73,8 @@ protected:
   uint32_t NumSupportedHardwareWatchpoints();
 
 private:
+  uint64_t 
+  m_gpr_mips64[k_num_gpr_registers_mips64]; // general purpose registers.
   ProcessMonitor ();
 };
 

Modified: 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp?rev=299200=299199=299200=diff
==
--- 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp 
(original)
+++ 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp 
Fri Mar 31 06:14:02 2017
@@ -80,152 +80,6 @@ struct pt_watch_regs default_watch_regs;
 using namespace lldb_private;
 using namespace lldb_private::process_linux;
 
-// 
-// Private namespace.
-// 
-
-namespace {
-// mips general purpose registers.
-const uint32_t g_gp_regnums_mips[] = {
-gpr_zero_mips,  gpr_r1_mips,gpr_r2_mips,  gpr_r3_mips,
-gpr_r4_mips,gpr_r5_mips,gpr_r6_mips,  gpr_r7_mips,
-gpr_r8_mips,gpr_r9_mips,gpr_r10_mips, gpr_r11_mips,
-gpr_r12_mips,   gpr_r13_mips,   gpr_r14_mips, gpr_r15_mips,
-gpr_r16_mips,   gpr_r17_mips,   gpr_r18_mips, gpr_r19_mips,
-gpr_r20_mips,   gpr_r21_mips,   gpr_r22_mips, gpr_r23_mips,
-gpr_r24_mips,   gpr_r25_mips,   gpr_r26_mips, gpr_r27_mips,
-gpr_gp_mips,gpr_sp_mips,gpr_r30_mips, gpr_ra_mips,
-gpr_sr_mips,gpr_mullo_mips, gpr_mulhi_mips,   gpr_badvaddr_mips,
-gpr_cause_mips, gpr_pc_mips,gpr_config5_mips,
-LLDB_INVALID_REGNUM // register sets need to end with this flag
-};
-
-static_assert((sizeof(g_gp_regnums_mips) / sizeof(g_gp_regnums_mips[0])) - 1 ==
-  k_num_gpr_registers_mips,
-

[Lldb-commits] [lldb] r299199 - [LLDB][MIPS] Fix Core file Architecture and OS information.

2017-03-31 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Fri Mar 31 06:06:25 2017
New Revision: 299199

URL: http://llvm.org/viewvc/llvm-project?rev=299199=rev
Log:
[LLDB][MIPS] Fix Core file Architecture and OS information.

Reviewers: labath, clayborg

Subscribers: jaydeep, bhushan, lldb-commits, slthakur

Differential Revision: https://reviews.llvm.org/D31280

Added:

lldb/trunk/packages/Python/lldbsuite/test/functionalities/postmortem/elf-core/linux-mips64el-gnuabi64.core

lldb/trunk/packages/Python/lldbsuite/test/functionalities/postmortem/elf-core/linux-mips64el-gnuabi64.out
   (with props)

lldb/trunk/packages/Python/lldbsuite/test/functionalities/postmortem/elf-core/linux-mips64el-gnuabin32.core

lldb/trunk/packages/Python/lldbsuite/test/functionalities/postmortem/elf-core/linux-mips64el-gnuabin32.out
   (with props)

lldb/trunk/packages/Python/lldbsuite/test/functionalities/postmortem/elf-core/linux-mipsel-gnuabio32.core

lldb/trunk/packages/Python/lldbsuite/test/functionalities/postmortem/elf-core/linux-mipsel-gnuabio32.out
   (with props)
Modified:

lldb/trunk/packages/Python/lldbsuite/test/functionalities/postmortem/elf-core/TestLinuxCore.py
lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
lldb/trunk/source/Plugins/Process/elf-core/ProcessElfCore.cpp

Modified: 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/postmortem/elf-core/TestLinuxCore.py
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/functionalities/postmortem/elf-core/TestLinuxCore.py?rev=299199=299198=299199=diff
==
--- 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/postmortem/elf-core/TestLinuxCore.py
 (original)
+++ 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/postmortem/elf-core/TestLinuxCore.py
 Fri Mar 31 06:06:25 2017
@@ -21,10 +21,14 @@ class LinuxCoreTestCase(TestBase):
 _i386_pid = 32306
 _x86_64_pid = 32259
 _s390x_pid = 1045
+_mips64_n64_pid = 25619
+_mips64_n32_pid = 3670
+_mips_o32_pid = 3532
 
 _i386_regions = 4
 _x86_64_regions = 5
 _s390x_regions = 2
+_mips_regions = 5
 
 def setUp(self):
 super(LinuxCoreTestCase, self).setUp()
@@ -40,6 +44,18 @@ class LinuxCoreTestCase(TestBase):
 """Test that lldb can read the process information from an i386 linux 
core file."""
 self.do_test("linux-i386", self._i386_pid, self._i386_regions)
 
+def test_mips_o32(self):
+"""Test that lldb can read the process information from an MIPS O32 
linux core file."""
+self.do_test("linux-mipsel-gnuabio32", self._mips_o32_pid, 
self._mips_regions)
+
+def test_mips_n32(self):
+"""Test that lldb can read the process information from an MIPS N32 
linux core file """
+self.do_test("linux-mips64el-gnuabin32", self._mips64_n32_pid, 
self._mips_regions)
+
+def test_mips_n64(self):
+"""Test that lldb can read the process information from an MIPS N64 
linux core file """
+self.do_test("linux-mips64el-gnuabi64", self._mips64_n64_pid, 
self._mips_regions)
+
 @skipIf(oslist=['windows'])
 @skipIf(triple='^mips')
 def test_x86_64(self):

Added: 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/postmortem/elf-core/linux-mips64el-gnuabi64.core
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/functionalities/postmortem/elf-core/linux-mips64el-gnuabi64.core?rev=299199=auto
==
Binary files 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/postmortem/elf-core/linux-mips64el-gnuabi64.core
 (added) and 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/postmortem/elf-core/linux-mips64el-gnuabi64.core
 Fri Mar 31 06:06:25 2017 differ

Added: 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/postmortem/elf-core/linux-mips64el-gnuabi64.out
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/functionalities/postmortem/elf-core/linux-mips64el-gnuabi64.out?rev=299199=auto
==
Binary files 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/postmortem/elf-core/linux-mips64el-gnuabi64.out
 (added) and 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/postmortem/elf-core/linux-mips64el-gnuabi64.out
 Fri Mar 31 06:06:25 2017 differ

Propchange: 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/postmortem/elf-core/linux-mips64el-gnuabi64.out
--
svn:executable = *

Added: 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/postmortem/elf-core/linux-mips64el-gnuabin32.core
URL:

[Lldb-commits] [lldb] r299196 - [LLDB][MIPS] Check if memory_info.GetName() is empty before finding corresponding module.

2017-03-31 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Fri Mar 31 05:55:55 2017
New Revision: 299196

URL: http://llvm.org/viewvc/llvm-project?rev=299196=rev
Log:
[LLDB][MIPS] Check if memory_info.GetName() is empty before finding 
corresponding module.

Reviewers: labath, clayborg

Subscribers: jaydeep, bhushan, lldb-commits, slthakur

Differential Revision: https://reviews.llvm.org/D30454

Modified:
lldb/trunk/source/Core/DynamicLoader.cpp

Modified: lldb/trunk/source/Core/DynamicLoader.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Core/DynamicLoader.cpp?rev=299196=299195=299196=diff
==
--- lldb/trunk/source/Core/DynamicLoader.cpp (original)
+++ lldb/trunk/source/Core/DynamicLoader.cpp Fri Mar 31 05:55:55 2017
@@ -189,7 +189,8 @@ ModuleSP DynamicLoader::LoadModuleAtAddr
 MemoryRegionInfo memory_info;
 Error error = m_process->GetMemoryRegionInfo(base_addr, memory_info);
 if (error.Success() && memory_info.GetMapped() &&
-memory_info.GetRange().GetRangeBase() == base_addr) {
+memory_info.GetRange().GetRangeBase() == base_addr && 
+!(memory_info.GetName().IsEmpty())) {
   ModuleSpec new_module_spec(
   FileSpec(memory_info.GetName().AsCString(), false),
   target.GetArchitecture());


___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] r294418 - [LLDB][MIPS] Fix TestMiExec and TestMiData failures

2017-02-07 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Wed Feb  8 01:42:56 2017
New Revision: 294418

URL: http://llvm.org/viewvc/llvm-project?rev=294418=rev
Log:
[LLDB][MIPS] Fix TestMiExec and TestMiData failures

Subscribers: jaydeep, bhushan, lldb-commits, slthakur

Modified:
lldb/trunk/packages/Python/lldbsuite/test/lldbtest.py

lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-mi/control/TestMiExec.py
lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-mi/data/TestMiData.py

Modified: lldb/trunk/packages/Python/lldbsuite/test/lldbtest.py
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/lldbtest.py?rev=294418=294417=294418=diff
==
--- lldb/trunk/packages/Python/lldbsuite/test/lldbtest.py (original)
+++ lldb/trunk/packages/Python/lldbsuite/test/lldbtest.py Wed Feb  8 01:42:56 
2017
@@ -1227,6 +1227,13 @@ class Base(unittest2.TestCase):
 # (enables reading of the current test configuration)
 # 
 
+def isMIPS(self):
+"""Returns true if the architecture is MIPS."""
+arch = self.getArchitecture()
+if re.match("mips", arch):
+return True
+return False
+
 def getArchitecture(self):
 """Returns the architecture in effect the test suite is running 
with."""
 module = builder_module()

Modified: 
lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-mi/control/TestMiExec.py
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-mi/control/TestMiExec.py?rev=294418=294417=294418=diff
==
--- 
lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-mi/control/TestMiExec.py 
(original)
+++ 
lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-mi/control/TestMiExec.py 
Wed Feb  8 01:42:56 2017
@@ -260,7 +260,7 @@ class MiExecTestCase(lldbmi_testcase.MiT
 self.expect("\^running")
 # Depending on compiler, it can stop at different line
 self.expect(
-
"\*stopped,reason=\"end-stepping-range\".+?main\.cpp\",line=\"(29|30|31)\"")
+
"\*stopped,reason=\"end-stepping-range\".+?main\.cpp\",line=\"(28|29|30|31)\"")
 
 # Test that an invalid --thread is handled
 self.runCmd("-exec-next-instruction --thread 0")
@@ -382,7 +382,17 @@ class MiExecTestCase(lldbmi_testcase.MiT
 
 # Test that -exec-step-instruction steps into g_MyFunction
 # instruction (and that --thread is optional)
-self.runCmd("-exec-step-instruction --frame 0")
+
+# In case of MIPS, there might be more than one instruction
+# before actual call instruction (like load, move and call 
instructions).
+# The -exec-step-instruction would step one assembly instruction.
+# Thus we may not enter into g_MyFunction function. The -exec-step 
would definitely
+# step into the function.
+
+if self.isMIPS():
+self.runCmd("-exec-step --frame 0")
+else:
+self.runCmd("-exec-step-instruction --frame 0")
 self.expect("\^running")
 self.expect(
 
"\*stopped,reason=\"end-stepping-range\".+?func=\"g_MyFunction.*?\"")

Modified: 
lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-mi/data/TestMiData.py
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-mi/data/TestMiData.py?rev=294418=294417=294418=diff
==
--- lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-mi/data/TestMiData.py 
(original)
+++ lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-mi/data/TestMiData.py 
Wed Feb  8 01:42:56 2017
@@ -77,7 +77,13 @@ class MiDataTestCase(lldbmi_testcase.MiT
 # Linux:  
{address="0x00400642",func-name="hello_world()",offset="18",size="5",inst="callq
 0x4004d0; symbol stub for: printf"}
 # To match the escaped characters in the ouptut, we must use four 
backslashes per matches backslash
 # See https://docs.python.org/2/howto/regex.html#the-backslash-plague
-
self.expect(["{address=\"0x[0-9a-f]+\",func-name=\"hello_world\(\)\",offset=\"[0-9]+\",size=\"[0-9]+\",inst=\".+?;
 \"Hello, World!n\"\"}",
+
+# The MIPS disassembler never prints stub name 
+if self.isMIPS():
+
self.expect(["{address=\"0x[0-9a-f]+\",func-name=\"hello_world\(\)\",offset=\"[0-9]+\",size=\"[0-9]+\",inst=\".+?;
 \"Hello, World!n\"\"}",
+ 
"{address=\"0x[0-9a-f]+\",func-name=\"hello_world\(\)\",offset=\"[0-9]+\",size=\"[0-9]+\",inst=\".+?\"}"])
+else:
+
self.expect(["{address=\"0x[0-9a-f]+\",func-name=\"hello_world\(\)\",offset=\"[0-9]+\",size=\"[0-9]+\",inst=\".+?;
 \"Hello, World!n\"\"}",

[Lldb-commits] [lldb] r294415 - [LLDB][MIPS] Fix TestMiniDumpNew

2017-02-07 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Wed Feb  8 01:29:24 2017
New Revision: 294415

URL: http://llvm.org/viewvc/llvm-project?rev=294415=rev
Log:
[LLDB][MIPS] Fix TestMiniDumpNew

Reviewers: labath, clayborg

Subscribers: jaydeep, bhushan, lldb-commits, slthakur

Differential Revision: https://reviews.llvm.org/D29215

Modified:

lldb/trunk/packages/Python/lldbsuite/test/functionalities/postmortem/minidump-new/TestMiniDumpNew.py

Modified: 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/postmortem/minidump-new/TestMiniDumpNew.py
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/functionalities/postmortem/minidump-new/TestMiniDumpNew.py?rev=294415=294414=294415=diff
==
--- 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/postmortem/minidump-new/TestMiniDumpNew.py
 (original)
+++ 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/postmortem/minidump-new/TestMiniDumpNew.py
 Wed Feb  8 01:29:24 2017
@@ -23,6 +23,14 @@ class MiniDumpNewTestCase(TestBase):
 _linux_x86_64_not_crashed_pid = 29939
 _linux_x86_64_not_crashed_pid_offset = 0xD967
 
+def setUp(self):
+super(MiniDumpNewTestCase, self).setUp()
+self._initial_platform = lldb.DBG.GetSelectedPlatform()
+
+def tearDown(self):
+lldb.DBG.SetSelectedPlatform(self._initial_platform)
+super(MiniDumpNewTestCase, self).tearDown()
+
 def test_process_info_in_minidump(self):
 """Test that lldb can read the process information from the 
Minidump."""
 # target create -c linux-x86_64.dmp


___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] r291554 - [LLDB][MIPS] Fix TestLldbGdbServer failure for MIPS

2017-01-10 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Tue Jan 10 03:33:43 2017
New Revision: 291554

URL: http://llvm.org/viewvc/llvm-project?rev=291554=rev
Log:
[LLDB][MIPS] Fix TestLldbGdbServer failure for MIPS

Reviewers: labath, clayborg

Subscribers: jaydeep, bhushan, lldb-commits, slthakur

Differential Revision: https://reviews.llvm.org/D27088

Added:
lldb/trunk/packages/Python/lldbsuite/test/lldbdwarf.py
Modified:

lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-server/TestLldbGdbServer.py

Added: lldb/trunk/packages/Python/lldbsuite/test/lldbdwarf.py
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/lldbdwarf.py?rev=291554=auto
==
--- lldb/trunk/packages/Python/lldbsuite/test/lldbdwarf.py (added)
+++ lldb/trunk/packages/Python/lldbsuite/test/lldbdwarf.py Tue Jan 10 03:33:43 
2017
@@ -0,0 +1,256 @@
+""" This module implement Dwarf expression opcode parser. """
+
+import lldb
+
+# DWARF Expression operators.
+DW_OP_addr  = 0x03
+DW_OP_deref = 0x06
+DW_OP_const1u   = 0x08
+DW_OP_const1s   = 0x09
+DW_OP_const2u   = 0x0A
+DW_OP_const2s   = 0x0B
+DW_OP_const4u   = 0x0C
+DW_OP_const4s   = 0x0D
+DW_OP_const8u   = 0x0E
+DW_OP_const8s   = 0x0F
+DW_OP_constu= 0x10
+DW_OP_consts= 0x11
+DW_OP_dup   = 0x12
+DW_OP_drop  = 0x13
+DW_OP_over  = 0x14
+DW_OP_pick  = 0x15
+DW_OP_swap  = 0x16
+DW_OP_rot   = 0x17
+DW_OP_xderef= 0x18
+DW_OP_abs   = 0x19
+DW_OP_and   = 0x1A
+DW_OP_div   = 0x1B
+DW_OP_minus = 0x1C
+DW_OP_mod   = 0x1D
+DW_OP_mul   = 0x1E
+DW_OP_neg   = 0x1F
+DW_OP_not   = 0x20
+DW_OP_or= 0x21
+DW_OP_plus  = 0x22
+DW_OP_plus_uconst   = 0x23
+DW_OP_shl   = 0x24
+DW_OP_shr   = 0x25
+DW_OP_shra  = 0x26
+DW_OP_xor   = 0x27
+DW_OP_skip  = 0x2F
+DW_OP_bra   = 0x28
+DW_OP_eq= 0x29
+DW_OP_ge= 0x2A
+DW_OP_gt= 0x2B
+DW_OP_le= 0x2C
+DW_OP_lt= 0x2D
+DW_OP_ne= 0x2E
+DW_OP_lit0  = 0x30
+DW_OP_lit1  = 0x31
+DW_OP_lit2  = 0x32
+DW_OP_lit3  = 0x33
+DW_OP_lit4  = 0x34
+DW_OP_lit5  = 0x35
+DW_OP_lit6  = 0x36
+DW_OP_lit7  = 0x37
+DW_OP_lit8  = 0x38
+DW_OP_lit9  = 0x39
+DW_OP_lit10 = 0x3A
+DW_OP_lit11 = 0x3B
+DW_OP_lit12 = 0x3C
+DW_OP_lit13 = 0x3D
+DW_OP_lit14 = 0x3E
+DW_OP_lit15 = 0x3F
+DW_OP_lit16 = 0x40
+DW_OP_lit17 = 0x41
+DW_OP_lit18 = 0x42
+DW_OP_lit19 = 0x43
+DW_OP_lit20 = 0x44
+DW_OP_lit21 = 0x45
+DW_OP_lit22 = 0x46
+DW_OP_lit23 = 0x47
+DW_OP_lit24 = 0x48
+DW_OP_lit25 = 0x49
+DW_OP_lit26 = 0x4A
+DW_OP_lit27 = 0x4B
+DW_OP_lit28 = 0x4C
+DW_OP_lit29 = 0x4D
+DW_OP_lit30 = 0x4E
+DW_OP_lit31 = 0x4F
+DW_OP_reg0  = 0x50
+DW_OP_reg1  = 0x51
+DW_OP_reg2  = 0x52
+DW_OP_reg3  = 0x53
+DW_OP_reg4  = 0x54
+DW_OP_reg5  = 0x55
+DW_OP_reg6  = 0x56
+DW_OP_reg7  = 0x57
+DW_OP_reg8  = 0x58
+DW_OP_reg9  = 0x59
+DW_OP_reg10 = 0x5A
+DW_OP_reg11 = 0x5B
+DW_OP_reg12 = 0x5C
+DW_OP_reg13 = 0x5D
+DW_OP_reg14 = 0x5E
+DW_OP_reg15 = 0x5F
+DW_OP_reg16

[Lldb-commits] [lldb] r291553 - [LLDB][MIPS] Revert TestLldbGdbServer failure for MIPS

2017-01-10 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Tue Jan 10 03:18:56 2017
New Revision: 291553

URL: http://llvm.org/viewvc/llvm-project?rev=291553=rev
Log:
[LLDB][MIPS] Revert TestLldbGdbServer failure for MIPS

Removed:
lldb/trunk/Python/
Modified:

lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-server/TestLldbGdbServer.py

Modified: 
lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-server/TestLldbGdbServer.py
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-server/TestLldbGdbServer.py?rev=291553=291552=291553=diff
==
--- 
lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-server/TestLldbGdbServer.py
 (original)
+++ 
lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-server/TestLldbGdbServer.py
 Tue Jan 10 03:18:56 2017
@@ -20,11 +20,10 @@ import platform
 import signal
 from lldbsuite.test.decorators import *
 from lldbsuite.test.lldbtest import *
-from lldbsuite.test.lldbdwarf import *
 from lldbsuite.test import lldbutil
 
 
-class LldbGdbServerTestCase(gdbremote_testcase.GdbRemoteTestCaseBase, 
DwarfOpcodeParser):
+class LldbGdbServerTestCase(gdbremote_testcase.GdbRemoteTestCaseBase):
 
 mydir = TestBase.compute_mydir(__file__)
 
@@ -542,10 +541,6 @@ class LldbGdbServerTestCase(gdbremote_te
 self.assertIsNotNone(reg_infos)
 self.assertTrue(len(reg_infos) > 0)
 
-inferior_exe_path = os.path.abspath("a.out")
-Target = self.dbg.CreateTarget(inferior_exe_path)
-byte_order = Target.GetByteOrder()
-
 # Read value for each register.
 reg_index = 0
 for reg_info in reg_infos:
@@ -570,9 +565,6 @@ class LldbGdbServerTestCase(gdbremote_te
 # Verify the response length.
 p_response = context.get("p_response")
 self.assertIsNotNone(p_response)
-
-if "dynamic_size_dwarf_expr_bytes" in reg_info:
-self.updateRegInfoBitsize(reg_info, byte_order)
 self.assertEqual(len(p_response), 2 * int(reg_info["bitsize"]) / 8)
 
 # Increment loop


___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] r291549 - [LLDB][MIPS] Fix TestLldbGdbServer failure for MIPS

2017-01-10 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Tue Jan 10 02:20:01 2017
New Revision: 291549

URL: http://llvm.org/viewvc/llvm-project?rev=291549=rev
Log:
[LLDB][MIPS] Fix TestLldbGdbServer failure for MIPS

Reviewers: labath, clayborg

Subscribers: jaydeep, bhushan, lldb-commits, slthakur

Differential Revision: https://reviews.llvm.org/D27088

Added:
lldb/trunk/Python/
lldb/trunk/Python/lldbsuite/
lldb/trunk/Python/lldbsuite/test/
lldb/trunk/Python/lldbsuite/test/lldbdwarf.py
Modified:

lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-server/TestLldbGdbServer.py

Added: lldb/trunk/Python/lldbsuite/test/lldbdwarf.py
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/Python/lldbsuite/test/lldbdwarf.py?rev=291549=auto
==
--- lldb/trunk/Python/lldbsuite/test/lldbdwarf.py (added)
+++ lldb/trunk/Python/lldbsuite/test/lldbdwarf.py Tue Jan 10 02:20:01 2017
@@ -0,0 +1,256 @@
+""" This module implement Dwarf expression opcode parser. """
+
+import lldb
+
+# DWARF Expression operators.
+DW_OP_addr  = 0x03
+DW_OP_deref = 0x06
+DW_OP_const1u   = 0x08
+DW_OP_const1s   = 0x09
+DW_OP_const2u   = 0x0A
+DW_OP_const2s   = 0x0B
+DW_OP_const4u   = 0x0C
+DW_OP_const4s   = 0x0D
+DW_OP_const8u   = 0x0E
+DW_OP_const8s   = 0x0F
+DW_OP_constu= 0x10
+DW_OP_consts= 0x11
+DW_OP_dup   = 0x12
+DW_OP_drop  = 0x13
+DW_OP_over  = 0x14
+DW_OP_pick  = 0x15
+DW_OP_swap  = 0x16
+DW_OP_rot   = 0x17
+DW_OP_xderef= 0x18
+DW_OP_abs   = 0x19
+DW_OP_and   = 0x1A
+DW_OP_div   = 0x1B
+DW_OP_minus = 0x1C
+DW_OP_mod   = 0x1D
+DW_OP_mul   = 0x1E
+DW_OP_neg   = 0x1F
+DW_OP_not   = 0x20
+DW_OP_or= 0x21
+DW_OP_plus  = 0x22
+DW_OP_plus_uconst   = 0x23
+DW_OP_shl   = 0x24
+DW_OP_shr   = 0x25
+DW_OP_shra  = 0x26
+DW_OP_xor   = 0x27
+DW_OP_skip  = 0x2F
+DW_OP_bra   = 0x28
+DW_OP_eq= 0x29
+DW_OP_ge= 0x2A
+DW_OP_gt= 0x2B
+DW_OP_le= 0x2C
+DW_OP_lt= 0x2D
+DW_OP_ne= 0x2E
+DW_OP_lit0  = 0x30
+DW_OP_lit1  = 0x31
+DW_OP_lit2  = 0x32
+DW_OP_lit3  = 0x33
+DW_OP_lit4  = 0x34
+DW_OP_lit5  = 0x35
+DW_OP_lit6  = 0x36
+DW_OP_lit7  = 0x37
+DW_OP_lit8  = 0x38
+DW_OP_lit9  = 0x39
+DW_OP_lit10 = 0x3A
+DW_OP_lit11 = 0x3B
+DW_OP_lit12 = 0x3C
+DW_OP_lit13 = 0x3D
+DW_OP_lit14 = 0x3E
+DW_OP_lit15 = 0x3F
+DW_OP_lit16 = 0x40
+DW_OP_lit17 = 0x41
+DW_OP_lit18 = 0x42
+DW_OP_lit19 = 0x43
+DW_OP_lit20 = 0x44
+DW_OP_lit21 = 0x45
+DW_OP_lit22 = 0x46
+DW_OP_lit23 = 0x47
+DW_OP_lit24 = 0x48
+DW_OP_lit25 = 0x49
+DW_OP_lit26 = 0x4A
+DW_OP_lit27 = 0x4B
+DW_OP_lit28 = 0x4C
+DW_OP_lit29 = 0x4D
+DW_OP_lit30 = 0x4E
+DW_OP_lit31 = 0x4F
+DW_OP_reg0  = 0x50
+DW_OP_reg1  = 0x51
+DW_OP_reg2  = 0x52
+DW_OP_reg3  = 0x53
+DW_OP_reg4  = 0x54
+DW_OP_reg5  = 0x55
+DW_OP_reg6  = 0x56
+DW_OP_reg7  = 0x57
+DW_OP_reg8  = 0x58
+DW_OP_reg9  = 0x59
+DW_OP_reg10 = 0x5A
+DW_OP_reg11 = 0x5B
+DW_OP_reg12 = 0x5C
+DW_OP_reg13 = 0x5D
+DW_OP_reg14 = 0x5E

[Lldb-commits] [lldb] r289211 - [LLDB][MIPS] Fix TestWatchpointIter failure

2016-12-09 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Fri Dec  9 07:54:47 2016
New Revision: 289211

URL: http://llvm.org/viewvc/llvm-project?rev=289211=rev
Log:
[LLDB][MIPS] Fix TestWatchpointIter failure

Reviewers: jingham

Subscribers: jaydeep, bhushan, slthakur, lldb-commits

Differential Revision: https://reviews.llvm.org/D27124

Modified:
lldb/trunk/source/Target/StopInfo.cpp

Modified: lldb/trunk/source/Target/StopInfo.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Target/StopInfo.cpp?rev=289211=289210=289211=diff
==
--- lldb/trunk/source/Target/StopInfo.cpp (original)
+++ lldb/trunk/source/Target/StopInfo.cpp Fri Dec  9 07:54:47 2016
@@ -692,7 +692,13 @@ protected:
 if (process_sp->GetWatchpointSupportInfo(num, wp_triggers_after)
 .Success()) {
   if (!wp_triggers_after) {
-process_sp->DisableWatchpoint(wp_sp.get(), false);
+// We need to preserve the watch_index before watchpoint 
+// is disable. Since Watchpoint::SetEnabled will clear the
+// watch index.
+// This will fix TestWatchpointIter failure
+Watchpoint *wp = wp_sp.get();
+uint32_t watch_index = wp->GetHardwareIndex();
+process_sp->DisableWatchpoint(wp, false);
 StopInfoSP stored_stop_info_sp = thread_sp->GetStopInfo();
 assert(stored_stop_info_sp.get() == this);
 
@@ -710,7 +716,8 @@ protected:
 process_sp->GetThreadList().SetSelectedThreadByID(
 thread_sp->GetID());
 thread_sp->SetStopInfo(stored_stop_info_sp);
-process_sp->EnableWatchpoint(wp_sp.get(), false);
+process_sp->EnableWatchpoint(wp, false);
+wp->SetHardwareIndex(watch_index);
   }
 }
   }


___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] r289210 - [LLDB][MIPS] Fix TestMultipleHits for MIPS

2016-12-09 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Fri Dec  9 07:44:15 2016
New Revision: 289210

URL: http://llvm.org/viewvc/llvm-project?rev=289210=rev
Log:
[LLDB][MIPS] Fix TestMultipleHits for MIPS

Reviewers: clayborg, labath, zturner

Subscribers: jaydeep, bhushan, slthakur, lldb-commits

Differential Revision: https://reviews.llvm.org/D27085

Modified:

lldb/trunk/packages/Python/lldbsuite/test/functionalities/watchpoint/multiple_hits/main.cpp

Modified: 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/watchpoint/multiple_hits/main.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/functionalities/watchpoint/multiple_hits/main.cpp?rev=289210=289209=289210=diff
==
--- 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/watchpoint/multiple_hits/main.cpp
 (original)
+++ 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/watchpoint/multiple_hits/main.cpp
 Fri Dec  9 07:44:15 2016
@@ -8,9 +8,7 @@
 
//===--===//
 #include 
 #include 
-
 alignas(16) uint8_t buf[32];
-
 // This uses inline assembly to generate an instruction that writes to a large
 // block of memory. If it fails on your compiler/architecture, please add
 // appropriate code to generate a large write to "buf". If you cannot write at
@@ -24,6 +22,8 @@ int main() {
   asm volatile ("stm %0, { r0, r1, r2, r3 }" : : "r"(buf));
 #elif defined(__aarch64__)
   asm volatile ("stp x0, x1, %0" : : "m"(buf));
+#elif defined(__mips__)
+  asm volatile ("lw $2, %0" : : "m"(buf));
 #endif
   return 0;
 }


___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] r289209 - [LLDB][MIPS] Fix some test case failures due to elf_abi field of qprocessInfo packet.

2016-12-09 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Fri Dec  9 07:37:14 2016
New Revision: 289209

URL: http://llvm.org/viewvc/llvm-project?rev=289209=rev
Log:
[LLDB][MIPS] Fix some test case failures due to elf_abi field of qprocessInfo 
packet.

Reviewers: jaydeep, bhushan, clayborg

Subscribers: slthakur, lldb-commits

Differential Revision: https://reviews.llvm.org/D26542

Modified:

lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py

Modified: 
lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py?rev=289209=289208=289209=diff
==
--- 
lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
 (original)
+++ 
lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
 Fri Dec  9 07:37:14 2016
@@ -663,6 +663,7 @@ class GdbRemoteTestCaseBase(TestBase):
 "triple",
 "vendor",
 "endian",
+"elf_abi",
 "ptrsize"
 ]
 


___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [PATCH] D27088: [LLDB][MIPS] Fix TestLldbGdbServer failure for MIPS

2016-11-24 Thread Nitesh Jain via lldb-commits

nitesh.jain created this revision.
nitesh.jain added reviewers: clayborg, labath, zturner.
nitesh.jain added subscribers: jaydeep, bhushan, slthakur, lldb-commits.

In case of MIPS, the floating point register size is based on FR bit of status 
register(SR) (https://reviews.llvm.org/rL277343). In this patch, we update 
reg_info["bitsize"] based on SR.FR bit.


https://reviews.llvm.org/D27088

Files:
  packages/Python/lldbsuite/test/tools/lldb-server/TestLldbGdbServer.py


Index: packages/Python/lldbsuite/test/tools/lldb-server/TestLldbGdbServer.py
===
--- packages/Python/lldbsuite/test/tools/lldb-server/TestLldbGdbServer.py
+++ packages/Python/lldbsuite/test/tools/lldb-server/TestLldbGdbServer.py
@@ -12,6 +12,7 @@
 
 from __future__ import print_function
 
+import struct
 
 import unittest2
 import gdbremote_testcase
@@ -565,6 +566,26 @@
 # Verify the response length.
 p_response = context.get("p_response")
 self.assertIsNotNone(p_response)
+triple = lldb.DBG.GetSelectedPlatform().GetTriple()
+
+if re.match("^mips",triple):
+if reg_info["name"] == "sr":
+split_triple = triple.split("--",1)
+if split_triple[0] == "mips64el" or split_triple == 
"mipsel":
+# In case of little endian
+# first decode the HEX ASCII bytes and then reverse it
+# to get actual value of SR register  
+p_response = "".join(reversed([p_response[i:i+2] for i 
in range(0,
+ len(p_response),2)]))
+# Check for SR.FR bit
+# if SR.FR(26) == 0 && reg_info["format"] == "float"
+# then reg_info["bitsize"] = 32
+sr_value = int(p_response,16)
+flag = 1
+flag = (sr_value >> 26) & flag
+
+if reg_info["format"] == "float" and (flag != 1):
+reg_info["bitsize"] = 32
 self.assertEqual(len(p_response), 2 * int(reg_info["bitsize"]) / 8)
 
 # Increment loop


Index: packages/Python/lldbsuite/test/tools/lldb-server/TestLldbGdbServer.py
===
--- packages/Python/lldbsuite/test/tools/lldb-server/TestLldbGdbServer.py
+++ packages/Python/lldbsuite/test/tools/lldb-server/TestLldbGdbServer.py
@@ -12,6 +12,7 @@
 
 from __future__ import print_function
 
+import struct
 
 import unittest2
 import gdbremote_testcase
@@ -565,6 +566,26 @@
 # Verify the response length.
 p_response = context.get("p_response")
 self.assertIsNotNone(p_response)
+triple = lldb.DBG.GetSelectedPlatform().GetTriple()
+
+if re.match("^mips",triple):
+if reg_info["name"] == "sr":
+split_triple = triple.split("--",1)
+if split_triple[0] == "mips64el" or split_triple == "mipsel":
+# In case of little endian
+# first decode the HEX ASCII bytes and then reverse it
+# to get actual value of SR register  
+p_response = "".join(reversed([p_response[i:i+2] for i in range(0,
+ len(p_response),2)]))
+# Check for SR.FR bit
+# if SR.FR(26) == 0 && reg_info["format"] == "float"
+# then reg_info["bitsize"] = 32
+sr_value = int(p_response,16)
+flag = 1
+flag = (sr_value >> 26) & flag
+
+if reg_info["format"] == "float" and (flag != 1):
+reg_info["bitsize"] = 32
 self.assertEqual(len(p_response), 2 * int(reg_info["bitsize"]) / 8)
 
 # Increment loop
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [PATCH] D27085: [LLDB][MIPS] Fix TestMultipleHits for MIPS

2016-11-23 Thread Nitesh Jain via lldb-commits

nitesh.jain created this revision.
nitesh.jain added reviewers: labath, clayborg, zturner.
nitesh.jain added subscribers: jaydeep, bhushan, slthakur, lldb-commits.

https://reviews.llvm.org/D27085

Files:
  
packages/Python/lldbsuite/test/functionalities/watchpoint/multiple_hits/main.cpp


Index: 
packages/Python/lldbsuite/test/functionalities/watchpoint/multiple_hits/main.cpp
===
--- 
packages/Python/lldbsuite/test/functionalities/watchpoint/multiple_hits/main.cpp
+++ 
packages/Python/lldbsuite/test/functionalities/watchpoint/multiple_hits/main.cpp
@@ -8,9 +8,7 @@
 
//===--===//
 #include 
 #include 
-
 alignas(16) uint8_t buf[32];
-
 // This uses inline assembly to generate an instruction that writes to a large
 // block of memory. If it fails on your compiler/architecture, please add
 // appropriate code to generate a large write to "buf". If you cannot write at
@@ -24,6 +22,8 @@
   asm volatile ("stm %0, { r0, r1, r2, r3 }" : : "r"(buf));
 #elif defined(__aarch64__)
   asm volatile ("stp x0, x1, %0" : : "m"(buf));
+#elif defined(__mips__)
+  asm volatile ("lw $2, %0" : : "m"(buf));
 #endif
   return 0;
 }


Index: packages/Python/lldbsuite/test/functionalities/watchpoint/multiple_hits/main.cpp
===
--- packages/Python/lldbsuite/test/functionalities/watchpoint/multiple_hits/main.cpp
+++ packages/Python/lldbsuite/test/functionalities/watchpoint/multiple_hits/main.cpp
@@ -8,9 +8,7 @@
 //===--===//
 #include 
 #include 
-
 alignas(16) uint8_t buf[32];
-
 // This uses inline assembly to generate an instruction that writes to a large
 // block of memory. If it fails on your compiler/architecture, please add
 // appropriate code to generate a large write to "buf". If you cannot write at
@@ -24,6 +22,8 @@
   asm volatile ("stm %0, { r0, r1, r2, r3 }" : : "r"(buf));
 #elif defined(__aarch64__)
   asm volatile ("stp x0, x1, %0" : : "m"(buf));
+#elif defined(__mips__)
+  asm volatile ("lw $2, %0" : : "m"(buf));
 #endif
   return 0;
 }
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [PATCH] D26542: [LLDB][MIPS] Fix some test case failures due to "elf_abi" field of qprocessInfo packet

2016-11-11 Thread Nitesh Jain via lldb-commits

nitesh.jain added a comment.

The elf_abi field was introduced in qprocessInfo packet (commit 
https://reviews.llvm.org/rL284001) so that LLDB can set pointer size and parse 
aux vector accordingly. This patch fix some test cases failures by introducing 
this field in  _KNOWN_PROCESS_INFO_KEYS.


https://reviews.llvm.org/D26542



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [PATCH] D26542: [LLDB][MIPS] Fix some test case failures due to "elf_abi" field of qprocessInfo packet

2016-11-11 Thread Nitesh Jain via lldb-commits

nitesh.jain created this revision.
nitesh.jain added reviewers: jaydeep, bhushan, clayborg.
nitesh.jain added subscribers: lldb-commits, slthakur.

https://reviews.llvm.org/D26542

Files:
  packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py


Index: packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
===
--- packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
+++ packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
@@ -663,6 +663,7 @@
 "triple",
 "vendor",
 "endian",
+"elf_abi",
 "ptrsize"
 ]
 


Index: packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
===
--- packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
+++ packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
@@ -663,6 +663,7 @@
 "triple",
 "vendor",
 "endian",
+"elf_abi",
 "ptrsize"
 ]
 
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [PATCH] D25021: [LLDB][MIPS] Fix qProcessInfo to return correct pointer size based on ELF ABI

2016-10-12 Thread Nitesh Jain via lldb-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL284001: [LLDB][MIPS] Fix qProcessInfo to return correct 
pointer size based on ELF ABI (authored by nitesh.jain).

Changed prior to commit:
  https://reviews.llvm.org/D25021?vs=73029=74356#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D25021

Files:
  lldb/trunk/include/lldb/Core/ArchSpec.h
  lldb/trunk/source/Core/ArchSpec.cpp
  lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
  
lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.cpp

Index: lldb/trunk/include/lldb/Core/ArchSpec.h
===
--- lldb/trunk/include/lldb/Core/ArchSpec.h
+++ lldb/trunk/include/lldb/Core/ArchSpec.h
@@ -310,6 +310,13 @@
   std::string GetClangTargetCPU();
 
   //--
+  /// Return a string representing target application ABI.
+  ///
+  /// @return A string representing target application ABI.
+  //--
+  std::string GetTargetABI() const;
+
+  //--
   /// Clears the object state.
   ///
   /// Clears the object state back to a default invalid state.
@@ -596,6 +603,8 @@
 
   void SetFlags(uint32_t flags) { m_flags = flags; }
 
+  void SetFlags(std::string elf_abi);
+
 protected:
   bool IsEqualTo(const ArchSpec , bool exact_match) const;
 
Index: lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.cpp
===
--- lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.cpp
+++ lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.cpp
@@ -1262,13 +1262,12 @@
   // Nothing.
   break;
 }
-
-if (proc_triple.isArch64Bit())
-  response.PutCString("ptrsize:8;");
-else if (proc_triple.isArch32Bit())
-  response.PutCString("ptrsize:4;");
-else if (proc_triple.isArch16Bit())
-  response.PutCString("ptrsize:2;");
+// In case of MIPS64, pointer size is depend on ELF ABI
+// For N32 the pointer size is 4 and for N64 it is 8
+std::string abi = proc_arch.GetTargetABI();
+if (!abi.empty())
+  response.Printf("elf_abi:%s;", abi.c_str());
+response.Printf("ptrsize:%d;", proc_arch.GetAddressByteSize());
   }
 }
 
Index: lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
===
--- lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
+++ lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
@@ -1849,6 +1849,7 @@
   std::string os_name;
   std::string vendor_name;
   std::string triple;
+  std::string elf_abi;
   uint32_t pointer_byte_size = 0;
   StringExtractor extractor;
   ByteOrder byte_order = eByteOrderInvalid;
@@ -1885,6 +1886,9 @@
 } else if (name.equals("pid")) {
   if (!value.getAsInteger(16, pid))
 ++num_keys_decoded;
+} else if (name.equals("elf_abi")) {
+  elf_abi = value;
+  ++num_keys_decoded;
 }
   }
   if (num_keys_decoded > 0)
@@ -1897,6 +1901,7 @@
   // Set the ArchSpec from the triple if we have it.
   if (!triple.empty()) {
 m_process_arch.SetTriple(triple.c_str());
+m_process_arch.SetFlags(elf_abi);
 if (pointer_byte_size) {
   assert(pointer_byte_size == m_process_arch.GetAddressByteSize());
 }
Index: lldb/trunk/source/Core/ArchSpec.cpp
===
--- lldb/trunk/source/Core/ArchSpec.cpp
+++ lldb/trunk/source/Core/ArchSpec.cpp
@@ -621,6 +621,42 @@
   return false;
 }
 
+std::string ArchSpec::GetTargetABI() const {
+
+  std::string abi;
+
+  if (IsMIPS()) {
+switch (GetFlags() & ArchSpec::eMIPSABI_mask) {
+case ArchSpec::eMIPSABI_N64:
+  abi = "n64";
+  return abi;
+case ArchSpec::eMIPSABI_N32:
+  abi = "n32";
+  return abi;
+case ArchSpec::eMIPSABI_O32:
+  abi = "o32";
+  return abi;
+default:
+  return abi;
+}
+  }
+  return abi;
+}
+
+void ArchSpec::SetFlags(std::string elf_abi) {
+
+  uint32_t flag = GetFlags();
+  if (IsMIPS()) {
+if (elf_abi == "n64")
+  flag |= ArchSpec::eMIPSABI_N64;
+else if (elf_abi == "n32")
+  flag |= ArchSpec::eMIPSABI_N32;
+else if (elf_abi == "o32")
+  flag |= ArchSpec::eMIPSABI_O32;
+  }
+  SetFlags(flag);
+}
+
 std::string ArchSpec::GetClangTargetCPU() {
   std::string cpu;
   const llvm::Triple::ArchType machine = GetMachine();
@@ -815,7 +851,8 @@
   return IsValid();
 }
 
-bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, ArchSpec ) {
+bool

[Lldb-commits] [PATCH] D24603: [LLDB][MIPS] fix Floating point register read/write for big endian

2016-10-12 Thread Nitesh Jain via lldb-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL284003: [LLDB][MIPS] fix Floating point register read/write 
for big endian (authored by nitesh.jain).

Changed prior to commit:
  https://reviews.llvm.org/D24603?vs=73278=74357#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D24603

Files:
  lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
  lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.h
  lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_mips.h
  lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_mips64.h
  lldb/trunk/source/Plugins/Process/Utility/lldb-mips-linux-register-enums.h

Index: lldb/trunk/source/Plugins/Process/Utility/lldb-mips-linux-register-enums.h
===
--- lldb/trunk/source/Plugins/Process/Utility/lldb-mips-linux-register-enums.h
+++ lldb/trunk/source/Plugins/Process/Utility/lldb-mips-linux-register-enums.h
@@ -282,6 +282,84 @@
 k_num_fpr_registers_mips64 +
 k_num_msa_registers_mips64
 };
+
+// Register no. for RegisterKind = eRegisterKindProcessPlugin
+// The ptrace request PTRACE_PEEKUSER/PTRACE_POKEUSER used this number
+enum {
+  ptrace_zero_mips,
+  ptrace_r1_mips,
+  ptrace_r2_mips,
+  ptrace_r3_mips,
+  ptrace_r4_mips,
+  ptrace_r5_mips,
+  ptrace_r6_mips,
+  ptrace_r7_mips,
+  ptrace_r8_mips,
+  ptrace_r9_mips,
+  ptrace_r10_mips,
+  ptrace_r11_mips,
+  ptrace_r12_mips,
+  ptrace_r13_mips,
+  ptrace_r14_mips,
+  ptrace_r15_mips,
+  ptrace_r16_mips,
+  ptrace_r17_mips,
+  ptrace_r18_mips,
+  ptrace_r19_mips,
+  ptrace_r20_mips,
+  ptrace_r21_mips,
+  ptrace_r22_mips,
+  ptrace_r23_mips,
+  ptrace_r24_mips,
+  ptrace_r25_mips,
+  ptrace_r26_mips,
+  ptrace_r27_mips,
+  ptrace_gp_mips,
+  ptrace_sp_mips,
+  ptrace_r30_mips,
+  ptrace_ra_mips,
+  ptrace_f0_mips,
+  ptrace_f1_mips,
+  ptrace_f2_mips,
+  ptrace_f3_mips,
+  ptrace_f4_mips,
+  ptrace_f5_mips,
+  ptrace_f6_mips,
+  ptrace_f7_mips,
+  ptrace_f8_mips,
+  ptrace_f9_mips,
+  ptrace_f10_mips,
+  ptrace_f11_mips,
+  ptrace_f12_mips,
+  ptrace_f13_mips,
+  ptrace_f14_mips,
+  ptrace_f15_mips,
+  ptrace_f16_mips,
+  ptrace_f17_mips,
+  ptrace_f18_mips,
+  ptrace_f19_mips,
+  ptrace_f20_mips,
+  ptrace_f21_mips,
+  ptrace_f22_mips,
+  ptrace_f23_mips,
+  ptrace_f24_mips,
+  ptrace_f25_mips,
+  ptrace_f26_mips,
+  ptrace_f27_mips,
+  ptrace_f28_mips,
+  ptrace_f29_mips,
+  ptrace_f30_mips,
+  ptrace_f31_mips,
+  ptrace_pc_mips,
+  ptrace_cause_mips,
+  ptrace_badvaddr_mips,
+  ptrace_mulhi_mips,
+  ptrace_mullo_mips,
+  ptrace_fcsr_mips,
+  ptrace_fir_mips,
+  ptrace_sr_mips,
+  ptrace_config5_mips
+};
 }
 
 #endif // #ifndef lldb_mips_linux_register_enums_h
Index: lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_mips.h
===
--- lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_mips.h
+++ lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_mips.h
@@ -35,11 +35,11 @@
LLVM_EXTENSION offsetof(MSA_linux_mips, regname))
 
 // Note that the size and offset will be updated by platform-specific classes.
-#define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4)   \
+#define DEFINE_GPR(reg, alt, kind1, kind2, kind3)  \
   {\
 #reg, alt, sizeof(((GPR_linux_mips *) NULL)->reg) / 2, \
   GPR_OFFSET(reg), eEncodingUint, eFormatHex,  \
- {kind1, kind2, kind3, kind4,  \
+ {kind1, kind2, kind3, ptrace_##reg##_mips,\
   gpr_##reg##_mips },  \
   NULL, NULL, NULL, 0  \
   }
@@ -49,21 +49,21 @@
 llvm::dwarf::DW_OP_lit26, llvm::dwarf::DW_OP_shl, llvm::dwarf::DW_OP_and,
 llvm::dwarf::DW_OP_lit26, llvm::dwarf::DW_OP_shr};
 
-#define DEFINE_FPR(reg, alt, kind1, kind2, kind3, kind4)   \
+#define DEFINE_FPR(reg, alt, kind1, kind2, kind3)  \
   {\
 #reg, alt, sizeof(((FPR_linux_mips *) NULL)->reg), \
   FPR_OFFSET(reg), eEncodingIEEE754, eFormatFloat, \
- {kind1, kind2, kind3, kind4,  \
+ {kind1, kind2, kind3, ptrace_##reg##_mips,\
   fpr_##reg##_mips },  \
   NULL, NULL, dwarf_opcode_mips,   \
   sizeof(dwarf_opcode_mips)\
   }
 
-#define

[Lldb-commits] [PATCH] D24603: [LLDB][MIPS] fix Floating point register read/write for big endian

2016-10-12 Thread Nitesh Jain via lldb-commits

nitesh.jain added a comment.

In https://reviews.llvm.org/D24603#566575, @clayborg wrote:

> Commit anytime.


Thanks


https://reviews.llvm.org/D24603



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] r284003 - [LLDB][MIPS] fix Floating point register read/write for big endian

2016-10-12 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Wed Oct 12 05:53:57 2016
New Revision: 284003

URL: http://llvm.org/viewvc/llvm-project?rev=284003=rev
Log:
[LLDB][MIPS] fix Floating point register read/write for big endian

Reviewers: clayborg, labath, jaydeep

Subscribers: bhushan, slthakur, lldb-commits

Differential Revision: https://reviews.llvm.org/D24603

Modified:

lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.h
lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_mips.h
lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_mips64.h
lldb/trunk/source/Plugins/Process/Utility/lldb-mips-linux-register-enums.h

Modified: 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp?rev=284003=284002=284003=diff
==
--- 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp 
(original)
+++ 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp 
Wed Oct 12 05:53:57 2016
@@ -26,6 +26,7 @@
 #include "lldb/Core/RegisterValue.h"
 #include "lldb/Host/Host.h"
 #include "lldb/Host/HostInfo.h"
+#include "lldb/Utility/LLDBAssert.h"
 #include "lldb/lldb-enumerations.h"
 #include "lldb/lldb-private-enumerations.h"
 #define NT_MIPS_MSA 0x600
@@ -392,6 +393,7 @@ NativeRegisterContextLinux_mips64::ReadR
   }
 
   const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB];
+  uint8_t byte_size = reg_info->byte_size;
   if (reg == LLDB_INVALID_REGNUM) {
 // This is likely an internal register for lldb use only and should not be
 // directly queried.
@@ -407,7 +409,8 @@ NativeRegisterContextLinux_mips64::ReadR
   }
 
   if (IsMSA(reg) || IsFPR(reg)) {
-uint8_t *src;
+uint8_t *src = nullptr;
+lldbassert(reg_info->byte_offset < sizeof(UserArea));
 
 error = ReadCP1();
 
@@ -417,14 +420,17 @@ NativeRegisterContextLinux_mips64::ReadR
 }
 
 if (IsFPR(reg)) {
-  assert(reg_info->byte_offset < sizeof(UserArea));
-  src = (uint8_t *)_fpr + reg_info->byte_offset - (sizeof(m_gpr));
-} else {
-  assert(reg_info->byte_offset < sizeof(UserArea));
+  if (IsFR0() && (byte_size != 4)) {
+byte_size = 4;
+uint8_t ptrace_index;
+ptrace_index = reg_info->kinds[lldb::eRegisterKindProcessPlugin];
+src = ReturnFPOffset(ptrace_index, reg_info->byte_offset);
+  } else
+src = (uint8_t *)_fpr + reg_info->byte_offset - sizeof(m_gpr);
+} else
   src = (uint8_t *)_msa + reg_info->byte_offset -
 (sizeof(m_gpr) + sizeof(m_fpr));
-}
-switch (reg_info->byte_size) {
+switch (byte_size) {
 case 4:
   reg_value.SetUInt32(*(uint32_t *)src);
   break;
@@ -466,21 +472,26 @@ lldb_private::Error NativeRegisterContex
   }
 
   if (IsFPR(reg_index) || IsMSA(reg_index)) {
-uint8_t *dst;
-uint64_t *src;
+uint8_t *dst = nullptr;
+uint64_t *src = nullptr;
+uint8_t byte_size = reg_info->byte_size;
+lldbassert(reg_info->byte_offset < sizeof(UserArea));
 
 // Initialise the FP and MSA buffers by reading all co-processor 1 
registers
 ReadCP1();
 
 if (IsFPR(reg_index)) {
-  assert(reg_info->byte_offset < sizeof(UserArea));
-  dst = (uint8_t *)_fpr + reg_info->byte_offset - (sizeof(m_gpr));
-} else {
-  assert(reg_info->byte_offset < sizeof(UserArea));
+  if (IsFR0() && (byte_size != 4)) {
+byte_size = 4;
+uint8_t ptrace_index;
+ptrace_index = reg_info->kinds[lldb::eRegisterKindProcessPlugin];
+dst = ReturnFPOffset(ptrace_index, reg_info->byte_offset);
+  } else
+dst = (uint8_t *)_fpr + reg_info->byte_offset - sizeof(m_gpr);
+} else
   dst = (uint8_t *)_msa + reg_info->byte_offset -
 (sizeof(m_gpr) + sizeof(m_fpr));
-}
-switch (reg_info->byte_size) {
+switch (byte_size) {
 case 4:
   *(uint32_t *)dst = reg_value.GetAsUInt32();
   break;
@@ -611,11 +622,12 @@ Error NativeRegisterContextLinux_mips64:
 Error NativeRegisterContextLinux_mips64::ReadCP1() {
   Error error;
 
-  uint8_t *src, *dst;
+  uint8_t *src = nullptr;
+  uint8_t *dst = nullptr;
 
   lldb::ByteOrder byte_order = GetByteOrder();
 
-  uint32_t IsBigEndian = (byte_order == lldb::eByteOrderBig);
+  bool IsBigEndian = (byte_order == lldb::eByteOrderBig);
 
   if (IsMSAAvailable()) {
 error = NativeRegisterContextLinux::ReadRegisterSet(
@@ -634,42 +646,36 @@ Error NativeRegisterContextLinux_mips64:
   } else {
 error = NativeRegisterContextLinux::ReadFPR();
   }
+  return error;
+}
 
-  // TODO: Add support for FRE
-  if (IsFR0()) {
-src = (uint8_t *)_fpr + 4 + (IsBigEndian * 4);
-dst = (uint8_t *)_fpr + 8 + (IsBigEndian * 4);
-for (int i = 0; i <

[Lldb-commits] [lldb] r284001 - [LLDB][MIPS] Fix qProcessInfo to return correct pointer size based on ELF ABI

2016-10-12 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Wed Oct 12 05:21:09 2016
New Revision: 284001

URL: http://llvm.org/viewvc/llvm-project?rev=284001=rev
Log:
[LLDB][MIPS] Fix qProcessInfo to return correct pointer size based on ELF ABI

Reviewers: clayborg, labath

Subscribers: jaydeep, bhushan, slthakur, lldb-commits

Differential Revision: https://reviews.llvm.org/D25021

Modified:
lldb/trunk/include/lldb/Core/ArchSpec.h
lldb/trunk/source/Core/ArchSpec.cpp

lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp

lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.cpp

Modified: lldb/trunk/include/lldb/Core/ArchSpec.h
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/include/lldb/Core/ArchSpec.h?rev=284001=284000=284001=diff
==
--- lldb/trunk/include/lldb/Core/ArchSpec.h (original)
+++ lldb/trunk/include/lldb/Core/ArchSpec.h Wed Oct 12 05:21:09 2016
@@ -310,6 +310,13 @@ public:
   std::string GetClangTargetCPU();
 
   //--
+  /// Return a string representing target application ABI.
+  ///
+  /// @return A string representing target application ABI.
+  //--
+  std::string GetTargetABI() const;
+
+  //--
   /// Clears the object state.
   ///
   /// Clears the object state back to a default invalid state.
@@ -596,6 +603,8 @@ public:
 
   void SetFlags(uint32_t flags) { m_flags = flags; }
 
+  void SetFlags(std::string elf_abi);
+
 protected:
   bool IsEqualTo(const ArchSpec , bool exact_match) const;
 

Modified: lldb/trunk/source/Core/ArchSpec.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Core/ArchSpec.cpp?rev=284001=284000=284001=diff
==
--- lldb/trunk/source/Core/ArchSpec.cpp (original)
+++ lldb/trunk/source/Core/ArchSpec.cpp Wed Oct 12 05:21:09 2016
@@ -621,6 +621,42 @@ bool ArchSpec::IsMIPS() const {
   return false;
 }
 
+std::string ArchSpec::GetTargetABI() const {
+
+  std::string abi;
+
+  if (IsMIPS()) {
+switch (GetFlags() & ArchSpec::eMIPSABI_mask) {
+case ArchSpec::eMIPSABI_N64:
+  abi = "n64";
+  return abi;
+case ArchSpec::eMIPSABI_N32:
+  abi = "n32";
+  return abi;
+case ArchSpec::eMIPSABI_O32:
+  abi = "o32";
+  return abi;
+default:
+  return abi;
+}
+  }
+  return abi;
+}
+
+void ArchSpec::SetFlags(std::string elf_abi) {
+
+  uint32_t flag = GetFlags();
+  if (IsMIPS()) {
+if (elf_abi == "n64")
+  flag |= ArchSpec::eMIPSABI_N64;
+else if (elf_abi == "n32")
+  flag |= ArchSpec::eMIPSABI_N32;
+else if (elf_abi == "o32")
+  flag |= ArchSpec::eMIPSABI_O32;
+  }
+  SetFlags(flag);
+}
+
 std::string ArchSpec::GetClangTargetCPU() {
   std::string cpu;
   const llvm::Triple::ArchType machine = GetMachine();
@@ -815,7 +851,8 @@ bool ArchSpec::SetTriple(const llvm::Tri
   return IsValid();
 }
 
-bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, 
ArchSpec ) {
+bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str,
+ ArchSpec ) {
   // Accept "12-10" or "12.10" as cpu type/subtype
   if (triple_str.empty())
 return false;

Modified: 
lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp?rev=284001=284000=284001=diff
==
--- 
lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp 
(original)
+++ 
lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp 
Wed Oct 12 05:21:09 2016
@@ -1849,6 +1849,7 @@ bool GDBRemoteCommunicationClient::GetCu
   std::string os_name;
   std::string vendor_name;
   std::string triple;
+  std::string elf_abi;
   uint32_t pointer_byte_size = 0;
   StringExtractor extractor;
   ByteOrder byte_order = eByteOrderInvalid;
@@ -1885,6 +1886,9 @@ bool GDBRemoteCommunicationClient::GetCu
 } else if (name.equals("pid")) {
   if (!value.getAsInteger(16, pid))
 ++num_keys_decoded;
+} else if (name.equals("elf_abi")) {
+  elf_abi = value;
+  ++num_keys_decoded;
 }
   }
   if (num_keys_decoded > 0)
@@ -1897,6 +1901,7 @@ bool GDBRemoteCommunicationClient::GetCu
   // Set the ArchSpec from the triple if we have it.
   if (!triple.empty()) {
 m_process_arch.SetTriple(triple.c_str());
+m_process_arch.SetFlags(elf_abi);
 if (pointer_byte_size) {
   assert(pointer_byte_size == m_process_arch.GetAddressByteSize());
 }

[Lldb-commits] [PATCH] D24498: [LLDB][MIPS] Fix TestReturnValue failure for MIPS

2016-10-11 Thread Nitesh Jain via lldb-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL283729: [LLDB][MIPS] Fix TestReturnValue failure for MIPS 
(authored by nitesh.jain).

Changed prior to commit:
  https://reviews.llvm.org/D24498?vs=71131=74203#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D24498

Files:
  lldb/trunk/source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp

Index: lldb/trunk/source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp
===
--- lldb/trunk/source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp
+++ lldb/trunk/source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp
@@ -923,23 +923,26 @@
target->GetArchitecture().GetAddressByteSize());
 
   RegisterValue r2_value, r3_value, f0_value, f1_value, f2_value;
+  // Tracks how much bytes of r2 and r3 registers we've consumed so far
+  uint32_t integer_bytes = 0;
 
-  uint32_t integer_bytes = 0; // Tracks how much bytes of r2 and r3
-  // registers we've consumed so far
-  bool use_fp_regs = 0; // True if return values are in FP return registers.
-  bool found_non_fp_field =
-  0; // True if we found any non floating point field in structure.
-  bool use_r2 = 0; // True if return values are in r2 register.
-  bool use_r3 = 0; // True if return values are in r3 register.
-  bool sucess = 0; // True if the result is copied into our data buffer
+  // True if return values are in FP return registers.
+  bool use_fp_regs = 0;
+  // True if we found any non floating point field in structure.
+  bool found_non_fp_field = 0;
+  // True if return values are in r2 register.
+  bool use_r2 = 0;
+  // True if return values are in r3 register.
+  bool use_r3 = 0;
+  // True if the result is copied into our data buffer
+  bool sucess = 0;
   std::string name;
   bool is_complex;
   uint32_t count;
   const uint32_t num_children = return_compiler_type.GetNumFields();
 
   // A structure consisting of one or two FP values (and nothing else) will
-  // be
-  // returned in the two FP return-value registers i.e fp0 and fp2.
+  // be returned in the two FP return-value registers i.e fp0 and fp2.
   if (num_children <= 2) {
 uint64_t field_bit_offset = 0;
 
@@ -967,7 +970,6 @@
   reg_ctx->ReadRegister(f2_info, f2_value);
 
   f0_value.GetData(f0_data);
-  f2_value.GetData(f2_data);
 
   for (uint32_t idx = 0; idx < num_children; idx++) {
 CompilerType field_compiler_type =
@@ -977,30 +979,40 @@
 field_compiler_type.GetByteSize(nullptr);
 
 DataExtractor *copy_from_extractor = nullptr;
+uint64_t return_value[2];
+offset_t offset = 0;
 
 if (idx == 0) {
-  if (field_byte_width == 16) // This case is for long double type.
-  {
+  // This case is for long double type.
+  if (field_byte_width == 16) {
+
 // If structure contains long double type, then it is returned
 // in fp0/fp1 registers.
-reg_ctx->ReadRegister(f1_info, f1_value);
-f1_value.GetData(f1_data);
-
 if (target_byte_order == eByteOrderLittle) {
-  f0_data.Append(f1_data);
-  copy_from_extractor = _data;
+  return_value[0] = f0_data.GetU64();
+  reg_ctx->ReadRegister(f1_info, f1_value);
+  f1_value.GetData(f1_data);
+  offset = 0;
+  return_value[1] = f1_data.GetU64();
 } else {
-  f1_data.Append(f0_data);
-  copy_from_extractor = _data;
+  return_value[1] = f0_data.GetU64();
+  reg_ctx->ReadRegister(f1_info, f1_value);
+  f1_value.GetData(f1_data);
+  offset = 0;
+  return_value[0] = f1_data.GetU64();
 }
-  } else
-copy_from_extractor = _data; // This is in f0, copy from
-// register to our result
-// structure
-} else
-  copy_from_extractor = _data; // This is in f2, copy from
+
+f0_data.SetData(return_value, field_byte_width,
+target_byte_order);
+  }
+  copy_from_extractor = _data; // This is in f0, copy from
   // register to our result
   // structure
+} else {
+  f2_value.GetData(f2_data);
+  // This is in f2, copy from register to our result structure
+  copy_from_extractor = _data;
+}
 
 //

[Lldb-commits] [PATCH] D24549: [LLDB][MIPS] Skip some test case which were causing LLDB to go into infinite loop

2016-10-11 Thread Nitesh Jain via lldb-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL283732: [LLDB][MIPS] Skip some test case which were causing 
LLDB to go into infinite… (authored by nitesh.jain).

Changed prior to commit:
  https://reviews.llvm.org/D24549?vs=71314=74204#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D24549

Files:
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/breakpoint_delay_breakpoint_one_signal/TestConcurrentBreakpointDelayBreakpointOneSignal.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/breakpoint_one_delay_breakpoint_threads/TestConcurrentBreakpointOneDelayBreakpointThreads.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/breakpoints_delayed_breakpoint_one_watchpoint/TestConcurrentBreakpointsDelayedBreakpointOneWatchpoint.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/crash_with_break/TestConcurrentCrashWithBreak.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/crash_with_signal/TestConcurrentCrashWithSignal.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/crash_with_watchpoint/TestConcurrentCrashWithWatchpoint.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/crash_with_watchpoint_breakpoint_signal/TestConcurrentCrashWithWatchpointBreakpointSignal.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/delay_signal_break/TestConcurrentDelaySignalBreak.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/delay_signal_watch/TestConcurrentDelaySignalWatch.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/delay_watch_break/TestConcurrentDelayWatchBreak.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/delayed_crash_with_breakpoint_signal/TestConcurrentDelayedCrashWithBreakpointSignal.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/delayed_crash_with_breakpoint_watchpoint/TestConcurrentDelayedCrashWithBreakpointWatchpoint.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/many_breakpoints/TestConcurrentManyBreakpoints.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/many_crash/TestConcurrentManyCrash.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/many_signals/TestConcurrentManySignals.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/many_watchpoints/TestConcurrentManyWatchpoints.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/n_watch_n_break/TestConcurrentNWatchNBreak.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/signal_break/TestConcurrentSignalBreak.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/signal_delay_break/TestConcurrentSignalDelayBreak.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/signal_delay_watch/TestConcurrentSignalDelayWatch.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/signal_n_watch_n_break/TestConcurrentSignalNWatchNBreak.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/signal_watch/TestConcurrentSignalWatch.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/signal_watch_break/TestConcurrentSignalWatchBreak.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/two_breakpoint_threads/TestConcurrentTwoBreakpointThreads.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/two_breakpoints_one_delay_signal/TestConcurrentTwoBreakpointsOneDelaySignal.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/two_breakpoints_one_signal/TestConcurrentTwoBreakpointsOneSignal.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/two_breakpoints_one_watchpoint/TestConcurrentTwoBreakpointsOneWatchpoint.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/two_watchpoint_threads/TestConcurrentTwoWatchpointThreads.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/two_watchpoints_one_breakpoint/TestConcurrentTwoWatchpointsOneBreakpoint.py
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/two_watchpoints_one_delay_breakpoint/TestConcurrentTwoWatchpointsOneDelayBreakpoint.py

[Lldb-commits] [PATCH] D24124: [LLDB][MIPS] Fix register read/write for 32 bit big endian system

2016-10-11 Thread Nitesh Jain via lldb-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL283728: [LLDB][MIPS] Fix register read/write for 32 bit big 
endian system (authored by nitesh.jain).

Changed prior to commit:
  https://reviews.llvm.org/D24124?vs=72024=74202#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D24124

Files:
  lldb/trunk/source/Core/RegisterValue.cpp
  lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp


Index: lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp
===
--- lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp
+++ lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp
@@ -169,7 +169,7 @@
 
   if (error.Success())
 // First cast to an unsigned of the same size to avoid sign extension.
-value.SetUInt64(static_cast(data));
+value.SetUInt(static_cast(data), size);
 
   if (log)
 log->Printf("NativeRegisterContextLinux::%s() reg %s: 0x%lx", __FUNCTION__,
Index: lldb/trunk/source/Core/RegisterValue.cpp
===
--- lldb/trunk/source/Core/RegisterValue.cpp
+++ lldb/trunk/source/Core/RegisterValue.cpp
@@ -633,8 +633,11 @@
 default:
   break;
 case 1:
+  return *(const uint8_t *)buffer.bytes;
 case 2:
+  return *(const uint16_t *)buffer.bytes;
 case 4:
+  return *(const uint32_t *)buffer.bytes;
 case 8:
   return *(const uint64_t *)buffer.bytes;
 }


Index: lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp
===
--- lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp
+++ lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp
@@ -169,7 +169,7 @@
 
   if (error.Success())
 // First cast to an unsigned of the same size to avoid sign extension.
-value.SetUInt64(static_cast(data));
+value.SetUInt(static_cast(data), size);
 
   if (log)
 log->Printf("NativeRegisterContextLinux::%s() reg %s: 0x%lx", __FUNCTION__,
Index: lldb/trunk/source/Core/RegisterValue.cpp
===
--- lldb/trunk/source/Core/RegisterValue.cpp
+++ lldb/trunk/source/Core/RegisterValue.cpp
@@ -633,8 +633,11 @@
 default:
   break;
 case 1:
+  return *(const uint8_t *)buffer.bytes;
 case 2:
+  return *(const uint16_t *)buffer.bytes;
 case 4:
+  return *(const uint32_t *)buffer.bytes;
 case 8:
   return *(const uint64_t *)buffer.bytes;
 }
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [PATCH] D24603: [LLDB][MIPS] fix Floating point register read/write for big endian

2016-10-10 Thread Nitesh Jain via lldb-commits

nitesh.jain added a comment.

Hi Greg,

The diff is update as per suggestion so should I commit this ?

Thanks


https://reviews.llvm.org/D24603



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] r283729 - [LLDB][MIPS] Fix TestReturnValue failure for MIPS

2016-10-10 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Mon Oct 10 04:16:20 2016
New Revision: 283729

URL: http://llvm.org/viewvc/llvm-project?rev=283729=rev
Log:
[LLDB][MIPS] Fix TestReturnValue failure for MIPS

Reviewers: clayborg, labath, bhushan

Subscribers: jaydeep, slthakur, llvm-commits

Differential Revision: https://reviews.llvm.org/D24498

Modified:
lldb/trunk/source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp

Modified: lldb/trunk/source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp?rev=283729=283728=283729=diff
==
--- lldb/trunk/source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp (original)
+++ lldb/trunk/source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp Mon Oct 10 
04:16:20 2016
@@ -923,23 +923,26 @@ ValueObjectSP ABISysV_mips64::GetReturnV
target->GetArchitecture().GetAddressByteSize());
 
   RegisterValue r2_value, r3_value, f0_value, f1_value, f2_value;
+  // Tracks how much bytes of r2 and r3 registers we've consumed so far
+  uint32_t integer_bytes = 0;
 
-  uint32_t integer_bytes = 0; // Tracks how much bytes of r2 and r3
-  // registers we've consumed so far
-  bool use_fp_regs = 0; // True if return values are in FP return 
registers.
-  bool found_non_fp_field =
-  0; // True if we found any non floating point field in structure.
-  bool use_r2 = 0; // True if return values are in r2 register.
-  bool use_r3 = 0; // True if return values are in r3 register.
-  bool sucess = 0; // True if the result is copied into our data buffer
+  // True if return values are in FP return registers.
+  bool use_fp_regs = 0;
+  // True if we found any non floating point field in structure.
+  bool found_non_fp_field = 0;
+  // True if return values are in r2 register.
+  bool use_r2 = 0;
+  // True if return values are in r3 register.
+  bool use_r3 = 0;
+  // True if the result is copied into our data buffer
+  bool sucess = 0;
   std::string name;
   bool is_complex;
   uint32_t count;
   const uint32_t num_children = return_compiler_type.GetNumFields();
 
   // A structure consisting of one or two FP values (and nothing else) will
-  // be
-  // returned in the two FP return-value registers i.e fp0 and fp2.
+  // be returned in the two FP return-value registers i.e fp0 and fp2.
   if (num_children <= 2) {
 uint64_t field_bit_offset = 0;
 
@@ -967,7 +970,6 @@ ValueObjectSP ABISysV_mips64::GetReturnV
   reg_ctx->ReadRegister(f2_info, f2_value);
 
   f0_value.GetData(f0_data);
-  f2_value.GetData(f2_data);
 
   for (uint32_t idx = 0; idx < num_children; idx++) {
 CompilerType field_compiler_type =
@@ -977,30 +979,40 @@ ValueObjectSP ABISysV_mips64::GetReturnV
 field_compiler_type.GetByteSize(nullptr);
 
 DataExtractor *copy_from_extractor = nullptr;
+uint64_t return_value[2];
+offset_t offset = 0;
 
 if (idx == 0) {
-  if (field_byte_width == 16) // This case is for long double type.
-  {
+  // This case is for long double type.
+  if (field_byte_width == 16) {
+
 // If structure contains long double type, then it is returned
 // in fp0/fp1 registers.
-reg_ctx->ReadRegister(f1_info, f1_value);
-f1_value.GetData(f1_data);
-
 if (target_byte_order == eByteOrderLittle) {
-  f0_data.Append(f1_data);
-  copy_from_extractor = _data;
+  return_value[0] = f0_data.GetU64();
+  reg_ctx->ReadRegister(f1_info, f1_value);
+  f1_value.GetData(f1_data);
+  offset = 0;
+  return_value[1] = f1_data.GetU64();
 } else {
-  f1_data.Append(f0_data);
-  copy_from_extractor = _data;
+  return_value[1] = f0_data.GetU64();
+  reg_ctx->ReadRegister(f1_info, f1_value);
+  f1_value.GetData(f1_data);
+  offset = 0;
+  return_value[0] = f1_data.GetU64();
 }
-  } else
-copy_from_extractor = _data; // This is in f0, copy from
-// register to our result
-// structure
-} else
-  copy_from_extractor = _data; // This is in f2, copy from
+
+f0_data.SetData(return_value, field_byte_width,
+target_byte_order);
+  }
+  copy_from_extractor = _data; // This is in f0, copy from

[Lldb-commits] [lldb] r283728 - [LLDB][MIPS] Fix register read/write for 32 bit big endian system

2016-10-10 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Mon Oct 10 04:02:41 2016
New Revision: 283728

URL: http://llvm.org/viewvc/llvm-project?rev=283728=rev
Log:
[LLDB][MIPS] Fix register read/write for 32 bit big endian system

Reviewers: clayborg, labath

Subscribers: jaydeep, bhushan, mohit.bhakkad, slthakur, llvm-commits

Differential Revision: https://reviews.llvm.org/D24124

Modified:
lldb/trunk/source/Core/RegisterValue.cpp
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp

Modified: lldb/trunk/source/Core/RegisterValue.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Core/RegisterValue.cpp?rev=283728=283727=283728=diff
==
--- lldb/trunk/source/Core/RegisterValue.cpp (original)
+++ lldb/trunk/source/Core/RegisterValue.cpp Mon Oct 10 04:02:41 2016
@@ -633,8 +633,11 @@ uint64_t RegisterValue::GetAsUInt64(uint
 default:
   break;
 case 1:
+  return *(const uint8_t *)buffer.bytes;
 case 2:
+  return *(const uint16_t *)buffer.bytes;
 case 4:
+  return *(const uint32_t *)buffer.bytes;
 case 8:
   return *(const uint64_t *)buffer.bytes;
 }

Modified: lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp?rev=283728=283727=283728=diff
==
--- lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp 
(original)
+++ lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp Mon 
Oct 10 04:02:41 2016
@@ -169,7 +169,7 @@ Error NativeRegisterContextLinux::DoRead
 
   if (error.Success())
 // First cast to an unsigned of the same size to avoid sign extension.
-value.SetUInt64(static_cast(data));
+value.SetUInt(static_cast(data), size);
 
   if (log)
 log->Printf("NativeRegisterContextLinux::%s() reg %s: 0x%lx", __FUNCTION__,


___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [PATCH] D24603: [LLDB][MIPS] fix Floating point register read/write for big endian

2016-10-03 Thread Nitesh Jain via lldb-commits

nitesh.jain updated this revision to Diff 73278.
nitesh.jain added a comment.

These diff remove manually bit twiddling due to the size of the floating point 
register that can change. We use register offset to get floating point register 
data based on endianess and it's size. We have not remove bit twiddling for MSA 
register since it's need to be tested( require support in ptrace).

Thanks


https://reviews.llvm.org/D24603

Files:
  source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
  source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.h
  source/Plugins/Process/Utility/RegisterInfos_mips.h
  source/Plugins/Process/Utility/RegisterInfos_mips64.h
  source/Plugins/Process/Utility/lldb-mips-linux-register-enums.h

Index: source/Plugins/Process/Utility/lldb-mips-linux-register-enums.h
===
--- source/Plugins/Process/Utility/lldb-mips-linux-register-enums.h
+++ source/Plugins/Process/Utility/lldb-mips-linux-register-enums.h
@@ -282,6 +282,84 @@
 k_num_fpr_registers_mips64 +
 k_num_msa_registers_mips64
 };
+
+// Register no. for RegisterKind = eRegisterKindProcessPlugin
+// The ptrace request PTRACE_PEEKUSER/PTRACE_POKEUSER used this number
+enum {
+  ptrace_zero_mips, 
+  ptrace_r1_mips,
+  ptrace_r2_mips,
+  ptrace_r3_mips,
+  ptrace_r4_mips,
+  ptrace_r5_mips,
+  ptrace_r6_mips,
+  ptrace_r7_mips,
+  ptrace_r8_mips,
+  ptrace_r9_mips,
+  ptrace_r10_mips,
+  ptrace_r11_mips,
+  ptrace_r12_mips,
+  ptrace_r13_mips,
+  ptrace_r14_mips,
+  ptrace_r15_mips,
+  ptrace_r16_mips,
+  ptrace_r17_mips,
+  ptrace_r18_mips,
+  ptrace_r19_mips,
+  ptrace_r20_mips,
+  ptrace_r21_mips,
+  ptrace_r22_mips,
+  ptrace_r23_mips,
+  ptrace_r24_mips,
+  ptrace_r25_mips,
+  ptrace_r26_mips,
+  ptrace_r27_mips,
+  ptrace_gp_mips,
+  ptrace_sp_mips,
+  ptrace_r30_mips,
+  ptrace_ra_mips,
+  ptrace_f0_mips,
+  ptrace_f1_mips,
+  ptrace_f2_mips,
+  ptrace_f3_mips,
+  ptrace_f4_mips,
+  ptrace_f5_mips,
+  ptrace_f6_mips,
+  ptrace_f7_mips,
+  ptrace_f8_mips,
+  ptrace_f9_mips,
+  ptrace_f10_mips,
+  ptrace_f11_mips,
+  ptrace_f12_mips,
+  ptrace_f13_mips,
+  ptrace_f14_mips,
+  ptrace_f15_mips,
+  ptrace_f16_mips,
+  ptrace_f17_mips,
+  ptrace_f18_mips,
+  ptrace_f19_mips,
+  ptrace_f20_mips,
+  ptrace_f21_mips,
+  ptrace_f22_mips,
+  ptrace_f23_mips,
+  ptrace_f24_mips,
+  ptrace_f25_mips,
+  ptrace_f26_mips,
+  ptrace_f27_mips,
+  ptrace_f28_mips,
+  ptrace_f29_mips,
+  ptrace_f30_mips,
+  ptrace_f31_mips,
+  ptrace_pc_mips,
+  ptrace_cause_mips,
+  ptrace_badvaddr_mips,
+  ptrace_mulhi_mips,
+  ptrace_mullo_mips,
+  ptrace_fcsr_mips,
+  ptrace_fir_mips,
+  ptrace_sr_mips,
+  ptrace_config5_mips
+};
 }
 
 #endif // #ifndef lldb_mips_linux_register_enums_h
Index: source/Plugins/Process/Utility/RegisterInfos_mips64.h
===
--- source/Plugins/Process/Utility/RegisterInfos_mips64.h
+++ source/Plugins/Process/Utility/RegisterInfos_mips64.h
@@ -42,11 +42,11 @@
 
 // Note that the size and offset will be updated by platform-specific classes.
 #ifdef LINUX_MIPS64
-#define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4)   \
+#define DEFINE_GPR(reg, alt, kind1, kind2, kind3)  \
   {\
 #reg, alt, sizeof(((GPR_linux_mips *) 0)->reg),\
   GPR_OFFSET(reg), eEncodingUint, eFormatHex,  \
- {kind1, kind2, kind3, kind4,  \
+ {kind1, kind2, kind3, ptrace_##reg##_mips,\
   gpr_##reg##_mips64 },\
   NULL, NULL, NULL, 0  \
   }
@@ -61,11 +61,11 @@
   }
 #endif
 
-#define DEFINE_GPR_INFO(reg, alt, kind1, kind2, kind3, kind4)  \
+#define DEFINE_GPR_INFO(reg, alt, kind1, kind2, kind3) \
   {\
 #reg, alt, sizeof(((GPR_linux_mips *) 0)->reg) / 2,\
   GPR_OFFSET(reg), eEncodingUint, eFormatHex,  \
- {kind1, kind2, kind3, kind4,  \
+ {kind1, kind2, kind3, ptrace_##reg##_mips,\
   gpr_##reg##_mips64 },\
   NULL, NULL, NULL, 0  \
   }
@@ -75,21 +75,21 @@
 llvm::dwarf::DW_OP_lit26, llvm::dwarf::DW_OP_shl, llvm::dwarf::DW_OP_and,
 llvm::dwarf::DW_OP_lit26, llvm::dwarf::DW_OP_shr};
 
-#define DEFINE_FPR(reg, alt, kind1, kind2, kind3, kind4)   \
+#define DEFINE_FPR(reg, alt, kind1,

[Lldb-commits] [PATCH] [Updated, 58 lines] D25021: [LLDB][MIPS] Fix qProcessInfo to return correct pointer size based on ELF ABI

2016-09-30 Thread Nitesh Jain via lldb-commits

nitesh.jain removed rL LLVM as the repository for this revision.
nitesh.jain updated this revision to Diff 73029.
nitesh.jain added a comment.

We just require ABI information so that auxv vector is parse when lldb try to 
attach a process via "attach -p pid"


https://reviews.llvm.org/D25021

Files:
  include/lldb/Core/ArchSpec.h
  source/Core/ArchSpec.cpp
  source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
  source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.cpp

Index: source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.cpp
===
--- source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.cpp
+++ source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.cpp
@@ -1212,13 +1212,12 @@
   // Nothing.
   break;
 }
-
-if (proc_triple.isArch64Bit())
-  response.PutCString("ptrsize:8;");
-else if (proc_triple.isArch32Bit())
-  response.PutCString("ptrsize:4;");
-else if (proc_triple.isArch16Bit())
-  response.PutCString("ptrsize:2;");
+// In case of MIPS64, pointer size is depend on ELF ABI
+// For N32 the pointer size is 4 and for N64 it is 8
+std::string abi = proc_arch.GetTargetABI();
+if (!abi.empty())
+  response.Printf("elf_abi:%s;",abi.c_str());
+response.Printf("ptrsize:%d;", proc_arch.GetAddressByteSize()); 
   }
 }
 
Index: source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
===
--- source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
+++ source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
@@ -1847,6 +1847,7 @@
   std::string os_name;
   std::string vendor_name;
   std::string triple;
+  std::string elf_abi;
   uint32_t pointer_byte_size = 0;
   StringExtractor extractor;
   ByteOrder byte_order = eByteOrderInvalid;
@@ -1883,6 +1884,9 @@
 } else if (name.equals("pid")) {
   if (!value.getAsInteger(16, pid))
 ++num_keys_decoded;
+} else if (name.equals("elf_abi")) {
+elf_abi = value;
+++num_keys_decoded;
 }
   }
   if (num_keys_decoded > 0)
@@ -1895,6 +1899,7 @@
   // Set the ArchSpec from the triple if we have it.
   if (!triple.empty()) {
 m_process_arch.SetTriple(triple.c_str());
+m_process_arch.SetFlags(elf_abi);
 if (pointer_byte_size) {
   assert(pointer_byte_size == m_process_arch.GetAddressByteSize());
 }
Index: source/Core/ArchSpec.cpp
===
--- source/Core/ArchSpec.cpp
+++ source/Core/ArchSpec.cpp
@@ -627,6 +627,42 @@
   return false;
 }
 
+std::string ArchSpec::GetTargetABI() const {
+
+  std::string abi;
+
+  if (IsMIPS()) {
+switch (GetFlags() & ArchSpec::eMIPSABI_mask) {
+case ArchSpec::eMIPSABI_N64:
+  abi = "n64";
+  return abi;
+case ArchSpec::eMIPSABI_N32:
+  abi = "n32";
+  return abi;
+case ArchSpec::eMIPSABI_O32:
+  abi = "o32";
+  return abi;
+default:
+  return abi;
+}
+  }
+  return abi;
+}
+
+void ArchSpec::SetFlags(std::string elf_abi) {
+
+  uint32_t flag = GetFlags();
+  if (IsMIPS()) {
+if (elf_abi == "n64")
+  flag |= ArchSpec::eMIPSABI_N64;
+else if (elf_abi == "n32")
+  flag |= ArchSpec::eMIPSABI_N32;
+else if (elf_abi == "o32")
+  flag |= ArchSpec::eMIPSABI_O32;
+  }
+  SetFlags(flag);
+}
+
 std::string ArchSpec::GetClangTargetCPU() {
   std::string cpu;
   const llvm::Triple::ArchType machine = GetMachine();
Index: include/lldb/Core/ArchSpec.h
===
--- include/lldb/Core/ArchSpec.h
+++ include/lldb/Core/ArchSpec.h
@@ -307,6 +307,8 @@
   //--
   std::string GetClangTargetCPU();
 
+  std::string GetTargetABI() const;
+
   //--
   /// Clears the object state.
   ///
@@ -592,6 +594,8 @@
 
   void SetFlags(uint32_t flags) { m_flags = flags; }
 
+  void SetFlags(std::string elf_abi);
+
 protected:
   bool IsEqualTo(const ArchSpec , bool exact_match) const;
 
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D25021: [LLDB][MIPS] Fix qProcessInfo to return correct pointer size based on ELF ABI

2016-09-29 Thread Nitesh Jain via lldb-commits

nitesh.jain added inline comments.


Comment at: 
source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.cpp:1218
@@ +1217,3 @@
+response.Printf("eflags:%" PRIx32 ";", proc_arch.GetFlags());
+if (proc_triple.isArch64Bit()) {
+   if (proc_arch.IsMIPS()) {

clayborg wrote:
> labath wrote:
> > Why do we have the compilcated switch here. Can't we replace that with:
> > `response.Printf("ptrsize:%d;", proc_arch.GetAddressByteSize());` for all 
> > sizes?
> labath: the default ptr size for MIPS64 is 8. We would need to modify 
> ArchSpec.cpp to look at the flags for MIPS64 and change the pointer size to 4 
> if the N32 is being used. 
Greg:  ArchSpec::GetAddressByteSize() will always return pointer size based on 
abi. So for N64 (default for MIPS64) abi it will return pointer size as 8
labath: We can replace switch with ArchSpec::GetAddressByteSize().



Repository:
  rL LLVM

https://reviews.llvm.org/D25021



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [PATCH] D25021: [LLDB][MIPS] Fix qProcessInfo to return correct pointer size based on ELF ABI

2016-09-28 Thread Nitesh Jain via lldb-commits

nitesh.jain created this revision.
nitesh.jain added reviewers: clayborg, labath.
nitesh.jain added subscribers: jaydeep, bhushan, slthakur, lldb-commits.
nitesh.jain set the repository for this revision to rL LLVM.

In case of MIPS64, the pointer size depends on ELF abi. The MIPS64 currently 
support following abi's

1) N32 : - The pointer size is 4 byte
2) N64 :- The pointer size is 8 byte

This patch add one more key (eflags) in qProcessInfo which will be use to get 
correct pointer size based on abi.

Repository:
  rL LLVM

https://reviews.llvm.org/D25021

Files:
  source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
  source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.cpp

Index: source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.cpp
===
--- source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.cpp
+++ source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.cpp
@@ -1212,9 +1212,15 @@
   // Nothing.
   break;
 }
-
-if (proc_triple.isArch64Bit())
-  response.PutCString("ptrsize:8;");
+// In case of MIPS64, pointer size is depend on ELF ABI
+// For N32 the pointer size is 4 and for N64 it is 8 
+response.Printf("eflags:%" PRIx32 ";", proc_arch.GetFlags());
+if (proc_triple.isArch64Bit()) {
+   if (proc_arch.IsMIPS()) {
+ response.Printf("ptrsize:%d;", proc_arch.GetAddressByteSize()); 
+   } else
+ response.PutCString("ptrsize:8;");
+}
 else if (proc_triple.isArch32Bit())
   response.PutCString("ptrsize:4;");
 else if (proc_triple.isArch16Bit())
Index: source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
===
--- source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
+++ source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
@@ -1847,6 +1847,7 @@
   std::string os_name;
   std::string vendor_name;
   std::string triple;
+  uint32_t proc_arch_eflags = 0;
   uint32_t pointer_byte_size = 0;
   StringExtractor extractor;
   ByteOrder byte_order = eByteOrderInvalid;
@@ -1883,6 +1884,9 @@
 } else if (name.equals("pid")) {
   if (!value.getAsInteger(16, pid))
 ++num_keys_decoded;
+} else if (name.equals("eflags")) {
+  if (!value.getAsInteger(16,proc_arch_eflags))
+++num_keys_decoded;
 }
   }
   if (num_keys_decoded > 0)
@@ -1895,6 +1899,7 @@
   // Set the ArchSpec from the triple if we have it.
   if (!triple.empty()) {
 m_process_arch.SetTriple(triple.c_str());
+m_process_arch.SetFlags(proc_arch_eflags);
 if (pointer_byte_size) {
   assert(pointer_byte_size == m_process_arch.GetAddressByteSize());
 }


Index: source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.cpp
===
--- source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.cpp
+++ source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerCommon.cpp
@@ -1212,9 +1212,15 @@
   // Nothing.
   break;
 }
-
-if (proc_triple.isArch64Bit())
-  response.PutCString("ptrsize:8;");
+// In case of MIPS64, pointer size is depend on ELF ABI
+// For N32 the pointer size is 4 and for N64 it is 8 
+response.Printf("eflags:%" PRIx32 ";", proc_arch.GetFlags());
+if (proc_triple.isArch64Bit()) {
+   if (proc_arch.IsMIPS()) {
+ response.Printf("ptrsize:%d;", proc_arch.GetAddressByteSize()); 
+   } else
+ response.PutCString("ptrsize:8;");
+}
 else if (proc_triple.isArch32Bit())
   response.PutCString("ptrsize:4;");
 else if (proc_triple.isArch16Bit())
Index: source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
===
--- source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
+++ source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
@@ -1847,6 +1847,7 @@
   std::string os_name;
   std::string vendor_name;
   std::string triple;
+  uint32_t proc_arch_eflags = 0;
   uint32_t pointer_byte_size = 0;
   StringExtractor extractor;
   ByteOrder byte_order = eByteOrderInvalid;
@@ -1883,6 +1884,9 @@
 } else if (name.equals("pid")) {
   if (!value.getAsInteger(16, pid))
 ++num_keys_decoded;
+} else if (name.equals("eflags")) {
+  if (!value.getAsInteger(16,proc_arch_eflags))
+++num_keys_decoded;
 }
   }
   if (num_keys_decoded > 0)
@@ -1895,6 +1899,7 @@
   // Set the ArchSpec from the triple if we have it.
   if (!triple.empty()) {
 m_process_arch.SetTriple(triple.c_str());
+m_process_arch.SetFlags(proc_arch_eflags);
 if

Re: [Lldb-commits] [PATCH] D24603: [LLDB][MIPS] fix Floating point register read/write for big endian

2016-09-27 Thread Nitesh Jain via lldb-commits

nitesh.jain added a comment.

In https://reviews.llvm.org/D24603#548902, @clayborg wrote:

> So it seems like this can be fixed by doing a few things:
>  1 - just set the RegisterInfo.offset to the actual offset in the buffer and 
> don't use the offset as the ptrace key used to grab the register
>  2 - modify the RegisterInfo.kinds[eRegisterKindProcessPlugin] to be the 
> offset to you to use for ptrace
>
> There should be no need what so ever to do manual bit twiddling with src and 
> dst.

The floating point register size can be dynamically changes . Hence following 
cases are possible when we read registers from ptrace in FPR_linux_mips buffer 
(In case of MIPS, ptrace always return value in 64 bit container irrespective 
of Arch).

1. Floating point register size is 32 (SR.FR = 0).

  a) In case of big endian system, the FPR_linux_mips.f0 will contains two 
floating point registers . The  $f0 register will be store in upper 32 bit and  
$f1 register in lower 32 bit of FPR_linux_mips.f0. The FPR_linux_mips.f1 will 
contain don't care value and similarly for all other registers. Thus each even 
buffer will contain valid value and represent two registers.

  b) In case of liitle endian , the  $f0 will be store in lower 32 bit and $f1 
in upper 32bit of  FPR_linux_mips.f0. The FPR_linux_mips.f1 will contain don't 
care value and similarly for all other registers.

2. Floating point register size is 64 (SR.FR = 1). In these case all buffer 
will have valid value.

Hence we need bit twiddling with src and dst  (in case of SR.FR = 0) so that 
each buffer will represent value for single register.

https://reviews.llvm.org/D24603

___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D24603: [LLDB][MIPS] fix Floating point register read/write for big endian

2016-09-27 Thread Nitesh Jain via lldb-commits

nitesh.jain updated this revision to Diff 72618.
nitesh.jain added a comment.
Herald added a subscriber: ki.stfu.

Updated patch as per suggestion.


https://reviews.llvm.org/D24603

Files:
  source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
  source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.h
  source/Plugins/Process/Utility/RegisterInfos_mips.h
  source/Plugins/Process/Utility/RegisterInfos_mips64.h
  source/Plugins/Process/Utility/lldb-mips-linux-register-enums.h

Index: source/Plugins/Process/Utility/lldb-mips-linux-register-enums.h
===
--- source/Plugins/Process/Utility/lldb-mips-linux-register-enums.h
+++ source/Plugins/Process/Utility/lldb-mips-linux-register-enums.h
@@ -282,6 +282,84 @@
 k_num_fpr_registers_mips64 +
 k_num_msa_registers_mips64
 };
+
+// Register no. for RegisterKind = eRegisterKindProcessPlugin
+// The ptrace request PTRACE_PEEKUSER/PTRACE_POKEUSER used this number
+enum {
+  ptrace_zero_mips, 
+  ptrace_r1_mips,
+  ptrace_r2_mips,
+  ptrace_r3_mips,
+  ptrace_r4_mips,
+  ptrace_r5_mips,
+  ptrace_r6_mips,
+  ptrace_r7_mips,
+  ptrace_r8_mips,
+  ptrace_r9_mips,
+  ptrace_r10_mips,
+  ptrace_r11_mips,
+  ptrace_r12_mips,
+  ptrace_r13_mips,
+  ptrace_r14_mips,
+  ptrace_r15_mips,
+  ptrace_r16_mips,
+  ptrace_r17_mips,
+  ptrace_r18_mips,
+  ptrace_r19_mips,
+  ptrace_r20_mips,
+  ptrace_r21_mips,
+  ptrace_r22_mips,
+  ptrace_r23_mips,
+  ptrace_r24_mips,
+  ptrace_r25_mips,
+  ptrace_r26_mips,
+  ptrace_r27_mips,
+  ptrace_gp_mips,
+  ptrace_sp_mips,
+  ptrace_r30_mips,
+  ptrace_ra_mips,
+  ptrace_f0_mips,
+  ptrace_f1_mips,
+  ptrace_f2_mips,
+  ptrace_f3_mips,
+  ptrace_f4_mips,
+  ptrace_f5_mips,
+  ptrace_f6_mips,
+  ptrace_f7_mips,
+  ptrace_f8_mips,
+  ptrace_f9_mips,
+  ptrace_f10_mips,
+  ptrace_f11_mips,
+  ptrace_f12_mips,
+  ptrace_f13_mips,
+  ptrace_f14_mips,
+  ptrace_f15_mips,
+  ptrace_f16_mips,
+  ptrace_f17_mips,
+  ptrace_f18_mips,
+  ptrace_f19_mips,
+  ptrace_f20_mips,
+  ptrace_f21_mips,
+  ptrace_f22_mips,
+  ptrace_f23_mips,
+  ptrace_f24_mips,
+  ptrace_f25_mips,
+  ptrace_f26_mips,
+  ptrace_f27_mips,
+  ptrace_f28_mips,
+  ptrace_f29_mips,
+  ptrace_f30_mips,
+  ptrace_f31_mips,
+  ptrace_pc_mips,
+  ptrace_cause_mips,
+  ptrace_badvaddr_mips,
+  ptrace_mulhi_mips,
+  ptrace_mullo_mips,
+  ptrace_fcsr_mips,
+  ptrace_fir_mips,
+  ptrace_sr_mips,
+  ptrace_config5_mips
+};
 }
 
 #endif // #ifndef lldb_mips_linux_register_enums_h
Index: source/Plugins/Process/Utility/RegisterInfos_mips64.h
===
--- source/Plugins/Process/Utility/RegisterInfos_mips64.h
+++ source/Plugins/Process/Utility/RegisterInfos_mips64.h
@@ -42,11 +42,11 @@
 
 // Note that the size and offset will be updated by platform-specific classes.
 #ifdef LINUX_MIPS64
-#define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4)   \
+#define DEFINE_GPR(reg, alt, kind1, kind2, kind3)  \
   {\
 #reg, alt, sizeof(((GPR_linux_mips *) 0)->reg),\
   GPR_OFFSET(reg), eEncodingUint, eFormatHex,  \
- {kind1, kind2, kind3, kind4,  \
+ {kind1, kind2, kind3, ptrace_##reg##_mips,\
   gpr_##reg##_mips64 },\
   NULL, NULL, NULL, 0  \
   }
@@ -61,11 +61,11 @@
   }
 #endif
 
-#define DEFINE_GPR_INFO(reg, alt, kind1, kind2, kind3, kind4)  \
+#define DEFINE_GPR_INFO(reg, alt, kind1, kind2, kind3) \
   {\
 #reg, alt, sizeof(((GPR_linux_mips *) 0)->reg) / 2,\
   GPR_OFFSET(reg), eEncodingUint, eFormatHex,  \
- {kind1, kind2, kind3, kind4,  \
+ {kind1, kind2, kind3, ptrace_##reg##_mips,\
   gpr_##reg##_mips64 },\
   NULL, NULL, NULL, 0  \
   }
@@ -75,21 +75,21 @@
 llvm::dwarf::DW_OP_lit26, llvm::dwarf::DW_OP_shl, llvm::dwarf::DW_OP_and,
 llvm::dwarf::DW_OP_lit26, llvm::dwarf::DW_OP_shr};
 
-#define DEFINE_FPR(reg, alt, kind1, kind2, kind3, kind4)   \
+#define DEFINE_FPR(reg, alt, kind1, kind2, kind3)  \
   {\
 #reg, alt, sizeof(((FPR_linux_mips *) 0)->reg),\
   FPR_OFFSET(reg),

Re: [Lldb-commits] [PATCH] D24124: [LLDB][MIPS] Fix register read/write for 32 bit big endian system

2016-09-21 Thread Nitesh Jain via lldb-commits

nitesh.jain added a comment.

In https://reviews.llvm.org/D24124#543823, @clayborg wrote:

> A few things about a the RegisterContext class in case it would change and 
> thing that you are submitting here. The entire register context defines a 
> buffer of bytes that can contain all register values. Each RegisterInfo 
> contains the offset for the value of this register in this buffer. This 
> buffer is said to have a specific byte order (big, little, etc). When a 
> register is read, it should place its bytes into the RegisterContext's buffer 
> of bytes and mark itself as being valid in the register context. Some 
> platforms read multiple registers at a time (they don't have a "read one 
> register value", they just have "read all GPR registers") and lets say you 
> are reading one GPR, and this causes all GPR values to be read, then all 
> bytes from all GPR values will be copied into the register context data 
> buffer and all GPRs should be marked as valid. So to get a RegisterValue for 
> a 32 bit register, we normally will just ask the RegisterInfo for the offset 
> of the register, and then extract the bytes from the buffer using a 
> DataExtractor object. If you have a 64 bit register whose value also contains 
> a 32 bit pseudo register (like rax contains eax on x86), then you should have 
> a RegisterInfo defined for "rax" that says its offset is N, and for a big 
> endian system, you would say that the register offset for "eax" is N + 4. 
> Extracting the value simply becomes extracting the bytes from the buffer 
> without the need for any tricks. After reading all of this, do you still 
> believe you have the right fix in here? It doesn't seem like you ever should 
> need to use DataExtractor::CopyByteOrderedData???


The issue was in RegisterValue::GetUInt64 function returning incorrect value 
for register of size 4/2/1 byte on 32 bit big endian system. We have modify it 
to return value based on register size which will fix the register read/write 
problem on 32 bit big endian system.


https://reviews.llvm.org/D24124



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D24124: [LLDB][MIPS] Fix register read/write for 32 bit big endian system

2016-09-21 Thread Nitesh Jain via lldb-commits

nitesh.jain updated the summary for this revision.
nitesh.jain updated this revision to Diff 72024.

https://reviews.llvm.org/D24124

Files:
  source/Core/RegisterValue.cpp
  source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp

Index: source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp
===
--- source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp
+++ source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp
@@ -169,7 +169,7 @@
 
   if (error.Success())
 // First cast to an unsigned of the same size to avoid sign extension.
-value.SetUInt64(static_cast(data));
+value.SetUInt(static_cast(data), size);
 
   if (log)
 log->Printf("NativeRegisterContextLinux::%s() reg %s: 0x%lx", __FUNCTION__,
Index: source/Core/RegisterValue.cpp
===
--- source/Core/RegisterValue.cpp
+++ source/Core/RegisterValue.cpp
@@ -633,8 +633,11 @@
 default:
   break;
 case 1:
+  return *(const uint8_t *)buffer.bytes;
 case 2:
+  return *(const uint16_t *)buffer.bytes;
 case 4:
+  return *(const uint32_t *)buffer.bytes;
 case 8:
   return *(const uint64_t *)buffer.bytes;
 }


Index: source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp
===
--- source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp
+++ source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp
@@ -169,7 +169,7 @@
 
   if (error.Success())
 // First cast to an unsigned of the same size to avoid sign extension.
-value.SetUInt64(static_cast(data));
+value.SetUInt(static_cast(data), size);
 
   if (log)
 log->Printf("NativeRegisterContextLinux::%s() reg %s: 0x%lx", __FUNCTION__,
Index: source/Core/RegisterValue.cpp
===
--- source/Core/RegisterValue.cpp
+++ source/Core/RegisterValue.cpp
@@ -633,8 +633,11 @@
 default:
   break;
 case 1:
+  return *(const uint8_t *)buffer.bytes;
 case 2:
+  return *(const uint16_t *)buffer.bytes;
 case 4:
+  return *(const uint32_t *)buffer.bytes;
 case 8:
   return *(const uint64_t *)buffer.bytes;
 }
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D24603: [LLDB][MIPS] fix Floating point register read/write for big endian

2016-09-15 Thread Nitesh Jain via lldb-commits

nitesh.jain marked an inline comment as done.
nitesh.jain added a comment.

https://reviews.llvm.org/D24603



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D24603: [LLDB][MIPS] fix Floating point register read/write for big endian

2016-09-15 Thread Nitesh Jain via lldb-commits

nitesh.jain updated this revision to Diff 71505.
nitesh.jain added a comment.

Updated diff as per suggestion.


https://reviews.llvm.org/D24603

Files:
  source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
  source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.h

Index: source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.h
===
--- source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.h
+++ source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.h
@@ -76,11 +76,16 @@
   static bool IsMSAAvailable();
 
 protected:
-  Error DoReadRegisterValue(uint32_t offset, const char *reg_name,
-uint32_t size, RegisterValue ) override;
+  Error Read_SR_Config(uint32_t offset, const char *reg_name, uint32_t size,
+   RegisterValue );
 
-  Error DoWriteRegisterValue(uint32_t offset, const char *reg_name,
- const RegisterValue ) override;
+  uint32_t GetPtraceOffset(uint32_t reg_index,
+   const RegisterInfo *const reg_info);
+
+  Error ReadRegisterRaw(uint32_t reg_index, RegisterValue ) override;
+
+  Error WriteRegisterRaw(uint32_t reg_index,
+ const RegisterValue ) override;
 
   Error DoReadWatchPointRegisterValue(lldb::tid_t tid, void *watch_readback);
 
Index: source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
===
--- source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
+++ source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
@@ -28,9 +28,16 @@
 #include "lldb/Host/HostInfo.h"
 #include "lldb/lldb-enumerations.h"
 #include "lldb/lldb-private-enumerations.h"
+
 #define NT_MIPS_MSA 0x600
 #define CONFIG5_FRE (1 << 8)
 #define SR_FR (1 << 26)
+#define FPR_BASE 32
+#define PC 64
+#define CAUSE 65
+#define BADVADDR 66
+#define MMHI 67
+#define MMLO 68
 #define NUM_REGISTERS 32
 
 #include 
@@ -466,21 +473,23 @@
   }
 
   if (IsFPR(reg_index) || IsMSA(reg_index)) {
-uint8_t *dst;
-uint64_t *src;
+uint8_t *dst = nullptr;
+uint64_t *src = nullptr;
+uint8_t byte_size = reg_info->byte_size;
 
 // Initialise the FP and MSA buffers by reading all co-processor 1 registers
 ReadCP1();
 
 if (IsFPR(reg_index)) {
   assert(reg_info->byte_offset < sizeof(UserArea));
   dst = (uint8_t *)_fpr + reg_info->byte_offset - (sizeof(m_gpr));
+  byte_size = IsFR0() ? 4 : 8;
 } else {
   assert(reg_info->byte_offset < sizeof(UserArea));
   dst = (uint8_t *)_msa + reg_info->byte_offset -
 (sizeof(m_gpr) + sizeof(m_fpr));
 }
-switch (reg_info->byte_size) {
+switch (byte_size) {
 case 4:
   *(uint32_t *)dst = reg_value.GetAsUInt32();
   break;
@@ -611,11 +620,12 @@
 Error NativeRegisterContextLinux_mips64::ReadCP1() {
   Error error;
 
-  uint8_t *src, *dst;
+  uint8_t *src = nullptr;
+  uint8_t *dst = nullptr;
 
   lldb::ByteOrder byte_order = GetByteOrder();
 
-  uint32_t IsBigEndian = (byte_order == lldb::eByteOrderBig);
+  bool IsBigEndian = (byte_order == lldb::eByteOrderBig);
 
   if (IsMSAAvailable()) {
 error = NativeRegisterContextLinux::ReadRegisterSet(
@@ -637,11 +647,18 @@
 
   // TODO: Add support for FRE
   if (IsFR0()) {
-src = (uint8_t *)_fpr + 4 + (IsBigEndian * 4);
-dst = (uint8_t *)_fpr + 8 + (IsBigEndian * 4);
+src = (uint8_t *)_fpr + (!IsBigEndian) * 4;
+dst = (uint8_t *)_fpr + 8;
 for (int i = 0; i < (NUM_REGISTERS / 2); i++) {
   // copy odd single from top of neighbouring even double
+  // In case of little endian, 32 bit LSB store even FP register
+  // and 32 bit MSB store odd FP register
+  // vice-versa for big-endian
   *(uint32_t *)dst = *(uint32_t *)src;
+
+  if (IsBigEndian)
+// Copy 32 bit MSB to 32 bit LSB
+*(uint32_t *)src = *(uint32_t *)(src + 4);
   src = src + 16;
   dst = dst + 16;
 }
@@ -653,18 +670,23 @@
 Error NativeRegisterContextLinux_mips64::WriteCP1() {
   Error error;
 
-  uint8_t *src, *dst;
+  uint8_t *src = nullptr;
+  uint8_t *dst = nullptr;
 
   lldb::ByteOrder byte_order = GetByteOrder();
 
-  uint32_t IsBigEndian = (byte_order == lldb::eByteOrderBig);
+  bool IsBigEndian = (byte_order == lldb::eByteOrderBig);
 
   // TODO: Add support for FRE
   if (IsFR0()) {
-src = (uint8_t *)_fpr + 8 + (IsBigEndian * 4);
-dst = (uint8_t *)_fpr + 4 + (IsBigEndian * 4);
+dst = (uint8_t *)_fpr + (!IsBigEndian) * 4;
+src = dst + 8 - (!IsBigEndian) * 4;
 for (int i = 0; i < (NUM_REGISTERS / 2); i++) {
   // copy odd single to top of neighbouring even double
+  if (IsBigEndian)
+// Copy 32 bit LSB to 32 bit MSB
+*(uint32_t *)(dst + 4) = *(uint32_t *)dst;
+
   *(uint32_t *)dst = *(uint32_t *)src;
   src = src + 16;
   dst = dst + 16;
@@ -1132,50 +1154,90

Re: [Lldb-commits] [PATCH] D24603: [LLDB][MIPS] fix Floating point register read/write for big endian

2016-09-15 Thread Nitesh Jain via lldb-commits

nitesh.jain added inline comments.


Comment at: 
source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp:1183
@@ +1182,3 @@
+  case dwarf_config5_mips64:
+return reg_info->byte_offset;
+  case dwarf_cause_mips:

labath wrote:
> Why do we need to do this remapping? Couldn't we structure the register infos 
> in a way that reg_info->byte_offset is exactly the offset that ptrace expects?
> 
> Or are you saying that ptrace does not accept register offsets, but some 
> random register numbers instead? (I cannot tell, as the comment above is 
> confusing.)
In case of MIPS, ptrace request PTRACE_PEEKUSER/PTRACE_POKEUSER accept register 
number as an offset.  We used reg_info->byte_offset to find register value in 
the struct GPR_linux_mips. The struct GPR_linux_mips  is same for 32 and 64 bit 
since ptrace always return 64 bit value irrespective of Arch (32 and 64) . 
Hence we can't modify reg_info->byte_offset to match exactly the offset that 
ptrace expects.


https://reviews.llvm.org/D24603



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [PATCH] D24603: [LLDB][MIPS] fix Floating point register read/write for big endian

2016-09-15 Thread Nitesh Jain via lldb-commits

nitesh.jain created this revision.
nitesh.jain added reviewers: clayborg, labath, jaydeep.
nitesh.jain added subscribers: bhushan, slthakur, lldb-commits.
Herald added a subscriber: sdardis.

This patch add fix for reading and writing floating point register based on 
SR.FR bit. 

https://reviews.llvm.org/D24603

Files:
  source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
  source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.h

Index: source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.h
===
--- source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.h
+++ source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.h
@@ -76,11 +76,16 @@
   static bool IsMSAAvailable();
 
 protected:
-  Error DoReadRegisterValue(uint32_t offset, const char *reg_name,
-uint32_t size, RegisterValue ) override;
+  Error Read_SR_Config(uint32_t offset, const char *reg_name, uint32_t size,
+   RegisterValue );
 
-  Error DoWriteRegisterValue(uint32_t offset, const char *reg_name,
- const RegisterValue ) override;
+  uint32_t GetPtraceOffset(uint32_t reg_index,
+   const RegisterInfo *const reg_info);
+
+  Error ReadRegisterRaw(uint32_t reg_index, RegisterValue ) override;
+
+  Error WriteRegisterRaw(uint32_t reg_index,
+ const RegisterValue ) override;
 
   Error DoReadWatchPointRegisterValue(lldb::tid_t tid, void *watch_readback);
 
Index: source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
===
--- source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
+++ source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
@@ -28,9 +28,16 @@
 #include "lldb/Host/HostInfo.h"
 #include "lldb/lldb-enumerations.h"
 #include "lldb/lldb-private-enumerations.h"
+
 #define NT_MIPS_MSA 0x600
 #define CONFIG5_FRE (1 << 8)
 #define SR_FR (1 << 26)
+#define FPR_BASE 32
+#define PC 64
+#define CAUSE 65
+#define BADVADDR 66
+#define MMHI 67
+#define MMLO 68
 #define NUM_REGISTERS 32
 
 #include 
@@ -466,21 +473,23 @@
   }
 
   if (IsFPR(reg_index) || IsMSA(reg_index)) {
-uint8_t *dst;
-uint64_t *src;
+uint8_t *dst = nullptr;
+uint64_t *src = nullptr;
+uint8_t byte_size = reg_info->byte_size;
 
 // Initialise the FP and MSA buffers by reading all co-processor 1 registers
 ReadCP1();
 
 if (IsFPR(reg_index)) {
   assert(reg_info->byte_offset < sizeof(UserArea));
   dst = (uint8_t *)_fpr + reg_info->byte_offset - (sizeof(m_gpr));
+  byte_size = IsFR0() ? 4 : 8;
 } else {
   assert(reg_info->byte_offset < sizeof(UserArea));
   dst = (uint8_t *)_msa + reg_info->byte_offset -
 (sizeof(m_gpr) + sizeof(m_fpr));
 }
-switch (reg_info->byte_size) {
+switch (byte_size) {
 case 4:
   *(uint32_t *)dst = reg_value.GetAsUInt32();
   break;
@@ -611,11 +620,12 @@
 Error NativeRegisterContextLinux_mips64::ReadCP1() {
   Error error;
 
-  uint8_t *src, *dst;
+  uint8_t *src = nullptr;
+  uint8_t *dst = nullptr;
 
   lldb::ByteOrder byte_order = GetByteOrder();
 
-  uint32_t IsBigEndian = (byte_order == lldb::eByteOrderBig);
+  bool IsBigEndian = (byte_order == lldb::eByteOrderBig);
 
   if (IsMSAAvailable()) {
 error = NativeRegisterContextLinux::ReadRegisterSet(
@@ -637,11 +647,18 @@
 
   // TODO: Add support for FRE
   if (IsFR0()) {
-src = (uint8_t *)_fpr + 4 + (IsBigEndian * 4);
-dst = (uint8_t *)_fpr + 8 + (IsBigEndian * 4);
+src = (uint8_t *)_fpr + (!IsBigEndian) * 4;
+dst = (uint8_t *)_fpr + 8;
 for (int i = 0; i < (NUM_REGISTERS / 2); i++) {
   // copy odd single from top of neighbouring even double
+  // In case of little endian, 32 bit LSB store even FP register
+  // and 32 bit MSB store odd FP register
+  // vice-versa for big-endian
   *(uint32_t *)dst = *(uint32_t *)src;
+
+  if (IsBigEndian)
+// Copy 32 bit MSB to 32 bit LSB
+*(uint32_t *)src = *(uint32_t *)(src + 4);
   src = src + 16;
   dst = dst + 16;
 }
@@ -653,18 +670,23 @@
 Error NativeRegisterContextLinux_mips64::WriteCP1() {
   Error error;
 
-  uint8_t *src, *dst;
+  uint8_t *src = nullptr;
+  uint8_t *dst = nullptr;
 
   lldb::ByteOrder byte_order = GetByteOrder();
 
-  uint32_t IsBigEndian = (byte_order == lldb::eByteOrderBig);
+  bool IsBigEndian = (byte_order == lldb::eByteOrderBig);
 
   // TODO: Add support for FRE
   if (IsFR0()) {
-src = (uint8_t *)_fpr + 8 + (IsBigEndian * 4);
-dst = (uint8_t *)_fpr + 4 + (IsBigEndian * 4);
+dst = (uint8_t *)_fpr + (!IsBigEndian) * 4;
+src = dst + 8 - (!IsBigEndian) * 4;
 for (int i = 0; i < (NUM_REGISTERS / 2); i++) {
   // copy odd single to top of neighbouring even double
+  if (IsBigEndian)
+// Copy 32 bit LSB to 32 bit

Re: [Lldb-commits] [PATCH] D24124: [LLDB][MIPS] Fix register read/write for 32 bit big endian system

2016-09-15 Thread Nitesh Jain via lldb-commits

nitesh.jain added a comment.

Will submit separate patch for Floating point register read/write and ptrace 
changes.


https://reviews.llvm.org/D24124



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D24124: [LLDB][MIPS] Fix register read/write for 32 bit big endian system

2016-09-15 Thread Nitesh Jain via lldb-commits

nitesh.jain marked 2 inline comments as done.
nitesh.jain added a comment.

https://reviews.llvm.org/D24124



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D24124: [LLDB][MIPS] Fix register read/write for 32 bit big endian system

2016-09-15 Thread Nitesh Jain via lldb-commits

nitesh.jain added inline comments.


Comment at: 
source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp:1940
@@ +1939,3 @@
+  uint64_t dst_value;
+  RegisterValue reg_value;
+  lldb::ByteOrder byte_order = lldb::eByteOrderInvalid;

The GetAsUint64 work well on 32 bit little endian system since 32 bit data  is 
copy at lower address in SetBytes which is valid for little endian but not on 
32 bit big endian system.  The Goal is to GetAsUint64 work for 32 bit big 
endian data type. We can do following change inorder to make it work for 
RegisterValue type eTypeBytes

uint64_t
RegisterValue::GetAsUInt64 (uint64_t fail_value, bool *success_ptr) const
{
if (success_ptr)
*success_ptr = true;
switch (m_type)
{
...
...
...
case eTypeBytes:
{
switch (buffer.length)
{
default:break;
case 1:
case 2:
case 4:
case 8: return *(const uint64_t *)buffer.bytes;
}
}
break;
}
if (success_ptr)
*success_ptr = false;
return fail_value;
}

We can modify the case for buffer.length = 4/2/1 

switch (buffer.length) {
  case 1:  return *(const uint8_t *)buffer.bytes;
  case 2:  return *(const uint16_t *)buffer.bytes;
  case 4:  return *(const uint32_t *)buffer.bytes;

...
...
...
   }



https://reviews.llvm.org/D24124



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D24124: [LLDB][MIPS] Fix register read/write for 32 bit big endian system

2016-09-15 Thread Nitesh Jain via lldb-commits

nitesh.jain retitled this revision from "[LLDB][MIPS] Fix register read/write 
for big endian" to "[LLDB][MIPS] Fix register read/write for 32 bit big endian 
system".
nitesh.jain updated the summary for this revision.
nitesh.jain updated this revision to Diff 71360.

https://reviews.llvm.org/D24124

Files:
  include/lldb/Core/DataExtractor.h
  source/Core/DataExtractor.cpp
  source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp
  source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp

Index: source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
===
--- source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
+++ source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
@@ -1936,8 +1936,17 @@
 
   // Build the reginfos response.
   StreamGDBRemote response;
-
-  RegisterValue reg_value(reg_bytes, reg_size, process_arch.GetByteOrder());
+  uint64_t dst_value;
+  RegisterValue reg_value;
+  lldb::ByteOrder byte_order = lldb::eByteOrderInvalid;
+  // The host will always send data in target byte order
+  // Hence source byte order will be same as destination byte order
+  m_debugged_process_sp->GetByteOrder(byte_order);
+  
+  DataExtractor::CopyByteOrderedData(reg_bytes, reg_size,
+ byte_order, _value,
+ sizeof(dst_value), byte_order);
+  reg_value.SetUInt(dst_value, reg_size);
   Error error = reg_context_sp->WriteRegister(reg_info, reg_value);
   if (error.Fail()) {
 if (log)
Index: source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp
===
--- source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp
+++ source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp
@@ -169,7 +169,7 @@
 
   if (error.Success())
 // First cast to an unsigned of the same size to avoid sign extension.
-value.SetUInt64(static_cast(data));
+value.SetUInt(static_cast(data), size);
 
   if (log)
 log->Printf("NativeRegisterContextLinux::%s() reg %s: 0x%lx", __FUNCTION__,
Index: source/Core/DataExtractor.cpp
===
--- source/Core/DataExtractor.cpp
+++ source/Core/DataExtractor.cpp
@@ -938,6 +938,87 @@
   return 0;
 }
 
+lldb::offset_t DataExtractor::CopyByteOrderedData(void *src_void_ptr,
+  offset_t src_len,
+  ByteOrder src_byte_order,
+  void *dst_void_ptr,
+  offset_t dst_len,
+  ByteOrder dst_byte_order) {
+
+  // Validate the source and destination info
+  assert(dst_void_ptr != nullptr || src_void_ptr != nullptr);
+  assert(dst_len > 0 || src_len > 0);
+  assert(src_len <= dst_len);
+  assert(dst_byte_order == eByteOrderBig || dst_byte_order == eByteOrderLittle);
+  assert(src_byte_order == eByteOrderBig || src_byte_order == eByteOrderLittle);
+
+  // Validate that only a word- or register-sized dst is byte swapped
+  assert(dst_byte_order == src_byte_order || dst_len == 1 || dst_len == 2 ||
+ dst_len == 4 || dst_len == 8 || dst_len == 10 || dst_len == 16 ||
+ dst_len == 32);
+
+  uint8_t* dst = (uint8_t*)dst_void_ptr;
+  const uint8_t* src = (const uint8_t *)src_void_ptr;
+  if (src) {
+if (dst_len >= src_len) {
+  // We are copying the entire value from src into dst.
+  // Calculate how many, if any, zeroes we need for the most
+  // significant bytes if "dst_len" is greater than "src_len"...
+  const size_t num_zeroes = dst_len - src_len;
+  if (dst_byte_order == eByteOrderBig) {
+// Big endian, so we lead with zeroes...
+if (num_zeroes > 0)
+  ::memset(dst, 0, num_zeroes);
+// Then either copy or swap the rest
+if (src_byte_order == eByteOrderBig) {
+  ::memcpy(dst + num_zeroes, src, src_len);
+} else {
+  for (uint32_t i = 0; i < src_len; ++i)
+dst[i + num_zeroes] = src[src_len - 1 - i];
+}
+  } else {
+// Little endian destination, so we lead the value bytes
+if (src_byte_order == eByteOrderBig) {
+  for (uint32_t i = 0; i < src_len; ++i)
+dst[i] = src[src_len - 1 - i];
+} else {
+  ::memcpy(dst, src, src_len);
+}
+// And zero the rest...
+if (num_zeroes > 0)
+  ::memset(dst + src_len, 0, num_zeroes);
+  }
+  return src_len;
+} else {
+  // We are only copying some of the value from src into dst..
+
+  if (dst_byte_order == eByteOrderBig) {
+// Big endian dst
+if (src_byte_order == eByteOrderBig) {
+  // Big endian dst, with big endian src
+  ::memcpy(dst, src + (src_len -

[Lldb-commits] [PATCH] D24549: [LLDB][MIPS] Skip some test case which were causing LLDB to go into infinite loop

2016-09-14 Thread Nitesh Jain via lldb-commits

nitesh.jain created this revision.
nitesh.jain added reviewers: clayborg, labath.
nitesh.jain added subscribers: jaydeep, bhushan, slthakur, lldb-commits.

These test cases tries to insert breakpoint in atomic sequence and cause atomic 
sequence to restart when breakpoint is hit . 

https://reviews.llvm.org/D24549

Files:
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/breakpoint_delay_breakpoint_one_signal/TestConcurrentBreakpointDelayBreakpointOneSignal.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/breakpoint_one_delay_breakpoint_threads/TestConcurrentBreakpointOneDelayBreakpointThreads.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/breakpoints_delayed_breakpoint_one_watchpoint/TestConcurrentBreakpointsDelayedBreakpointOneWatchpoint.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/crash_with_break/TestConcurrentCrashWithBreak.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/crash_with_signal/TestConcurrentCrashWithSignal.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/crash_with_watchpoint/TestConcurrentCrashWithWatchpoint.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/crash_with_watchpoint_breakpoint_signal/TestConcurrentCrashWithWatchpointBreakpointSignal.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/delay_signal_break/TestConcurrentDelaySignalBreak.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/delay_signal_watch/TestConcurrentDelaySignalWatch.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/delay_watch_break/TestConcurrentDelayWatchBreak.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/delayed_crash_with_breakpoint_signal/TestConcurrentDelayedCrashWithBreakpointSignal.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/delayed_crash_with_breakpoint_watchpoint/TestConcurrentDelayedCrashWithBreakpointWatchpoint.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/many_breakpoints/TestConcurrentManyBreakpoints.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/many_crash/TestConcurrentManyCrash.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/many_signals/TestConcurrentManySignals.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/many_watchpoints/TestConcurrentManyWatchpoints.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/n_watch_n_break/TestConcurrentNWatchNBreak.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/signal_break/TestConcurrentSignalBreak.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/signal_delay_break/TestConcurrentSignalDelayBreak.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/signal_delay_watch/TestConcurrentSignalDelayWatch.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/signal_n_watch_n_break/TestConcurrentSignalNWatchNBreak.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/signal_watch/TestConcurrentSignalWatch.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/signal_watch_break/TestConcurrentSignalWatchBreak.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/two_breakpoint_threads/TestConcurrentTwoBreakpointThreads.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/two_breakpoints_one_delay_signal/TestConcurrentTwoBreakpointsOneDelaySignal.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/two_breakpoints_one_signal/TestConcurrentTwoBreakpointsOneSignal.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/two_breakpoints_one_watchpoint/TestConcurrentTwoBreakpointsOneWatchpoint.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/two_watchpoint_threads/TestConcurrentTwoWatchpointThreads.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/two_watchpoints_one_breakpoint/TestConcurrentTwoWatchpointsOneBreakpoint.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/two_watchpoints_one_delay_breakpoint/TestConcurrentTwoWatchpointsOneDelayBreakpoint.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/two_watchpoints_one_signal/TestConcurrentTwoWatchpointsOneSignal.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/watch_break/TestConcurrentWatchBreak.py
  
packages/Python/lldbsuite/test/functionalities/thread/concurrent_events/watch_break_delay/TestConcurrentWatchBreakDelay.py

Re: [Lldb-commits] [PATCH] D24498: [LLDB][MIPS] Fix TestReturnValue failure for MIPS

2016-09-13 Thread Nitesh Jain via lldb-commits

nitesh.jain added inline comments.


Comment at: source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp:972
@@ -968,4 +971,3 @@
 
   f0_value.GetData(f0_data);
 

The issued was while setting f0_data and f2_data successively via 
RegisterValue.GetData. Since RegisterValue.GetData() will internally call 
Scalar::GetBytes() which contain static member (flt_val and db1_val) for 
floating point type . Hence two successive calls to set data for m_type 
float/double will cause  the content of f0_data to be overwritten with the 
content of f2_value.

Scalar::GetBytes() const
{
const uint64_t *apint_words;
const uint8_t *bytes;
static float_t flt_val;
static double_t dbl_val;
static uint64_t swapped_words[4];

...
...
...
}


https://reviews.llvm.org/D24498



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [PATCH] D24498: [LLDB][MIPS] Fix TestReturnValue failure for MIPS

2016-09-13 Thread Nitesh Jain via lldb-commits

nitesh.jain created this revision.
nitesh.jain added reviewers: clayborg, labath, bhushan.
nitesh.jain added subscribers: jaydeep, slthakur, lldb-commits.
Herald added a subscriber: sdardis.

https://reviews.llvm.org/D24498

Files:
  source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp

Index: source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp
===
--- source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp
+++ source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp
@@ -923,23 +923,26 @@
target->GetArchitecture().GetAddressByteSize());
 
   RegisterValue r2_value, r3_value, f0_value, f1_value, f2_value;
-
-  uint32_t integer_bytes = 0; // Tracks how much bytes of r2 and r3
-  // registers we've consumed so far
-  bool use_fp_regs = 0; // True if return values are in FP return registers.
-  bool found_non_fp_field =
-  0; // True if we found any non floating point field in structure.
-  bool use_r2 = 0; // True if return values are in r2 register.
-  bool use_r3 = 0; // True if return values are in r3 register.
-  bool sucess = 0; // True if the result is copied into our data buffer
+  // Tracks how much bytes of r2 and r3 registers we've consumed so far
+  uint32_t integer_bytes = 0;
+
+  // True if return values are in FP return registers.
+  bool use_fp_regs = 0;
+  // True if we found any non floating point field in structure.
+  bool found_non_fp_field = 0;
+  // True if return values are in r2 register.
+  bool use_r2 = 0;
+  // True if return values are in r3 register.
+  bool use_r3 = 0;
+  // True if the result is copied into our data buffer
+  bool sucess = 0;
   std::string name;
   bool is_complex;
   uint32_t count;
   const uint32_t num_children = return_compiler_type.GetNumFields();
 
   // A structure consisting of one or two FP values (and nothing else) will
-  // be
-  // returned in the two FP return-value registers i.e fp0 and fp2.
+  // be returned in the two FP return-value registers i.e fp0 and fp2.
   if (num_children <= 2) {
 uint64_t field_bit_offset = 0;
 
@@ -967,7 +970,6 @@
   reg_ctx->ReadRegister(f2_info, f2_value);
 
   f0_value.GetData(f0_data);
-  f2_value.GetData(f2_data);
 
   for (uint32_t idx = 0; idx < num_children; idx++) {
 CompilerType field_compiler_type =
@@ -977,30 +979,40 @@
 field_compiler_type.GetByteSize(nullptr);
 
 DataExtractor *copy_from_extractor = nullptr;
+uint64_t return_value[2];
+offset_t offset = 0;
 
 if (idx == 0) {
-  if (field_byte_width == 16) // This case is for long double type.
-  {
+  // This case is for long double type.
+  if (field_byte_width == 16) {
+
 // If structure contains long double type, then it is returned
 // in fp0/fp1 registers.
-reg_ctx->ReadRegister(f1_info, f1_value);
-f1_value.GetData(f1_data);
-
 if (target_byte_order == eByteOrderLittle) {
-  f0_data.Append(f1_data);
-  copy_from_extractor = _data;
+  return_value[0] = f0_data.GetU64();
+  reg_ctx->ReadRegister(f1_info, f1_value);
+  f1_value.GetData(f1_data);
+  offset = 0;
+  return_value[1] = f1_data.GetU64();
 } else {
-  f1_data.Append(f0_data);
-  copy_from_extractor = _data;
+  return_value[1] = f0_data.GetU64();
+  reg_ctx->ReadRegister(f1_info, f1_value);
+  f1_value.GetData(f1_data);
+  offset = 0;
+  return_value[0] = f1_data.GetU64();
 }
-  } else
-copy_from_extractor = _data; // This is in f0, copy from
-// register to our result
-// structure
-} else
-  copy_from_extractor = _data; // This is in f2, copy from
+
+f0_data.SetData(return_value, field_byte_width,
+target_byte_order);
+  }
+  copy_from_extractor = _data; // This is in f0, copy from
   // register to our result
   // structure
+} else {
+  f2_value.GetData(f2_data);
+  // This is in f2, copy from register to our result structure
+  copy_from_extractor = _data;
+}
 
 // Sanity check to avoid crash
 if (!copy_from_extractor ||
___
lldb-commits

[Lldb-commits] [lldb] r281032 - [LLDB][MIPS] Fix Emulation for JALR64 Instruction

2016-09-09 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Fri Sep  9 05:46:25 2016
New Revision: 281032

URL: http://llvm.org/viewvc/llvm-project?rev=281032=rev
Log:
[LLDB][MIPS] Fix Emulation for JALR64 Instruction

Subscribers: jaydeep, bhushan, slthakur, sdardis, lldb-commits

Modified:
lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp

Modified: 
lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp?rev=281032=281031=281032=diff
==
--- lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp 
(original)
+++ lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp 
Fri Sep  9 05:46:25 2016
@@ -869,6 +869,7 @@ EmulateInstructionMIPS64::GetOpcodeForIn
   {"JAL", ::Emulate_JAL, "JAL target"},
   {"JALX", ::Emulate_JAL, "JALX target"},
   {"JALR", ::Emulate_JALR, "JALR target"},
+  {"JALR64", ::Emulate_JALR, "JALR target"},
   {"JALR_HB", ::Emulate_JALR, "JALR.HB target"},
   {"JIALC", ::Emulate_JIALC, "JIALC rt,offset"},
   {"JIC", ::Emulate_JIC, "JIC rt,offset"},


___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D24122: [LLDB][MIPS] Fix TestEhFrameUnwind.py for MIPS

2016-09-09 Thread Nitesh Jain via lldb-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL281031: [LLDB][MIPS] Fix TestEhFrameUnwind.py for MIPS 
(authored by nitesh.jain).

Changed prior to commit:
  https://reviews.llvm.org/D24122?vs=69974=70807#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D24122

Files:
  
lldb/trunk/packages/Python/lldbsuite/test/functionalities/unwind/ehframe/main.c

Index: 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/unwind/ehframe/main.c
===
--- 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/unwind/ehframe/main.c
+++ 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/unwind/ehframe/main.c
@@ -1,4 +1,6 @@
 void func() {
+
+#ifndef __mips__
__asm__ (
"pushq $0x10;"
".cfi_def_cfa_offset 16;"
@@ -10,11 +12,35 @@
"movq $0x48, %rax;"
"popq %rax;"
);
-
+#elif __mips64
+   __asm__ (
+"daddiu $sp,$sp,-16;"
+".cfi_def_cfa_offset 16;"
+"sd $ra,8($sp);"
+".cfi_offset 31, -8;"
+"daddiu $ra,$zero,0;"
+"ld $ra,8($sp);"
+"daddiu $sp, $sp,16;"
+".cfi_restore 31;"
+".cfi_def_cfa_offset 0;"
+   );
+#else
+   // For MIPS32
+   __asm__ (
+"addiu $sp,$sp,-8;"
+".cfi_def_cfa_offset 8;"
+"sw $ra,4($sp);"
+".cfi_offset 31, -4;"
+"addiu $ra,$zero,0;"
+"lw $ra,4($sp);"
+"addiu $sp,$sp,8;"
+".cfi_restore 31;"
+".cfi_def_cfa_offset 0;"
+   );
+#endif
 }
 
-
 int main(int argc, char const *argv[])
 {
func();
-}
\ No newline at end of file
+}


Index: lldb/trunk/packages/Python/lldbsuite/test/functionalities/unwind/ehframe/main.c
===
--- lldb/trunk/packages/Python/lldbsuite/test/functionalities/unwind/ehframe/main.c
+++ lldb/trunk/packages/Python/lldbsuite/test/functionalities/unwind/ehframe/main.c
@@ -1,4 +1,6 @@
 void func() {
+
+#ifndef __mips__
 	__asm__ (
 		"pushq $0x10;"
 		".cfi_def_cfa_offset 16;"
@@ -10,11 +12,35 @@
 		"movq $0x48, %rax;"
 		"popq %rax;"
 	);
-
+#elif __mips64
+   __asm__ (
+"daddiu $sp,$sp,-16;"
+".cfi_def_cfa_offset 16;"
+"sd $ra,8($sp);"
+".cfi_offset 31, -8;"
+"daddiu $ra,$zero,0;"
+"ld $ra,8($sp);"
+"daddiu $sp, $sp,16;"
+".cfi_restore 31;"
+".cfi_def_cfa_offset 0;"
+   );
+#else
+   // For MIPS32
+   __asm__ (
+"addiu $sp,$sp,-8;"
+".cfi_def_cfa_offset 8;"
+"sw $ra,4($sp);"
+".cfi_offset 31, -4;"
+"addiu $ra,$zero,0;"
+"lw $ra,4($sp);"
+"addiu $sp,$sp,8;"
+".cfi_restore 31;"
+".cfi_def_cfa_offset 0;"
+   );
+#endif
 }
 
-
 int main(int argc, char const *argv[])
 {
 	func();
-}
\ No newline at end of file
+}
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] r281031 - [LLDB][MIPS] Fix TestEhFrameUnwind.py for MIPS

2016-09-09 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Fri Sep  9 05:20:08 2016
New Revision: 281031

URL: http://llvm.org/viewvc/llvm-project?rev=281031=rev
Log:
[LLDB][MIPS] Fix TestEhFrameUnwind.py for MIPS

Reviewers: clayborg, labath

Subscribers: jaydeep, bhushan, slthakur, lldb-commits

Differential Revision: https://reviews.llvm.org/D24122

Modified:

lldb/trunk/packages/Python/lldbsuite/test/functionalities/unwind/ehframe/main.c

Modified: 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/unwind/ehframe/main.c
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/functionalities/unwind/ehframe/main.c?rev=281031=281030=281031=diff
==
--- 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/unwind/ehframe/main.c 
(original)
+++ 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/unwind/ehframe/main.c 
Fri Sep  9 05:20:08 2016
@@ -1,4 +1,6 @@
 void func() {
+
+#ifndef __mips__
__asm__ (
"pushq $0x10;"
".cfi_def_cfa_offset 16;"
@@ -10,11 +12,35 @@ void func() {
"movq $0x48, %rax;"
"popq %rax;"
);
-
+#elif __mips64
+   __asm__ (
+"daddiu $sp,$sp,-16;"
+".cfi_def_cfa_offset 16;"
+"sd $ra,8($sp);"
+".cfi_offset 31, -8;"
+"daddiu $ra,$zero,0;"
+"ld $ra,8($sp);"
+"daddiu $sp, $sp,16;"
+".cfi_restore 31;"
+".cfi_def_cfa_offset 0;"
+   );
+#else
+   // For MIPS32
+   __asm__ (
+"addiu $sp,$sp,-8;"
+".cfi_def_cfa_offset 8;"
+"sw $ra,4($sp);"
+".cfi_offset 31, -4;"
+"addiu $ra,$zero,0;"
+"lw $ra,4($sp);"
+"addiu $sp,$sp,8;"
+".cfi_restore 31;"
+".cfi_def_cfa_offset 0;"
+   );
+#endif
 }
 
-
 int main(int argc, char const *argv[])
 {
func();
-}
\ No newline at end of file
+}


___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] r281026 - [LLDB][MIPS] Fix TestLldbGdbServer.py failure

2016-09-09 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Fri Sep  9 04:50:33 2016
New Revision: 281026

URL: http://llvm.org/viewvc/llvm-project?rev=281026=rev
Log:
[LLDB][MIPS] Fix TestLldbGdbServer.py failure

Subscribers: jaydeep, bhushan, slthakur, lldb-commits

Modified:

lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py

Modified: 
lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py?rev=281026=281025=281026=diff
==
--- 
lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
 (original)
+++ 
lldb/trunk/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
 Fri Sep  9 04:50:33 2016
@@ -724,7 +724,9 @@ class GdbRemoteTestCaseBase(TestBase):
 "dwarf",
 "generic",
 "container-regs",
-"invalidate-regs"
+"invalidate-regs",
+"dynamic_size_dwarf_expr_bytes",
+"dynamic_size_dwarf_len"
 ]
 
 def assert_valid_reg_info(self, reg_info):


___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D24124: [LLDB][MIPS] Fix register read/write for big endian

2016-09-01 Thread Nitesh Jain via lldb-commits

nitesh.jain added inline comments.


Comment at: 
source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp:1844
@@ +1843,3 @@
+
+uint64_t value;
+value = reg_size == 4 ? *(uint32_t *)reg_bytes : *(uint64_t *)reg_bytes;

labath wrote:
> This looks like a massive hack. The register value object already takes a 
> byte order as a parameter, so the fact that you are doing some funny endian 
> conversions here means that there is something wrong. Also, this probably 
> will not work for registers whose sizes are not 4 or 8 (%ah, %ax, all SSE 
> registers, etc.).
> 
> I think we'll need to find a different way to fix this.
The problem is  with RegisterValue.SetBytes 

RegisterValue (uint8_t *bytes, size_t length, lldb::ByteOrder byte_order)
{
SetBytes (bytes, length, byte_order);
}

The RegisterValue.SetBytes use memcpy to perform copy . So for register whose 
size is 4 it will be copy to lower 32bit LSB and hence 
RegisterValue.GetAsUInt64 will give incorrect result for 32 bit big endian 
system. 


https://reviews.llvm.org/D24124



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [PATCH] D24124: [LLDB][MIPS] Fix register read/write for big endian

2016-09-01 Thread Nitesh Jain via lldb-commits

nitesh.jain created this revision.
nitesh.jain added reviewers: clayborg, labath.
nitesh.jain added subscribers: jaydeep, bhushan, slthakur, lldb-commits.
Herald added a subscriber: sdardis.

The RegisterValue.SetBytes for 4 byte data followed by GetAsUInt64 for 32 bit 
big endian system will produce incorrect result. Instead use 
RegisterValue.SetUInt which will preserved endianess. This patch also add 
register read/write via PTRACE_PEEKUSER/PTRACE_POKEUSER for and fix floating 
point register read/write for MIPS.

https://reviews.llvm.org/D24124

Files:
  source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp
  source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
  source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.h
  source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp

Index: source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
===
--- source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
+++ source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
@@ -1840,8 +1840,12 @@
 
 // Build the reginfos response.
 StreamGDBRemote response;
+
+uint64_t value;
+value = reg_size == 4 ? *(uint32_t *)reg_bytes : *(uint64_t *)reg_bytes;
 
-RegisterValue reg_value (reg_bytes, reg_size, process_arch.GetByteOrder ());
+RegisterValue reg_value;
+reg_value.SetUInt (value, reg_size);
 Error error = reg_context_sp->WriteRegister (reg_info, reg_value);
 if (error.Fail ())
 {
Index: source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.h
===
--- source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.h
+++ source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.h
@@ -94,15 +94,22 @@
 
 protected:
 Error
-DoReadRegisterValue(uint32_t offset,
-const char* reg_name,
-uint32_t size,
-RegisterValue ) override;
+DoReadRegister_SR_Config (uint32_t offset,
+  const char* reg_name,
+  uint32_t size,
+  RegisterValue );
+
+uint32_t
+GetPtraceRegisterOffset (uint32_t reg_index,
+ const RegisterInfo *const reg_info);
+
+Error
+ReadRegisterRaw (uint32_t reg_index,
+ RegisterValue ) override;
 
 Error
-DoWriteRegisterValue(uint32_t offset,
- const char* reg_name,
- const RegisterValue ) override;
+WriteRegisterRaw (uint32_t reg_index,
+  const RegisterValue ) override;
 
 Error
 DoReadWatchPointRegisterValue(lldb::tid_t tid, void* watch_readback);
Index: source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
===
--- source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
+++ source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
@@ -28,9 +28,16 @@
 #include "Plugins/Process/Linux/Procfs.h"
 #include "Plugins/Process/Utility/RegisterContextLinux_mips64.h"
 #include "Plugins/Process/Utility/RegisterContextLinux_mips.h"
+
 #define NT_MIPS_MSA 0x600
 #define CONFIG5_FRE (1 << 8)
 #define SR_FR (1 << 26)
+#define FPR_BASE32
+#define PC  64
+#define CAUSE   65
+#define BADVADDR66
+#define MMHI67
+#define MMLO68
 #define NUM_REGISTERS 32
 
 #include 
@@ -649,7 +656,7 @@
 
 if (IsFPR(reg_index) || IsMSA(reg_index))
 {
-uint8_t *dst;
+uint8_t *dst, byte_size;
 uint64_t *src;
 
 // Initialise the FP and MSA buffers by reading all co-processor 1 registers
@@ -659,13 +666,14 @@
 {
 assert (reg_info->byte_offset < sizeof(UserArea));
 dst = (uint8_t *)_fpr + reg_info->byte_offset - (sizeof(m_gpr));
+byte_size = IsFR0 () ? 4 : 8;
 }
 else
 {
 assert (reg_info->byte_offset < sizeof(UserArea));
 dst = (uint8_t *)_msa + reg_info->byte_offset - (sizeof(m_gpr) + sizeof(m_fpr));
 }
-switch (reg_info->byte_size)
+switch (byte_size)
 {
 case 4:
 *(uint32_t *)dst = reg_value.GetAsUInt32();
@@ -801,7 +809,7 @@
 
 lldb::ByteOrder byte_order = GetByteOrder();
 
-uint32_t IsBigEndian = (byte_order == lldb::eByteOrderBig);
+bool IsBigEndian = (byte_order == lldb::eByteOrderBig);
 
 if (IsMSAAvailable())
 {
@@ -827,12 +835,20 @@
 // TODO: Add support for FRE
 if (IsFR0())
 {
- src = (uint8_t *)_fpr + 4 + (IsBigEndian * 4);
- dst = (uint8_t *)_fpr + 8 + (IsBigEndian * 4);
+

[Lldb-commits] [PATCH] D24122: [LLDB][MIPS] Fix TestEhFrameUnwind.py for MIPS

2016-09-01 Thread Nitesh Jain via lldb-commits

nitesh.jain created this revision.
nitesh.jain added reviewers: clayborg, labath.
nitesh.jain added subscribers: jaydeep, bhushan, slthakur, lldb-commits.

This patch will fix TestEhFrameUnwind.py failure for MIPS

https://reviews.llvm.org/D24122

Files:
  packages/Python/lldbsuite/test/functionalities/unwind/ehframe/main.c

Index: packages/Python/lldbsuite/test/functionalities/unwind/ehframe/main.c
===
--- packages/Python/lldbsuite/test/functionalities/unwind/ehframe/main.c
+++ packages/Python/lldbsuite/test/functionalities/unwind/ehframe/main.c
@@ -1,4 +1,6 @@
 void func() {
+
+#ifndef __mips__
__asm__ (
"pushq $0x10;"
".cfi_def_cfa_offset 16;"
@@ -10,11 +12,35 @@
"movq $0x48, %rax;"
"popq %rax;"
);
-
+#elif __mips64
+   __asm__ (
+"daddiu $sp,$sp,-16;"
+".cfi_def_cfa_offset 16;"
+"sd $ra,8($sp);"
+".cfi_offset 31, -8;"
+"daddiu $ra,$zero,0;"
+"ld $ra,8($sp);"
+"daddiu $sp, $sp,16;"
+".cfi_restore 31;"
+".cfi_def_cfa_offset 0;"
+   );
+#else
+   // For MIPS32
+   __asm__ (
+"addiu $sp,$sp,-8;"
+".cfi_def_cfa_offset 8;"
+"sw $ra,4($sp);"
+".cfi_offset 31, -4;"
+"addiu $ra,$zero,0;"
+"lw $ra,4($sp);"
+"addiu $sp,$sp,8;"
+".cfi_restore 31;"
+".cfi_def_cfa_offset 0;"
+   );
+#endif
 }
 
-
 int main(int argc, char const *argv[])
 {
func();
-}
\ No newline at end of file
+}


Index: packages/Python/lldbsuite/test/functionalities/unwind/ehframe/main.c
===
--- packages/Python/lldbsuite/test/functionalities/unwind/ehframe/main.c
+++ packages/Python/lldbsuite/test/functionalities/unwind/ehframe/main.c
@@ -1,4 +1,6 @@
 void func() {
+
+#ifndef __mips__
 	__asm__ (
 		"pushq $0x10;"
 		".cfi_def_cfa_offset 16;"
@@ -10,11 +12,35 @@
 		"movq $0x48, %rax;"
 		"popq %rax;"
 	);
-
+#elif __mips64
+   __asm__ (
+"daddiu $sp,$sp,-16;"
+".cfi_def_cfa_offset 16;"
+"sd $ra,8($sp);"
+".cfi_offset 31, -8;"
+"daddiu $ra,$zero,0;"
+"ld $ra,8($sp);"
+"daddiu $sp, $sp,16;"
+".cfi_restore 31;"
+".cfi_def_cfa_offset 0;"
+   );
+#else
+   // For MIPS32
+   __asm__ (
+"addiu $sp,$sp,-8;"
+".cfi_def_cfa_offset 8;"
+"sw $ra,4($sp);"
+".cfi_offset 31, -4;"
+"addiu $ra,$zero,0;"
+"lw $ra,4($sp);"
+"addiu $sp,$sp,8;"
+".cfi_restore 31;"
+".cfi_def_cfa_offset 0;"
+   );
+#endif
 }
 
-
 int main(int argc, char const *argv[])
 {
 	func();
-}
\ No newline at end of file
+}
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D23802: gdb-remote: Make the sequence mutex non-recursive

2016-08-30 Thread Nitesh Jain via lldb-commits

nitesh.jain added a comment.

Forgot to mention that this case has been observed for MIPS architecture. Since 
for MIPS, the floating point register size is calculated at runtime.

-NJ


Repository:
  rL LLVM

https://reviews.llvm.org/D23802



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D23802: gdb-remote: Make the sequence mutex non-recursive

2016-08-30 Thread Nitesh Jain via lldb-commits

nitesh.jain added inline comments.


Comment at: 
lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp:131
@@ +130,3 @@
+
+GDBRemoteClientBase::Lock lock(gdb_comm, false);
+if (!lock)

Hi labath,

This patch cause deadlock when we try to run "reg read f0".  The 
GDBRemoteRegisterContext::ReadRegister is call twice which result in deadlock 
since earlier acquire lock has not been release.

1) To Evaluate Dwarf expression so that floating register size can be determine 
at run time. It add overhead of reading one more register which cause lock to 
acquire and forgot to release at the end.

2) To read register f0. This time it try to acquire lock which is not been 
release resulting in deadlock.

-NJ




Repository:
  rL LLVM

https://reviews.llvm.org/D23802



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [Diffusion] rL277426: [LLVM][MIPS] Add (D)SUBU, (D)ADDU, LUI instructions emulation . Fix emulation…

2016-08-09 Thread Nitesh Jain via lldb-commits

Thanks Hans

-Original Message-
From: hwennb...@google.com [mailto:hwennb...@google.com] On Behalf Of Hans 
Wennborg
Sent: 09 August 2016 01:59
To: Greg Clayton
Cc: Nitesh Jain; Jaydeep Patil; Bhushan Attarde; lldb-commits@lists.llvm.org
Subject: Re: [Diffusion] rL277426: [LLVM][MIPS] Add (D)SUBU, (D)ADDU, LUI 
instructions emulation . Fix emulation…

Thanks! r278047.

On Mon, Aug 8, 2016 at 10:26 AM, Greg Clayton  wrote:
> I am fine with this. It is in MIPS only code so it shouldn't affect anything 
> else.
>
>> On Aug 2, 2016, at 8:49 AM, Hans Wennborg  wrote:
>>
>> While this all seems very MIPS-specific, so probably fine to merge if 
>> you want to, it does look more like new development than just bug 
>> fixing.
>>
>> I'm OK with merging this if Clayton approves, though.
>>
>> Thanks,
>> Hans
>>
>> On Tue, Aug 2, 2016 at 12:49 AM, Nitesh Jain  wrote:
>>> Hi Hans,
>>>
>>> Could you please merge this to the LLDB 3.9 release branch ?
>>>
>>> Thanks & regards,
>>> Nitesh Jain
>>>
>>> -Original Message-
>>> From: Nitesh Jain
>>> Sent: 02 August 2016 12:56
>>> To: Nitesh Jain
>>> Subject: Re: [Diffusion] rL277426: [LLVM][MIPS] Add (D)SUBU, 
>>> (D)ADDU, LUI instructions emulation . Fix emulation…
>>>
>>> nitesh.jain committed rL277426: [LLVM][MIPS] Add (D)SUBU, (D)ADDU, LUI 
>>> instructions emulation . Fix emulation….
>>>
>>> [LLVM][MIPS] Add (D)SUBU, (D)ADDU, LUI instructions emulation . Fix 
>>> emulation for (D)ADDIU, SD/SW and LW/LD instructions
>>>
>>> Reviewers: clayborg, jaydeep, bhushan
>>>
>>> Subscribers: mohit.bhakkad, slthakur, sdardis, lldb-commits
>>>
>>> Differential Revision: https://reviews.llvm.org/D22851
>>>
>>>
>>> Files:
>>>  
>>> /lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.c
>>> pp  
>>> /lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h
>>>  
>>> /lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS
>>> 64.cpp  
>>> /lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS
>>> 64.h
>>>
>>> Users:
>>>  nitesh.jain (Author)
>>>
>>> https://reviews.llvm.org/rL277426
>>>
>>>
>>>
>
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D20357: [LLDB][MIPS] Fix FPU Size Based on Dynamic FR (Merge Request)

2016-08-09 Thread Nitesh Jain via lldb-commits

Thanks Hans.

-Original Message-
From: hwennb...@google.com [mailto:hwennb...@google.com] On Behalf Of Hans 
Wennborg
Sent: 09 August 2016 01:58
To: Greg Clayton
Cc: Nitesh Jain; Jaydeep Patil; Bhushan Attarde; lldb-commits@lists.llvm.org
Subject: Re: [PATCH] D20357: [LLDB][MIPS] Fix FPU Size Based on Dynamic FR 
(Merge Request)

Thanks! Merged in r278046.

On Mon, Aug 8, 2016 at 10:25 AM, Greg Clayton  wrote:
> I am fine with this going in, but this fix is for MIPS only.
>
>
>> On Aug 2, 2016, at 8:47 AM, Hans Wennborg  wrote:
>>
>> Looks like a pretty big change to merge at this stage.
>>
>> I'll let Clayton decide.
>>
>> Thanks,
>> Hans
>>
>> On Mon, Aug 1, 2016 at 11:25 PM, Nitesh Jain  wrote:
>>> Hi Hans,
>>>
>>> Could you please add this to the LLDB 3.9 release branch ?
>>>
>>> Thanks & regards,
>>> Nitesh Jain
>>>
>>>
>>> -Original Message-
>>> From: Nitesh Jain
>>> Sent: 01 August 2016 19:24
>>> To: Nitesh Jain; jing...@apple.com; clayb...@gmail.com
>>> Cc: ema...@freebsd.org; nemanja.i@gmail.com; lab...@google.com; 
>>> lldb-commits@lists.llvm.org; Simon Dardis; Mohit Bhakkad; Sagar 
>>> Thakur; Bhushan Attarde; Jaydeep Patil
>>> Subject: Re: [PATCH] D20357: [LLDB][MIPS] Fix FPU Size Based on 
>>> Dynamic FR
>>>
>>> This revision was automatically updated to reflect the committed changes.
>>> Closed by commit rL277343: [LLVM][MIPS] Fix FPU Size Based on Dynamic FR. 
>>> (authored by nitesh.jain).
>>>
>>> Changed prior to commit:
>>>  https://reviews.llvm.org/D20357?vs=65923=66314#toc
>>>
>>> Repository:
>>>  rL LLVM
>>>
>>> https://reviews.llvm.org/D20357
>>>
>>> Files:
>>>  lldb/trunk/include/lldb/Target/RegisterContext.h
>>>  lldb/trunk/include/lldb/lldb-private-types.h
>>>  lldb/trunk/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp
>>>  lldb/trunk/source/Plugins/Process/Utility/DynamicRegisterInfo.h
>>>  
>>> lldb/trunk/source/Plugins/Process/Utility/RegisterContextDarwin_arm.
>>> cpp  
>>> lldb/trunk/source/Plugins/Process/Utility/RegisterContextDarwin_arm6
>>> 4.cpp  
>>> lldb/trunk/source/Plugins/Process/Utility/RegisterContextFreeBSD_arm
>>> .cpp  
>>> lldb/trunk/source/Plugins/Process/Utility/RegisterContextFreeBSD_arm
>>> 64.cpp  
>>> lldb/trunk/source/Plugins/Process/Utility/RegisterContextLinux_arm.c
>>> pp  
>>> lldb/trunk/source/Plugins/Process/Utility/RegisterContextLinux_arm64
>>> .cpp  lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_arm.h
>>>  lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_arm64.h
>>>  lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_i386.h
>>>  lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_mips.h
>>>  lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_mips64.h
>>>  lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_powerpc.h
>>>  lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_s390x.h
>>>  lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_x86_64.h
>>>  
>>> lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationS
>>> erverLLGS.cpp  
>>> lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContex
>>> t.cpp  
>>> lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
>>>  lldb/trunk/source/Target/RegisterContext.cpp
>>>
>
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D22851: [LLDB][MIPS] Add (D)SUBU, (D)ADDU, LUI instructions emulation . Fix emulation for (D)ADDIU, SD/SW and LW/LD instructions

2016-08-02 Thread Nitesh Jain via lldb-commits

nitesh.jain closed this revision.
nitesh.jain added a comment.

committed in revision https://reviews.llvm.org/rL277426,


https://reviews.llvm.org/D22851



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] r277426 - [LLVM][MIPS] Add (D)SUBU, (D)ADDU, LUI instructions emulation . Fix emulation for (D)ADDIU, SD/SW and LW/LD instructions

2016-08-02 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Tue Aug  2 02:18:07 2016
New Revision: 277426

URL: http://llvm.org/viewvc/llvm-project?rev=277426=rev
Log:
[LLVM][MIPS] Add (D)SUBU, (D)ADDU, LUI instructions emulation . Fix emulation 
for (D)ADDIU, SD/SW and LW/LD instructions

Reviewers: clayborg, jaydeep, bhushan

Subscribers: mohit.bhakkad, slthakur, sdardis, lldb-commits

Differential Revision: https://reviews.llvm.org/D20357

Modified:
lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h
lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h

Modified: lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp?rev=277426=277425=277426=diff
==
--- lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp 
(original)
+++ lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp Tue 
Aug  2 02:18:07 2016
@@ -494,9 +494,13 @@ EmulateInstructionMIPS::GetOpcodeForInst
 
//--
 // Prologue/Epilogue instructions
 
//--
-{ "ADDiu",  ::Emulate_ADDiu,   "ADDIU 
rt,rs,immediate"},
-{ "SW", ::Emulate_SW,  "SW 
rt,offset(rs)" },
-{ "LW", ::Emulate_LW,  "LW 
rt,offset(base)"   },
+{ "ADDiu",  ::Emulate_ADDiu,   "ADDIU 
rt, rs, immediate"},
+{ "SW", ::Emulate_SW,  "SW rt, 
offset(rs)"  },
+{ "LW", ::Emulate_LW,  "LW rt, 
offset(base)"},
+{ "SUBU",   ::Emulate_SUBU_ADDU,   "SUBU 
rd, rs, rt"},
+{ "ADDU",   ::Emulate_SUBU_ADDU,   "ADDU 
rd, rs, rt"},
+{ "LUI",::Emulate_LUI,  "LUI 
rt, immediate"  },
+
 
//--
 // MicroMIPS Prologue/Epilogue instructions
 
//--
@@ -904,36 +908,57 @@ EmulateInstructionMIPS::nonvolatile_reg_
 bool
 EmulateInstructionMIPS::Emulate_ADDiu (llvm::MCInst& insn)
 {
+// ADDIU rt, rs, immediate
+// GPR[rt] <- GPR[rs] + sign_extend(immediate)
+
+uint8_t dst, src;
 bool success = false;
 const uint32_t imm16 = insn.getOperand(2).getImm();
-uint32_t imm = SignedBits(imm16, 15, 0);
-uint64_t result;
-uint32_t src, dst;
+int64_t imm = SignedBits(imm16, 15, 0);
 
 dst = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
 src = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
 
-/* Check if this is addiu sp,,imm16 */
-if (dst == dwarf_sp_mips)
+// If immediate value is greater then 2^16 - 1 then clang generate
+// LUI, ADDIU, SUBU instructions in prolog.
+// Example
+// lui$1, 0x2
+// addiu $1, $1, -0x5920
+// subu  $sp, $sp, $1
+// In this case, ADDIU dst and src will be same and not equal to sp
+if (dst == src)
 {
+Context context;
+
 /* read  register */
-uint64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, 
dwarf_zero_mips + src, 0, );
+const int64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, 
dwarf_zero_mips + src, 0, );
 if (!success)
 return false;
 
-result = src_opd_val + imm;
+/* Check if this is daddiu sp, sp, imm16 */
+if (dst == dwarf_sp_mips)
+{
+uint64_t result = src_opd_val + imm;
+RegisterInfo reg_info_sp;
 
-Context context;
-RegisterInfo reg_info_sp;
-if (GetRegisterInfo (eRegisterKindDWARF, dwarf_sp_mips, reg_info_sp))
-context.SetRegisterPlusOffset (reg_info_sp, imm);
+if (GetRegisterInfo (eRegisterKindDWARF, dwarf_sp_mips, 
reg_info_sp))
+context.SetRegisterPlusOffset (reg_info_sp, imm);
 
-/* We are allocating bytes on stack */
-context.type = eContextAdjustStackPointer;
+/* We are allocating bytes on stack */
+context.type = eContextAdjustStackPointer;
 
-WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_sp_mips, 
result);
+WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_sp_mips, 
result);
+return true;
+}
+
+imm += src_opd_val;
+context.SetImmediateSigned (imm);
+context.type = eContextImmediate;
+
+if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, 
dwarf_zero_mips + dst, imm))
+return false;

Re: [Lldb-commits] [PATCH] D20357: [LLDB][MIPS] Fix FPU Size Based on Dynamic FR

2016-08-01 Thread Nitesh Jain via lldb-commits

nitesh.jain added a comment.

Thanks Greg for all your help.


Repository:
  rL LLVM

https://reviews.llvm.org/D20357



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D20357: [LLDB][MIPS] Fix FPU Size Based on Dynamic FR

2016-07-28 Thread Nitesh Jain via lldb-commits

nitesh.jain marked 9 inline comments as done.
nitesh.jain added a comment.

https://reviews.llvm.org/D20357



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [PATCH] D22851: [LLDB][MIPS] Add (D)SUBU, (D)ADDU, LUI instructions emulation . Fix emulation for (D)ADDIU, SD/SW and LW/LD instructions

2016-07-27 Thread Nitesh Jain via lldb-commits

nitesh.jain created this revision.
nitesh.jain added reviewers: jaydeep, bhushan, clayborg.
nitesh.jain added subscribers: slthakur, mohit.bhakkad, lldb-commits, sdardis.
Herald added a subscriber: dsanders.

To handle the immediate size greater than 2^16 - 1 , the clang compiler 
generate LUI, (D)ADDIU, (D)SUBU sequence of instructions.

https://reviews.llvm.org/D22851

Files:
  source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
  source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h
  source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
  source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h

Index: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
===
--- source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
+++ source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
@@ -121,6 +121,12 @@
 Emulate_DADDiu (llvm::MCInst& insn);
 
 bool
+Emulate_DSUBU_DADDU (llvm::MCInst& insn);
+
+bool
+Emulate_LUI (llvm::MCInst& insn);
+
+bool
 Emulate_SD (llvm::MCInst& insn);
 
 bool
Index: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
===
--- source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
+++ source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
@@ -482,10 +482,15 @@
 //--
 // Prologue/Epilogue instructions
 //--
-{ "DADDiu", ::Emulate_DADDiu,  "DADDIU rt,rs,immediate"},
-{ "ADDiu",  ::Emulate_DADDiu,  "ADDIU rt,rs,immediate" },
-{ "SD", ::Emulate_SD,  "SD rt,offset(rs)"  },
-{ "LD", ::Emulate_LD,  "LD rt,offset(base)"},
+{ "DADDiu", ::Emulate_DADDiu,  "DADDIU rt, rs, immediate"},
+{ "ADDiu",  ::Emulate_DADDiu,  "ADDIU  rt, rs, immediate"},
+{ "SD", ::Emulate_SD,  "SD rt, offset(rs)"   },
+{ "LD", ::Emulate_LD,  "LD rt, offset(base)" },
+{ "DSUBU",  ::Emulate_DSUBU_DADDU, "DSUBU  rd, rs, rt"   },
+{ "SUBU",   ::Emulate_DSUBU_DADDU, "SUBU   rd, rs, rt"   },
+{ "DADDU",  ::Emulate_DSUBU_DADDU, "DADDU  rd, rs, rt"   },
+{ "ADDU",   ::Emulate_DSUBU_DADDU, "ADDU   rd, rs, rt"   },
+{ "LUI",::Emulate_LUI, "LUIrt, immediate"},
 
 
 
@@ -771,36 +776,57 @@
 bool
 EmulateInstructionMIPS64::Emulate_DADDiu (llvm::MCInst& insn)
 {
+// DADDIU rt, rs, immediate
+// GPR[rt] <- GPR[rs] + sign_extend(immediate)
+
+uint8_t dst, src;
 bool success = false;
 const uint32_t imm16 = insn.getOperand(2).getImm();
-uint64_t imm = SignedBits(imm16, 15, 0);
-uint64_t result;
-uint32_t src, dst;
+int64_t imm = SignedBits(imm16, 15, 0);
 
 dst = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
 src = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
 
-/* Check if this is daddiu sp,,imm16 */
-if (dst == dwarf_sp_mips64)
+// If immediate is greater than 2^16 - 1 then clang generate
+// LUI, (D)ADDIU,(D)SUBU instructions in prolog.
+// Example
+// lui$1, 0x2
+// daddiu $1, $1, -0x5920
+// dsubu  $sp, $sp, $1
+// In this case, (D)ADDIU dst and src will be same and not equal to sp
+if (dst == src)
 {
+Context context;
+
 /* read  register */
-uint64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + src, 0, );
+const int64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + src, 0, );
 if (!success)
 return false;
 
-result = src_opd_val + imm;
+/* Check if this is daddiu sp, sp, imm16 */
+if (dst == dwarf_sp_mips64)
+{
+uint64_t result = src_opd_val + imm;
+RegisterInfo reg_info_sp;
 
-Context context;
-RegisterInfo reg_info_sp;
-if (GetRegisterInfo (eRegisterKindDWARF, dwarf_sp_mips64, reg_info_sp))
-context.SetRegisterPlusOffset (reg_info_sp, imm);
+if (GetRegisterInfo (eRegisterKindDWARF, dwarf_sp_mips64, reg_info_sp))
+context.SetRegisterPlusOffset (reg_info_sp, imm);
 
-/* We are allocating bytes on stack */
-context.type = eContextAdjustStackPointer;
+/* We are allocating bytes on stack */
+context.type = eContextAdjustStackPointer;
 
-WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_sp_mips64, result);
+WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_sp_mips64, result);
+return true;
+}
+
+

Re: [Lldb-commits] [PATCH] D20357: [LLDB][MIPS] Fix FPU Size Based on Dynamic FR

2016-07-20 Thread Nitesh Jain via lldb-commits

nitesh.jain marked 8 inline comments as done.
nitesh.jain added a comment.

https://reviews.llvm.org/D20357



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D20357: [LLDB][MIPS] Fix FPU Size Based on Dynamic FR

2016-07-20 Thread Nitesh Jain via lldb-commits

nitesh.jain updated this revision to Diff 64693.
nitesh.jain added a comment.

Removed dynamic_size_dwarf_len field from RegisterInfo struct.


https://reviews.llvm.org/D20357

Files:
  include/lldb/Host/common/NativeRegisterContext.h
  include/lldb/Host/common/NativeRegisterContextRegisterInfo.h
  include/lldb/Target/RegisterContext.h
  include/lldb/lldb-private-types.h
  source/Host/common/NativeRegisterContext.cpp
  source/Host/common/NativeRegisterContextRegisterInfo.cpp
  source/Plugins/Process/Utility/DynamicRegisterInfo.cpp
  source/Plugins/Process/Utility/DynamicRegisterInfo.h
  source/Plugins/Process/Utility/RegisterContextLinux_mips.cpp
  source/Plugins/Process/Utility/RegisterContextLinux_mips.h
  source/Plugins/Process/Utility/RegisterContextLinux_mips64.cpp
  source/Plugins/Process/Utility/RegisterContextLinux_mips64.h
  source/Plugins/Process/Utility/RegisterInfoInterface.h
  source/Plugins/Process/Utility/RegisterInfos_mips.h
  source/Plugins/Process/Utility/RegisterInfos_mips64.h
  source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
  source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
  source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
  source/Target/RegisterContext.cpp

Index: source/Target/RegisterContext.cpp
===
--- source/Target/RegisterContext.cpp
+++ source/Target/RegisterContext.cpp
@@ -21,7 +21,9 @@
 #include "lldb/Target/Process.h"
 #include "lldb/Target/Thread.h"
 #include "lldb/Target/Target.h"
-
+#include "lldb/Core/Module.h"
+#include "lldb/Expression/DWARFExpression.h"
+#include "lldb/Core/Value.h"
 using namespace lldb;
 using namespace lldb_private;
 
@@ -76,6 +78,46 @@
 return nullptr;
 }
 
+uint32_t
+RegisterContext::UpdateDynamicRegisterSize (const lldb_private::ArchSpec ,
+RegisterInfo* reg_info,
+size_t opcode_len)
+{
+ExecutionContext exe_ctx (CalculateThread());
+
+// In MIPS, the floating point registers size is depends on FR bit of SR register.
+// if SR.FR  == 1 then all floating point registers are 64 bits.
+// else they are all 32 bits.
+
+int expr_result;
+uint32_t addr_size =  arch.GetAddressByteSize ();
+const uint8_t* opcode_ptr = reg_info->dynamic_size_dwarf_expr_bytes;
+
+DataExtractor dwarf_data (opcode_ptr, opcode_len, 
+  arch.GetByteOrder (), addr_size);
+ModuleSP opcode_ctx;
+DWARFExpression dwarf_expr (opcode_ctx, dwarf_data, nullptr, 0, opcode_len);
+Value result;
+Error error;
+const lldb::offset_t offset = 0;
+if(dwarf_expr.Evaluate (_ctx, nullptr, nullptr, this, opcode_ctx, dwarf_data, nullptr,
+offset, opcode_len, eRegisterKindDWARF, nullptr, nullptr, result, ))
+{
+expr_result = result.GetScalar().SInt(-1);
+switch (expr_result)
+{
+case 0: return 4;
+case 1: return 8;
+default: return reg_info->byte_size;
+}
+}
+else
+{
+printf("Error executing DwarfExpression::Evaluate %s\n", error.AsCString());
+return reg_info->byte_size;
+}
+}
+
 const RegisterInfo *
 RegisterContext::GetRegisterInfo (lldb::RegisterKind kind, uint32_t num)
 {
Index: source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
===
--- source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
+++ source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
@@ -539,6 +539,8 @@
 ConstString set_name;
 std::vector value_regs;
 std::vector invalidate_regs;
+uint8_t *dwarf_opcode_bytes = NULL;
+uint32_t dwarf_expr_bytes_len;
 RegisterInfo reg_info = { NULL, // Name
 NULL, // Alt name
 0,// byte size
@@ -553,6 +555,7 @@
 reg_num   // native register number
 },
 NULL,
+NULL,
 NULL
 };
 
@@ -638,6 +641,25 @@
 {
 SplitCommaSeparatedRegisterNumberString(value, invalidate_regs, 16);
 }
+else if (name.compare("dynamic_size_dwarf_expr_bytes") == 0)
+{
+   dwarf_expr_bytes_len = value.length () / 2;
+   assert(dwarf_expr_bytes_len > 0);
+   dwarf_opcode_bytes = new uint8_t[dwarf_expr_bytes_len];
+   StringExtractor name_extractor;
+   
+   if (dwarf_opcode_bytes)
+   {
+   // Swap "value" over into "name_extractor"
+

[Lldb-commits] [lldb] r275785 - [LLVM][MIPS] Revert support for FRE.

2016-07-18 Thread Nitesh Jain via lldb-commits

Author: nitesh.jain
Date: Mon Jul 18 07:37:44 2016
New Revision: 275785

URL: http://llvm.org/viewvc/llvm-project?rev=275785=rev
Log:
[LLVM][MIPS] Revert support for FRE.

Reviewers: jaydeep

Subscribers: bhushan, mohit.bhakkad, slthakur, llvm-commits

Modified:

lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp

Modified: 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp?rev=275785=275784=275785=diff
==
--- 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp 
(original)
+++ 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp 
Mon Jul 18 07:37:44 2016
@@ -824,7 +824,8 @@ NativeRegisterContextLinux_mips64::ReadC
 error = NativeRegisterContextLinux::ReadFPR();
 }
 
-if (IsFR0() || IsFRE())
+// TODO: Add support for FRE
+if (IsFR0())
 {
  src = (uint8_t *)_fpr + 4 + (IsBigEndian * 4);
  dst = (uint8_t *)_fpr + 8 + (IsBigEndian * 4);
@@ -851,7 +852,8 @@ NativeRegisterContextLinux_mips64::Write
 
 uint32_t IsBigEndian = (byte_order == lldb::eByteOrderBig);
 
-if (IsFR0() || IsFRE())
+// TODO: Add support for FRE
+if (IsFR0())
 {
 src = (uint8_t *)_fpr + 8 + (IsBigEndian * 4);
 dst = (uint8_t *)_fpr + 4 + (IsBigEndian * 4);


___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D22322: [LLDB] Fixes for standalone build

2016-07-14 Thread Nitesh Jain via lldb-commits

nitesh.jain accepted this revision.
nitesh.jain added a comment.

LGTM. Thanks


Repository:
  rL LLVM

http://reviews.llvm.org/D22322



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D20357: [LLDB][MIPS] Fix FPU Size Based on Dynamic FR

2016-07-11 Thread Nitesh Jain via lldb-commits

nitesh.jain added a comment.

Hi Greg,

Please could you find some time to review this ?

Thanks


http://reviews.llvm.org/D20357



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D20357: [LLDB][MIPS] Fix FPU Size Based on Dynamic FR

2016-07-08 Thread Nitesh Jain via lldb-commits

nitesh.jain marked an inline comment as done.
nitesh.jain added a comment.

http://reviews.llvm.org/D20357



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D20357: [LLDB][MIPS] Fix FPU Size Based on Dynamic FR

2016-07-08 Thread Nitesh Jain via lldb-commits

nitesh.jain removed rL LLVM as the repository for this revision.
nitesh.jain updated this revision to Diff 63224.
nitesh.jain added a comment.

Added  lldb_private::RegisterInfo * DynamicRegisterInfo::GetRegisterInfoAtIndex 
(uint32_t i)


http://reviews.llvm.org/D20357

Files:
  include/lldb/lldb-private-types.h
  source/Plugins/Process/Utility/DynamicRegisterInfo.cpp
  source/Plugins/Process/Utility/DynamicRegisterInfo.h
  source/Plugins/Process/Utility/RegisterInfos_mips.h
  source/Plugins/Process/Utility/RegisterInfos_mips64.h
  source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
  source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
  source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h
  source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp

Index: source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
===
--- source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
+++ source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
@@ -539,6 +539,7 @@
 ConstString set_name;
 std::vector value_regs;
 std::vector invalidate_regs;
+uint8_t dwarf_opcode[8];
 RegisterInfo reg_info = { NULL, // Name
 NULL, // Alt name
 0,// byte size
@@ -553,7 +554,9 @@
 reg_num   // native register number
 },
 NULL,
-NULL
+NULL,
+NULL,
+0// dynamic_size default value
 };
 
 while (response.GetNameColonValue(name, value))
@@ -638,6 +641,22 @@
 {
 SplitCommaSeparatedRegisterNumberString(value, invalidate_regs, 16);
 }
+else if (name.compare("dynamic_size_dwarf_len") == 0)
+{
+reg_info.dynamic_size_dwarf_len = StringConvert::ToUInt32(value.c_str(), 0, 0);
+}
+else if (name.compare("dynamic_size_dwarf_expr_bytes") == 0)
+{
+   uint32_t dwarf_len = reg_info.dynamic_size_dwarf_len;
+   assert(dwarf_len > 0);
+   StringExtractor name_extractor;
+
+   // Swap "value" over into "name_extractor"
+   name_extractor.GetStringRef().swap(value);
+   uint32_t ret_val = name_extractor.GetHexBytesAvail (dwarf_opcode, dwarf_len);
+   assert(dwarf_len == ret_val);
+   reg_info.dynamic_size_dwarf_expr_bytes = dwarf_opcode;
+}
 }
 
 reg_info.byte_offset = reg_offset;
@@ -4373,6 +4392,7 @@
 ConstString set_name;
 std::vector value_regs;
 std::vector invalidate_regs;
+uint8_t dwarf_opcode[8];
 bool encoding_set = false;
 bool format_set = false;
 RegisterInfo reg_info = { NULL, // Name
@@ -4389,10 +4409,12 @@
 cur_reg_num // native register number
 },
 NULL,
-NULL
+NULL,
+NULL,
+0
 };
 
-reg_node.ForEachAttribute([_info, _group, _type, _name, _name, _name, _regs, _regs, _set, _set, _info, _reg_num, _offset](const llvm::StringRef , const llvm::StringRef ) -> bool {
+reg_node.ForEachAttribute([_info, _group, _type, _name, _name, _name, _regs, _regs, _set, _set, _info, _reg_num, _offset, _opcode](const llvm::StringRef , const llvm::StringRef ) -> bool {
 if (name == "name")
 {
 reg_name.SetString(value);
@@ -4480,6 +4502,21 @@
 {
 SplitCommaSeparatedRegisterNumberString(value, invalidate_regs, 0);
 }
+else if (name == "dynamic_size_dwarf_len")
+{
+reg_info.dynamic_size_dwarf_len = StringConvert::ToUInt32 (value.data(), 0, 0);
+}
+else if (name == "dynamic_size_dwarf_expr_bytes")
+{
+StringExtractor name_extractor;
+uint32_t dwarf_len = reg_info.dynamic_size_dwarf_len;
+assert(dwarf_len > 0);
+std::string opcode_string = value.str();
+name_extractor.GetStringRef().swap(opcode_string);
+uint32_t ret_val = name_extractor.GetHexBytesAvail (dwarf_opcode, dwarf_len);
+assert(dwarf_len == ret_val);
+reg_info.dynamic_size_dwarf_expr_bytes = dwarf_opcode;
+}
 else
 {
 printf("unhandled attribute %s = %s\n", name.data(), value.data());
Index:

Re: [Lldb-commits] [PATCH] D20357: [LLDB][MIPS] Fix FPU Size Based on Dynamic FR

2016-07-08 Thread Nitesh Jain via lldb-commits

nitesh.jain added inline comments.


Comment at: source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp:98
@@ +97,3 @@
+const ArchSpec  = 
m_thread.GetProcess()->GetTarget().GetArchitecture();
+RegisterInfo* reg_info = const_cast(m_reg_info.GetRegisterInfoAtIndex (reg));
+if(reg_info->dynamic_size_dwarf_len)

labath wrote:
> Can we get rid of these const_casts? It looks like UpdateDynamicRegisterSize 
> does not actually need this to be non-const.
No, it require so that we can modify the reg_info->byte_size member.


Repository:
  rL LLVM

http://reviews.llvm.org/D20357



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D20357: [LLDB][MIPS] Fix FPU Size Based on Dynamic FR

2016-07-08 Thread Nitesh Jain via lldb-commits

nitesh.jain marked an inline comment as done.
nitesh.jain added a comment.

Repository:
  rL LLVM

http://reviews.llvm.org/D20357



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D20357: [LLDB][MIPS] Fix FPU Size Based on Dynamic FR

2016-07-08 Thread Nitesh Jain via lldb-commits

nitesh.jain marked 6 inline comments as done.
nitesh.jain added a comment.

Repository:
  rL LLVM

http://reviews.llvm.org/D20357



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D20357: [LLDB][MIPS] Fix FPU Size Based on Dynamic FR

2016-07-08 Thread Nitesh Jain via lldb-commits

nitesh.jain retitled this revision from "[LLDB][MIPS] Fix FPU Size Based on 
Dynamic FR/FRE bit" to "[LLDB][MIPS] Fix FPU Size Based on Dynamic FR".
nitesh.jain updated the summary for this revision.
nitesh.jain updated this revision to Diff 63201.
nitesh.jain added a comment.

Update diff as per suggestion. In case of FRE mode, FPU registers are all 64 
bit.


Repository:
  rL LLVM

http://reviews.llvm.org/D20357

Files:
  include/lldb/lldb-private-types.h
  source/Plugins/Process/Utility/DynamicRegisterInfo.cpp
  source/Plugins/Process/Utility/DynamicRegisterInfo.h
  source/Plugins/Process/Utility/RegisterInfos_mips.h
  source/Plugins/Process/Utility/RegisterInfos_mips64.h
  source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
  source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
  source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h
  source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp

Index: source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
===
--- source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
+++ source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
@@ -539,6 +539,7 @@
 ConstString set_name;
 std::vector value_regs;
 std::vector invalidate_regs;
+uint8_t dwarf_opcode[8];
 RegisterInfo reg_info = { NULL, // Name
 NULL, // Alt name
 0,// byte size
@@ -553,7 +554,9 @@
 reg_num   // native register number
 },
 NULL,
-NULL
+NULL,
+NULL,
+0// dynamic_size default value
 };
 
 while (response.GetNameColonValue(name, value))
@@ -638,6 +641,22 @@
 {
 SplitCommaSeparatedRegisterNumberString(value, invalidate_regs, 16);
 }
+else if (name.compare("dynamic_size_dwarf_len") == 0)
+{
+reg_info.dynamic_size_dwarf_len = StringConvert::ToUInt32(value.c_str(), 0, 0);
+}
+else if (name.compare("dynamic_size_dwarf_expr_bytes") == 0)
+{
+   uint32_t dwarf_len = reg_info.dynamic_size_dwarf_len;
+   assert(dwarf_len > 0);
+   StringExtractor name_extractor;
+
+   // Swap "value" over into "name_extractor"
+   name_extractor.GetStringRef().swap(value);
+   uint32_t ret_val = name_extractor.GetHexBytesAvail (dwarf_opcode, dwarf_len);
+   assert(dwarf_len == ret_val);
+   reg_info.dynamic_size_dwarf_expr_bytes = dwarf_opcode;
+}
 }
 
 reg_info.byte_offset = reg_offset;
@@ -4373,6 +4392,7 @@
 ConstString set_name;
 std::vector value_regs;
 std::vector invalidate_regs;
+uint8_t dwarf_opcode[8];
 bool encoding_set = false;
 bool format_set = false;
 RegisterInfo reg_info = { NULL, // Name
@@ -4389,10 +4409,12 @@
 cur_reg_num // native register number
 },
 NULL,
-NULL
+NULL,
+NULL,
+0
 };
 
-reg_node.ForEachAttribute([_info, _group, _type, _name, _name, _name, _regs, _regs, _set, _set, _info, _reg_num, _offset](const llvm::StringRef , const llvm::StringRef ) -> bool {
+reg_node.ForEachAttribute([_info, _group, _type, _name, _name, _name, _regs, _regs, _set, _set, _info, _reg_num, _offset, _opcode](const llvm::StringRef , const llvm::StringRef ) -> bool {
 if (name == "name")
 {
 reg_name.SetString(value);
@@ -4480,6 +4502,21 @@
 {
 SplitCommaSeparatedRegisterNumberString(value, invalidate_regs, 0);
 }
+else if (name == "dynamic_size_dwarf_len")
+{
+reg_info.dynamic_size_dwarf_len = StringConvert::ToUInt32 (value.data(), 0, 0);
+}
+else if (name == "dynamic_size_dwarf_expr_bytes")
+{
+StringExtractor name_extractor;
+uint32_t dwarf_len = reg_info.dynamic_size_dwarf_len;
+assert(dwarf_len > 0);
+std::string opcode_string = value.str();
+name_extractor.GetStringRef().swap(opcode_string);
+uint32_t ret_val = name_extractor.GetHexBytesAvail (dwarf_opcode, dwarf_len);
+assert(dwarf_len == ret_val);
+reg_info.dynamic_size_dwarf_expr_bytes = dwarf_opcode;
+}

Re: [Lldb-commits] [PATCH] D20464: [LLDB][MIPS] Check if libatomic needs to be specified explicitly.

2016-07-07 Thread Nitesh Jain via lldb-commits

nitesh.jain added a comment.

In http://reviews.llvm.org/D20464#473884, @Eugene.Zelenko wrote:

> As fas as I could judge from log, you built LLDB with LLVM/Clang. But problem 
> happens when it's necessary to build LLDB separately from LLVM/Clang 
> (standalone build).

Then we need to introduce a 64 bit atomic check in 
cmake/modules/LLDBStandalone.cmake. what do you thing?

Thanks

Repository:
  rL LLVM

http://reviews.llvm.org/D20464

___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D20464: [LLDB][MIPS] Check if libatomic needs to be specified explicitly.

2016-07-04 Thread Nitesh Jain via lldb-commits

nitesh.jain added a comment.

In http://reviews.llvm.org/D20464#472733, @Eugene.Zelenko wrote:

> I run CMake with --trace and is mentioned only in condition added there.


I have attach log of CMake with --trace. 
F2135359: log 


Repository:
  rL LLVM

http://reviews.llvm.org/D20464



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D20357: [LLDB][MIPS] Fix FPU Size Based on Dynamic FR/FRE bit

2016-07-01 Thread Nitesh Jain via lldb-commits

nitesh.jain added inline comments.


Comment at: 
source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp:497-505
@@ +496,11 @@
+ {
+bool fre;
+bool fr1;
+IsFR1_FRE (fr1, fre);
+
+// fr1  fre fpu_reg_size
+// 10   64
+// 11   32
+// 00   32
+reg_info->byte_size = (fr1 ^ fre) ? 8 : 4;
+ }

clayborg wrote:
> If we don't add anything to RegisterInfo, then this code is fine. Else we 
> will need to check "reg_info->dynamic_size_dwarf_expr_bytes" and evaluate the 
> DWARF expression to get the size.
If Dwarf expression need to be evaluate at server side, then we need to add one 
more function in DWARFExpression::Evaluate to take NativeRegisterContext has a 
parameter. So should I add one more functionality in it ?

Thanks


Repository:
  rL LLVM

http://reviews.llvm.org/D20357



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D20464: [LLDB][MIPS] Check if libatomic needs to be specified explicitly.

2016-07-01 Thread Nitesh Jain via lldb-commits

nitesh.jain added a comment.

In http://reviews.llvm.org/D20464#471803, @Eugene.Zelenko wrote:

> I see HAVE_CXX_ATOMICS64_WITHOUT_LIB messages during LLVM Cmake run, but I 
> don't see such message during LLDB CMake run.
>
> Is this value is supposed to be read form LLVM CMake cache?


Yes.


Repository:
  rL LLVM

http://reviews.llvm.org/D20464



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D20464: [LLDB][MIPS] Check if libatomic needs to be specified explicitly.

2016-06-27 Thread Nitesh Jain via lldb-commits

nitesh.jain updated this revision to Diff 61940.
nitesh.jain added a comment.

Thanks Labath.
Updated diff as per suggestion.


Repository:
  rL LLVM

http://reviews.llvm.org/D20464

Files:
  cmake/LLDBDependencies.cmake

Index: cmake/LLDBDependencies.cmake
===
--- cmake/LLDBDependencies.cmake
+++ cmake/LLDBDependencies.cmake
@@ -157,6 +157,11 @@
 endif()
   endif()
 endif()
+
+if (NOT HAVE_CXX_ATOMICS64_WITHOUT_LIB )
+list(APPEND LLDB_SYSTEM_LIBS atomic)
+endif()
+
 # On FreeBSD/NetBSD backtrace() is provided by libexecinfo, not libc.
 if (CMAKE_SYSTEM_NAME MATCHES "FreeBSD" OR CMAKE_SYSTEM_NAME MATCHES "NetBSD")
   list(APPEND LLDB_SYSTEM_LIBS execinfo)


Index: cmake/LLDBDependencies.cmake
===
--- cmake/LLDBDependencies.cmake
+++ cmake/LLDBDependencies.cmake
@@ -157,6 +157,11 @@
 endif()
   endif()
 endif()
+
+if (NOT HAVE_CXX_ATOMICS64_WITHOUT_LIB )
+list(APPEND LLDB_SYSTEM_LIBS atomic)
+endif()
+
 # On FreeBSD/NetBSD backtrace() is provided by libexecinfo, not libc.
 if (CMAKE_SYSTEM_NAME MATCHES "FreeBSD" OR CMAKE_SYSTEM_NAME MATCHES "NetBSD")
   list(APPEND LLDB_SYSTEM_LIBS execinfo)
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D21064: [LLDB][MIPS] Fix Emulation of Compact branch and ADDIU instructions

2016-06-23 Thread Nitesh Jain via lldb-commits

nitesh.jain added a comment.

In http://reviews.llvm.org/D21064#465410, @sdardis wrote:

> You also need to emulate dsubu and subu as the MIPS LLVM backend will 
> generate them in certain cases.


Thanks will emulate them too.


Repository:
  rL LLVM

http://reviews.llvm.org/D21064



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D20368: Remove Platform usages from NativeProcessLinux

2016-06-13 Thread Nitesh Jain via lldb-commits

nitesh.jain added inline comments.


Comment at: 
source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp:438
@@ +437,3 @@
+// The auxiliary vector consists of a sequence of key-value pairs, where 
key and value are of
+// the pointer size for the architecture that the process is running on. 
We can use this to
+// detect the process architecture. We will try reading the vector as if 
it were a 64-bit

labath wrote:
> nitesh.jain wrote:
> > There are three flavours of ABI,
> > 
> > |  ABI | pointer-size  | Arch | Processs Type 
> > | O32 |4 |   Mips32  |   32 bit 
> > | N32|4   | Mips64   |  32 bit 
> > | N64|8   | Mips64   | 64 bit 
> > 
> > So not sure whether it will work for "N32", I will check and let you know 
> > asap.
> Uh-oh. :)
> 
> So, I don't think the ABI should matter much to the native register context. 
> What matters here is the registers and their sizes. I'm guessing the N32 
> thing is something like the x32 intel abi, wher all registers are 64-bit, but 
> sizeof(void*) is 32-bit. In that case this function will not work correctly, 
> as it will detect it as 32-bit (but the NT_PRSTATUS-based one would, I guess).
> 
> Does N32 work on pre-3.13 kernels? (Grepping the source seems to find 
> mentions of it, but i don't know how well it actually worked).
> 
> I guess is back to drawing board with this one again. Could you please send 
> me the contents of the N32 auxiliary vector (LD_SHOW_AUXV as well as the 
> actual binary contents). I presume the one you sent me earlier was O32.
> 
> cheers,
> pl
In N32 ABI, all GPR register are 64 bit and sizeof(void *) is 32 bit. 

Yes, N32 ABI works on pre-3.13 kernels. I have send earlier aux for O32 ABI .

Thanks,
Nj


http://reviews.llvm.org/D20368



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D20368: Remove Platform usages from NativeProcessLinux

2016-06-10 Thread Nitesh Jain via lldb-commits

nitesh.jain added inline comments.


Comment at: 
source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp:438
@@ +437,3 @@
+// The auxiliary vector consists of a sequence of key-value pairs, where 
key and value are of
+// the pointer size for the architecture that the process is running on. 
We can use this to
+// detect the process architecture. We will try reading the vector as if 
it were a 64-bit

There are three flavours of ABI,

|  ABI | pointer-size  | Arch | Processs Type 
| O32 |4 |   Mips32  |   32 bit 
| N32|4   | Mips64   |  32 bit 
| N64|8   | Mips64   | 64 bit 

So not sure whether it will work for "N32", I will check and let you know asap.


http://reviews.llvm.org/D20368



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D20368: Remove Platform usages from NativeProcessLinux

2016-06-10 Thread Nitesh Jain via lldb-commits

nitesh.jain added a comment.

I will check it and let you know asap.

Thanks


http://reviews.llvm.org/D20368



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D20368: Remove Platform usages from NativeProcessLinux

2016-05-24 Thread Nitesh Jain via lldb-commits

nitesh.jain added a comment.

In case of MIPS, ptrace always return 64 bit data irrespetive of Arch.


http://reviews.llvm.org/D20368



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D20368: Remove Platform usages from NativeProcessLinux

2016-05-24 Thread Nitesh Jain via lldb-commits

nitesh.jain added inline comments.


Comment at: source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp:53
@@ -22,2 +52,3 @@
+
 NativeRegisterContextLinux::NativeRegisterContextLinux(NativeThreadProtocol 
_thread,
uint32_t 
concrete_frame_idx,

labath wrote:
> jaydeep wrote:
> > We have tried executing ptrace(NT_PRSTATUS) on MIPS with 3.18. It is able 
> > to detect the arch correctly (64->64 and 64->32). However with 3.10 it 
> > fails with EIO. Is there any fallback method when ptrace(NT_PRSTATUS) fails?
> Thanks for checking that out.
> 
> This makes things a bit tricky. We *could* fallback to the "parse the 
> executable ELF" method of getting the architecture, but that would make this 
> patch a bit pointless, as that is what I am trying to remove in the first 
> place. I suppose we could make the fallback mips-only, but that will not be 
> too ideal either.
> 
> I don't know about any other fallbacks. It would be interesting to know how 
> strace does that. I've tried looking at strace source code, but I could not 
> make much out of it. Do you know if a single strace binary is capable of 
> correctly tracing both 32- and 64-bit processes? If so, could you try running 
> the following experiment for me:
> - create a simple c file that does a sleep(1) and exits
> - compile 32- and 64-bit versions of the executable
> - execute the following commands:
> ```
> strace -o /tmp/32.txt -- strace -o /dev/null -- a.out.32
> strace -o /tmp/64.txt -- strace -o /dev/null -- a.out.64
> ```
> 
> Could you send me the outputs (32.txt, 64.txt). Maybe I'll be able to figure 
> something out from that.
> 
> If that does not work, I may have to abandon this.
> 
> thanks.
// 32 bit ELF
gcc-4.9 -g -O0 -mabi=64 -mips64r2 simple.c -o a.out.64

// 64 bit ELF
gcc-4.9 -g -O0 -mabi=32 -mips32r2 simple.c -o a.out.32

// Strace for 32 and 64 bit
strace -o /tmp/64.txt -- strace -o /dev/null -- ./a.out.64
strace -o /tmp/32.txt -- strace -o /dev/null -- ./a.out.32


// File command output for both file

a.out.64: ELF 64-bit LSB executable, MIPS, MIPS64 rel2 version 1 (SYSV), 
dynamically linked, interpreter /lib64/ld.so.1, 
BuildID[sha1]=6e0f92a8abee292b4b6462d79ec0420a3d8aaad0, for GNU/Linux 2.6.32, 
not stripped

a.out.32: ELF 32-bit LSB executable, MIPS, MIPS32 rel2 version 1, dynamically 
linked, interpreter /lib/ld.so.1, for GNU/Linux 2.6.32, 
BuildID[sha1]=c4e09148526975f777e3e70bec85868616d3ce94, not stripped


{F1978053}

{F1978054}


http://reviews.llvm.org/D20368



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D20416: [LLDB][MIPS] Fix floating point handling in case of thread step-out

2016-05-20 Thread Nitesh Jain via lldb-commits

nitesh.jain added a comment.

committed in revision 270207


Repository:
  rL LLVM

http://reviews.llvm.org/D20416



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D20368: Remove Platform usages from NativeProcessLinux

2016-05-20 Thread Nitesh Jain via lldb-commits

nitesh.jain added inline comments.


Comment at: source/Plugins/Process/Linux/NativeRegisterContextLinux.cpp:39
@@ +38,3 @@
+int regset = NT_PRSTATUS;
+Error error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, tid, 
, , sizeof_native_regs_struct);
+HostInfo::ArchitectureKind kind = HostInfo::eArchKindDefault; // same 
bitness this process

Ptrace call with ptrace request "PTRACE_GETREGSET"  is failing for MIPS. We are 
currently investigating the reason for the failure. I will let you know asap.

Thanks


http://reviews.llvm.org/D20368



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D18638: [LLDB][MIPS] Provide ABI string to compiler for appropriate code generation for MIPS

2016-05-13 Thread Nitesh Jain via lldb-commits

nitesh.jain closed this revision.
nitesh.jain added a comment.

Committed in revision 269407


Repository:
  rL LLVM

http://reviews.llvm.org/D18638



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

Re: [Lldb-commits] [PATCH] D18858: [LLDB][MIPS] Setting appropriate ArchSpec::m_flags based on ABI

2016-05-11 Thread Nitesh Jain via lldb-commits

nitesh.jain updated this revision to Diff 56891.
nitesh.jain added a comment.

Added IsMIPS() method.


Repository:
  rL LLVM

http://reviews.llvm.org/D18858

Files:
  include/lldb/Core/ArchSpec.h
  source/Core/ArchSpec.cpp
  source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp

Index: source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
===
--- source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
+++ source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
@@ -1697,8 +1697,7 @@
 
 I->section_name = name;
 
-if (arch_spec.GetMachine() == llvm::Triple::mips || 
arch_spec.GetMachine() == llvm::Triple::mipsel
-|| arch_spec.GetMachine() == llvm::Triple::mips64 || 
arch_spec.GetMachine() == llvm::Triple::mips64el)
+if (arch_spec.IsMIPS())
 {
 uint32_t arch_flags = arch_spec.GetFlags ();
 DataExtractor data;
@@ -1712,13 +1711,27 @@
 }
 }
 // Settings appropriate ArchSpec ABI Flags
-if (header.e_flags & llvm::ELF::EF_MIPS_ABI2)
+switch(header.e_flags & llvm::ELF::EF_MIPS_ABI)
 {
-arch_flags |= lldb_private::ArchSpec::eMIPSABI_N32;
-}
-else if (header.e_flags & llvm::ELF::EF_MIPS_ABI_O32)
-{
- arch_flags |= lldb_private::ArchSpec::eMIPSABI_O32;
+case llvm::ELF::EF_MIPS_ABI_O32:
+arch_flags |= lldb_private::ArchSpec::eMIPSABI_O32;
+break;
+case EF_MIPS_ABI_O64:
+arch_flags |= lldb_private::ArchSpec::eMIPSABI_O64;
+break;
+case EF_MIPS_ABI_EABI32:
+arch_flags |= 
lldb_private::ArchSpec::eMIPSABI_EABI32;
+break;
+case EF_MIPS_ABI_EABI64:
+arch_flags |= 
lldb_private::ArchSpec::eMIPSABI_EABI64;
+break;
+default:
+// ABI Mask doesn't cover N32 and N64 ABI.
+if (header.e_ident[EI_CLASS] == 
llvm::ELF::ELFCLASS64)
+arch_flags |= 
lldb_private::ArchSpec::eMIPSABI_N64;
+else if (header.e_flags && llvm::ELF::EF_MIPS_ABI2)
+arch_flags |= 
lldb_private::ArchSpec::eMIPSABI_N32;
+break;
 }
 arch_spec.SetFlags (arch_flags);
 }
Index: source/Core/ArchSpec.cpp
===
--- source/Core/ArchSpec.cpp
+++ source/Core/ArchSpec.cpp
@@ -507,6 +507,18 @@
 return "unknown";
 }
 
+bool 
+ArchSpec::IsMIPS() const
+{
+const llvm::Triple::ArchType machine = GetMachine();
+if(machine == llvm::Triple::mips ||
+   machine == llvm::Triple::mipsel ||
+   machine == llvm::Triple::mips64 ||
+   machine == llvm::Triple::mips64el)
+   return true;
+return false;
+}
+
 std::string
 ArchSpec::GetClangTargetCPU ()
 {
Index: include/lldb/Core/ArchSpec.h
===
--- include/lldb/Core/ArchSpec.h
+++ include/lldb/Core/ArchSpec.h
@@ -69,6 +69,9 @@
 eMIPSABI_O32= 0x2000,
 eMIPSABI_N32= 0x4000,
 eMIPSABI_N64= 0x8000,
+eMIPSABI_O64= 0x0002,
+eMIPSABI_EABI32 = 0x0004,
+eMIPSABI_EABI64 = 0x0008,
 eMIPSABI_mask   = 0x000ff000
 };
 
@@ -289,6 +292,14 @@
 const char *
 GetArchitectureName () const;
 
+//-
+/// if MIPS architecture return true.
+///
+///  @return a boolean value.
+//-
+bool
+IsMIPS() const;
+
 //--
 /// Returns a string representing current architecture as a target CPU
 /// for tools like compiler, disassembler etc.


Index: source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
===
--- source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
+++ source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
@@ -1697,8 +1697,7 @@
 
 I->section_name = name;
 
-if (arch_spec.GetMachine() == llvm::Triple::mips || arch_spec.GetMachine() == llvm::Triple::mipsel
-|| arch_spec.GetMachine() == llvm::Triple::mips64 || arch_spec.GetMachine() == llvm::Triple::mips64el)
+if

Re: [Lldb-commits] [PATCH] D18858: [LLDB][MIPS] Setting appropriate ArchSpec::m_flags based on ABI

2016-04-13 Thread Nitesh Jain via lldb-commits

nitesh.jain added inline comments.


Comment at: source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp:1625-1626
@@ -1624,4 +1624,4 @@
 
 if (arch_spec.GetMachine() == llvm::Triple::mips || 
arch_spec.GetMachine() == llvm::Triple::mipsel
 || arch_spec.GetMachine() == llvm::Triple::mips64 || 
arch_spec.GetMachine() == llvm::Triple::mips64el)
 {

clayborg wrote:
> Should we add a function like:
> 
> ```
> bool ArchSpec::IsMIPS() const;
> ```
> 
> Every patch I see for MIPS has these same four machine checks. If we add 
> another we will need to update all places that do this..
I agree with you. We need to add above function so it will be easy for future 
updates. I will update the diff as per suggestion


Repository:
  rL LLVM

http://reviews.llvm.org/D18858



___
lldb-commits mailing list
lldb-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [PATCH] D18858: [LLDB][MIPS] Setting appropriate ArchSpec::m_flags based on ABI

2016-04-07 Thread Nitesh Jain via lldb-commits

nitesh.jain created this revision.
nitesh.jain added reviewers: clayborg, ovyalov.
nitesh.jain added subscribers: jaydeep, bhushan, sagar, mohit.bhakkad, 
lldb-commits.
nitesh.jain set the repository for this revision to rL LLVM.

The ArchSpec::m_flags will be set based on ELF flag ABI.

Repository:
  rL LLVM

http://reviews.llvm.org/D18858

Files:
  include/lldb/Core/ArchSpec.h
  source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp

Index: source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
===
--- source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
+++ source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
@@ -1637,13 +1637,27 @@
 }
 }
 // Settings appropriate ArchSpec ABI Flags
-if (header.e_flags & llvm::ELF::EF_MIPS_ABI2)
+switch(header.e_flags & llvm::ELF::EF_MIPS_ABI)
 {
-arch_flags |= lldb_private::ArchSpec::eMIPSABI_N32;
-}
-else if (header.e_flags & llvm::ELF::EF_MIPS_ABI_O32)
-{
- arch_flags |= lldb_private::ArchSpec::eMIPSABI_O32;
+case llvm::ELF::EF_MIPS_ABI_O32:
+arch_flags |= lldb_private::ArchSpec::eMIPSABI_O32;
+break;
+case EF_MIPS_ABI_O64:
+arch_flags |= lldb_private::ArchSpec::eMIPSABI_O64;
+break;
+case EF_MIPS_ABI_EABI32:
+arch_flags |= 
lldb_private::ArchSpec::eMIPSABI_EABI32;
+break;
+case EF_MIPS_ABI_EABI64:
+arch_flags |= 
lldb_private::ArchSpec::eMIPSABI_EABI64;
+break;
+default:
+// ABI Mask doesn't cover N32 and N64 ABI.
+if (header.e_ident[EI_CLASS] == 
llvm::ELF::ELFCLASS64)
+arch_flags |= 
lldb_private::ArchSpec::eMIPSABI_N64;
+else if (header.e_flags && llvm::ELF::EF_MIPS_ABI2)
+arch_flags |= 
lldb_private::ArchSpec::eMIPSABI_N32;
+break;
 }
 arch_spec.SetFlags (arch_flags);
 }
Index: include/lldb/Core/ArchSpec.h
===
--- include/lldb/Core/ArchSpec.h
+++ include/lldb/Core/ArchSpec.h
@@ -69,6 +69,9 @@
 eMIPSABI_O32= 0x2000,
 eMIPSABI_N32= 0x4000,
 eMIPSABI_N64= 0x8000,
+eMIPSABI_O64= 0x0002,
+eMIPSABI_EABI32 = 0x0004,
+eMIPSABI_EABI64 = 0x0008,
 eMIPSABI_mask   = 0x000ff000
 };
 


Index: source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
===
--- source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
+++ source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
@@ -1637,13 +1637,27 @@
 }
 }
 // Settings appropriate ArchSpec ABI Flags
-if (header.e_flags & llvm::ELF::EF_MIPS_ABI2)
+switch(header.e_flags & llvm::ELF::EF_MIPS_ABI)
 {
-arch_flags |= lldb_private::ArchSpec::eMIPSABI_N32;
-}
-else if (header.e_flags & llvm::ELF::EF_MIPS_ABI_O32)
-{
- arch_flags |= lldb_private::ArchSpec::eMIPSABI_O32;
+case llvm::ELF::EF_MIPS_ABI_O32:
+arch_flags |= lldb_private::ArchSpec::eMIPSABI_O32;
+break;
+case EF_MIPS_ABI_O64:
+arch_flags |= lldb_private::ArchSpec::eMIPSABI_O64;
+break;
+case EF_MIPS_ABI_EABI32:
+arch_flags |= lldb_private::ArchSpec::eMIPSABI_EABI32;
+break;
+case EF_MIPS_ABI_EABI64:
+arch_flags |= lldb_private::ArchSpec::eMIPSABI_EABI64;
+break;
+default:
+// ABI Mask doesn't cover N32 and N64 ABI.
+if (header.e_ident[EI_CLASS] == llvm::ELF::ELFCLASS64)
+arch_flags |= lldb_private::ArchSpec::eMIPSABI_N64;
+else if (header.e_flags && llvm::ELF::EF_MIPS_ABI2)
+arch_flags |= lldb_private::ArchSpec::eMIPSABI_N32;
+break;

1 2 >

1 - 100 of 123 matches

Mail list logo